Openmoko Bug #1841: white screen of death (WSOD) after resume

Openmoko Public Trac bugs at
Wed Nov 26 10:30:19 CET 2008

#1841: white screen of death (WSOD) after resume
 Reporter:  Rorschach  |          Owner:  openmoko-devel
     Type:  defect     |         Status:  new           
 Priority:  highest    |      Milestone:                
Component:  unknown    |        Version:  GTA02v5       
 Severity:  critical   |       Keywords:  wsod,resume   
 Haspatch:  0          |      Blockedby:                
Estimated:             |    Patchreview:                
 Blocking:             |   Reproducible:  always        

Comment(by joerg):

 Given we see a dependency of failure to resume from suspend and
 temperature, we may assume this is no misconfiguration of any register, or
 a missing command etc, but instead most probably a voltage or timing
 From jbt6k74.c and varaha:'docs/by_function/lcm/td028ttec1/JBT6K74A-22AS
 TSB_JBT6K74A-22AS_rev231s(D)_eg_20060329' I found the following suspects:

 [p27]: e) Note for "Deep standby mode" release
 ■   Release method
 [ [a diagram showing transfer of three words all-zeroes, with a pause
 between them marked "WAIT=1ms"] ]
 1) Release method
     When transfer “D/C=”0”、Command ="00h" continuously three times.
 Release “Deep standby mode”
       (This rule is All=”0”x9bitx3 times.)

 [ [corresponding code] ]
 static int standby_to_sleep(struct jbt_info *jbt)
         int rc;

         /* three times command zero */
         rc = jbt_reg_write_nodata(jbt, 0x00);
         rc |= jbt_reg_write_nodata(jbt, 0x00);
         rc |= jbt_reg_write_nodata(jbt, 0x00);

         /* deep standby out */
         rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);

         return rc ? -EIO : 0;

 [ [comment] ]
 The 1ms WAIT might be critical, and the language in datasheet makes me
 think this is a minimum value. We should increase to 2ms, just to make

 (00h is being described as "No Operation" and "always valid". Found no
 further info on this)

 Software reset (01h)
        D/XC       D7        D6       D5        D4        D3         D2
 D1        D0
          0         0         0        0         0         0          0
 0         1
    The software reset command initializes the registers for which software
 reset is enabled. A wait of at least 5 ms
 is necessary after the software reset command is issued. Be sure to insert
 a wait of 5 ms or longer before entering
 the next command. If this command is issued in the normal display state,
 the JBT6K74A-22AS reverts to the initial
 state and requires 120 ms to initialize the internal circuits of the LCD
 driver. Wait at least 120 ms before entering
 normal display mode (Sleep-out).

 [ [corresponding code] ]
         /* hard reset the jbt6k74 */

         (jbt6k74_pdata->reset)(0, 0);
         (jbt6k74_pdata->reset)(0, 1);

         rc = jbt_reg_write_nodata(jbt, 0x01);
         if (rc < 0)
                 dev_err(dev, "cannot soft reset\n");


         jbt->state = JBT_STATE_DEEP_STANDBY;

 [ [comment] ]
 Same considerations apply - we should increase time to avoid being "on the
 edge". Here the manual is even specific in specifying "at least 120ms". A
 few dozen more, just for test, won't hurt.

 Sleep-in (10h)
        D/XC       D7         D6        D5       D4       D3         D2
 D1        D0
          0         0          0         0        1        0          0
 0         0
   This command causes the JBT6K74A-22AS to enter sleep mode. In sleep
 mode, the booster and display controller
 are stopped. MCU command access and graphic controller data access are,
 however, permitted. After executing the
 Sleep-in command, the PCLK, VSYNC, and HSYNC synchronization signals from
 the graphics controller must be
 supplied for a period of at least two frames.
   The display controller is stopped in sleep mode. To stop it with
 internal operation stabilized, however, write a
 single frame of all-white (or all-black) display data. This write clears
 the display screen in sleep mode to maintain
 the LCD quality.
   The Sleep-in command must be followed by a wait time of 5 ms to allow
 the internal circuits to stop automatically.
 Be sure to wait for at least 5 ms before entering the command next to the
 Sleep-in command. Note that the
 command cannot be executed until a wait time of 120 ms elapses after the
 Sleep-out command is executed.

 [ [AND] ]
 Sleep-out (11h)
        D/XC       D7       D6        D5       D4        D3        D2
 D1         D0
          0         0        0         0        1         0         0
 0          1
   This command releases the JBT6K74A-22AS from sleep mode. The booster and
 display controller restart upon
 the termination of sleep mode. Display synchronization signals can be
 stopped in sleep mode. Ensure that display
 synchronization signals are supplied for a period of at least two frames
 before executing the Sleep-out command.
 Those signals are necessary to generate an idling state so that the
 internal circuits can start normally.
   The Sleep-out command is the only method of terminating sleep mode. The
 Sleep-out command must be followed
 by a wait time of 5 ms to allow the booster and display controller to
 restart stably. Be sure to wait for at least 5 ms
 before executing the next command. Note that executing the Sleep-out
 command after the Sleep-in command
 requires a wait time of 120 ms between them.

 [ [corresponding code] ]
 [ [comment] ]
 The 5ms seem to be an issue. I don't assume we are entering suspend and
 resuming from suspend in less than 120ms (well maybe even this should be
 checked ;-)

 Detailed explanations on the detail setup commands
 Power supply on/off control (B0h)
 [ [AND] ]
 Booster operation setup (B1h)
 [ [AND] ]
 Booster mode setup (B2h)
 [ [comment] ]
 voltage setup should be checked by OM EE, if we can't find an explanation
 for temperature dependency, which is based on timing issues.
 see [p57:] ''(Supplementation 1) Please evaluate customer’s module to
 optimize booster command setting.''


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