r3600 - branches/src/target/kernel/2.6.24.x/patches
laforge at sita.openmoko.org
laforge at sita.openmoko.org
Thu Dec 6 12:24:50 CET 2007
Author: laforge
Date: 2007-12-06 12:24:48 +0100 (Thu, 06 Dec 2007)
New Revision: 3600
Modified:
branches/src/target/kernel/2.6.24.x/patches/gta01-jbt6k74.patch
Log:
merge commit 3237 from 2.6.22.x patchset: remove double register settings. Not
listed in the data-sheet and it works fine without them. Looks like a
copy-and-paste error. (Stefan Schmidt)
Modified: branches/src/target/kernel/2.6.24.x/patches/gta01-jbt6k74.patch
===================================================================
--- branches/src/target/kernel/2.6.24.x/patches/gta01-jbt6k74.patch 2007-12-06 11:22:14 UTC (rev 3599)
+++ branches/src/target/kernel/2.6.24.x/patches/gta01-jbt6k74.patch 2007-12-06 11:24:48 UTC (rev 3600)
@@ -29,7 +29,7 @@
===================================================================
--- /dev/null
+++ linux-2.6/drivers/spi/jbt6k74.c
-@@ -0,0 +1,654 @@
+@@ -0,0 +1,646 @@
+/* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
@@ -213,7 +213,6 @@
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
-+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
+ rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
+ rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
@@ -234,14 +233,12 @@
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
-+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+
+ if (!qvga) {
+ DEBUGP("entering VGA mode\n");
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
+ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
-+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
+ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
@@ -265,11 +262,6 @@
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
+ }
+
-+#if 0
-+ rc |= jct_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ffe;
-+ ic |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
-+#endif
-+
+ return rc;
+}
+
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