r3629 - developers/sameo/patches/ar6k-ng

sameo at sita.openmoko.org sameo at sita.openmoko.org
Tue Dec 11 02:34:32 CET 2007


Author: sameo
Date: 2007-12-11 02:34:30 +0100 (Tue, 11 Dec 2007)
New Revision: 3629

Added:
   developers/sameo/patches/ar6k-ng/160-ar6k_ng.patch
Log:
ar6k-ng: Added the ar6k code itself to the ng driver.


Added: developers/sameo/patches/ar6k-ng/160-ar6k_ng.patch
===================================================================
--- developers/sameo/patches/ar6k-ng/160-ar6k_ng.patch	2007-12-10 22:31:54 UTC (rev 3628)
+++ developers/sameo/patches/ar6k-ng/160-ar6k_ng.patch	2007-12-11 01:34:30 UTC (rev 3629)
@@ -0,0 +1,20805 @@
+---
+ drivers/net/wireless/Kconfig                           |    1 
+ drivers/net/wireless/Makefile                          |    1 
+ drivers/net/wireless/ar6k/Kconfig                      |   11 
+ drivers/net/wireless/ar6k/Makefile                     |   19 
+ drivers/net/wireless/ar6k/ar6k.h                       |   68 
+ drivers/net/wireless/ar6k/ar6k_main.c                  | 5574 +++++++++++++++++
+ drivers/net/wireless/ar6k/bmi.c                        |  450 +
+ drivers/net/wireless/ar6k/hif.c                        |  204 
+ drivers/net/wireless/ar6k/hif.h                        |   48 
+ drivers/net/wireless/ar6k/htc/Makefile                 |    5 
+ drivers/net/wireless/ar6k/htc/htc.c                    |  426 +
+ drivers/net/wireless/ar6k/htc/htc_events.c             |  886 ++
+ drivers/net/wireless/ar6k/htc/htc_internal.h           |  456 +
+ drivers/net/wireless/ar6k/htc/htc_recv.c               |  197 
+ drivers/net/wireless/ar6k/htc/htc_send.c               |  359 +
+ drivers/net/wireless/ar6k/htc/htc_utils.c              |  394 +
+ drivers/net/wireless/ar6k/include/AR6000_bmi.h         |  136 
+ drivers/net/wireless/ar6k/include/AR6000_gpio.h        |   39 
+ drivers/net/wireless/ar6k/include/AR6000_version.h     |   44 
+ drivers/net/wireless/ar6k/include/app/dset.h           |   77 
+ drivers/net/wireless/ar6k/include/ar6k_api.h           |   79 
+ drivers/net/wireless/ar6k/include/athdefs.h            |   85 
+ drivers/net/wireless/ar6k/include/athdrv.h             |  597 +
+ drivers/net/wireless/ar6k/include/dset_api.h           |   47 
+ drivers/net/wireless/ar6k/include/gpio_api.h           |   60 
+ drivers/net/wireless/ar6k/include/hif.h                |   79 
+ drivers/net/wireless/ar6k/include/host_version.h       |   47 
+ drivers/net/wireless/ar6k/include/htc.h                |  115 
+ drivers/net/wireless/ar6k/include/hw/#mbox_host_reg.h# |  416 +
+ drivers/net/wireless/ar6k/include/hw/mbox_host_reg.h   |  416 +
+ drivers/net/wireless/ar6k/include/hw/mbox_reg.h        |  550 +
+ drivers/net/wireless/ar6k/include/hw/mc_reg.h          | 1129 +++
+ drivers/net/wireless/ar6k/include/hw/rtc_reg.h         | 1204 +++
+ drivers/net/wireless/ar6k/include/ieee80211.h          |  333 +
+ drivers/net/wireless/ar6k/include/ieee80211_ioctl.h    |  121 
+ drivers/net/wireless/ar6k/include/ieee80211_node.h     |   74 
+ drivers/net/wireless/ar6k/include/osapi.h              |   49 
+ drivers/net/wireless/ar6k/include/osapi_linux.h        |  167 
+ drivers/net/wireless/ar6k/include/queue.h              |  550 +
+ drivers/net/wireless/ar6k/include/wlan_api.h           |   90 
+ drivers/net/wireless/ar6k/include/wmi.h                | 1133 +++
+ drivers/net/wireless/ar6k/include/wmi_api.h            |  165 
+ drivers/net/wireless/ar6k/include/wmi_host.h           |   74 
+ drivers/net/wireless/ar6k/include/wmix.h               |  196 
+ drivers/net/wireless/ar6k/install                      |    3 
+ drivers/net/wireless/ar6k/wlan/Makefile                |    2 
+ drivers/net/wireless/ar6k/wlan/wlan_node.c             |  259 
+ drivers/net/wireless/ar6k/wlan/wlan_recv_beacon.c      |  169 
+ drivers/net/wireless/ar6k/wlan/wlan_utils.c            |   53 
+ drivers/net/wireless/ar6k/wmi.c                        | 2834 ++++++++
+ 50 files changed, 20491 insertions(+)
+
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/ar6k.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/ar6k.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Copyright (c) 2007 Felix Fietkau <nbd at openwrt.org>
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ */
++
++#ifndef _AR6K_H_
++#define _AR6K_H_
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/scatterlist.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sdio_func.h>
++#include "include/athdefs.h"
++#include "hif.h"
++
++#define MAX_AR6000                  1
++#define AR6000_MAX_RX_BUFFERS       16
++#define AR6000_BUFFER_SIZE          1552
++#define AR6000_TX_TIMEOUT           10
++#define AR6000_ETH_ADDR_LEN         6
++#define AR6000_MAX_ENDPOINTS        4
++#define MAX_NODE_NUM                15
++#define MAX_COOKIE_NUM              150
++#define AR6000_DATA_OFFSET          64
++
++static inline struct sk_buff *ar6k_alloc_skb(int size)
++{
++	struct sk_buff *skb;
++
++	skb = dev_alloc_skb(AR6000_DATA_OFFSET + size);
++	skb_reserve(skb, AR6000_DATA_OFFSET);
++
++	return skb;
++}
++
++
++/* BMI API */
++void BMIInit(void);
++int BMIDone(struct sdio_func *device);
++int BMIGetTargetId(struct sdio_func *device, u32 * id);
++int BMIReadMemory(struct sdio_func *device, u32 address, u8 * buffer,
++				  u32 length);
++int BMIWriteMemory(struct sdio_func *device, u32 address, u8 * buffer,
++				   u32 length);
++int BMIExecute(struct sdio_func *device, u32 address, u32 * param);
++int BMISetAppStart(struct sdio_func *device, u32 address);
++int BMIReadSOCRegister(struct sdio_func *device, u32 address, u32 * param);
++int BMIWriteSOCRegister(struct sdio_func *device, u32 address, u32 param);
++
++#endif
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/ar6k_main.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/ar6k_main.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,5574 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Copyright (c) 2007 Felix Fietkau <nbd at openwrt.org>
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ */
++
++/*
++ * This driver is a pseudo ethernet driver to access the Atheros AR6000
++ * WLAN Device
++ */
++
++#include "ar6k.h"
++#include <linux/spinlock.h>
++#include <linux/skbuff.h>
++#include <linux/if_ether.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <net/iw_handler.h>
++#include <linux/if_arp.h>
++#include <linux/ip.h>
++#include <linux/rtnetlink.h>
++#include <linux/netdevice.h>
++#include <asm/semaphore.h>
++#include <linux/wireless.h>
++
++#include "include/osapi.h"
++#include "include/htc.h"
++#include "include/wmi.h"
++#include "include/athdrv.h"
++#include "include/ieee80211.h"
++#include "include/ieee80211_ioctl.h"
++#include "include/wlan_api.h"
++#include "include/wmi_api.h"
++#include "include/dset_api.h"
++#include "include/app/dset.h"
++#include "include/gpio_api.h"
++#include "include/AR6000_gpio.h"
++#include "include/host_version.h"
++#include "include/hw/mbox_host_reg.h"
++#include "include/hw/mc_reg.h"
++#include "include/hw/mbox_reg.h"
++#include "include/hw/rtc_reg.h"
++
++MODULE_LICENSE("GPL");
++
++#if defined (SPI)
++#define CONTROL_PADCONF_AA12 0x00E8
++unsigned int awake_gpio = 17;
++unsigned int awake_gpio_pad_conf_offset = CONTROL_PADCONF_AA12;
++unsigned int awake_gpio_pad_conf_byte = 1;
++unsigned int awake_gpio_pad_mode_value = 0x3;
++#endif
++
++int bmienable = 0;
++unsigned int bypasswmi = 0;
++unsigned int debuglevel = 0;
++int tspecCompliance = CCX_V4_COMPLIANCE;
++unsigned int busspeedlow = 0;
++unsigned int onebitmode = 0;
++unsigned int skipflash = 0;
++
++module_param(bmienable, int, 0644);
++module_param(bypasswmi, int, 0644);
++module_param(debuglevel, int, 0644);
++module_param(tspecCompliance, int, 0644);
++module_param(onebitmode, int, 0644);
++module_param(busspeedlow, int, 0644);
++module_param(skipflash, int, 0644);
++
++#define MAX_ALLOWED_TXQ_DEPTH   (HTC_DATA_REQUEST_RING_BUFFER_SIZE - 2)
++static int txFlowCtrlThresh[HTC_MAILBOX_NUM_MAX]
++	= { 0 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++	1 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++	2 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++	3 * (MAX_ALLOWED_TXQ_DEPTH - 1)
++};
++
++/* in 2.6.10 and later this is now a pointer to a uint */
++unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
++#define mboxnum &_mboxnum
++
++#ifdef CONFIG_AR6K_DEBUG
++int debugdriver = 3;
++unsigned int debughtc = 128;
++unsigned int debugbmi = 1;
++unsigned int debughif = 1;
++unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = { 0 };
++unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = { 0 };
++unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = { 0 };
++unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = { 0 };
++
++module_param(debugdriver, int, 0644);
++module_param(debughtc, int, 0644);
++module_param(debugbmi, int, 0644);
++module_param(debughif, int, 0644);
++module_param_array(txcreditsavailable, int, mboxnum, 0644);
++module_param_array(txcreditsconsumed, int, mboxnum, 0644);
++module_param_array(txcreditintrenable, int, mboxnum, 0644);
++module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644);
++
++#endif							/* DEBUG */
++
++unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = { 0 };
++unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = { 0 };
++unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = { 0 };
++module_param_array(tx_attempt, int, mboxnum, 0644);
++module_param_array(tx_post, int, mboxnum, 0644);
++module_param_array(tx_complete, int, mboxnum, 0644);
++
++#ifdef BLOCK_TX_PATH_FLAG
++int blocktx = 0;
++module_param(blocktx, int, 0644);
++#endif							/* BLOCK_TX_PATH_FLAG */
++
++#ifdef CONFIG_AR6K_DEBUG
++#define AR_DEBUG_PRINTF(args...)        if (debugdriver) printk(args);
++#define AR_DEBUG2_PRINTF(args...)        if (debugdriver >= 2) printk(args);
++#else
++#define AR_DEBUG_PRINTF(args...)
++#define AR_DEBUG2_PRINTF(args...)
++#endif
++
++struct ar_wep_key {
++	u8 arKeyIndex;
++	u8 arKeyLen;
++	u8 arKey[64];
++};
++
++struct ar_node_mapping {
++	u8 macAddress[6];
++	u8 epId;
++	u8 txPending;
++};
++
++struct ar_cookie {
++	u32 arc_bp[2];				/* Must be first field */
++	struct ar_cookie *arc_list_next;
++};
++
++typedef struct ar6_softc {
++	struct net_device *arNetDev;	/* net_device pointer */
++	void *arWmi;
++	int arTxPending[AR6000_MAX_ENDPOINTS];
++	int arTotalTxDataPending;
++	u8 arNumDataEndPts;
++	u8 arWmiEnabled;
++	u8 arWmiReady;
++	u8 arConnected;
++	void *arHtcTarget;
++	void *arHifDevice;
++	spinlock_t arLock;
++	struct semaphore arSem;
++	int arRxBuffers[AR6000_MAX_ENDPOINTS];
++	int arSsidLen;
++	u_char arSsid[32];
++	u8 arNetworkType;
++	u8 arDot11AuthMode;
++	u8 arAuthMode;
++	u8 arPairwiseCrypto;
++	u8 arPairwiseCryptoLen;
++	u8 arGroupCrypto;
++	u8 arGroupCryptoLen;
++	u8 arDefTxKeyIndex;
++	struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1];
++	u8 arBssid[6];
++	u8 arReqBssid[6];
++	u16 arChannelHint;
++	u16 arBssChannel;
++	u16 arListenInterval;
++	struct ar6k_version arVersion;
++	s8 arRssi;
++	u8 arTxPwr;
++	u8 arTxPwrSet;
++	s32 arBitRate;
++	struct net_device_stats arNetStats;
++	struct iw_statistics arIwStats;
++	s8 arNumChannels;
++	u16 arChannelList[32];
++	u32 arRegCode;
++	u8 statsUpdatePending;
++	TARGET_STATS arTargetStats;
++	s8 arMaxRetries;
++	u8 arPhyCapability;
++	AR6000_WLAN_STATE arWlanState;
++	struct ar_node_mapping arNodeMap[MAX_NODE_NUM];
++	u8 arIbssPsEnable;
++	u8 arNodeNum;
++	u8 arNexEpId;
++	struct ar_cookie *arCookieList;
++	u8 arConnectPending;
++} AR_SOFTC_T;
++
++struct ar_giwscan_param {
++	char *current_ev;
++	char *end_buf;
++	u8 firstPass;
++};
++
++#define AR6000_STAT_INC(ar, stat)       (ar->arNetStats.stat++)
++
++#define AR6000_SPIN_LOCK(lock, param)   do {                            \
++    if (irqs_disabled()) {                                              \
++        AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n");                 \
++    }                                                                   \
++    spin_lock_bh(lock);                                                 \
++} while (0)
++
++#define AR6000_SPIN_UNLOCK(lock, param) do {                            \
++    if (irqs_disabled()) {                                              \
++        AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n");              \
++    }                                                                   \
++    spin_unlock_bh(lock);                                               \
++} while (0)
++
++/* Function declarations */
++static int ar6k_init_module(void);
++static void ar6k_cleanup_module(void);
++
++static int ar6k_init(struct net_device *dev);
++static int ar6k_open(struct net_device *dev);
++static int ar6k_close(struct net_device *dev);
++static void ar6k_init_control_info(AR_SOFTC_T * ar);
++static void ar6k_init_profile_info(AR_SOFTC_T * ar);
++static int ar6k_data_tx(struct sk_buff *skb, struct net_device *dev);
++static int ar6k_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++static void ar6k_destroy(struct net_device *dev);
++static struct net_device_stats *ar6k_get_stats(struct net_device *dev);
++static void ar6k_ioctl_iwsetup(struct iw_handler_def *def);
++static int ar6k_ioctl_set_channelParams(struct net_device *dev,
++										  struct ifreq *rq);
++static int ar6k_ioctl_set_probedSsid(struct net_device *dev,
++									   struct ifreq *rq);
++static int ar6k_ioctl_set_badAp(struct net_device *dev,
++								  struct ifreq *rq);
++static int ar6k_ioctl_get_qos_queue(struct net_device *dev,
++									  struct ifreq *rq);
++static int ar6k_ioctl_delete_qos(struct net_device *dev,
++								   struct ifreq *rq);
++static int ar6k_ioctl_create_qos(struct net_device *dev,
++								   struct ifreq *rq);
++static int ar6k_ioctl_set_link_threshold(struct net_device *dev,
++										   struct ifreq *rq);
++static int ar6k_ioctl_get_target_stats(struct net_device *dev,
++										 struct ifreq *rq);
++static int ar6k_ioctl_set_error_report_bitmask(struct net_device *dev,
++												 struct ifreq *rq);
++static int ar6k_ioctl_set_access_params(struct net_device *dev,
++										  struct ifreq *rq);
++static int ar6k_ioctl_set_disconnect_timeout(struct net_device *dev,
++											   struct ifreq *rq);
++static int ar6k_xioctl_set_voice_pkt_size(struct net_device *dev,
++											char *userdata);
++static int ar6k_xioctl_set_max_sp_len(struct net_device *dev,
++										char *userdata);
++static int ar6k_ioctl_get_roam_tbl(struct net_device *dev,
++									 struct ifreq *rq);
++static int ar6k_ioctl_get_roam_data(struct net_device *dev,
++									  struct ifreq *rq);
++static int ar6k_ioctl_set_roam_ctrl(struct net_device *dev,
++									  char *userdata);
++static int ar6k_ioctl_set_powersave_timers(struct net_device *dev,
++											 char *userdata);
++static int ar6k_ioctl_get_power_mode(struct net_device *dev,
++									   struct ifreq *rq);
++
++#ifdef HTC_RAW_INTERFACE
++static void ar6k_htc_raw_read_cb(HTC_TARGET * htcTarget,
++								   HTC_ENDPOINT_ID endPointId,
++								   HTC_EVENT_ID evId,
++								   HTC_EVENT_INFO * evInfo, void *arg);
++static void ar6k_htc_raw_unread_cb(HTC_TARGET * htcTarget,
++									 HTC_ENDPOINT_ID endPointId,
++									 HTC_EVENT_ID evId,
++									 HTC_EVENT_INFO * evInfo, void *arg);
++static void ar6k_htc_raw_write_cb(HTC_TARGET * htcTarget,
++									HTC_ENDPOINT_ID endPointId,
++									HTC_EVENT_ID evId,
++									HTC_EVENT_INFO * evInfo, void *arg);
++static int ar6k_htc_raw_open(HTC_TARGET * htcTarget);
++static int ar6k_htc_raw_close(HTC_TARGET * htcTarget);
++static ssize_t ar6k_htc_raw_read(HTC_TARGET * htcTarget,
++								   HTC_ENDPOINT_ID endPointId,
++								   char __user * buffer, size_t count);
++static ssize_t ar6k_htc_raw_write(HTC_TARGET * htcTarget,
++									HTC_ENDPOINT_ID endPointId,
++									char __user * buffer, size_t count);
++#endif							/* HTC_RAW_INTERFACE */
++static void ar6k_install_static_wep_keys(AR_SOFTC_T * ar);
++static int ar6k_ioctl_addpmkid(struct net_device *dev,
++								 struct iw_request_info *info, void *w,
++								 char *extra);
++
++#if CONFIG_HOST_DSET_SUPPORT
++static void ar6k_dset_init(void);
++static int ar6k_ioctl_wait_dset_req(struct net_device *dev,
++									  struct ifreq *rq);
++static int ar6k_ioctl_dset_open_reply(struct net_device *dev,
++										struct ifreq *rq);
++static int ar6k_ioctl_dset_data_reply(struct net_device *dev,
++										struct ifreq *rq);
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++static void ar6k_gpio_init(void);
++int ar6k_gpio_output_set(struct net_device *dev,
++						   u32 set_mask,
++						   u32 clear_mask,
++						   u32 enable_mask, u32 disable_mask);
++static int ar6k_gpio_input_get(struct net_device *dev);
++static int ar6k_gpio_register_set(struct net_device *dev,
++									u32 gpioreg_id, u32 value);
++static int ar6k_gpio_register_get(struct net_device *dev,
++									u32 gpioreg_id);
++static int ar6k_gpio_intr_ack(struct net_device *dev, u32 ack_mask);
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++/*
++ * HTC event handlers
++ */
++static void ar6k_avail_ev(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++							HTC_EVENT_ID id, HTC_EVENT_INFO * evInfo,
++							void *arg);
++
++static void ar6k_unavail_ev(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++							  HTC_EVENT_ID id, HTC_EVENT_INFO * evInfo,
++							  void *arg);
++
++static void ar6k_rx(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++					  HTC_EVENT_ID id, HTC_EVENT_INFO * evInfo, void *arg);
++
++static void ar6k_rx_refill(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++							 HTC_EVENT_ID id, HTC_EVENT_INFO * evInfo,
++							 void *arg);
++
++static void ar6k_tx_complete(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++							   HTC_EVENT_ID id, HTC_EVENT_INFO * evInfo,
++							   void *arg);
++
++/*
++ * Static variables
++ */
++static struct net_device *ar6k_devices[MAX_AR6000];
++static struct iw_handler_def ath_iw_handler_def;
++static DECLARE_WAIT_QUEUE_HEAD(arEvent);
++static u8 bcast_mac[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
++static u8 null_mac[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
++
++#if CONFIG_HOST_GPIO_SUPPORT
++struct ar6k_gpio_intr_wait_cmd_s gpio_intr_results;
++/* gpio_reg_results and gpio_data_available are protected by arSem */
++static struct ar6k_gpio_register_cmd_s gpio_reg_results;
++static u8 gpio_data_available;	/* Requested GPIO data available */
++static u8 gpio_intr_available;	/* GPIO interrupt info available */
++static u8 gpio_ack_received;	/* GPIO ack was received */
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++#if 0
++static struct iw_statistics *ar6k_get_iwstats(struct net_device *dev);
++#endif
++
++/*
++ * adhoc PS support
++ */
++static void ar6k_cookie_init(AR_SOFTC_T * ar);
++static void ar6k_cookie_cleanup(AR_SOFTC_T * ar);
++static void ar6k_free_cookie(AR_SOFTC_T * ar, struct ar_cookie *cookie);
++static struct ar_cookie *ar6k_alloc_cookie(AR_SOFTC_T * ar);
++
++static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
++
++static int __init ar6k_init_module(void)
++{
++	static int probed = 0;
++	int status;
++
++       	printk("##### %s() #########\n", __FUNCTION__);
++
++	if (probed) {
++		return -ENODEV;
++	}
++	probed++;
++
++#if CONFIG_HOST_DSET_SUPPORT
++	ar6k_dset_init();
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++	ar6k_gpio_init();
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++	status = HTCInit();
++	if (status != A_OK)
++		return -ENODEV;
++
++	HTCEventReg(NULL, ENDPOINT_UNUSED, HTC_TARGET_AVAILABLE,
++				ar6k_avail_ev, NULL);
++	HTCEventReg(NULL, ENDPOINT_UNUSED, HTC_TARGET_UNAVAILABLE,
++				ar6k_unavail_ev, NULL);
++
++	return 0;
++}
++
++static void __exit ar6k_cleanup_module(void)
++{
++	int i = 0;
++	struct net_device *ar6k_netdev;
++
++	for (i = 0; i < MAX_AR6000; i++) {
++		if (ar6k_devices[i] != NULL) {
++			ar6k_netdev = ar6k_devices[i];
++			ar6k_devices[i] = NULL;
++			ar6k_destroy(ar6k_netdev);
++		}
++	}
++
++	/* This will unregister with the SDIO bus driver */
++	HTCShutDown(NULL);
++
++	AR_DEBUG_PRINTF("ar6k_cleanup: success\n");
++}
++
++/*
++ * Write to the AR6000 through its diagnostic window.
++ * No cooperation from the Target is required for this.
++ */
++int ar6k_WriteRegDiag(struct sdio_func *func, u32 * address, u32 * data)
++{
++	int ret;
++
++	ret = sdio_memcpy_toio(func, WINDOW_DATA_ADDRESS, data, sizeof(u32));
++	if (ret) {
++		AR_DEBUG_PRINTF("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n",
++						*data);
++		return A_ERROR;
++	}
++
++	ret = sdio_memcpy_toio(func, WINDOW_WRITE_ADDR_ADDRESS + 1,
++						   ((u8 *) address) + 1, sizeof(u32) - 1);
++	if (ret) {
++		AR_DEBUG_PRINTF
++			("Cannot write initial bytes of 0x%x to WINDOW_WRITE_ADDR_ADDRESS\n",
++			 *address);
++		return A_ERROR;
++	}
++
++	ret =
++		sdio_memcpy_toio(func, WINDOW_WRITE_ADDR_ADDRESS, (u8 *) address,
++						 1);
++	if (ret) {
++		AR_DEBUG_PRINTF("Cannot write 0x%x to WINDOW_WRITE_ADDR_ADDRESS\n",
++						*address);
++		return A_ERROR;
++	}
++
++	return 0;
++}
++
++/*
++ * HTC Event handlers
++ */
++static void
++ar6k_avail_ev(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++	      HTC_EVENT_ID event, HTC_EVENT_INFO * evInfo, void *arg)
++{
++	int i, ret ;
++	struct net_device *dev;
++	AR_SOFTC_T *ar;
++	int device_index = 0;
++
++	AR_DEBUG_PRINTF("ar6k_available\n");
++
++	for (i = 0; i < MAX_AR6000; i++) {
++		if (ar6k_devices[i] == NULL) {
++			break;
++		}
++	}
++
++	if (i == MAX_AR6000) {
++		AR_DEBUG_PRINTF("ar6k_available: max devices reached\n");
++		return;
++	}
++
++	/* Save this. It gives a bit better readability especially since */
++	/* we use another local "i" variable below.  */
++	device_index = i;
++
++	A_ASSERT(htcTarget != NULL);
++	A_ASSERT(event == HTC_TARGET_AVAILABLE);
++
++	dev = alloc_etherdev(sizeof(AR_SOFTC_T));
++	if (dev == NULL) {
++		AR_DEBUG_PRINTF("ar6k_available: can't alloc etherdev\n");
++		return;
++	}
++
++	ether_setup(dev);
++
++	if (dev->priv == NULL) {
++		printk(KERN_CRIT "ar6k_available: Could not allocate memory\n");
++		return;
++	}
++
++	A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T));
++
++	ar = (AR_SOFTC_T *) dev->priv;
++	ar->arNetDev = dev;
++	ar->arHtcTarget = htcTarget;
++	ar->arHifDevice = evInfo->buffer;
++	ar->arWlanState = WLAN_ENABLED;
++
++	ar6k_init_control_info(ar);
++	init_waitqueue_head(&arEvent);
++	sema_init(&ar->arSem, 1);
++
++	/*
++	 * If requested, perform some magic which requires no cooperation from
++	 * the Target.  It causes the Target to ignore flash and execute the
++	 * OS from ROM.
++	 *
++	 * This code uses the Diagnostic Window to remap instructions at
++	 * the start of ROM in such a way that on the next CPU reset, the
++	 * ROM code avoids using flash.  Then it uses the Diagnostic
++	 * Window to force a CPU Warm Reset.
++	 *
++	 * This is intended to support recovery from a corrupted flash.
++	 */
++	if (skipflash) {
++		int i;
++
++		static struct {
++			u32 addr;
++			u32 data;
++		} ForceROM[] = {
++			/* NB: This is ROM-version dependent. */
++			{
++				0x00001ff0, 0x175b0027
++			},	/* jump instruction at 0xa0001ff0 */
++			{
++				0x00001ff4, 0x00000000
++			},	/* nop instruction at 0xa0001ff4 */
++			{
++				MC_REMAP_TARGET_ADDRESS, 0x00001ff0
++			},	/* remap to 0xa0001ff0 */
++			{
++				MC_REMAP_COMPARE_ADDRESS, 0x01000040
++			},	/* ...from 0xbfc00040 */
++			{
++				MC_REMAP_SIZE_ADDRESS, 0x00000000
++			},	/* ...1 cache line */
++			{
++				MC_REMAP_VALID_ADDRESS, 0x00000001
++			},	/* ...remap is valid */
++			{
++				LOCAL_COUNT_ADDRESS + 0x10, 0
++			},	/* clear BMI credit counter */
++			{
++				RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK
++			},
++		};
++
++		AR_DEBUG_PRINTF("Force Target to execute from ROM....\n");
++		for (i = 0; i < sizeof(ForceROM) / sizeof(*ForceROM); i++) {
++			if (ar6k_WriteRegDiag(ar->arHifDevice,
++					      &ForceROM[i].addr,
++					      &ForceROM[i].data) != A_OK) {
++				AR_DEBUG_PRINTF("Cannot force Target to execute ROM!\n");
++				break;
++			}
++		}
++	}
++
++	BMIInit();
++	if ((BMIGetTargetId(ar->arHifDevice, &ar->arVersion.target_ver)) !=
++		A_OK) {
++		return;
++	}
++
++	spin_lock_init(&ar->arLock);
++
++	/* Don't install the init function if BMI is requested */
++	if (!bmienable) {
++		dev->init = ar6k_init;
++	}
++	dev->open = &ar6k_open;
++	dev->stop = &ar6k_close;
++	dev->hard_start_xmit = &ar6k_data_tx;
++	dev->get_stats = &ar6k_get_stats;
++#if 0
++	dev->get_wireless_stats = ar6k_get_iwstats;	/* Displayed via proc
++													   fs */
++#endif
++	/* dev->tx_timeout = ar6k_tx_timeout; */
++	dev->do_ioctl = &ar6k_ioctl;
++	dev->watchdog_timeo = AR6000_TX_TIMEOUT;
++	ar6k_ioctl_iwsetup(&ath_iw_handler_def);
++	dev->wireless_handlers = &ath_iw_handler_def;
++
++	/*
++	 * We need the OS to provide us with more headroom in order to
++	 * perform dix to 802.3, WMI header encap, and the HTC header
++	 */
++	dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
++		sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN;
++
++	/* This runs the init function */
++	ret = register_netdev(dev);
++	if (ret) {
++		AR_DEBUG_PRINTF("ar6k_avail: register_netdev failed (%d)\n", ret);
++		ar6k_destroy(dev);
++		return;
++	}
++
++	/* We only register the device in the global list if we succeed. */
++	/* If the device is in the global list, it will be destroyed */
++	/* when the module is unloaded.  */
++	ar6k_devices[device_index] = dev;
++
++	AR_DEBUG_PRINTF
++		("ar6k_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n",
++		 dev->name, (u32) htcTarget, (u32) dev, device_index, (u32) ar);
++}
++
++static void
++ar6k_unavail_ev(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++				  HTC_EVENT_ID event, HTC_EVENT_INFO * evInfo, void *arg)
++{
++	int i;
++	AR_SOFTC_T *ar;
++	struct net_device *ar6k_netdev;
++
++	for (i = 0; i < MAX_AR6000; i++) {
++		if (ar6k_devices[i] != NULL) {
++			ar = (AR_SOFTC_T *) ar6k_devices[i]->priv;
++			if (ar && ar->arHtcTarget == htcTarget) {
++				ar6k_netdev = ar6k_devices[i];
++				ar6k_devices[i] = NULL;
++				ar6k_destroy(ar6k_netdev);
++			}
++		}
++	}
++}
++
++static void ar6k_destroy(struct net_device *dev)
++{
++	AR_SOFTC_T *ar;
++
++	if ((dev == NULL) || ((ar = netdev_priv(dev)) == NULL)) {
++		AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n",
++						__func__);
++		return;
++	}
++
++	/* Stop the transmit queues */
++	netif_stop_queue(dev);
++
++	/* Disable the target and the interrupts associated with it */
++	if (ar->arWmiReady == TRUE) {
++		if (!bypasswmi) {
++			if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
++				AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__);
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				ar6k_init_profile_info(ar);
++				wmi_disconnect_cmd(ar->arWmi);
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++
++			/* It's necessary to wait for the tx pending cleaning */
++			wait_event_interruptible(arEvent,
++									 ar->arTxPending[WMI_CONTROL_MBOX] ==
++									 0);
++
++			ar->arWmiReady = FALSE;
++			ar->arConnected = FALSE;
++			ar->arConnectPending = FALSE;
++			wmi_shutdown(ar->arWmi);
++			ar->arWmiEnabled = FALSE;
++			ar->arWmi = NULL;
++			ar->arWlanState = WLAN_ENABLED;
++		}
++
++		/* It's necessary to wait for the tx pending cleaning */
++		wait_event_interruptible(arEvent,
++								 ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++
++		HTCStop(ar->arHtcTarget);
++
++		/* It's necessary to wait for the tx pending cleaning */
++		wait_event_interruptible(arEvent,
++								 ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++
++		AR_DEBUG_PRINTF("%s(): WMI and HTC stopped\n", __func__);
++	} else {
++		AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n",
++						__func__, (unsigned int) ar,
++						(unsigned int) ar->arWmi);
++
++		/* Shut down WMI if we have started it */
++		if (ar->arWmiEnabled == TRUE) {
++			AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__);
++			wmi_shutdown(ar->arWmi);
++			ar->arWmiEnabled = FALSE;
++			ar->arWmi = NULL;
++		}
++
++		/* It's necessary to wait for the tx pending cleaning */
++		wait_event_interruptible(arEvent,
++					 ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++
++		HTCStop(ar->arHtcTarget);
++
++		/* It's necessary to wait for the tx pending cleaning */
++		wait_event_interruptible(arEvent,
++					 ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++	}
++
++	BMIInit();
++
++	/* Done with cookies */
++	ar6k_cookie_cleanup(ar);
++
++	/* Free up the device data structure */
++	HTCShutDown(ar->arHtcTarget);
++
++	unregister_netdev(dev);
++#ifdef mvlcee31_2_4_20_omap2420_gsm_gprs
++	kfree(dev);
++#else
++	free_netdev(dev);
++#endif
++}
++
++static void ar6k_init_profile_info(AR_SOFTC_T * ar)
++{
++	ar->arSsidLen = 0;
++	A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++	ar->arNetworkType = INFRA_NETWORK;
++	ar->arDot11AuthMode = OPEN_AUTH;
++	ar->arAuthMode = NONE_AUTH;
++	ar->arPairwiseCrypto = NONE_CRYPT;
++	ar->arPairwiseCryptoLen = 0;
++	ar->arGroupCrypto = NONE_CRYPT;
++	ar->arGroupCryptoLen = 0;
++	A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
++	A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++	A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
++	ar->arBssChannel = 0;
++}
++
++static void ar6k_init_control_info(AR_SOFTC_T * ar)
++{
++	ar->arWmiEnabled = FALSE;
++	ar6k_init_profile_info(ar);
++	ar->arDefTxKeyIndex = 0;
++	A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
++	ar->arChannelHint = 0;
++	ar->arListenInterval = MAX_LISTEN_INTERVAL;
++	ar->arVersion.host_ver = AR6000_SW_VERSION;
++	ar->arRssi = 0;
++	ar->arTxPwr = 0;
++	ar->arTxPwrSet = FALSE;
++	ar->arBitRate = 0;
++	ar->arMaxRetries = 0;
++}
++
++static int ar6k_open(struct net_device *dev)
++{
++	/* Wake up the queues */
++	netif_wake_queue(dev);
++
++	return 0;
++}
++
++static int ar6k_close(struct net_device *dev)
++{
++	netif_stop_queue(dev);
++
++	return 0;
++}
++
++/* This function does one time initialization for the lifetime of the device */
++static int ar6k_init(struct net_device *dev)
++{
++	int i;
++	AR_SOFTC_T *ar;
++	int endpoint[] = { ENDPOINT1, ENDPOINT2, ENDPOINT3, ENDPOINT4 };
++	int status;
++	s32 timeleft;
++
++	if ((ar = netdev_priv(dev)) == NULL) {
++		return (-EIO);
++	}
++
++	/* Do we need to finish the BMI phase */
++	if (BMIDone(ar->arHifDevice) != A_OK) {
++		return -EIO;
++	}
++
++	if (!bypasswmi) {
++		if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
++			A_PRINTF("WARNING: Host version 0x%x does not match Target "
++					 " version 0x%x!\n",
++					 ar->arVersion.host_ver, ar->arVersion.target_ver);
++		}
++
++		/* Indicate that WMI is enabled (although not ready yet) */
++		ar->arWmiEnabled = TRUE;
++		if ((ar->arWmi = wmi_init((void *) ar)) == NULL) {
++			AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__);
++			return (-EIO);
++		}
++
++		AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__,
++						(unsigned int) ar->arWmi);
++	}
++
++	/* Install event handlers for each end point */
++	for (i = 0; i < (sizeof(endpoint) / sizeof(int)); i++) {
++		if (HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_BUFFER_RECEIVED,
++						ar6k_rx, ar) != A_OK) {
++			return (-EIO);
++		}
++
++		if (HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_DATA_AVAILABLE,
++						ar6k_rx_refill, ar) != A_OK) {
++			return (-EIO);
++		}
++
++		if (HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_BUFFER_SENT,
++						ar6k_tx_complete, ar) != A_OK) {
++			return (-EIO);
++		}
++	}
++
++	/*
++	 * Provide HTC with receive buffers
++	 */
++	ar6k_rx_refill(ar->arHtcTarget, ENDPOINT1, HTC_DATA_AVAILABLE,
++					 NULL, ar);
++
++	ar6k_rx_refill(ar->arHtcTarget, ENDPOINT2, HTC_DATA_AVAILABLE,
++					 NULL, ar);
++
++	/*
++	 * We will post the receive buffers only for SPE testing and so we are
++	 * making it conditional on the 'bypasswmi' flag.
++	 */
++	if (bypasswmi) {
++		ar6k_rx_refill(ar->arHtcTarget, ENDPOINT3, HTC_DATA_AVAILABLE,
++						 NULL, ar);
++
++		ar6k_rx_refill(ar->arHtcTarget, ENDPOINT4, HTC_DATA_AVAILABLE,
++						 NULL, ar);
++	}
++
++	/* Since cookies are used for HTC transports, they should be */
++	/* initialized prior to enabling HTC.  */
++	ar6k_cookie_init(ar);
++
++	/* Enable the target and the interrupts associated with it */
++	status = HTCStart(ar->arHtcTarget);
++
++	if (status != A_OK) {
++		if (ar->arWmiEnabled == TRUE) {
++			wmi_shutdown(ar->arWmi);
++			ar->arWmiEnabled = FALSE;
++			ar->arWmi = NULL;
++		}
++		ar6k_cookie_cleanup(ar);
++		return -EIO;
++	}
++
++	if (!bypasswmi) {
++		/* Wait for Wmi event to be ready */
++		timeleft = wait_event_interruptible_timeout(arEvent,
++													(ar->arWmiReady ==
++													 TRUE), 1 * HZ);
++
++		if (!timeleft || signal_pending(current)) {
++			AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n");
++			return -EIO;
++		}
++
++		AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__);
++	}
++
++	ar->arNumDataEndPts = 1;
++
++	return (0);
++}
++
++/* This would basically hold all the private ioctls that are not related to
++   WLAN operation */
++static int ar6k_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct sdio_func *hifDevice = ar->arHifDevice;
++	HTC_TARGET *htcTarget = ar->arHtcTarget;
++	int ret, param;
++	unsigned int address = 0;
++	unsigned int length = 0;
++	unsigned char *buffer;
++	char *userdata;
++#ifdef HTC_RAW_INTERFACE
++	HTC_ENDPOINT_ID endPointId = 0;
++	static u8 rawIfInit = FALSE;
++#endif							/* HTC_RAW_INTERFACE */
++	static WMI_SCAN_PARAMS_CMD scParams = { 0, 0, 0, 0, 0,
++		WMI_SHORTSCANRATIO_DEFAULT
++	};
++
++	if (cmd == AR6000_IOCTL_EXTENDED) {
++		/*
++		 * This allows for many more wireless ioctls than would otherwise
++		 * be available.  Applications embed the actual ioctl command in
++		 * the first word of the parameter block, and use the command
++		 * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
++		 */
++		get_user(cmd, (int *) rq->ifr_data);
++		userdata = (char *) (((unsigned int *) rq->ifr_data) + 1);
++	} else {
++		userdata = (char *) rq->ifr_data;
++	}
++
++	if ((ar->arWlanState == WLAN_DISABLED) &&
++		(cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE)) {
++		return -EIO;
++	}
++
++	ret = 0;
++	switch (cmd) {
++	case AR6000_XIOCTL_BMI_DONE:
++		if (bmienable) {
++			ret = ar6k_init(dev);
++		} else {
++			ret = BMIDone(hifDevice);
++		}
++		break;
++
++	case AR6000_XIOCTL_BMI_READ_MEMORY:
++		get_user(address, (unsigned int *) userdata);
++		get_user(length, (unsigned int *) userdata + 1);
++		AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n",
++						address, length);
++		if ((buffer = (unsigned char *) A_MALLOC(length)) != NULL) {
++			A_MEMZERO(buffer, length);
++			ret = BMIReadMemory(hifDevice, address, buffer, length);
++			if (copy_to_user(rq->ifr_data, buffer, length)) {
++				ret = -EFAULT;
++			}
++			A_FREE(buffer);
++		} else {
++			ret = -ENOMEM;
++		}
++		break;
++
++	case AR6000_XIOCTL_BMI_WRITE_MEMORY:
++		get_user(address, (unsigned int *) userdata);
++		get_user(length, (unsigned int *) userdata + 1);
++		AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n",
++						address, length);
++		if ((buffer = (unsigned char *) A_MALLOC(length)) != NULL) {
++			A_MEMZERO(buffer, length);
++			if (copy_from_user(buffer, &userdata[sizeof(address) +
++												 sizeof(length)], length))
++			{
++				ret = -EFAULT;
++			} else {
++				ret = BMIWriteMemory(hifDevice, address, buffer, length);
++			}
++			A_FREE(buffer);
++		} else {
++			ret = -ENOMEM;
++		}
++		break;
++
++	case AR6000_XIOCTL_BMI_TEST:
++		AR_DEBUG_PRINTF("No longer supported\n");
++		ret = -EOPNOTSUPP;
++		break;
++
++	case AR6000_XIOCTL_BMI_EXECUTE:
++		get_user(address, (unsigned int *) userdata);
++		get_user(param, (unsigned int *) userdata + 1);
++		AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n",
++						address, param);
++		ret = BMIExecute(hifDevice, address, &param);
++		put_user(param, (unsigned int *) rq->ifr_data);	/* return value */
++		break;
++
++	case AR6000_XIOCTL_BMI_SET_APP_START:
++		get_user(address, (unsigned int *) userdata);
++		AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address);
++		ret = BMISetAppStart(hifDevice, address);
++		break;
++
++	case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
++		get_user(address, (unsigned int *) userdata);
++		ret = BMIReadSOCRegister(hifDevice, address, &param);
++		put_user(param, (unsigned int *) rq->ifr_data);	/* return value */
++		break;
++
++	case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
++		get_user(address, (unsigned int *) userdata);
++		get_user(param, (unsigned int *) userdata + 1);
++		ret = BMIWriteSOCRegister(hifDevice, address, param);
++		break;
++
++#ifdef HTC_RAW_INTERFACE
++	case AR6000_XIOCTL_HTC_RAW_OPEN:
++		ret = A_OK;
++		if (!rawIfInit) {
++			/* Terminate the BMI phase */
++			ret = BMIDone(hifDevice);
++			if (ret == A_OK) {
++				ret = ar6k_htc_raw_open(htcTarget);
++			}
++			if (ret == A_OK) {
++				rawIfInit = TRUE;
++			}
++		}
++		break;
++
++	case AR6000_XIOCTL_HTC_RAW_CLOSE:
++		if (rawIfInit) {
++			ret = ar6k_htc_raw_close(htcTarget);
++			rawIfInit = FALSE;
++		} else {
++			ret = A_ERROR;
++		}
++		break;
++
++	case AR6000_XIOCTL_HTC_RAW_READ:
++		if (rawIfInit) {
++			get_user(endPointId, (unsigned int *) userdata);
++			get_user(length, (unsigned int *) userdata + 1);
++			buffer = rq->ifr_data + sizeof(length);
++			ret = ar6k_htc_raw_read(htcTarget, endPointId,
++									  buffer, length);
++			put_user(ret, (unsigned int *) rq->ifr_data);
++		} else {
++			ret = A_ERROR;
++		}
++		break;
++
++	case AR6000_XIOCTL_HTC_RAW_WRITE:
++		if (rawIfInit) {
++			get_user(endPointId, (unsigned int *) userdata);
++			get_user(length, (unsigned int *) userdata + 1);
++			buffer = userdata + sizeof(endPointId) + sizeof(length);
++			ret = ar6k_htc_raw_write(htcTarget, endPointId,
++									   buffer, length);
++			put_user(ret, (unsigned int *) rq->ifr_data);
++		} else {
++			ret = A_ERROR;
++		}
++		break;
++#endif							/* HTC_RAW_INTERFACE */
++
++	case AR6000_IOCTL_WMI_GETREV:
++		{
++			if (copy_to_user(rq->ifr_data, &ar->arVersion,
++							 sizeof(ar->arVersion))) {
++				ret = -EFAULT;
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SETPWR:
++		{
++			WMI_POWER_MODE_CMD pwrModeCmd;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&pwrModeCmd, userdata,
++									  sizeof(pwrModeCmd))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
++					!= A_OK) {
++					ret = -EIO;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
++		{
++			WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&ibssPmCaps, userdata,
++									  sizeof(ibssPmCaps))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_ibsspmcaps_cmd
++					(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
++					 ibssPmCaps.atim_windows,
++					 ibssPmCaps.timeout_value) != A_OK) {
++					ret = -EIO;
++				}
++				ar->arIbssPsEnable = ibssPmCaps.power_saving;
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_PMPARAMS:
++		{
++			WMI_POWER_PARAMS_CMD pmParams;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&pmParams, userdata,
++									  sizeof(pmParams))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
++									 pmParams.pspoll_number,
++									 pmParams.dtim_policy) != A_OK) {
++					ret = -EIO;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SETSCAN:
++		{
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&scParams, userdata,
++									  sizeof(scParams))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
++									   scParams.fg_end_period,
++									   scParams.bg_period,
++									   scParams.act_chdwell_time,
++									   scParams.pas_chdwell_time,
++									   scParams.shortScanRatio) != A_OK) {
++					ret = -EIO;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SETLISTENINT:
++		{
++			WMI_LISTEN_INT_CMD listenCmd;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&listenCmd, userdata,
++									  sizeof(listenCmd))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_listeninterval_cmd
++					(ar->arWmi, listenCmd.listenInterval,
++					 listenCmd.numBeacons) != A_OK) {
++					ret = -EIO;
++				} else {
++					ar->arListenInterval = param;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_BMISS_TIME:
++		{
++			WMI_BMISS_TIME_CMD bmissCmd;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&bmissCmd, userdata,
++									  sizeof(bmissCmd))) {
++				ret = -EFAULT;
++			} else {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_bmisstime_cmd
++					(ar->arWmi, bmissCmd.bmissTime,
++					 bmissCmd.numBeacons) != A_OK) {
++					ret = -EIO;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SETBSSFILTER:
++		{
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else {
++				get_user(param, (unsigned int *) userdata);
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				if (wmi_bssfilter_cmd(ar->arWmi, param) != A_OK) {
++					ret = -EIO;
++				}
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_LINKTHRESHOLD:
++		{
++			ret = ar6k_ioctl_set_link_threshold(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
++		{
++			ret = ar6k_ioctl_set_channelParams(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_PROBEDSSID:
++		{
++			ret = ar6k_ioctl_set_probedSsid(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_BADAP:
++		{
++			ret = ar6k_ioctl_set_badAp(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_CREATE_QOS:
++		{
++			ret = ar6k_ioctl_create_qos(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_DELETE_QOS:
++		{
++			ret = ar6k_ioctl_delete_qos(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
++		{
++			ret = ar6k_ioctl_get_qos_queue(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_GET_TARGET_STATS:
++		{
++			ret = ar6k_ioctl_get_target_stats(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
++		{
++			ret = ar6k_ioctl_set_error_report_bitmask(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
++		{
++			WMI_SET_ASSOC_INFO_CMD cmd;
++			u8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else {
++				get_user(cmd.ieType, userdata);
++				if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
++					ret = -EIO;
++				} else {
++					get_user(cmd.bufferSize, userdata + 1);
++					if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
++						ret = -EFAULT;
++						break;
++					}
++					if (copy_from_user(assocInfo, userdata + 2,
++									   cmd.bufferSize)) {
++						ret = -EFAULT;
++					} else {
++						AR6000_SPIN_LOCK(&ar->arLock, 0);
++						if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
++											  cmd.bufferSize,
++											  assocInfo) != A_OK) {
++							ret = -EIO;
++						}
++						AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++					}
++				}
++			}
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
++		{
++			ret = ar6k_ioctl_set_access_params(dev, rq);
++			break;
++		}
++	case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
++		{
++			ret = ar6k_ioctl_set_disconnect_timeout(dev, rq);
++			break;
++		}
++#if CONFIG_HOST_DSET_SUPPORT
++	case AR6000_XIOCTL_WMI_DSET_WAIT_REQ:
++		{
++			ar6k_ioctl_wait_dset_req(dev, rq);
++			break;
++		}
++	case AR6000_XIOCTL_WMI_DSET_OPEN_REPLY:
++		{
++			AR6000_SPIN_LOCK(&ar->arLock, 0);
++			ar6k_ioctl_dset_open_reply(dev, rq);
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			break;
++		}
++	case AR6000_XIOCTL_WMI_DSET_DATA_REPLY:
++		{
++			AR6000_SPIN_LOCK(&ar->arLock, 0);
++			ar6k_ioctl_dset_data_reply(dev, rq);
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			break;
++		}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++	case AR6000_XIOCTL_FORCE_TARGET_RESET:
++		{
++			if (htcTarget) {
++//                HTCForceReset(htcTarget);
++			} else {
++				AR_DEBUG_PRINTF("ar6k_ioctl cannot attempt reset.\n");
++			}
++			break;
++		}
++	case AR6000_XIOCTL_CHECK_TARGET_READY:
++		{
++			/* If we made it to here, then the Target exists and is ready.
++			 */
++			break;
++		}
++#if CONFIG_HOST_GPIO_SUPPORT
++	case AR6000_XIOCTL_GPIO_OUTPUT_SET:
++		{
++			struct ar6k_gpio_output_set_cmd_s gpio_output_set_cmd;
++
++			if (ar->arWmiReady == FALSE) {
++				return -EIO;
++			}
++			if (down_interruptible(&ar->arSem)) {
++				return -ERESTARTSYS;
++			}
++
++			if (copy_from_user(&gpio_output_set_cmd, userdata,
++							   sizeof(gpio_output_set_cmd))) {
++				ret = -EFAULT;
++			} else {
++				ret = ar6k_gpio_output_set(dev,
++											 gpio_output_set_cmd.set_mask,
++											 gpio_output_set_cmd.
++											 clear_mask,
++											 gpio_output_set_cmd.
++											 enable_mask,
++											 gpio_output_set_cmd.
++											 disable_mask);
++				if (ret != A_OK) {
++					ret = EIO;
++				}
++			}
++			up(&ar->arSem);
++			break;
++		}
++	case AR6000_XIOCTL_GPIO_INPUT_GET:
++		{
++			if (ar->arWmiReady == FALSE) {
++				return -EIO;
++			}
++			if (down_interruptible(&ar->arSem)) {
++				return -ERESTARTSYS;
++			}
++
++			ret = ar6k_gpio_input_get(dev);
++			if (ret != A_OK) {
++				up(&ar->arSem);
++				return -EIO;
++			}
++
++			/* Wait for Target to respond. */
++			wait_event_interruptible(arEvent, gpio_data_available);
++			if (signal_pending(current)) {
++				ret = -EINTR;
++			} else {
++				A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
++
++				if (copy_to_user(userdata, &gpio_reg_results.value,
++								 sizeof(gpio_reg_results.value))) {
++					ret = -EFAULT;
++				}
++			}
++			up(&ar->arSem);
++			break;
++		}
++	case AR6000_XIOCTL_GPIO_REGISTER_SET:
++		{
++			struct ar6k_gpio_register_cmd_s gpio_register_cmd;
++
++			if (ar->arWmiReady == FALSE) {
++				return -EIO;
++			}
++			if (down_interruptible(&ar->arSem)) {
++				return -ERESTARTSYS;
++			}
++
++			if (copy_from_user(&gpio_register_cmd, userdata,
++							   sizeof(gpio_register_cmd))) {
++				ret = -EFAULT;
++			} else {
++				ret = ar6k_gpio_register_set(dev,
++											   gpio_register_cmd.
++											   gpioreg_id,
++											   gpio_register_cmd.value);
++				if (ret != A_OK) {
++					ret = EIO;
++				}
++
++				/* Wait for acknowledgement from Target */
++				wait_event_interruptible(arEvent, gpio_ack_received);
++				if (signal_pending(current)) {
++					ret = -EINTR;
++				}
++			}
++			up(&ar->arSem);
++			break;
++		}
++	case AR6000_XIOCTL_GPIO_REGISTER_GET:
++		{
++			struct ar6k_gpio_register_cmd_s gpio_register_cmd;
++
++			if (ar->arWmiReady == FALSE) {
++				return -EIO;
++			}
++			if (down_interruptible(&ar->arSem)) {
++				return -ERESTARTSYS;
++			}
++
++			if (copy_from_user(&gpio_register_cmd, userdata,
++							   sizeof(gpio_register_cmd))) {
++				ret = -EFAULT;
++			} else {
++				ret =
++					ar6k_gpio_register_get(dev,
++											 gpio_register_cmd.gpioreg_id);
++				if (ret != A_OK) {
++					up(&ar->arSem);
++					return -EIO;
++				}
++
++				/* Wait for Target to respond. */
++				wait_event_interruptible(arEvent, gpio_data_available);
++				if (signal_pending(current)) {
++					ret = -EINTR;
++				} else {
++					A_ASSERT(gpio_register_cmd.gpioreg_id ==
++							 gpio_reg_results.gpioreg_id);
++					if (copy_to_user
++						(userdata, &gpio_reg_results,
++						 sizeof(gpio_reg_results))) {
++						ret = -EFAULT;
++					}
++				}
++			}
++			up(&ar->arSem);
++			break;
++		}
++	case AR6000_XIOCTL_GPIO_INTR_ACK:
++		{
++			struct ar6k_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
++
++			if (ar->arWmiReady == FALSE) {
++				return -EIO;
++			}
++			if (down_interruptible(&ar->arSem)) {
++				return -ERESTARTSYS;
++			}
++
++			if (copy_from_user(&gpio_intr_ack_cmd, userdata,
++							   sizeof(gpio_intr_ack_cmd))) {
++				ret = -EFAULT;
++			} else {
++				ret =
++					ar6k_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
++				if (ret != A_OK) {
++					ret = EIO;
++				}
++			}
++			up(&ar->arSem);
++			break;
++		}
++	case AR6000_XIOCTL_GPIO_INTR_WAIT:
++		{
++			/* Wait for Target to report an interrupt. */
++			dev_hold(dev);
++			rtnl_unlock();
++			wait_event_interruptible(arEvent, gpio_intr_available);
++			rtnl_lock();
++			dev_put(dev);
++
++			if (signal_pending(current)) {
++				ret = -EINTR;
++			} else {
++				if (copy_to_user(userdata, &gpio_intr_results,
++								 sizeof(gpio_intr_results))) {
++					ret = -EFAULT;
++				}
++			}
++			break;
++		}
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++	case AR6000_XIOCTL_SET_ADHOC_BSSID:
++		{
++			WMI_SET_ADHOC_BSSID_CMD adhocBssid;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&adhocBssid, userdata,
++									  sizeof(adhocBssid))) {
++				ret = -EFAULT;
++			} else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
++								AR6000_ETH_ADDR_LEN) == 0) {
++				ret = -EFAULT;
++			} else {
++
++				A_MEMCPY(ar->arReqBssid, adhocBssid.bssid,
++						 sizeof(ar->arReqBssid));
++			}
++			break;
++		}
++
++	case AR6000_XIOCTL_SET_OPT_MODE:
++		{
++			WMI_SET_OPT_MODE_CMD optModeCmd;
++			AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&optModeCmd, userdata,
++									  sizeof(optModeCmd))) {
++				ret = -EFAULT;
++			} else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
++				ret = -EFAULT;
++
++			} else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
++					   != A_OK) {
++				ret = -EIO;
++			}
++			break;
++		}
++
++	case AR6000_XIOCTL_OPT_SEND_FRAME:
++		{
++			WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
++			u8 data[MAX_OPT_DATA_LEN];
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&optTxFrmCmd, userdata,
++									  sizeof(optTxFrmCmd))) {
++				ret = -EFAULT;
++			} else if (copy_from_user(data,
++									  optTxFrmCmd.optIEData,
++									  optTxFrmCmd.optIEDataLen)) {
++				ret = -EFAULT;
++			} else {
++				ret = wmi_opt_tx_frame_cmd(ar->arWmi,
++										   optTxFrmCmd.frmType,
++										   optTxFrmCmd.dstAddr,
++										   optTxFrmCmd.bssid,
++										   optTxFrmCmd.optIEDataLen, data);
++			}
++
++			break;
++		}
++
++	case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL:
++		{
++			WMI_BEACON_INT_CMD bIntvlCmd;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&bIntvlCmd, userdata,
++									  sizeof(bIntvlCmd))) {
++				ret = -EFAULT;
++			} else
++				if (wmi_set_adhoc_bconIntvl_cmd
++					(ar->arWmi, bIntvlCmd.beaconInterval)
++					!= A_OK) {
++				ret = -EIO;
++			}
++			break;
++		}
++	case IEEE80211_IOCTL_SETAUTHALG:
++		{
++			AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++			struct ieee80211req_authalg req;
++
++			if (ar->arWmiReady == FALSE) {
++				ret = -EIO;
++			} else if (copy_from_user(&req, userdata,
++									  sizeof(struct ieee80211req_authalg)))
++			{
++				ret = -EFAULT;
++			} else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) {
++				ar->arDot11AuthMode = OPEN_AUTH;
++				ar->arPairwiseCrypto = NONE_CRYPT;
++				ar->arGroupCrypto = NONE_CRYPT;
++			} else if (req.auth_alg == AUTH_ALG_LEAP) {
++				ar->arDot11AuthMode = LEAP_AUTH;
++			} else {
++				ret = -EIO;
++			}
++			break;
++		}
++
++	case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
++		ret = ar6k_xioctl_set_voice_pkt_size(dev, userdata);
++		break;
++
++	case AR6000_XIOCTL_SET_MAX_SP:
++		ret = ar6k_xioctl_set_max_sp_len(dev, userdata);
++		break;
++
++	case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
++		ret = ar6k_ioctl_get_roam_tbl(dev, rq);
++		break;
++	case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
++		ret = ar6k_ioctl_set_roam_ctrl(dev, userdata);
++		break;
++	case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
++		ret = ar6k_ioctl_set_powersave_timers(dev, userdata);
++		break;
++	case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
++		ret = ar6k_ioctl_get_power_mode(dev, rq);
++		break;
++	case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
++		get_user(ar->arWlanState, (unsigned int *) userdata);
++		if (ar->arWmiReady == FALSE) {
++			ret = -EIO;
++			break;
++		}
++
++		if (ar->arWlanState == WLAN_ENABLED) {
++			/* Enable foreground scanning */
++			AR6000_SPIN_LOCK(&ar->arLock, 0);
++			if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
++								   scParams.fg_end_period,
++								   scParams.bg_period,
++								   scParams.act_chdwell_time,
++								   scParams.pas_chdwell_time,
++								   scParams.shortScanRatio) != A_OK) {
++				ret = -EIO;
++			}
++			if (ar->arSsidLen) {
++				if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
++									ar->arDot11AuthMode, ar->arAuthMode,
++									ar->arPairwiseCrypto,
++									ar->arPairwiseCryptoLen,
++									ar->arGroupCrypto,
++									ar->arGroupCryptoLen, ar->arSsidLen,
++									ar->arSsid, ar->arReqBssid,
++									ar->arChannelHint) != A_OK) {
++					ret = -EIO;
++				} else {
++					ar->arConnectPending = TRUE;
++				}
++			}
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		} else {
++			/* Disconnect from the AP and disable foreground scanning */
++			AR6000_SPIN_LOCK(&ar->arLock, 0);
++			if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
++				wmi_disconnect_cmd(ar->arWmi);
++			}
++			if (wmi_scanparams_cmd(ar->arWmi, 65535, 0, 0, 0, 0, 0) !=
++				A_OK) {
++				ret = -EIO;
++			}
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		}
++		break;
++	case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
++		ret = ar6k_ioctl_get_roam_data(dev, rq);
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++	}
++	return ret;
++}
++
++void ar6k_bitrate_rx(void *devt, s32 rateKbps)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++
++	ar->arBitRate = rateKbps;
++	wake_up(&arEvent);
++}
++
++void ar6k_txPwr_rx(void *devt, u8 txPwr)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++
++	ar->arTxPwr = txPwr;
++	wake_up(&arEvent);
++}
++
++static int
++ar6k_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	if (cmd.numChannels > 1) {
++		cmdp = A_MALLOC(128);
++		if (copy_from_user(cmdp, rq->ifr_data,
++						   sizeof(*cmdp) +
++						   ((cmd.numChannels - 1) * sizeof(u16)))) {
++			kfree(cmdp);
++			return -EFAULT;
++		}
++	} else {
++		cmdp = &cmd;
++	}
++
++	if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
++		((cmdp->phyMode == WMI_11A_MODE)
++		 || (cmdp->phyMode == WMI_11AG_MODE))) {
++		ret = -EINVAL;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (!ret &&
++		(wmi_set_channelParams_cmd
++		 (ar->arWmi, cmdp->phyMode, cmdp->numChannels,
++		  cmdp->channelList) != A_OK)) {
++		ret = -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	if (cmd.numChannels > 1) {
++		kfree(cmdp);
++	}
++
++	return ret;
++}
++
++static int
++ar6k_ioctl_set_link_threshold(struct net_device *dev, struct ifreq *rq)
++{
++
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_set_link_threshold_params(ar->arWmi,
++									  cmd.highThreshold_upperVal,
++									  cmd.highThreshold_lowerVal,
++									  cmd.lowThreshold_upperVal,
++									  cmd.lowThreshold_lowerVal,
++									  cmd.pollTime) != A_OK) {
++		ret = -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return ret;
++}
++
++void ar6k_channelList_rx(void *devt, char numChan, u16 * chanList)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++
++	A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof(u16));
++	ar->arNumChannels = numChan;
++
++	wake_up(&arEvent);
++}
++
++static int
++ar6k_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_PROBED_SSID_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_probedSsid_cmd
++		(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
++		 cmd.ssid) != A_OK) {
++		ret = -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return ret;
++}
++
++static int ar6k_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_ADD_BAD_AP_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
++		return -EIO;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
++		/*
++		 * This is a delete badAP.
++		 */
++		if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
++			ret = -EIO;
++		}
++	} else {
++		if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
++			ret = -EIO;
++		}
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return ret;
++}
++
++static int
++ar6k_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_CREATE_PSTREAM_CMD cmd;
++	int ret;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	cmd.rxQueueNum = 0xFF;
++	ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
++	if (ret == A_OK)
++		ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	switch (ret) {
++	case A_OK:
++		return 0;
++	case A_EBUSY:
++		return -EBUSY;
++	case A_NO_MEMORY:
++		return -ENOMEM;
++	case A_EINVAL:
++	default:
++		return -EFAULT;
++	}
++}
++
++static int
++ar6k_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_DELETE_PSTREAM_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.txQueueNumber,
++								 cmd.rxQueueNumber, cmd.trafficDirection);
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	switch (ret) {
++	case A_OK:
++		return 0;
++	case A_EBUSY:
++		return -EBUSY;
++	case A_NO_MEMORY:
++		return -ENOMEM;
++	case A_EINVAL:
++	default:
++		return -EFAULT;
++	}
++}
++
++static int
++ar6k_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ar6k_queuereq qreq;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	copy_from_user(&qreq, rq->ifr_data, sizeof(struct ar6k_queuereq));
++
++	qreq.queueNumber = wmi_get_mapped_qos_queue(ar->arWmi,
++												qreq.trafficDirection,
++												qreq.trafficClass);
++
++	if (copy_to_user(rq->ifr_data, &qreq, sizeof(struct ar6k_queuereq))) {
++		ret = -EFAULT;
++	}
++	return ret;
++}
++
++#ifdef HTC_RAW_INTERFACE
++#define RAW_HTC_READ_BUFFERS_NUM                     16
++#define RAW_HTC_WRITE_BUFFERS_NUM                    16
++typedef struct {
++	int currPtr;
++	int length;
++	unsigned char data[AR6000_BUFFER_SIZE];
++} raw_htc_buffer;
++
++static struct semaphore raw_htc_read_sem[HTC_MAILBOX_NUM_MAX];
++static struct semaphore raw_htc_write_sem[HTC_MAILBOX_NUM_MAX];
++static wait_queue_head_t raw_htc_read_queue[HTC_MAILBOX_NUM_MAX];
++static wait_queue_head_t raw_htc_write_queue[HTC_MAILBOX_NUM_MAX];
++static raw_htc_buffer
++	raw_htc_read_buffer[HTC_MAILBOX_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
++static raw_htc_buffer
++	raw_htc_write_buffer[HTC_MAILBOX_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
++static u8 write_buffer_available[HTC_MAILBOX_NUM_MAX];
++static u8 read_buffer_available[HTC_MAILBOX_NUM_MAX];
++
++static void
++ar6k_htc_raw_read_cb(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID endPointId,
++					   HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo,
++					   void *arg)
++{
++	HTC_TARGET *target;
++	raw_htc_buffer *busy;
++
++	target = (HTC_TARGET *) arg;
++	A_ASSERT(target != NULL);
++	busy = (raw_htc_buffer *) evInfo->cookie;
++	A_ASSERT(busy != NULL);
++
++	if (evInfo->status == A_ECANCELED) {
++		/*
++		 * HTC provides A_ECANCELED status when it doesn't want to be refilled
++		 * (probably due to a shutdown)
++		 */
++		memset(busy, 0, sizeof(raw_htc_buffer));
++		return;
++	}
++#ifdef CF
++	if (down_trylock(&raw_htc_read_sem[endPointId])) {
++#else
++	if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++#endif							/* CF */
++		AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
++	}
++
++	A_ASSERT(evId == HTC_BUFFER_RECEIVED);
++	A_ASSERT((evInfo->status != A_OK) ||
++			 (evInfo->buffer == (busy->data + HTC_HEADER_LEN)));
++
++	busy->length = evInfo->actualLength + HTC_HEADER_LEN;
++	busy->currPtr = HTC_HEADER_LEN;
++	read_buffer_available[endPointId] = TRUE;
++	up(&raw_htc_read_sem[endPointId]);
++
++	/* Signal the waiting process */
++	AR_DEBUG2_PRINTF("Waking up the endpoint(%d) read process\n",
++					 endPointId);
++	wake_up_interruptible(&raw_htc_read_queue[endPointId]);
++}
++
++static void
++ar6k_htc_raw_write_cb(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID endPointId,
++						HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo,
++						void *arg)
++{
++	HTC_TARGET *target;
++	raw_htc_buffer *free;
++
++	target = (HTC_TARGET *) arg;
++	A_ASSERT(target != NULL);
++	free = (raw_htc_buffer *) evInfo->cookie;
++	A_ASSERT(free != NULL);
++
++	if (evInfo->status == A_ECANCELED) {
++		/*
++		 * HTC provides A_ECANCELED status when it doesn't want to be refilled
++		 * (probably due to a shutdown)
++		 */
++		memset(free, 0, sizeof(raw_htc_buffer));
++		return;
++	}
++#ifdef CF
++	if (down_trylock(&raw_htc_write_sem[endPointId])) {
++#else
++	if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++#endif							/* CF */
++		AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
++	}
++
++	A_ASSERT(evId == HTC_BUFFER_SENT);
++	A_ASSERT(evInfo->buffer == (free->data + HTC_HEADER_LEN));
++
++	free->length = 0;
++	write_buffer_available[endPointId] = TRUE;
++	up(&raw_htc_write_sem[endPointId]);
++
++	/* Signal the waiting process */
++	AR_DEBUG2_PRINTF("Waking up the endpoint(%d) write process\n",
++					 endPointId);
++	wake_up_interruptible(&raw_htc_write_queue[endPointId]);
++}
++
++static void
++ar6k_htc_raw_unread_cb(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++						 HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo,
++						 void *arg)
++{
++	HTC_TARGET *target;
++
++	target = (HTC_TARGET *) arg;
++	A_ASSERT(target != NULL);
++
++	AR_DEBUG_PRINTF("Not implemented\n");
++}
++
++static int ar6k_htc_raw_open(HTC_TARGET * htcTarget)
++{
++	int status;
++	int count1, count2;
++	raw_htc_buffer *buffer;
++
++	for (count1 = 0; count1 < HTC_MAILBOX_NUM_MAX; count1++) {
++		/* Initialize the data structures */
++		init_MUTEX(&raw_htc_read_sem[count1]);
++		init_MUTEX(&raw_htc_write_sem[count1]);
++		init_waitqueue_head(&raw_htc_read_queue[count1]);
++		init_waitqueue_head(&raw_htc_write_queue[count1]);
++
++		/* Register the event handlers */
++		if ((status = HTCEventReg(htcTarget, count1, HTC_BUFFER_RECEIVED,
++								  ar6k_htc_raw_read_cb,
++								  htcTarget)) != A_OK) {
++			BMIInit();
++			return -EIO;
++		}
++		if ((status = HTCEventReg(htcTarget, count1, HTC_DATA_AVAILABLE,
++								  ar6k_htc_raw_unread_cb,
++								  htcTarget)) != A_OK) {
++			BMIInit();
++			return -EIO;
++		}
++		if ((status = HTCEventReg(htcTarget, count1, HTC_BUFFER_SENT,
++								  ar6k_htc_raw_write_cb,
++								  htcTarget)) != A_OK) {
++			BMIInit();
++			return -EIO;
++		}
++
++		for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2++) {
++			/* Initialize the receive buffers */
++			buffer = &raw_htc_write_buffer[count1][count2];
++			memset(buffer, 0, sizeof(raw_htc_buffer));
++			buffer = &raw_htc_read_buffer[count1][count2];
++			memset(buffer, 0, sizeof(raw_htc_buffer));
++
++			/* Queue buffers to HTC for receive */
++			if ((status = HTCBufferReceive(htcTarget, count1, buffer->data,
++										   AR6000_BUFFER_SIZE,
++										   buffer)) != A_OK) {
++				BMIInit();
++				return -EIO;
++			}
++		}
++
++		for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2++) {
++			/* Initialize the receive buffers */
++			buffer = &raw_htc_write_buffer[count1][count2];
++			memset(buffer, 0, sizeof(raw_htc_buffer));
++		}
++
++		read_buffer_available[count1] = FALSE;
++		write_buffer_available[count1] = TRUE;
++	}
++
++	/* Start the HTC component */
++	if ((status = HTCStart(htcTarget)) != A_OK) {
++		BMIInit();
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int ar6k_htc_raw_close(HTC_TARGET * htcTarget)
++{
++	int count;
++	int status;
++
++	/* Stop the HTC */
++	HTCStop(htcTarget);
++
++	/* Unregister the event handlers */
++	for (count = 0; count < HTC_MAILBOX_NUM_MAX; count++) {
++		status = HTCEventReg(htcTarget, count, HTC_BUFFER_RECEIVED,
++							 NULL, htcTarget);
++
++		status = HTCEventReg(htcTarget, count, HTC_DATA_AVAILABLE,
++							 NULL, htcTarget);
++
++		status = HTCEventReg(htcTarget, count, HTC_BUFFER_SENT,
++							 NULL, htcTarget);
++	}
++
++	/* Initialize the BMI component */
++	BMIInit();
++
++	return 0;
++}
++
++raw_htc_buffer *get_filled_buffer(HTC_ENDPOINT_ID endPointId)
++{
++	int count;
++	raw_htc_buffer *busy;
++
++	/* Check for data */
++	for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count++) {
++		busy = &raw_htc_read_buffer[endPointId][count];
++		if (busy->length) {
++			break;
++		}
++	}
++	if (busy->length) {
++		read_buffer_available[endPointId] = TRUE;
++	} else {
++		read_buffer_available[endPointId] = FALSE;
++	}
++
++	return busy;
++}
++
++static ssize_t
++ar6k_htc_raw_read(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID endPointId,
++					char __user * buffer, size_t length)
++{
++	int readPtr;
++	raw_htc_buffer *busy;
++
++	if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++		return -ERESTARTSYS;
++	}
++
++	busy = get_filled_buffer(endPointId);
++	while (!read_buffer_available[endPointId]) {
++		up(&raw_htc_read_sem[endPointId]);
++
++		/* Wait for the data */
++		AR_DEBUG2_PRINTF("Sleeping endpoint(%d) read process\n",
++						 endPointId);
++		if (wait_event_interruptible
++			(raw_htc_read_queue[endPointId],
++			 read_buffer_available[endPointId])) {
++			return -EINTR;
++		}
++		if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++			return -ERESTARTSYS;
++		}
++		busy = get_filled_buffer(endPointId);
++	}
++
++	/* Read the data */
++	readPtr = busy->currPtr;
++	if (length > busy->length - HTC_HEADER_LEN) {
++		length = busy->length - HTC_HEADER_LEN;
++	}
++	if (copy_to_user(buffer, &busy->data[readPtr], length)) {
++		up(&raw_htc_read_sem[endPointId]);
++		return -EFAULT;
++	}
++
++	busy->currPtr += length;
++	if (busy->currPtr == busy->length) {
++		/* Packet has been completely read. Queue it with HTC */
++		memset(busy, 0, sizeof(raw_htc_buffer));
++		HTCBufferReceive(htcTarget, endPointId, busy->data,
++						 AR6000_BUFFER_SIZE, busy);
++	}
++	read_buffer_available[endPointId] = FALSE;
++	up(&raw_htc_read_sem[endPointId]);
++
++	return length;
++}
++
++raw_htc_buffer *get_free_buffer(HTC_ENDPOINT_ID endPointId)
++{
++	int count;
++	raw_htc_buffer *free;
++
++	free = NULL;
++	for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count++) {
++		free = &raw_htc_write_buffer[endPointId][count];
++		if (free->length == 0) {
++			break;
++		}
++	}
++	if (!free->length) {
++		write_buffer_available[endPointId] = TRUE;
++	} else {
++		write_buffer_available[endPointId] = FALSE;
++	}
++
++	return free;
++}
++
++static ssize_t
++ar6k_htc_raw_write(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID endPointId,
++					 char __user * buffer, size_t length)
++{
++	int writePtr;
++	raw_htc_buffer *free;
++
++	if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++		return -ERESTARTSYS;
++	}
++
++	/* Search for a free buffer */
++	free = get_free_buffer(endPointId);
++
++	/* Check if there is space to write else wait */
++	while (!write_buffer_available[endPointId]) {
++		up(&raw_htc_write_sem[endPointId]);
++
++		/* Wait for buffer to become free */
++		AR_DEBUG2_PRINTF("Sleeping endpoint(%d) write process\n",
++						 endPointId);
++		if (wait_event_interruptible
++			(raw_htc_write_queue[endPointId],
++			 write_buffer_available[endPointId])) {
++			return -EINTR;
++		}
++		if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++			return -ERESTARTSYS;
++		}
++		free = get_free_buffer(endPointId);
++	}
++
++	/* Send the data */
++	writePtr = HTC_HEADER_LEN;
++	if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) {
++		length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN;
++	}
++
++	if (copy_from_user(&free->data[writePtr], buffer, length)) {
++		up(&raw_htc_read_sem[endPointId]);
++		return -EFAULT;
++	}
++
++	free->length = length;
++	HTCBufferSend(htcTarget, endPointId, &free->data[writePtr], length,
++				  free);
++	write_buffer_available[endPointId] = FALSE;
++	up(&raw_htc_write_sem[endPointId]);
++
++	return length;
++}
++#endif							/* HTC_RAW_INTERFACE */
++
++/*
++ * As soon as the DataSet Server application waits for a request,
++ * we know that the server is operational, and we try to process
++ * requests.  If the Target sends any requests before the server
++ * has started, we reject the request.  The model we use is that
++ * once started, the server must continue to service requests as
++ * long as they may arrive, and the server ought to be started
++ * before WMI is started (before the network interface is brought
++ * up.
++ */
++static u8 dset_server_alive;
++
++#if CONFIG_HOST_DSET_SUPPORT
++/*
++ * For now, we allow for just one outstanding (unhandled) request
++ * at a time.  The current Target doesn't need any more than that.
++ * If we ever need to handle many simultaneous requests, this
++ * pending_dset_request and pending_dset_request_valid mechanism
++ * can get more complicated.  The use of dset_request_lock is
++ * also very simple; it assumes that a single well-behaved thread
++ * serves all requests.
++ */
++static u8 pending_dset_request_valid;
++static dset_request_t pending_dset_request;
++
++static spinlock_t dset_request_lock;
++static DECLARE_WAIT_QUEUE_HEAD(dset_request);
++
++static int
++ar6k_ioctl_wait_dset_req(struct net_device *dev, struct ifreq *rq)
++{
++	int ret = 0;
++
++	dset_server_alive = TRUE;
++
++	/* Wait for a DataSet Request to arrive. */
++	dev_hold(dev);
++	rtnl_unlock();
++	wait_event_interruptible(dset_request, pending_dset_request_valid);
++	rtnl_lock();
++	dev_put(dev);
++
++	if (signal_pending(current)) {
++		ret = -EINTR;
++	} else {
++		if (copy_to_user(rq->ifr_data,
++						 &pending_dset_request,
++						 sizeof(pending_dset_request))) {
++			ret = -EFAULT;
++		}
++
++		/* pending_dset_request is now available for use */
++		pending_dset_request_valid = FALSE;
++		spin_unlock(&dset_request_lock);
++	}
++
++	return ret;
++}
++
++static int
++ar6k_ioctl_dset_open_reply(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int ret = 0;
++	dset_open_reply_t dset_reply;
++
++	if (copy_from_user(&dset_reply, rq->ifr_data, sizeof(dset_reply))) {
++		ret = -EFAULT;
++	} else {
++		A_ASSERT(dset_reply.cmd == AR6000_XIOCTL_WMI_DSET_OPEN_REPLY);
++		ret = wmi_dset_open_reply(ar->arWmi,
++								  dset_reply.status,
++								  dset_reply.access_cookie,
++								  dset_reply.size,
++								  dset_reply.version,
++								  dset_reply.targ_handle,
++								  dset_reply.targ_reply_fn,
++								  dset_reply.targ_reply_arg);
++
++		if (ret == A_NO_MEMORY) {
++			ret = -ENOMEM;
++		} else if (ret == A_ERROR) {
++			ret = -EFAULT;
++		}
++	}
++
++	return ret;
++}
++
++static int
++ar6k_ioctl_dset_data_reply(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int ret = 0;
++	dset_data_reply_t dset_reply;
++
++	if (copy_from_user(&dset_reply, rq->ifr_data, sizeof(dset_reply))) {
++		ret = -EFAULT;
++	} else {
++		A_ASSERT(dset_reply.cmd == AR6000_XIOCTL_WMI_DSET_DATA_REPLY);
++		ret = wmi_dset_data_reply(ar->arWmi,
++								  dset_reply.status,
++								  dset_reply.buf,
++								  dset_reply.length,
++								  dset_reply.targ_buf,
++								  dset_reply.targ_reply_fn,
++								  dset_reply.targ_reply_arg);
++
++		if (ret == A_NO_MEMORY) {
++			ret = -ENOMEM;
++		} else if (ret == A_ERROR) {
++			ret = -EFAULT;
++		}
++	}
++
++	return ret;
++}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++u8 ar6k_ibss_map_epid(struct sk_buff * skb, struct net_device * dev,
++						u32 * mapNo)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	u8 *datap;
++	ATH_MAC_HDR *macHdr;
++	u32 i, emptMap;
++
++	(*mapNo) = 0;
++	datap = skb->data;
++	macHdr = (ATH_MAC_HDR *) (datap + sizeof(WMI_DATA_HDR));
++	if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
++		return ENDPOINT3;
++	}
++
++	emptMap = -1;
++	for (i = 0; i < ar->arNodeNum; i++) {
++		if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
++			(*mapNo) = i + 1;
++			ar->arNodeMap[i].txPending++;
++			return ar->arNodeMap[i].epId;
++		}
++
++		if ((emptMap == -1) && !ar->arNodeMap[i].txPending) {
++			emptMap = i;
++		}
++	}
++
++	if (emptMap == -1) {
++		emptMap = ar->arNodeNum;
++		ar->arNodeNum++;
++		A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
++	}
++
++	A_MEMCPY(ar->arNodeMap[emptMap].macAddress, macHdr->dstMac,
++			 IEEE80211_ADDR_LEN);
++
++	for (i = ENDPOINT2; i <= ENDPOINT4; i++) {
++		if (!ar->arTxPending[i]) {
++			ar->arNodeMap[emptMap].epId = i;
++			break;
++		}
++	}
++
++	if (i > ENDPOINT4) {
++		ar->arNodeMap[emptMap].epId = ar->arNexEpId;
++		ar->arNexEpId++;
++		if (ar->arNexEpId > ENDPOINT4) {
++			ar->arNexEpId = ENDPOINT2;
++		}
++	}
++
++	(*mapNo) = emptMap + 1;
++	ar->arNodeMap[emptMap].txPending++;
++
++	return ar->arNodeMap[ar->arNodeNum - 1].epId;
++}
++
++static int ar6k_data_tx(struct sk_buff *skb, struct net_device *dev)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	HTC_ENDPOINT_ID endPointId;
++	u32 mapNo = 0;
++	struct iphdr *ipHdr;
++	struct sk_buff *newbuf;
++	int len;
++	struct ar_cookie *cookie;
++
++	if (ar->arWmiReady == FALSE && bypasswmi == 0) {
++		dev_kfree_skb(skb);
++		return 0;
++	}
++#ifdef BLOCK_TX_PATH_FLAG
++	if (blocktx) {
++		dev_kfree_skb(skb);
++		return 0;
++	}
++#endif							/* BLOCK_TX_PATH_FLAG */
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	/* If all data queues are full, notify upper layer to stop. */
++	if (ar->arTotalTxDataPending >=
++		(txFlowCtrlThresh[ar->arNumDataEndPts])) {
++		netif_stop_queue(ar->arNetDev);
++	}
++
++	AR_DEBUG2_PRINTF
++		("ar6k_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
++		 (u32) skb, (u32) skb->data, skb->len);
++
++	if (ar->arWmiEnabled == TRUE) {
++		if (skb_headroom(skb) < dev->hard_header_len) {
++			/*
++			 * We really should have gotten enough headroom but sometimes
++			 * we still get packets with not enough headroom.  Copy the packet.
++			 */
++			len = skb->len;
++			newbuf = ar6k_alloc_skb(len);
++			if (newbuf == NULL) {
++				dev_kfree_skb(skb);
++				AR6000_STAT_INC(ar, tx_dropped);
++				AR6000_STAT_INC(ar, tx_aborted_errors);
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++				return A_NO_MEMORY;
++			}
++			skb_put(newbuf, len);
++			A_MEMCPY(newbuf->data, skb->data, len);
++			dev_kfree_skb(skb);
++			skb = newbuf;
++		}
++		if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
++			AR_DEBUG_PRINTF("ar6k_data_tx - wmi_dix_2_dot3 failed\n");
++			AR6000_STAT_INC(ar, tx_dropped);
++			AR6000_STAT_INC(ar, tx_aborted_errors);
++			dev_kfree_skb(skb);
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			return 0;
++		}
++
++		if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) {
++			AR_DEBUG_PRINTF("ar6k_data_tx - wmi_data_hdr_add failed\n");
++			AR6000_STAT_INC(ar, tx_dropped);
++			AR6000_STAT_INC(ar, tx_aborted_errors);
++			dev_kfree_skb(skb);
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			return 0;
++		}
++
++		if ((ar->arNetworkType == ADHOC_NETWORK) &&
++			ar->arIbssPsEnable && ar->arConnected) {
++			endPointId = ar6k_ibss_map_epid(skb, dev, &mapNo);
++		} else {
++			/* Extract the end point information */
++			endPointId = wmi_get_endpoint(ar->arWmi,
++										  wmi_implicit_create_pstream(ar->
++																	  arWmi,
++																	  skb,
++																	  UPLINK_TRAFFIC));
++		}
++	} else {
++		/*
++		 * the endpoint is directly based on the TOS field in the IP
++		 * header
++		 */
++		ipHdr = (struct iphdr *) (skb->data + sizeof(ATH_MAC_HDR));
++		endPointId = ((ipHdr->tos >> 1) & 0x03);
++	}
++
++	AR_DEBUG2_PRINTF
++		("ar6k_data_tx - ep=%d skb=0x%x, data=0x%x, len=0x%x\n",
++		 endPointId, (u32) skb, (u32) skb->data, skb->len);
++
++	ar->arTxPending[endPointId]++;
++	ar->arTotalTxDataPending++;
++
++	/* If the particular data queue is full, silently drop the pkt. */
++	if (ar->arTxPending[endPointId] > MAX_ALLOWED_TXQ_DEPTH) {
++		ar->arTxPending[endPointId]--;
++		ar->arTotalTxDataPending--;
++		dev_kfree_skb(skb);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return 0;
++	}
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	cookie = ar6k_alloc_cookie(ar);
++	if (cookie == NULL) {
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		ar->arTxPending[endPointId]--;
++		ar->arTotalTxDataPending--;
++		dev_kfree_skb(skb);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return 0;
++	}
++
++	cookie->arc_bp[0] = (u32) skb;
++	cookie->arc_bp[1] = mapNo;
++
++	if (HTCBufferSend(ar->arHtcTarget, endPointId, skb->data,
++					  skb->len, cookie) != A_OK) {
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		ar->arTxPending[endPointId]--;
++		ar->arTotalTxDataPending--;
++		AR_DEBUG_PRINTF("Dropping the frame\n");
++		ar6k_free_cookie(ar, cookie);
++		dev_kfree_skb(skb);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	}
++
++	return 0;
++}
++
++static void
++ar6k_tx_complete(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++				   HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo, void *arg)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) arg;
++	void *cookie = (void *) evInfo->cookie;
++	struct sk_buff *skb = NULL;
++	u32 mapNo = 0;
++
++	if (ar->arWmiReady == TRUE || bypasswmi != 0) {
++		struct ar_cookie *ar_cookie = (struct ar_cookie *) cookie;
++		skb = (struct sk_buff *) ar_cookie->arc_bp[0];
++		mapNo = ar_cookie->arc_bp[1];
++	} else {
++		skb = (struct sk_buff *) cookie;
++		AR_DEBUG_PRINTF("%s() WARNING Wierd cookie\n", __func__);
++	}
++
++	A_ASSERT(skb);
++	A_ASSERT(evId == HTC_BUFFER_SENT);
++	A_ASSERT(evInfo->buffer == skb->data);
++	if (evInfo->status != A_ECANCELED) {
++		A_ASSERT(evInfo->actualLength == skb->len);
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	ar->arTxPending[eid]--;
++	if (eid != WMI_CONTROL_MBOX || bypasswmi) {
++		ar->arTotalTxDataPending--;
++	}
++	AR_DEBUG2_PRINTF
++		("ar6k_tx_complete skb=0x%x data=0x%x len=0x%x mbox=%d ",
++		 (u32) skb, (u32) evInfo->buffer, evInfo->actualLength, eid);
++
++	if ((eid == WMI_CONTROL_MBOX) &&
++		(ar->arTxPending[WMI_CONTROL_MBOX] == 0)) {
++		wake_up(&arEvent);
++	}
++
++
++	if (evInfo->status != A_OK) {
++		AR_DEBUG_PRINTF("%s() -TX ERROR\n", __func__);
++		AR6000_STAT_INC(ar, tx_errors);
++	} else {
++		AR_DEBUG2_PRINTF("OK\n");
++		AR6000_STAT_INC(ar, tx_packets);
++		ar->arNetStats.tx_bytes += skb->len;
++	}
++
++	if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
++		&& (eid != WMI_CONTROL_MBOX) && mapNo) {
++		mapNo--;
++		ar->arNodeMap[mapNo].txPending--;
++
++		if (!ar->arNodeMap[mapNo].txPending
++			&& (mapNo == (ar->arNodeNum - 1))) {
++			u32 i;
++			for (i = ar->arNodeNum; i > 0; i--) {
++				if (!ar->arNodeMap[i - 1].txPending) {
++					A_MEMZERO(&ar->arNodeMap[i - 1],
++							  sizeof(struct ar_node_mapping));
++					ar->arNodeNum--;
++				} else {
++					break;
++				}
++			}
++		}
++	}
++
++	/* Freeing a cookie should not be contingent on either of */
++	/* these flags, just if we have a cookie or not.  */
++	/* Can we even get here without a cookie? Fix later.  */
++	if (ar->arWmiReady == TRUE || (bypasswmi)) {
++		ar6k_free_cookie(ar, cookie);
++	}
++
++	dev_kfree_skb(skb);
++
++	if ((ar->arConnected == TRUE) || (bypasswmi)) {
++		netif_wake_queue(ar->arNetDev);
++	}
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++}
++
++/*
++ * Receive event handler.  This is called by HTC when a packet is received
++ */
++int pktcount;
++static void
++ar6k_rx(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++		  HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo, void *arg)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) arg;
++	struct sk_buff *skb = (struct sk_buff *) evInfo->cookie;
++	int minHdrLen;
++
++	A_ASSERT(evId == HTC_BUFFER_RECEIVED);
++	A_ASSERT((evInfo->status != A_OK)
++			 || (evInfo->buffer == (skb->data + HTC_HEADER_LEN)));
++
++#ifdef DEBUG
++	AR_DEBUG2_PRINTF
++		("ar6k_rx ar=0x%x ep=%d, skb=0x%x, data=0x%x, len=0x%x ",
++		 (u32) ar, eid, (u32) skb, (u32) evInfo->buffer,
++		 evInfo->actualLength);
++	if (evInfo->status != A_OK) {
++		AR_DEBUG2_PRINTF("ERR\n");
++	} else {
++		AR_DEBUG2_PRINTF("OK\n");
++	}
++#endif							/* DEBUG */
++
++	ar->arRxBuffers[eid]--;
++	AR6000_STAT_INC(ar, rx_packets);
++	ar->arNetStats.rx_bytes += evInfo->actualLength;
++
++	skb_put(skb, evInfo->actualLength + HTC_HEADER_LEN);
++
++	skb_pull(skb, HTC_HEADER_LEN);
++
++	if (evInfo->status != A_OK) {
++		AR6000_STAT_INC(ar, rx_errors);
++		dev_kfree_skb(skb);
++	} else if (ar->arWmiEnabled == TRUE) {
++		if (eid == WMI_CONTROL_MBOX) {
++			/*
++			 * this is a wmi control msg
++			 */
++			AR6000_SPIN_LOCK(&ar->arLock, 0);
++			wmi_control_rx(ar->arWmi, skb);
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		} else {
++			WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *) skb->data;
++			if (WMI_DATA_HDR_IS_MSG_TYPE(dhdr, CNTL_MSGTYPE)) {
++				/*
++				 * this is a wmi control msg
++				 */
++				/* strip off WMI hdr */
++				wmi_data_hdr_remove(ar->arWmi, skb);
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				wmi_control_rx(ar->arWmi, skb);
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			} else {
++				/*
++				 * this is a wmi data packet
++				 */
++				minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
++					sizeof(ATH_LLC_SNAP_HDR);
++
++				if ((evInfo->actualLength < minHdrLen) ||
++					(evInfo->actualLength > AR6000_BUFFER_SIZE)) {
++					/*
++					 * packet is too short or too long
++					 */
++					AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n");
++					AR6000_STAT_INC(ar, rx_errors);
++					AR6000_STAT_INC(ar, rx_length_errors);
++					dev_kfree_skb(skb);
++				} else {
++					AR6000_SPIN_LOCK(&ar->arLock, 0);
++					wmi_implicit_create_pstream(ar->arWmi, skb,
++												DNLINK_TRAFFIC);
++					AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++#if 0
++					/* Access RSSI values here */
++					AR_DEBUG_PRINTF("RSSI %d\n",
++									((WMI_DATA_HDR *)
++									 skb->data)->rssi);
++#endif
++					wmi_data_hdr_remove(ar->arWmi, skb);
++					wmi_dot3_2_dix(ar->arWmi, skb);
++
++					if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
++						skb->dev = ar->arNetDev;
++						skb->protocol = eth_type_trans(skb, ar->arNetDev);
++						netif_rx(skb);
++					} else {
++						dev_kfree_skb(skb);
++					}
++				}
++			}
++		}
++	} else {
++		if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
++			skb->dev = ar->arNetDev;
++			skb->protocol = eth_type_trans(skb, ar->arNetDev);
++			netif_rx(skb);
++		} else {
++			dev_kfree_skb(skb);
++		}
++	}
++
++	if (evInfo->status != A_ECANCELED) {
++		/*
++		 * HTC provides A_ECANCELED status when it doesn't want to be refilled
++		 * (probably due to a shutdown)
++		 */
++		ar6k_rx_refill(htcTarget, eid, HTC_DATA_AVAILABLE, NULL, ar);
++	}
++}
++
++static void
++ar6k_rx_refill(HTC_TARGET * htcTarget, HTC_ENDPOINT_ID eid,
++				 HTC_EVENT_ID evId, HTC_EVENT_INFO * evInfo, void *arg)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) arg;
++	struct sk_buff *skb;
++	int arRxBuffers;
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	arRxBuffers = ar->arRxBuffers[eid];
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	AR_DEBUG2_PRINTF
++		("ar6k_rx_refill: providing htc with %d buffers at eid=%d\n",
++		 AR6000_MAX_RX_BUFFERS - arRxBuffers, eid);
++	while (arRxBuffers < AR6000_MAX_RX_BUFFERS) {
++		skb = ar6k_alloc_skb(AR6000_BUFFER_SIZE);
++		HTCBufferReceive(htcTarget, eid, skb->data,
++						 AR6000_BUFFER_SIZE, skb);
++		arRxBuffers++;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	ar->arRxBuffers[eid] = arRxBuffers;
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++}
++
++static struct net_device_stats *ar6k_get_stats(struct net_device *dev)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	return &ar->arNetStats;
++}
++
++#if 0
++static struct iw_statistics *ar6k_get_iwstats(struct net_device *dev)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	TARGET_STATS *pStats = &ar->arTargetStats;
++	struct iw_statistics *pIwStats = &ar->arIwStats;
++
++	if (ar->arWmiReady == FALSE) {
++		pIwStats->status = 0;
++		pIwStats->qual.qual = 0;
++		pIwStats->qual.level = 0;
++		pIwStats->qual.noise = 0;
++		pIwStats->discard.code = 0;
++		pIwStats->discard.retries = 0;
++		pIwStats->miss.beacon = 0;
++		return pIwStats;
++	}
++	if (down_interruptible(&ar->arSem)) {
++		pIwStats->status = 0;
++		return pIwStats;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	ar->statsUpdatePending = TRUE;
++
++	if (wmi_get_stats_cmd(ar->arWmi) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		up(&ar->arSem);
++		pIwStats->status = 0;
++		return pIwStats;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	wait_event_interruptible(arEvent, ar->statsUpdatePending == FALSE);
++
++	if (signal_pending(current)) {
++		pIwStats->status = 0;
++		return pIwStats;
++	}
++	pIwStats->status = 1;
++	pIwStats->qual.qual = pStats->cs_aveBeacon_rssi;
++	pIwStats->qual.level = pStats->cs_aveBeacon_rssi + 161;	/* noise is
++															   -95 dBm */
++	pIwStats->qual.noise = pStats->noise_floor_calibation;
++	pIwStats->discard.code = pStats->rx_decrypt_err;
++	pIwStats->discard.retries = pStats->tx_retry_cnt;
++	pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
++	up(&ar->arSem);
++	return pIwStats;
++}
++#endif
++
++void ar6k_ready_event(void *devt, u8 * datap, u8 phyCap)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++	struct net_device *dev = ar->arNetDev;
++
++	ar->arWmiReady = TRUE;
++	wake_up(&arEvent);
++	A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
++	AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
++					dev->dev_addr[0], dev->dev_addr[1],
++					dev->dev_addr[2], dev->dev_addr[3],
++					dev->dev_addr[4], dev->dev_addr[5]);
++
++	ar->arPhyCapability = phyCap;
++}
++
++u8 ar6k_iptos_to_userPriority(u8 * pkt)
++{
++	struct iphdr *ipHdr = (struct iphdr *) pkt;
++	u8 userPriority;
++
++	/*
++	 * IP Tos format :
++	 *      (Refer Pg 57 WMM-test-plan-v1.2)
++	 * IP-TOS - 8bits
++	 *          : DSCP(6-bits) ECN(2-bits)
++	 *          : DSCP - P2 P1 P0 X X X
++	 *              where (P2 P1 P0) form 802.1D
++	 */
++	userPriority = ipHdr->tos >> 5;
++	return (userPriority & 0x7);
++}
++
++void
++ar6k_connect_event(AR_SOFTC_T * ar, u16 channel, u8 * bssid,
++					 u16 listenInterval, u8 beaconIeLen,
++					 u8 assocReqLen, u8 assocRespLen, u8 * assocInfo)
++{
++	union iwreq_data wrqu;
++	int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
++	static const char *tag1 = "ASSOCINFO(ReqIEs=";
++	static const char *tag2 = "ASSOCRESPIE=";
++	static const char *beaconIetag = "BEACONIE=";
++	char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + sizeof(tag1)];
++	char *pos;
++
++	A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
++	ar->arBssChannel = channel;
++
++	A_PRINTF("AR6000 connected event on freq %d ", channel);
++	A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
++			 " listenInterval=%d, beaconIeLen = %d assocReqLen=%d"
++			 " assocRespLen =%d\n",
++			 bssid[0], bssid[1], bssid[2],
++			 bssid[3], bssid[4], bssid[5],
++			 listenInterval, beaconIeLen, assocReqLen, assocRespLen);
++
++	if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
++		AR_DEBUG_PRINTF("\nBeaconIEs= ");
++
++		beacon_ie_pos = 0;
++		A_MEMZERO(buf, sizeof(buf));
++		sprintf(buf, "%s", beaconIetag);
++		pos = buf + 9;
++		for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
++			AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++			sprintf(pos, "%2.2x", assocInfo[i]);
++			pos += 2;
++		}
++		AR_DEBUG_PRINTF("\n");
++
++		A_MEMZERO(&wrqu, sizeof(wrqu));
++		wrqu.data.length = strlen(buf);
++		wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++	}
++
++	if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) {
++		assoc_resp_ie_pos = beaconIeLen + assocReqLen + sizeof(u16) +	/* capinfo */
++			sizeof(u16) +		/* status Code */
++			sizeof(u16);		/* associd */
++		A_MEMZERO(buf, sizeof(buf));
++		sprintf(buf, "%s", tag2);
++		pos = buf + 12;
++		AR_DEBUG_PRINTF("\nAssocRespIEs= ");
++		/*
++		 * The Association Response Frame w.o. the WLAN header is delivered to
++		 * the host, so skip over to the IEs
++		 */
++		for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen;
++			 i++) {
++			AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++			sprintf(pos, "%2.2x", assocInfo[i]);
++			pos += 2;
++		}
++		AR_DEBUG_PRINTF("\n");
++
++		A_MEMZERO(&wrqu, sizeof(wrqu));
++		wrqu.data.length = strlen(buf);
++		wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++	}
++
++	if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
++		/*
++		 * assoc Request includes capability and listen interval. Skip these.
++		 */
++		assoc_req_ie_pos = beaconIeLen + sizeof(u16) +	/* capinfo */
++			sizeof(u16);		/* listen interval */
++
++		A_MEMZERO(buf, sizeof(buf));
++		sprintf(buf, "%s", tag1);
++		pos = buf + 17;
++		AR_DEBUG_PRINTF("AssocReqIEs= ");
++		for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen; i++) {
++			AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++			sprintf(pos, "%2.2x", assocInfo[i]);
++			pos += 2;;
++		}
++		AR_DEBUG_PRINTF("\n");
++
++		A_MEMZERO(&wrqu, sizeof(wrqu));
++		wrqu.data.length = strlen(buf);
++		wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++	}
++
++	if (ar->arTotalTxDataPending < txFlowCtrlThresh[ar->arNumDataEndPts]) {
++		netif_wake_queue(ar->arNetDev);
++	}
++
++	if ((OPEN_AUTH == ar->arDot11AuthMode) &&
++		(NONE_AUTH == ar->arAuthMode) &&
++		(WEP_CRYPT == ar->arPairwiseCrypto)) {
++		if (!ar->arConnected) {
++			ar6k_install_static_wep_keys(ar);
++		}
++	}
++
++	ar->arConnected = TRUE;
++	ar->arConnectPending = FALSE;
++
++	A_MEMZERO(&wrqu, sizeof(wrqu));
++	A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
++	wrqu.addr.sa_family = ARPHRD_ETHER;
++	wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
++
++	if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
++		A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
++		ar->arNodeNum = 0;
++		ar->arNexEpId = ENDPOINT2;
++	}
++}
++
++void ar6k_set_numdataendpts(AR_SOFTC_T * ar, u32 num)
++{
++	A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
++	ar->arNumDataEndPts = num;
++}
++
++void
++ar6k_disconnect_event(AR_SOFTC_T * ar, u8 reason, u8 * bssid,
++						u8 assocRespLen, u8 * assocInfo)
++{
++	u8 i;
++
++	A_PRINTF("AR6000 disconnected");
++	if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4]
++		|| bssid[5]) {
++		A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", bssid[0],
++				 bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
++	}
++
++	AR_DEBUG_PRINTF("\nAssocResp Frame = %s", assocRespLen ? " " : "NULL");
++	for (i = 0; i < assocRespLen; i++) {
++		if (!(i % 0x10)) {
++			AR_DEBUG_PRINTF("\n");
++		}
++		AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++	}
++	AR_DEBUG_PRINTF("\n");
++	/*
++	 * If the event is due to disconnect cmd from the host, only they the target
++	 * would stop trying to connect. Under any other condition, target would
++	 * keep trying to connect.
++	 *
++	 */
++	if (reason == DISCONNECT_CMD) {
++		ar->arConnectPending = FALSE;
++	}
++	ar->arConnected = FALSE;
++
++	netif_stop_queue(ar->arNetDev);
++	A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
++	ar->arBssChannel = 0;
++}
++
++void ar6k_regDomain_event(AR_SOFTC_T * ar, u32 regCode)
++{
++	A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
++	ar->arRegCode = regCode;
++}
++
++void
++ar6k_neighborReport_event(AR_SOFTC_T * ar, int numAps,
++							WMI_NEIGHBOR_INFO * info)
++{
++	static const char *tag = "PRE-AUTH";
++	char buf[128];
++	union iwreq_data wrqu;
++	int i;
++
++	A_PRINTF("AR6000 Neighbor Report Event\n");
++	for (i = 0; i < numAps; info++, i++) {
++		A_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
++				 info->bssid[0], info->bssid[1], info->bssid[2],
++				 info->bssid[3], info->bssid[4], info->bssid[5]);
++		if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
++			A_PRINTF("preauth-cap");
++		}
++		if (info->bssFlags & WMI_PMKID_VALID_BSS) {
++			A_PRINTF(" pmkid-valid\n");
++			continue;			/* we skip bss if the pmkid is already
++								   valid */
++		}
++		A_PRINTF("\n");
++		snprintf(buf, sizeof(buf),
++				 "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", tag,
++				 info->bssid[0], info->bssid[1], info->bssid[2],
++				 info->bssid[3], info->bssid[4], info->bssid[5], i,
++				 info->bssFlags);
++		A_MEMZERO(&wrqu, sizeof(wrqu));
++		wrqu.data.length = strlen(buf);
++		wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++	}
++}
++
++void ar6k_tkip_micerr_event(AR_SOFTC_T * ar, u8 keyid, u8 ismcast)
++{
++	static const char *tag = "MLME-MICHAELMICFAILURE.indication";
++	char buf[128];
++	union iwreq_data wrqu;
++
++	A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
++			 keyid, ismcast ? "multi" : "uni");
++	snprintf(buf, sizeof(buf), "%s(keyid=%d %scat)", tag, keyid,
++			 ismcast ? "multi" : "uni");
++	memset(&wrqu, 0, sizeof(wrqu));
++	wrqu.data.length = strlen(buf);
++	wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++}
++
++void ar6k_scanComplete_event(AR_SOFTC_T * ar)
++{
++	A_PRINTF("AR6000 scan complete\n");
++}
++
++void ar6k_targetStats_event(AR_SOFTC_T * ar, WMI_TARGET_STATS * pTarget)
++{
++	TARGET_STATS *pStats = &ar->arTargetStats;
++	u8 ac;
++
++	A_PRINTF("AR6000 updating target stats\n");
++	pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets;
++	pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes;
++	pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
++	pStats->tx_unicast_bytes +=
++		pTarget->txrxStats.tx_stats.tx_unicast_bytes;
++	pStats->tx_multicast_pkts +=
++		pTarget->txrxStats.tx_stats.tx_multicast_pkts;
++	pStats->tx_multicast_bytes +=
++		pTarget->txrxStats.tx_stats.tx_multicast_bytes;
++	pStats->tx_broadcast_pkts +=
++		pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
++	pStats->tx_broadcast_bytes +=
++		pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
++	pStats->tx_rts_success_cnt +=
++		pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
++	for (ac = 0; ac < WMM_NUM_AC; ac++)
++		pStats->tx_packet_per_ac[ac] +=
++			pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
++	pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors;
++	pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt;
++	pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt;
++	pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
++
++	pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets;
++	pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes;
++	pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
++	pStats->rx_unicast_bytes +=
++		pTarget->txrxStats.rx_stats.rx_unicast_bytes;
++	pStats->rx_multicast_pkts +=
++		pTarget->txrxStats.rx_stats.rx_multicast_pkts;
++	pStats->rx_multicast_bytes +=
++		pTarget->txrxStats.rx_stats.rx_multicast_bytes;
++	pStats->rx_broadcast_pkts +=
++		pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
++	pStats->rx_broadcast_bytes +=
++		pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
++	pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
++	pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors;
++	pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr;
++	pStats->rx_key_cache_miss +=
++		pTarget->txrxStats.rx_stats.rx_key_cache_miss;
++	pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err;
++	pStats->rx_duplicate_frames +=
++		pTarget->txrxStats.rx_stats.rx_duplicate_frames;
++
++
++	pStats->tkip_local_mic_failure
++		+= pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
++	pStats->tkip_counter_measures_invoked
++		+= pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
++	pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
++	pStats->tkip_format_errors +=
++		pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
++	pStats->ccmp_format_errors +=
++		pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
++	pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
++
++
++	pStats->power_save_failure_cnt +=
++		pTarget->pmStats.power_save_failure_cnt;
++	pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
++
++	pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt;
++	pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt;
++	pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt;
++	pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt;
++	pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
++	pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec;
++
++	ar->statsUpdatePending = FALSE;
++	wake_up(&arEvent);
++}
++
++
++void
++ar6k_rssiThreshold_event(AR_SOFTC_T * ar,
++						   WMI_RSSI_THRESHOLD_VAL newThreshold)
++{
++	A_PRINTF("AR6000 Threshold val = %d \n", newThreshold);
++}
++
++void
++ar6k_reportError_event(AR_SOFTC_T * ar, WMI_TARGET_ERROR_VAL errorVal)
++{
++	char *errString[] = {
++		[WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL",
++		[WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND",
++		[WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
++		[WMI_TARGET_BMISS] "WMI_TARGET_BMISS",
++		[WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN"
++	};
++
++	A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
++
++	/* One error is reported at a time, and errorval is a bitmask */
++	if (errorVal & (errorVal - 1))
++		return;
++
++	A_PRINTF("AR6000 Error type = ");
++	switch (errorVal) {
++	case WMI_TARGET_PM_ERR_FAIL:
++	case WMI_TARGET_KEY_NOT_FOUND:
++	case WMI_TARGET_DECRYPTION_ERR:
++	case WMI_TARGET_BMISS:
++	case WMI_PSDISABLE_NODE_JOIN:
++		A_PRINTF("%s\n", errString[errorVal]);
++		break;
++	default:
++		A_PRINTF("INVALID\n");
++		break;
++	}
++
++}
++
++
++void
++ar6k_cac_event(AR_SOFTC_T * ar, u8 ac, u8 cacIndication,
++				 u8 statusCode, u8 * tspecSuggestion)
++{
++	WMM_TSPEC_IE *tspecIe;
++
++	/*
++	 * This is the TSPEC IE suggestion from AP.
++	 * Suggestion provided by AP under some error
++	 * cases, could be helpful for the host app.
++	 * Check documentation.
++	 */
++	tspecIe = (WMM_TSPEC_IE *) tspecSuggestion;
++
++	/*
++	 * What do we do, if we get TSPEC rejection? One thought
++	 * that comes to mind is implictly delete the pstream...
++	 */
++	A_PRINTF("AR6000 CAC notification. "
++			 "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
++			 ac, cacIndication, statusCode);
++}
++
++#define AR6000_PRINT_BSSID(_pBss)  do {     \
++        A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
++                 (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
++                 (_pBss)[4],(_pBss)[5]);  \
++} while(0)
++
++void ar6k_roam_tbl_event(AR_SOFTC_T * ar, WMI_TARGET_ROAM_TBL * pTbl)
++{
++	u8 i;
++
++	A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
++			 pTbl->numEntries, pTbl->roamMode);
++	for (i = 0; i < pTbl->numEntries; i++) {
++		A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
++				 pTbl->bssRoamInfo[i].bssid[0],
++				 pTbl->bssRoamInfo[i].bssid[1],
++				 pTbl->bssRoamInfo[i].bssid[2],
++				 pTbl->bssRoamInfo[i].bssid[3],
++				 pTbl->bssRoamInfo[i].bssid[4],
++				 pTbl->bssRoamInfo[i].bssid[5]);
++		A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
++				 " BIAS %d\n", pTbl->bssRoamInfo[i].rssi,
++				 pTbl->bssRoamInfo[i].rssidt,
++				 pTbl->bssRoamInfo[i].last_rssi, pTbl->bssRoamInfo[i].util,
++				 pTbl->bssRoamInfo[i].roam_util,
++				 pTbl->bssRoamInfo[i].bias);
++	}
++}
++
++/*
++ * Report the Roaming related data collected on the target
++ */
++void ar6k_display_roam_time(WMI_TARGET_ROAM_TIME * p)
++{
++	A_PRINTF("Disconnect Data : BSSID: ");
++	AR6000_PRINT_BSSID(p->disassoc_bssid);
++	A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
++			 p->disassoc_bss_rssi, p->disassoc_time, p->no_txrx_time);
++	A_PRINTF("Connect Data: BSSID: ");
++	AR6000_PRINT_BSSID(p->assoc_bssid);
++	A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
++			 p->assoc_bss_rssi, p->assoc_time, p->allow_txrx_time);
++	A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "
++			 "First Data Tx Time (after Assoc) %d\n",
++			 p->last_data_txrx_time, p->first_data_txrx_time);
++}
++
++void ar6k_roam_data_event(AR_SOFTC_T * ar, WMI_TARGET_ROAM_DATA * p)
++{
++	switch (p->roamDataType) {
++	case ROAM_DATA_TIME:
++		ar6k_display_roam_time(&p->u.roamTime);
++		break;
++	default:
++		break;
++	}
++}
++
++static int
++ar6k_ioctl_set_error_report_bitmask(struct net_device *dev,
++									  struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_TARGET_ERROR_REPORT_BITMASK cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return (ret == 0 ? ret : -EINVAL);
++}
++
++
++static int
++ar6k_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	TARGET_STATS *pStats = &ar->arTargetStats;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++	if (down_interruptible(&ar->arSem)) {
++		return -ERESTARTSYS;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	ar->statsUpdatePending = TRUE;
++
++	if (wmi_get_stats_cmd(ar->arWmi) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		up(&ar->arSem);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	wait_event_interruptible(arEvent, ar->statsUpdatePending == FALSE);
++
++	if (signal_pending(current)) {
++		ret = -EINTR;
++	}
++
++	if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
++		ret = -EFAULT;
++	}
++
++	up(&ar->arSem);
++
++	return ret;
++}
++
++static int
++ar6k_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_SET_ACCESS_PARAMS_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_set_access_params_cmd
++		(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax, cmd.aifsn) == A_OK) {
++		ret = 0;
++	} else {
++		ret = -EINVAL;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return (ret);
++}
++
++static int
++ar6k_ioctl_set_disconnect_timeout(struct net_device *dev,
++									struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_DISC_TIMEOUT_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) {
++		ret = 0;
++	} else {
++		ret = -EINVAL;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return (ret);
++}
++
++static int
++ar6k_xioctl_set_voice_pkt_size(struct net_device *dev, char *userdata)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_SET_VOICE_PKT_SIZE_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) {
++		ret = 0;
++	} else {
++		ret = -EINVAL;
++	}
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return (ret);
++}
++
++static int
++ar6k_xioctl_set_max_sp_len(struct net_device *dev, char *userdata)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_SET_MAX_SP_LEN_CMD cmd;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) {
++		ret = 0;
++	} else {
++		ret = -EINVAL;
++	}
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return (ret);
++}
++
++int ar6k_control_tx(void *devt, struct sk_buff *skb, int endPt)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++	int status;
++	struct ar_cookie *cookie;
++	WMI_DATA_HDR *dhdr;
++
++	A_ASSERT((endPt == WMI_CONTROL_MBOX)
++			 || (endPt == WMI_LOW_PRIORITY_MBOX)
++			 || (endPt == WMI_HIGH_PRIORITY_MBOX)
++			 || (endPt == WMI_BEST_EFFORT_MBOX));
++
++	ar->arTxPending[endPt]++;
++	if (endPt != WMI_CONTROL_MBOX) {
++		ar->arTotalTxDataPending++;
++	}
++
++	cookie = ar6k_alloc_cookie(ar);
++
++	/* If the particular data queue is full, silently drop the pkt. */
++	dhdr = (WMI_DATA_HDR *) skb->data;
++	if ((cookie == NULL) ||
++		((ar->arTxPending[endPt] > MAX_ALLOWED_TXQ_DEPTH) &&
++		 (!WMI_DATA_HDR_IS_MSG_TYPE(dhdr, SYNC_MSGTYPE)))) {
++		ar->arTxPending[endPt]--;
++		if (endPt != WMI_CONTROL_MBOX) {
++			ar->arTotalTxDataPending--;
++		}
++		dev_kfree_skb(skb);
++		if (cookie != NULL) {
++			ar6k_free_cookie(ar, cookie);
++		}
++		return A_NO_MEMORY;
++	}
++
++	cookie->arc_bp[0] = (u32) skb;
++	cookie->arc_bp[1] = 0;
++	status = HTCBufferSend(ar->arHtcTarget, endPt, skb->data,
++						   skb->len, cookie);
++	if (status != A_OK) {
++		/*
++		 * XXX This is an error that requires us to reset chip
++		 */
++		ar->arTxPending[endPt]--;
++		if (endPt != WMI_CONTROL_MBOX) {
++			ar->arTotalTxDataPending--;
++		}
++		AR_DEBUG_PRINTF("Dropping control frame!!\n");
++		ar6k_free_cookie(ar, cookie);
++		dev_kfree_skb(skb);
++		return (status);
++	}
++
++	return A_OK;
++}
++
++module_init(ar6k_init_module);
++module_exit(ar6k_cleanup_module);
++
++/*
++ * SIOCGIWNAME
++ */
++int
++ar6k_ioctl_giwname(struct net_device *dev,
++					 struct iw_request_info *info, char *name, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	switch (ar->arPhyCapability) {
++	case (WMI_11A_CAPABILITY):
++		strncpy(name, "AR6000 802.11a", IFNAMSIZ);
++		break;
++	case (WMI_11G_CAPABILITY):
++		strncpy(name, "AR6000 802.11g", IFNAMSIZ);
++		break;
++	case (WMI_11AG_CAPABILITY):
++		strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
++		break;
++	default:
++		strncpy(name, "AR6000 802.11", IFNAMSIZ);
++		break;
++	}
++
++	return 0;
++}
++
++/*
++ * SIOCSIWFREQ
++ */
++int
++ar6k_ioctl_siwfreq(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_freq *freq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	/*
++	 * We support limiting the channels via wmiconfig.
++	 *
++	 * We use this command to configure the channel hint for the connect cmd
++	 * so it is possible the target will end up connecting to a different
++	 * channel.
++	 */
++	if (freq->e > 1) {
++		return -EINVAL;
++	} else if (freq->e == 1) {
++		ar->arChannelHint = freq->m / 100000;
++	} else {
++		ar->arChannelHint = wlan_ieee2freq(freq->m);
++	}
++
++	A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
++	return 0;
++}
++
++/*
++ * SIOCGIWFREQ
++ */
++int
++ar6k_ioctl_giwfreq(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_freq *freq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ar->arConnected != TRUE) {
++		return -EINVAL;
++	}
++
++	freq->m = ar->arBssChannel * 100000;
++	freq->e = 1;
++
++	return 0;
++}
++
++/*
++ * SIOCSIWMODE
++ */
++int
++ar6k_ioctl_siwmode(struct net_device *dev,
++					 struct iw_request_info *info,
++					 __u32 * mode, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	switch (*mode) {
++	case IW_MODE_INFRA:
++		ar->arNetworkType = INFRA_NETWORK;
++		break;
++	case IW_MODE_ADHOC:
++		ar->arNetworkType = ADHOC_NETWORK;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/*
++ * SIOCGIWMODE
++ */
++int
++ar6k_ioctl_giwmode(struct net_device *dev,
++					 struct iw_request_info *info,
++					 __u32 * mode, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	switch (ar->arNetworkType) {
++	case INFRA_NETWORK:
++		*mode = IW_MODE_INFRA;
++		break;
++	case ADHOC_NETWORK:
++		*mode = IW_MODE_ADHOC;
++		break;
++	default:
++		return -EIO;
++	}
++	return 0;
++}
++
++/*
++ * SIOCSIWSENS
++ */
++int
++ar6k_ioctl_siwsens(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_param *sens, char *extra)
++{
++	return 0;
++}
++
++/*
++ * SIOCGIWSENS
++ */
++int
++ar6k_ioctl_giwsens(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_param *sens, char *extra)
++{
++	sens->value = 0;
++	sens->fixed = 1;
++
++	return 0;
++}
++
++/*
++ * SIOCGIWRANGE
++ */
++int
++ar6k_ioctl_giwrange(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_point *data, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct iw_range *range = (struct iw_range *) extra;
++	int i, ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (down_interruptible(&ar->arSem)) {
++		return -ERESTARTSYS;
++	}
++	ar->arNumChannels = -1;
++	A_MEMZERO(ar->arChannelList, sizeof(ar->arChannelList));
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		up(&ar->arSem);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	wait_event_interruptible(arEvent, ar->arNumChannels != -1);
++
++	if (signal_pending(current)) {
++		up(&ar->arSem);
++		return -EINTR;
++	}
++
++	data->length = sizeof(struct iw_range);
++	A_MEMZERO(range, sizeof(struct iw_range));
++
++	range->txpower_capa = 0;
++
++	range->min_pmp = 1 * 1024;
++	range->max_pmp = 65535 * 1024;
++	range->min_pmt = 1 * 1024;
++	range->max_pmt = 1000 * 1024;
++	range->pmp_flags = IW_POWER_PERIOD;
++	range->pmt_flags = IW_POWER_TIMEOUT;
++	range->pm_capa = 0;
++
++	range->we_version_compiled = WIRELESS_EXT;
++	range->we_version_source = 13;
++
++	range->retry_capa = IW_RETRY_LIMIT;
++	range->retry_flags = IW_RETRY_LIMIT;
++	range->min_retry = 0;
++	range->max_retry = 255;
++
++	range->num_frequency = range->num_channels = ar->arNumChannels;
++	for (i = 0; i < ar->arNumChannels; i++) {
++		range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
++		range->freq[i].m = ar->arChannelList[i] * 100000;
++		range->freq[i].e = 1;
++	}
++
++	/* Max quality is max field value minus noise floor */
++	range->max_qual.qual = 0xff - 161;
++
++	/*
++	 * In order to use dBm measurements, 'level' must be lower
++	 * than any possible measurement (see iw_print_stats() in
++	 * wireless tools).  It's unclear how this is meant to be
++	 * done, but setting zero in these values forces dBm and
++	 * the actual numbers are not used.
++	 */
++	range->max_qual.level = 0;
++	range->max_qual.noise = 0;
++
++	range->sensitivity = 3;
++
++	range->max_encoding_tokens = 4;
++	/* XXX query driver to find out supported key sizes */
++	range->num_encoding_sizes = 3;
++	range->encoding_size[0] = 5;	/* 40-bit */
++	range->encoding_size[1] = 13;	/* 104-bit */
++	range->encoding_size[2] = 16;	/* 128-bit */
++
++	range->num_bitrates = 0;
++
++	/* estimated maximum TCP throughput values (bps) */
++	range->throughput = 22000000;
++
++	range->min_rts = 0;
++	range->max_rts = 2347;
++	range->min_frag = 256;
++	range->max_frag = 2346;
++
++	up(&ar->arSem);
++
++	return ret;
++}
++
++/*
++ * SIOCSIWAP
++ * This ioctl is used to set the desired bssid for the connect command.
++ */
++int
++ar6k_ioctl_siwap(struct net_device *dev,
++				   struct iw_request_info *info,
++				   struct sockaddr *ap_addr, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ap_addr->sa_family != ARPHRD_ETHER) {
++		return -EIO;
++	}
++
++	if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
++		A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++	} else {
++		A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data,
++				 sizeof(ar->arReqBssid));
++	}
++
++	return 0;
++}
++
++/*
++ * SIOCGIWAP
++ */
++int
++ar6k_ioctl_giwap(struct net_device *dev,
++				   struct iw_request_info *info,
++				   struct sockaddr *ap_addr, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ar->arConnected != TRUE) {
++		return -EINVAL;
++	}
++
++	A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
++	ap_addr->sa_family = ARPHRD_ETHER;
++
++	return 0;
++}
++
++/*
++ * SIOCGIWAPLIST
++ */
++int
++ar6k_ioctl_iwaplist(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_point *data, char *extra)
++{
++	return -EIO;				/* for now */
++}
++
++/*
++ * SIOCGIWSCAN
++ */
++int
++ar6k_ioctl_siwscan(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_point *data, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN) != A_OK) {
++		ret = -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return ret;
++}
++
++#if WIRELESS_EXT > 14
++/*
++ * Encode a WPA or RSN information element as a custom
++ * element using the hostap format.
++ */
++static u_int
++encode_ie(void *buf, size_t bufsize,
++		  const u_int8_t * ie, size_t ielen,
++		  const char *leader, size_t leader_len)
++{
++	u_int8_t *p;
++	int i;
++
++	if (bufsize < leader_len)
++		return 0;
++	p = buf;
++	memcpy(p, leader, leader_len);
++	bufsize -= leader_len;
++	p += leader_len;
++	for (i = 0; i < ielen && bufsize > 2; i++)
++		p += sprintf(p, "%02x", ie[i]);
++	return (i == ielen ? p - (u_int8_t *) buf : 0);
++}
++#endif							/* WIRELESS_EXT > 14 */
++/*
++ * Units are in db above the noise floor. That means the
++ * rssi values reported in the tx/rx descriptors in the
++ * driver are the SNR expressed in db.
++ *
++ * If you assume that the noise floor is -95, which is an
++ * excellent assumption 99.5 % of the time, then you can
++ * derive the absolute signal level (i.e. -95 + rssi).
++ * There are some other slight factors to take into account
++ * depending on whether the rssi measurement is from 11b,
++ * 11g, or 11a.   These differences are at most 2db and
++ * can be documented.
++ *
++ * NB: various calculations are based on the orinoco/wavelan
++ *     drivers for compatibility
++ */
++static void ar6k_set_quality(struct iw_quality *iq, s8 rssi)
++{
++	if (rssi < 0) {
++		iq->qual = 0;
++	} else {
++		iq->qual = rssi;
++	}
++
++	/* NB: max is 94 because noise is hardcoded to 161 */
++	if (iq->qual > 94)
++		iq->qual = 94;
++
++	iq->noise = 161;			/* -95dBm */
++	iq->level = iq->noise + iq->qual;
++	iq->updated = 7;
++}
++
++void ar6k_scan_node(void *arg, bss_t * ni)
++{
++	struct iw_event iwe;
++#if WIRELESS_EXT > 14
++	char buf[64 * 2 + 30];
++#endif
++	struct ar_giwscan_param *param;
++	u8 *current_ev;
++	u8 *end_buf;
++	struct ieee80211_common_ie *cie;
++
++	param = (struct ar_giwscan_param *) arg;
++
++	if (param->current_ev >= param->end_buf) {
++		return;
++	}
++	if ((param->firstPass == TRUE) && (ni->ni_cie.ie_wpa == NULL)) {
++		/*
++		 * Only forward wpa bss's in first pass
++		 */
++		return;
++	}
++	if ((param->firstPass == FALSE) && (ni->ni_cie.ie_wpa != NULL)) {
++		/*
++		 * Only forward non-wpa bss's in 2nd pass
++		 */
++		return;
++	}
++
++	current_ev = param->current_ev;
++	end_buf = param->end_buf;
++
++	cie = &ni->ni_cie;
++
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = SIOCGIWAP;
++	iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++	A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
++	current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++									  IW_EV_ADDR_LEN);
++
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = SIOCGIWESSID;
++	iwe.u.data.flags = 1;
++	iwe.u.data.length = cie->ie_ssid[1];
++	current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe,
++									  &cie->ie_ssid[2]);
++
++	if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS | IEEE80211_CAPINFO_IBSS)) {
++		A_MEMZERO(&iwe, sizeof(iwe));
++		iwe.cmd = SIOCGIWMODE;
++		iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
++			IW_MODE_MASTER : IW_MODE_ADHOC;
++		current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++										  IW_EV_UINT_LEN);
++	}
++
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = SIOCGIWFREQ;
++	iwe.u.freq.m = cie->ie_chan * 100000;
++	iwe.u.freq.e = 1;
++	current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++									  IW_EV_FREQ_LEN);
++
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = IWEVQUAL;
++	ar6k_set_quality(&iwe.u.qual, ni->ni_rssi);
++	current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++									  IW_EV_QUAL_LEN);
++
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = SIOCGIWENCODE;
++	if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
++		iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++	} else {
++		iwe.u.data.flags = IW_ENCODE_DISABLED;
++	}
++	iwe.u.data.length = 0;
++	current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, "");
++
++#ifdef NOTYET
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = SIOCGIWRATE;
++	current_val = current_ev + IW_EV_LCP_LEN;
++	for (j = 0; j < ni->ni_rates.rs_nrates; j++) {
++		if (ni->ni_rates.rs_rates[j]) {
++			iwe.u.bitrate.value = ((ni->ni_rates.rs_rates[j] &
++									IEEE80211_RATE_VAL) / 2) * 1000000;
++			current_val = iwe_stream_add_value(current_ev,
++											   current_val, end_buf, &iwe,
++											   IW_EV_PARAM_LEN);
++		}
++	}
++	/* remove fixed header if no rates were added */
++	if ((current_val - current_ev) > IW_EV_LCP_LEN)
++		current_ev = current_val;
++#endif							/* NOTYET */
++
++#if WIRELESS_EXT > 14
++	A_MEMZERO(&iwe, sizeof(iwe));
++	iwe.cmd = IWEVCUSTOM;
++	snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
++	iwe.u.data.length = strlen(buf);
++	current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++
++	if (cie->ie_wpa != NULL) {
++		static const char rsn_leader[] = "rsn_ie=";
++		static const char wpa_leader[] = "wpa_ie=";
++
++		A_MEMZERO(&iwe, sizeof(iwe));
++		iwe.cmd = IWEVCUSTOM;
++		if (cie->ie_wpa[0] == IEEE80211_ELEMID_RSN) {
++			iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
++										  cie->ie_wpa[1] + 2,
++										  rsn_leader,
++										  sizeof(rsn_leader) - 1);
++		} else {
++			iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
++										  cie->ie_wpa[1] + 2,
++										  wpa_leader,
++										  sizeof(wpa_leader) - 1);
++		}
++		if (iwe.u.data.length != 0) {
++			current_ev =
++				iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++		}
++	}
++
++	if (cie->ie_wmm != NULL) {
++		static const char wmm_leader[] = "wmm_ie=";
++
++		A_MEMZERO(&iwe, sizeof(iwe));
++		iwe.cmd = IWEVCUSTOM;
++		iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
++									  cie->ie_wmm[1] + 2,
++									  wmm_leader, sizeof(wmm_leader) - 1);
++		if (iwe.u.data.length != 0) {
++			current_ev =
++				iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++		}
++	}
++
++	if (cie->ie_ath != NULL) {
++		static const char ath_leader[] = "ath_ie=";
++
++		A_MEMZERO(&iwe, sizeof(iwe));
++		iwe.cmd = IWEVCUSTOM;
++		iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
++									  cie->ie_ath[1] + 2,
++									  ath_leader, sizeof(ath_leader) - 1);
++		if (iwe.u.data.length != 0) {
++			current_ev =
++				iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++		}
++	}
++#endif							/* WIRELESS_EXT > 14 */
++
++	param->current_ev = current_ev;
++}
++
++int
++ar6k_ioctl_giwscan(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_point *data, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ar_giwscan_param param;
++	int i;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	param.current_ev = extra;
++	param.end_buf = extra + IW_SCAN_MAX_DATA;
++	param.firstPass = TRUE;
++
++	/*
++	 * Do two passes to insure WPA scan candidates
++	 * are sorted to the front.  This is a hack to deal with
++	 * the wireless extensions capping scan results at
++	 * IW_SCAN_MAX_DATA bytes.  In densely populated environments
++	 * it's easy to overflow this buffer (especially with WPA/RSN
++	 * information elements).  Note this sorting hack does not
++	 * guarantee we won't overflow anyway.
++	 */
++	for (i = 0; i < 2; i++) {
++		/*
++		 * Translate data to WE format.
++		 */
++		wmi_iterate_nodes(ar->arWmi, ar6k_scan_node, &param);
++		param.firstPass = FALSE;
++		if (param.current_ev >= param.end_buf) {
++			break;
++		}
++	}
++
++	data->length = param.current_ev - extra;
++	return 0;
++}
++
++/* SIOCSIWESSID */
++static int
++ar6k_ioctl_siwessid(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_point *data, char *ssid)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int status;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	/*
++	 * iwconfig passes a null terminated string with length including this
++	 * so we need to account for this
++	 */
++	if (data->flags && (!data->length || (data->length == 1) ||
++						((data->length - 1) > sizeof(ar->arSsid)))) {
++		/*
++		 * ssid is invalid
++		 */
++		return -EINVAL;
++	}
++
++	if (down_interruptible(&ar->arSem)) {
++		return -ERESTARTSYS;
++	}
++
++	if (ar->arTxPending[WMI_CONTROL_MBOX]) {
++		/*
++		 * sleep until the command queue drains
++		 */
++		wait_event_interruptible(arEvent,
++								 ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++		if (signal_pending(current)) {
++			return -EINTR;
++		}
++	}
++
++	if ((ar->arSsidLen) || (!data->flags)) {
++		if ((!data->flags) ||
++			(A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
++			(ar->arSsidLen != (data->length - 1))) {
++			/*
++			 * SSID set previously or essid off has been issued.
++			 *
++			 * Disconnect Command is issued in two cases after wmi is ready
++			 * (1) ssid is different from the previous setting
++			 * (2) essid off has been issued
++			 *
++			 */
++			if (ar->arWmiReady == TRUE) {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				status = wmi_disconnect_cmd(ar->arWmi);
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++				A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++				ar->arSsidLen = 0;
++				A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++				if (!data->flags) {
++					up(&ar->arSem);
++					return 0;
++				}
++			} else {
++				up(&ar->arSem);
++			}
++		} else {
++			/*
++			 * SSID is same, so we assume profile hasn't changed.
++			 * If the interface is up and wmi is ready, we issue
++			 * a reconnect cmd.
++			 */
++			if ((ar->arConnected == TRUE || ar->arConnectPending == TRUE)
++				&& (ar->arWmiReady == TRUE)) {
++				AR6000_SPIN_LOCK(&ar->arLock, 0);
++				status = wmi_reconnect_cmd(ar->arWmi, ar->arReqBssid,
++										   ar->arChannelHint);
++				AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++				up(&ar->arSem);
++				if (status != A_OK) {
++					return -EIO;
++				}
++				return 0;
++			} else {
++				up(&ar->arSem);
++				return 0;
++			}
++		}
++	}
++
++	ar->arSsidLen = data->length - 1;
++	A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
++
++	/* The ssid length check prevents second "essid off" from the user, to
++	   be treated as a connect cmd. The second "essid off" is ignored. */
++	if ((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0)) {
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		if (SHARED_AUTH == ar->arDot11AuthMode) {
++			ar6k_install_static_wep_keys(ar);
++		}
++		AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"
++						" PW crypto %d PW crypto Len %d GRP crypto %d"
++						" GRP crypto Len %d\n",
++						ar->arAuthMode, ar->arDot11AuthMode,
++						ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
++						ar->arGroupCrypto, ar->arGroupCryptoLen);
++
++		status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
++								 ar->arDot11AuthMode, ar->arAuthMode,
++								 ar->arPairwiseCrypto,
++								 ar->arPairwiseCryptoLen,
++								 ar->arGroupCrypto, ar->arGroupCryptoLen,
++								 ar->arSsidLen, ar->arSsid, ar->arReqBssid,
++								 ar->arChannelHint);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++		up(&ar->arSem);
++
++		if (status != A_OK) {
++			return -EIO;
++		}
++		ar->arConnectPending = TRUE;
++	} else {
++		up(&ar->arSem);
++	}
++	return 0;
++}
++
++/* SIOCGIWESSID */
++static int
++ar6k_ioctl_giwessid(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_point *data, char *essid)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (!ar->arSsidLen) {
++		return -EINVAL;
++	}
++
++	data->flags = 1;
++	data->length = ar->arSsidLen;
++	A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
++
++	return 0;
++}
++
++/*
++ * SIOCSIWRATE
++ */
++int
++ar6k_ioctl_siwrate(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	u32 kbps;
++
++	if (rrq->fixed) {
++		kbps = rrq->value / 1000;	/* rrq->value is in bps */
++	} else {
++		kbps = -1;				/* -1 indicates auto rate */
++	}
++	if (wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) {
++		AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps);
++		return -EINVAL;
++	}
++	ar->arBitRate = kbps;
++	if (ar->arWmiReady == TRUE) {
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) {
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			return -EINVAL;
++		}
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	}
++	return 0;
++}
++
++/*
++ * SIOCGIWRATE
++ */
++int
++ar6k_ioctl_giwrate(struct net_device *dev,
++					 struct iw_request_info *info,
++					 struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int ret = 0;
++
++	if (down_interruptible(&ar->arSem)) {
++		return -ERESTARTSYS;
++	}
++	if (ar->arWmiReady == TRUE) {
++		ar->arBitRate = 0xFFFF;
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			up(&ar->arSem);
++			return -EIO;
++		}
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		wait_event_interruptible(arEvent, ar->arBitRate != 0xFFFF);
++		if (signal_pending(current)) {
++			ret = -EINTR;
++		}
++	}
++	/* If the interface is down or wmi is not ready or the target is not
++	   connected - return the value stored in the device structure */
++	if (!ret) {
++		if (ar->arBitRate == -1) {
++			rrq->fixed = TRUE;
++			rrq->value = 0;
++		} else {
++			rrq->value = ar->arBitRate * 1000;
++		}
++	}
++
++	up(&ar->arSem);
++
++	return ret;
++}
++
++/*
++ * SIOCSIWTXPOW
++ */
++static int
++ar6k_ioctl_siwtxpow(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	u8 dbM;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (rrq->disabled) {
++		return -EOPNOTSUPP;
++	}
++
++	if (rrq->fixed) {
++		if (rrq->flags != IW_TXPOW_DBM) {
++			return -EOPNOTSUPP;
++		}
++		ar->arTxPwr = dbM = rrq->value;
++		ar->arTxPwrSet = TRUE;
++	} else {
++		ar->arTxPwr = dbM = 0;
++		ar->arTxPwrSet = FALSE;
++	}
++	if (ar->arWmiReady == TRUE) {
++		AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM);
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		wmi_set_txPwr_cmd(ar->arWmi, dbM);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	}
++	return 0;
++}
++
++/*
++ * SIOCGIWTXPOW
++ */
++int
++ar6k_ioctl_giwtxpow(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int ret = 0;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (down_interruptible(&ar->arSem)) {
++		return -ERESTARTSYS;
++	}
++	if ((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) {
++		ar->arTxPwr = 0;
++
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
++			AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++			up(&ar->arSem);
++			return -EIO;
++		}
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++		wait_event_interruptible(arEvent, ar->arTxPwr != 0);
++
++		if (signal_pending(current)) {
++			ret = -EINTR;
++		}
++	}
++	/* If the interace is down or wmi is not ready or target is not
++	   connected then return value stored in the device structure */
++
++	if (!ret) {
++		if (ar->arTxPwrSet == TRUE) {
++			rrq->fixed = TRUE;
++		}
++		rrq->value = ar->arTxPwr;
++		rrq->flags = IW_TXPOW_DBM;
++	}
++
++	up(&ar->arSem);
++
++	return ret;
++}
++
++/*
++ * SIOCSIWRETRY
++ * since iwconfig only provides us with one max retry value, we use it
++ * to apply to data frames of the BE traffic class.
++ */
++static int
++ar6k_ioctl_siwretry(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (rrq->disabled) {
++		return -EOPNOTSUPP;
++	}
++
++	if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
++		return -EOPNOTSUPP;
++	}
++
++	if (!(rrq->value >= WMI_MIN_RETRIES)
++		|| !(rrq->value <= WMI_MAX_RETRIES)) {
++		return -EINVAL;
++	}
++	if (ar->arWmiReady == TRUE) {
++		if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
++									 rrq->value) == A_OK) {
++			return -EINVAL;
++		}
++	}
++	ar->arMaxRetries = rrq->value;
++	return 0;
++}
++
++/*
++ * SIOCGIWRETRY
++ */
++static int
++ar6k_ioctl_giwretry(struct net_device *dev,
++					  struct iw_request_info *info,
++					  struct iw_param *rrq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	rrq->disabled = 0;
++	switch (rrq->flags & IW_RETRY_TYPE) {
++	case IW_RETRY_LIFETIME:
++		return -EOPNOTSUPP;
++		break;
++	case IW_RETRY_LIMIT:
++		rrq->flags = IW_RETRY_LIMIT;
++		switch (rrq->flags & IW_RETRY_MODIFIER) {
++		case IW_RETRY_MIN:
++			rrq->flags |= IW_RETRY_MIN;
++			rrq->value = WMI_MIN_RETRIES;
++			break;
++		case IW_RETRY_MAX:
++			rrq->flags |= IW_RETRY_MAX;
++			rrq->value = ar->arMaxRetries;
++			break;
++		}
++		break;
++	}
++	return 0;
++}
++
++/*
++ * SIOCSIWENCODE
++ */
++static int
++ar6k_ioctl_siwencode(struct net_device *dev,
++					   struct iw_request_info *info,
++					   struct iw_point *erq, char *keybuf)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int index;
++	DOT11_AUTH_MODE auth = ar->arDot11AuthMode;
++	/*
++	 *  Static WEP Keys should be configured before setting the SSID
++	 */
++	if (ar->arSsidLen) {
++		return -EIO;
++	}
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	index = erq->flags & IW_ENCODE_INDEX;
++
++	if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
++				  ((index - 1) > WMI_MAX_KEY_INDEX))) {
++		return -EIO;
++	}
++
++	if (erq->flags & IW_ENCODE_DISABLED) {
++		/*
++		 * Encryption disabled
++		 */
++		if (index) {
++			/*
++			 * If key index was specified then clear the specified key
++			 */
++			index--;
++			A_MEMZERO(ar->arWepKeyList[index].arKey,
++					  sizeof(ar->arWepKeyList[index].arKey));
++			ar->arWepKeyList[index].arKeyLen = 0;
++		}
++		ar->arDot11AuthMode = OPEN_AUTH;
++		ar->arPairwiseCrypto = NONE_CRYPT;
++		ar->arGroupCrypto = NONE_CRYPT;
++		ar->arAuthMode = NONE_AUTH;
++	} else {
++		/*
++		 * Enabling WEP encryption
++		 */
++		if (index) {
++			index--;			/* keyindex is off base 1 in iwconfig */
++		}
++
++		if (erq->flags & IW_ENCODE_OPEN) {
++			auth = OPEN_AUTH;
++		} else if (erq->flags & IW_ENCODE_RESTRICTED) {
++			auth = SHARED_AUTH;
++		}
++
++		if (erq->length) {
++			if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
++				return -EIO;
++			}
++
++			A_MEMZERO(ar->arWepKeyList[index].arKey,
++					  sizeof(ar->arWepKeyList[index].arKey));
++			A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
++			ar->arWepKeyList[index].arKeyLen = erq->length;
++		} else {
++			if (ar->arWepKeyList[index].arKeyLen == 0) {
++				return -EIO;
++			}
++			ar->arDefTxKeyIndex = index;
++		}
++
++		ar->arPairwiseCrypto = WEP_CRYPT;
++		ar->arGroupCrypto = WEP_CRYPT;
++		ar->arDot11AuthMode = auth;
++		ar->arAuthMode = NONE_AUTH;
++	}
++
++	/*
++	 * profile has changed.  Erase ssid to signal change
++	 */
++	A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_giwencode(struct net_device *dev,
++					   struct iw_request_info *info,
++					   struct iw_point *erq, char *key)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	u8 keyIndex;
++	struct ar_wep_key *wk;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (ar->arPairwiseCrypto == NONE_CRYPT) {
++		erq->length = 0;
++		erq->flags = IW_ENCODE_DISABLED;
++	} else {
++		/* get the keyIndex */
++		keyIndex = erq->flags & IW_ENCODE_INDEX;
++		if (0 == keyIndex) {
++			keyIndex = ar->arDefTxKeyIndex;
++		} else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
++				   (keyIndex - 1 > WMI_MAX_KEY_INDEX)) {
++			keyIndex = WMI_MIN_KEY_INDEX;
++		} else {
++			keyIndex--;
++		}
++		erq->flags = keyIndex + 1;
++		erq->flags |= IW_ENCODE_ENABLED;
++		wk = &ar->arWepKeyList[keyIndex];
++		if (erq->length > wk->arKeyLen) {
++			erq->length = wk->arKeyLen;
++		}
++		if (wk->arKeyLen) {
++			A_MEMCPY(key, wk->arKey, erq->length);
++		}
++		if (ar->arDot11AuthMode == OPEN_AUTH) {
++			erq->flags |= IW_ENCODE_OPEN;
++		} else if (ar->arDot11AuthMode == SHARED_AUTH) {
++			erq->flags |= IW_ENCODE_RESTRICTED;
++		}
++	}
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_setparam(struct net_device *dev,
++					  struct iw_request_info *info, void *erq, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	int *i = (int *) extra;
++	int param = i[0];
++	int value = i[1];
++	int ret = 0;
++	u8 profChanged = FALSE;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	switch (param) {
++	case IEEE80211_PARAM_WPA:
++		switch (value) {
++		case WPA_MODE_WPA1:
++			ar->arAuthMode = WPA_AUTH;
++			profChanged = TRUE;
++			break;
++		case WPA_MODE_WPA2:
++			ar->arAuthMode = WPA2_AUTH;
++			profChanged = TRUE;
++			break;
++		case WPA_MODE_NONE:
++			ar->arAuthMode = NONE_AUTH;
++			profChanged = TRUE;
++			break;
++		}
++		break;
++	case IEEE80211_PARAM_AUTHMODE:
++		switch (value) {
++		case IEEE80211_AUTH_WPA_PSK:
++			if (WPA_AUTH == ar->arAuthMode) {
++				ar->arAuthMode = WPA_PSK_AUTH;
++				profChanged = TRUE;
++			} else if (WPA2_AUTH == ar->arAuthMode) {
++				ar->arAuthMode = WPA2_PSK_AUTH;
++				profChanged = TRUE;
++			} else {
++				AR_DEBUG_PRINTF("Error -  Setting PSK mode when WPA "
++								"param was set to %d\n", ar->arAuthMode);
++				ret = -1;
++			}
++			break;
++		case IEEE80211_AUTH_WPA_CCKM:
++			if (WPA2_AUTH == ar->arAuthMode) {
++				ar->arAuthMode = WPA2_AUTH_CCKM;
++			} else {
++				ar->arAuthMode = WPA_AUTH_CCKM;
++			}
++			break;
++		default:
++			break;
++		}
++		break;
++	case IEEE80211_PARAM_UCASTCIPHER:
++		switch (value) {
++		case IEEE80211_CIPHER_AES_CCM:
++			ar->arPairwiseCrypto = AES_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_TKIP:
++			ar->arPairwiseCrypto = TKIP_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_WEP:
++			ar->arPairwiseCrypto = WEP_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_NONE:
++			ar->arPairwiseCrypto = NONE_CRYPT;
++			profChanged = TRUE;
++			break;
++		}
++		break;
++	case IEEE80211_PARAM_UCASTKEYLEN:
++		if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
++			ret = -EIO;
++		} else {
++			ar->arPairwiseCryptoLen = value;
++		}
++		break;
++	case IEEE80211_PARAM_MCASTCIPHER:
++		switch (value) {
++		case IEEE80211_CIPHER_AES_CCM:
++			ar->arGroupCrypto = AES_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_TKIP:
++			ar->arGroupCrypto = TKIP_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_WEP:
++			ar->arGroupCrypto = WEP_CRYPT;
++			profChanged = TRUE;
++			break;
++		case IEEE80211_CIPHER_NONE:
++			ar->arGroupCrypto = NONE_CRYPT;
++			profChanged = TRUE;
++			break;
++		}
++		break;
++	case IEEE80211_PARAM_MCASTKEYLEN:
++		if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
++			ret = -EIO;
++		} else {
++			ar->arGroupCryptoLen = value;
++		}
++		break;
++	case IEEE80211_PARAM_COUNTERMEASURES:
++		if (ar->arWmiReady == FALSE) {
++			return -EIO;
++		}
++
++		AR6000_SPIN_LOCK(&ar->arLock, 0);
++		wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		break;
++	default:
++		break;
++	}
++
++	if (profChanged == TRUE) {
++		/*
++		 * profile has changed.  Erase ssid to signal change
++		 */
++		A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++	}
++
++	return ret;
++}
++
++int
++ar6k_ioctl_getparam(struct net_device *dev, struct iw_request_info *info,
++					  void *w, char *extra)
++{
++	return -EIO;				/* for now */
++}
++
++int
++ar6k_ioctl_setkey(struct net_device *dev, struct iw_request_info *info,
++					void *w, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ieee80211req_key *ik = (struct ieee80211req_key *) extra;
++	KEY_USAGE keyUsage;
++	int status;
++	CRYPTO_TYPE keyType = NONE_CRYPT;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	if (0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00",
++					IEEE80211_ADDR_LEN)) {
++		keyUsage = GROUP_USAGE;
++	} else {
++		keyUsage = PAIRWISE_USAGE;
++	}
++
++	switch (ik->ik_type) {
++	case IEEE80211_CIPHER_WEP:
++		keyType = WEP_CRYPT;
++		break;
++	case IEEE80211_CIPHER_TKIP:
++		keyType = TKIP_CRYPT;
++		break;
++	case IEEE80211_CIPHER_AES_CCM:
++		keyType = AES_CRYPT;
++		break;
++	default:
++		break;
++	}
++
++	if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
++		if (NONE_CRYPT == keyType) {
++			return -EIO;
++		}
++
++		status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
++								ik->ik_keylen, (u8 *) & ik->ik_keyrsc,
++								ik->ik_keydata, SYNC_BEFORE_WMIFLAG);
++
++		if (status != A_OK) {
++			return -EIO;
++		}
++	} else {
++		status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
++	}
++
++	return 0;
++}
++
++void ar6k_install_static_wep_keys(AR_SOFTC_T * ar)
++{
++	u8 index;
++	u8 keyUsage;
++
++	for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
++		if (ar->arWepKeyList[index].arKeyLen) {
++			keyUsage = GROUP_USAGE;
++			if (index == ar->arDefTxKeyIndex) {
++				keyUsage |= TX_USAGE;
++			}
++			wmi_addKey_cmd(ar->arWmi,
++						   index,
++						   WEP_CRYPT,
++						   keyUsage,
++						   ar->arWepKeyList[index].arKeyLen,
++						   NULL,
++						   ar->arWepKeyList[index].arKey, NO_SYNC_WMIFLAG);
++		}
++	}
++}
++
++int
++ar6k_ioctl_delkey(struct net_device *dev, struct iw_request_info *info,
++					void *w, char *extra)
++{
++	return 0;
++}
++
++int
++ar6k_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info,
++					 void *w, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *) extra;
++
++	if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE)) {
++		return -EIO;
++	}
++
++	switch (mlme->im_op) {
++	case IEEE80211_MLME_DISASSOC:
++	case IEEE80211_MLME_DEAUTH:
++		/* Not Supported */
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++int
++ar6k_ioctl_setwmmparams(struct net_device *dev,
++						  struct iw_request_info *info, void *w,
++						  char *extra)
++{
++	return -EIO;				/* for now */
++}
++
++int
++ar6k_ioctl_getwmmparams(struct net_device *dev,
++						  struct iw_request_info *info, void *w,
++						  char *extra)
++{
++	return -EIO;				/* for now */
++}
++
++int
++ar6k_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info,
++					  void *w, char *extra)
++{
++	return 0;
++}
++
++int
++ar6k_ioctl_setauthalg(struct net_device *dev,
++						struct iw_request_info *info, void *w, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ieee80211req_authalg *req =
++		(struct ieee80211req_authalg *) extra;
++	int ret = 0;
++
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) {
++		ar->arDot11AuthMode = OPEN_AUTH;
++	} else if (req->auth_alg == AUTH_ALG_LEAP) {
++		ar->arDot11AuthMode = LEAP_AUTH;
++		ar->arPairwiseCrypto = WEP_CRYPT;
++		ar->arGroupCrypto = WEP_CRYPT;
++	} else {
++		ret = -EIO;
++	}
++
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return ret;
++}
++static int
++ar6k_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info,
++					  void *w, char *extra)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	struct ieee80211req_addpmkid *req =
++		(struct ieee80211req_addpmkid *) extra;
++	int status;
++
++	if (ar->arWlanState == WLAN_DISABLED) {
++		return -EIO;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++	AR_DEBUG_PRINTF
++		("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
++		 req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2],
++		 req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5],
++		 req->pi_enable);
++
++	status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid,
++							  req->pi_enable);
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++	if (status != A_OK) {
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	if (wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	/* currently assume only roam times are required */
++	if (wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_SET_ROAM_CTRL_CMD cmd;
++	u8 size = sizeof(cmd);
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++
++	if (copy_from_user(&cmd, userdata, size)) {
++		return -EFAULT;
++	}
++
++	if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
++		if (cmd.info.bssBiasInfo.numBss > 1) {
++			size +=
++				(cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
++		}
++	}
++
++	if (copy_from_user(&cmd, userdata, size)) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	if (wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return 0;
++}
++
++static int
++ar6k_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_POWERSAVE_TIMERS_CMD cmd;
++	u8 size = sizeof(cmd);
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	if (copy_from_user(&cmd, userdata, size)) {
++		return -EFAULT;
++	}
++
++	if (copy_from_user(&cmd, userdata, size)) {
++		return -EFAULT;
++	}
++
++	AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++	if (wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
++		AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++		return -EIO;
++	}
++	AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++	return 0;
++}
++
++
++#if defined(CONFIG_AR6K_DEBUG)
++int dset_debug = 1;
++#define DSET_DEBUG_PRINTF(args...)        if (dset_debug) printk(args);
++#else
++#define DSET_DEBUG_PRINTF(args...)
++#endif
++
++/* Called when a DataSet Open request is received from the Target. */
++void
++ar6k_dset_open_req(void *devt,
++					 u32 id,
++					 u32 targ_handle,
++					 u32 targ_reply_fn, u32 targ_reply_arg)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++
++	DSET_DEBUG_PRINTF("ar6k_dset_open_req id=0x%x\n", id);
++
++	if (!dset_server_alive) {
++		/*
++		 * An attempt to open a Host DataSet before the DataSet Server
++		 * has started.  (Or this Host chooses not to serve DataSets.)
++		 */
++		DSET_DEBUG_PRINTF
++			("DataSet Server not running. Unable to handle open request for id=0x%x\n",
++			 id);
++		wmi_dset_open_reply(ar->arWmi, A_ENOTSUP, 0, 0, 0, targ_handle,
++							targ_reply_fn, targ_reply_arg);
++		return;
++	}
++#if CONFIG_HOST_DSET_SUPPORT
++	if (spin_trylock(&dset_request_lock)) {
++		pending_dset_request.cmd = AR6000_OPEN_REQ;
++		pending_dset_request.u.open_req.id = id;
++		pending_dset_request.u.open_req.targ_handle = targ_handle;
++		pending_dset_request.u.open_req.targ_reply_fn = targ_reply_fn;
++		pending_dset_request.u.open_req.targ_reply_arg = targ_reply_arg;
++		/* Wakeup waiting thread */
++		pending_dset_request_valid = TRUE;
++		wake_up(&dset_request);
++	} else {
++		wmi_dset_open_reply(ar->arWmi, A_EBUSY, 0, 0, 0,
++							targ_handle, targ_reply_fn, targ_reply_arg);
++	}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++/* Called when a DataSet Close is received from the Target. */
++void ar6k_dset_close(void *devt, u32 access_cookie)
++{
++	DSET_DEBUG_PRINTF("ar6k_dset_close access_cookie=0x%x\n",
++					  access_cookie);
++}
++
++/* Called when a DataSet Data Request is received from the Target. */
++void
++ar6k_dset_data_req(void *devt,
++					 u32 access_cookie,
++					 u32 offset,
++					 u32 length,
++					 u32 targ_buf, u32 targ_reply_fn, u32 targ_reply_arg)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
++
++	DSET_DEBUG_PRINTF
++		("ar6k_dset_data_req: Cookie=0x%x offset=%d length=%d\n",
++		 access_cookie, offset, length);
++
++	if (spin_trylock(&dset_request_lock)) {
++		pending_dset_request.cmd = AR6000_DATA_REQ;
++		pending_dset_request.u.data_req.access_cookie = access_cookie;
++		pending_dset_request.u.data_req.offset = offset;
++		pending_dset_request.u.data_req.length = length;
++		pending_dset_request.u.data_req.targ_buf = targ_buf;
++		pending_dset_request.u.data_req.targ_reply_fn = targ_reply_fn;
++		pending_dset_request.u.data_req.targ_reply_arg = targ_reply_arg;
++
++		/* Wakeup waiting thread */
++		pending_dset_request_valid = TRUE;
++		wake_up(&dset_request);
++	} else {
++		wmi_dset_data_reply(ar->arWmi, A_EBUSY, NULL, length,
++							targ_buf, targ_reply_fn, targ_reply_arg);
++	}
++}
++
++/* Init cookie queue */
++static void ar6k_cookie_init(AR_SOFTC_T * ar)
++{
++	u32 i;
++
++	ar->arCookieList = NULL;
++	A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
++
++	for (i = 0; i < MAX_COOKIE_NUM; i++) {
++		ar6k_free_cookie(ar, &s_ar_cookie_mem[i]);
++	}
++}
++
++/* cleanup cookie queue */
++static void ar6k_cookie_cleanup(AR_SOFTC_T * ar)
++{
++	/* It is gone .... */
++	ar->arCookieList = NULL;
++}
++
++/* Init cookie queue */
++static void ar6k_free_cookie(AR_SOFTC_T * ar, struct ar_cookie *cookie)
++{
++	/* Insert first */
++	cookie->arc_list_next = ar->arCookieList;
++	ar->arCookieList = cookie;
++}
++
++/* cleanup cookie queue */
++static struct ar_cookie *ar6k_alloc_cookie(AR_SOFTC_T * ar)
++{
++	struct ar_cookie *cookie;
++
++	cookie = ar->arCookieList;
++	if (cookie != NULL) {
++		ar->arCookieList = cookie->arc_list_next;
++	}
++
++	return cookie;
++}
++
++/* Host-side initialization for DataSets */
++static void ar6k_dset_init(void)
++{
++	spin_lock_init(&dset_request_lock);
++	pending_dset_request_valid = FALSE;
++}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++/* Host-side initialization for General Purpose I/O support */
++static void ar6k_gpio_init(void)
++{
++	gpio_intr_available = FALSE;
++	gpio_data_available = FALSE;
++	gpio_ack_received = FALSE;
++}
++
++/*
++ * Called when a GPIO interrupt is received from the Target.
++ * intr_values shows which GPIO pins have interrupted.
++ * input_values shows a recent value of GPIO pins.
++ */
++void ar6k_gpio_intr_rx(u32 intr_mask, u32 input_values)
++{
++	gpio_intr_results.intr_mask = intr_mask;
++	gpio_intr_results.input_values = input_values;
++	*((volatile u8 *) &gpio_intr_available) = TRUE;
++	wake_up(&arEvent);
++}
++
++/*
++ * This is called when a response is received from the Target
++ * for a previous or ar6k_gpio_input_get or ar6k_gpio_register_get
++ * call.
++ */
++void ar6k_gpio_data_rx(u32 reg_id, u32 value)
++{
++	gpio_reg_results.gpioreg_id = reg_id;
++	gpio_reg_results.value = value;
++	*((volatile u8 *) &gpio_data_available) = TRUE;
++	wake_up(&arEvent);
++}
++
++/*
++ * This is called when an acknowledgement is received from the Target
++ * for a previous or ar6k_gpio_output_set or ar6k_gpio_register_set
++ * call.
++ */
++void ar6k_gpio_ack_rx(void)
++{
++	gpio_ack_received = TRUE;
++	wake_up(&arEvent);
++}
++
++int
++ar6k_gpio_output_set(struct net_device *dev,
++					   u32 set_mask,
++					   u32 clear_mask, u32 enable_mask, u32 disable_mask)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	gpio_ack_received = FALSE;
++	return wmi_gpio_output_set(ar->arWmi,
++							   set_mask, clear_mask, enable_mask,
++							   disable_mask);
++}
++
++static int ar6k_gpio_input_get(struct net_device *dev)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	*((volatile u8 *) &gpio_data_available) = FALSE;
++	return wmi_gpio_input_get(ar->arWmi);
++}
++
++static int
++ar6k_gpio_register_set(struct net_device *dev, u32 gpioreg_id, u32 value)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	gpio_ack_received = FALSE;
++	return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
++}
++
++static int ar6k_gpio_register_get(struct net_device *dev, u32 gpioreg_id)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	*((volatile u8 *) &gpio_data_available) = FALSE;
++	return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
++}
++
++static int ar6k_gpio_intr_ack(struct net_device *dev, u32 ack_mask)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++
++	gpio_intr_available = FALSE;
++	return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
++}
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++/* Structures to export the Wireless Handlers */
++static const iw_handler ath_handlers[] = {
++	(iw_handler) NULL,			/* SIOCSIWCOMMIT */
++	(iw_handler) ar6k_ioctl_giwname,	/* SIOCGIWNAME */
++	(iw_handler) NULL,			/* SIOCSIWNWID */
++	(iw_handler) NULL,			/* SIOCGIWNWID */
++	(iw_handler) ar6k_ioctl_siwfreq,	/* SIOCSIWFREQ */
++	(iw_handler) ar6k_ioctl_giwfreq,	/* SIOCGIWFREQ */
++	(iw_handler) ar6k_ioctl_siwmode,	/* SIOCSIWMODE */
++	(iw_handler) ar6k_ioctl_giwmode,	/* SIOCGIWMODE */
++	(iw_handler) ar6k_ioctl_siwsens,	/* SIOCSIWSENS */
++	(iw_handler) ar6k_ioctl_giwsens,	/* SIOCGIWSENS */
++	(iw_handler) NULL /* not _used */ ,	/* SIOCSIWRANGE */
++	(iw_handler) ar6k_ioctl_giwrange,	/* SIOCGIWRANGE */
++	(iw_handler) NULL /* not used */ ,	/* SIOCSIWPRIV */
++	(iw_handler) NULL /* kernel code */ ,	/* SIOCGIWPRIV */
++	(iw_handler) NULL /* not used */ ,	/* SIOCSIWSTATS */
++	(iw_handler) NULL /* kernel code */ ,	/* SIOCGIWSTATS */
++	(iw_handler) NULL,			/* SIOCSIWSPY */
++	(iw_handler) NULL,			/* SIOCGIWSPY */
++	(iw_handler) NULL,			/* SIOCSIWTHRSPY */
++	(iw_handler) NULL,			/* SIOCGIWTHRSPY */
++	(iw_handler) ar6k_ioctl_siwap,	/* SIOCSIWAP */
++	(iw_handler) ar6k_ioctl_giwap,	/* SIOCGIWAP */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) ar6k_ioctl_iwaplist,	/* SIOCGIWAPLIST */
++	(iw_handler) ar6k_ioctl_siwscan,	/* SIOCSIWSCAN */
++	(iw_handler) ar6k_ioctl_giwscan,	/* SIOCGIWSCAN */
++	(iw_handler) ar6k_ioctl_siwessid,	/* SIOCSIWESSID */
++	(iw_handler) ar6k_ioctl_giwessid,	/* SIOCGIWESSID */
++	(iw_handler) NULL,			/* SIOCSIWNICKN */
++	(iw_handler) NULL,			/* SIOCGIWNICKN */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) ar6k_ioctl_siwrate,	/* SIOCSIWRATE */
++	(iw_handler) ar6k_ioctl_giwrate,	/* SIOCGIWRATE */
++#ifdef NOTYET
++	(iw_handler) ar6k_ioctl_siwrts,	/* SIOCSIWRTS */
++	(iw_handler) ar6k_ioctl_giwrts,	/* SIOCGIWRTS */
++	(iw_handler) ar6k_ioctl_siwfrag,	/* SIOCSIWFRAG */
++	(iw_handler) ar6k_ioctl_giwfrag,	/* SIOCGIWFRAG */
++	(iw_handler) ar6k_ioctl_siwtxpow,	/* SIOCSIWTXPOW */
++	(iw_handler) ar6k_ioctl_giwtxpow,	/* SIOCGIWTXPOW */
++	(iw_handler) ar6k_ioctl_siwretry,	/* SIOCSIWRETRY */
++	(iw_handler) ar6k_ioctl_giwretry,	/* SIOCGIWRETRY */
++	(iw_handler) ar6k_ioctl_siwencode,	/* SIOCSIWENCODE */
++	(iw_handler) ar6k_ioctl_giwencode,	/* SIOCGIWENCODE */
++	(iw_handler) ar6k_ioctl_siwpower,	/* SIOCSIWPOWER */
++	(iw_handler) ar6k_ioctl_giwpower,	/* SIOCGIWPOWER */
++#else
++	(iw_handler) NULL,			/* SIOCSIWRTS */
++	(iw_handler) NULL,			/* SIOCGIWRTS */
++	(iw_handler) NULL,			/* SIOCSIWFRAG */
++	(iw_handler) NULL,			/* SIOCGIWFRAG */
++	(iw_handler) ar6k_ioctl_siwtxpow,	/* SIOCSIWTXPOW */
++	(iw_handler) ar6k_ioctl_giwtxpow,	/* SIOCGIWTXPOW */
++	(iw_handler) ar6k_ioctl_siwretry,	/* SIOCSIWRETRY */
++	(iw_handler) ar6k_ioctl_giwretry,	/* SIOCGIWRETRY */
++	(iw_handler) ar6k_ioctl_siwencode,	/* SIOCSIWENCODE */
++	(iw_handler) ar6k_ioctl_giwencode,	/* SIOCGIWENCODE */
++	(iw_handler) NULL,			/* SIOCSIWPOWER */
++	(iw_handler) NULL,			/* SIOCGIWPOWER */
++#endif							/* NOTYET */
++};
++
++static const iw_handler ath_priv_handlers[] = {
++	(iw_handler) ar6k_ioctl_setparam,	/* SIOCWFIRSTPRIV+0 */
++	(iw_handler) ar6k_ioctl_getparam,	/* SIOCWFIRSTPRIV+1 */
++	(iw_handler) ar6k_ioctl_setkey,	/* SIOCWFIRSTPRIV+2 */
++	(iw_handler) ar6k_ioctl_setwmmparams,	/* SIOCWFIRSTPRIV+3 */
++	(iw_handler) ar6k_ioctl_delkey,	/* SIOCWFIRSTPRIV+4 */
++	(iw_handler) ar6k_ioctl_getwmmparams,	/* SIOCWFIRSTPRIV+5 */
++	(iw_handler) NULL,			/* SIOCWFIRSTPRIV+6 */
++	(iw_handler) NULL,			/* SIOCWFIRSTPRIV+7 */
++	(iw_handler) ar6k_ioctl_addpmkid,	/* SIOCWFIRSTPRIV+8 */
++	(iw_handler) NULL,			/* SIOCWFIRSTPRIV+9 */
++#ifdef NOT_YET
++	(iw_handler) ar6k_ioctl_setauthalg,	/* SIOCWFIRSTPRIV+10 */
++#endif
++};
++
++#define IW_PRIV_TYPE_KEY \
++    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key))
++#define IW_PRIV_TYPE_DELKEY \
++    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key))
++#define IW_PRIV_TYPE_MLME \
++    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme))
++#define IW_PRIV_TYPE_ADDPMKID \
++    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid))
++
++static const struct iw_priv_args ar6k_priv_args[] = {
++	{IEEE80211_IOCTL_SETKEY,
++	 IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0, "setkey"},
++	{IEEE80211_IOCTL_DELKEY,
++	 IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0, "delkey"},
++	{IEEE80211_IOCTL_SETPARAM,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setparam"},
++	{IEEE80211_IOCTL_GETPARAM,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getparam"},
++	{IEEE80211_IOCTL_SETWMMPARAMS,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0, "setwmmparams"},
++	{IEEE80211_IOCTL_GETWMMPARAMS,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3,
++	 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getwmmparams"},
++	{IEEE80211_IOCTL_ADDPMKID,
++	 IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0, "addpmkid"},
++};
++
++static void ar6k_ioctl_iwsetup(struct iw_handler_def *def)
++{
++#define N(a) (sizeof(a) / sizeof(a[0]))
++	def->private_args = (struct iw_priv_args *) ar6k_priv_args;
++	def->num_private_args = N(ar6k_priv_args);
++#undef N
++}
++
++static struct iw_handler_def ath_iw_handler_def = {
++#define N(a) (sizeof (a) / sizeof (a[0]))
++	.standard = (iw_handler *) ath_handlers,
++	.num_standard = N(ath_handlers),
++	.private = (iw_handler *) ath_priv_handlers,
++	.num_private = N(ath_priv_handlers),
++#undef N
++};
++
++/* Get power mode command */
++static int
++ar6k_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
++{
++	AR_SOFTC_T *ar = (AR_SOFTC_T *) dev->priv;
++	WMI_POWER_MODE_CMD power_mode;
++	int ret = 0;
++
++	if (ar->arWmiReady == FALSE) {
++		return -EIO;
++	}
++
++	power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
++	if (copy_to_user
++		(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
++		ret = -EFAULT;
++	}
++
++	return ret;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/bmi.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/bmi.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,450 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the routines that implement the Boot loader messaging
++ * interface
++ */
++
++#include "ar6k.h"
++#include "hif.h"
++#include "include/athdrv.h"
++#include "include/htc.h"
++#include "include/AR6000_bmi.h"
++#include "include/hw/mbox_host_reg.h"
++
++/*
++Although we had envisioned BMI to run on top of HTC, this is not what the
++final implementation boiled down to on dragon. Its a part of BSP and does
++not use the HTC protocol either. On the host side, however, we were still
++living with the original idea. I think the time has come to accept the truth
++and separate it from HTC which has been carrying BMI's burden all this while.
++It shall make HTC state machine relatively simpler
++*/
++
++#define BMI_COMMUNICATION_TIMEOUT       100000
++
++/* ------ Static Variables ------ */
++
++/* ------ Global Variable Declarations ------- */
++u8 bmiDone;
++extern u32 debugbmi;
++
++#ifdef CONFIG_AR6K_DEBUG
++#define AR_DEBUG_PRINTF(...)        if (debugbmi) A_PRINTF(__VA_ARGS__);
++#else
++#define AR_DEBUG_PRINTF(...)
++#endif
++
++int bmiBufferSend(struct sdio_func *func, u8 * buffer, u32 length);
++int bmiBufferReceive(struct sdio_func *func, u8 * buffer, u32 length);
++
++/* APIs visible to the driver */
++void BMIInit(void)
++{
++	bmiDone = FALSE;
++}
++
++int BMIDone(struct sdio_func *device)
++{
++	int status;
++	u32 cid;
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF("BMI Done: Enter (device: 0x%p)\n", device);
++	bmiDone = TRUE;
++	cid = BMI_DONE;
++
++	sdio_claim_host(device);
++	status = bmiBufferSend(device, (u8 *) & cid, sizeof(cid));
++	sdio_release_host(device);
++
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++	AR_DEBUG_PRINTF("BMI Done: Exit\n");
++
++	return A_OK;
++}
++
++int BMIGetTargetId(struct sdio_func *device, u32 * id)
++{
++	int status;
++	u32 cid;
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF("BMI Get Target ID: Enter (device: 0x%p)\n", device);
++	cid = BMI_GET_TARGET_ID;
++
++	sdio_claim_host(device);
++	status = bmiBufferSend(device, (u8 *) & cid, sizeof(cid));
++	sdio_release_host(device);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++
++#if 0
++	sdio_claim_host(device);
++	status = bmiBufferReceive(device, (u8 *) id, sizeof(*id));
++	sdio_release_host(device);
++
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to read from the device\n");
++		return A_ERROR;
++	}
++	AR_DEBUG_PRINTF("BMI Get Target ID: Exit (ID: 0x%x)\n", *id);
++
++#endif
++
++	return A_OK;
++}
++
++int
++BMIReadMemory(struct sdio_func *device,
++			  u32 address, u8 * buffer, u32 length)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	u32 remaining, rxlen;
++	const u32 header = sizeof(cid) + sizeof(address) + sizeof(length);
++	u8 data[BMI_DATASZ_MAX + header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
++		 device, address, length);
++
++	cid = BMI_READ_MEMORY;
++
++	remaining = length;
++	while (remaining) {
++		rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
++		offset = 0;
++		A_MEMCPY(&data[offset], &cid, sizeof(cid));
++		offset += sizeof(cid);
++		A_MEMCPY(&data[offset], &address, sizeof(address));
++		offset += sizeof(address);
++		A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen));
++		offset += sizeof(length);
++		status = bmiBufferSend(device, data, offset);
++		if (status != A_OK) {
++			AR_DEBUG_PRINTF("Unable to write to the device\n");
++			return A_ERROR;
++		}
++		status = bmiBufferReceive(device, data, rxlen);
++		if (status != A_OK) {
++			AR_DEBUG_PRINTF("Unable to read from the device\n");
++			return A_ERROR;
++		}
++		A_MEMCPY(&buffer[length - remaining], data, rxlen);
++		remaining -= rxlen;
++		address += rxlen;
++	}
++
++	AR_DEBUG_PRINTF("BMI Read Memory: Exit\n");
++	return A_OK;
++}
++
++int
++BMIWriteMemory(struct sdio_func *device,
++			   u32 address, u8 * buffer, u32 length)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	u32 remaining, txlen;
++	const u32 header = sizeof(cid) + sizeof(address) + sizeof(length);
++	u8 data[BMI_DATASZ_MAX + header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
++		 device, address, length);
++
++	cid = BMI_WRITE_MEMORY;
++
++	remaining = length;
++	while (remaining) {
++		txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
++			remaining : (BMI_DATASZ_MAX - header);
++		offset = 0;
++		A_MEMCPY(&data[offset], &cid, sizeof(cid));
++		offset += sizeof(cid);
++		A_MEMCPY(&data[offset], &address, sizeof(address));
++		offset += sizeof(address);
++		A_MEMCPY(&data[offset], &txlen, sizeof(txlen));
++		offset += sizeof(txlen);
++		A_MEMCPY(&data[offset], &buffer[length - remaining], txlen);
++		offset += txlen;
++		status = bmiBufferSend(device, data, offset);
++		if (status != A_OK) {
++			AR_DEBUG_PRINTF("Unable to write to the device\n");
++			return A_ERROR;
++		}
++		remaining -= txlen;
++		address += txlen;
++	}
++
++	AR_DEBUG_PRINTF("BMI Write Memory: Exit\n");
++
++	return A_OK;
++}
++
++int BMIExecute(struct sdio_func *device, u32 address, u32 * param)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	const u32 header = sizeof(cid) + sizeof(address) + sizeof(*param);
++	u8 data[header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
++		 device, address, *param);
++
++	cid = BMI_EXECUTE;
++
++	offset = 0;
++	A_MEMCPY(&data[offset], &cid, sizeof(cid));
++	offset += sizeof(cid);
++	A_MEMCPY(&data[offset], &address, sizeof(address));
++	offset += sizeof(address);
++	A_MEMCPY(&data[offset], param, sizeof(*param));
++	offset += sizeof(*param);
++	status = bmiBufferSend(device, data, offset);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++
++	status = bmiBufferReceive(device, data, sizeof(*param));
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to read from the device\n");
++		return A_ERROR;
++	}
++
++	A_MEMCPY(param, data, sizeof(*param));
++
++	AR_DEBUG_PRINTF("BMI Execute: Exit (param: %d)\n", *param);
++	return A_OK;
++}
++
++int BMISetAppStart(struct sdio_func *device, u32 address)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	const u32 header = sizeof(cid) + sizeof(address);
++	u8 data[header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
++		 device, address);
++
++	cid = BMI_SET_APP_START;
++
++	offset = 0;
++	A_MEMCPY(&data[offset], &cid, sizeof(cid));
++	offset += sizeof(cid);
++	A_MEMCPY(&data[offset], &address, sizeof(address));
++	offset += sizeof(address);
++	status = bmiBufferSend(device, data, offset);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF("BMI Set App Start: Exit\n");
++	return A_OK;
++}
++
++int BMIReadSOCRegister(struct sdio_func *device, u32 address, u32 * param)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	const u32 header = sizeof(cid) + sizeof(address);
++	u8 data[header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
++		 device, address);
++
++	cid = BMI_READ_SOC_REGISTER;
++
++	offset = 0;
++	A_MEMCPY(&data[offset], &cid, sizeof(cid));
++	offset += sizeof(cid);
++	A_MEMCPY(&data[offset], &address, sizeof(address));
++	offset += sizeof(address);
++	status = bmiBufferSend(device, data, offset);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++
++	status = bmiBufferReceive(device, data, sizeof(*param));
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to read from the device\n");
++		return A_ERROR;
++	}
++	A_MEMCPY(param, data, sizeof(*param));
++
++	AR_DEBUG_PRINTF("BMI Read SOC Register: Exit (value: %d)\n", *param);
++	return A_OK;
++}
++
++int BMIWriteSOCRegister(struct sdio_func *device, u32 address, u32 param)
++{
++	u32 cid;
++	int status;
++	u32 offset;
++	const u32 header = sizeof(cid) + sizeof(address) + sizeof(param);
++	u8 data[header];
++
++	if (bmiDone) {
++		AR_DEBUG_PRINTF("Command disallowed\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF
++		("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
++		 device, address, param);
++
++	cid = BMI_WRITE_SOC_REGISTER;
++
++	offset = 0;
++	A_MEMCPY(&data[offset], &cid, sizeof(cid));
++	offset += sizeof(cid);
++	A_MEMCPY(&data[offset], &address, sizeof(address));
++	offset += sizeof(address);
++	A_MEMCPY(&data[offset], &param, sizeof(param));
++	offset += sizeof(param);
++	status = bmiBufferSend(device, data, offset);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF("Unable to write to the device\n");
++		return A_ERROR;
++	}
++
++	AR_DEBUG_PRINTF("BMI Read SOC Register: Exit\n");
++	return A_OK;
++}
++
++/* BMI Access routines */
++int bmiBufferSend(struct sdio_func *func, u8 * buffer, u32 length)
++{
++	int ret;
++	u32 timeout;
++	u32 address;
++	u8 cmdCredits;
++
++	cmdCredits = 0;
++	timeout = BMI_COMMUNICATION_TIMEOUT;
++	while (timeout-- && !cmdCredits) {
++		/* Read the counter register to get the command credits */
++		address =
++			COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
++		cmdCredits = sdio_readb(func, address, &ret);
++		if (ret) {
++			AR_DEBUG_PRINTF
++				("Unable to decrement the command credit count register: %d\n",
++				 ret);
++			return A_ERROR;
++		}
++	}
++
++	if (!cmdCredits) {
++		AR_DEBUG_PRINTF("BMI Communication timeout\n");
++		return A_ERROR;
++	}
++
++	address = HIF_MBOX_START_ADDR(ENDPOINT1);
++	ret = sdio_memcpy_toio(func, address, buffer, length);
++	if (ret) {
++		AR_DEBUG_PRINTF("Unable to send the BMI data to the device: %d\n",
++						ret);
++		return A_ERROR;
++	}
++
++	return 0;
++}
++
++int bmiBufferReceive(struct sdio_func *func, u8 * buffer, u32 length)
++{
++	int ret;
++	u32 address;
++	u32 timeout;
++	u8 cmdCredits;
++
++	cmdCredits = 0;
++	timeout = BMI_COMMUNICATION_TIMEOUT;
++	while (timeout-- && !cmdCredits) {
++		/* Read the counter register to get the command credits */
++		address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
++		cmdCredits = sdio_readb(func, address, &ret);
++		if (ret) {
++			AR_DEBUG_PRINTF
++				("Unable to decrement the command credit count register: %d\n",
++				 ret);
++			return A_ERROR;
++		}
++	}
++
++	if (!cmdCredits) {
++		AR_DEBUG_PRINTF("BMI Communication timeout\n");
++		return A_ERROR;
++	}
++
++	address = HIF_MBOX_START_ADDR(ENDPOINT1);
++	ret = sdio_memcpy_fromio(func, buffer, address, length);
++	if (ret) {
++		AR_DEBUG_PRINTF("Unable to read the BMI data from the device\n");
++		return A_ERROR;
++	}
++
++	return 0;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/hif.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/hif.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,204 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the interaction with the SDIO
++ * driver
++ */
++#include "ar6k.h"
++#include "hif.h"
++
++/* ------ Static Variables ------ */
++
++/* ------ Global Variable Declarations ------- */
++
++const struct sdio_device_id ar6k_id_table[] = {
++	{ SDIO_DEVICE(SDIO_ANY_ID, 0x10b) },
++	{ SDIO_DEVICE(SDIO_ANY_ID, 0x10a) },
++	{ SDIO_DEVICE(SDIO_ANY_ID, 0x109) },
++	{ SDIO_DEVICE(SDIO_ANY_ID, 0x108) },
++	{},
++};
++
++struct sdio_driver ar6k_driver = {
++	.name = "sdio_wlan",
++	.id_table = ar6k_id_table,
++	.probe = hifDeviceInserted,
++	.remove = hifDeviceRemoved,
++};
++
++
++HTC_CALLBACKS htcCallbacks;
++
++#define PFX "ar6k_hif: "
++#ifdef CONFIG_AR6K_DEBUG
++#define ATH_DEBUG_ERROR 1
++#define ATH_DEBUG_WARN  2
++#define ATH_DEBUG_TRACE 3
++#define _AR_DEBUG_PRINTX_ARG(arg...) arg
++#define AR_DEBUG_PRINTF(lvl, args) \
++		A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);
++#else
++#define AR_DEBUG_PRINTF(lvl, args)
++#endif
++
++/* ------ Functions ------ */
++void
++HIFRegisterCallbacks (HTC_CALLBACKS *callbacks)
++{
++	/* Store the callback and event handlers */
++	htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
++	htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
++	htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
++	htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
++	htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
++	htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
++	htcCallbacks.dsrHandler = callbacks->dsrHandler;
++
++	printk("###### REGISTERING AR6k DRIVER ######## \n");
++
++	/* Register with bus driver core */
++	if (sdio_register_driver(&ar6k_driver))
++		printk(KERN_ERR "failed to register SDIO driver\n");
++}
++
++void
++HIFShutDownDevice(struct sdio_func *func)
++{
++	if (func)
++		sdio_disable_func(func);
++	sdio_unregister_driver(&ar6k_driver);
++}
++
++void
++hifRWCompletionHandler(struct mmc_request *mrq)
++{
++	int status;
++	void *context;
++
++	if (!mrq->cmd->error) {
++		status = A_OK;
++	} else {
++		status = A_ERROR;
++	}
++	context = (void *)mrq->done_data;
++
++	htcCallbacks.rwCompletionHandler(context, status);
++	kfree(mrq->data->sg);
++	kfree(mrq->data);
++	kfree(mrq->cmd);
++	kfree(mrq);
++}
++
++void
++hifIRQHandler(struct sdio_func *func)
++{
++	printk("DEBUG: %s\n", __func__);
++	htcCallbacks.dsrHandler(func);
++}
++
++
++int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
++{
++	int ret;
++
++	printk("%s()\n", __FUNCTION__);
++
++	sdio_claim_host(func);
++
++	printk("%s(): host claimed\n", __FUNCTION__);
++
++	ret = sdio_enable_func(func);
++	if (ret) {
++		printk("%s(), ret %d\n", __FUNCTION__, ret);
++		sdio_release_host(func);
++		return ret;
++	}
++
++	ret = sdio_claim_irq(func, hifIRQHandler);
++	if (ret) {
++		printk("%s(), claim_irq failed ret %d\n", __FUNCTION__, ret);
++		sdio_disable_func(func);
++		sdio_release_host(func);
++		return ret;
++	}
++
++	sdio_release_host(func);
++
++	/*
++	 * Adding a wait of around a second before we issue the very first
++	 * command to dragon. During the process of loading/unloading the
++	 * driver repeatedly it was observed that we get a data timeout
++	 * while accessing function 1 registers in the chip. The theory at
++	 * this point is that some initialization delay in dragon is
++	 * causing the SDIO state in dragon core to be not ready even after
++	 * the ready bit indicates that function 1 is ready. Accomodating
++	 * for this behavior by adding some delay in the driver before it
++	 * issues the first command after switching on dragon. Need to
++	 * investigate this a bit more - TODO
++	 */
++
++	A_MDELAY(800);
++
++	/* Inform HTC */
++	if ((htcCallbacks.deviceInsertedHandler(func)) != A_OK) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
++		return FALSE;
++	}
++
++
++
++	return 0;
++}
++
++void
++HIFAckInterrupt(struct sdio_func *func)
++{
++	/* XXX; should done by the stack already, not sure */
++#if 0
++	SDIO_STATUS status;
++	/* Acknowledge our function IRQ */
++	status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ACK_IRQ,
++							   NULL, 0);
++#endif
++}
++
++int HIFUnMaskInterrupt(struct sdio_func *func)
++{
++	printk("DEBUG: %s\n", __func__);
++	return 0;
++//	return sdio_claim_irq(func, hifIRQHandler);
++}
++
++void HIFMaskInterrupt(struct sdio_func *func)
++{
++	printk("DEBUG: %s\n", __func__);
++//	sdio_release_irq(func);
++}
++
++void
++hifDeviceRemoved(struct sdio_func *func)
++{
++	printk("DEBUG: %s\n", __func__);
++
++	sdio_claim_host(func);
++
++	sdio_release_irq(func);
++	sdio_disable_func(func);
++
++	sdio_release_host(func);
++
++	htcCallbacks.deviceRemovedHandler(func);
++}
++
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/hif.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/hif.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++   $ATH_LICENSE_AR6K0$
++ *
++ */
++
++#include "include/athdefs.h"
++#include "include/osapi.h"
++#include "include/hif.h"
++
++#define MANUFACTURER_ID_BASE               0x100
++#define FUNCTION_CLASS                     0x0
++#define MANUFACTURER_CODE                  0x271
++
++#define BUS_REQUEST_MAX_NUM                32
++
++#define SDIO_CLOCK_FREQUENCY_DEFAULT       24000000
++#define SDIO_CLOCK_FREQUENCY_REDUCED       12000000
++
++#define SDWLAN_ENABLE_DISABLE_TIMEOUT      20
++#define FLAGS_CARD_ENAB                    0x02
++#define FLAGS_CARD_IRQ_UNMSK               0x04
++
++#define HIF_MBOX_BLOCK_SIZE                128
++#define HIF_MBOX_BASE_ADDR                 0x800
++#define HIF_MBOX_WIDTH                     0x800
++#define HIF_MBOX0_BLOCK_SIZE               1
++#define HIF_MBOX1_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX2_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX3_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
++
++#define HIF_MBOX_START_ADDR(mbox)                        \
++    HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
++
++#define HIF_MBOX_END_ADDR(mbox)	                         \
++    HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
++
++
++int
++hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
++
++void hifDeviceRemoved(struct sdio_func *func);
++
++void hifRWCompletionHandler(struct mmc_request *mrq);
++
++void hifIRQHandler(struct sdio_func *func);
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,426 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Copyright (c) 2007 Felix Fietkau <nbd at openwrt.org>
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the HTC APIs that are exposed to higher layers.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++HTC_TARGET *AtherosTargetList[HIF_MAX_DEVICES];
++HTC_GLOBAL_EVENT_TABLE AtherosEventTable;
++A_MUTEX_T creditCS, counterCS, instanceCS;
++A_WAITQUEUE_HEAD htcEvent;
++
++#ifdef CONFIG_AR6K_DEBUG
++extern u32 debughtc;
++extern u32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++
++extern int tx_attempt[HTC_MAILBOX_NUM_MAX];	/* Num of attempts to add */
++extern int tx_post[HTC_MAILBOX_NUM_MAX];	/* Num of attemps succeded */
++extern int tx_complete[HTC_MAILBOX_NUM_MAX];	/* Num of tx complete */
++
++/* Initializes the HTC module */
++int HTCInit(void)
++{
++	HTC_CALLBACKS htcCallbacks;
++	static u8 HTCInitialized = FALSE;
++
++
++	printk("##### %s() #########\n", __FUNCTION__);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n"));
++	if (HTCInitialized) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
++		return A_OK;
++	}
++
++	A_MEMZERO(&AtherosEventTable, sizeof(HTC_GLOBAL_EVENT_TABLE));
++	A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
++	A_INIT_WAITQUEUE_HEAD(&htcEvent);
++
++	htcCallbacks.deviceInsertedHandler = htcTargetInsertedHandler;
++	htcCallbacks.deviceRemovedHandler = htcTargetRemovedHandler;
++	htcCallbacks.rwCompletionHandler = htcRWCompletionHandler;
++#ifdef CF
++	htcCallbacks.deviceInterruptEnabler = htcInterruptEnabler;
++	htcCallbacks.deviceInterruptDisabler = htcInterruptDisabler;
++#endif							/* CF */
++
++	htcCallbacks.dsrHandler = htcDSRHandler;
++	HIFRegisterCallbacks(&htcCallbacks);
++	HTCInitialized = TRUE;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
++	return A_OK;
++}
++
++/* Enables Dragon interrupts */
++int HTCStart(HTC_TARGET * target)
++{
++	int status;
++	u32 address;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
++
++	/* Unmask the host controller interrupts */
++	status = HIFUnMaskInterrupt(target->device);
++	if (status) {
++		printk("UnmaskInterrupt returned %d\n", status);
++		return status;
++	}
++
++	printk("%s(): Interrupts unmasked\n", __FUNCTION__);
++
++	/* Enable all the interrupts except for the dragon interrupt */
++	target->table.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
++		INT_STATUS_ENABLE_CPU_SET(0x01) |
++		INT_STATUS_ENABLE_COUNTER_SET(0x01) |
++		INT_STATUS_ENABLE_MBOX_DATA_SET(0x0F);
++
++	/* Set up the CPU Interrupt Status Register */
++	target->table.cpu_int_status_enable =
++		CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
++
++	/* Set up the Error Interrupt Status Register */
++	target->table.error_status_enable =
++		ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
++		ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
++
++	/* Set up the Counter Interrupt Status Register */
++	target->table.counter_int_status_enable =
++		COUNTER_INT_STATUS_ENABLE_BIT_SET(0xFF);
++
++	/* Write to the register */
++	address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++	status =
++		sdio_memcpy_toio(target->device, address,
++						 &target->table.int_status_enable, 4);
++	if (status) {
++		/* Can't write it for some reason */
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("Failed to enable INT_STATUS_ENABLE | CPU_INT_STATUS_ENABLE | ERROR_STATUS_ENABLE | COUNTER_INT_STATUS_ENABLE, err: %d\n",
++						 status));
++		HTCStop(target);
++		return A_ERROR;
++	}
++#ifdef CONFIG_AR6K_DEBUG
++	txcreditintrenable[ENDPOINT1] += 1;
++	txcreditintrenable[ENDPOINT2] += 1;
++	txcreditintrenable[ENDPOINT3] += 1;
++	txcreditintrenable[ENDPOINT4] += 1;
++	txcreditintrenableaggregate[ENDPOINT1] += 1;
++	txcreditintrenableaggregate[ENDPOINT2] += 1;
++	txcreditintrenableaggregate[ENDPOINT3] += 1;
++	txcreditintrenableaggregate[ENDPOINT4] += 1;
++#endif							/* DEBUG */
++
++	/* Wait on a timed semaphore that will get signalled once the block
++	   size negotiation with the target has completed. Furthermore, we
++	   have to do it only once during the lifetime of the target detection
++	 */
++	if (!target->ready) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++				("Waiting for the block size negotiation to finish\n"));
++		A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(htcEvent,
++						   (target->ready == TRUE),
++						   HTC_TARGET_RESPONSE_TIMEOUT);
++
++		if (target->ready) {
++			status = A_OK;
++		} else {
++			status = A_ERROR;
++			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++							("Failed to negotiate the block sizes\n"));
++			HTCStop(target);
++		}
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
++	return status;
++}
++
++/*
++ * Provides an interface for the higher layer module to register for
++ * different events supported by the HTC module
++ */
++int
++HTCEventReg(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++			HTC_EVENT_ID eventId, HTC_EVENT_HANDLER eventHandler,
++			void *param)
++{
++	/*
++	 * Add the event handler against the specified event and store it in
++	 * the event table
++	 */
++	int status;
++	HTC_ENDPOINT *endPoint;
++	HTC_EVENT_INFO eventInfo;
++	HTC_DATA_REQUEST_QUEUE *sendQueue, *recvQueue;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++					("HTCEventReg: Enter (eventId: 0x%x, endPointId: %d)\n",
++					 eventId, endPointId));
++
++	if (eventHandler) {
++		if ((status = addToEventTable(target, endPointId, eventId,
++									  eventHandler, param)) != A_OK) {
++			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++							("Could not add the event 0x%x to the event table\n",
++							 eventId));
++			return status;
++		}
++	}
++
++	switch (eventId) {
++	case HTC_TARGET_AVAILABLE:
++		if (eventHandler != NULL) {
++			/*
++			 * Dispatch a Target Available event for all the targets
++			 * present. Iterate through the global list of targets but
++			 * currently we shall simply look for the first instance
++			 */
++			target = AtherosTargetList[0];
++			if (target != NULL) {
++				FRAME_EVENT(eventInfo, (u8 *) target->device,
++							sizeof(struct sdio_func *),
++							sizeof(struct sdio_func *), A_OK, NULL);
++				dispatchEvent(target, ENDPOINT_UNUSED, eventId,
++							  &eventInfo);
++			}
++		} else {
++			/* Initiate a shut down procedure */
++		}
++		break;
++
++	case HTC_TARGET_UNAVAILABLE:
++		break;
++
++	case HTC_BUFFER_RECEIVED:
++		if (eventHandler == NULL) {
++			/* Flush the queue before unregistering the event handler */
++			endPoint = &target->endPoint[endPointId];
++			recvQueue = &endPoint->recvQueue;
++			flushMboxQueue(endPoint, recvQueue, HTC_BUFFER_RECEIVED);
++		}
++		break;
++
++	case HTC_SKB_RECEIVED:
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("skb not handled currently\n"));
++		break;
++
++	case HTC_BUFFER_SENT:
++		if (eventHandler == NULL) {
++			/* Flush the queue before unregistering the event handler */
++			endPoint = &target->endPoint[endPointId];
++			sendQueue = &endPoint->sendQueue;
++			flushMboxQueue(endPoint, sendQueue, HTC_BUFFER_SENT);
++		}
++		break;
++
++	case HTC_SKB_SENT:
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("skb not handled currently\n"));
++		break;
++
++	case HTC_DATA_AVAILABLE:
++		/*
++		 * Dispatch a data available event with the length. We are
++		 * not handling this specific case currently because registering
++		 * for HTC_DATA_AVAILABLE event is a part of the discipline
++		 * that is imposed before one starts using HTC
++		 */
++		break;
++
++	default:
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("Unknown Event ID: 0x%x\n", eventId));
++		return A_EINVAL;
++	}
++
++	/* Check if its a call for registering the event or unregistering it */
++	if (eventHandler == NULL) {
++		if ((status = removeFromEventTable(target, endPointId,
++										   eventId)) != A_OK) {
++			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++							("Could not remove the event 0x%x from the event table\n",
++							 eventId));
++			return status;
++		}
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCEventReg: Exit\n"));
++	return A_OK;
++}
++
++/*
++ * Commit an address to either WINDOW_WRITE_ADDR_REG or to
++ * WINDOW_READ_ADDR_REG.  We write the least significan byte (LSB)
++ * last, since it triggers the read/write.
++ */
++static void
++_WRITE_WINDOW_ADDR(HTC_TARGET * target, u32 whichreg, u32 value)
++{
++	u32 window_addr;
++	u32 address;
++
++	window_addr = value;
++	address = getRegAddr(whichreg, ENDPOINT_UNUSED);
++
++	sdio_memcpy_toio(target->device, address + 1,
++					 ((u8 *) & window_addr) + 1, 3);
++	sdio_memcpy_toio(target->device, address, (u8 *) & window_addr, 1);
++}
++
++void HTCStop(HTC_TARGET * target)
++{
++	u32 count;
++	int status;
++	u32 address;
++	u32 window_data;
++	HTC_ENDPOINT *endPoint;
++	HTC_REG_REQUEST_LIST *regList;
++	HTC_REG_REQUEST_ELEMENT *element;
++	HTC_DATA_REQUEST_QUEUE *sendQueue;
++	HTC_DATA_REQUEST_QUEUE *recvQueue;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStop: Enter"));
++
++	/* Disable all the dragon interrupts */
++	target->table.int_status_enable = 0;
++	target->table.cpu_int_status_enable = 0;
++	target->table.error_status_enable = 0;
++	target->table.counter_int_status_enable = 0;
++
++	address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++	sdio_writel(target->device, target->table.int_status_enable, address,
++				&status);
++	AR_DEBUG_ASSERT(status == 0);
++
++	/* Disable the host controller interrupts */
++	HIFMaskInterrupt(target->device);
++
++	/* Flush all the queues and return the buffers to their owner */
++	for (count = ENDPOINT1; count <= ENDPOINT4; count++) {
++		endPoint = &target->endPoint[count];
++
++		/* Decrement the number of credits consumed */
++		if (endPoint->txCreditsConsumed) {
++			address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, count);
++			status =
++				sdio_writesb(target->device, address,
++							 endPoint->txCreditsAvailable,
++							 endPoint->txCreditsConsumed);
++			AR_DEBUG_ASSERT(status == 0);
++		}
++
++		SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++		SET_TX_CREDITS_CONSUMED(endPoint, 0);
++
++#ifdef CONFIG_AR6K_DEBUG
++		txcreditsavailable[count] = GET_TX_CREDITS_AVAILABLE(endPoint);
++		txcreditsconsumed[count] = GET_TX_CREDITS_CONSUMED(endPoint);
++#endif
++
++		endPoint->txCreditsIntrEnable = FALSE;
++		endPoint->rxLengthPending = 0;
++		endPoint->enabled = FALSE;
++
++		/* Flush the Pending Receive Queue */
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("Flushing the recv queue & returning the buffers\n"));
++
++		recvQueue = &endPoint->recvQueue;
++		flushMboxQueue(endPoint, recvQueue, HTC_BUFFER_RECEIVED);
++
++		/* Flush the Pending Send Queue */
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("Flushing the send queue & returning the buffers\n"));
++		sendQueue = &endPoint->sendQueue;
++		flushMboxQueue(endPoint, sendQueue, HTC_BUFFER_SENT);
++	}
++
++	/* Clear the tx counters */
++	memset(tx_attempt, 0, sizeof(tx_attempt));
++	memset(tx_post, 0, sizeof(tx_post));
++	memset(tx_complete, 0, sizeof(tx_complete));
++
++	/* Attempting a force reset of the target */
++	window_data = RESET_CONTROL_COLD_RST_MASK;
++	address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
++	sdio_writel(target->device, window_data, address, &status);
++	AR_DEBUG_ASSERT(status == 0);
++
++	_WRITE_WINDOW_ADDR(target, WINDOW_WRITE_ADDR_REG,
++					   RESET_CONTROL_ADDRESS);
++
++	/*
++	 * Read back the RESET CAUSE register to ensure that the cold reset
++	 * went through.
++	 */
++	mdelay(2000);				/* 2 second delay to allow dragon to
++								   settle down */
++	_WRITE_WINDOW_ADDR(target, WINDOW_READ_ADDR_REG, RESET_CAUSE_ADDRESS);
++
++	window_data = 0;
++	address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
++	sdio_writel(target->device, window_data, address, &status);
++	AR_DEBUG_ASSERT(status == 0);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("window data: %d\n", window_data));
++	window_data &= RESET_CAUSE_LAST_MASK;
++
++	if (window_data != 2) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("Unable to cold reset the target\n"));
++	}
++
++	/*
++	 * Ensure that all the pending asynchronous register read/writes have
++	 * been finished.
++	 */
++	regList = &target->regList;
++	for (count = 0; count < HTC_REG_REQUEST_LIST_SIZE; count++) {
++		element = &regList->element[count];
++		AR_DEBUG_ASSERT(IS_ELEMENT_FREE(element));
++	}
++
++	/* Initialize the shadow copy of the target register table */
++	A_MEMZERO(&target->table, sizeof(HTC_REGISTER_TABLE));
++	target->ready = FALSE;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStop: Exit"));
++}
++
++
++void HTCShutDown(HTC_TARGET * target)
++{
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCShutDown: Enter\n"));
++
++	if (target != NULL) {
++		HIFShutDownDevice(target->device);
++		delTargetInstance(target);
++		A_MEMZERO(target, sizeof(HTC_TARGET));
++		A_FREE(target);
++	} else {
++		HIFShutDownDevice(NULL);
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCShutDown: Exit\n"));
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_events.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_events.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,886 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the different events and callbacks
++ * from the hardware interface layer.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern A_MUTEX_T instanceCS, counterCS, creditCS;
++extern A_WAITQUEUE_HEAD htcEvent;
++
++#ifdef CONFIG_AR6K_DEBUG
++extern u32 debughtc;
++extern u32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++
++extern u32 tx_complete[HTC_MAILBOX_NUM_MAX];	/* Num of tx complete */
++
++/* ------ Static Variables ------ */
++
++
++
++int htcRWCompletionHandler(void *context, int status)
++{
++	HTC_QUEUE_ELEMENT *element;
++
++	element = (HTC_QUEUE_ELEMENT *) context;
++	AR_DEBUG_ASSERT(element != NULL);
++
++	return (element->completionCB(element, status));
++}
++
++int htcTxCompletionCB(HTC_DATA_REQUEST_ELEMENT * element, int status)
++{
++	HTC_TARGET *target;
++	HTC_ENDPOINT_ID endPointId;
++	HTC_ENDPOINT *endPoint;
++	HTC_EVENT_INFO eventInfo;
++	HTC_MBOX_BUFFER *mboxBuffer;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("htcTxCompletionCB - Enter\n"));
++
++	/* Get the context */
++	mboxBuffer = GET_MBOX_BUFFER(element);
++	AR_DEBUG_ASSERT(mboxBuffer != NULL);
++	endPoint = mboxBuffer->endPoint;
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++					("mboxBuffer: 0x%p, buffer: 0x%p, endPoint(%d): 0x%p, target: 0x%p\n",
++					 mboxBuffer, mboxBuffer->buffer, endPointId, endPoint,
++					 target));
++
++	/* Return the buffer to the user if the transmission was not
++	   successful */
++	if (status) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++						("Frame transmission failed\n"));
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++						("EndPoint: %d, Tx credits available: %d\n",
++						 endPointId, GET_TX_CREDITS_AVAILABLE(endPoint)));
++		/*
++		 * In the failure case it is possible that while queueing of the
++		 * request itself it returned an error status in which case we
++		 * would have dispatched an event and freed the element there
++		 * itself. Ideally if it failed to queue the request then it
++		 * should not generate a callback but we are being a little
++		 * conservative.
++		 */
++		if (!(IS_ELEMENT_FREE(element))) {
++			mboxBuffer->buffer += HTC_HEADER_LEN;
++			FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++						mboxBuffer->bufferLength, mboxBuffer->actualLength,
++						A_ECANCELED, mboxBuffer->cookie);
++			RECYCLE_DATA_REQUEST_ELEMENT(element);
++			dispatchEvent(target, endPointId, HTC_BUFFER_SENT, &eventInfo);
++			AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++							("htcTxCompletionCB - Exit\n"));
++		}
++		return 0;
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++					("Frame transmission complete\n"));
++
++	/*
++	 * The user should see the actual length and buffer length
++	 * to be the same. In case of block mode, we use the actual length
++	 * parameter to reflect the total number of bytes transmitted after
++	 * padding.
++	 */
++	mboxBuffer->actualLength = mboxBuffer->bufferLength;
++	mboxBuffer->buffer += HTC_HEADER_LEN;
++
++	/*
++	 * Return the transmit buffer to the user through the HTC_BUFFER_SENT
++	 * event indicating that the frame was transmitted successfully.
++	 */
++	FRAME_EVENT(eventInfo, mboxBuffer->buffer, mboxBuffer->bufferLength,
++				mboxBuffer->actualLength, A_OK, mboxBuffer->cookie);
++	RECYCLE_DATA_REQUEST_ELEMENT(element);
++
++	tx_complete[endPointId] += 1;
++
++	dispatchEvent(target, endPointId, HTC_BUFFER_SENT, &eventInfo);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("htcTxCompletionCB - Exit\n"));
++
++	return 0;
++}
++
++int htcBlkSzNegCompletionCB(HTC_DATA_REQUEST_ELEMENT * element, int status)
++{
++	HTC_TARGET *target;
++	HTC_ENDPOINT *endPoint;
++	HTC_MBOX_BUFFER *mboxBuffer;
++	HTC_REG_REQUEST_ELEMENT *regElement;
++	u32 address;
++
++	/* Get the context */
++	mboxBuffer = GET_MBOX_BUFFER(element);
++	AR_DEBUG_ASSERT(mboxBuffer != NULL);
++	endPoint = mboxBuffer->endPoint;
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++
++	/* Recycle the request element */
++	RECYCLE_DATA_REQUEST_ELEMENT(element);
++	element->completionCB = htcTxCompletionCB;
++
++	if (status == 0) {
++		/* Mark the state to be ready */
++		endPoint->enabled = TRUE;
++
++		/* Set the state of the target as ready */
++		if (target->endPoint[ENDPOINT1].enabled &&
++			target->endPoint[ENDPOINT2].enabled &&
++			target->endPoint[ENDPOINT3].enabled &&
++			target->endPoint[ENDPOINT4].enabled) {
++			/* Send the INT_WLAN interrupt to the target */
++			target->table.int_wlan = 1;
++			regElement = allocateRegRequestElement(target);
++			address = getRegAddr(INT_WLAN_REG, ENDPOINT_UNUSED);
++
++			/* FIXME: do an async request here */
++			sdio_writeb(target->device, target->table.int_wlan, address,
++						&status);
++			if (status == 0)
++				regElement->completionCB(regElement, status);
++		}
++	}
++
++	return 0;
++}
++
++int htcRxCompletionCB(HTC_DATA_REQUEST_ELEMENT * element, int status)
++{
++	HTC_TARGET *target;
++	HTC_ENDPOINT *endPoint;
++	HTC_EVENT_INFO eventInfo;
++	HTC_ENDPOINT_ID endPointId;
++	HTC_MBOX_BUFFER *mboxBuffer;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("htcRxCompletionCB - Enter\n"));
++
++	/* Get the context */
++	mboxBuffer = GET_MBOX_BUFFER(element);
++	AR_DEBUG_ASSERT(mboxBuffer != NULL);
++	endPoint = mboxBuffer->endPoint;
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV,
++					("mboxBuffer: 0x%p, buffer: 0x%p, endPoint(%d): 0x%p, target: 0x%p\n",
++					 mboxBuffer, mboxBuffer->buffer, endPointId, endPoint,
++					 target));
++
++	/* Return the buffer to the user if the reception was not successful */
++	if (status != 0) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++						("Frame reception failed\n"));
++		/*
++		 * In the failure case it is possible that while queueing of the
++		 * request itself it returned an error status in which case we
++		 * would have dispatched an event and freed the element there
++		 * itself. Ideally if it failed to queue the request then it
++		 * should not generate a callback but we are being a little
++		 * conservative.
++		 */
++		if (!(IS_ELEMENT_FREE(element))) {
++			mboxBuffer->actualLength = 0;
++			mboxBuffer->buffer += HTC_HEADER_LEN;
++			FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++						mboxBuffer->bufferLength, mboxBuffer->actualLength,
++						A_ECANCELED, mboxBuffer->cookie);
++			RECYCLE_DATA_REQUEST_ELEMENT(element);
++			dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED,
++						  &eventInfo);
++			AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++							("htcRxCompletionCB - Exit\n"));
++		}
++		return 0;
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV,
++					("Frame reception complete\n"));
++
++	AR_DEBUG_PRINTBUF(mboxBuffer->buffer, mboxBuffer->actualLength);
++
++	/*
++	 * Advance the pointer by the size of HTC header and pass the payload
++	 * pointer to the upper layer.
++	 */
++	mboxBuffer->actualLength = ((mboxBuffer->buffer[0] << 0) |
++								(mboxBuffer->buffer[1] << 8));
++	mboxBuffer->buffer += HTC_HEADER_LEN;
++
++	/*
++	 * Frame the HTC_BUFFER_RECEIVED to the upper layer indicating that the
++	 * packet has been succesfully received.
++	 */
++	FRAME_EVENT(eventInfo, mboxBuffer->buffer, mboxBuffer->bufferLength,
++				mboxBuffer->actualLength, A_OK, mboxBuffer->cookie);
++
++	/* Recycle the bufferElement structure */
++	RECYCLE_DATA_REQUEST_ELEMENT(element);
++
++	/* Dispatch the event */
++	dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED, &eventInfo);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++					("htcRxCompletion - Exit\n"));
++
++	return 0;
++}
++
++int htcRegCompletionCB(HTC_REG_REQUEST_ELEMENT * element, int status)
++{
++	int ret = 0;
++	HTC_TARGET *target;
++	HTC_ENDPOINT *endPoint;
++	HTC_REG_BUFFER *regBuffer;
++	u8 txCreditsConsumed;
++	u8 txCreditsAvailable;
++	HTC_ENDPOINT_ID endPointId;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV | ATH_DEBUG_SEND,
++					("htcRegCompletion - Enter\n"));
++	AR_DEBUG_ASSERT(status == 0);
++
++	/* Get the context */
++	AR_DEBUG_ASSERT(element != NULL);
++	regBuffer = GET_REG_BUFFER(element);
++	AR_DEBUG_ASSERT(regBuffer != NULL);
++	target = regBuffer->target;
++	AR_DEBUG_ASSERT(target != NULL);
++
++	/* Identify the register and the operation responsible for the
++	   callback */
++	switch (regBuffer->base) {
++	case TX_CREDIT_COUNTER_DECREMENT_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("TX_CREDIT_COUNTER_DECREMENT_REG\n"));
++		endPointId = regBuffer->offset;
++		endPoint = &target->endPoint[endPointId];
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++						("Critical Section (credit): LOCK at line %d in file %s\n",
++						 __LINE__, __FILE__));
++		A_MUTEX_LOCK(&creditCS);
++
++		/* Calculate the number of credits available */
++		AR_DEBUG_ASSERT(GET_TX_CREDITS_CONSUMED(endPoint) ==
++						regBuffer->length);
++		AR_DEBUG_ASSERT(regBuffer->buffer[0] >=
++						GET_TX_CREDITS_CONSUMED(endPoint));
++		SET_TX_CREDITS_AVAILABLE(endPoint,
++								 regBuffer->buffer[0] -
++								 GET_TX_CREDITS_CONSUMED(endPoint));
++		SET_TX_CREDITS_CONSUMED(endPoint, 0);
++		txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++		txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++		AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++						("Critical Section (credit): UNLOCK at line %d in file %s\n",
++						 __LINE__, __FILE__));
++		A_MUTEX_UNLOCK(&creditCS);
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++						("Pulling %d tx credits from the target\n",
++						 txCreditsAvailable));
++
++#ifdef CONFIG_AR6K_DEBUG
++		txcreditsavailable[endPointId] = txCreditsAvailable;
++		txcreditsconsumed[endPointId] = txCreditsConsumed;
++#endif							/* DEBUG */
++
++		if (txCreditsAvailable) {
++			htcSendFrame(endPoint);
++		} else {
++			/*
++			 * Enable the Tx credit counter interrupt so that we can get the
++			 * credits posted by the target.
++			 */
++			htcEnableCreditCounterInterrupt(target, endPointId);
++
++#ifdef CONFIG_AR6K_DEBUG
++			txcreditintrenable[endPointId] += 1;
++			txcreditintrenableaggregate[endPointId] += 1;
++#endif							/* DEBUG */
++		}
++		break;
++
++	case TX_CREDIT_COUNTER_RESET_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("TX_CREDIT_COUNTER_RESET_REG\n"));
++		endPointId = regBuffer->offset;
++
++		/*
++		 * Enable the Tx credit counter interrupt so that we can get the
++		 * credits posted by the target.
++		 */
++		htcEnableCreditCounterInterrupt(target, endPointId);
++
++#ifdef CONFIG_AR6K_DEBUG
++		txcreditintrenable[endPointId] += 1;
++		txcreditintrenableaggregate[endPointId] += 1;
++#endif							/* DEBUG */
++		break;
++
++	case COUNTER_INT_STATUS_ENABLE_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("COUNTER_INT_STATUS_ENABLE: 0x%x\n",
++						 target->table.counter_int_status_enable));
++		break;
++
++	case COUNTER_INT_STATUS_DISABLE_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("COUNTER_INT_STATUS_DISABLE:0x%x\n",
++						 target->table.counter_int_status_enable));
++		HIFAckInterrupt(target->device);
++		AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler - ACK\n"));
++		break;
++
++	case INT_WLAN_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("INT_WLAN: 0x%x\n",
++										target->table.int_wlan));
++		target->table.int_wlan = 0;
++
++		/* Mark the target state as ready and signal the waiting sem */
++		target->ready = TRUE;
++		A_WAKE_UP(&htcEvent);
++		break;
++
++	case INT_STATUS_ENABLE_REG:
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("INT_STATUS_ENABLE: 0x%x\n",
++										target->table.int_status_enable));
++		break;
++
++	default:
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("Invalid register address: %d\n",
++						 regBuffer->base));
++	}
++
++	/* Free the register request structure */
++	freeRegRequestElement(element);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcRegCompletion - Exit\n"));
++
++	return ret;
++}
++
++
++int htcTargetInsertedHandler(struct sdio_func *device)
++{
++	HTC_TARGET *target;
++	HTC_ENDPOINT *endPoint;
++	u8 count1, count2;
++	HTC_EVENT_INFO eventInfo;
++	HTC_REG_BUFFER *regBuffer;
++	HTC_QUEUE_ELEMENT *element;
++	HTC_MBOX_BUFFER *mboxBuffer;
++	HTC_REG_REQUEST_LIST *regList;
++	HTC_DATA_REQUEST_QUEUE *sendQueue, *recvQueue;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n"));
++
++	/* Initialize the locks */
++	A_MUTEX_INIT(&instanceCS);
++	A_MUTEX_INIT(&creditCS);
++	A_MUTEX_INIT(&counterCS);
++
++	/* Allocate target memory */
++	if ((target = (HTC_TARGET *) A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
++		return A_ERROR;
++	}
++	A_MEMZERO(target, sizeof(HTC_TARGET));
++	target->device = device;
++	target->ready = FALSE;
++
++	/* Initialize the endpoints, mbox queues, event table */
++	for (count1 = ENDPOINT1; count1 <= ENDPOINT4; count1++) {
++		endPoint = &target->endPoint[count1];
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("endPoint[%d]: %p\n", count1, endPoint));
++		A_MEMZERO(endPoint->txCreditsAvailable, HTC_TX_CREDITS_NUM_MAX);
++		endPoint->txCreditsConsumed = 0;
++		endPoint->txCreditsIntrEnable = FALSE;
++		endPoint->rxLengthPending = 0;
++		endPoint->target = target;
++		endPoint->enabled = FALSE;
++		for (count2 = 0; count2 < HTC_DATA_REQUEST_RING_BUFFER_SIZE;
++			 count2++) {
++			/* Send Queue */
++			sendQueue = &endPoint->sendQueue;
++			sendQueue->head = sendQueue->size = 0;
++			element = &sendQueue->element[count2];
++			A_MEMZERO(element, sizeof(HTC_DATA_REQUEST_ELEMENT));
++			element->buffer.free = TRUE;
++			element->completionCB = htcTxCompletionCB;
++			mboxBuffer = GET_MBOX_BUFFER(element);
++			mboxBuffer->endPoint = endPoint;
++
++			/* Receive Queue */
++			recvQueue = &endPoint->recvQueue;
++			recvQueue->head = recvQueue->size = 0;
++			element = &recvQueue->element[count2];
++			A_MEMZERO(element, sizeof(HTC_DATA_REQUEST_ELEMENT));
++			element->buffer.free = TRUE;
++			element->completionCB = htcRxCompletionCB;
++			mboxBuffer = GET_MBOX_BUFFER(element);
++			mboxBuffer->endPoint = endPoint;
++		}
++		A_MEMZERO(&target->endPoint[count1].eventTable,
++				  sizeof(HTC_ENDPOINT_EVENT_TABLE));
++	}
++
++	/* Populate the block size for each of the end points */
++	for (count1 = ENDPOINT1; count1 <= ENDPOINT4; count1++) {
++		endPoint = &target->endPoint[count1];
++		endPoint->blockSize = (count1 == ENDPOINT1 ? HIF_MBOX0_BLOCK_SIZE : HIF_MBOX_BLOCK_SIZE);
++		endPoint->address = HIF_MBOX_START_ADDR(count1);
++	}
++
++	/* Initialize the shadow copy of the target register table */
++	A_MEMZERO(&target->table, sizeof(HTC_REGISTER_TABLE));
++
++	/* Initialize the register request list */
++	regList = &target->regList;
++	for (count1 = 0; count1 < HTC_REG_REQUEST_LIST_SIZE; count1++) {
++		element = &regList->element[count1];
++		A_MEMZERO(element, sizeof(HTC_REG_REQUEST_ELEMENT));
++		element->buffer.free = TRUE;
++		element->completionCB = htcRegCompletionCB;
++		regBuffer = GET_REG_BUFFER(element);
++		regBuffer->target = target;
++	}
++
++	/* Add the target instance to the global list */
++	addTargetInstance(target);
++
++	/*
++	 * Frame a TARGET_AVAILABLE event and send it to the host. Return the
++	 * struct sdio_func handle as a parameter with the event.
++	 */
++	FRAME_EVENT(eventInfo, (u8 *) device, sizeof(struct sdio_func *),
++				sizeof(struct sdio_func *), A_OK, NULL);
++	dispatchEvent(target, ENDPOINT_UNUSED, HTC_TARGET_AVAILABLE,
++				  &eventInfo);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n"));
++
++	return 0;
++}
++
++int htcTargetRemovedHandler(struct sdio_func *device)
++{
++	HTC_TARGET *target;
++	HTC_EVENT_INFO eventInfo;
++
++	/* Get the target instance bound to this device */
++	target = getTargetInstance(device);
++
++	if (target != NULL) {
++		/* Frame a TARGET_UNAVAILABLE event and send it to the host */
++		FRAME_EVENT(eventInfo, NULL, 0, 0, A_OK, NULL);
++		dispatchEvent(target, ENDPOINT_UNUSED, HTC_TARGET_UNAVAILABLE,
++					  &eventInfo);
++	}
++
++	return 0;
++}
++
++
++
++int htcDSRHandler(struct sdio_func *device)
++{
++	int status;
++	u32 address;
++	HTC_TARGET *target;
++	u8 host_int_status;
++
++	printk("%s()\n", __FUNCTION__);
++
++	target = getTargetInstance(device);
++	AR_DEBUG_ASSERT(target != NULL);
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++			("htcDsrHandler: Enter (target: 0x%p\n", target));
++
++	/*
++	 * Read the first 28 bytes of the HTC register table. This will yield us
++	 * the value of different int status registers and the lookahead
++	 * registers.
++	 *    length = sizeof(int_status) + sizeof(cpu_int_status) +
++	 *             sizeof(error_int_status) + sizeof(counter_int_status) +
++	 *             sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
++	 *             sizeof(hole) +  sizeof(rx_lookahead) +
++	 *             sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
++	 *             sizeof(error_status_enable) +
++	 *             sizeof(counter_int_status_enable);
++	 */
++	address = getRegAddr(INT_STATUS_REG, ENDPOINT_UNUSED);
++	status =
++		sdio_memcpy_fromio(target->device, &target->table.host_int_status,
++				   address, 28);
++	AR_DEBUG_ASSERT(status == 0);
++
++#ifdef CONFIG_AR6K_DEBUG
++	dumpRegisters(target);
++#endif							/* DEBUG */
++	/* Update only those registers that are enabled */
++	host_int_status = target->table.host_int_status &
++		target->table.int_status_enable;
++
++	printk("%s(), 0x%x\n", __FUNCTION__, host_int_status);
++
++	AR_DEBUG_ASSERT(host_int_status);
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++			("Valid interrupt source(s) in INT_STATUS: 0x%x\n",
++			 host_int_status));
++	if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
++		/* CPU Interrupt */
++		htcServiceCPUInterrupt(target);
++	}
++
++	if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
++		/* Error Interrupt */
++		htcServiceErrorInterrupt(target);
++	}
++
++	if (HOST_INT_STATUS_MBOX_DATA_GET(host_int_status)) {
++		/* Mailbox Interrupt */
++		htcServiceMailboxInterrupt(target);
++	}
++
++	if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
++		/* Counter Interrupt */
++		htcServiceCounterInterrupt(target);
++	} else {
++		/* Ack the interrupt */
++		HIFAckInterrupt(target->device);
++		AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler - ACK\n"));
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler: Exit\n"));
++	return 0;
++}
++
++void htcServiceCPUInterrupt(HTC_TARGET * target)
++{
++	int status;
++	u32 address;
++	u8 cpu_int_status;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("CPU Interrupt\n"));
++	cpu_int_status = target->table.cpu_int_status &
++		target->table.cpu_int_status_enable;
++	AR_DEBUG_ASSERT(cpu_int_status);
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
++					 cpu_int_status));
++
++	/* Figure out the interrupt number */
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Interrupt Number: 0x%x\n",
++									htcGetBitNumSet(cpu_int_status)));
++
++	/* Clear the interrupt */
++	target->table.cpu_int_status = cpu_int_status;	/* W1C */
++	address = getRegAddr(CPU_INT_STATUS_REG, ENDPOINT_UNUSED);
++	sdio_writeb(target->device, target->table.cpu_int_status, address,
++				&status);
++	AR_DEBUG_ASSERT(status == 0);
++}
++
++
++void htcServiceErrorInterrupt(HTC_TARGET * target)
++{
++	int status;
++	u32 address;
++	u8 error_int_status;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Error Interrupt\n"));
++	error_int_status = target->table.error_int_status &
++		target->table.error_status_enable;
++	AR_DEBUG_ASSERT(error_int_status);
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
++					 error_int_status));
++
++	if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
++		/* Wakeup */
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Wakeup\n"));
++	}
++
++	if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
++		/* Rx Underflow */
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Rx Underflow\n"));
++	}
++
++	if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
++		/* Tx Overflow */
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Tx Overflow\n"));
++	}
++
++	/* Clear the interrupt */
++	target->table.error_int_status = error_int_status;	/* W1C */
++	address = getRegAddr(ERROR_INT_STATUS_REG, ENDPOINT_UNUSED);
++	sdio_writeb(target->device, target->table.error_int_status, address,
++				&status);
++	AR_DEBUG_ASSERT(status == 0);
++}
++
++void htcServiceCounterInterrupt(HTC_TARGET * target)
++{
++	int status;
++	u32 address;
++	HTC_ENDPOINT *endPoint;
++	HTC_ENDPOINT_ID endPointId;
++	u8 counter_int_status;
++	u8 reset_credit_int_status;
++	u8 update_credit_int_status;
++	HTC_REG_REQUEST_ELEMENT *element;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Counter Interrupt\n"));
++
++	counter_int_status = target->table.counter_int_status &
++		target->table.counter_int_status_enable;
++	AR_DEBUG_ASSERT(counter_int_status);
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
++					 counter_int_status));
++
++	/* Service the reset credit counter interrupt */
++	reset_credit_int_status = (counter_int_status & 0x0F);
++	while (reset_credit_int_status) {
++		endPointId = htcGetBitNumSet(reset_credit_int_status);
++		endPoint = &target->endPoint[endPointId];
++		AR_DEBUG_ASSERT(endPoint != NULL);
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("endPoint(%d): %p\n", endPointId, endPoint));
++
++		/* Initialize the number of credits available to zero */
++		SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++
++		/* Clear the interrupt */
++		address = getRegAddr(TX_CREDIT_COUNTER_RESET_REG, endPointId);
++		element = allocateRegRequestElement(target);
++		AR_DEBUG_ASSERT(element != NULL);
++		FILL_REG_BUFFER(element, &endPoint->txCreditsAvailable[1], 1,
++						TX_CREDIT_COUNTER_RESET_REG, endPointId);
++		/* FIXME: async request? */
++		sdio_writeb(target->device, endPoint->txCreditsAvailable[1],
++					address, &status);
++		if (status == 0) {
++			/* Enable the Tx credit counter interrupt so that we can get
++			   the credits posted by the target */
++			htcEnableCreditCounterInterrupt(target, endPointId);
++		}
++		reset_credit_int_status &=
++			~(1 << htcGetBitNumSet(reset_credit_int_status));
++	}
++
++	/* Disable the credit counter interrupt */
++	htcDisableCreditCounterInterrupt(target, ENDPOINT_UNUSED);
++
++	/* Service the credit counter interrupt */
++	update_credit_int_status = counter_int_status & 0xF0;
++	while (update_credit_int_status) {
++		endPointId = htcGetBitNumSet(update_credit_int_status) -
++			HTC_MAILBOX_NUM_MAX;
++		endPoint = &target->endPoint[endPointId];
++		AR_DEBUG_ASSERT(endPoint != NULL);
++
++		/* This is the minimum number of credits that we would have got */
++		AR_DEBUG_ASSERT(GET_TX_CREDITS_AVAILABLE(endPoint) == 0);
++		SET_TX_CREDITS_AVAILABLE(endPoint, 1);
++
++#ifdef CONFIG_AR6K_DEBUG
++		txcreditsavailable[endPointId] =
++			GET_TX_CREDITS_AVAILABLE(endPoint);
++		txcreditintrenable[endPointId] -= 1;
++#endif							/* DEBUG */
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Tx Credits Available: %d\n",
++										GET_TX_CREDITS_AVAILABLE
++										(endPoint)));
++
++		if (!target->ready) {
++			htcSendBlkSize(endPoint);
++		} else {
++			htcSendFrame(endPoint);
++		}
++
++		update_credit_int_status &=
++			~(1 << htcGetBitNumSet(update_credit_int_status));
++	}
++}
++
++
++void
++htcEnableCreditCounterInterrupt(HTC_TARGET * target,
++								HTC_ENDPOINT_ID endPointId)
++{
++	int status;
++	u32 address;
++	HTC_ENDPOINT *endPoint;
++
++	endPoint = &target->endPoint[endPointId];
++	AR_DEBUG_ASSERT(endPoint != NULL);
++
++	A_MUTEX_LOCK(&counterCS);
++
++	endPoint->txCreditsIntrEnable = TRUE;
++	address = getRegAddr(COUNTER_INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++
++	/* FIXME: async request? */
++	sdio_writeb(target->device, ((target->endPoint[0].
++								  txCreditsIntrEnable << (4)) | (target->
++																 endPoint
++																 [1].
++																 txCreditsIntrEnable
++																 << (5)) |
++								 (target->endPoint[2].
++								  txCreditsIntrEnable << (6)) | (target->
++																 endPoint
++																 [3].
++																 txCreditsIntrEnable
++																 << (7)) |
++								 0x0F), address, &status);
++	A_MUTEX_UNLOCK(&counterCS);
++}
++
++void
++htcDisableCreditCounterInterrupt(HTC_TARGET * target,
++								 HTC_ENDPOINT_ID unused)
++{
++	int status;
++	u32 address;
++	HTC_ENDPOINT *endPoint;
++	HTC_ENDPOINT_ID endPointId;
++	u8 counter_int_status;
++	u8 update_credit_int_status;
++
++	A_MUTEX_LOCK(&counterCS);
++
++	/* The Tx credit counter update bits are reflected in the upper nibble
++	 */
++	counter_int_status = target->table.counter_int_status &
++		target->table.counter_int_status_enable;
++	update_credit_int_status = counter_int_status & 0xF0;
++	while (update_credit_int_status) {
++		endPointId = htcGetBitNumSet(update_credit_int_status) -
++			HTC_MAILBOX_NUM_MAX;
++		endPoint = &target->endPoint[endPointId];
++		AR_DEBUG_ASSERT(endPoint != NULL);
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("endPoint(%d): %p\n", endPointId, endPoint));
++
++		/* Disable the tx credit interrupt */
++		endPoint->txCreditsIntrEnable = FALSE;
++
++		update_credit_int_status &=
++			~(1 << htcGetBitNumSet(update_credit_int_status));
++	}
++
++	address = getRegAddr(COUNTER_INT_STATUS_DISABLE_REG, ENDPOINT_UNUSED);
++	/* FIXME: async request? */
++	sdio_writeb(target->device, ((target->endPoint[0].
++				      txCreditsIntrEnable << (4)) | (target->endPoint
++								     [1].
++								     txCreditsIntrEnable
++								     << (5)) |
++								 (target->endPoint[2].
++								  txCreditsIntrEnable << (6)) |
++				     (target->
++												 endPoint
++												 [3].
++												 txCreditsIntrEnable
++												 << (7)) |
++				     0x0F), address, &status);
++	A_MUTEX_UNLOCK(&counterCS);
++}
++
++void htcServiceMailboxInterrupt(HTC_TARGET * target)
++{
++	int status, counter = 1000;
++	u32 address;
++	HTC_ENDPOINT *endPoint;
++	HTC_ENDPOINT_ID endPointId;
++	u8 mailbox_int_status;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Mailbox Interrupt\n"));
++
++	/* The Rx interrupt bits are reflected in the lower nibble */
++	mailbox_int_status = target->table.host_int_status &
++		HOST_INT_STATUS_MBOX_DATA_MASK;
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("Valid mailbox interrupt source(s) in INT_STATUS: 0x%x\n",
++					 mailbox_int_status));
++
++	/* Disable the receive interrupt for all four mailboxes */
++	target->table.int_status_enable &= ~(HOST_INT_STATUS_MBOX_DATA_MASK);
++
++	do {
++		while (mailbox_int_status) {
++			endPointId = htcGetBitNumSet(mailbox_int_status);
++			endPoint = &target->endPoint[endPointId];
++			AR_DEBUG_ASSERT(endPoint != NULL);
++
++			AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++							("endPoint(%d): %p\n", endPointId, endPoint));
++
++			/* Service the Rx interrupt */
++			htcReceiveFrame(endPoint);
++			mailbox_int_status &=
++				~(1 << htcGetBitNumSet(mailbox_int_status));
++		}
++
++		/*
++		 * Read the register table again. Repeat the process until there are
++		 * no more valid packets queued up on receive. It is assumed that
++		 * the following request will be serialized along with the request
++		 * above and will be completed in the order in which it is received
++		 * by the bus driver.
++		 */
++		address = getRegAddr(INT_STATUS_REG, ENDPOINT_UNUSED);
++		status =
++			sdio_memcpy_fromio(target->device,
++					   &target->table.host_int_status, address,
++					   24);
++//		AR_DEBUG_ASSERT(status == 0);
++		mailbox_int_status = target->table.host_int_status &
++			HOST_INT_STATUS_MBOX_DATA_MASK;
++		counter--;
++	} while (mailbox_int_status && counter);
++
++	target->table.int_status_enable |= HOST_INT_STATUS_MBOX_DATA_MASK;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_internal.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_internal.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,456 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ * 2. The name of the author may not be used to endorse or promote products
++ *    derived from this software withough specific prior written permission
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * HTC internal specific declarations and prototypes
++ */
++
++#ifndef _HTC_INTERNAL_H_
++#define _HTC_INTERNAL_H_
++
++/* Header files */
++#include "../ar6k.h"
++#include "../include/athdefs.h"
++#include "../include/hw/mbox_host_reg.h"
++#include "../include/hw/rtc_reg.h"
++#include "../include/htc.h"
++#include "../include/AR6000_bmi.h"
++#include "../include/osapi.h"
++#include "../include/hif.h"
++
++/* HTC operational parameters */
++#define HTC_GLOBAL_EVENT_NUM_MAX           2 /* Target available/unavailable */
++#define HTC_ENDPOINT_EVENT_NUM_MAX         5 /* Endpoint specific */
++#define HTC_REG_REQUEST_LIST_SIZE          16
++#define HTC_MESSAGE_SIZE_MAX               1536 - HTC_HEADER_LEN /* Default maximum message size for each mailbox */
++#define HTC_TX_CREDITS_NUM_MAX             64
++#define HTC_TARGET_RESPONSE_TIMEOUT        5000 /* in ms */
++
++/* Useful macros */
++#define GET_ENDPOINT_ID(endPoint) (endPoint - endPoint->target->endPoint)
++
++/* ------- Debug related stuff ------- */
++enum {
++    ATH_DEBUG_SEND = 0x0001,
++    ATH_DEBUG_RECV = 0x0002,
++    ATH_DEBUG_SYNC = 0x0004,
++    ATH_DEBUG_DUMP = 0x0008,
++    ATH_DEBUG_INF  = 0x0010,
++    ATH_DEBUG_TRC  = 0x0020,
++    ATH_DEBUG_WARN = 0x0040,
++    ATH_DEBUG_ERR  = 0x0080,
++    ATH_DEBUG_ANY  = 0xFFFF,
++};
++
++#ifdef CONFIG_AR6K_DEBUG
++#define AR_DEBUG_PRINTBUF(buffer, length) do {   \
++    if (debughtc & ATH_DEBUG_DUMP) {             \
++        dumpBytes(buffer, length);               \
++    }                                            \
++} while(0)
++#define PRINTX_ARG(arg...) arg
++#define AR_DEBUG_PRINTF(flags, args) do {        \
++    if (debughtc & (flags)) {                    \
++        A_PRINTF(KERN_ALERT PRINTX_ARG args);      \
++    }                                            \
++} while (0)
++#define AR_DEBUG_ASSERT(test) do {               \
++    if (!(test)) {                               \
++        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test));         \
++    }                                            \
++} while(0)
++#else
++#define AR_DEBUG_PRINTF(flags, args)
++#define AR_DEBUG_PRINTBUF(buffer, length)
++#define AR_DEBUG_ASSERT(test)
++#endif
++
++/* ------- Event Related Data Structures ------- */
++typedef struct htc_event_map HTC_EVENT_MAP;
++typedef struct event_table_element EVENT_TABLE_ELEMENT;
++typedef struct htc_endpoint_event_table HTC_ENDPOINT_EVENT_TABLE;
++typedef struct htc_global_event_table HTC_GLOBAL_EVENT_TABLE;
++
++#define FRAME_EVENT(_eventInfo, _buffer, _bufferLength,   \
++                    _actualLength, _status, _cookie) do { \
++    _eventInfo.buffer  = _buffer;                         \
++    _eventInfo.bufferLength = _bufferLength;              \
++    _eventInfo.actualLength = _actualLength;              \
++    _eventInfo.status = _status;                          \
++    _eventInfo.cookie = _cookie;                          \
++} while (0)
++
++struct event_table_element {
++    HTC_EVENT_ID         id;
++    HTC_EVENT_HANDLER    handler;
++    void                *param;
++};
++
++struct htc_endpoint_event_table {
++    EVENT_TABLE_ELEMENT element[HTC_ENDPOINT_EVENT_NUM_MAX];
++};
++
++struct htc_global_event_table {
++    EVENT_TABLE_ELEMENT element[HTC_GLOBAL_EVENT_NUM_MAX];
++
++};
++
++/* ------ Mailbox Related Data Structures ------ */
++typedef struct htc_queue_element HTC_QUEUE_ELEMENT, HTC_REG_REQUEST_ELEMENT, HTC_DATA_REQUEST_ELEMENT;
++typedef struct htc_mbox_buffer HTC_MBOX_BUFFER;
++typedef struct htc_reg_buffer HTC_REG_BUFFER;
++typedef struct htc_data_request_queue HTC_DATA_REQUEST_QUEUE;
++typedef struct htc_reg_request_list HTC_REG_REQUEST_LIST;
++typedef struct htc_endpoint HTC_ENDPOINT;
++
++typedef enum {
++    INT_STATUS_REG,
++    ERROR_INT_STATUS_REG,
++    CPU_INT_STATUS_REG,
++    RX_LOOKAHEAD_VALID_REG,
++    RX_LOOKAHEAD0_REG,
++    RX_LOOKAHEAD1_REG,
++    RX_LOOKAHEAD2_REG,
++    RX_LOOKAHEAD3_REG,
++    TX_CREDIT_COUNTER_REG,
++    TX_CREDIT_COUNTER_RESET_REG,
++    TX_CREDIT_COUNTER_DECREMENT_REG,
++    SCRATCH_REG,
++    INT_STATUS_ENABLE_REG,
++    CPU_INT_STATUS_ENABLE_REG,
++    ERROR_STATUS_ENABLE_REG,
++    COUNTER_INT_STATUS_READ_REG,
++    COUNTER_INT_STATUS_ENABLE_REG,
++    COUNTER_INT_STATUS_DISABLE_REG,
++    INT_WLAN_REG,
++    WINDOW_DATA_REG,
++    WINDOW_WRITE_ADDR_REG,
++    WINDOW_READ_ADDR_REG
++} TARGET_REGISTERS;
++
++#define SET_TX_CREDITS_AVAILABLE(endPoint, credits) \
++                                    endPoint->txCreditsAvailable[0] = (credits)
++#define SET_TX_CREDITS_CONSUMED(endPoint, credits) \
++                                    endPoint->txCreditsConsumed = (credits)
++#define GET_TX_CREDITS_AVAILABLE(endPoint) \
++                                    endPoint->txCreditsAvailable[0]
++#define GET_TX_CREDITS_CONSUMED(endPoint) \
++                                    endPoint->txCreditsConsumed
++
++#define IS_ELEMENT_FREE(element)	element->buffer.free
++#define GET_MBOX_BUFFER(element)	&((element)->buffer.u.mboxBuffer)
++#define GET_REG_BUFFER(element)		&((element)->buffer.u.regBuffer)
++#define GET_QUEUE_TAIL(queue)		&queue->element[(queue->head + queue->size) % HTC_DATA_REQUEST_RING_BUFFER_SIZE]
++#define GET_QUEUE_HEAD(queue)		&queue->element[queue->head]
++#define IS_DATA_QUEUE_EMPTY(queue)      (!queue->size)
++#define IS_DATA_QUEUE_FULL(queue)       (!(HTC_DATA_REQUEST_RING_BUFFER_SIZE - queue->size))
++
++#define RECYCLE_DATA_REQUEST_ELEMENT(element) do { \
++    FILL_MBOX_BUFFER(element, NULL, 0, 0, NULL); \
++    (element)->buffer.free = TRUE; \
++} while (0)
++
++#define FILL_MBOX_BUFFER(element, _buffer, _bufferLength, _actualLength, _cookie) do { \
++    (GET_MBOX_BUFFER(element))->buffer = _buffer; \
++    (GET_MBOX_BUFFER(element))->bufferLength = _bufferLength; \
++    (GET_MBOX_BUFFER(element))->actualLength = _actualLength; \
++    (GET_MBOX_BUFFER(element))->cookie = _cookie; \
++} while (0)
++
++#define FILL_REG_BUFFER(element, _buffer, _length, _base, _offset) do { \
++    (GET_REG_BUFFER(element))->buffer = _buffer; \
++    (GET_REG_BUFFER(element))->length = _length; \
++    (GET_REG_BUFFER(element))->base = _base; \
++    (GET_REG_BUFFER(element))->offset = _offset; \
++} while (0)
++
++struct htc_queue_element {
++    int	(*completionCB)(HTC_QUEUE_ELEMENT *element, int status);
++    struct htc_buffer {
++        /* In use or available */
++        u8	free;
++        union {
++            struct htc_mbox_buffer {
++                /*
++                 * Given by the caller and is associated with the buffer being
++                 * queued up.
++                 */
++                void			*cookie;
++
++                /*
++                 * Pointer to the start of the buffer. In the transmit
++                 * direction this points to the start of the payload. In the
++                 * receive direction, however, the buffer when queued up
++                 * points to the start of the HTC header but when returned
++                 * to the caller points to the start of the payload
++                 */
++                u8			*buffer;
++
++                /* Holds the length of the buffer */
++                u32		bufferLength;
++
++                /* Holds the length of the payload */
++                u32		actualLength;
++
++                HTC_ENDPOINT    *endPoint;
++            } mboxBuffer;
++            struct htc_reg_buffer {
++                HTC_TARGET		*target;
++                u8			*buffer;
++                u32		length;
++                TARGET_REGISTERS	base;
++                u32		offset;
++            } regBuffer;
++        } u;
++    } buffer;
++};
++
++/* This is a FIFO queue of the pending data read/write requests. When a request
++has to be issued, the element at the head of the queue is dequeued and
++processed. New requests are added at the tail of the queue. The queue can only
++support a fixed number of requests and stops adding new requests once the total
++number of requests that are pending to be processed and the ones that are still
++under process reach the queue capacity */
++struct htc_data_request_queue {
++    u32                  head;
++    u32                  size;
++    HTC_DATA_REQUEST_ELEMENT  element[HTC_DATA_REQUEST_RING_BUFFER_SIZE];
++};
++
++/* This is a list of 'free' register read/write requests. When a request has to
++be issued an element is taken from this list and after the completion of the
++request is added back to the list */
++struct htc_reg_request_list {
++    HTC_REG_REQUEST_ELEMENT  element[HTC_REG_REQUEST_LIST_SIZE];
++};
++
++struct htc_endpoint {
++    /* Enabled or Disabled */
++    u8                   enabled;
++
++    /*
++     * Used to hold the length of the frame received from the target in
++     * case there are no buffers that have been queued up to receive the
++     * data.
++     */
++    u32                 rxLengthPending;
++
++    /* Number of frames for which the target has space for at any time */
++    u8                  txCreditsAvailable[1 + HTC_TX_CREDITS_NUM_MAX];
++
++    /*
++     * Number of frames that have been sent since the transmit credits
++     * were last updated.
++     */
++    u8                  txCreditsConsumed;
++
++    u8                   txCreditsIntrEnable;
++
++    /* Pending Send Queue */
++    HTC_DATA_REQUEST_QUEUE   sendQueue;
++
++    /* Pending Receive Queue */
++    HTC_DATA_REQUEST_QUEUE   recvQueue;
++
++    /* Inverse reference to the target */
++    HTC_TARGET              *target;
++
++    /* Block size configured for the endpoint */
++    u32                 blockSize;
++
++    /* Event Table */
++    HTC_ENDPOINT_EVENT_TABLE eventTable;
++
++    /* Stating address of the endpoint */
++    u32                 address;
++};
++
++/* ------- Target Related Data structures ------- */
++typedef struct htc_register_table HTC_REGISTER_TABLE;
++
++/*
++ * The following Register table only contain those registers that are used
++ * in HTC. It does not reflect the actual register layout in the hardware
++ */
++struct htc_register_table {
++    u8                      host_int_status;
++    u8                      cpu_int_status;
++    u8                      error_int_status;
++    u8                      counter_int_status;
++    u8                      mbox_frame;
++    u8                      rx_lookahead_valid;
++    u8                      hole[2];
++    u32                     rx_lookahead[HTC_MAILBOX_NUM_MAX];
++    u8                      int_status_enable;
++    u8                      cpu_int_status_enable;
++    u8                      error_status_enable;
++    u8                      counter_int_status_enable;
++    u8                      int_wlan;
++};
++
++struct htc_target {
++    u8                       ready;
++    void                        *device; /* Handle to the device instance
++                                            reported by the bus driver */
++    HTC_ENDPOINT                 endPoint[HTC_MAILBOX_NUM_MAX];
++    HTC_REGISTER_TABLE           table;
++    HTC_REG_REQUEST_LIST         regList;
++};
++
++
++/* ------- Function Prototypes for Receive -------- */
++void
++htcReceiveFrame(HTC_ENDPOINT *endPoint);
++
++u32
++htcGetFrameLength(HTC_ENDPOINT *endPoint);
++
++
++/* ------- Function Prototypes for Transmit -------- */
++void
++htcSendFrame(HTC_ENDPOINT *endPoint);
++
++void
++htcSendBlkSize(HTC_ENDPOINT *endPoint);
++
++
++/* ------- Function Prototypes for Events and Callbacks  ------- */
++int
++htcRWCompletionHandler(void *element,
++                       int status);
++
++int
++htcTxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++                  int status);
++
++int
++htcBlkSzNegCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++                        int status);
++
++int
++htcRxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++                  int status);
++
++int
++htcRegCompletionCB(HTC_REG_REQUEST_ELEMENT *element,
++                   int status);
++
++int
++htcTargetInsertedHandler(struct sdio_func *device);
++
++int
++htcTargetRemovedHandler(struct sdio_func *device);
++
++int
++htcDSRHandler(struct sdio_func *device);
++
++#ifdef CF
++int
++htcInterruptDisabler(struct sdio_func *device,u8 *callDsr);
++
++int
++htcInterruptEnabler(struct sdio_func *device);
++#endif /* CF */
++
++void
++htcServiceCPUInterrupt(HTC_TARGET *target);
++
++void
++htcServiceErrorInterrupt(HTC_TARGET *target);
++
++void
++htcServiceCounterInterrupt(HTC_TARGET *target);
++
++void
++htcServiceMailboxInterrupt(HTC_TARGET *target);
++
++void
++htcEnableCreditCounterInterrupt(HTC_TARGET *target,
++                                HTC_ENDPOINT_ID endPointId);
++
++void
++htcDisableCreditCounterInterrupt(HTC_TARGET *target,
++                                 HTC_ENDPOINT_ID endPointId);
++
++/* ------- Function Prototypes for Utility routines ------- */
++int
++addToMboxQueue(HTC_DATA_REQUEST_QUEUE *queue,
++               u8        *buffer,
++               u32        bufferLength,
++               u32        actualLength,
++               void           *cookie);
++
++HTC_DATA_REQUEST_ELEMENT *
++removeFromMboxQueue(HTC_DATA_REQUEST_QUEUE *queue);
++
++void
++flushMboxQueue(HTC_ENDPOINT *endPoint,
++               HTC_DATA_REQUEST_QUEUE *queue,
++               HTC_EVENT_ID eventId);
++
++HTC_REG_REQUEST_ELEMENT *
++allocateRegRequestElement(HTC_TARGET *target);
++
++void
++freeRegRequestElement(HTC_REG_REQUEST_ELEMENT *element);
++
++int
++addToEventTable(HTC_TARGET       *target,
++                HTC_ENDPOINT_ID   endPointId,
++                HTC_EVENT_ID      eventId,
++                HTC_EVENT_HANDLER handler,
++                void             *param);
++
++int
++removeFromEventTable(HTC_TARGET *target,
++                     HTC_ENDPOINT_ID endPointId,
++                     HTC_EVENT_ID  eventId);
++
++void
++dispatchEvent(HTC_TARGET     *target,
++              HTC_ENDPOINT_ID endPointId,
++              HTC_EVENT_ID    eventId,
++              HTC_EVENT_INFO *eventInfo);
++
++HTC_TARGET *
++getTargetInstance(void *device);
++
++void
++addTargetInstance(HTC_TARGET *target);
++
++void
++delTargetInstance(HTC_TARGET *target);
++
++u32
++getRegAddr(TARGET_REGISTERS base,
++           HTC_ENDPOINT_ID endPointId);
++
++u8
++htcGetBitNumSet(u32 data);
++
++void
++dumpBytes(u8 *buffer, u16 length);
++
++void
++dumpRegisters(HTC_TARGET *target);
++
++#endif /* _HTC_INTERNAL_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_recv.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_recv.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,197 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the receive path.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++#ifdef CONFIG_AR6K_DEBUG
++extern u32 debughtc;
++#endif
++
++/* ------ Static Variables ------ */
++
++
++/* ------ Functions ------ */
++/* Makes a buffer available to the HTC module */
++int
++HTCBufferReceive(HTC_TARGET * target,
++				 HTC_ENDPOINT_ID endPointId,
++				 u8 * buffer, u32 length, void *cookie)
++{
++	int status;
++	HTC_ENDPOINT *endPoint;
++	HTC_DATA_REQUEST_QUEUE *recvQueue;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++					("HTCBufferReceive: Enter (endPointId: %d, buffer: 0x%p, length: %d, cookie: 0x%p)\n",
++					 endPointId, buffer, length, cookie));
++
++	AR_DEBUG_ASSERT((endPointId >= ENDPOINT1)
++					&& (endPointId <= ENDPOINT4));
++
++	/* Extract the end point instance */
++	endPoint = &target->endPoint[endPointId];
++	AR_DEBUG_ASSERT(endPoint != NULL);
++
++	recvQueue = &endPoint->recvQueue;
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV, ("recvQueue: %p\n",
++													 recvQueue));
++
++	/* Add this posted buffer to the pending receive queue */
++	status = addToMboxQueue(recvQueue, buffer, length, 0, cookie);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++						("Mailbox (%d) Send queue full. Unable to add buffer\n",
++						 GET_ENDPOINT_ID(endPoint)));
++		return A_ERROR;
++	}
++
++	/*
++	 * If this API was called as a result of a HTC_DATA_AVAILABLE event to
++	 * the upper layer, indicating that HTC is out of buffers, then we should
++	 * receive the frame in the buffer supplied otherwise we simply add the
++	 * buffer to the Pending Receive Queue
++	 */
++	if (endPoint->rxLengthPending) {
++		htcReceiveFrame(endPoint);
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++					("HTCBufferReceive: Exit\n"));
++	return A_OK;
++}
++
++void htcReceiveFrame(HTC_ENDPOINT * endPoint)
++{
++	int status;
++	u32 paddedLength;
++	u32 frameLength;
++	HTC_ENDPOINT_ID endPointId;
++	HTC_QUEUE_ELEMENT *element;
++	HTC_MBOX_BUFFER *mboxBuffer;
++	HTC_DATA_REQUEST_QUEUE *recvQueue;
++	HTC_TARGET *target;
++	HTC_EVENT_INFO eventInfo;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++					("htcReceiveFrame - Enter\n"));
++
++	/* Get the context */
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	recvQueue = &endPoint->recvQueue;
++	AR_DEBUG_ASSERT(recvQueue != NULL);
++
++	/*
++	 * Receive the frame if we have any pending frames and a buffer to
++	 * receive it into.
++	 */
++	if (IS_DATA_QUEUE_EMPTY(recvQueue)) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_WARN | ATH_DEBUG_RECV,
++						("Mailbox (%d) recv queue empty. Unable to remove buffer\n",
++						 endPointId));
++
++		/*
++		 * Communicate this situation to the host via the HTC_DATA_AVAILABLE
++		 * event to request some buffers in the queue.
++		 */
++		endPoint->rxLengthPending = htcGetFrameLength(endPoint);
++		AR_DEBUG_ASSERT(endPoint->rxLengthPending);
++		FRAME_EVENT(eventInfo, NULL, endPoint->rxLengthPending,
++					0, A_OK, NULL);
++		dispatchEvent(target, endPointId, HTC_DATA_AVAILABLE, &eventInfo);
++		return;
++	}
++
++	/*
++	 * Get the length from the lookahead register if there is nothing
++	 * pending.
++	 */
++	if (endPoint->rxLengthPending) {
++		frameLength = endPoint->rxLengthPending;
++		endPoint->rxLengthPending = 0;
++	} else {
++		frameLength = htcGetFrameLength(endPoint);
++	}
++	AR_DEBUG_ASSERT((frameLength > 0) &&
++					(frameLength <= HTC_MESSAGE_SIZE_MAX));
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV, ("Frame Length: %d\n",
++													 frameLength));
++
++	/* Adjust the length to be a multiple of block size if appropriate */
++	paddedLength = (frameLength + (endPoint->blockSize - 1)) &
++		(~(endPoint->blockSize - 1));
++
++	/*
++	 * Receive the frame(s). Pull an empty buffer from the head of the
++	 * Pending Receive Queue.
++	 */
++	element = removeFromMboxQueue(recvQueue);
++	mboxBuffer = GET_MBOX_BUFFER(element);
++	mboxBuffer->actualLength = paddedLength;
++
++	/* FIXME: async request */
++	status = sdio_memcpy_fromio(target->device, mboxBuffer->buffer,
++								endPoint->address,
++								mboxBuffer->actualLength);
++
++	if (status) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++						("Frame reception failed\n"));
++		if (!IS_ELEMENT_FREE(element)) {
++			mboxBuffer->actualLength = 0;
++			FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++						mboxBuffer->bufferLength, mboxBuffer->actualLength,
++						A_ECANCELED, mboxBuffer->cookie);
++			RECYCLE_DATA_REQUEST_ELEMENT(element);
++			dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED,
++						  &eventInfo);
++			AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++							("htcReceiveFrame - Exit\n"));
++		}
++		return;
++	}
++	if (element->completionCB)
++		element->completionCB(element, status);
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++					("htcReceiveFrame - Exit\n"));
++}
++
++u32 htcGetFrameLength(HTC_ENDPOINT * endPoint)
++{
++	HTC_TARGET *target;
++	u32 frameLength;
++	HTC_ENDPOINT_ID endPointId;
++
++	/* Get the context */
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++
++	AR_DEBUG_ASSERT(target->table.rx_lookahead_valid & (1 << endPointId));
++
++	/* The length is contained in the first two bytes - HTC_HEADER_LEN */
++	frameLength = (target->table.rx_lookahead[endPointId] & 0xFFFF) +
++		HTC_HEADER_LEN;
++	AR_DEBUG_ASSERT(frameLength);
++
++	return frameLength;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_send.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_send.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,359 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the transmit path.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern A_MUTEX_T creditCS;
++
++#ifdef CONFIG_AR6K_DEBUG
++extern u32 debughtc;
++extern u32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++#ifdef HTC_SYNC
++extern u32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern u32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++#endif
++
++extern u32 tx_attempt[HTC_MAILBOX_NUM_MAX];	/* Num of attempts to add */
++extern u32 tx_post[HTC_MAILBOX_NUM_MAX];	/* Num of attemps succeded */
++extern u32 tx_complete[HTC_MAILBOX_NUM_MAX];	/* Num of tx complete */
++
++/* ------ Functions ------ */
++int
++HTCBufferSend(HTC_TARGET * target,
++			  HTC_ENDPOINT_ID endPointId,
++			  u8 * buffer, u32 length, void *cookie)
++{
++	int status;
++	HTC_ENDPOINT *endPoint;
++	HTC_DATA_REQUEST_QUEUE *sendQueue;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("HTCBufferSend: Enter (endPointId: %d, buffer: 0x%p, length: %d, cookie: 0x%p)\n",
++					 endPointId, buffer, length, cookie));
++
++	AR_DEBUG_ASSERT((endPointId >= ENDPOINT1)
++					&& (endPointId <= ENDPOINT4));
++	AR_DEBUG_ASSERT(length);
++
++	/* Extract the end point instance */
++	endPoint = &target->endPoint[endPointId];
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	sendQueue = &endPoint->sendQueue;
++	AR_DEBUG_ASSERT(sendQueue != NULL);
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++					("mboxQueue: %p\n", sendQueue));
++
++	/*
++	 * Add this posted buffer to the pending send queue. We need to allocate
++	 * a bufferElement to store the packet information and we borrow that
++	 * buffer from the pending send queue. If circumstances allow us to
++	 * transmit it right away then we dequeue it otherwise we let it remain
++	 * to be picked in the interrupt handler context.
++	 */
++	tx_attempt[endPointId] += 1;
++
++	if (!endPoint->enabled) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Endpoint not enabled: %d\n",
++										GET_ENDPOINT_ID(endPoint)));
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("tx_attempt[%d] = %d, tx_post[%d] = %d, tx_complete[%d] = %d\n",
++						 endPointId, tx_attempt[endPointId], endPointId,
++						 tx_post[endPointId], endPointId,
++						 tx_complete[endPointId]));
++		return A_ERROR;
++	}
++
++	status = addToMboxQueue(sendQueue, buffer, length, 0, cookie);
++	if (status != A_OK) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++						("Mailbox (%d) PSQ full. Unable to add buffer\n",
++						 endPointId));
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++						("tx_attempt[%d] = %d, tx_post[%d] = %d, tx_complete[%d] = %d\n",
++						 endPointId, tx_attempt[endPointId], endPointId,
++						 tx_post[endPointId], endPointId,
++						 tx_complete[endPointId]));
++		return A_ERROR;
++	}
++
++	tx_post[endPointId] += 1;
++
++	/*
++	 * The frame shall be dequeued and sent if there are any credits
++	 * available.
++	 */
++	htcSendFrame(endPoint);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("HTCBufferSend: Exit\n"));
++	return A_OK;
++}
++
++
++void htcSendFrame(HTC_ENDPOINT * endPoint)
++{
++	int status;
++	HTC_TARGET *target;
++	u32 frameLength;
++	u32 paddedLength;
++	HTC_EVENT_INFO eventInfo;
++	u8 txCreditsConsumed;
++	u8 txCreditsAvailable;
++	HTC_ENDPOINT_ID endPointId;
++	HTC_QUEUE_ELEMENT *element;
++	HTC_MBOX_BUFFER *mboxBuffer;
++	HTC_REG_REQUEST_LIST *regList;
++	HTC_DATA_REQUEST_QUEUE *sendQueue;
++	HTC_REG_BUFFER *regBuffer;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("htcSendFrame - Enter\n"));
++
++	/* Get the context */
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	sendQueue = &endPoint->sendQueue;
++	AR_DEBUG_ASSERT(sendQueue != NULL);
++	regList = &target->regList;
++	AR_DEBUG_ASSERT(regList != NULL);
++
++	/*
++	 * Transmit the frames as long as we have the credits available and
++	 * the queue is not out of them
++	 */
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (credit): LOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_LOCK(&creditCS);
++	txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++	txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++	SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++	SET_TX_CREDITS_CONSUMED(endPoint,
++							txCreditsConsumed + txCreditsAvailable);
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (credit): UNLOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_UNLOCK(&creditCS);
++
++	/*
++	 * Send the packet only when there are packets to be sent and there
++	 * are positive number of credits available.
++	 */
++	while ((!IS_DATA_QUEUE_EMPTY(sendQueue)) && txCreditsAvailable) {
++		/* Get the request buffer from the Pending Send Queue */
++		element = removeFromMboxQueue(sendQueue);
++		mboxBuffer = GET_MBOX_BUFFER(element);
++
++		/*
++		 * Prepend the actual length in the first 2 bytes of the outgoing
++		 * packet.
++		 */
++		mboxBuffer->buffer -= HTC_HEADER_LEN;
++		A_MEMCPY(mboxBuffer->buffer, &mboxBuffer->bufferLength,
++				 HTC_HEADER_LEN);
++
++		/*
++		 * Adjust the length in the block mode only when its not an integral
++		 * multiple of the block size. Assumption is that the block size is
++		 * a power of 2.
++		 */
++		frameLength = mboxBuffer->bufferLength + HTC_HEADER_LEN;
++		paddedLength = (frameLength + (endPoint->blockSize - 1)) &
++			(~(endPoint->blockSize - 1));
++		mboxBuffer->actualLength = paddedLength;
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++						("Original frame length: %d, Padded frame length: %d\n",
++						 frameLength, paddedLength));
++
++		AR_DEBUG_PRINTBUF(mboxBuffer->buffer, mboxBuffer->actualLength);
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++						("Available Tx credits: %d\n",
++						 txCreditsAvailable));
++
++		/* Send the data to the bus driver, FIXME: async request */
++		status = sdio_memcpy_toio(target->device, endPoint->address, mboxBuffer->buffer, mboxBuffer->actualLength);
++		if (status) {
++			AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++							("Frame transmission failed\n"));
++			AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++							("EndPoint: %d, Tx credits available: %d\n",
++							 endPointId,
++							 GET_TX_CREDITS_AVAILABLE(endPoint)));
++			/*
++			 * We need to check just in case the callback routine was called
++			 * with the error status before we reach this point and in that
++			 * context we fee up the buffer so its just a conservative design.
++			 */
++			if (!IS_ELEMENT_FREE(element)) {
++				mboxBuffer->buffer += HTC_HEADER_LEN;
++				FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++							mboxBuffer->bufferLength,
++							mboxBuffer->actualLength,
++							A_ECANCELED, mboxBuffer->cookie);
++				RECYCLE_DATA_REQUEST_ELEMENT(element);
++				dispatchEvent(target, endPointId, HTC_BUFFER_SENT,
++							  &eventInfo);
++			}
++			AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++							("htcSendFrame - Exit\n"));
++			return;
++		}
++		if (element->completionCB)
++			element->completionCB(element, status);
++
++		txCreditsAvailable -= 1;
++		txCreditsConsumed += 1;
++
++#ifdef CONFIG_AR6K_DEBUG
++		txcreditsavailable[endPointId] = txCreditsAvailable;
++		txcreditsconsumed[endPointId] = txCreditsConsumed;
++#endif							/* DEBUG */
++
++		if (!txCreditsAvailable) {
++			u32 address;
++
++			AR_DEBUG_ASSERT(txCreditsConsumed);
++
++			/*
++			 * Instead of taking an interrupt we can just poll for more
++			 * credits that might have been queued up by now.
++			 */
++			address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, endPointId);
++			/* FIXME: async request */
++			status = sdio_readsb(target->device, &endPoint->txCreditsAvailable[1], address, txCreditsConsumed);
++
++#ifdef notyet
++			/* for async */
++			AR_DEBUG_ASSERT(status == A_OK);
++			AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++							("htcSendFrame - Exit\n"));
++			return;
++#else
++			if (status) {
++				printk(KERN_INFO "Failed to send frame: %d\n", status);
++				continue;
++			}
++
++			A_MUTEX_LOCK(&creditCS);
++
++			regBuffer = GET_REG_BUFFER(element);
++			/* Calculate the number of credits available */
++			AR_DEBUG_ASSERT(GET_TX_CREDITS_CONSUMED(endPoint) ==
++							regBuffer->length);
++			SET_TX_CREDITS_AVAILABLE(endPoint, regBuffer->buffer[0] -
++									 GET_TX_CREDITS_CONSUMED
++									 (endPoint));
++			SET_TX_CREDITS_CONSUMED(endPoint, 0);
++			txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++			txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++			AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++							("Critical Section (credit): UNLOCK at line %d in file %s\n",
++							 __LINE__, __FILE__));
++			A_MUTEX_UNLOCK(&creditCS);
++
++			AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++							("Pulling %d tx credits from the target\n",
++							 txCreditsAvailable));
++
++#ifdef CONFIG_AR6K_DEBUG
++			txcreditsavailable[endPointId] = txCreditsAvailable;
++			txcreditsconsumed[endPointId] = txCreditsConsumed;
++#endif							/* DEBUG */
++
++			freeRegRequestElement(element);
++
++			if (!txCreditsAvailable) {
++
++				/* Enable the Tx credit counter interrupt so that we
++				   can get the credits posted by the target */
++
++				htcEnableCreditCounterInterrupt(target, endPointId);
++
++				/* Counter Interrupts have been enabled if
++				   txCreditsAvailable is still 0 after polling. We
++				   need to return here as there is nothing we can send
++				   till we get a Counter Interrupt. */
++				return;
++			}
++		}
++#endif /* notyet */
++	}
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (credit): LOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_LOCK(&creditCS);
++	SET_TX_CREDITS_AVAILABLE(endPoint, txCreditsAvailable);
++	SET_TX_CREDITS_CONSUMED(endPoint, txCreditsConsumed);
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (credit): UNLOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_UNLOCK(&creditCS);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++					("htcSendFrame - Exit\n"));
++}
++
++void htcSendBlkSize(HTC_ENDPOINT * endPoint)
++{
++	int status;
++	u32 address;
++	HTC_TARGET *target;
++	HTC_ENDPOINT_ID endPointId;
++	HTC_QUEUE_ELEMENT *element;
++	HTC_MBOX_BUFFER *mboxBuffer;
++	HTC_DATA_REQUEST_QUEUE *sendQueue;
++	HTC_REG_REQUEST_LIST *regList;
++
++	/* Get the context */
++	AR_DEBUG_ASSERT(endPoint != NULL);
++	target = endPoint->target;
++	AR_DEBUG_ASSERT(target != NULL);
++	regList = &target->regList;
++	AR_DEBUG_ASSERT(regList != NULL);
++	sendQueue = &endPoint->sendQueue;
++	AR_DEBUG_ASSERT(sendQueue != NULL);
++	endPointId = GET_ENDPOINT_ID(endPoint);
++
++	/* Decrement the tx credit count */
++	AR_DEBUG_ASSERT(endPoint->txCreditsConsumed == 0);
++	endPoint->txCreditsConsumed = 1;
++	address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, endPointId);
++	/* FIXME: async request */
++	status = sdio_readsb(target->device, &endPoint->txCreditsAvailable[1], address, endPoint->txCreditsConsumed);
++
++	/* Negotiate the maximum block size for the endpoint */
++	addToMboxQueue(sendQueue, (u8 *) & endPoint->blockSize,
++				   sizeof(endPoint->blockSize),
++				   sizeof(endPoint->blockSize), NULL);
++	element = removeFromMboxQueue(sendQueue);
++	element->completionCB = htcBlkSzNegCompletionCB;
++	mboxBuffer = GET_MBOX_BUFFER(element);
++	status = sdio_memcpy_toio(target->device, endPoint->address, mboxBuffer->buffer, mboxBuffer->bufferLength);
++	if (!status)
++		element->completionCB(element, status);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++					("Mailbox(%d), Block size: %d\n",
++					 endPointId, endPoint->blockSize));
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_utils.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/htc_utils.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,394 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the utility routines used across the entire HTC module.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern HTC_TARGET *AtherosTargetList[HIF_MAX_DEVICES];
++extern HTC_GLOBAL_EVENT_TABLE AtherosEventTable;
++extern A_MUTEX_T instanceCS;
++
++#ifdef CONFIG_AR6K_DEBUG
++extern u32 debughtc;
++#endif
++
++/* ------ Static Variables ------ */
++
++/* ------ Functions ------ */
++void
++dispatchEvent(HTC_TARGET * target,
++	      HTC_ENDPOINT_ID endPointId,
++	      HTC_EVENT_ID eventId, HTC_EVENT_INFO * eventInfo)
++{
++	EVENT_TABLE_ELEMENT *eventElement;
++	int claim = 0;
++
++	if (eventId == HTC_TARGET_AVAILABLE) {
++		eventElement = &AtherosEventTable.element[0];
++	} else if (eventId == HTC_TARGET_UNAVAILABLE) {
++		eventElement = &AtherosEventTable.element[1];
++	} else {
++		claim = 1;
++		eventElement =
++			&target->endPoint[endPointId].eventTable.element[eventId];
++	}
++	AR_DEBUG_ASSERT(eventElement != NULL);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("dispatchEvent(endpoint: %d, eventId: 0x%d, handler: 0x%p)\n",
++					 endPointId, eventElement->id, eventElement->handler));
++	if (eventElement->handler) {
++		if (claim)
++			sdio_claim_host(target->device);
++		eventElement->handler(target, endPointId, eventId, eventInfo,
++				      eventElement->param);
++		if (claim)
++			sdio_release_host(target->device);
++	}
++}
++
++
++int
++addToEventTable(HTC_TARGET * target,
++				HTC_ENDPOINT_ID endPointId,
++				HTC_EVENT_ID eventId,
++				HTC_EVENT_HANDLER handler, void *param)
++{
++	EVENT_TABLE_ELEMENT *new;
++
++	if (eventId == HTC_TARGET_AVAILABLE) {
++		new = &AtherosEventTable.element[0];
++	} else if (eventId == HTC_TARGET_UNAVAILABLE) {
++		new = &AtherosEventTable.element[1];
++	} else {
++		new = &target->endPoint[endPointId].eventTable.element[eventId];
++	}
++
++	/* Store the event id, the corresponding handler and the param passed */
++	new->id = eventId;
++	new->handler = handler;
++	new->param = param;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++					("addToEventTable(endpoint: %d, eventId: 0x%d, handler: 0x%p)\n",
++					 endPointId, new->id, new->handler));
++
++	return A_OK;
++}
++
++
++int
++removeFromEventTable(HTC_TARGET * target,
++					 HTC_ENDPOINT_ID endPointId, HTC_EVENT_ID eventId)
++{
++	EVENT_TABLE_ELEMENT *remove;
++
++	if (eventId == HTC_TARGET_AVAILABLE) {
++		remove = &AtherosEventTable.element[0];
++	} else if (eventId == HTC_TARGET_UNAVAILABLE) {
++		remove = &AtherosEventTable.element[1];
++	} else {
++		remove = &target->endPoint[endPointId].eventTable.element[eventId];
++	}
++
++	/* Remove the event handler */
++	A_MEMZERO(remove, sizeof(EVENT_TABLE_ELEMENT));
++
++	return A_OK;
++}
++
++int
++addToMboxQueue(HTC_DATA_REQUEST_QUEUE * queue,
++			   u8 * buffer,
++			   u32 bufferLength, u32 actualLength, void *cookie)
++{
++	int status;
++	HTC_DATA_REQUEST_ELEMENT *element;
++
++	AR_DEBUG_ASSERT(queue != NULL);
++	AR_DEBUG_ASSERT(bufferLength);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (queue): LOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_LOCK(&instanceCS);
++	element = GET_QUEUE_TAIL(queue);
++	if (!(IS_DATA_QUEUE_FULL(queue)) && IS_ELEMENT_FREE(element)) {
++		element->buffer.free = FALSE;
++		FILL_MBOX_BUFFER(element, buffer, bufferLength, actualLength,
++						 cookie);
++		queue->size += 1;
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("addToMboxQueue (index: %d, size: %d, bufferElement: 0x%p, bufferElement->buffer: 0x%p, bufferElement->cookie: 0x%p)\n",
++						 (queue->head + queue->size -
++						  1) % HTC_DATA_REQUEST_RING_BUFFER_SIZE,
++						 queue->size, element,
++						 (GET_MBOX_BUFFER(element))->buffer,
++						 (GET_MBOX_BUFFER(element))->cookie));
++		status = A_OK;
++	} else {
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Queue size: %d\n", queue->size));
++		status = A_ERROR;
++	}
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (queue): UNLOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_UNLOCK(&instanceCS);
++
++	return status;
++}
++
++HTC_DATA_REQUEST_ELEMENT *removeFromMboxQueue(HTC_DATA_REQUEST_QUEUE *
++											  queue)
++{
++	HTC_DATA_REQUEST_ELEMENT *element;
++	AR_DEBUG_ASSERT(queue != NULL);
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (queue): LOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_LOCK(&instanceCS);
++	if (!(IS_DATA_QUEUE_EMPTY(queue))) {
++		element = GET_QUEUE_HEAD(queue);
++		queue->head =
++			(queue->head + 1) % HTC_DATA_REQUEST_RING_BUFFER_SIZE;
++		queue->size -= 1;
++
++		AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++						("removeFromMboxQueue (index: %d, size: %d, bufferElement: 0x%p, bufferElement->buffer: 0x%p, bufferElement->cookie: 0x%p)\n",
++						 queue->head, queue->size, element,
++						 (GET_MBOX_BUFFER(element))->buffer,
++						 (GET_MBOX_BUFFER(element))->cookie));
++	} else {
++		element = NULL;
++	}
++	AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++					("Critical Section (queue): UNLOCK at line %d in file %s\n",
++					 __LINE__, __FILE__));
++	A_MUTEX_UNLOCK(&instanceCS);
++
++	return element;
++}
++
++void
++flushMboxQueue(HTC_ENDPOINT * endPoint,
++			   HTC_DATA_REQUEST_QUEUE * queue, HTC_EVENT_ID eventId)
++{
++	HTC_DATA_REQUEST_ELEMENT *curr;
++	HTC_EVENT_INFO eventInfo;
++	HTC_ENDPOINT_EVENT_TABLE *eventTable;
++	HTC_ENDPOINT_ID endPointId;
++	EVENT_TABLE_ELEMENT *eventElement;
++	HTC_MBOX_BUFFER *mboxBuffer;
++
++	eventTable = &endPoint->eventTable;
++	endPointId = GET_ENDPOINT_ID(endPoint);
++
++	/*
++	 * Release the buffer to WMI using the registered event handler. If WMI
++	 * has not registered any callbacks for a particular endpoint then it
++	 * means that its queues will not have any buffers so we skip that
++	 * endpoint.
++	 */
++	if ((eventElement = &eventTable->element[eventId]) != NULL) {
++		while ((curr = removeFromMboxQueue(queue)) != NULL) {
++			/* Frame the event and dispatch it */
++			mboxBuffer = GET_MBOX_BUFFER(curr);
++			FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++						mboxBuffer->bufferLength, mboxBuffer->actualLength,
++						A_ECANCELED, mboxBuffer->cookie);
++			if (eventElement->handler) {
++				eventElement->handler(endPoint->target, endPointId,
++									  eventId, &eventInfo,
++									  eventElement->param);
++			}
++			RECYCLE_DATA_REQUEST_ELEMENT(curr);
++		}
++	}
++
++	/* Initialize the head and tail pointer */
++	queue->head = 0;
++	queue->size = 0;
++}
++
++HTC_REG_REQUEST_ELEMENT *allocateRegRequestElement(HTC_TARGET * target)
++{
++	u32 count;
++	HTC_REG_REQUEST_ELEMENT *element;
++
++	A_MUTEX_LOCK(&instanceCS);
++	element = NULL;
++	for (count = 0; count < HTC_REG_REQUEST_LIST_SIZE; count++) {
++		element = &target->regList.element[count];
++		if (IS_ELEMENT_FREE(element)) {
++			element->buffer.free = FALSE;
++			break;
++		}
++	}
++	A_MUTEX_UNLOCK(&instanceCS);
++
++	return element;
++}
++
++void freeRegRequestElement(HTC_REG_REQUEST_ELEMENT * element)
++{
++	A_MUTEX_LOCK(&instanceCS);
++	FILL_REG_BUFFER(element, NULL, 0, 0, 0);
++	element->buffer.free = TRUE;
++	A_MUTEX_UNLOCK(&instanceCS);
++}
++
++HTC_TARGET *getTargetInstance(void *device)
++{
++	return AtherosTargetList[0];
++}
++
++void addTargetInstance(HTC_TARGET * target)
++{
++	AtherosTargetList[0] = target;
++}
++
++void delTargetInstance(HTC_TARGET * target)
++{
++	AtherosTargetList[0] = NULL;
++}
++
++u32 getRegAddr(TARGET_REGISTERS base, HTC_ENDPOINT_ID endPointId)
++{
++	u32 address;
++
++	switch (base) {
++	case TX_CREDIT_COUNTER_RESET_REG:
++		address = COUNT_DEC_ADDRESS + endPointId * 4;
++		break;
++
++	case TX_CREDIT_COUNTER_DECREMENT_REG:
++		address =
++			COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + endPointId) * 4;
++		break;
++
++	case TX_CREDIT_COUNTER_REG:
++		address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + endPointId) * 4;
++		break;
++
++	case INT_STATUS_ENABLE_REG:
++		address = INT_STATUS_ENABLE_ADDRESS;
++		break;
++
++	case COUNTER_INT_STATUS_ENABLE_REG:
++	case COUNTER_INT_STATUS_DISABLE_REG:
++		address = COUNTER_INT_STATUS_ENABLE_ADDRESS;
++		break;
++
++	case INT_STATUS_REG:
++		address = HOST_INT_STATUS_ADDRESS;
++		break;
++
++	case CPU_INT_STATUS_REG:
++		address = CPU_INT_STATUS_ADDRESS;
++		break;
++
++	case ERROR_INT_STATUS_REG:
++		address = ERROR_INT_STATUS_ADDRESS;
++		break;
++
++	case INT_WLAN_REG:
++		address = INT_WLAN_ADDRESS;
++		break;
++
++	case WINDOW_DATA_REG:
++		address = WINDOW_DATA_ADDRESS;
++		break;
++
++	case WINDOW_WRITE_ADDR_REG:
++		address = WINDOW_WRITE_ADDR_ADDRESS;
++		break;
++
++	case WINDOW_READ_ADDR_REG:
++		address = WINDOW_READ_ADDR_ADDRESS;
++		break;
++
++	default:
++		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid register: %d\n", base));
++		AR_DEBUG_ASSERT(0);
++		address = 0;
++		break;
++	}
++
++	return address;
++}
++
++void dumpBytes(u8 * buffer, u16 length)
++{
++	u8 stream[60];
++	u32 i;
++	u16 offset, count;
++
++	AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
++					("Dumping %d Bytes : ------>\n", length));
++
++	count = 0;
++	offset = 0;
++	for (i = 0; i < length; i++) {
++		sprintf(stream + offset, "%2x ", buffer[i]);
++		count++;
++		offset += 3;
++
++		if (count == 16) {
++			count = 0;
++			offset = 0;
++			AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("[H]: %s\n", stream));
++			A_MEMZERO(stream, 60);
++		}
++	}
++
++	if (offset != 0) {
++		AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("[H]: %s\n", stream));
++	}
++}
++
++void dumpRegisters(HTC_TARGET * target)
++{
++	HTC_REGISTER_TABLE *reg;
++
++	reg = &target->table;
++	AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
++					("\n<------- Register Table -------->\nInt Status:                0x%x\nCPU Int Status:            0x%x\nError Int Status:          0x%x\nCounter Int Status:        0x%x\nMbox Frame:                0x%x\nRx Lookahead Valid:        0x%x\nRx Lookahead 0:            0x%x\nRx Lookahead 1:            0x%x\nRx Lookahead 2:            0x%x\nRx Lookahead 3:            0x%x\nInt Status Enable:         0x%x\nCounter Int Status Enable: 0x%x\n<------------------------------->\n",
++					 reg->host_int_status, reg->cpu_int_status,
++					 reg->error_int_status, reg->counter_int_status,
++					 reg->mbox_frame, reg->rx_lookahead_valid,
++					 reg->rx_lookahead[ENDPOINT1],
++					 reg->rx_lookahead[ENDPOINT2],
++					 reg->rx_lookahead[ENDPOINT3],
++					 reg->rx_lookahead[ENDPOINT4], reg->int_status_enable,
++					 reg->counter_int_status_enable));
++}
++
++u8 htcGetBitNumSet(u32 data)
++{
++	u8 count;
++
++	count = 0;
++	while (!(data & 0x1)) {
++		count += 1;
++		data >>= 1;
++	}
++
++	return count;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/htc/Makefile	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO ar6000 wlan htc function driver
++#
++obj-$(CONFIG_AR6K)	+= htc.o htc_events.o htc_recv.o htc_send.o htc_utils.o
++
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/app/dset.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/app/dset.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,77 @@
++#ifndef _DSET_H_
++#define _DSET_H_
++
++/*
++ * Structures used to communicate between an application and the kernel for
++ * DataSet ioctls.
++ *
++ * Pass a dset_request_t with cmd=AR6000_XIOCTL_WMI_WAITDSETREQ in order to
++ * wait for the next DataSet Request to arrive.  Once a request is received
++ * from the Target, the kernel fills in information about the Request and
++ * returns from the ioctl to the application.  When the ioctl returns,
++ * cmd is set to either AR6000_OPEN_REQ or AR6000_DATA_REQ.
++ *
++ * Pass a dset_open_reply_t with cmd=AR6000_IOCTL_WMI_DSET_OPEN_REPLY in order
++ * to send a DataSet Open reply to the Target.  The targ_* fields should simply
++ * be copied from the original Open Request.  The status field should be set
++ * to 0 for success or non-zero for failure.
++ *
++ * Pass a dset_data_reply_t with cmd=AR6000_IOCTL_WMI_DSET_DATA_REPLY in order
++ * to send a DataSet Data reply to the Target.  The targ_* fields should simply
++ * be copied from the original Data Request.  The status field should be set
++ * to 0 for success or non-zero for failure.  The buf field is a pointer
++ * to a buffer that contains the requested data.
++ */
++
++/* A DataSet Request, either Open Request or Data Request */
++typedef struct dset_request_s {
++    unsigned int      cmd;
++    union {
++        struct open_req_s {
++            unsigned int        id;
++            unsigned int        targ_handle;
++            unsigned int        targ_reply_fn;
++            unsigned int        targ_reply_arg;
++        } open_req;
++        struct data_req_s {
++            unsigned int        access_cookie;
++            unsigned int        offset;
++            unsigned int        length;
++            unsigned int        targ_buf;
++            unsigned int        targ_reply_fn;
++            unsigned int        targ_reply_arg;
++        } data_req;
++    } u;
++} dset_request_t;
++
++/*
++ * Values in cmd on return from an AR6000_IOCTL_EXTENDED ioctl that had
++ * cmd=AR6000_XIOCTL_WMI_WAITDSETREQ.
++ */
++#define AR6000_OPEN_REQ         1
++#define AR6000_DATA_REQ         2
++
++/* Open Reply from Application to Kernel (to be sent to Target) */
++typedef struct dset_open_reply {
++    unsigned int        cmd;
++    unsigned int        status;
++    unsigned int        targ_handle;
++    unsigned int        targ_reply_fn;
++    unsigned int        targ_reply_arg;
++    unsigned int        access_cookie;
++    unsigned int        size;
++    unsigned int        version;
++} dset_open_reply_t;
++
++/* Data Reply from Application to Kernel (to be sent to Target) */
++typedef struct dset_data_reply {
++    unsigned int        cmd;
++    unsigned int        status;
++    char               *buf;
++    unsigned int        length;
++    unsigned int        targ_buf;
++    unsigned int        targ_reply_fn;
++    unsigned int        targ_reply_arg;
++} dset_data_reply_t;
++
++#endif /* _DSET_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_bmi.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_bmi.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,136 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++#ifndef __AR6000_BMI_H__
++#define __AR6000_BMI_H__
++
++/*
++ * Bootloader Messaging Interface (BMI)
++ *
++ * BMI is a very simple messaging interface used during initialization
++ * to read memory, write memory, execute code, and to define an
++ * application entry PC.
++ *
++ * It is used to download an application to AR6000, to provide
++ * patches to code that is already resident on AR6000, and generally
++ * to examine and modify state.  The Host has an opportunity to use
++ * BMI only once during bootup.  Once the Host issues a BMI_DONE
++ * command, this opportunity ends.
++ *
++ * The Host writes BMI requests to mailbox0, and reads BMI responses
++ * from mailbox0.   BMI requests all begin with a command
++ * (see below for specific commands), and are followed by
++ * command-specific data.
++ *
++ * Flow control:
++ * The Host can only issue a command once the Target gives it a
++ * "BMI Command Credit", using AR6000 Counter #4.  As soon as the
++ * Target has completed a command, it issues another BMI Command
++ * Credit (so the Host can issue the next command).
++ *
++ * BMI handles all required Target-side cache flushing.
++ */
++
++
++/* Maximum data size used for BMI transfers */
++#define BMI_DATASZ_MAX                     32
++
++/* BMI Commands */
++
++#define BMI_NO_COMMAND                      0
++
++#define BMI_DONE                            1
++		/*
++		 * Semantics: Host is done using BMI
++		 * Request format:
++		 *    u32      command (BMI_DONE)
++		 * Response format: none
++		 */
++
++#define BMI_READ_MEMORY                     2
++		/*
++		 * Semantics: Host reads AR6000 memory
++		 * Request format:
++		 *    u32      command (BMI_READ_MEMORY)
++		 *    u32      address
++		 *    u32      length, at most BMI_DATASZ_MAX
++		 * Response format:
++		 *    u8       data[length]
++		 */
++
++#define BMI_WRITE_MEMORY                    3
++		/*
++		 * Semantics: Host writes AR6000 memory
++		 * Request format:
++		 *    u32       command (BMI_WRITE_MEMORY)
++		 *    u32      address
++		 *    u32      length, at most BMI_DATASZ_MAX
++		 *    u8       data[length]
++		 * Response format: none
++		 */
++
++#define BMI_EXECUTE                         4
++		/*
++		 * Semantics: Causes AR6000 to execute code
++		 * Request format:
++		 *    u32      command (BMI_EXECUTE)
++		 *    u32      address
++		 *    u32      parameter
++		 * Response format:
++		 *    u32      return value
++		 */
++
++#define BMI_SET_APP_START                   5
++		/*
++		 * Semantics: Set Target application starting address
++		 * Request format:
++		 *    u32      command (BMI_SET_APP_START)
++		 *    u32      address
++		 * Response format: none
++		 */
++
++#define BMI_READ_SOC_REGISTER               6
++		/*
++		 * Semantics: Read a 32-bit Target SOC register.
++		 * Request format:
++		 *    u32      command (BMI_READ_REGISTER)
++		 *    u32      address
++		 * Response format:
++		 *    u32      value
++		 */
++
++#define BMI_WRITE_SOC_REGISTER              7
++		/*
++		 * Semantics: Write a 32-bit Target SOC register.
++		 * Request format:
++		 *    u32      command (BMI_WRITE_REGISTER)
++		 *    u32      address
++		 *    u32      value
++		 *
++		 * Response format: none
++		 */
++
++#define BMI_GET_TARGET_ID                  8
++		/*
++		 * Semantics: Fetch the 4-byte Target ID.
++		 * Request format:
++		 *    u32      command (BMI_GET_TARGET_ID)
++		 *
++		 * Response format:
++		 *    u32      TargetID
++		 */
++
++#endif							/* __AR6000_BMI_H__ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_gpio.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_gpio.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,39 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++
++#define GPIO_PIN_COUNT 18
++
++/*
++ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
++ * NB: These match hardware order, so that addresses can
++ * easily be computed.
++ */
++#define GPIO_ID_OUT             0x00000000
++#define GPIO_ID_OUT_W1TS        0x00000001
++#define GPIO_ID_OUT_W1TC        0x00000002
++#define GPIO_ID_ENABLE          0x00000003
++#define GPIO_ID_ENABLE_W1TS     0x00000004
++#define GPIO_ID_ENABLE_W1TC     0x00000005
++#define GPIO_ID_IN              0x00000006
++#define GPIO_ID_STATUS          0x00000007
++#define GPIO_ID_STATUS_W1TS     0x00000008
++#define GPIO_ID_STATUS_W1TC     0x00000009
++#define GPIO_ID_PIN0            0x0000000a
++#define GPIO_ID_PIN(n)          (GPIO_ID_PIN0+(n))
++
++#define GPIO_LAST_REGISTER_ID   GPIO_ID_PIN(17)
++#define GPIO_ID_NONE            0xffffffff
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_version.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/AR6000_version.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,44 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++
++#define __VER_MAJOR_ 1
++#define __VER_MINOR_ 1
++#define __VER_PATCH_ 0
++
++
++/* The makear6ksdk script (used for release builds) modifies the following line. */
++#define __BUILD_NUMBER_ 2
++
++
++/* Format of the version number. */
++#define VER_MAJOR_BIT_OFFSET		28
++#define VER_MINOR_BIT_OFFSET		24
++#define VER_PATCH_BIT_OFFSET		16
++#define VER_BUILD_NUM_BIT_OFFSET	0
++
++
++/*
++ * The version has the following format:
++ * Bits 28-31: Major version
++ * Bits 24-27: Minor version
++ * Bits 16-23: Patch version
++ * Bits 0-15:  Build number (automatically generated during build process )
++ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
++ *
++ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
++ */
++#define AR6000_SW_VERSION 	( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ar6k_api.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ar6k_api.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the API to access the OS dependent atheros host driver
++ * by the WMI or WLAN generic modules.
++ *
++ */
++
++#ifndef _AR6000_API_H_
++#define _AR6000_API_H_
++
++	struct ar6_softc;
++
++	void ar6k_ready_event(void *devt, u8 * datap, u8 phyCap);
++	u8 ar6k_iptos_to_userPriority(u8 * pkt);
++	int ar6k_control_tx(void *devt, struct sk_buff *skb, int endPt);
++	void ar6k_connect_event(struct ar6_softc *ar, u16 channel,
++							  u8 * bssid, u16 listenInterval,
++							  u8 beaconIeLen, u8 assocReqLen,
++							  u8 assocRespLen, u8 * assocInfo);
++	void ar6k_disconnect_event(struct ar6_softc *ar, u8 reason,
++								 u8 * bssid, u8 assocRespLen,
++								 u8 * assocInfo);
++	void ar6k_tkip_micerr_event(struct ar6_softc *ar, u8 keyid,
++								  u8 ismcast);
++	void ar6k_bitrate_rx(void *devt, s32 rateKbps);
++	void ar6k_channelList_rx(void *devt, int numChan, u16 * chanList);
++	void ar6k_regDomain_event(struct ar6_softc *ar, u32 regCode);
++	void ar6k_txPwr_rx(void *devt, u8 txPwr);
++	void ar6k_neighborReport_event(struct ar6_softc *ar, int numAps,
++									 WMI_NEIGHBOR_INFO * info);
++	void ar6k_set_numdataendpts(struct ar6_softc *ar, u32 num);
++	void ar6k_scanComplete_event(struct ar6_softc *ar);
++	void ar6k_targetStats_event(struct ar6_softc *ar,
++								  WMI_TARGET_STATS * pStats);
++	void ar6k_rssiThreshold_event(struct ar6_softc *,
++									WMI_RSSI_THRESHOLD_VAL);
++	void ar6k_reportError_event(struct ar6_softc *,
++								  WMI_TARGET_ERROR_VAL errorVal);
++	void ar6k_cac_event(struct ar6_softc *ar, u8 ac, u8 cac_indication,
++						  u8 statusCode, u8 * tspecSuggestion);
++
++	void
++	 ar6k_roam_tbl_event(struct ar6_softc *ar,
++						   WMI_TARGET_ROAM_TBL * pTbl);
++
++	void
++	 ar6k_roam_data_event(struct ar6_softc **ar,
++							WMI_TARGET_ROAM_DATA * p);
++
++	void ar6k_dset_open_req(void *devt,
++							  u32 id,
++							  u32 targ_handle,
++							  u32 targ_reply_fn, u32 targ_reply_arg);
++	void ar6k_dset_close(void *devt, u32 access_cookie);
++	void ar6k_dset_data_req(void *devt,
++							  u32 access_cookie,
++							  u32 offset,
++							  u32 length,
++							  u32 targ_buf,
++							  u32 targ_reply_fn, u32 targ_reply_arg);
++
++	void ar6k_gpio_intr_rx(u32 intr_mask, u32 input_values);
++	void ar6k_gpio_data_rx(u32 reg_id, u32 value);
++	void ar6k_gpio_ack_rx(void);
++
++#endif							/* _AR6000_API_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/athdefs.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/athdefs.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,85 @@
++
++#ifndef __ATHDEFS_H__
++#define __ATHDEFS_H__
++
++/*
++ * This file contains definitions that may be used across both
++ * Host and Target software.  Nothing here is module-dependent
++ * or platform-dependent.
++ */
++
++/*
++ * Generic error codes that can be used by hw, sta, ap, sim, dk
++ * and any other environments. Since these are enums, feel free to
++ * add any more codes that you need.
++ */
++
++enum {
++	A_ERROR = -1,				/* Generic error return */
++	A_OK = 0,					/* success */
++	/* Following values start at 1 */
++	A_DEVICE_NOT_FOUND,			/* not able to find PCI device */
++	A_NO_MEMORY,				/* not able to allocate memory, not
++								   available */
++	A_MEMORY_NOT_AVAIL,			/* memory region is not free for mapping */
++	A_NO_FREE_DESC,				/* no free descriptors available */
++	A_BAD_ADDRESS,				/* address does not match descriptor */
++	A_WIN_DRIVER_ERROR,			/* used in NT_HW version, if problem at
++								   init */
++	A_REGS_NOT_MAPPED,			/* registers not correctly mapped */
++	A_EPERM,					/* Not superuser */
++	A_EACCES,					/* Access denied */
++	A_ENOENT,					/* No such entry, search failed, etc. */
++	A_EEXIST,					/* The object already exists (can't
++								   create) */
++	A_EFAULT,					/* Bad address fault */
++	A_EBUSY,					/* Object is busy */
++	A_EINVAL,					/* Invalid parameter */
++	A_EMSGSIZE,					/* Inappropriate message buffer length */
++	A_ECANCELED,				/* Operation canceled */
++	A_ENOTSUP,					/* Operation not supported */
++	A_ECOMM,					/* Communication error on send */
++	A_EPROTO,					/* Protocol error */
++	A_ENODEV,					/* No such device */
++	A_EDEVNOTUP,				/* device is not UP */
++	A_NO_RESOURCE,				/* No resources for requested operation */
++	A_HARDWARE,					/* Hardware failure */
++	A_PENDING,					/* Asynchronous routine; will send up
++								   results la ter (typically in callback) */
++	A_EBADCHANNEL,				/* The channel cannot be used */
++	A_DECRYPT_ERROR,			/* Decryption error */
++	A_PHY_ERROR,				/* RX PHY error */
++	A_CONSUMED					/* Object was consumed */
++};
++
++#define A_SUCCESS(x)        (x == A_OK)
++#define A_FAILED(x)         (!A_SUCCESS(x))
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++/*
++ * The following definition is WLAN specific definition
++ */
++typedef enum {
++	MODE_11A = 0,				/* 11a Mode */
++	MODE_11G = 1,				/* 11g + 11b Mode */
++	MODE_11B = 2,				/* 11b Mode */
++	MODE_11GONLY = 3,			/* 11g only Mode */
++	MODE_UNKNOWN = 4,
++
++	MODE_MAX = 4
++} WLAN_PHY_MODE;
++
++typedef enum {
++	WLAN_11A_CAPABILITY = 1,
++	WLAN_11G_CAPABILITY = 2,
++	WLAN_11AG_CAPABILITY = 3,
++} WALN_CAPABILITY;
++
++#endif							/* __ATHDEFS_H__ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/athdrv.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/athdrv.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,597 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the AR6000 linux driver.
++ *
++ */
++
++#ifndef _ATHDRV_H_
++#define _ATHDRV_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*
++ * There are two types of ioctl's here: Standard ioctls and
++ * eXtended ioctls.  All extended ioctls (XIOCTL) are multiplexed
++ * off of the single ioctl command, AR6000_IOCTL_EXTENDED.  The
++ * arguments for every XIOCTL starts with a 32-bit command word
++ * that is used to select which extended ioctl is in use.  After
++ * the command word are command-specific arguments.
++ */
++
++/* Linux standard Wireless Extensions, private ioctl interfaces */
++#define IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)
++#define IEEE80211_IOCTL_GETPARAM             (SIOCIWFIRSTPRIV+1)
++#define IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+2)
++#define IEEE80211_IOCTL_SETWMMPARAMS         (SIOCIWFIRSTPRIV+3)
++#define IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+4)
++#define IEEE80211_IOCTL_GETWMMPARAMS         (SIOCIWFIRSTPRIV+5)
++#define IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+6)
++#define IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+6)
++#define IEEE80211_IOCTL_GETOPTIE             (SIOCIWFIRSTPRIV+7)
++#define IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+8)
++//#define IEEE80211_IOCTL_SETAUTHALG           (SIOCIWFIRSTPRIV+10)
++#define IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+9)
++
++
++
++/*                      ====WMI Ioctls====                                    */
++/*
++ *
++ * Many ioctls simply provide WMI services to application code:
++ * an application makes such an ioctl call with a set of arguments
++ * that are packaged into the corresponding WMI message, and sent
++ * to the Target.
++ */
++
++#define AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+10)
++/*
++ * arguments:
++ *   ar6k_version *revision
++ */
++
++#define AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+11)
++/*
++ * arguments:
++ *   WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
++ * uses: WMI_SET_POWER_MODE_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+12)
++/*
++ * arguments:
++ *   WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
++ * uses: WMI_SET_SCAN_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+13)
++/*
++ * arguments:
++ *   UINT32 listenInterval
++ * uses: WMI_SET_LISTEN_INT_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+14)
++/*
++ * arguments:
++ *   WMI_BSS_FILTER filter (see include/wmi.h)
++ * uses: WMI_SET_BSS_FILTER_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)
++/*
++ * arguments:
++ *   WMI_CHANNEL_PARAMS_CMD chParams
++ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)
++/*
++ * arguments:
++ *   WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
++ * uses: WMI_SETPROBED_SSID_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)
++/*
++ * arguments:
++ *   WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
++ * uses: WMI_SET_POWER_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)
++/*
++ * arguments:
++ *   WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
++ * uses: WMI_ADD_BAD_AP_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)
++/*
++ * arguments:
++ *   ar6k_queuereq queueRequest (see below)
++ */
++
++#define AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)
++/*
++ * arguments:
++ *   WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
++ * uses: WMI_CREATE_PSTREAM_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)
++/*
++ * arguments:
++ *   WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
++ * uses: WMI_DELETE_PSTREAM_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_LINKTHRESHOLD   (SIOCIWFIRSTPRIV+23)
++/*
++ * arguments:
++ *   WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
++ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
++/*
++ * arguments:
++ *   WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
++ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)
++/*
++ * arguments:
++ *   TARGET_STATS *targetStats (see below)
++ * uses: WMI_GET_STATISTICS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)
++/*
++ * arguments:
++ *   WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
++ * uses: WMI_SET_ASSOC_INFO_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)
++/*
++ * arguments:
++ *   WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
++ * uses: WMI_SET_ACCESS_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)
++/*
++ * arguments:
++ *   UINT32 beaconMissTime
++ * uses: WMI_SET_BMISS_TIME_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)
++/*
++ * arguments:
++ *   WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
++ * uses: WMI_SET_DISC_TIMEOUT_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)
++/*
++ * arguments:
++ *   WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
++ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
++ */
++
++/*
++ * There is a very small space available for driver-private
++ * wireless ioctls.  In order to circumvent this limitation,
++ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
++ * single AR6000_IOCTL_EXTENDED ioctl.
++ */
++#define AR6000_IOCTL_EXTENDED                (SIOCIWFIRSTPRIV+31)
++
++
++/*                         ====BMI Extended Ioctls====                        */
++
++#define AR6000_XIOCTL_BMI_DONE                 1
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
++ * uses: BMI_DONE
++ */
++
++#define AR6000_XIOCTL_BMI_READ_MEMORY          2
++/*
++ * arguments:
++ *   union {
++ *     struct {
++ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
++ *       UINT32 address
++ *       UINT32 length
++ *     }
++ *     char results[length]
++ *   }
++ * uses: BMI_READ_MEMORY
++ */
++
++#define AR6000_XIOCTL_BMI_WRITE_MEMORY         3
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
++ *   UINT32 address
++ *   UINT32 length
++ *   char data[length]
++ * uses: BMI_WRITE_MEMORY
++ */
++
++#define AR6000_XIOCTL_BMI_EXECUTE              4
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
++ *   UINT32 TargetAddress
++ *   UINT32 parameter
++ * uses: BMI_EXECUTE
++ */
++
++#define AR6000_XIOCTL_BMI_SET_APP_START        5
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
++ *   UINT32 TargetAddress
++ * uses: BMI_SET_APP_START
++ */
++
++#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER    6
++/*
++ * arguments:
++ *   union {
++ *     struct {
++ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
++ *       UINT32 TargetAddress, 32-bit aligned
++ *     }
++ *     UINT32 result
++ *   }
++ * uses: BMI_READ_SOC_REGISTER
++ */
++
++#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER   7
++/*
++ * arguments:
++ *     struct {
++ *       UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
++ *       UINT32 TargetAddress, 32-bit aligned
++ *       UINT32 newValue
++ *     }
++ * uses: BMI_WRITE_SOC_REGISTER
++ */
++
++#define AR6000_XIOCTL_BMI_TEST                 8
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
++ *   UINT32 address
++ *   UINT32 length
++ *   UINT32 count
++ */
++
++
++
++/*                      ====DataSet Extended Ioctls====                       */
++
++#define AR6000_XIOCTL_WMI_DSET_WAIT_REQ        9
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_WMI_DSET_WAIT_REQ)
++ */
++
++#define AR6000_XIOCTL_WMI_DSET_OPEN_REPLY     10
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_WMI_DSET_OPEN_REPLY)
++ *   dset_open_reply_t (see host/include/app/dset.h)
++ * uses: WMIX_DSETOPEN_REPLY_CMDID
++ */
++
++#define AR6000_XIOCTL_WMI_DSET_DATA_REPLY     11
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_WMI_DSET_DATA_REPLY)
++ *   dset_data_reply_t (see host/include/app/dset.h)
++ * uses: WMIX_DSETDATA_REPLY_CMDID
++ */
++
++#define AR6000_XIOCTL_FORCE_TARGET_RESET      12
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
++ */
++
++
++#ifdef HTC_RAW_INTERFACE
++/* HTC Raw Interface Ioctls */
++#define AR6000_XIOCTL_HTC_RAW_OPEN            13
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_CLOSE           14
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_READ            15
++/*
++ * arguments:
++ *   union {
++ *     struct {
++ *       UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
++ *       UINT32 mailboxID
++ *       UINT32 length
++ *     }
++ *     results[length]
++ *   }
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_WRITE           16
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
++ *   UINT32 mailboxID
++ *   UINT32 length
++ *   char buffer[length]
++ */
++#endif							/* HTC_RAW_INTERFACE */
++
++#define AR6000_XIOCTL_CHECK_TARGET_READY      17
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
++ */
++
++
++
++/*                ====GPIO (General Purpose I/O) Extended Ioctls====          */
++
++#define AR6000_XIOCTL_GPIO_OUTPUT_SET         18
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
++ *   ar6k_gpio_output_set_cmd_s (see below)
++ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INPUT_GET          19
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
++ * uses: WMIX_GPIO_INPUT_GET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_REGISTER_SET       20
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
++ *   ar6k_gpio_register_cmd_s (see below)
++ * uses: WMIX_GPIO_REGISTER_SET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_REGISTER_GET       21
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
++ *   ar6k_gpio_register_cmd_s (see below)
++ * uses: WMIX_GPIO_REGISTER_GET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INTR_ACK           22
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
++ *   ar6k_cpio_intr_ack_cmd_s (see below)
++ * uses: WMIX_GPIO_INTR_ACK_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INTR_WAIT          23
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
++ */
++
++
++
++/*                    ====more wireless commands====                          */
++
++#define AR6000_XIOCTL_SET_ADHOC_BSSID         24
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
++ *   WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
++ */
++
++#define AR6000_XIOCTL_SET_OPT_MODE            25
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
++ *   WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
++ * uses: WMI_SET_OPT_MODE_CMDID
++ */
++
++#define AR6000_XIOCTL_OPT_SEND_FRAME          26
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
++ *   WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
++ * uses: WMI_OPT_TX_FRAME_CMDID
++ */
++
++#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL 27
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL)
++ *   WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
++ * uses: WMI_SET_BEACON_INT_CMDID
++ */
++
++
++#define IEEE80211_IOCTL_SETAUTHALG           28
++
++
++#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE        29
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
++ *   WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
++ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
++ */
++
++
++#define AR6000_XIOCTL_SET_MAX_SP                30
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
++ *   WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
++ * uses: WMI_SET_MAX_SP_LEN_CMDID
++ */
++
++#define AR6000_XIOCTL_WMI_GET_ROAM_TBL             31
++
++#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL            32
++
++#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS    33
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
++ *   WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
++ *   WMI_SET_POWERSAVE_TIMERS_CMDID
++ */
++
++#define AR6000_XIOCTRL_WMI_GET_POWER_MODE          34
++/*
++ * arguments:
++ *   UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
++ */
++
++#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE          35
++	typedef enum {
++		WLAN_DISABLED,
++		WLAN_ENABLED
++	} AR6000_WLAN_STATE;
++/*
++ * arguments:
++ * enable/disable
++ */
++
++#define AR6000_XIOCTL_WMI_GET_ROAM_DATA            36
++
++/* used by AR6000_IOCTL_WMI_GETREV */
++	struct ar6k_version {
++		u32 host_ver;
++		u32 target_ver;
++	};
++
++/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
++	struct ar6k_queuereq {
++		u8 trafficDirection;
++		u8 trafficClass;
++		s8 queueNumber;
++	};
++
++/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
++	typedef struct targetStats_t {
++		u64 tx_packets;
++		u64 tx_bytes;
++		u64 tx_unicast_pkts;
++		u64 tx_unicast_bytes;
++		u64 tx_multicast_pkts;
++		u64 tx_multicast_bytes;
++		u64 tx_broadcast_pkts;
++		u64 tx_broadcast_bytes;
++		u64 tx_rts_success_cnt;
++		u64 tx_packet_per_ac[4];
++
++		u64 tx_errors;
++		u64 tx_failed_cnt;
++		u64 tx_retry_cnt;
++		u64 tx_rts_fail_cnt;
++		u64 rx_packets;
++		u64 rx_bytes;
++		u64 rx_unicast_pkts;
++		u64 rx_unicast_bytes;
++		u64 rx_multicast_pkts;
++		u64 rx_multicast_bytes;
++		u64 rx_broadcast_pkts;
++		u64 rx_broadcast_bytes;
++		u64 rx_fragment_pkt;
++
++		u64 rx_errors;
++		u64 rx_crcerr;
++		u64 rx_key_cache_miss;
++		u64 rx_decrypt_err;
++		u64 rx_duplicate_frames;
++
++		u64 tkip_local_mic_failure;
++		u64 tkip_counter_measures_invoked;
++		u64 tkip_replays;
++		u64 tkip_format_errors;
++		u64 ccmp_format_errors;
++		u64 ccmp_replays;
++
++		u64 power_save_failure_cnt;
++		s16 noise_floor_calibation;
++
++		u64 cs_bmiss_cnt;
++		u64 cs_lowRssi_cnt;
++		u64 cs_connect_cnt;
++		u64 cs_disconnect_cnt;
++		u8 cs_aveBeacon_rssi;
++		u8 cs_lastRoam_msec;
++	} TARGET_STATS;
++
++/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
++	struct ar6k_gpio_output_set_cmd_s {
++		u32 set_mask;
++		u32 clear_mask;
++		u32 enable_mask;
++		u32 disable_mask;
++	};
++
++/*
++ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
++ */
++	struct ar6k_gpio_register_cmd_s {
++		u32 gpioreg_id;
++		u32 value;
++	};
++
++/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
++	struct ar6k_gpio_intr_ack_cmd_s {
++		u32 ack_mask;
++	};
++
++/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
++	struct ar6k_gpio_intr_wait_cmd_s {
++		u32 intr_mask;
++		u32 input_values;
++	};
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _ATHDRV_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/dset_api.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/dset_api.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,47 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * Host-side DataSet API.
++ *
++ */
++
++#ifndef _DSET_API_H_
++#define _DSET_API_H_
++
++/*
++ * Host-side DataSet support is optional, and is not
++ * currently required for correct operation.  To disable
++ * Host-side DataSet support, set this to 0.
++ */
++#define CONFIG_HOST_DSET_SUPPORT 1
++
++/* Called to send a DataSet Open Reply back to the Target. */
++int wmi_dset_open_reply(struct wmi_t *wmip,
++						u32 status,
++						u32 access_cookie,
++						u32 size,
++						u32 version,
++						u32 targ_handle,
++						u32 targ_reply_fn, u32 targ_reply_arg);
++
++/* Called to send a DataSet Data Reply back to the Target. */
++int wmi_dset_data_reply(struct wmi_t *wmip,
++						u32 status,
++						u8 * host_buf,
++						u32 length,
++						u32 targ_buf,
++						u32 targ_reply_fn, u32 targ_reply_arg);
++
++#endif							/* _DSET_API_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/gpio_api.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/gpio_api.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,60 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ */
++
++#ifndef _GPIO_API_H_
++#define _GPIO_API_H_
++
++/*
++ * Host-side GPIO support is optional.
++ * If run-time access to GPIO pins is not required, then
++ * this should be changed to 0.
++ */
++#define CONFIG_HOST_GPIO_SUPPORT 1
++
++/*
++ * Host-side General Purpose I/O API.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/host/include/gpio_api.h#2 $
++ */
++
++/*
++ * Send a command to the Target in order to change output on GPIO pins.
++ */
++int wmi_gpio_output_set(struct wmi_t *wmip,
++						u32 set_mask,
++						u32 clear_mask, u32 enable_mask, u32 disable_mask);
++
++/*
++ * Send a command to the Target requesting input state of GPIO pins.
++ */
++int wmi_gpio_input_get(struct wmi_t *wmip);
++
++/*
++ * Send a command to the Target to change the value of a GPIO register.
++ */
++int wmi_gpio_register_set(struct wmi_t *wmip, u32 gpioreg_id, u32 value);
++
++/*
++ * Send a command to the Target to fetch the value of a GPIO register.
++ */
++int wmi_gpio_register_get(struct wmi_t *wmip, u32 gpioreg_id);
++
++/*
++ * Send a command to the Target, acknowledging some GPIO interrupts.
++ */
++int wmi_gpio_intr_ack(struct wmi_t *wmip, u32 ack_mask);
++
++#endif							/* _GPIO_API_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hif.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hif.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * HIF specific declarations and prototypes
++ */
++
++#ifndef _HIF_H_
++#define _HIF_H_
++
++/* Header files */
++#include "../include/athdefs.h"
++#include "../include/osapi.h"
++
++typedef struct htc_callbacks HTC_CALLBACKS;
++
++#define HIF_MAX_DEVICES                 1
++
++struct htc_callbacks {
++	u8 *name;
++	u32 id;
++	int (*deviceInsertedHandler) (struct sdio_func * func);
++	int (*deviceRemovedHandler) (struct sdio_func * func);
++	int (*deviceSuspendHandler) (struct sdio_func * func);
++	int (*deviceResumeHandler) (struct sdio_func * func);
++	int (*deviceWakeupHandler) (struct sdio_func * func);
++	int (*rwCompletionHandler) (void *context, int status);
++#ifdef CF
++	int (*deviceInterruptDisabler) (struct sdio_func * func, u8 * callDsr);
++	int (*deviceInterruptEnabler) (struct sdio_func * func);
++#endif							/* CF */
++	int (*dsrHandler) (struct sdio_func * func);
++};
++
++/*
++ * This API is used by the HTC layer to register different callback routines
++ * with the HIF layer. Support for following events has been captured - DSR,
++ * Read/Write completion, Device insertion/removal, Device suspension/
++ * resumption/wakeup. In addition to this, the API is also used to register
++ * the name and the revision of the chip. The latter can be used to verify
++ * the revision of the chip read from the device before reporting it to HTC.
++ */
++void HIFRegisterCallbacks(HTC_CALLBACKS * callbacks);
++
++/*
++ * This can be initiated from the unload driver context ie when the HTCShutdown
++ * routine is called.
++ */
++void
++ HIFShutDownDevice(struct sdio_func *func);
++
++/*
++ * This should translate to an acknowledgment to the bus driver indicating that
++ * the previous interrupt request has been serviced and the all the relevant
++ * sources have been cleared. HTC is ready to process more interrupts.
++ * This should prevent the bus driver from raising an interrupt unless the
++ * previous one has been serviced and acknowledged using the previous API.
++ */
++void
++ HIFAckInterrupt(struct sdio_func *func);
++
++void
++ HIFMaskInterrupt(struct sdio_func *func);
++
++int
++ HIFUnMaskInterrupt(struct sdio_func *func);
++
++#endif							/* _HIF_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/host_version.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/host_version.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains version information for the sample host driver for the
++ * AR6000 chip
++ *
++ *
++ */
++
++#ifndef _HOST_VERSION_H_
++#define _HOST_VERSION_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "../include/AR6000_version.h"
++
++/*
++ * The version number is made up of major, minor, patch and build
++ * numbers. These are 16 bit numbers.  The build and release script will
++ * set the build number using a Perforce counter.  Here the build number is
++ * set to 9999 so that builds done without the build-release script are easily
++ * identifiable.
++ */
++
++#define ATH_SW_VER_MAJOR      __VER_MAJOR_
++#define ATH_SW_VER_MINOR      __VER_MINOR_
++#define ATH_SW_VER_PATCH      __VER_PATCH_
++#define ATH_SW_VER_BUILD 2
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _HOST_VERSION_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/htc.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/htc.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,115 @@
++/*
++ * Copyright (c) 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * htc.h  -  HTC Module specific declarations and prototypes
++ */
++
++#ifndef _HTC_H_
++#define _HTC_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif							/* __cplusplus */
++
++/* ------ MBOX ID ------ */
++	typedef enum {
++		ENDPOINT_UNUSED = -1,
++		ENDPOINT1 = 0,
++		ENDPOINT2,
++		ENDPOINT3,
++		ENDPOINT4,
++	} HTC_ENDPOINT_ID;
++
++/* ------ Event Types ------ */
++	typedef enum {
++		HTC_BUFFER_RECEIVED = 0,
++		HTC_SKB_RECEIVED,
++		HTC_BUFFER_SENT,
++		HTC_SKB_SENT,
++		HTC_DATA_AVAILABLE,
++		HTC_TARGET_AVAILABLE,
++		HTC_TARGET_UNAVAILABLE,
++	} HTC_EVENT_ID;
++
++#define HTC_MAILBOX_NUM_MAX                4
++#define HTC_HEADER_LEN                     2
++#define HTC_DATA_REQUEST_RING_BUFFER_SIZE  30
++
++/* ------- Target Specific Data structures ------- */
++	typedef struct htc_target HTC_TARGET;
++
++/* ------- Event Specific Data Structures ------- */
++	typedef struct htc_event_info HTC_EVENT_INFO;
++	typedef void (*HTC_EVENT_HANDLER) (HTC_TARGET *,
++									   HTC_ENDPOINT_ID,
++									   HTC_EVENT_ID,
++									   HTC_EVENT_INFO *, void *);
++
++/* WMI layer extracts the relevant information from this data structure */
++	struct htc_event_info {
++		u8 *buffer;
++		void *cookie;
++		u32 bufferLength;
++		u32 actualLength;
++		int status;
++	};
++
++/* ------ Function Prototypes ------ */
++	int
++	 HTCInit(void);
++
++	int
++	 HTCStart(HTC_TARGET * target);
++/* target - IN */
++
++	int
++	 HTCEventReg(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++				 HTC_EVENT_ID eventId, HTC_EVENT_HANDLER eventHandler,
++				 void *param);
++/* target - IN, endPointId - IN, eventId - IN, eventHandler - IN, param - IN */
++
++	int
++	 HTCBufferReceive(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++					  u8 * buffer, u32 length, void *cookie);
++/* target - IN, endPointId - IN, buffer - IN, length - IN, cookie - IN */
++
++#if 0
++	int
++	 HTCSkbReceive(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++				   struct sk_buff *skb, void *cookie);
++#endif
++
++	int
++	 HTCBufferSend(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++				   u8 * buffer, u32 length, void *cookie);
++/* target - IN, endPointId - IN, buffer - IN, length - IN, cookie - IN */
++
++#if 0
++	int
++	 HTCSkbSend(HTC_TARGET * target, HTC_ENDPOINT_ID endPointId,
++				struct sk_buff *skb, void *cookie);
++#endif
++
++	void
++	 HTCStop(HTC_TARGET * target);
++/* target - IN */
++
++	void
++	 HTCShutDown(HTC_TARGET * target);
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _HTC_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/#mbox_host_reg.h#
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/#mbox_host_reg.h#	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,416 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++
++#ifndef _MBOX_HOST_REG_REG_H_
++#define _MBOX_HOST_REG_REG_H_
++
++#define HOST_INT_STATUS_ADDRESS                  0x00000400
++#define HOST_INT_STATUS_OFFSET                   0x00000400
++#define HOST_INT_STATUS_ERROR_MSB                7
++#define HOST_INT_STATUS_ERROR_LSB                7
++#define HOST_INT_STATUS_ERROR_MASK               0x00000080
++#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
++#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
++#define HOST_INT_STATUS_CPU_MSB                  6
++#define HOST_INT_STATUS_CPU_LSB                  6
++#define HOST_INT_STATUS_CPU_MASK                 0x00000040
++#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
++#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
++#define HOST_INT_STATUS_DRAGON_INT_MSB           5
++#define HOST_INT_STATUS_DRAGON_INT_LSB           5
++#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
++#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
++#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
++#define HOST_INT_STATUS_COUNTER_MSB              4
++#define HOST_INT_STATUS_COUNTER_LSB              4
++#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
++#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
++#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
++#define HOST_INT_STATUS_MBOX_DATA_MSB            3
++#define HOST_INT_STATUS_MBOX_DATA_LSB            0
++#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
++#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
++#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ADDRESS                   0x00000401
++#define CPU_INT_STATUS_OFFSET                    0x00000401
++#define CPU_INT_STATUS_BIT_MSB                   7
++#define CPU_INT_STATUS_BIT_LSB                   0
++#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
++#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
++#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
++
++#define ERROR_INT_STATUS_ADDRESS                 0x00000402
++#define ERROR_INT_STATUS_OFFSET                  0x00000402
++#define ERROR_INT_STATUS_SPI_MSB                 3
++#define ERROR_INT_STATUS_SPI_LSB                 3
++#define ERROR_INT_STATUS_SPI_MASK                0x00000008
++#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
++#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
++#define ERROR_INT_STATUS_WAKEUP_MSB              2
++#define ERROR_INT_STATUS_WAKEUP_LSB              2
++#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
++#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
++#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
++#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
++#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
++#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
++#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
++#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
++#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ADDRESS               0x00000403
++#define COUNTER_INT_STATUS_OFFSET                0x00000403
++#define COUNTER_INT_STATUS_COUNTER_MSB           7
++#define COUNTER_INT_STATUS_COUNTER_LSB           0
++#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
++#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
++#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
++
++#define MBOX_FRAME_ADDRESS                       0x00000404
++#define MBOX_FRAME_OFFSET                        0x00000404
++#define MBOX_FRAME_RX_EOM_MSB                    7
++#define MBOX_FRAME_RX_EOM_LSB                    4
++#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
++#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
++#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
++#define MBOX_FRAME_RX_SOM_MSB                    3
++#define MBOX_FRAME_RX_SOM_LSB                    0
++#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
++#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
++#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
++
++#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
++#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
++#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
++#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
++#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
++#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
++#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
++
++#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
++#define RX_LOOKAHEAD0_OFFSET                     0x00000408
++#define RX_LOOKAHEAD0_DATA_MSB                   7
++#define RX_LOOKAHEAD0_DATA_LSB                   0
++#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
++#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
++
++#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
++#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
++#define RX_LOOKAHEAD1_DATA_MSB                   7
++#define RX_LOOKAHEAD1_DATA_LSB                   0
++#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
++#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
++
++#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
++#define RX_LOOKAHEAD2_OFFSET                     0x00000410
++#define RX_LOOKAHEAD2_DATA_MSB                   7
++#define RX_LOOKAHEAD2_DATA_LSB                   0
++#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
++#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
++
++#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
++#define RX_LOOKAHEAD3_OFFSET                     0x00000414
++#define RX_LOOKAHEAD3_DATA_MSB                   7
++#define RX_LOOKAHEAD3_DATA_LSB                   0
++#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
++#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
++
++#define INT_STATUS_ENABLE_ADDRESS                0x00000418
++#define INT_STATUS_ENABLE_OFFSET                 0x00000418
++#define INT_STATUS_ENABLE_ERROR_MSB              7
++#define INT_STATUS_ENABLE_ERROR_LSB              7
++#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
++#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
++#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
++#define INT_STATUS_ENABLE_CPU_MSB                6
++#define INT_STATUS_ENABLE_CPU_LSB                6
++#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
++#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
++#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
++#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
++#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
++#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
++#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
++#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
++#define INT_STATUS_ENABLE_COUNTER_MSB            4
++#define INT_STATUS_ENABLE_COUNTER_LSB            4
++#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
++#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
++#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
++#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
++#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
++#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
++#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
++#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
++#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
++#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
++#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
++#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
++#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
++#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
++
++#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
++#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
++#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
++#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
++#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
++#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
++#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
++#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
++#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
++#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
++#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
++
++#define COUNT_ADDRESS                            0x00000420
++#define COUNT_OFFSET                             0x00000420
++#define COUNT_VALUE_MSB                          7
++#define COUNT_VALUE_LSB                          0
++#define COUNT_VALUE_MASK                         0x000000ff
++#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
++#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
++
++#define COUNT_DEC_ADDRESS                        0x00000440
++#define COUNT_DEC_OFFSET                         0x00000440
++#define COUNT_DEC_VALUE_MSB                      7
++#define COUNT_DEC_VALUE_LSB                      0
++#define COUNT_DEC_VALUE_MASK                     0x000000ff
++#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
++#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
++
++#define SCRATCH_ADDRESS                          0x00000460
++#define SCRATCH_OFFSET                           0x00000460
++#define SCRATCH_VALUE_MSB                        7
++#define SCRATCH_VALUE_LSB                        0
++#define SCRATCH_VALUE_MASK                       0x000000ff
++#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
++#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ADDRESS                     0x00000468
++#define FIFO_TIMEOUT_OFFSET                      0x00000468
++#define FIFO_TIMEOUT_VALUE_MSB                   7
++#define FIFO_TIMEOUT_VALUE_LSB                   0
++#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
++#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
++#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
++#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
++#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
++#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
++#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
++#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
++#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
++
++#define DISABLE_SLEEP_ADDRESS                    0x0000046a
++#define DISABLE_SLEEP_OFFSET                     0x0000046a
++#define DISABLE_SLEEP_FOR_INT_MSB                1
++#define DISABLE_SLEEP_FOR_INT_LSB                1
++#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
++#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
++#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
++#define DISABLE_SLEEP_ON_MSB                     0
++#define DISABLE_SLEEP_ON_LSB                     0
++#define DISABLE_SLEEP_ON_MASK                    0x00000001
++#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
++#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
++
++#define LOCAL_BUS_ENDIAN_ADDRESS                 0x0000046e
++#define LOCAL_BUS_ENDIAN_OFFSET                  0x0000046e
++#define LOCAL_BUS_ENDIAN_BIG_MSB                 0
++#define LOCAL_BUS_ENDIAN_BIG_LSB                 0
++#define LOCAL_BUS_ENDIAN_BIG_MASK                0x00000001
++#define LOCAL_BUS_ENDIAN_BIG_GET(x)              (((x) & LOCAL_BUS_ENDIAN_BIG_MASK) >> LOCAL_BUS_ENDIAN_BIG_LSB)
++#define LOCAL_BUS_ENDIAN_BIG_SET(x)              (((x) << LOCAL_BUS_ENDIAN_BIG_LSB) & LOCAL_BUS_ENDIAN_BIG_MASK)
++
++#define LOCAL_BUS_ADDRESS                        0x00000470
++#define LOCAL_BUS_OFFSET                         0x00000470
++#define LOCAL_BUS_SOFT_RESET_MSB                 4
++#define LOCAL_BUS_SOFT_RESET_LSB                 4
++#define LOCAL_BUS_SOFT_RESET_MASK                0x00000010
++#define LOCAL_BUS_SOFT_RESET_GET(x)              (((x) & LOCAL_BUS_SOFT_RESET_MASK) >> LOCAL_BUS_SOFT_RESET_LSB)
++#define LOCAL_BUS_SOFT_RESET_SET(x)              (((x) << LOCAL_BUS_SOFT_RESET_LSB) & LOCAL_BUS_SOFT_RESET_MASK)
++#define LOCAL_BUS_IO_ENABLE_MSB                  3
++#define LOCAL_BUS_IO_ENABLE_LSB                  3
++#define LOCAL_BUS_IO_ENABLE_MASK                 0x00000008
++#define LOCAL_BUS_IO_ENABLE_GET(x)               (((x) & LOCAL_BUS_IO_ENABLE_MASK) >> LOCAL_BUS_IO_ENABLE_LSB)
++#define LOCAL_BUS_IO_ENABLE_SET(x)               (((x) << LOCAL_BUS_IO_ENABLE_LSB) & LOCAL_BUS_IO_ENABLE_MASK)
++#define LOCAL_BUS_KEEP_AWAKE_MSB                 2
++#define LOCAL_BUS_KEEP_AWAKE_LSB                 2
++#define LOCAL_BUS_KEEP_AWAKE_MASK                0x00000004
++#define LOCAL_BUS_KEEP_AWAKE_GET(x)              (((x) & LOCAL_BUS_KEEP_AWAKE_MASK) >> LOCAL_BUS_KEEP_AWAKE_LSB)
++#define LOCAL_BUS_KEEP_AWAKE_SET(x)              (((x) << LOCAL_BUS_KEEP_AWAKE_LSB) & LOCAL_BUS_KEEP_AWAKE_MASK)
++#define LOCAL_BUS_STATE_MSB                      1
++#define LOCAL_BUS_STATE_LSB                      0
++#define LOCAL_BUS_STATE_MASK                     0x00000003
++#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
++#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
++
++#define INT_WLAN_ADDRESS                         0x00000472
++#define INT_WLAN_OFFSET                          0x00000472
++#define INT_WLAN_VECTOR_MSB                      7
++#define INT_WLAN_VECTOR_LSB                      0
++#define INT_WLAN_VECTOR_MASK                     0x000000ff
++#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
++#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
++
++#define WINDOW_DATA_ADDRESS                      0x00000474
++#define WINDOW_DATA_OFFSET                       0x00000474
++#define WINDOW_DATA_DATA_MSB                     7
++#define WINDOW_DATA_DATA_LSB                     0
++#define WINDOW_DATA_DATA_MASK                    0x000000ff
++#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
++#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
++
++#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
++#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
++#define WINDOW_WRITE_ADDR_ADDR_MSB               7
++#define WINDOW_WRITE_ADDR_ADDR_LSB               0
++#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
++#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
++#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
++
++#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
++#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
++#define WINDOW_READ_ADDR_ADDR_MSB                7
++#define WINDOW_READ_ADDR_ADDR_LSB                0
++#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
++#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
++#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
++
++#define SPI_CONFIG_ADDRESS                       0x00000480
++#define SPI_CONFIG_OFFSET                        0x00000480
++#define SPI_CONFIG_SPI_RESET_MSB                 4
++#define SPI_CONFIG_SPI_RESET_LSB                 4
++#define SPI_CONFIG_SPI_RESET_MASK                0x00000010
++#define SPI_CONFIG_SPI_RESET_GET(x)              (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
++#define SPI_CONFIG_SPI_RESET_SET(x)              (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
++#define SPI_CONFIG_INTERRUPT_ENABLE_MSB          3
++#define SPI_CONFIG_INTERRUPT_ENABLE_LSB          3
++#define SPI_CONFIG_INTERRUPT_ENABLE_MASK         0x00000008
++#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x)       (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
++#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x)       (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
++#define SPI_CONFIG_TEST_MODE_MSB                 2
++#define SPI_CONFIG_TEST_MODE_LSB                 2
++#define SPI_CONFIG_TEST_MODE_MASK                0x00000004
++#define SPI_CONFIG_TEST_MODE_GET(x)              (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
++#define SPI_CONFIG_TEST_MODE_SET(x)              (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
++#define SPI_CONFIG_DATA_SIZE_MSB                 1
++#define SPI_CONFIG_DATA_SIZE_LSB                 0
++#define SPI_CONFIG_DATA_SIZE_MASK                0x00000003
++#define SPI_CONFIG_DATA_SIZE_GET(x)              (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
++#define SPI_CONFIG_DATA_SIZE_SET(x)              (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
++
++#define SPI_STATUS_ADDRESS                       0x00000481
++#define SPI_STATUS_OFFSET                        0x00000481
++#define SPI_STATUS_ADDR_ERR_MSB                  3
++#define SPI_STATUS_ADDR_ERR_LSB                  3
++#define SPI_STATUS_ADDR_ERR_MASK                 0x00000008
++#define SPI_STATUS_ADDR_ERR_GET(x)               (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
++#define SPI_STATUS_ADDR_ERR_SET(x)               (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
++#define SPI_STATUS_RD_ERR_MSB                    2
++#define SPI_STATUS_RD_ERR_LSB                    2
++#define SPI_STATUS_RD_ERR_MASK                   0x00000004
++#define SPI_STATUS_RD_ERR_GET(x)                 (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
++#define SPI_STATUS_RD_ERR_SET(x)                 (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
++#define SPI_STATUS_WR_ERR_MSB                    1
++#define SPI_STATUS_WR_ERR_LSB                    1
++#define SPI_STATUS_WR_ERR_MASK                   0x00000002
++#define SPI_STATUS_WR_ERR_GET(x)                 (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
++#define SPI_STATUS_WR_ERR_SET(x)                 (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
++#define SPI_STATUS_READY_MSB                     0
++#define SPI_STATUS_READY_LSB                     0
++#define SPI_STATUS_READY_MASK                    0x00000001
++#define SPI_STATUS_READY_GET(x)                  (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
++#define SPI_STATUS_READY_SET(x)                  (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
++
++#define CIS_WINDOW_ADDRESS                       0x00000600
++#define CIS_WINDOW_OFFSET                        0x00000600
++#define CIS_WINDOW_DATA_MSB                      7
++#define CIS_WINDOW_DATA_LSB                      0
++#define CIS_WINDOW_DATA_MASK                     0x000000ff
++#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
++#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mbox_host_reg_reg_s {
++  unsigned char pad0[1024]; /* pad to 0x400 */
++  volatile unsigned char host_int_status;
++  volatile unsigned char cpu_int_status;
++  volatile unsigned char error_int_status;
++  volatile unsigned char counter_int_status;
++  volatile unsigned char mbox_frame;
++  volatile unsigned char rx_lookahead_valid;
++  unsigned char pad1[2]; /* pad to 0x408 */
++  volatile unsigned char rx_lookahead0[4];
++  volatile unsigned char rx_lookahead1[4];
++  volatile unsigned char rx_lookahead2[4];
++  volatile unsigned char rx_lookahead3[4];
++  volatile unsigned char int_status_enable;
++  volatile unsigned char cpu_int_status_enable;
++  volatile unsigned char error_status_enable;
++  volatile unsigned char counter_int_status_enable;
++  unsigned char pad2[4]; /* pad to 0x420 */
++  volatile unsigned char count[8];
++  unsigned char pad3[24]; /* pad to 0x440 */
++  volatile unsigned char count_dec[32];
++  volatile unsigned char scratch[8];
++  volatile unsigned char fifo_timeout;
++  volatile unsigned char fifo_timeout_enable;
++  volatile unsigned char disable_sleep;
++  unsigned char pad4[3]; /* pad to 0x46e */
++  volatile unsigned char local_bus_endian;
++  unsigned char pad5[1]; /* pad to 0x470 */
++  volatile unsigned char local_bus;
++  unsigned char pad6[1]; /* pad to 0x472 */
++  volatile unsigned char int_wlan;
++  unsigned char pad7[1]; /* pad to 0x474 */
++  volatile unsigned char window_data[4];
++  volatile unsigned char window_write_addr[4];
++  volatile unsigned char window_read_addr[4];
++  volatile unsigned char spi_config;
++  volatile unsigned char spi_status;
++  unsigned char pad8[382]; /* pad to 0x600 */
++  volatile unsigned char cis_window[512];
++} mbox_host_reg_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MBOX_HOST_REG_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mbox_host_reg.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mbox_host_reg.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,416 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++
++#ifndef _MBOX_HOST_REG_REG_H_
++#define _MBOX_HOST_REG_REG_H_
++
++#define HOST_INT_STATUS_ADDRESS                  0x00000400
++#define HOST_INT_STATUS_OFFSET                   0x00000400
++#define HOST_INT_STATUS_ERROR_MSB                7
++#define HOST_INT_STATUS_ERROR_LSB                7
++#define HOST_INT_STATUS_ERROR_MASK               0x00000080
++#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
++#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
++#define HOST_INT_STATUS_CPU_MSB                  6
++#define HOST_INT_STATUS_CPU_LSB                  6
++#define HOST_INT_STATUS_CPU_MASK                 0x00000040
++#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
++#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
++#define HOST_INT_STATUS_DRAGON_INT_MSB           5
++#define HOST_INT_STATUS_DRAGON_INT_LSB           5
++#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
++#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
++#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
++#define HOST_INT_STATUS_COUNTER_MSB              4
++#define HOST_INT_STATUS_COUNTER_LSB              4
++#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
++#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
++#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
++#define HOST_INT_STATUS_MBOX_DATA_MSB            3
++#define HOST_INT_STATUS_MBOX_DATA_LSB            0
++#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
++#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
++#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ADDRESS                   0x00000401
++#define CPU_INT_STATUS_OFFSET                    0x00000401
++#define CPU_INT_STATUS_BIT_MSB                   7
++#define CPU_INT_STATUS_BIT_LSB                   0
++#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
++#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
++#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
++
++#define ERROR_INT_STATUS_ADDRESS                 0x00000402
++#define ERROR_INT_STATUS_OFFSET                  0x00000402
++#define ERROR_INT_STATUS_SPI_MSB                 3
++#define ERROR_INT_STATUS_SPI_LSB                 3
++#define ERROR_INT_STATUS_SPI_MASK                0x00000008
++#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
++#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
++#define ERROR_INT_STATUS_WAKEUP_MSB              2
++#define ERROR_INT_STATUS_WAKEUP_LSB              2
++#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
++#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
++#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
++#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
++#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
++#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
++#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
++#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
++#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ADDRESS               0x00000403
++#define COUNTER_INT_STATUS_OFFSET                0x00000403
++#define COUNTER_INT_STATUS_COUNTER_MSB           7
++#define COUNTER_INT_STATUS_COUNTER_LSB           0
++#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
++#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
++#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
++
++#define MBOX_FRAME_ADDRESS                       0x00000404
++#define MBOX_FRAME_OFFSET                        0x00000404
++#define MBOX_FRAME_RX_EOM_MSB                    7
++#define MBOX_FRAME_RX_EOM_LSB                    4
++#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
++#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
++#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
++#define MBOX_FRAME_RX_SOM_MSB                    3
++#define MBOX_FRAME_RX_SOM_LSB                    0
++#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
++#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
++#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
++
++#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
++#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
++#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
++#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
++#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
++#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
++#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
++
++#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
++#define RX_LOOKAHEAD0_OFFSET                     0x00000408
++#define RX_LOOKAHEAD0_DATA_MSB                   7
++#define RX_LOOKAHEAD0_DATA_LSB                   0
++#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
++#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
++
++#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
++#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
++#define RX_LOOKAHEAD1_DATA_MSB                   7
++#define RX_LOOKAHEAD1_DATA_LSB                   0
++#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
++#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
++
++#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
++#define RX_LOOKAHEAD2_OFFSET                     0x00000410
++#define RX_LOOKAHEAD2_DATA_MSB                   7
++#define RX_LOOKAHEAD2_DATA_LSB                   0
++#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
++#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
++
++#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
++#define RX_LOOKAHEAD3_OFFSET                     0x00000414
++#define RX_LOOKAHEAD3_DATA_MSB                   7
++#define RX_LOOKAHEAD3_DATA_LSB                   0
++#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
++#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
++#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
++
++#define INT_STATUS_ENABLE_ADDRESS                0x00000418
++#define INT_STATUS_ENABLE_OFFSET                 0x00000418
++#define INT_STATUS_ENABLE_ERROR_MSB              7
++#define INT_STATUS_ENABLE_ERROR_LSB              7
++#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
++#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
++#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
++#define INT_STATUS_ENABLE_CPU_MSB                6
++#define INT_STATUS_ENABLE_CPU_LSB                6
++#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
++#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
++#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
++#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
++#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
++#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
++#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
++#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
++#define INT_STATUS_ENABLE_COUNTER_MSB            4
++#define INT_STATUS_ENABLE_COUNTER_LSB            4
++#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
++#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
++#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
++#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
++#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
++#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
++#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
++#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
++#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
++#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
++#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
++#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
++#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
++#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
++
++#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
++#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
++#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
++#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
++#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
++#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
++#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
++#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
++#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
++#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
++#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
++
++#define COUNT_ADDRESS                            0x00000420
++#define COUNT_OFFSET                             0x00000420
++#define COUNT_VALUE_MSB                          7
++#define COUNT_VALUE_LSB                          0
++#define COUNT_VALUE_MASK                         0x000000ff
++#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
++#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
++
++#define COUNT_DEC_ADDRESS                        0x00000440
++#define COUNT_DEC_OFFSET                         0x00000440
++#define COUNT_DEC_VALUE_MSB                      7
++#define COUNT_DEC_VALUE_LSB                      0
++#define COUNT_DEC_VALUE_MASK                     0x000000ff
++#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
++#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
++
++#define SCRATCH_ADDRESS                          0x00000460
++#define SCRATCH_OFFSET                           0x00000460
++#define SCRATCH_VALUE_MSB                        7
++#define SCRATCH_VALUE_LSB                        0
++#define SCRATCH_VALUE_MASK                       0x000000ff
++#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
++#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ADDRESS                     0x00000468
++#define FIFO_TIMEOUT_OFFSET                      0x00000468
++#define FIFO_TIMEOUT_VALUE_MSB                   7
++#define FIFO_TIMEOUT_VALUE_LSB                   0
++#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
++#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
++#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
++#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
++#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
++#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
++#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
++#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
++#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
++
++#define DISABLE_SLEEP_ADDRESS                    0x0000046a
++#define DISABLE_SLEEP_OFFSET                     0x0000046a
++#define DISABLE_SLEEP_FOR_INT_MSB                1
++#define DISABLE_SLEEP_FOR_INT_LSB                1
++#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
++#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
++#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
++#define DISABLE_SLEEP_ON_MSB                     0
++#define DISABLE_SLEEP_ON_LSB                     0
++#define DISABLE_SLEEP_ON_MASK                    0x00000001
++#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
++#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
++
++#define LOCAL_BUS_ENDIAN_ADDRESS                 0x0000046e
++#define LOCAL_BUS_ENDIAN_OFFSET                  0x0000046e
++#define LOCAL_BUS_ENDIAN_BIG_MSB                 0
++#define LOCAL_BUS_ENDIAN_BIG_LSB                 0
++#define LOCAL_BUS_ENDIAN_BIG_MASK                0x00000001
++#define LOCAL_BUS_ENDIAN_BIG_GET(x)              (((x) & LOCAL_BUS_ENDIAN_BIG_MASK) >> LOCAL_BUS_ENDIAN_BIG_LSB)
++#define LOCAL_BUS_ENDIAN_BIG_SET(x)              (((x) << LOCAL_BUS_ENDIAN_BIG_LSB) & LOCAL_BUS_ENDIAN_BIG_MASK)
++
++#define LOCAL_BUS_ADDRESS                        0x00000470
++#define LOCAL_BUS_OFFSET                         0x00000470
++#define LOCAL_BUS_SOFT_RESET_MSB                 4
++#define LOCAL_BUS_SOFT_RESET_LSB                 4
++#define LOCAL_BUS_SOFT_RESET_MASK                0x00000010
++#define LOCAL_BUS_SOFT_RESET_GET(x)              (((x) & LOCAL_BUS_SOFT_RESET_MASK) >> LOCAL_BUS_SOFT_RESET_LSB)
++#define LOCAL_BUS_SOFT_RESET_SET(x)              (((x) << LOCAL_BUS_SOFT_RESET_LSB) & LOCAL_BUS_SOFT_RESET_MASK)
++#define LOCAL_BUS_IO_ENABLE_MSB                  3
++#define LOCAL_BUS_IO_ENABLE_LSB                  3
++#define LOCAL_BUS_IO_ENABLE_MASK                 0x00000008
++#define LOCAL_BUS_IO_ENABLE_GET(x)               (((x) & LOCAL_BUS_IO_ENABLE_MASK) >> LOCAL_BUS_IO_ENABLE_LSB)
++#define LOCAL_BUS_IO_ENABLE_SET(x)               (((x) << LOCAL_BUS_IO_ENABLE_LSB) & LOCAL_BUS_IO_ENABLE_MASK)
++#define LOCAL_BUS_KEEP_AWAKE_MSB                 2
++#define LOCAL_BUS_KEEP_AWAKE_LSB                 2
++#define LOCAL_BUS_KEEP_AWAKE_MASK                0x00000004
++#define LOCAL_BUS_KEEP_AWAKE_GET(x)              (((x) & LOCAL_BUS_KEEP_AWAKE_MASK) >> LOCAL_BUS_KEEP_AWAKE_LSB)
++#define LOCAL_BUS_KEEP_AWAKE_SET(x)              (((x) << LOCAL_BUS_KEEP_AWAKE_LSB) & LOCAL_BUS_KEEP_AWAKE_MASK)
++#define LOCAL_BUS_STATE_MSB                      1
++#define LOCAL_BUS_STATE_LSB                      0
++#define LOCAL_BUS_STATE_MASK                     0x00000003
++#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
++#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
++
++#define INT_WLAN_ADDRESS                         0x00000472
++#define INT_WLAN_OFFSET                          0x00000472
++#define INT_WLAN_VECTOR_MSB                      7
++#define INT_WLAN_VECTOR_LSB                      0
++#define INT_WLAN_VECTOR_MASK                     0x000000ff
++#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
++#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
++
++#define WINDOW_DATA_ADDRESS                      0x00000474
++#define WINDOW_DATA_OFFSET                       0x00000474
++#define WINDOW_DATA_DATA_MSB                     7
++#define WINDOW_DATA_DATA_LSB                     0
++#define WINDOW_DATA_DATA_MASK                    0x000000ff
++#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
++#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
++
++#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
++#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
++#define WINDOW_WRITE_ADDR_ADDR_MSB               7
++#define WINDOW_WRITE_ADDR_ADDR_LSB               0
++#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
++#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
++#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
++
++#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
++#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
++#define WINDOW_READ_ADDR_ADDR_MSB                7
++#define WINDOW_READ_ADDR_ADDR_LSB                0
++#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
++#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
++#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
++
++#define SPI_CONFIG_ADDRESS                       0x00000480
++#define SPI_CONFIG_OFFSET                        0x00000480
++#define SPI_CONFIG_SPI_RESET_MSB                 4
++#define SPI_CONFIG_SPI_RESET_LSB                 4
++#define SPI_CONFIG_SPI_RESET_MASK                0x00000010
++#define SPI_CONFIG_SPI_RESET_GET(x)              (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
++#define SPI_CONFIG_SPI_RESET_SET(x)              (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
++#define SPI_CONFIG_INTERRUPT_ENABLE_MSB          3
++#define SPI_CONFIG_INTERRUPT_ENABLE_LSB          3
++#define SPI_CONFIG_INTERRUPT_ENABLE_MASK         0x00000008
++#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x)       (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
++#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x)       (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
++#define SPI_CONFIG_TEST_MODE_MSB                 2
++#define SPI_CONFIG_TEST_MODE_LSB                 2
++#define SPI_CONFIG_TEST_MODE_MASK                0x00000004
++#define SPI_CONFIG_TEST_MODE_GET(x)              (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
++#define SPI_CONFIG_TEST_MODE_SET(x)              (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
++#define SPI_CONFIG_DATA_SIZE_MSB                 1
++#define SPI_CONFIG_DATA_SIZE_LSB                 0
++#define SPI_CONFIG_DATA_SIZE_MASK                0x00000003
++#define SPI_CONFIG_DATA_SIZE_GET(x)              (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
++#define SPI_CONFIG_DATA_SIZE_SET(x)              (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
++
++#define SPI_STATUS_ADDRESS                       0x00000481
++#define SPI_STATUS_OFFSET                        0x00000481
++#define SPI_STATUS_ADDR_ERR_MSB                  3
++#define SPI_STATUS_ADDR_ERR_LSB                  3
++#define SPI_STATUS_ADDR_ERR_MASK                 0x00000008
++#define SPI_STATUS_ADDR_ERR_GET(x)               (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
++#define SPI_STATUS_ADDR_ERR_SET(x)               (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
++#define SPI_STATUS_RD_ERR_MSB                    2
++#define SPI_STATUS_RD_ERR_LSB                    2
++#define SPI_STATUS_RD_ERR_MASK                   0x00000004
++#define SPI_STATUS_RD_ERR_GET(x)                 (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
++#define SPI_STATUS_RD_ERR_SET(x)                 (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
++#define SPI_STATUS_WR_ERR_MSB                    1
++#define SPI_STATUS_WR_ERR_LSB                    1
++#define SPI_STATUS_WR_ERR_MASK                   0x00000002
++#define SPI_STATUS_WR_ERR_GET(x)                 (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
++#define SPI_STATUS_WR_ERR_SET(x)                 (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
++#define SPI_STATUS_READY_MSB                     0
++#define SPI_STATUS_READY_LSB                     0
++#define SPI_STATUS_READY_MASK                    0x00000001
++#define SPI_STATUS_READY_GET(x)                  (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
++#define SPI_STATUS_READY_SET(x)                  (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
++
++#define CIS_WINDOW_ADDRESS                       0x00000600
++#define CIS_WINDOW_OFFSET                        0x00000600
++#define CIS_WINDOW_DATA_MSB                      7
++#define CIS_WINDOW_DATA_LSB                      0
++#define CIS_WINDOW_DATA_MASK                     0x000000ff
++#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
++#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mbox_host_reg_reg_s {
++  unsigned char pad0[1024]; /* pad to 0x400 */
++  volatile unsigned char host_int_status;
++  volatile unsigned char cpu_int_status;
++  volatile unsigned char error_int_status;
++  volatile unsigned char counter_int_status;
++  volatile unsigned char mbox_frame;
++  volatile unsigned char rx_lookahead_valid;
++  unsigned char pad1[2]; /* pad to 0x408 */
++  volatile unsigned char rx_lookahead0[4];
++  volatile unsigned char rx_lookahead1[4];
++  volatile unsigned char rx_lookahead2[4];
++  volatile unsigned char rx_lookahead3[4];
++  volatile unsigned char int_status_enable;
++  volatile unsigned char cpu_int_status_enable;
++  volatile unsigned char error_status_enable;
++  volatile unsigned char counter_int_status_enable;
++  unsigned char pad2[4]; /* pad to 0x420 */
++  volatile unsigned char count[8];
++  unsigned char pad3[24]; /* pad to 0x440 */
++  volatile unsigned char count_dec[32];
++  volatile unsigned char scratch[8];
++  volatile unsigned char fifo_timeout;
++  volatile unsigned char fifo_timeout_enable;
++  volatile unsigned char disable_sleep;
++  unsigned char pad4[3]; /* pad to 0x46e */
++  volatile unsigned char local_bus_endian;
++  unsigned char pad5[1]; /* pad to 0x470 */
++  volatile unsigned char local_bus;
++  unsigned char pad6[1]; /* pad to 0x472 */
++  volatile unsigned char int_wlan;
++  unsigned char pad7[1]; /* pad to 0x474 */
++  volatile unsigned char window_data[4];
++  volatile unsigned char window_write_addr[4];
++  volatile unsigned char window_read_addr[4];
++  volatile unsigned char spi_config;
++  volatile unsigned char spi_status;
++  unsigned char pad8[382]; /* pad to 0x600 */
++  volatile unsigned char cis_window[512];
++} mbox_host_reg_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MBOX_HOST_REG_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mbox_reg.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mbox_reg.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,550 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _MBOX_REG_H_
++#define _MBOX_REG_H_
++
++#define MBOX_FIFO_ADDRESS                        0x0c014000
++#define MBOX_FIFO_OFFSET                         0x00000000
++#define MBOX_FIFO_DATA_MSB                       19
++#define MBOX_FIFO_DATA_LSB                       0
++#define MBOX_FIFO_DATA_MASK                      0x000fffff
++#define MBOX_FIFO_DATA_GET(x)                    (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
++#define MBOX_FIFO_DATA_SET(x)                    (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
++
++#define MBOX_FIFO_STATUS_ADDRESS                 0x0c014010
++#define MBOX_FIFO_STATUS_OFFSET                  0x00000010
++#define MBOX_FIFO_STATUS_EMPTY_MSB               19
++#define MBOX_FIFO_STATUS_EMPTY_LSB               16
++#define MBOX_FIFO_STATUS_EMPTY_MASK              0x000f0000
++#define MBOX_FIFO_STATUS_EMPTY_GET(x)            (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
++#define MBOX_FIFO_STATUS_EMPTY_SET(x)            (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
++#define MBOX_FIFO_STATUS_FULL_MSB                15
++#define MBOX_FIFO_STATUS_FULL_LSB                12
++#define MBOX_FIFO_STATUS_FULL_MASK               0x0000f000
++#define MBOX_FIFO_STATUS_FULL_GET(x)             (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
++#define MBOX_FIFO_STATUS_FULL_SET(x)             (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
++
++#define MBOX_DMA_POLICY_ADDRESS                  0x0c014014
++#define MBOX_DMA_POLICY_OFFSET                   0x00000014
++#define MBOX_DMA_POLICY_TX_QUANTUM_MSB           3
++#define MBOX_DMA_POLICY_TX_QUANTUM_LSB           3
++#define MBOX_DMA_POLICY_TX_QUANTUM_MASK          0x00000008
++#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
++#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
++#define MBOX_DMA_POLICY_TX_ORDER_MSB             2
++#define MBOX_DMA_POLICY_TX_ORDER_LSB             2
++#define MBOX_DMA_POLICY_TX_ORDER_MASK            0x00000004
++#define MBOX_DMA_POLICY_TX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
++#define MBOX_DMA_POLICY_TX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
++#define MBOX_DMA_POLICY_RX_QUANTUM_MSB           1
++#define MBOX_DMA_POLICY_RX_QUANTUM_LSB           1
++#define MBOX_DMA_POLICY_RX_QUANTUM_MASK          0x00000002
++#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
++#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
++#define MBOX_DMA_POLICY_RX_ORDER_MSB             0
++#define MBOX_DMA_POLICY_RX_ORDER_LSB             0
++#define MBOX_DMA_POLICY_RX_ORDER_MASK            0x00000001
++#define MBOX_DMA_POLICY_RX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
++#define MBOX_DMA_POLICY_RX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
++
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014018
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000018
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX0_DMA_RX_CONTROL_ADDRESS             0x0c01401c
++#define MBOX0_DMA_RX_CONTROL_OFFSET              0x0000001c
++#define MBOX0_DMA_RX_CONTROL_RESUME_MSB          2
++#define MBOX0_DMA_RX_CONTROL_RESUME_LSB          2
++#define MBOX0_DMA_RX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX0_DMA_RX_CONTROL_START_MSB           1
++#define MBOX0_DMA_RX_CONTROL_START_LSB           1
++#define MBOX0_DMA_RX_CONTROL_START_MASK          0x00000002
++#define MBOX0_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
++#define MBOX0_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
++#define MBOX0_DMA_RX_CONTROL_STOP_MSB            0
++#define MBOX0_DMA_RX_CONTROL_STOP_LSB            0
++#define MBOX0_DMA_RX_CONTROL_STOP_MASK           0x00000001
++#define MBOX0_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX0_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014020
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000020
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX0_DMA_TX_CONTROL_ADDRESS             0x0c014024
++#define MBOX0_DMA_TX_CONTROL_OFFSET              0x00000024
++#define MBOX0_DMA_TX_CONTROL_RESUME_MSB          2
++#define MBOX0_DMA_TX_CONTROL_RESUME_LSB          2
++#define MBOX0_DMA_TX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX0_DMA_TX_CONTROL_START_MSB           1
++#define MBOX0_DMA_TX_CONTROL_START_LSB           1
++#define MBOX0_DMA_TX_CONTROL_START_MASK          0x00000002
++#define MBOX0_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
++#define MBOX0_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
++#define MBOX0_DMA_TX_CONTROL_STOP_MSB            0
++#define MBOX0_DMA_TX_CONTROL_STOP_LSB            0
++#define MBOX0_DMA_TX_CONTROL_STOP_MASK           0x00000001
++#define MBOX0_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX0_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014028
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000028
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX1_DMA_RX_CONTROL_ADDRESS             0x0c01402c
++#define MBOX1_DMA_RX_CONTROL_OFFSET              0x0000002c
++#define MBOX1_DMA_RX_CONTROL_RESUME_MSB          2
++#define MBOX1_DMA_RX_CONTROL_RESUME_LSB          2
++#define MBOX1_DMA_RX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX1_DMA_RX_CONTROL_START_MSB           1
++#define MBOX1_DMA_RX_CONTROL_START_LSB           1
++#define MBOX1_DMA_RX_CONTROL_START_MASK          0x00000002
++#define MBOX1_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
++#define MBOX1_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
++#define MBOX1_DMA_RX_CONTROL_STOP_MSB            0
++#define MBOX1_DMA_RX_CONTROL_STOP_LSB            0
++#define MBOX1_DMA_RX_CONTROL_STOP_MASK           0x00000001
++#define MBOX1_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX1_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014030
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000030
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX1_DMA_TX_CONTROL_ADDRESS             0x0c014034
++#define MBOX1_DMA_TX_CONTROL_OFFSET              0x00000034
++#define MBOX1_DMA_TX_CONTROL_RESUME_MSB          2
++#define MBOX1_DMA_TX_CONTROL_RESUME_LSB          2
++#define MBOX1_DMA_TX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX1_DMA_TX_CONTROL_START_MSB           1
++#define MBOX1_DMA_TX_CONTROL_START_LSB           1
++#define MBOX1_DMA_TX_CONTROL_START_MASK          0x00000002
++#define MBOX1_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
++#define MBOX1_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
++#define MBOX1_DMA_TX_CONTROL_STOP_MSB            0
++#define MBOX1_DMA_TX_CONTROL_STOP_LSB            0
++#define MBOX1_DMA_TX_CONTROL_STOP_MASK           0x00000001
++#define MBOX1_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX1_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014038
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000038
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX2_DMA_RX_CONTROL_ADDRESS             0x0c01403c
++#define MBOX2_DMA_RX_CONTROL_OFFSET              0x0000003c
++#define MBOX2_DMA_RX_CONTROL_RESUME_MSB          2
++#define MBOX2_DMA_RX_CONTROL_RESUME_LSB          2
++#define MBOX2_DMA_RX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX2_DMA_RX_CONTROL_START_MSB           1
++#define MBOX2_DMA_RX_CONTROL_START_LSB           1
++#define MBOX2_DMA_RX_CONTROL_START_MASK          0x00000002
++#define MBOX2_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
++#define MBOX2_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
++#define MBOX2_DMA_RX_CONTROL_STOP_MSB            0
++#define MBOX2_DMA_RX_CONTROL_STOP_LSB            0
++#define MBOX2_DMA_RX_CONTROL_STOP_MASK           0x00000001
++#define MBOX2_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX2_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014040
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000040
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX2_DMA_TX_CONTROL_ADDRESS             0x0c014044
++#define MBOX2_DMA_TX_CONTROL_OFFSET              0x00000044
++#define MBOX2_DMA_TX_CONTROL_RESUME_MSB          2
++#define MBOX2_DMA_TX_CONTROL_RESUME_LSB          2
++#define MBOX2_DMA_TX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX2_DMA_TX_CONTROL_START_MSB           1
++#define MBOX2_DMA_TX_CONTROL_START_LSB           1
++#define MBOX2_DMA_TX_CONTROL_START_MASK          0x00000002
++#define MBOX2_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
++#define MBOX2_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
++#define MBOX2_DMA_TX_CONTROL_STOP_MSB            0
++#define MBOX2_DMA_TX_CONTROL_STOP_LSB            0
++#define MBOX2_DMA_TX_CONTROL_STOP_MASK           0x00000001
++#define MBOX2_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX2_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014048
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000048
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX3_DMA_RX_CONTROL_ADDRESS             0x0c01404c
++#define MBOX3_DMA_RX_CONTROL_OFFSET              0x0000004c
++#define MBOX3_DMA_RX_CONTROL_RESUME_MSB          2
++#define MBOX3_DMA_RX_CONTROL_RESUME_LSB          2
++#define MBOX3_DMA_RX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX3_DMA_RX_CONTROL_START_MSB           1
++#define MBOX3_DMA_RX_CONTROL_START_LSB           1
++#define MBOX3_DMA_RX_CONTROL_START_MASK          0x00000002
++#define MBOX3_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
++#define MBOX3_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
++#define MBOX3_DMA_RX_CONTROL_STOP_MSB            0
++#define MBOX3_DMA_RX_CONTROL_STOP_LSB            0
++#define MBOX3_DMA_RX_CONTROL_STOP_MASK           0x00000001
++#define MBOX3_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX3_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014050
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000050
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX3_DMA_TX_CONTROL_ADDRESS             0x0c014054
++#define MBOX3_DMA_TX_CONTROL_OFFSET              0x00000054
++#define MBOX3_DMA_TX_CONTROL_RESUME_MSB          2
++#define MBOX3_DMA_TX_CONTROL_RESUME_LSB          2
++#define MBOX3_DMA_TX_CONTROL_RESUME_MASK         0x00000004
++#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX3_DMA_TX_CONTROL_START_MSB           1
++#define MBOX3_DMA_TX_CONTROL_START_LSB           1
++#define MBOX3_DMA_TX_CONTROL_START_MASK          0x00000002
++#define MBOX3_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
++#define MBOX3_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
++#define MBOX3_DMA_TX_CONTROL_STOP_MSB            0
++#define MBOX3_DMA_TX_CONTROL_STOP_LSB            0
++#define MBOX3_DMA_TX_CONTROL_STOP_MASK           0x00000001
++#define MBOX3_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX3_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX_INT_STATUS_ADDRESS                  0x0c014058
++#define MBOX_INT_STATUS_OFFSET                   0x00000058
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB      31
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB      28
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK     0xf0000000
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB  27
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB  24
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB      23
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB      20
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK     0x00f00000
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_OVERFLOW_MSB          17
++#define MBOX_INT_STATUS_TX_OVERFLOW_LSB          17
++#define MBOX_INT_STATUS_TX_OVERFLOW_MASK         0x00020000
++#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
++#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
++#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB         16
++#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB         16
++#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK        0x00010000
++#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
++#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB         15
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB         12
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK        0x0000f000
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
++#define MBOX_INT_STATUS_RX_NOT_FULL_MSB          11
++#define MBOX_INT_STATUS_RX_NOT_FULL_LSB          8
++#define MBOX_INT_STATUS_RX_NOT_FULL_MASK         0x00000f00
++#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
++#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
++#define MBOX_INT_STATUS_HOST_MSB                 7
++#define MBOX_INT_STATUS_HOST_LSB                 0
++#define MBOX_INT_STATUS_HOST_MASK                0x000000ff
++#define MBOX_INT_STATUS_HOST_GET(x)              (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
++#define MBOX_INT_STATUS_HOST_SET(x)              (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
++
++#define MBOX_INT_ENABLE_ADDRESS                  0x0c01405c
++#define MBOX_INT_ENABLE_OFFSET                   0x0000005c
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB      31
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB      28
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK     0xf0000000
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB  27
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB  24
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB      23
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB      20
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK     0x00f00000
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB          17
++#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB          17
++#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK         0x00020000
++#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
++#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB         16
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB         16
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK        0x00010000
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB         15
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB         12
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK        0x0000f000
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
++#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB          11
++#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB          8
++#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK         0x00000f00
++#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
++#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
++#define MBOX_INT_ENABLE_HOST_MSB                 7
++#define MBOX_INT_ENABLE_HOST_LSB                 0
++#define MBOX_INT_ENABLE_HOST_MASK                0x000000ff
++#define MBOX_INT_ENABLE_HOST_GET(x)              (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
++#define MBOX_INT_ENABLE_HOST_SET(x)              (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
++
++#define INT_HOST_ADDRESS                         0x0c014060
++#define INT_HOST_OFFSET                          0x00000060
++#define INT_HOST_VECTOR_MSB                      7
++#define INT_HOST_VECTOR_LSB                      0
++#define INT_HOST_VECTOR_MASK                     0x000000ff
++#define INT_HOST_VECTOR_GET(x)                   (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
++#define INT_HOST_VECTOR_SET(x)                   (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
++
++#define LOCAL_COUNT_ADDRESS                      0x0c014080
++#define LOCAL_COUNT_OFFSET                       0x00000080
++#define LOCAL_COUNT_VALUE_MSB                    7
++#define LOCAL_COUNT_VALUE_LSB                    0
++#define LOCAL_COUNT_VALUE_MASK                   0x000000ff
++#define LOCAL_COUNT_VALUE_GET(x)                 (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
++#define LOCAL_COUNT_VALUE_SET(x)                 (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
++
++#define COUNT_INC_ADDRESS                        0x0c0140a0
++#define COUNT_INC_OFFSET                         0x000000a0
++#define COUNT_INC_VALUE_MSB                      7
++#define COUNT_INC_VALUE_LSB                      0
++#define COUNT_INC_VALUE_MASK                     0x000000ff
++#define COUNT_INC_VALUE_GET(x)                   (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
++#define COUNT_INC_VALUE_SET(x)                   (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
++
++#define LOCAL_SCRATCH_ADDRESS                    0x0c0140c0
++#define LOCAL_SCRATCH_OFFSET                     0x000000c0
++#define LOCAL_SCRATCH_VALUE_MSB                  7
++#define LOCAL_SCRATCH_VALUE_LSB                  0
++#define LOCAL_SCRATCH_VALUE_MASK                 0x000000ff
++#define LOCAL_SCRATCH_VALUE_GET(x)               (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
++#define LOCAL_SCRATCH_VALUE_SET(x)               (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
++
++#define USE_LOCAL_BUS_ADDRESS                    0x0c0140e0
++#define USE_LOCAL_BUS_OFFSET                     0x000000e0
++#define USE_LOCAL_BUS_PIN_INIT_MSB               0
++#define USE_LOCAL_BUS_PIN_INIT_LSB               0
++#define USE_LOCAL_BUS_PIN_INIT_MASK              0x00000001
++#define USE_LOCAL_BUS_PIN_INIT_GET(x)            (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
++#define USE_LOCAL_BUS_PIN_INIT_SET(x)            (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
++
++#define SDIO_CONFIG_ADDRESS                      0x0c0140e4
++#define SDIO_CONFIG_OFFSET                       0x000000e4
++#define SDIO_CONFIG_CCCR_IOR1_MSB                0
++#define SDIO_CONFIG_CCCR_IOR1_LSB                0
++#define SDIO_CONFIG_CCCR_IOR1_MASK               0x00000001
++#define SDIO_CONFIG_CCCR_IOR1_GET(x)             (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
++#define SDIO_CONFIG_CCCR_IOR1_SET(x)             (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
++
++#define MBOX_DEBUG_ADDRESS                       0x0c0140e8
++#define MBOX_DEBUG_OFFSET                        0x000000e8
++#define MBOX_DEBUG_SEL_MSB                       2
++#define MBOX_DEBUG_SEL_LSB                       0
++#define MBOX_DEBUG_SEL_MASK                      0x00000007
++#define MBOX_DEBUG_SEL_GET(x)                    (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
++#define MBOX_DEBUG_SEL_SET(x)                    (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
++
++#define MBOX_FIFO_RESET_ADDRESS                  0x0c0140ec
++#define MBOX_FIFO_RESET_OFFSET                   0x000000ec
++#define MBOX_FIFO_RESET_INIT_MSB                 0
++#define MBOX_FIFO_RESET_INIT_LSB                 0
++#define MBOX_FIFO_RESET_INIT_MASK                0x00000001
++#define MBOX_FIFO_RESET_INIT_GET(x)              (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
++#define MBOX_FIFO_RESET_INIT_SET(x)              (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
++
++#define STEREO_CONFIG_ADDRESS                    0x0c0140f0
++#define STEREO_CONFIG_OFFSET                     0x000000f0
++#define STEREO_CONFIG_ENABLE_MSB                 24
++#define STEREO_CONFIG_ENABLE_LSB                 24
++#define STEREO_CONFIG_ENABLE_MASK                0x01000000
++#define STEREO_CONFIG_ENABLE_GET(x)              (((x) & STEREO_CONFIG_ENABLE_MASK) >> STEREO_CONFIG_ENABLE_LSB)
++#define STEREO_CONFIG_ENABLE_SET(x)              (((x) << STEREO_CONFIG_ENABLE_LSB) & STEREO_CONFIG_ENABLE_MASK)
++#define STEREO_CONFIG_RESET_MSB                  23
++#define STEREO_CONFIG_RESET_LSB                  23
++#define STEREO_CONFIG_RESET_MASK                 0x00800000
++#define STEREO_CONFIG_RESET_GET(x)               (((x) & STEREO_CONFIG_RESET_MASK) >> STEREO_CONFIG_RESET_LSB)
++#define STEREO_CONFIG_RESET_SET(x)               (((x) << STEREO_CONFIG_RESET_LSB) & STEREO_CONFIG_RESET_MASK)
++#define STEREO_CONFIG_I2S_DELAY_MSB              22
++#define STEREO_CONFIG_I2S_DELAY_LSB              22
++#define STEREO_CONFIG_I2S_DELAY_MASK             0x00400000
++#define STEREO_CONFIG_I2S_DELAY_GET(x)           (((x) & STEREO_CONFIG_I2S_DELAY_MASK) >> STEREO_CONFIG_I2S_DELAY_LSB)
++#define STEREO_CONFIG_I2S_DELAY_SET(x)           (((x) << STEREO_CONFIG_I2S_DELAY_LSB) & STEREO_CONFIG_I2S_DELAY_MASK)
++#define STEREO_CONFIG_MIC_MASTER_MSB             21
++#define STEREO_CONFIG_MIC_MASTER_LSB             21
++#define STEREO_CONFIG_MIC_MASTER_MASK            0x00200000
++#define STEREO_CONFIG_MIC_MASTER_GET(x)          (((x) & STEREO_CONFIG_MIC_MASTER_MASK) >> STEREO_CONFIG_MIC_MASTER_LSB)
++#define STEREO_CONFIG_MIC_MASTER_SET(x)          (((x) << STEREO_CONFIG_MIC_MASTER_LSB) & STEREO_CONFIG_MIC_MASTER_MASK)
++#define STEREO_CONFIG_MIC_WORD_SIZE_MSB          20
++#define STEREO_CONFIG_MIC_WORD_SIZE_LSB          20
++#define STEREO_CONFIG_MIC_WORD_SIZE_MASK         0x00100000
++#define STEREO_CONFIG_MIC_WORD_SIZE_GET(x)       (((x) & STEREO_CONFIG_MIC_WORD_SIZE_MASK) >> STEREO_CONFIG_MIC_WORD_SIZE_LSB)
++#define STEREO_CONFIG_MIC_WORD_SIZE_SET(x)       (((x) << STEREO_CONFIG_MIC_WORD_SIZE_LSB) & STEREO_CONFIG_MIC_WORD_SIZE_MASK)
++#define STEREO_CONFIG_STEREO_MONO_MSB            19
++#define STEREO_CONFIG_STEREO_MONO_LSB            18
++#define STEREO_CONFIG_STEREO_MONO_MASK           0x000c0000
++#define STEREO_CONFIG_STEREO_MONO_GET(x)         (((x) & STEREO_CONFIG_STEREO_MONO_MASK) >> STEREO_CONFIG_STEREO_MONO_LSB)
++#define STEREO_CONFIG_STEREO_MONO_SET(x)         (((x) << STEREO_CONFIG_STEREO_MONO_LSB) & STEREO_CONFIG_STEREO_MONO_MASK)
++#define STEREO_CONFIG_DATA_WORD_SIZE_MSB         17
++#define STEREO_CONFIG_DATA_WORD_SIZE_LSB         16
++#define STEREO_CONFIG_DATA_WORD_SIZE_MASK        0x00030000
++#define STEREO_CONFIG_DATA_WORD_SIZE_GET(x)      (((x) & STEREO_CONFIG_DATA_WORD_SIZE_MASK) >> STEREO_CONFIG_DATA_WORD_SIZE_LSB)
++#define STEREO_CONFIG_DATA_WORD_SIZE_SET(x)      (((x) << STEREO_CONFIG_DATA_WORD_SIZE_LSB) & STEREO_CONFIG_DATA_WORD_SIZE_MASK)
++#define STEREO_CONFIG_I2S_WORD_SIZE_MSB          15
++#define STEREO_CONFIG_I2S_WORD_SIZE_LSB          15
++#define STEREO_CONFIG_I2S_WORD_SIZE_MASK         0x00008000
++#define STEREO_CONFIG_I2S_WORD_SIZE_GET(x)       (((x) & STEREO_CONFIG_I2S_WORD_SIZE_MASK) >> STEREO_CONFIG_I2S_WORD_SIZE_LSB)
++#define STEREO_CONFIG_I2S_WORD_SIZE_SET(x)       (((x) << STEREO_CONFIG_I2S_WORD_SIZE_LSB) & STEREO_CONFIG_I2S_WORD_SIZE_MASK)
++#define STEREO_CONFIG_MCK_SEL_MSB                14
++#define STEREO_CONFIG_MCK_SEL_LSB                14
++#define STEREO_CONFIG_MCK_SEL_MASK               0x00004000
++#define STEREO_CONFIG_MCK_SEL_GET(x)             (((x) & STEREO_CONFIG_MCK_SEL_MASK) >> STEREO_CONFIG_MCK_SEL_LSB)
++#define STEREO_CONFIG_MCK_SEL_SET(x)             (((x) << STEREO_CONFIG_MCK_SEL_LSB) & STEREO_CONFIG_MCK_SEL_MASK)
++#define STEREO_CONFIG_MCK_CNT_MSB                13
++#define STEREO_CONFIG_MCK_CNT_LSB                10
++#define STEREO_CONFIG_MCK_CNT_MASK               0x00003c00
++#define STEREO_CONFIG_MCK_CNT_GET(x)             (((x) & STEREO_CONFIG_MCK_CNT_MASK) >> STEREO_CONFIG_MCK_CNT_LSB)
++#define STEREO_CONFIG_MCK_CNT_SET(x)             (((x) << STEREO_CONFIG_MCK_CNT_LSB) & STEREO_CONFIG_MCK_CNT_MASK)
++#define STEREO_CONFIG_MCK_RAW_MSB                9
++#define STEREO_CONFIG_MCK_RAW_LSB                9
++#define STEREO_CONFIG_MCK_RAW_MASK               0x00000200
++#define STEREO_CONFIG_MCK_RAW_GET(x)             (((x) & STEREO_CONFIG_MCK_RAW_MASK) >> STEREO_CONFIG_MCK_RAW_LSB)
++#define STEREO_CONFIG_MCK_RAW_SET(x)             (((x) << STEREO_CONFIG_MCK_RAW_LSB) & STEREO_CONFIG_MCK_RAW_MASK)
++#define STEREO_CONFIG_MASTER_MSB                 8
++#define STEREO_CONFIG_MASTER_LSB                 8
++#define STEREO_CONFIG_MASTER_MASK                0x00000100
++#define STEREO_CONFIG_MASTER_GET(x)              (((x) & STEREO_CONFIG_MASTER_MASK) >> STEREO_CONFIG_MASTER_LSB)
++#define STEREO_CONFIG_MASTER_SET(x)              (((x) << STEREO_CONFIG_MASTER_LSB) & STEREO_CONFIG_MASTER_MASK)
++#define STEREO_CONFIG_POSEDGE_MSB                7
++#define STEREO_CONFIG_POSEDGE_LSB                0
++#define STEREO_CONFIG_POSEDGE_MASK               0x000000ff
++#define STEREO_CONFIG_POSEDGE_GET(x)             (((x) & STEREO_CONFIG_POSEDGE_MASK) >> STEREO_CONFIG_POSEDGE_LSB)
++#define STEREO_CONFIG_POSEDGE_SET(x)             (((x) << STEREO_CONFIG_POSEDGE_LSB) & STEREO_CONFIG_POSEDGE_MASK)
++
++#define STEREO_VOLUME_ADDRESS                    0x0c0140f4
++#define STEREO_VOLUME_OFFSET                     0x000000f4
++#define STEREO_VOLUME_CHANNEL1_MSB               12
++#define STEREO_VOLUME_CHANNEL1_LSB               8
++#define STEREO_VOLUME_CHANNEL1_MASK              0x00001f00
++#define STEREO_VOLUME_CHANNEL1_GET(x)            (((x) & STEREO_VOLUME_CHANNEL1_MASK) >> STEREO_VOLUME_CHANNEL1_LSB)
++#define STEREO_VOLUME_CHANNEL1_SET(x)            (((x) << STEREO_VOLUME_CHANNEL1_LSB) & STEREO_VOLUME_CHANNEL1_MASK)
++#define STEREO_VOLUME_CHANNEL0_MSB               4
++#define STEREO_VOLUME_CHANNEL0_LSB               0
++#define STEREO_VOLUME_CHANNEL0_MASK              0x0000001f
++#define STEREO_VOLUME_CHANNEL0_GET(x)            (((x) & STEREO_VOLUME_CHANNEL0_MASK) >> STEREO_VOLUME_CHANNEL0_LSB)
++#define STEREO_VOLUME_CHANNEL0_SET(x)            (((x) << STEREO_VOLUME_CHANNEL0_LSB) & STEREO_VOLUME_CHANNEL0_MASK)
++
++#define HOST_IF_WINDOW_ADDRESS                   0x0c016000
++#define HOST_IF_WINDOW_OFFSET                    0x00002000
++#define HOST_IF_WINDOW_DATA_MSB                  7
++#define HOST_IF_WINDOW_DATA_LSB                  0
++#define HOST_IF_WINDOW_DATA_MASK                 0x000000ff
++#define HOST_IF_WINDOW_DATA_GET(x)               (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
++#define HOST_IF_WINDOW_DATA_SET(x)               (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mbox_reg_s {
++  volatile unsigned int mbox_fifo[4];
++  volatile unsigned int mbox_fifo_status;
++  volatile unsigned int mbox_dma_policy;
++  volatile unsigned int mbox0_dma_rx_descriptor_base;
++  volatile unsigned int mbox0_dma_rx_control;
++  volatile unsigned int mbox0_dma_tx_descriptor_base;
++  volatile unsigned int mbox0_dma_tx_control;
++  volatile unsigned int mbox1_dma_rx_descriptor_base;
++  volatile unsigned int mbox1_dma_rx_control;
++  volatile unsigned int mbox1_dma_tx_descriptor_base;
++  volatile unsigned int mbox1_dma_tx_control;
++  volatile unsigned int mbox2_dma_rx_descriptor_base;
++  volatile unsigned int mbox2_dma_rx_control;
++  volatile unsigned int mbox2_dma_tx_descriptor_base;
++  volatile unsigned int mbox2_dma_tx_control;
++  volatile unsigned int mbox3_dma_rx_descriptor_base;
++  volatile unsigned int mbox3_dma_rx_control;
++  volatile unsigned int mbox3_dma_tx_descriptor_base;
++  volatile unsigned int mbox3_dma_tx_control;
++  volatile unsigned int mbox_int_status;
++  volatile unsigned int mbox_int_enable;
++  volatile unsigned int int_host;
++  unsigned char pad0[28]; /* pad to 0x80 */
++  volatile unsigned int local_count[8];
++  volatile unsigned int count_inc[8];
++  volatile unsigned int local_scratch[8];
++  volatile unsigned int use_local_bus;
++  volatile unsigned int sdio_config;
++  volatile unsigned int mbox_debug;
++  volatile unsigned int mbox_fifo_reset;
++  volatile unsigned int stereo_config;
++  volatile unsigned int stereo_volume;
++  unsigned char pad1[7944]; /* pad to 0x2000 */
++  volatile unsigned int host_if_window[2048];
++} mbox_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MBOX_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mc_reg.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/mc_reg.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,1129 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _MC_REG_H_
++#define _MC_REG_H_
++
++#define BANK0_ADDR_ADDRESS                       0x0c004000
++#define BANK0_ADDR_OFFSET                        0x00000000
++#define BANK0_ADDR_SIZE_MSB                      31
++#define BANK0_ADDR_SIZE_LSB                      28
++#define BANK0_ADDR_SIZE_MASK                     0xf0000000
++#define BANK0_ADDR_SIZE_GET(x)                   (((x) & BANK0_ADDR_SIZE_MASK) >> BANK0_ADDR_SIZE_LSB)
++#define BANK0_ADDR_SIZE_SET(x)                   (((x) << BANK0_ADDR_SIZE_LSB) & BANK0_ADDR_SIZE_MASK)
++#define BANK0_ADDR_BASE_MSB                      27
++#define BANK0_ADDR_BASE_LSB                      10
++#define BANK0_ADDR_BASE_MASK                     0x0ffffc00
++#define BANK0_ADDR_BASE_GET(x)                   (((x) & BANK0_ADDR_BASE_MASK) >> BANK0_ADDR_BASE_LSB)
++#define BANK0_ADDR_BASE_SET(x)                   (((x) << BANK0_ADDR_BASE_LSB) & BANK0_ADDR_BASE_MASK)
++
++#define BANK0_CONFIG_ADDRESS                     0x0c004004
++#define BANK0_CONFIG_OFFSET                      0x00000004
++#define BANK0_CONFIG_ENABLE_MSB                  31
++#define BANK0_CONFIG_ENABLE_LSB                  31
++#define BANK0_CONFIG_ENABLE_MASK                 0x80000000
++#define BANK0_CONFIG_ENABLE_GET(x)               (((x) & BANK0_CONFIG_ENABLE_MASK) >> BANK0_CONFIG_ENABLE_LSB)
++#define BANK0_CONFIG_ENABLE_SET(x)               (((x) << BANK0_CONFIG_ENABLE_LSB) & BANK0_CONFIG_ENABLE_MASK)
++#define BANK0_CONFIG_WIDTH_MSB                   28
++#define BANK0_CONFIG_WIDTH_LSB                   28
++#define BANK0_CONFIG_WIDTH_MASK                  0x10000000
++#define BANK0_CONFIG_WIDTH_GET(x)                (((x) & BANK0_CONFIG_WIDTH_MASK) >> BANK0_CONFIG_WIDTH_LSB)
++#define BANK0_CONFIG_WIDTH_SET(x)                (((x) << BANK0_CONFIG_WIDTH_LSB) & BANK0_CONFIG_WIDTH_MASK)
++#define BANK0_CONFIG_PROTECT_MSB                 26
++#define BANK0_CONFIG_PROTECT_LSB                 26
++#define BANK0_CONFIG_PROTECT_MASK                0x04000000
++#define BANK0_CONFIG_PROTECT_GET(x)              (((x) & BANK0_CONFIG_PROTECT_MASK) >> BANK0_CONFIG_PROTECT_LSB)
++#define BANK0_CONFIG_PROTECT_SET(x)              (((x) << BANK0_CONFIG_PROTECT_LSB) & BANK0_CONFIG_PROTECT_MASK)
++#define BANK0_CONFIG_WB_ENABLE_MSB               25
++#define BANK0_CONFIG_WB_ENABLE_LSB               25
++#define BANK0_CONFIG_WB_ENABLE_MASK              0x02000000
++#define BANK0_CONFIG_WB_ENABLE_GET(x)            (((x) & BANK0_CONFIG_WB_ENABLE_MASK) >> BANK0_CONFIG_WB_ENABLE_LSB)
++#define BANK0_CONFIG_WB_ENABLE_SET(x)            (((x) << BANK0_CONFIG_WB_ENABLE_LSB) & BANK0_CONFIG_WB_ENABLE_MASK)
++#define BANK0_CONFIG_WB_FLUSH_MSB                24
++#define BANK0_CONFIG_WB_FLUSH_LSB                24
++#define BANK0_CONFIG_WB_FLUSH_MASK               0x01000000
++#define BANK0_CONFIG_WB_FLUSH_GET(x)             (((x) & BANK0_CONFIG_WB_FLUSH_MASK) >> BANK0_CONFIG_WB_FLUSH_LSB)
++#define BANK0_CONFIG_WB_FLUSH_SET(x)             (((x) << BANK0_CONFIG_WB_FLUSH_LSB) & BANK0_CONFIG_WB_FLUSH_MASK)
++#define BANK0_CONFIG_SCALE_MSB                   21
++#define BANK0_CONFIG_SCALE_LSB                   20
++#define BANK0_CONFIG_SCALE_MASK                  0x00300000
++#define BANK0_CONFIG_SCALE_GET(x)                (((x) & BANK0_CONFIG_SCALE_MASK) >> BANK0_CONFIG_SCALE_LSB)
++#define BANK0_CONFIG_SCALE_SET(x)                (((x) << BANK0_CONFIG_SCALE_LSB) & BANK0_CONFIG_SCALE_MASK)
++#define BANK0_CONFIG_HOLDOFF_MSB                 19
++#define BANK0_CONFIG_HOLDOFF_LSB                 16
++#define BANK0_CONFIG_HOLDOFF_MASK                0x000f0000
++#define BANK0_CONFIG_HOLDOFF_GET(x)              (((x) & BANK0_CONFIG_HOLDOFF_MASK) >> BANK0_CONFIG_HOLDOFF_LSB)
++#define BANK0_CONFIG_HOLDOFF_SET(x)              (((x) << BANK0_CONFIG_HOLDOFF_LSB) & BANK0_CONFIG_HOLDOFF_MASK)
++#define BANK0_CONFIG_TIMER3_MSB                  15
++#define BANK0_CONFIG_TIMER3_LSB                  12
++#define BANK0_CONFIG_TIMER3_MASK                 0x0000f000
++#define BANK0_CONFIG_TIMER3_GET(x)               (((x) & BANK0_CONFIG_TIMER3_MASK) >> BANK0_CONFIG_TIMER3_LSB)
++#define BANK0_CONFIG_TIMER3_SET(x)               (((x) << BANK0_CONFIG_TIMER3_LSB) & BANK0_CONFIG_TIMER3_MASK)
++#define BANK0_CONFIG_TIMER2_MSB                  11
++#define BANK0_CONFIG_TIMER2_LSB                  8
++#define BANK0_CONFIG_TIMER2_MASK                 0x00000f00
++#define BANK0_CONFIG_TIMER2_GET(x)               (((x) & BANK0_CONFIG_TIMER2_MASK) >> BANK0_CONFIG_TIMER2_LSB)
++#define BANK0_CONFIG_TIMER2_SET(x)               (((x) << BANK0_CONFIG_TIMER2_LSB) & BANK0_CONFIG_TIMER2_MASK)
++#define BANK0_CONFIG_TIMER1_MSB                  7
++#define BANK0_CONFIG_TIMER1_LSB                  4
++#define BANK0_CONFIG_TIMER1_MASK                 0x000000f0
++#define BANK0_CONFIG_TIMER1_GET(x)               (((x) & BANK0_CONFIG_TIMER1_MASK) >> BANK0_CONFIG_TIMER1_LSB)
++#define BANK0_CONFIG_TIMER1_SET(x)               (((x) << BANK0_CONFIG_TIMER1_LSB) & BANK0_CONFIG_TIMER1_MASK)
++#define BANK0_CONFIG_TIMER0_MSB                  3
++#define BANK0_CONFIG_TIMER0_LSB                  0
++#define BANK0_CONFIG_TIMER0_MASK                 0x0000000f
++#define BANK0_CONFIG_TIMER0_GET(x)               (((x) & BANK0_CONFIG_TIMER0_MASK) >> BANK0_CONFIG_TIMER0_LSB)
++#define BANK0_CONFIG_TIMER0_SET(x)               (((x) << BANK0_CONFIG_TIMER0_LSB) & BANK0_CONFIG_TIMER0_MASK)
++
++#define BANK0_READ_ADDRESS                       0x0c004008
++#define BANK0_READ_OFFSET                        0x00000008
++#define BANK0_READ_ENABLE_WAIT_MSB               31
++#define BANK0_READ_ENABLE_WAIT_LSB               31
++#define BANK0_READ_ENABLE_WAIT_MASK              0x80000000
++#define BANK0_READ_ENABLE_WAIT_GET(x)            (((x) & BANK0_READ_ENABLE_WAIT_MASK) >> BANK0_READ_ENABLE_WAIT_LSB)
++#define BANK0_READ_ENABLE_WAIT_SET(x)            (((x) << BANK0_READ_ENABLE_WAIT_LSB) & BANK0_READ_ENABLE_WAIT_MASK)
++#define BANK0_READ_WAIT_EVENT_MSB                30
++#define BANK0_READ_WAIT_EVENT_LSB                28
++#define BANK0_READ_WAIT_EVENT_MASK               0x70000000
++#define BANK0_READ_WAIT_EVENT_GET(x)             (((x) & BANK0_READ_WAIT_EVENT_MASK) >> BANK0_READ_WAIT_EVENT_LSB)
++#define BANK0_READ_WAIT_EVENT_SET(x)             (((x) << BANK0_READ_WAIT_EVENT_LSB) & BANK0_READ_WAIT_EVENT_MASK)
++#define BANK0_READ_END_EVENT_MSB                 26
++#define BANK0_READ_END_EVENT_LSB                 24
++#define BANK0_READ_END_EVENT_MASK                0x07000000
++#define BANK0_READ_END_EVENT_GET(x)              (((x) & BANK0_READ_END_EVENT_MASK) >> BANK0_READ_END_EVENT_LSB)
++#define BANK0_READ_END_EVENT_SET(x)              (((x) << BANK0_READ_END_EVENT_LSB) & BANK0_READ_END_EVENT_MASK)
++#define BANK0_READ_BURST_END_EVENT_MSB           22
++#define BANK0_READ_BURST_END_EVENT_LSB           20
++#define BANK0_READ_BURST_END_EVENT_MASK          0x00700000
++#define BANK0_READ_BURST_END_EVENT_GET(x)        (((x) & BANK0_READ_BURST_END_EVENT_MASK) >> BANK0_READ_BURST_END_EVENT_LSB)
++#define BANK0_READ_BURST_END_EVENT_SET(x)        (((x) << BANK0_READ_BURST_END_EVENT_LSB) & BANK0_READ_BURST_END_EVENT_MASK)
++#define BANK0_READ_BURST_START_EVENT_MSB         18
++#define BANK0_READ_BURST_START_EVENT_LSB         16
++#define BANK0_READ_BURST_START_EVENT_MASK        0x00070000
++#define BANK0_READ_BURST_START_EVENT_GET(x)      (((x) & BANK0_READ_BURST_START_EVENT_MASK) >> BANK0_READ_BURST_START_EVENT_LSB)
++#define BANK0_READ_BURST_START_EVENT_SET(x)      (((x) << BANK0_READ_BURST_START_EVENT_LSB) & BANK0_READ_BURST_START_EVENT_MASK)
++#define BANK0_READ_EVENT3_DC_MSB                 15
++#define BANK0_READ_EVENT3_DC_LSB                 15
++#define BANK0_READ_EVENT3_DC_MASK                0x00008000
++#define BANK0_READ_EVENT3_DC_GET(x)              (((x) & BANK0_READ_EVENT3_DC_MASK) >> BANK0_READ_EVENT3_DC_LSB)
++#define BANK0_READ_EVENT3_DC_SET(x)              (((x) << BANK0_READ_EVENT3_DC_LSB) & BANK0_READ_EVENT3_DC_MASK)
++#define BANK0_READ_EVENT3_BE_MSB                 14
++#define BANK0_READ_EVENT3_BE_LSB                 14
++#define BANK0_READ_EVENT3_BE_MASK                0x00004000
++#define BANK0_READ_EVENT3_BE_GET(x)              (((x) & BANK0_READ_EVENT3_BE_MASK) >> BANK0_READ_EVENT3_BE_LSB)
++#define BANK0_READ_EVENT3_BE_SET(x)              (((x) << BANK0_READ_EVENT3_BE_LSB) & BANK0_READ_EVENT3_BE_MASK)
++#define BANK0_READ_EVENT3_OE_MSB                 13
++#define BANK0_READ_EVENT3_OE_LSB                 13
++#define BANK0_READ_EVENT3_OE_MASK                0x00002000
++#define BANK0_READ_EVENT3_OE_GET(x)              (((x) & BANK0_READ_EVENT3_OE_MASK) >> BANK0_READ_EVENT3_OE_LSB)
++#define BANK0_READ_EVENT3_OE_SET(x)              (((x) << BANK0_READ_EVENT3_OE_LSB) & BANK0_READ_EVENT3_OE_MASK)
++#define BANK0_READ_EVENT3_CS_MSB                 12
++#define BANK0_READ_EVENT3_CS_LSB                 12
++#define BANK0_READ_EVENT3_CS_MASK                0x00001000
++#define BANK0_READ_EVENT3_CS_GET(x)              (((x) & BANK0_READ_EVENT3_CS_MASK) >> BANK0_READ_EVENT3_CS_LSB)
++#define BANK0_READ_EVENT3_CS_SET(x)              (((x) << BANK0_READ_EVENT3_CS_LSB) & BANK0_READ_EVENT3_CS_MASK)
++#define BANK0_READ_EVENT2_DC_MSB                 11
++#define BANK0_READ_EVENT2_DC_LSB                 11
++#define BANK0_READ_EVENT2_DC_MASK                0x00000800
++#define BANK0_READ_EVENT2_DC_GET(x)              (((x) & BANK0_READ_EVENT2_DC_MASK) >> BANK0_READ_EVENT2_DC_LSB)
++#define BANK0_READ_EVENT2_DC_SET(x)              (((x) << BANK0_READ_EVENT2_DC_LSB) & BANK0_READ_EVENT2_DC_MASK)
++#define BANK0_READ_EVENT2_BE_MSB                 10
++#define BANK0_READ_EVENT2_BE_LSB                 10
++#define BANK0_READ_EVENT2_BE_MASK                0x00000400
++#define BANK0_READ_EVENT2_BE_GET(x)              (((x) & BANK0_READ_EVENT2_BE_MASK) >> BANK0_READ_EVENT2_BE_LSB)
++#define BANK0_READ_EVENT2_BE_SET(x)              (((x) << BANK0_READ_EVENT2_BE_LSB) & BANK0_READ_EVENT2_BE_MASK)
++#define BANK0_READ_EVENT2_OE_MSB                 9
++#define BANK0_READ_EVENT2_OE_LSB                 9
++#define BANK0_READ_EVENT2_OE_MASK                0x00000200
++#define BANK0_READ_EVENT2_OE_GET(x)              (((x) & BANK0_READ_EVENT2_OE_MASK) >> BANK0_READ_EVENT2_OE_LSB)
++#define BANK0_READ_EVENT2_OE_SET(x)              (((x) << BANK0_READ_EVENT2_OE_LSB) & BANK0_READ_EVENT2_OE_MASK)
++#define BANK0_READ_EVENT2_CS_MSB                 8
++#define BANK0_READ_EVENT2_CS_LSB                 8
++#define BANK0_READ_EVENT2_CS_MASK                0x00000100
++#define BANK0_READ_EVENT2_CS_GET(x)              (((x) & BANK0_READ_EVENT2_CS_MASK) >> BANK0_READ_EVENT2_CS_LSB)
++#define BANK0_READ_EVENT2_CS_SET(x)              (((x) << BANK0_READ_EVENT2_CS_LSB) & BANK0_READ_EVENT2_CS_MASK)
++#define BANK0_READ_EVENT1_DC_MSB                 7
++#define BANK0_READ_EVENT1_DC_LSB                 7
++#define BANK0_READ_EVENT1_DC_MASK                0x00000080
++#define BANK0_READ_EVENT1_DC_GET(x)              (((x) & BANK0_READ_EVENT1_DC_MASK) >> BANK0_READ_EVENT1_DC_LSB)
++#define BANK0_READ_EVENT1_DC_SET(x)              (((x) << BANK0_READ_EVENT1_DC_LSB) & BANK0_READ_EVENT1_DC_MASK)
++#define BANK0_READ_EVENT1_BE_MSB                 6
++#define BANK0_READ_EVENT1_BE_LSB                 6
++#define BANK0_READ_EVENT1_BE_MASK                0x00000040
++#define BANK0_READ_EVENT1_BE_GET(x)              (((x) & BANK0_READ_EVENT1_BE_MASK) >> BANK0_READ_EVENT1_BE_LSB)
++#define BANK0_READ_EVENT1_BE_SET(x)              (((x) << BANK0_READ_EVENT1_BE_LSB) & BANK0_READ_EVENT1_BE_MASK)
++#define BANK0_READ_EVENT1_OE_MSB                 5
++#define BANK0_READ_EVENT1_OE_LSB                 5
++#define BANK0_READ_EVENT1_OE_MASK                0x00000020
++#define BANK0_READ_EVENT1_OE_GET(x)              (((x) & BANK0_READ_EVENT1_OE_MASK) >> BANK0_READ_EVENT1_OE_LSB)
++#define BANK0_READ_EVENT1_OE_SET(x)              (((x) << BANK0_READ_EVENT1_OE_LSB) & BANK0_READ_EVENT1_OE_MASK)
++#define BANK0_READ_EVENT1_CS_MSB                 4
++#define BANK0_READ_EVENT1_CS_LSB                 4
++#define BANK0_READ_EVENT1_CS_MASK                0x00000010
++#define BANK0_READ_EVENT1_CS_GET(x)              (((x) & BANK0_READ_EVENT1_CS_MASK) >> BANK0_READ_EVENT1_CS_LSB)
++#define BANK0_READ_EVENT1_CS_SET(x)              (((x) << BANK0_READ_EVENT1_CS_LSB) & BANK0_READ_EVENT1_CS_MASK)
++#define BANK0_READ_EVENT0_DC_MSB                 3
++#define BANK0_READ_EVENT0_DC_LSB                 3
++#define BANK0_READ_EVENT0_DC_MASK                0x00000008
++#define BANK0_READ_EVENT0_DC_GET(x)              (((x) & BANK0_READ_EVENT0_DC_MASK) >> BANK0_READ_EVENT0_DC_LSB)
++#define BANK0_READ_EVENT0_DC_SET(x)              (((x) << BANK0_READ_EVENT0_DC_LSB) & BANK0_READ_EVENT0_DC_MASK)
++#define BANK0_READ_EVENT0_BE_MSB                 2
++#define BANK0_READ_EVENT0_BE_LSB                 2
++#define BANK0_READ_EVENT0_BE_MASK                0x00000004
++#define BANK0_READ_EVENT0_BE_GET(x)              (((x) & BANK0_READ_EVENT0_BE_MASK) >> BANK0_READ_EVENT0_BE_LSB)
++#define BANK0_READ_EVENT0_BE_SET(x)              (((x) << BANK0_READ_EVENT0_BE_LSB) & BANK0_READ_EVENT0_BE_MASK)
++#define BANK0_READ_EVENT0_OE_MSB                 1
++#define BANK0_READ_EVENT0_OE_LSB                 1
++#define BANK0_READ_EVENT0_OE_MASK                0x00000002
++#define BANK0_READ_EVENT0_OE_GET(x)              (((x) & BANK0_READ_EVENT0_OE_MASK) >> BANK0_READ_EVENT0_OE_LSB)
++#define BANK0_READ_EVENT0_OE_SET(x)              (((x) << BANK0_READ_EVENT0_OE_LSB) & BANK0_READ_EVENT0_OE_MASK)
++#define BANK0_READ_EVENT0_CS_MSB                 0
++#define BANK0_READ_EVENT0_CS_LSB                 0
++#define BANK0_READ_EVENT0_CS_MASK                0x00000001
++#define BANK0_READ_EVENT0_CS_GET(x)              (((x) & BANK0_READ_EVENT0_CS_MASK) >> BANK0_READ_EVENT0_CS_LSB)
++#define BANK0_READ_EVENT0_CS_SET(x)              (((x) << BANK0_READ_EVENT0_CS_LSB) & BANK0_READ_EVENT0_CS_MASK)
++
++#define BANK0_WRITE_ADDRESS                      0x0c00400c
++#define BANK0_WRITE_OFFSET                       0x0000000c
++#define BANK0_WRITE_ENABLE_WAIT_MSB              31
++#define BANK0_WRITE_ENABLE_WAIT_LSB              31
++#define BANK0_WRITE_ENABLE_WAIT_MASK             0x80000000
++#define BANK0_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK0_WRITE_ENABLE_WAIT_MASK) >> BANK0_WRITE_ENABLE_WAIT_LSB)
++#define BANK0_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK0_WRITE_ENABLE_WAIT_LSB) & BANK0_WRITE_ENABLE_WAIT_MASK)
++#define BANK0_WRITE_WAIT_EVENT_MSB               30
++#define BANK0_WRITE_WAIT_EVENT_LSB               28
++#define BANK0_WRITE_WAIT_EVENT_MASK              0x70000000
++#define BANK0_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK0_WRITE_WAIT_EVENT_MASK) >> BANK0_WRITE_WAIT_EVENT_LSB)
++#define BANK0_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK0_WRITE_WAIT_EVENT_LSB) & BANK0_WRITE_WAIT_EVENT_MASK)
++#define BANK0_WRITE_END_EVENT_MSB                26
++#define BANK0_WRITE_END_EVENT_LSB                24
++#define BANK0_WRITE_END_EVENT_MASK               0x07000000
++#define BANK0_WRITE_END_EVENT_GET(x)             (((x) & BANK0_WRITE_END_EVENT_MASK) >> BANK0_WRITE_END_EVENT_LSB)
++#define BANK0_WRITE_END_EVENT_SET(x)             (((x) << BANK0_WRITE_END_EVENT_LSB) & BANK0_WRITE_END_EVENT_MASK)
++#define BANK0_WRITE_BURST_END_EVENT_MSB          22
++#define BANK0_WRITE_BURST_END_EVENT_LSB          20
++#define BANK0_WRITE_BURST_END_EVENT_MASK         0x00700000
++#define BANK0_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK0_WRITE_BURST_END_EVENT_MASK) >> BANK0_WRITE_BURST_END_EVENT_LSB)
++#define BANK0_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK0_WRITE_BURST_END_EVENT_LSB) & BANK0_WRITE_BURST_END_EVENT_MASK)
++#define BANK0_WRITE_BURST_START_EVENT_MSB        18
++#define BANK0_WRITE_BURST_START_EVENT_LSB        16
++#define BANK0_WRITE_BURST_START_EVENT_MASK       0x00070000
++#define BANK0_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK0_WRITE_BURST_START_EVENT_MASK) >> BANK0_WRITE_BURST_START_EVENT_LSB)
++#define BANK0_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK0_WRITE_BURST_START_EVENT_LSB) & BANK0_WRITE_BURST_START_EVENT_MASK)
++#define BANK0_WRITE_EVENT3_BE_MSB                14
++#define BANK0_WRITE_EVENT3_BE_LSB                14
++#define BANK0_WRITE_EVENT3_BE_MASK               0x00004000
++#define BANK0_WRITE_EVENT3_BE_GET(x)             (((x) & BANK0_WRITE_EVENT3_BE_MASK) >> BANK0_WRITE_EVENT3_BE_LSB)
++#define BANK0_WRITE_EVENT3_BE_SET(x)             (((x) << BANK0_WRITE_EVENT3_BE_LSB) & BANK0_WRITE_EVENT3_BE_MASK)
++#define BANK0_WRITE_EVENT3_WE_MSB                13
++#define BANK0_WRITE_EVENT3_WE_LSB                13
++#define BANK0_WRITE_EVENT3_WE_MASK               0x00002000
++#define BANK0_WRITE_EVENT3_WE_GET(x)             (((x) & BANK0_WRITE_EVENT3_WE_MASK) >> BANK0_WRITE_EVENT3_WE_LSB)
++#define BANK0_WRITE_EVENT3_WE_SET(x)             (((x) << BANK0_WRITE_EVENT3_WE_LSB) & BANK0_WRITE_EVENT3_WE_MASK)
++#define BANK0_WRITE_EVENT3_CS_MSB                12
++#define BANK0_WRITE_EVENT3_CS_LSB                12
++#define BANK0_WRITE_EVENT3_CS_MASK               0x00001000
++#define BANK0_WRITE_EVENT3_CS_GET(x)             (((x) & BANK0_WRITE_EVENT3_CS_MASK) >> BANK0_WRITE_EVENT3_CS_LSB)
++#define BANK0_WRITE_EVENT3_CS_SET(x)             (((x) << BANK0_WRITE_EVENT3_CS_LSB) & BANK0_WRITE_EVENT3_CS_MASK)
++#define BANK0_WRITE_EVENT2_BE_MSB                10
++#define BANK0_WRITE_EVENT2_BE_LSB                10
++#define BANK0_WRITE_EVENT2_BE_MASK               0x00000400
++#define BANK0_WRITE_EVENT2_BE_GET(x)             (((x) & BANK0_WRITE_EVENT2_BE_MASK) >> BANK0_WRITE_EVENT2_BE_LSB)
++#define BANK0_WRITE_EVENT2_BE_SET(x)             (((x) << BANK0_WRITE_EVENT2_BE_LSB) & BANK0_WRITE_EVENT2_BE_MASK)
++#define BANK0_WRITE_EVENT2_WE_MSB                9
++#define BANK0_WRITE_EVENT2_WE_LSB                9
++#define BANK0_WRITE_EVENT2_WE_MASK               0x00000200
++#define BANK0_WRITE_EVENT2_WE_GET(x)             (((x) & BANK0_WRITE_EVENT2_WE_MASK) >> BANK0_WRITE_EVENT2_WE_LSB)
++#define BANK0_WRITE_EVENT2_WE_SET(x)             (((x) << BANK0_WRITE_EVENT2_WE_LSB) & BANK0_WRITE_EVENT2_WE_MASK)
++#define BANK0_WRITE_EVENT2_CS_MSB                8
++#define BANK0_WRITE_EVENT2_CS_LSB                8
++#define BANK0_WRITE_EVENT2_CS_MASK               0x00000100
++#define BANK0_WRITE_EVENT2_CS_GET(x)             (((x) & BANK0_WRITE_EVENT2_CS_MASK) >> BANK0_WRITE_EVENT2_CS_LSB)
++#define BANK0_WRITE_EVENT2_CS_SET(x)             (((x) << BANK0_WRITE_EVENT2_CS_LSB) & BANK0_WRITE_EVENT2_CS_MASK)
++#define BANK0_WRITE_EVENT1_BE_MSB                6
++#define BANK0_WRITE_EVENT1_BE_LSB                6
++#define BANK0_WRITE_EVENT1_BE_MASK               0x00000040
++#define BANK0_WRITE_EVENT1_BE_GET(x)             (((x) & BANK0_WRITE_EVENT1_BE_MASK) >> BANK0_WRITE_EVENT1_BE_LSB)
++#define BANK0_WRITE_EVENT1_BE_SET(x)             (((x) << BANK0_WRITE_EVENT1_BE_LSB) & BANK0_WRITE_EVENT1_BE_MASK)
++#define BANK0_WRITE_EVENT1_WE_MSB                5
++#define BANK0_WRITE_EVENT1_WE_LSB                5
++#define BANK0_WRITE_EVENT1_WE_MASK               0x00000020
++#define BANK0_WRITE_EVENT1_WE_GET(x)             (((x) & BANK0_WRITE_EVENT1_WE_MASK) >> BANK0_WRITE_EVENT1_WE_LSB)
++#define BANK0_WRITE_EVENT1_WE_SET(x)             (((x) << BANK0_WRITE_EVENT1_WE_LSB) & BANK0_WRITE_EVENT1_WE_MASK)
++#define BANK0_WRITE_EVENT1_CS_MSB                4
++#define BANK0_WRITE_EVENT1_CS_LSB                4
++#define BANK0_WRITE_EVENT1_CS_MASK               0x00000010
++#define BANK0_WRITE_EVENT1_CS_GET(x)             (((x) & BANK0_WRITE_EVENT1_CS_MASK) >> BANK0_WRITE_EVENT1_CS_LSB)
++#define BANK0_WRITE_EVENT1_CS_SET(x)             (((x) << BANK0_WRITE_EVENT1_CS_LSB) & BANK0_WRITE_EVENT1_CS_MASK)
++#define BANK0_WRITE_EVENT0_BE_MSB                2
++#define BANK0_WRITE_EVENT0_BE_LSB                2
++#define BANK0_WRITE_EVENT0_BE_MASK               0x00000004
++#define BANK0_WRITE_EVENT0_BE_GET(x)             (((x) & BANK0_WRITE_EVENT0_BE_MASK) >> BANK0_WRITE_EVENT0_BE_LSB)
++#define BANK0_WRITE_EVENT0_BE_SET(x)             (((x) << BANK0_WRITE_EVENT0_BE_LSB) & BANK0_WRITE_EVENT0_BE_MASK)
++#define BANK0_WRITE_EVENT0_WE_MSB                1
++#define BANK0_WRITE_EVENT0_WE_LSB                1
++#define BANK0_WRITE_EVENT0_WE_MASK               0x00000002
++#define BANK0_WRITE_EVENT0_WE_GET(x)             (((x) & BANK0_WRITE_EVENT0_WE_MASK) >> BANK0_WRITE_EVENT0_WE_LSB)
++#define BANK0_WRITE_EVENT0_WE_SET(x)             (((x) << BANK0_WRITE_EVENT0_WE_LSB) & BANK0_WRITE_EVENT0_WE_MASK)
++#define BANK0_WRITE_EVENT0_CS_MSB                0
++#define BANK0_WRITE_EVENT0_CS_LSB                0
++#define BANK0_WRITE_EVENT0_CS_MASK               0x00000001
++#define BANK0_WRITE_EVENT0_CS_GET(x)             (((x) & BANK0_WRITE_EVENT0_CS_MASK) >> BANK0_WRITE_EVENT0_CS_LSB)
++#define BANK0_WRITE_EVENT0_CS_SET(x)             (((x) << BANK0_WRITE_EVENT0_CS_LSB) & BANK0_WRITE_EVENT0_CS_MASK)
++
++#define BANK1_ADDR_ADDRESS                       0x0c004010
++#define BANK1_ADDR_OFFSET                        0x00000010
++#define BANK1_ADDR_SIZE_MSB                      31
++#define BANK1_ADDR_SIZE_LSB                      28
++#define BANK1_ADDR_SIZE_MASK                     0xf0000000
++#define BANK1_ADDR_SIZE_GET(x)                   (((x) & BANK1_ADDR_SIZE_MASK) >> BANK1_ADDR_SIZE_LSB)
++#define BANK1_ADDR_SIZE_SET(x)                   (((x) << BANK1_ADDR_SIZE_LSB) & BANK1_ADDR_SIZE_MASK)
++#define BANK1_ADDR_BASE_MSB                      27
++#define BANK1_ADDR_BASE_LSB                      10
++#define BANK1_ADDR_BASE_MASK                     0x0ffffc00
++#define BANK1_ADDR_BASE_GET(x)                   (((x) & BANK1_ADDR_BASE_MASK) >> BANK1_ADDR_BASE_LSB)
++#define BANK1_ADDR_BASE_SET(x)                   (((x) << BANK1_ADDR_BASE_LSB) & BANK1_ADDR_BASE_MASK)
++
++#define BANK1_CONFIG_ADDRESS                     0x0c004014
++#define BANK1_CONFIG_OFFSET                      0x00000014
++#define BANK1_CONFIG_ENABLE_MSB                  31
++#define BANK1_CONFIG_ENABLE_LSB                  31
++#define BANK1_CONFIG_ENABLE_MASK                 0x80000000
++#define BANK1_CONFIG_ENABLE_GET(x)               (((x) & BANK1_CONFIG_ENABLE_MASK) >> BANK1_CONFIG_ENABLE_LSB)
++#define BANK1_CONFIG_ENABLE_SET(x)               (((x) << BANK1_CONFIG_ENABLE_LSB) & BANK1_CONFIG_ENABLE_MASK)
++#define BANK1_CONFIG_WIDTH_MSB                   28
++#define BANK1_CONFIG_WIDTH_LSB                   28
++#define BANK1_CONFIG_WIDTH_MASK                  0x10000000
++#define BANK1_CONFIG_WIDTH_GET(x)                (((x) & BANK1_CONFIG_WIDTH_MASK) >> BANK1_CONFIG_WIDTH_LSB)
++#define BANK1_CONFIG_WIDTH_SET(x)                (((x) << BANK1_CONFIG_WIDTH_LSB) & BANK1_CONFIG_WIDTH_MASK)
++#define BANK1_CONFIG_PROTECT_MSB                 26
++#define BANK1_CONFIG_PROTECT_LSB                 26
++#define BANK1_CONFIG_PROTECT_MASK                0x04000000
++#define BANK1_CONFIG_PROTECT_GET(x)              (((x) & BANK1_CONFIG_PROTECT_MASK) >> BANK1_CONFIG_PROTECT_LSB)
++#define BANK1_CONFIG_PROTECT_SET(x)              (((x) << BANK1_CONFIG_PROTECT_LSB) & BANK1_CONFIG_PROTECT_MASK)
++#define BANK1_CONFIG_WB_ENABLE_MSB               25
++#define BANK1_CONFIG_WB_ENABLE_LSB               25
++#define BANK1_CONFIG_WB_ENABLE_MASK              0x02000000
++#define BANK1_CONFIG_WB_ENABLE_GET(x)            (((x) & BANK1_CONFIG_WB_ENABLE_MASK) >> BANK1_CONFIG_WB_ENABLE_LSB)
++#define BANK1_CONFIG_WB_ENABLE_SET(x)            (((x) << BANK1_CONFIG_WB_ENABLE_LSB) & BANK1_CONFIG_WB_ENABLE_MASK)
++#define BANK1_CONFIG_WB_FLUSH_MSB                24
++#define BANK1_CONFIG_WB_FLUSH_LSB                24
++#define BANK1_CONFIG_WB_FLUSH_MASK               0x01000000
++#define BANK1_CONFIG_WB_FLUSH_GET(x)             (((x) & BANK1_CONFIG_WB_FLUSH_MASK) >> BANK1_CONFIG_WB_FLUSH_LSB)
++#define BANK1_CONFIG_WB_FLUSH_SET(x)             (((x) << BANK1_CONFIG_WB_FLUSH_LSB) & BANK1_CONFIG_WB_FLUSH_MASK)
++#define BANK1_CONFIG_SCALE_MSB                   21
++#define BANK1_CONFIG_SCALE_LSB                   20
++#define BANK1_CONFIG_SCALE_MASK                  0x00300000
++#define BANK1_CONFIG_SCALE_GET(x)                (((x) & BANK1_CONFIG_SCALE_MASK) >> BANK1_CONFIG_SCALE_LSB)
++#define BANK1_CONFIG_SCALE_SET(x)                (((x) << BANK1_CONFIG_SCALE_LSB) & BANK1_CONFIG_SCALE_MASK)
++#define BANK1_CONFIG_HOLDOFF_MSB                 19
++#define BANK1_CONFIG_HOLDOFF_LSB                 16
++#define BANK1_CONFIG_HOLDOFF_MASK                0x000f0000
++#define BANK1_CONFIG_HOLDOFF_GET(x)              (((x) & BANK1_CONFIG_HOLDOFF_MASK) >> BANK1_CONFIG_HOLDOFF_LSB)
++#define BANK1_CONFIG_HOLDOFF_SET(x)              (((x) << BANK1_CONFIG_HOLDOFF_LSB) & BANK1_CONFIG_HOLDOFF_MASK)
++#define BANK1_CONFIG_TIMER3_MSB                  15
++#define BANK1_CONFIG_TIMER3_LSB                  12
++#define BANK1_CONFIG_TIMER3_MASK                 0x0000f000
++#define BANK1_CONFIG_TIMER3_GET(x)               (((x) & BANK1_CONFIG_TIMER3_MASK) >> BANK1_CONFIG_TIMER3_LSB)
++#define BANK1_CONFIG_TIMER3_SET(x)               (((x) << BANK1_CONFIG_TIMER3_LSB) & BANK1_CONFIG_TIMER3_MASK)
++#define BANK1_CONFIG_TIMER2_MSB                  11
++#define BANK1_CONFIG_TIMER2_LSB                  8
++#define BANK1_CONFIG_TIMER2_MASK                 0x00000f00
++#define BANK1_CONFIG_TIMER2_GET(x)               (((x) & BANK1_CONFIG_TIMER2_MASK) >> BANK1_CONFIG_TIMER2_LSB)
++#define BANK1_CONFIG_TIMER2_SET(x)               (((x) << BANK1_CONFIG_TIMER2_LSB) & BANK1_CONFIG_TIMER2_MASK)
++#define BANK1_CONFIG_TIMER1_MSB                  7
++#define BANK1_CONFIG_TIMER1_LSB                  4
++#define BANK1_CONFIG_TIMER1_MASK                 0x000000f0
++#define BANK1_CONFIG_TIMER1_GET(x)               (((x) & BANK1_CONFIG_TIMER1_MASK) >> BANK1_CONFIG_TIMER1_LSB)
++#define BANK1_CONFIG_TIMER1_SET(x)               (((x) << BANK1_CONFIG_TIMER1_LSB) & BANK1_CONFIG_TIMER1_MASK)
++#define BANK1_CONFIG_TIMER0_MSB                  3
++#define BANK1_CONFIG_TIMER0_LSB                  0
++#define BANK1_CONFIG_TIMER0_MASK                 0x0000000f
++#define BANK1_CONFIG_TIMER0_GET(x)               (((x) & BANK1_CONFIG_TIMER0_MASK) >> BANK1_CONFIG_TIMER0_LSB)
++#define BANK1_CONFIG_TIMER0_SET(x)               (((x) << BANK1_CONFIG_TIMER0_LSB) & BANK1_CONFIG_TIMER0_MASK)
++
++#define BANK1_READ_ADDRESS                       0x0c004018
++#define BANK1_READ_OFFSET                        0x00000018
++#define BANK1_READ_ENABLE_WAIT_MSB               31
++#define BANK1_READ_ENABLE_WAIT_LSB               31
++#define BANK1_READ_ENABLE_WAIT_MASK              0x80000000
++#define BANK1_READ_ENABLE_WAIT_GET(x)            (((x) & BANK1_READ_ENABLE_WAIT_MASK) >> BANK1_READ_ENABLE_WAIT_LSB)
++#define BANK1_READ_ENABLE_WAIT_SET(x)            (((x) << BANK1_READ_ENABLE_WAIT_LSB) & BANK1_READ_ENABLE_WAIT_MASK)
++#define BANK1_READ_WAIT_EVENT_MSB                30
++#define BANK1_READ_WAIT_EVENT_LSB                28
++#define BANK1_READ_WAIT_EVENT_MASK               0x70000000
++#define BANK1_READ_WAIT_EVENT_GET(x)             (((x) & BANK1_READ_WAIT_EVENT_MASK) >> BANK1_READ_WAIT_EVENT_LSB)
++#define BANK1_READ_WAIT_EVENT_SET(x)             (((x) << BANK1_READ_WAIT_EVENT_LSB) & BANK1_READ_WAIT_EVENT_MASK)
++#define BANK1_READ_END_EVENT_MSB                 26
++#define BANK1_READ_END_EVENT_LSB                 24
++#define BANK1_READ_END_EVENT_MASK                0x07000000
++#define BANK1_READ_END_EVENT_GET(x)              (((x) & BANK1_READ_END_EVENT_MASK) >> BANK1_READ_END_EVENT_LSB)
++#define BANK1_READ_END_EVENT_SET(x)              (((x) << BANK1_READ_END_EVENT_LSB) & BANK1_READ_END_EVENT_MASK)
++#define BANK1_READ_BURST_END_EVENT_MSB           22
++#define BANK1_READ_BURST_END_EVENT_LSB           20
++#define BANK1_READ_BURST_END_EVENT_MASK          0x00700000
++#define BANK1_READ_BURST_END_EVENT_GET(x)        (((x) & BANK1_READ_BURST_END_EVENT_MASK) >> BANK1_READ_BURST_END_EVENT_LSB)
++#define BANK1_READ_BURST_END_EVENT_SET(x)        (((x) << BANK1_READ_BURST_END_EVENT_LSB) & BANK1_READ_BURST_END_EVENT_MASK)
++#define BANK1_READ_BURST_START_EVENT_MSB         18
++#define BANK1_READ_BURST_START_EVENT_LSB         16
++#define BANK1_READ_BURST_START_EVENT_MASK        0x00070000
++#define BANK1_READ_BURST_START_EVENT_GET(x)      (((x) & BANK1_READ_BURST_START_EVENT_MASK) >> BANK1_READ_BURST_START_EVENT_LSB)
++#define BANK1_READ_BURST_START_EVENT_SET(x)      (((x) << BANK1_READ_BURST_START_EVENT_LSB) & BANK1_READ_BURST_START_EVENT_MASK)
++#define BANK1_READ_EVENT3_DC_MSB                 15
++#define BANK1_READ_EVENT3_DC_LSB                 15
++#define BANK1_READ_EVENT3_DC_MASK                0x00008000
++#define BANK1_READ_EVENT3_DC_GET(x)              (((x) & BANK1_READ_EVENT3_DC_MASK) >> BANK1_READ_EVENT3_DC_LSB)
++#define BANK1_READ_EVENT3_DC_SET(x)              (((x) << BANK1_READ_EVENT3_DC_LSB) & BANK1_READ_EVENT3_DC_MASK)
++#define BANK1_READ_EVENT3_BE_MSB                 14
++#define BANK1_READ_EVENT3_BE_LSB                 14
++#define BANK1_READ_EVENT3_BE_MASK                0x00004000
++#define BANK1_READ_EVENT3_BE_GET(x)              (((x) & BANK1_READ_EVENT3_BE_MASK) >> BANK1_READ_EVENT3_BE_LSB)
++#define BANK1_READ_EVENT3_BE_SET(x)              (((x) << BANK1_READ_EVENT3_BE_LSB) & BANK1_READ_EVENT3_BE_MASK)
++#define BANK1_READ_EVENT3_OE_MSB                 13
++#define BANK1_READ_EVENT3_OE_LSB                 13
++#define BANK1_READ_EVENT3_OE_MASK                0x00002000
++#define BANK1_READ_EVENT3_OE_GET(x)              (((x) & BANK1_READ_EVENT3_OE_MASK) >> BANK1_READ_EVENT3_OE_LSB)
++#define BANK1_READ_EVENT3_OE_SET(x)              (((x) << BANK1_READ_EVENT3_OE_LSB) & BANK1_READ_EVENT3_OE_MASK)
++#define BANK1_READ_EVENT3_CS_MSB                 12
++#define BANK1_READ_EVENT3_CS_LSB                 12
++#define BANK1_READ_EVENT3_CS_MASK                0x00001000
++#define BANK1_READ_EVENT3_CS_GET(x)              (((x) & BANK1_READ_EVENT3_CS_MASK) >> BANK1_READ_EVENT3_CS_LSB)
++#define BANK1_READ_EVENT3_CS_SET(x)              (((x) << BANK1_READ_EVENT3_CS_LSB) & BANK1_READ_EVENT3_CS_MASK)
++#define BANK1_READ_EVENT2_DC_MSB                 11
++#define BANK1_READ_EVENT2_DC_LSB                 11
++#define BANK1_READ_EVENT2_DC_MASK                0x00000800
++#define BANK1_READ_EVENT2_DC_GET(x)              (((x) & BANK1_READ_EVENT2_DC_MASK) >> BANK1_READ_EVENT2_DC_LSB)
++#define BANK1_READ_EVENT2_DC_SET(x)              (((x) << BANK1_READ_EVENT2_DC_LSB) & BANK1_READ_EVENT2_DC_MASK)
++#define BANK1_READ_EVENT2_BE_MSB                 10
++#define BANK1_READ_EVENT2_BE_LSB                 10
++#define BANK1_READ_EVENT2_BE_MASK                0x00000400
++#define BANK1_READ_EVENT2_BE_GET(x)              (((x) & BANK1_READ_EVENT2_BE_MASK) >> BANK1_READ_EVENT2_BE_LSB)
++#define BANK1_READ_EVENT2_BE_SET(x)              (((x) << BANK1_READ_EVENT2_BE_LSB) & BANK1_READ_EVENT2_BE_MASK)
++#define BANK1_READ_EVENT2_OE_MSB                 9
++#define BANK1_READ_EVENT2_OE_LSB                 9
++#define BANK1_READ_EVENT2_OE_MASK                0x00000200
++#define BANK1_READ_EVENT2_OE_GET(x)              (((x) & BANK1_READ_EVENT2_OE_MASK) >> BANK1_READ_EVENT2_OE_LSB)
++#define BANK1_READ_EVENT2_OE_SET(x)              (((x) << BANK1_READ_EVENT2_OE_LSB) & BANK1_READ_EVENT2_OE_MASK)
++#define BANK1_READ_EVENT2_CS_MSB                 8
++#define BANK1_READ_EVENT2_CS_LSB                 8
++#define BANK1_READ_EVENT2_CS_MASK                0x00000100
++#define BANK1_READ_EVENT2_CS_GET(x)              (((x) & BANK1_READ_EVENT2_CS_MASK) >> BANK1_READ_EVENT2_CS_LSB)
++#define BANK1_READ_EVENT2_CS_SET(x)              (((x) << BANK1_READ_EVENT2_CS_LSB) & BANK1_READ_EVENT2_CS_MASK)
++#define BANK1_READ_EVENT1_DC_MSB                 7
++#define BANK1_READ_EVENT1_DC_LSB                 7
++#define BANK1_READ_EVENT1_DC_MASK                0x00000080
++#define BANK1_READ_EVENT1_DC_GET(x)              (((x) & BANK1_READ_EVENT1_DC_MASK) >> BANK1_READ_EVENT1_DC_LSB)
++#define BANK1_READ_EVENT1_DC_SET(x)              (((x) << BANK1_READ_EVENT1_DC_LSB) & BANK1_READ_EVENT1_DC_MASK)
++#define BANK1_READ_EVENT1_BE_MSB                 6
++#define BANK1_READ_EVENT1_BE_LSB                 6
++#define BANK1_READ_EVENT1_BE_MASK                0x00000040
++#define BANK1_READ_EVENT1_BE_GET(x)              (((x) & BANK1_READ_EVENT1_BE_MASK) >> BANK1_READ_EVENT1_BE_LSB)
++#define BANK1_READ_EVENT1_BE_SET(x)              (((x) << BANK1_READ_EVENT1_BE_LSB) & BANK1_READ_EVENT1_BE_MASK)
++#define BANK1_READ_EVENT1_OE_MSB                 5
++#define BANK1_READ_EVENT1_OE_LSB                 5
++#define BANK1_READ_EVENT1_OE_MASK                0x00000020
++#define BANK1_READ_EVENT1_OE_GET(x)              (((x) & BANK1_READ_EVENT1_OE_MASK) >> BANK1_READ_EVENT1_OE_LSB)
++#define BANK1_READ_EVENT1_OE_SET(x)              (((x) << BANK1_READ_EVENT1_OE_LSB) & BANK1_READ_EVENT1_OE_MASK)
++#define BANK1_READ_EVENT1_CS_MSB                 4
++#define BANK1_READ_EVENT1_CS_LSB                 4
++#define BANK1_READ_EVENT1_CS_MASK                0x00000010
++#define BANK1_READ_EVENT1_CS_GET(x)              (((x) & BANK1_READ_EVENT1_CS_MASK) >> BANK1_READ_EVENT1_CS_LSB)
++#define BANK1_READ_EVENT1_CS_SET(x)              (((x) << BANK1_READ_EVENT1_CS_LSB) & BANK1_READ_EVENT1_CS_MASK)
++#define BANK1_READ_EVENT0_DC_MSB                 3
++#define BANK1_READ_EVENT0_DC_LSB                 3
++#define BANK1_READ_EVENT0_DC_MASK                0x00000008
++#define BANK1_READ_EVENT0_DC_GET(x)              (((x) & BANK1_READ_EVENT0_DC_MASK) >> BANK1_READ_EVENT0_DC_LSB)
++#define BANK1_READ_EVENT0_DC_SET(x)              (((x) << BANK1_READ_EVENT0_DC_LSB) & BANK1_READ_EVENT0_DC_MASK)
++#define BANK1_READ_EVENT0_BE_MSB                 2
++#define BANK1_READ_EVENT0_BE_LSB                 2
++#define BANK1_READ_EVENT0_BE_MASK                0x00000004
++#define BANK1_READ_EVENT0_BE_GET(x)              (((x) & BANK1_READ_EVENT0_BE_MASK) >> BANK1_READ_EVENT0_BE_LSB)
++#define BANK1_READ_EVENT0_BE_SET(x)              (((x) << BANK1_READ_EVENT0_BE_LSB) & BANK1_READ_EVENT0_BE_MASK)
++#define BANK1_READ_EVENT0_OE_MSB                 1
++#define BANK1_READ_EVENT0_OE_LSB                 1
++#define BANK1_READ_EVENT0_OE_MASK                0x00000002
++#define BANK1_READ_EVENT0_OE_GET(x)              (((x) & BANK1_READ_EVENT0_OE_MASK) >> BANK1_READ_EVENT0_OE_LSB)
++#define BANK1_READ_EVENT0_OE_SET(x)              (((x) << BANK1_READ_EVENT0_OE_LSB) & BANK1_READ_EVENT0_OE_MASK)
++#define BANK1_READ_EVENT0_CS_MSB                 0
++#define BANK1_READ_EVENT0_CS_LSB                 0
++#define BANK1_READ_EVENT0_CS_MASK                0x00000001
++#define BANK1_READ_EVENT0_CS_GET(x)              (((x) & BANK1_READ_EVENT0_CS_MASK) >> BANK1_READ_EVENT0_CS_LSB)
++#define BANK1_READ_EVENT0_CS_SET(x)              (((x) << BANK1_READ_EVENT0_CS_LSB) & BANK1_READ_EVENT0_CS_MASK)
++
++#define BANK1_WRITE_ADDRESS                      0x0c00401c
++#define BANK1_WRITE_OFFSET                       0x0000001c
++#define BANK1_WRITE_ENABLE_WAIT_MSB              31
++#define BANK1_WRITE_ENABLE_WAIT_LSB              31
++#define BANK1_WRITE_ENABLE_WAIT_MASK             0x80000000
++#define BANK1_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK1_WRITE_ENABLE_WAIT_MASK) >> BANK1_WRITE_ENABLE_WAIT_LSB)
++#define BANK1_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK1_WRITE_ENABLE_WAIT_LSB) & BANK1_WRITE_ENABLE_WAIT_MASK)
++#define BANK1_WRITE_WAIT_EVENT_MSB               30
++#define BANK1_WRITE_WAIT_EVENT_LSB               28
++#define BANK1_WRITE_WAIT_EVENT_MASK              0x70000000
++#define BANK1_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK1_WRITE_WAIT_EVENT_MASK) >> BANK1_WRITE_WAIT_EVENT_LSB)
++#define BANK1_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK1_WRITE_WAIT_EVENT_LSB) & BANK1_WRITE_WAIT_EVENT_MASK)
++#define BANK1_WRITE_END_EVENT_MSB                26
++#define BANK1_WRITE_END_EVENT_LSB                24
++#define BANK1_WRITE_END_EVENT_MASK               0x07000000
++#define BANK1_WRITE_END_EVENT_GET(x)             (((x) & BANK1_WRITE_END_EVENT_MASK) >> BANK1_WRITE_END_EVENT_LSB)
++#define BANK1_WRITE_END_EVENT_SET(x)             (((x) << BANK1_WRITE_END_EVENT_LSB) & BANK1_WRITE_END_EVENT_MASK)
++#define BANK1_WRITE_BURST_END_EVENT_MSB          22
++#define BANK1_WRITE_BURST_END_EVENT_LSB          20
++#define BANK1_WRITE_BURST_END_EVENT_MASK         0x00700000
++#define BANK1_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK1_WRITE_BURST_END_EVENT_MASK) >> BANK1_WRITE_BURST_END_EVENT_LSB)
++#define BANK1_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK1_WRITE_BURST_END_EVENT_LSB) & BANK1_WRITE_BURST_END_EVENT_MASK)
++#define BANK1_WRITE_BURST_START_EVENT_MSB        18
++#define BANK1_WRITE_BURST_START_EVENT_LSB        16
++#define BANK1_WRITE_BURST_START_EVENT_MASK       0x00070000
++#define BANK1_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK1_WRITE_BURST_START_EVENT_MASK) >> BANK1_WRITE_BURST_START_EVENT_LSB)
++#define BANK1_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK1_WRITE_BURST_START_EVENT_LSB) & BANK1_WRITE_BURST_START_EVENT_MASK)
++#define BANK1_WRITE_EVENT3_BE_MSB                14
++#define BANK1_WRITE_EVENT3_BE_LSB                14
++#define BANK1_WRITE_EVENT3_BE_MASK               0x00004000
++#define BANK1_WRITE_EVENT3_BE_GET(x)             (((x) & BANK1_WRITE_EVENT3_BE_MASK) >> BANK1_WRITE_EVENT3_BE_LSB)
++#define BANK1_WRITE_EVENT3_BE_SET(x)             (((x) << BANK1_WRITE_EVENT3_BE_LSB) & BANK1_WRITE_EVENT3_BE_MASK)
++#define BANK1_WRITE_EVENT3_WE_MSB                13
++#define BANK1_WRITE_EVENT3_WE_LSB                13
++#define BANK1_WRITE_EVENT3_WE_MASK               0x00002000
++#define BANK1_WRITE_EVENT3_WE_GET(x)             (((x) & BANK1_WRITE_EVENT3_WE_MASK) >> BANK1_WRITE_EVENT3_WE_LSB)
++#define BANK1_WRITE_EVENT3_WE_SET(x)             (((x) << BANK1_WRITE_EVENT3_WE_LSB) & BANK1_WRITE_EVENT3_WE_MASK)
++#define BANK1_WRITE_EVENT3_CS_MSB                12
++#define BANK1_WRITE_EVENT3_CS_LSB                12
++#define BANK1_WRITE_EVENT3_CS_MASK               0x00001000
++#define BANK1_WRITE_EVENT3_CS_GET(x)             (((x) & BANK1_WRITE_EVENT3_CS_MASK) >> BANK1_WRITE_EVENT3_CS_LSB)
++#define BANK1_WRITE_EVENT3_CS_SET(x)             (((x) << BANK1_WRITE_EVENT3_CS_LSB) & BANK1_WRITE_EVENT3_CS_MASK)
++#define BANK1_WRITE_EVENT2_BE_MSB                10
++#define BANK1_WRITE_EVENT2_BE_LSB                10
++#define BANK1_WRITE_EVENT2_BE_MASK               0x00000400
++#define BANK1_WRITE_EVENT2_BE_GET(x)             (((x) & BANK1_WRITE_EVENT2_BE_MASK) >> BANK1_WRITE_EVENT2_BE_LSB)
++#define BANK1_WRITE_EVENT2_BE_SET(x)             (((x) << BANK1_WRITE_EVENT2_BE_LSB) & BANK1_WRITE_EVENT2_BE_MASK)
++#define BANK1_WRITE_EVENT2_WE_MSB                9
++#define BANK1_WRITE_EVENT2_WE_LSB                9
++#define BANK1_WRITE_EVENT2_WE_MASK               0x00000200
++#define BANK1_WRITE_EVENT2_WE_GET(x)             (((x) & BANK1_WRITE_EVENT2_WE_MASK) >> BANK1_WRITE_EVENT2_WE_LSB)
++#define BANK1_WRITE_EVENT2_WE_SET(x)             (((x) << BANK1_WRITE_EVENT2_WE_LSB) & BANK1_WRITE_EVENT2_WE_MASK)
++#define BANK1_WRITE_EVENT2_CS_MSB                8
++#define BANK1_WRITE_EVENT2_CS_LSB                8
++#define BANK1_WRITE_EVENT2_CS_MASK               0x00000100
++#define BANK1_WRITE_EVENT2_CS_GET(x)             (((x) & BANK1_WRITE_EVENT2_CS_MASK) >> BANK1_WRITE_EVENT2_CS_LSB)
++#define BANK1_WRITE_EVENT2_CS_SET(x)             (((x) << BANK1_WRITE_EVENT2_CS_LSB) & BANK1_WRITE_EVENT2_CS_MASK)
++#define BANK1_WRITE_EVENT1_BE_MSB                6
++#define BANK1_WRITE_EVENT1_BE_LSB                6
++#define BANK1_WRITE_EVENT1_BE_MASK               0x00000040
++#define BANK1_WRITE_EVENT1_BE_GET(x)             (((x) & BANK1_WRITE_EVENT1_BE_MASK) >> BANK1_WRITE_EVENT1_BE_LSB)
++#define BANK1_WRITE_EVENT1_BE_SET(x)             (((x) << BANK1_WRITE_EVENT1_BE_LSB) & BANK1_WRITE_EVENT1_BE_MASK)
++#define BANK1_WRITE_EVENT1_WE_MSB                5
++#define BANK1_WRITE_EVENT1_WE_LSB                5
++#define BANK1_WRITE_EVENT1_WE_MASK               0x00000020
++#define BANK1_WRITE_EVENT1_WE_GET(x)             (((x) & BANK1_WRITE_EVENT1_WE_MASK) >> BANK1_WRITE_EVENT1_WE_LSB)
++#define BANK1_WRITE_EVENT1_WE_SET(x)             (((x) << BANK1_WRITE_EVENT1_WE_LSB) & BANK1_WRITE_EVENT1_WE_MASK)
++#define BANK1_WRITE_EVENT1_CS_MSB                4
++#define BANK1_WRITE_EVENT1_CS_LSB                4
++#define BANK1_WRITE_EVENT1_CS_MASK               0x00000010
++#define BANK1_WRITE_EVENT1_CS_GET(x)             (((x) & BANK1_WRITE_EVENT1_CS_MASK) >> BANK1_WRITE_EVENT1_CS_LSB)
++#define BANK1_WRITE_EVENT1_CS_SET(x)             (((x) << BANK1_WRITE_EVENT1_CS_LSB) & BANK1_WRITE_EVENT1_CS_MASK)
++#define BANK1_WRITE_EVENT0_BE_MSB                2
++#define BANK1_WRITE_EVENT0_BE_LSB                2
++#define BANK1_WRITE_EVENT0_BE_MASK               0x00000004
++#define BANK1_WRITE_EVENT0_BE_GET(x)             (((x) & BANK1_WRITE_EVENT0_BE_MASK) >> BANK1_WRITE_EVENT0_BE_LSB)
++#define BANK1_WRITE_EVENT0_BE_SET(x)             (((x) << BANK1_WRITE_EVENT0_BE_LSB) & BANK1_WRITE_EVENT0_BE_MASK)
++#define BANK1_WRITE_EVENT0_WE_MSB                1
++#define BANK1_WRITE_EVENT0_WE_LSB                1
++#define BANK1_WRITE_EVENT0_WE_MASK               0x00000002
++#define BANK1_WRITE_EVENT0_WE_GET(x)             (((x) & BANK1_WRITE_EVENT0_WE_MASK) >> BANK1_WRITE_EVENT0_WE_LSB)
++#define BANK1_WRITE_EVENT0_WE_SET(x)             (((x) << BANK1_WRITE_EVENT0_WE_LSB) & BANK1_WRITE_EVENT0_WE_MASK)
++#define BANK1_WRITE_EVENT0_CS_MSB                0
++#define BANK1_WRITE_EVENT0_CS_LSB                0
++#define BANK1_WRITE_EVENT0_CS_MASK               0x00000001
++#define BANK1_WRITE_EVENT0_CS_GET(x)             (((x) & BANK1_WRITE_EVENT0_CS_MASK) >> BANK1_WRITE_EVENT0_CS_LSB)
++#define BANK1_WRITE_EVENT0_CS_SET(x)             (((x) << BANK1_WRITE_EVENT0_CS_LSB) & BANK1_WRITE_EVENT0_CS_MASK)
++
++#define BANK2_ADDR_ADDRESS                       0x0c004020
++#define BANK2_ADDR_OFFSET                        0x00000020
++#define BANK2_ADDR_SIZE_MSB                      31
++#define BANK2_ADDR_SIZE_LSB                      28
++#define BANK2_ADDR_SIZE_MASK                     0xf0000000
++#define BANK2_ADDR_SIZE_GET(x)                   (((x) & BANK2_ADDR_SIZE_MASK) >> BANK2_ADDR_SIZE_LSB)
++#define BANK2_ADDR_SIZE_SET(x)                   (((x) << BANK2_ADDR_SIZE_LSB) & BANK2_ADDR_SIZE_MASK)
++#define BANK2_ADDR_BASE_MSB                      27
++#define BANK2_ADDR_BASE_LSB                      10
++#define BANK2_ADDR_BASE_MASK                     0x0ffffc00
++#define BANK2_ADDR_BASE_GET(x)                   (((x) & BANK2_ADDR_BASE_MASK) >> BANK2_ADDR_BASE_LSB)
++#define BANK2_ADDR_BASE_SET(x)                   (((x) << BANK2_ADDR_BASE_LSB) & BANK2_ADDR_BASE_MASK)
++
++#define BANK2_CONFIG_ADDRESS                     0x0c004024
++#define BANK2_CONFIG_OFFSET                      0x00000024
++#define BANK2_CONFIG_ENABLE_MSB                  31
++#define BANK2_CONFIG_ENABLE_LSB                  31
++#define BANK2_CONFIG_ENABLE_MASK                 0x80000000
++#define BANK2_CONFIG_ENABLE_GET(x)               (((x) & BANK2_CONFIG_ENABLE_MASK) >> BANK2_CONFIG_ENABLE_LSB)
++#define BANK2_CONFIG_ENABLE_SET(x)               (((x) << BANK2_CONFIG_ENABLE_LSB) & BANK2_CONFIG_ENABLE_MASK)
++#define BANK2_CONFIG_WIDTH_MSB                   28
++#define BANK2_CONFIG_WIDTH_LSB                   28
++#define BANK2_CONFIG_WIDTH_MASK                  0x10000000
++#define BANK2_CONFIG_WIDTH_GET(x)                (((x) & BANK2_CONFIG_WIDTH_MASK) >> BANK2_CONFIG_WIDTH_LSB)
++#define BANK2_CONFIG_WIDTH_SET(x)                (((x) << BANK2_CONFIG_WIDTH_LSB) & BANK2_CONFIG_WIDTH_MASK)
++#define BANK2_CONFIG_PROTECT_MSB                 26
++#define BANK2_CONFIG_PROTECT_LSB                 26
++#define BANK2_CONFIG_PROTECT_MASK                0x04000000
++#define BANK2_CONFIG_PROTECT_GET(x)              (((x) & BANK2_CONFIG_PROTECT_MASK) >> BANK2_CONFIG_PROTECT_LSB)
++#define BANK2_CONFIG_PROTECT_SET(x)              (((x) << BANK2_CONFIG_PROTECT_LSB) & BANK2_CONFIG_PROTECT_MASK)
++#define BANK2_CONFIG_WB_ENABLE_MSB               25
++#define BANK2_CONFIG_WB_ENABLE_LSB               25
++#define BANK2_CONFIG_WB_ENABLE_MASK              0x02000000
++#define BANK2_CONFIG_WB_ENABLE_GET(x)            (((x) & BANK2_CONFIG_WB_ENABLE_MASK) >> BANK2_CONFIG_WB_ENABLE_LSB)
++#define BANK2_CONFIG_WB_ENABLE_SET(x)            (((x) << BANK2_CONFIG_WB_ENABLE_LSB) & BANK2_CONFIG_WB_ENABLE_MASK)
++#define BANK2_CONFIG_WB_FLUSH_MSB                24
++#define BANK2_CONFIG_WB_FLUSH_LSB                24
++#define BANK2_CONFIG_WB_FLUSH_MASK               0x01000000
++#define BANK2_CONFIG_WB_FLUSH_GET(x)             (((x) & BANK2_CONFIG_WB_FLUSH_MASK) >> BANK2_CONFIG_WB_FLUSH_LSB)
++#define BANK2_CONFIG_WB_FLUSH_SET(x)             (((x) << BANK2_CONFIG_WB_FLUSH_LSB) & BANK2_CONFIG_WB_FLUSH_MASK)
++#define BANK2_CONFIG_SCALE_MSB                   21
++#define BANK2_CONFIG_SCALE_LSB                   20
++#define BANK2_CONFIG_SCALE_MASK                  0x00300000
++#define BANK2_CONFIG_SCALE_GET(x)                (((x) & BANK2_CONFIG_SCALE_MASK) >> BANK2_CONFIG_SCALE_LSB)
++#define BANK2_CONFIG_SCALE_SET(x)                (((x) << BANK2_CONFIG_SCALE_LSB) & BANK2_CONFIG_SCALE_MASK)
++#define BANK2_CONFIG_HOLDOFF_MSB                 19
++#define BANK2_CONFIG_HOLDOFF_LSB                 16
++#define BANK2_CONFIG_HOLDOFF_MASK                0x000f0000
++#define BANK2_CONFIG_HOLDOFF_GET(x)              (((x) & BANK2_CONFIG_HOLDOFF_MASK) >> BANK2_CONFIG_HOLDOFF_LSB)
++#define BANK2_CONFIG_HOLDOFF_SET(x)              (((x) << BANK2_CONFIG_HOLDOFF_LSB) & BANK2_CONFIG_HOLDOFF_MASK)
++#define BANK2_CONFIG_TIMER3_MSB                  15
++#define BANK2_CONFIG_TIMER3_LSB                  12
++#define BANK2_CONFIG_TIMER3_MASK                 0x0000f000
++#define BANK2_CONFIG_TIMER3_GET(x)               (((x) & BANK2_CONFIG_TIMER3_MASK) >> BANK2_CONFIG_TIMER3_LSB)
++#define BANK2_CONFIG_TIMER3_SET(x)               (((x) << BANK2_CONFIG_TIMER3_LSB) & BANK2_CONFIG_TIMER3_MASK)
++#define BANK2_CONFIG_TIMER2_MSB                  11
++#define BANK2_CONFIG_TIMER2_LSB                  8
++#define BANK2_CONFIG_TIMER2_MASK                 0x00000f00
++#define BANK2_CONFIG_TIMER2_GET(x)               (((x) & BANK2_CONFIG_TIMER2_MASK) >> BANK2_CONFIG_TIMER2_LSB)
++#define BANK2_CONFIG_TIMER2_SET(x)               (((x) << BANK2_CONFIG_TIMER2_LSB) & BANK2_CONFIG_TIMER2_MASK)
++#define BANK2_CONFIG_TIMER1_MSB                  7
++#define BANK2_CONFIG_TIMER1_LSB                  4
++#define BANK2_CONFIG_TIMER1_MASK                 0x000000f0
++#define BANK2_CONFIG_TIMER1_GET(x)               (((x) & BANK2_CONFIG_TIMER1_MASK) >> BANK2_CONFIG_TIMER1_LSB)
++#define BANK2_CONFIG_TIMER1_SET(x)               (((x) << BANK2_CONFIG_TIMER1_LSB) & BANK2_CONFIG_TIMER1_MASK)
++#define BANK2_CONFIG_TIMER0_MSB                  3
++#define BANK2_CONFIG_TIMER0_LSB                  0
++#define BANK2_CONFIG_TIMER0_MASK                 0x0000000f
++#define BANK2_CONFIG_TIMER0_GET(x)               (((x) & BANK2_CONFIG_TIMER0_MASK) >> BANK2_CONFIG_TIMER0_LSB)
++#define BANK2_CONFIG_TIMER0_SET(x)               (((x) << BANK2_CONFIG_TIMER0_LSB) & BANK2_CONFIG_TIMER0_MASK)
++
++#define BANK2_READ_ADDRESS                       0x0c004028
++#define BANK2_READ_OFFSET                        0x00000028
++#define BANK2_READ_ENABLE_WAIT_MSB               31
++#define BANK2_READ_ENABLE_WAIT_LSB               31
++#define BANK2_READ_ENABLE_WAIT_MASK              0x80000000
++#define BANK2_READ_ENABLE_WAIT_GET(x)            (((x) & BANK2_READ_ENABLE_WAIT_MASK) >> BANK2_READ_ENABLE_WAIT_LSB)
++#define BANK2_READ_ENABLE_WAIT_SET(x)            (((x) << BANK2_READ_ENABLE_WAIT_LSB) & BANK2_READ_ENABLE_WAIT_MASK)
++#define BANK2_READ_WAIT_EVENT_MSB                30
++#define BANK2_READ_WAIT_EVENT_LSB                28
++#define BANK2_READ_WAIT_EVENT_MASK               0x70000000
++#define BANK2_READ_WAIT_EVENT_GET(x)             (((x) & BANK2_READ_WAIT_EVENT_MASK) >> BANK2_READ_WAIT_EVENT_LSB)
++#define BANK2_READ_WAIT_EVENT_SET(x)             (((x) << BANK2_READ_WAIT_EVENT_LSB) & BANK2_READ_WAIT_EVENT_MASK)
++#define BANK2_READ_END_EVENT_MSB                 26
++#define BANK2_READ_END_EVENT_LSB                 24
++#define BANK2_READ_END_EVENT_MASK                0x07000000
++#define BANK2_READ_END_EVENT_GET(x)              (((x) & BANK2_READ_END_EVENT_MASK) >> BANK2_READ_END_EVENT_LSB)
++#define BANK2_READ_END_EVENT_SET(x)              (((x) << BANK2_READ_END_EVENT_LSB) & BANK2_READ_END_EVENT_MASK)
++#define BANK2_READ_BURST_END_EVENT_MSB           22
++#define BANK2_READ_BURST_END_EVENT_LSB           20
++#define BANK2_READ_BURST_END_EVENT_MASK          0x00700000
++#define BANK2_READ_BURST_END_EVENT_GET(x)        (((x) & BANK2_READ_BURST_END_EVENT_MASK) >> BANK2_READ_BURST_END_EVENT_LSB)
++#define BANK2_READ_BURST_END_EVENT_SET(x)        (((x) << BANK2_READ_BURST_END_EVENT_LSB) & BANK2_READ_BURST_END_EVENT_MASK)
++#define BANK2_READ_BURST_START_EVENT_MSB         18
++#define BANK2_READ_BURST_START_EVENT_LSB         16
++#define BANK2_READ_BURST_START_EVENT_MASK        0x00070000
++#define BANK2_READ_BURST_START_EVENT_GET(x)      (((x) & BANK2_READ_BURST_START_EVENT_MASK) >> BANK2_READ_BURST_START_EVENT_LSB)
++#define BANK2_READ_BURST_START_EVENT_SET(x)      (((x) << BANK2_READ_BURST_START_EVENT_LSB) & BANK2_READ_BURST_START_EVENT_MASK)
++#define BANK2_READ_EVENT3_DC_MSB                 15
++#define BANK2_READ_EVENT3_DC_LSB                 15
++#define BANK2_READ_EVENT3_DC_MASK                0x00008000
++#define BANK2_READ_EVENT3_DC_GET(x)              (((x) & BANK2_READ_EVENT3_DC_MASK) >> BANK2_READ_EVENT3_DC_LSB)
++#define BANK2_READ_EVENT3_DC_SET(x)              (((x) << BANK2_READ_EVENT3_DC_LSB) & BANK2_READ_EVENT3_DC_MASK)
++#define BANK2_READ_EVENT3_BE_MSB                 14
++#define BANK2_READ_EVENT3_BE_LSB                 14
++#define BANK2_READ_EVENT3_BE_MASK                0x00004000
++#define BANK2_READ_EVENT3_BE_GET(x)              (((x) & BANK2_READ_EVENT3_BE_MASK) >> BANK2_READ_EVENT3_BE_LSB)
++#define BANK2_READ_EVENT3_BE_SET(x)              (((x) << BANK2_READ_EVENT3_BE_LSB) & BANK2_READ_EVENT3_BE_MASK)
++#define BANK2_READ_EVENT3_OE_MSB                 13
++#define BANK2_READ_EVENT3_OE_LSB                 13
++#define BANK2_READ_EVENT3_OE_MASK                0x00002000
++#define BANK2_READ_EVENT3_OE_GET(x)              (((x) & BANK2_READ_EVENT3_OE_MASK) >> BANK2_READ_EVENT3_OE_LSB)
++#define BANK2_READ_EVENT3_OE_SET(x)              (((x) << BANK2_READ_EVENT3_OE_LSB) & BANK2_READ_EVENT3_OE_MASK)
++#define BANK2_READ_EVENT3_CS_MSB                 12
++#define BANK2_READ_EVENT3_CS_LSB                 12
++#define BANK2_READ_EVENT3_CS_MASK                0x00001000
++#define BANK2_READ_EVENT3_CS_GET(x)              (((x) & BANK2_READ_EVENT3_CS_MASK) >> BANK2_READ_EVENT3_CS_LSB)
++#define BANK2_READ_EVENT3_CS_SET(x)              (((x) << BANK2_READ_EVENT3_CS_LSB) & BANK2_READ_EVENT3_CS_MASK)
++#define BANK2_READ_EVENT2_DC_MSB                 11
++#define BANK2_READ_EVENT2_DC_LSB                 11
++#define BANK2_READ_EVENT2_DC_MASK                0x00000800
++#define BANK2_READ_EVENT2_DC_GET(x)              (((x) & BANK2_READ_EVENT2_DC_MASK) >> BANK2_READ_EVENT2_DC_LSB)
++#define BANK2_READ_EVENT2_DC_SET(x)              (((x) << BANK2_READ_EVENT2_DC_LSB) & BANK2_READ_EVENT2_DC_MASK)
++#define BANK2_READ_EVENT2_BE_MSB                 10
++#define BANK2_READ_EVENT2_BE_LSB                 10
++#define BANK2_READ_EVENT2_BE_MASK                0x00000400
++#define BANK2_READ_EVENT2_BE_GET(x)              (((x) & BANK2_READ_EVENT2_BE_MASK) >> BANK2_READ_EVENT2_BE_LSB)
++#define BANK2_READ_EVENT2_BE_SET(x)              (((x) << BANK2_READ_EVENT2_BE_LSB) & BANK2_READ_EVENT2_BE_MASK)
++#define BANK2_READ_EVENT2_OE_MSB                 9
++#define BANK2_READ_EVENT2_OE_LSB                 9
++#define BANK2_READ_EVENT2_OE_MASK                0x00000200
++#define BANK2_READ_EVENT2_OE_GET(x)              (((x) & BANK2_READ_EVENT2_OE_MASK) >> BANK2_READ_EVENT2_OE_LSB)
++#define BANK2_READ_EVENT2_OE_SET(x)              (((x) << BANK2_READ_EVENT2_OE_LSB) & BANK2_READ_EVENT2_OE_MASK)
++#define BANK2_READ_EVENT2_CS_MSB                 8
++#define BANK2_READ_EVENT2_CS_LSB                 8
++#define BANK2_READ_EVENT2_CS_MASK                0x00000100
++#define BANK2_READ_EVENT2_CS_GET(x)              (((x) & BANK2_READ_EVENT2_CS_MASK) >> BANK2_READ_EVENT2_CS_LSB)
++#define BANK2_READ_EVENT2_CS_SET(x)              (((x) << BANK2_READ_EVENT2_CS_LSB) & BANK2_READ_EVENT2_CS_MASK)
++#define BANK2_READ_EVENT1_DC_MSB                 7
++#define BANK2_READ_EVENT1_DC_LSB                 7
++#define BANK2_READ_EVENT1_DC_MASK                0x00000080
++#define BANK2_READ_EVENT1_DC_GET(x)              (((x) & BANK2_READ_EVENT1_DC_MASK) >> BANK2_READ_EVENT1_DC_LSB)
++#define BANK2_READ_EVENT1_DC_SET(x)              (((x) << BANK2_READ_EVENT1_DC_LSB) & BANK2_READ_EVENT1_DC_MASK)
++#define BANK2_READ_EVENT1_BE_MSB                 6
++#define BANK2_READ_EVENT1_BE_LSB                 6
++#define BANK2_READ_EVENT1_BE_MASK                0x00000040
++#define BANK2_READ_EVENT1_BE_GET(x)              (((x) & BANK2_READ_EVENT1_BE_MASK) >> BANK2_READ_EVENT1_BE_LSB)
++#define BANK2_READ_EVENT1_BE_SET(x)              (((x) << BANK2_READ_EVENT1_BE_LSB) & BANK2_READ_EVENT1_BE_MASK)
++#define BANK2_READ_EVENT1_OE_MSB                 5
++#define BANK2_READ_EVENT1_OE_LSB                 5
++#define BANK2_READ_EVENT1_OE_MASK                0x00000020
++#define BANK2_READ_EVENT1_OE_GET(x)              (((x) & BANK2_READ_EVENT1_OE_MASK) >> BANK2_READ_EVENT1_OE_LSB)
++#define BANK2_READ_EVENT1_OE_SET(x)              (((x) << BANK2_READ_EVENT1_OE_LSB) & BANK2_READ_EVENT1_OE_MASK)
++#define BANK2_READ_EVENT1_CS_MSB                 4
++#define BANK2_READ_EVENT1_CS_LSB                 4
++#define BANK2_READ_EVENT1_CS_MASK                0x00000010
++#define BANK2_READ_EVENT1_CS_GET(x)              (((x) & BANK2_READ_EVENT1_CS_MASK) >> BANK2_READ_EVENT1_CS_LSB)
++#define BANK2_READ_EVENT1_CS_SET(x)              (((x) << BANK2_READ_EVENT1_CS_LSB) & BANK2_READ_EVENT1_CS_MASK)
++#define BANK2_READ_EVENT0_DC_MSB                 3
++#define BANK2_READ_EVENT0_DC_LSB                 3
++#define BANK2_READ_EVENT0_DC_MASK                0x00000008
++#define BANK2_READ_EVENT0_DC_GET(x)              (((x) & BANK2_READ_EVENT0_DC_MASK) >> BANK2_READ_EVENT0_DC_LSB)
++#define BANK2_READ_EVENT0_DC_SET(x)              (((x) << BANK2_READ_EVENT0_DC_LSB) & BANK2_READ_EVENT0_DC_MASK)
++#define BANK2_READ_EVENT0_BE_MSB                 2
++#define BANK2_READ_EVENT0_BE_LSB                 2
++#define BANK2_READ_EVENT0_BE_MASK                0x00000004
++#define BANK2_READ_EVENT0_BE_GET(x)              (((x) & BANK2_READ_EVENT0_BE_MASK) >> BANK2_READ_EVENT0_BE_LSB)
++#define BANK2_READ_EVENT0_BE_SET(x)              (((x) << BANK2_READ_EVENT0_BE_LSB) & BANK2_READ_EVENT0_BE_MASK)
++#define BANK2_READ_EVENT0_OE_MSB                 1
++#define BANK2_READ_EVENT0_OE_LSB                 1
++#define BANK2_READ_EVENT0_OE_MASK                0x00000002
++#define BANK2_READ_EVENT0_OE_GET(x)              (((x) & BANK2_READ_EVENT0_OE_MASK) >> BANK2_READ_EVENT0_OE_LSB)
++#define BANK2_READ_EVENT0_OE_SET(x)              (((x) << BANK2_READ_EVENT0_OE_LSB) & BANK2_READ_EVENT0_OE_MASK)
++#define BANK2_READ_EVENT0_CS_MSB                 0
++#define BANK2_READ_EVENT0_CS_LSB                 0
++#define BANK2_READ_EVENT0_CS_MASK                0x00000001
++#define BANK2_READ_EVENT0_CS_GET(x)              (((x) & BANK2_READ_EVENT0_CS_MASK) >> BANK2_READ_EVENT0_CS_LSB)
++#define BANK2_READ_EVENT0_CS_SET(x)              (((x) << BANK2_READ_EVENT0_CS_LSB) & BANK2_READ_EVENT0_CS_MASK)
++
++#define BANK2_WRITE_ADDRESS                      0x0c00402c
++#define BANK2_WRITE_OFFSET                       0x0000002c
++#define BANK2_WRITE_ENABLE_WAIT_MSB              31
++#define BANK2_WRITE_ENABLE_WAIT_LSB              31
++#define BANK2_WRITE_ENABLE_WAIT_MASK             0x80000000
++#define BANK2_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK2_WRITE_ENABLE_WAIT_MASK) >> BANK2_WRITE_ENABLE_WAIT_LSB)
++#define BANK2_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK2_WRITE_ENABLE_WAIT_LSB) & BANK2_WRITE_ENABLE_WAIT_MASK)
++#define BANK2_WRITE_WAIT_EVENT_MSB               30
++#define BANK2_WRITE_WAIT_EVENT_LSB               28
++#define BANK2_WRITE_WAIT_EVENT_MASK              0x70000000
++#define BANK2_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK2_WRITE_WAIT_EVENT_MASK) >> BANK2_WRITE_WAIT_EVENT_LSB)
++#define BANK2_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK2_WRITE_WAIT_EVENT_LSB) & BANK2_WRITE_WAIT_EVENT_MASK)
++#define BANK2_WRITE_END_EVENT_MSB                26
++#define BANK2_WRITE_END_EVENT_LSB                24
++#define BANK2_WRITE_END_EVENT_MASK               0x07000000
++#define BANK2_WRITE_END_EVENT_GET(x)             (((x) & BANK2_WRITE_END_EVENT_MASK) >> BANK2_WRITE_END_EVENT_LSB)
++#define BANK2_WRITE_END_EVENT_SET(x)             (((x) << BANK2_WRITE_END_EVENT_LSB) & BANK2_WRITE_END_EVENT_MASK)
++#define BANK2_WRITE_BURST_END_EVENT_MSB          22
++#define BANK2_WRITE_BURST_END_EVENT_LSB          20
++#define BANK2_WRITE_BURST_END_EVENT_MASK         0x00700000
++#define BANK2_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK2_WRITE_BURST_END_EVENT_MASK) >> BANK2_WRITE_BURST_END_EVENT_LSB)
++#define BANK2_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK2_WRITE_BURST_END_EVENT_LSB) & BANK2_WRITE_BURST_END_EVENT_MASK)
++#define BANK2_WRITE_BURST_START_EVENT_MSB        18
++#define BANK2_WRITE_BURST_START_EVENT_LSB        16
++#define BANK2_WRITE_BURST_START_EVENT_MASK       0x00070000
++#define BANK2_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK2_WRITE_BURST_START_EVENT_MASK) >> BANK2_WRITE_BURST_START_EVENT_LSB)
++#define BANK2_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK2_WRITE_BURST_START_EVENT_LSB) & BANK2_WRITE_BURST_START_EVENT_MASK)
++#define BANK2_WRITE_EVENT3_BE_MSB                14
++#define BANK2_WRITE_EVENT3_BE_LSB                14
++#define BANK2_WRITE_EVENT3_BE_MASK               0x00004000
++#define BANK2_WRITE_EVENT3_BE_GET(x)             (((x) & BANK2_WRITE_EVENT3_BE_MASK) >> BANK2_WRITE_EVENT3_BE_LSB)
++#define BANK2_WRITE_EVENT3_BE_SET(x)             (((x) << BANK2_WRITE_EVENT3_BE_LSB) & BANK2_WRITE_EVENT3_BE_MASK)
++#define BANK2_WRITE_EVENT3_WE_MSB                13
++#define BANK2_WRITE_EVENT3_WE_LSB                13
++#define BANK2_WRITE_EVENT3_WE_MASK               0x00002000
++#define BANK2_WRITE_EVENT3_WE_GET(x)             (((x) & BANK2_WRITE_EVENT3_WE_MASK) >> BANK2_WRITE_EVENT3_WE_LSB)
++#define BANK2_WRITE_EVENT3_WE_SET(x)             (((x) << BANK2_WRITE_EVENT3_WE_LSB) & BANK2_WRITE_EVENT3_WE_MASK)
++#define BANK2_WRITE_EVENT3_CS_MSB                12
++#define BANK2_WRITE_EVENT3_CS_LSB                12
++#define BANK2_WRITE_EVENT3_CS_MASK               0x00001000
++#define BANK2_WRITE_EVENT3_CS_GET(x)             (((x) & BANK2_WRITE_EVENT3_CS_MASK) >> BANK2_WRITE_EVENT3_CS_LSB)
++#define BANK2_WRITE_EVENT3_CS_SET(x)             (((x) << BANK2_WRITE_EVENT3_CS_LSB) & BANK2_WRITE_EVENT3_CS_MASK)
++#define BANK2_WRITE_EVENT2_BE_MSB                10
++#define BANK2_WRITE_EVENT2_BE_LSB                10
++#define BANK2_WRITE_EVENT2_BE_MASK               0x00000400
++#define BANK2_WRITE_EVENT2_BE_GET(x)             (((x) & BANK2_WRITE_EVENT2_BE_MASK) >> BANK2_WRITE_EVENT2_BE_LSB)
++#define BANK2_WRITE_EVENT2_BE_SET(x)             (((x) << BANK2_WRITE_EVENT2_BE_LSB) & BANK2_WRITE_EVENT2_BE_MASK)
++#define BANK2_WRITE_EVENT2_WE_MSB                9
++#define BANK2_WRITE_EVENT2_WE_LSB                9
++#define BANK2_WRITE_EVENT2_WE_MASK               0x00000200
++#define BANK2_WRITE_EVENT2_WE_GET(x)             (((x) & BANK2_WRITE_EVENT2_WE_MASK) >> BANK2_WRITE_EVENT2_WE_LSB)
++#define BANK2_WRITE_EVENT2_WE_SET(x)             (((x) << BANK2_WRITE_EVENT2_WE_LSB) & BANK2_WRITE_EVENT2_WE_MASK)
++#define BANK2_WRITE_EVENT2_CS_MSB                8
++#define BANK2_WRITE_EVENT2_CS_LSB                8
++#define BANK2_WRITE_EVENT2_CS_MASK               0x00000100
++#define BANK2_WRITE_EVENT2_CS_GET(x)             (((x) & BANK2_WRITE_EVENT2_CS_MASK) >> BANK2_WRITE_EVENT2_CS_LSB)
++#define BANK2_WRITE_EVENT2_CS_SET(x)             (((x) << BANK2_WRITE_EVENT2_CS_LSB) & BANK2_WRITE_EVENT2_CS_MASK)
++#define BANK2_WRITE_EVENT1_BE_MSB                6
++#define BANK2_WRITE_EVENT1_BE_LSB                6
++#define BANK2_WRITE_EVENT1_BE_MASK               0x00000040
++#define BANK2_WRITE_EVENT1_BE_GET(x)             (((x) & BANK2_WRITE_EVENT1_BE_MASK) >> BANK2_WRITE_EVENT1_BE_LSB)
++#define BANK2_WRITE_EVENT1_BE_SET(x)             (((x) << BANK2_WRITE_EVENT1_BE_LSB) & BANK2_WRITE_EVENT1_BE_MASK)
++#define BANK2_WRITE_EVENT1_WE_MSB                5
++#define BANK2_WRITE_EVENT1_WE_LSB                5
++#define BANK2_WRITE_EVENT1_WE_MASK               0x00000020
++#define BANK2_WRITE_EVENT1_WE_GET(x)             (((x) & BANK2_WRITE_EVENT1_WE_MASK) >> BANK2_WRITE_EVENT1_WE_LSB)
++#define BANK2_WRITE_EVENT1_WE_SET(x)             (((x) << BANK2_WRITE_EVENT1_WE_LSB) & BANK2_WRITE_EVENT1_WE_MASK)
++#define BANK2_WRITE_EVENT1_CS_MSB                4
++#define BANK2_WRITE_EVENT1_CS_LSB                4
++#define BANK2_WRITE_EVENT1_CS_MASK               0x00000010
++#define BANK2_WRITE_EVENT1_CS_GET(x)             (((x) & BANK2_WRITE_EVENT1_CS_MASK) >> BANK2_WRITE_EVENT1_CS_LSB)
++#define BANK2_WRITE_EVENT1_CS_SET(x)             (((x) << BANK2_WRITE_EVENT1_CS_LSB) & BANK2_WRITE_EVENT1_CS_MASK)
++#define BANK2_WRITE_EVENT0_BE_MSB                2
++#define BANK2_WRITE_EVENT0_BE_LSB                2
++#define BANK2_WRITE_EVENT0_BE_MASK               0x00000004
++#define BANK2_WRITE_EVENT0_BE_GET(x)             (((x) & BANK2_WRITE_EVENT0_BE_MASK) >> BANK2_WRITE_EVENT0_BE_LSB)
++#define BANK2_WRITE_EVENT0_BE_SET(x)             (((x) << BANK2_WRITE_EVENT0_BE_LSB) & BANK2_WRITE_EVENT0_BE_MASK)
++#define BANK2_WRITE_EVENT0_WE_MSB                1
++#define BANK2_WRITE_EVENT0_WE_LSB                1
++#define BANK2_WRITE_EVENT0_WE_MASK               0x00000002
++#define BANK2_WRITE_EVENT0_WE_GET(x)             (((x) & BANK2_WRITE_EVENT0_WE_MASK) >> BANK2_WRITE_EVENT0_WE_LSB)
++#define BANK2_WRITE_EVENT0_WE_SET(x)             (((x) << BANK2_WRITE_EVENT0_WE_LSB) & BANK2_WRITE_EVENT0_WE_MASK)
++#define BANK2_WRITE_EVENT0_CS_MSB                0
++#define BANK2_WRITE_EVENT0_CS_LSB                0
++#define BANK2_WRITE_EVENT0_CS_MASK               0x00000001
++#define BANK2_WRITE_EVENT0_CS_GET(x)             (((x) & BANK2_WRITE_EVENT0_CS_MASK) >> BANK2_WRITE_EVENT0_CS_LSB)
++#define BANK2_WRITE_EVENT0_CS_SET(x)             (((x) << BANK2_WRITE_EVENT0_CS_LSB) & BANK2_WRITE_EVENT0_CS_MASK)
++
++#define MC_REMAP_VALID_ADDRESS                   0x0c004080
++#define MC_REMAP_VALID_OFFSET                    0x00000080
++#define MC_REMAP_VALID_BIT_MSB                   0
++#define MC_REMAP_VALID_BIT_LSB                   0
++#define MC_REMAP_VALID_BIT_MASK                  0x00000001
++#define MC_REMAP_VALID_BIT_GET(x)                (((x) & MC_REMAP_VALID_BIT_MASK) >> MC_REMAP_VALID_BIT_LSB)
++#define MC_REMAP_VALID_BIT_SET(x)                (((x) << MC_REMAP_VALID_BIT_LSB) & MC_REMAP_VALID_BIT_MASK)
++
++#define MC_REMAP_SIZE_ADDRESS                    0x0c004100
++#define MC_REMAP_SIZE_OFFSET                     0x00000100
++#define MC_REMAP_SIZE_VALUE_MSB                  2
++#define MC_REMAP_SIZE_VALUE_LSB                  0
++#define MC_REMAP_SIZE_VALUE_MASK                 0x00000007
++#define MC_REMAP_SIZE_VALUE_GET(x)               (((x) & MC_REMAP_SIZE_VALUE_MASK) >> MC_REMAP_SIZE_VALUE_LSB)
++#define MC_REMAP_SIZE_VALUE_SET(x)               (((x) << MC_REMAP_SIZE_VALUE_LSB) & MC_REMAP_SIZE_VALUE_MASK)
++
++#define MC_REMAP_COMPARE_ADDRESS                 0x0c004180
++#define MC_REMAP_COMPARE_OFFSET                  0x00000180
++#define MC_REMAP_COMPARE_ADDRESS_MSB             17
++#define MC_REMAP_COMPARE_ADDRESS_LSB             4
++#define MC_REMAP_COMPARE_ADDRESS_MASK            0x0003fff0
++#define MC_REMAP_COMPARE_ADDRESS_GET(x)          (((x) & MC_REMAP_COMPARE_ADDRESS_MASK) >> MC_REMAP_COMPARE_ADDRESS_LSB)
++#define MC_REMAP_COMPARE_ADDRESS_SET(x)          (((x) << MC_REMAP_COMPARE_ADDRESS_LSB) & MC_REMAP_COMPARE_ADDRESS_MASK)
++
++#define MC_REMAP_TARGET_ADDRESS                  0x0c004200
++#define MC_REMAP_TARGET_OFFSET                   0x00000200
++#define MC_REMAP_TARGET_ADDRESS_MSB              16
++#define MC_REMAP_TARGET_ADDRESS_LSB              4
++#define MC_REMAP_TARGET_ADDRESS_MASK             0x0001fff0
++#define MC_REMAP_TARGET_ADDRESS_GET(x)           (((x) & MC_REMAP_TARGET_ADDRESS_MASK) >> MC_REMAP_TARGET_ADDRESS_LSB)
++#define MC_REMAP_TARGET_ADDRESS_SET(x)           (((x) << MC_REMAP_TARGET_ADDRESS_LSB) & MC_REMAP_TARGET_ADDRESS_MASK)
++
++#define G729_ROM_ADDRESS                         0x0c004280
++#define G729_ROM_OFFSET                          0x00000280
++#define G729_ROM_ENABLE_MSB                      0
++#define G729_ROM_ENABLE_LSB                      0
++#define G729_ROM_ENABLE_MASK                     0x00000001
++#define G729_ROM_ENABLE_GET(x)                   (((x) & G729_ROM_ENABLE_MASK) >> G729_ROM_ENABLE_LSB)
++#define G729_ROM_ENABLE_SET(x)                   (((x) << G729_ROM_ENABLE_LSB) & G729_ROM_ENABLE_MASK)
++
++#define ERROR_VALID_ADDRESS                      0x0c004284
++#define ERROR_VALID_OFFSET                       0x00000284
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MSB     8
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB     8
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK    0x00000100
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_GET(x)  (((x) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK) >> ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB)
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_SET(x)  (((x) << ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK)
++#define ERROR_VALID_APB_ERROR_OVERFLOW_MSB       5
++#define ERROR_VALID_APB_ERROR_OVERFLOW_LSB       5
++#define ERROR_VALID_APB_ERROR_OVERFLOW_MASK      0x00000020
++#define ERROR_VALID_APB_ERROR_OVERFLOW_GET(x)    (((x) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK) >> ERROR_VALID_APB_ERROR_OVERFLOW_LSB)
++#define ERROR_VALID_APB_ERROR_OVERFLOW_SET(x)    (((x) << ERROR_VALID_APB_ERROR_OVERFLOW_LSB) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK)
++#define ERROR_VALID_APB_ERROR_VALID_MSB          4
++#define ERROR_VALID_APB_ERROR_VALID_LSB          4
++#define ERROR_VALID_APB_ERROR_VALID_MASK         0x00000010
++#define ERROR_VALID_APB_ERROR_VALID_GET(x)       (((x) & ERROR_VALID_APB_ERROR_VALID_MASK) >> ERROR_VALID_APB_ERROR_VALID_LSB)
++#define ERROR_VALID_APB_ERROR_VALID_SET(x)       (((x) << ERROR_VALID_APB_ERROR_VALID_LSB) & ERROR_VALID_APB_ERROR_VALID_MASK)
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_MSB       1
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_LSB       1
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_MASK      0x00000002
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_GET(x)    (((x) & ERROR_VALID_AHB_ERROR_OVERFLOW_MASK) >> ERROR_VALID_AHB_ERROR_OVERFLOW_LSB)
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_SET(x)    (((x) << ERROR_VALID_AHB_ERROR_OVERFLOW_LSB) & ERROR_VALID_AHB_ERROR_OVERFLOW_MASK)
++#define ERROR_VALID_AHB_ERROR_VALID_MSB          0
++#define ERROR_VALID_AHB_ERROR_VALID_LSB          0
++#define ERROR_VALID_AHB_ERROR_VALID_MASK         0x00000001
++#define ERROR_VALID_AHB_ERROR_VALID_GET(x)       (((x) & ERROR_VALID_AHB_ERROR_VALID_MASK) >> ERROR_VALID_AHB_ERROR_VALID_LSB)
++#define ERROR_VALID_AHB_ERROR_VALID_SET(x)       (((x) << ERROR_VALID_AHB_ERROR_VALID_LSB) & ERROR_VALID_AHB_ERROR_VALID_MASK)
++
++#define AHB_ERROR_ADDRESS                        0x0c004288
++#define AHB_ERROR_OFFSET                         0x00000288
++#define AHB_ERROR_HMASTER_MSB                    31
++#define AHB_ERROR_HMASTER_LSB                    30
++#define AHB_ERROR_HMASTER_MASK                   0xc0000000
++#define AHB_ERROR_HMASTER_GET(x)                 (((x) & AHB_ERROR_HMASTER_MASK) >> AHB_ERROR_HMASTER_LSB)
++#define AHB_ERROR_HMASTER_SET(x)                 (((x) << AHB_ERROR_HMASTER_LSB) & AHB_ERROR_HMASTER_MASK)
++#define AHB_ERROR_HTRANS_MSB                     29
++#define AHB_ERROR_HTRANS_LSB                     28
++#define AHB_ERROR_HTRANS_MASK                    0x30000000
++#define AHB_ERROR_HTRANS_GET(x)                  (((x) & AHB_ERROR_HTRANS_MASK) >> AHB_ERROR_HTRANS_LSB)
++#define AHB_ERROR_HTRANS_SET(x)                  (((x) << AHB_ERROR_HTRANS_LSB) & AHB_ERROR_HTRANS_MASK)
++#define AHB_ERROR_HWRITE_MSB                     27
++#define AHB_ERROR_HWRITE_LSB                     27
++#define AHB_ERROR_HWRITE_MASK                    0x08000000
++#define AHB_ERROR_HWRITE_GET(x)                  (((x) & AHB_ERROR_HWRITE_MASK) >> AHB_ERROR_HWRITE_LSB)
++#define AHB_ERROR_HWRITE_SET(x)                  (((x) << AHB_ERROR_HWRITE_LSB) & AHB_ERROR_HWRITE_MASK)
++#define AHB_ERROR_HBURST_MSB                     26
++#define AHB_ERROR_HBURST_LSB                     24
++#define AHB_ERROR_HBURST_MASK                    0x07000000
++#define AHB_ERROR_HBURST_GET(x)                  (((x) & AHB_ERROR_HBURST_MASK) >> AHB_ERROR_HBURST_LSB)
++#define AHB_ERROR_HBURST_SET(x)                  (((x) << AHB_ERROR_HBURST_LSB) & AHB_ERROR_HBURST_MASK)
++#define AHB_ERROR_HADDR_MSB                      23
++#define AHB_ERROR_HADDR_LSB                      0
++#define AHB_ERROR_HADDR_MASK                     0x00ffffff
++#define AHB_ERROR_HADDR_GET(x)                   (((x) & AHB_ERROR_HADDR_MASK) >> AHB_ERROR_HADDR_LSB)
++#define AHB_ERROR_HADDR_SET(x)                   (((x) << AHB_ERROR_HADDR_LSB) & AHB_ERROR_HADDR_MASK)
++
++#define APB_ERROR_ADDRESS                        0x0c00428c
++#define APB_ERROR_OFFSET                         0x0000028c
++#define APB_ERROR_PADDR_MSB                      31
++#define APB_ERROR_PADDR_LSB                      2
++#define APB_ERROR_PADDR_MASK                     0xfffffffc
++#define APB_ERROR_PADDR_GET(x)                   (((x) & APB_ERROR_PADDR_MASK) >> APB_ERROR_PADDR_LSB)
++#define APB_ERROR_PADDR_SET(x)                   (((x) << APB_ERROR_PADDR_LSB) & APB_ERROR_PADDR_MASK)
++#define APB_ERROR_PVALID_MSB                     1
++#define APB_ERROR_PVALID_LSB                     1
++#define APB_ERROR_PVALID_MASK                    0x00000002
++#define APB_ERROR_PVALID_GET(x)                  (((x) & APB_ERROR_PVALID_MASK) >> APB_ERROR_PVALID_LSB)
++#define APB_ERROR_PVALID_SET(x)                  (((x) << APB_ERROR_PVALID_LSB) & APB_ERROR_PVALID_MASK)
++#define APB_ERROR_PWRITE_MSB                     0
++#define APB_ERROR_PWRITE_LSB                     0
++#define APB_ERROR_PWRITE_MASK                    0x00000001
++#define APB_ERROR_PWRITE_GET(x)                  (((x) & APB_ERROR_PWRITE_MASK) >> APB_ERROR_PWRITE_LSB)
++#define APB_ERROR_PWRITE_SET(x)                  (((x) << APB_ERROR_PWRITE_LSB) & APB_ERROR_PWRITE_MASK)
++
++#define PERF_CONFIG_ADDRESS                      0x0c004290
++#define PERF_CONFIG_OFFSET                       0x00000290
++#define PERF_CONFIG_ENABLE_MSB                   20
++#define PERF_CONFIG_ENABLE_LSB                   20
++#define PERF_CONFIG_ENABLE_MASK                  0x00100000
++#define PERF_CONFIG_ENABLE_GET(x)                (((x) & PERF_CONFIG_ENABLE_MASK) >> PERF_CONFIG_ENABLE_LSB)
++#define PERF_CONFIG_ENABLE_SET(x)                (((x) << PERF_CONFIG_ENABLE_LSB) & PERF_CONFIG_ENABLE_MASK)
++#define PERF_CONFIG_RESET_MSB                    19
++#define PERF_CONFIG_RESET_LSB                    16
++#define PERF_CONFIG_RESET_MASK                   0x000f0000
++#define PERF_CONFIG_RESET_GET(x)                 (((x) & PERF_CONFIG_RESET_MASK) >> PERF_CONFIG_RESET_LSB)
++#define PERF_CONFIG_RESET_SET(x)                 (((x) << PERF_CONFIG_RESET_LSB) & PERF_CONFIG_RESET_MASK)
++#define PERF_CONFIG_COUNTER3_MSB                 15
++#define PERF_CONFIG_COUNTER3_LSB                 12
++#define PERF_CONFIG_COUNTER3_MASK                0x0000f000
++#define PERF_CONFIG_COUNTER3_GET(x)              (((x) & PERF_CONFIG_COUNTER3_MASK) >> PERF_CONFIG_COUNTER3_LSB)
++#define PERF_CONFIG_COUNTER3_SET(x)              (((x) << PERF_CONFIG_COUNTER3_LSB) & PERF_CONFIG_COUNTER3_MASK)
++#define PERF_CONFIG_COUNTER2_MSB                 11
++#define PERF_CONFIG_COUNTER2_LSB                 8
++#define PERF_CONFIG_COUNTER2_MASK                0x00000f00
++#define PERF_CONFIG_COUNTER2_GET(x)              (((x) & PERF_CONFIG_COUNTER2_MASK) >> PERF_CONFIG_COUNTER2_LSB)
++#define PERF_CONFIG_COUNTER2_SET(x)              (((x) << PERF_CONFIG_COUNTER2_LSB) & PERF_CONFIG_COUNTER2_MASK)
++#define PERF_CONFIG_COUNTER1_MSB                 7
++#define PERF_CONFIG_COUNTER1_LSB                 4
++#define PERF_CONFIG_COUNTER1_MASK                0x000000f0
++#define PERF_CONFIG_COUNTER1_GET(x)              (((x) & PERF_CONFIG_COUNTER1_MASK) >> PERF_CONFIG_COUNTER1_LSB)
++#define PERF_CONFIG_COUNTER1_SET(x)              (((x) << PERF_CONFIG_COUNTER1_LSB) & PERF_CONFIG_COUNTER1_MASK)
++#define PERF_CONFIG_COUNTER0_MSB                 3
++#define PERF_CONFIG_COUNTER0_LSB                 0
++#define PERF_CONFIG_COUNTER0_MASK                0x0000000f
++#define PERF_CONFIG_COUNTER0_GET(x)              (((x) & PERF_CONFIG_COUNTER0_MASK) >> PERF_CONFIG_COUNTER0_LSB)
++#define PERF_CONFIG_COUNTER0_SET(x)              (((x) << PERF_CONFIG_COUNTER0_LSB) & PERF_CONFIG_COUNTER0_MASK)
++
++#define PERF_COUNTER_ADDRESS                     0x0c0042a0
++#define PERF_COUNTER_OFFSET                      0x000002a0
++#define PERF_COUNTER_VALUE_MSB                   19
++#define PERF_COUNTER_VALUE_LSB                   0
++#define PERF_COUNTER_VALUE_MASK                  0x000fffff
++#define PERF_COUNTER_VALUE_GET(x)                (((x) & PERF_COUNTER_VALUE_MASK) >> PERF_COUNTER_VALUE_LSB)
++#define PERF_COUNTER_VALUE_SET(x)                (((x) << PERF_COUNTER_VALUE_LSB) & PERF_COUNTER_VALUE_MASK)
++
++#define CPU_SETUP_CONFIG_ADDRESS                 0x0c0042b0
++#define CPU_SETUP_CONFIG_OFFSET                  0x000002b0
++#define CPU_SETUP_CONFIG_ENABLE_MSB              1
++#define CPU_SETUP_CONFIG_ENABLE_LSB              1
++#define CPU_SETUP_CONFIG_ENABLE_MASK             0x00000002
++#define CPU_SETUP_CONFIG_ENABLE_GET(x)           (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
++#define CPU_SETUP_CONFIG_ENABLE_SET(x)           (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
++#define CPU_SETUP_CONFIG_CLEAR_MSB               0
++#define CPU_SETUP_CONFIG_CLEAR_LSB               0
++#define CPU_SETUP_CONFIG_CLEAR_MASK              0x00000001
++#define CPU_SETUP_CONFIG_CLEAR_GET(x)            (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
++#define CPU_SETUP_CONFIG_CLEAR_SET(x)            (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
++
++#define MC_SETUP_CONFIG_ADDRESS                  0x0c0042b4
++#define MC_SETUP_CONFIG_OFFSET                   0x000002b4
++#define MC_SETUP_CONFIG_ENABLE_MSB               1
++#define MC_SETUP_CONFIG_ENABLE_LSB               1
++#define MC_SETUP_CONFIG_ENABLE_MASK              0x00000002
++#define MC_SETUP_CONFIG_ENABLE_GET(x)            (((x) & MC_SETUP_CONFIG_ENABLE_MASK) >> MC_SETUP_CONFIG_ENABLE_LSB)
++#define MC_SETUP_CONFIG_ENABLE_SET(x)            (((x) << MC_SETUP_CONFIG_ENABLE_LSB) & MC_SETUP_CONFIG_ENABLE_MASK)
++#define MC_SETUP_CONFIG_CLEAR_MSB                0
++#define MC_SETUP_CONFIG_CLEAR_LSB                0
++#define MC_SETUP_CONFIG_CLEAR_MASK               0x00000001
++#define MC_SETUP_CONFIG_CLEAR_GET(x)             (((x) & MC_SETUP_CONFIG_CLEAR_MASK) >> MC_SETUP_CONFIG_CLEAR_LSB)
++#define MC_SETUP_CONFIG_CLEAR_SET(x)             (((x) << MC_SETUP_CONFIG_CLEAR_LSB) & MC_SETUP_CONFIG_CLEAR_MASK)
++
++#define BB_SETUP_CONFIG_ADDRESS                  0x0c0042b8
++#define BB_SETUP_CONFIG_OFFSET                   0x000002b8
++#define BB_SETUP_CONFIG_ENABLE_MSB               1
++#define BB_SETUP_CONFIG_ENABLE_LSB               1
++#define BB_SETUP_CONFIG_ENABLE_MASK              0x00000002
++#define BB_SETUP_CONFIG_ENABLE_GET(x)            (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
++#define BB_SETUP_CONFIG_ENABLE_SET(x)            (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
++#define BB_SETUP_CONFIG_CLEAR_MSB                0
++#define BB_SETUP_CONFIG_CLEAR_LSB                0
++#define BB_SETUP_CONFIG_CLEAR_MASK               0x00000001
++#define BB_SETUP_CONFIG_CLEAR_GET(x)             (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
++#define BB_SETUP_CONFIG_CLEAR_SET(x)             (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
++
++#define SDIO_SETUP_CONFIG_ADDRESS                0x0c0042bc
++#define SDIO_SETUP_CONFIG_OFFSET                 0x000002bc
++#define SDIO_SETUP_CONFIG_ENABLE_MSB             1
++#define SDIO_SETUP_CONFIG_ENABLE_LSB             1
++#define SDIO_SETUP_CONFIG_ENABLE_MASK            0x00000002
++#define SDIO_SETUP_CONFIG_ENABLE_GET(x)          (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
++#define SDIO_SETUP_CONFIG_ENABLE_SET(x)          (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
++#define SDIO_SETUP_CONFIG_CLEAR_MSB              0
++#define SDIO_SETUP_CONFIG_CLEAR_LSB              0
++#define SDIO_SETUP_CONFIG_CLEAR_MASK             0x00000001
++#define SDIO_SETUP_CONFIG_CLEAR_GET(x)           (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
++#define SDIO_SETUP_CONFIG_CLEAR_SET(x)           (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
++
++#define CPU_SETUP_CIRCUIT_ADDRESS                0x0c0042c0
++#define CPU_SETUP_CIRCUIT_OFFSET                 0x000002c0
++#define CPU_SETUP_CIRCUIT_VECTOR_MSB             7
++#define CPU_SETUP_CIRCUIT_VECTOR_LSB             0
++#define CPU_SETUP_CIRCUIT_VECTOR_MASK            0x000000ff
++#define CPU_SETUP_CIRCUIT_VECTOR_GET(x)          (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
++#define CPU_SETUP_CIRCUIT_VECTOR_SET(x)          (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define MC_SETUP_CIRCUIT_ADDRESS                 0x0c0042e0
++#define MC_SETUP_CIRCUIT_OFFSET                  0x000002e0
++#define MC_SETUP_CIRCUIT_VECTOR_MSB              7
++#define MC_SETUP_CIRCUIT_VECTOR_LSB              0
++#define MC_SETUP_CIRCUIT_VECTOR_MASK             0x000000ff
++#define MC_SETUP_CIRCUIT_VECTOR_GET(x)           (((x) & MC_SETUP_CIRCUIT_VECTOR_MASK) >> MC_SETUP_CIRCUIT_VECTOR_LSB)
++#define MC_SETUP_CIRCUIT_VECTOR_SET(x)           (((x) << MC_SETUP_CIRCUIT_VECTOR_LSB) & MC_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define BB_SETUP_CIRCUIT_ADDRESS                 0x0c004300
++#define BB_SETUP_CIRCUIT_OFFSET                  0x00000300
++#define BB_SETUP_CIRCUIT_VECTOR_MSB              7
++#define BB_SETUP_CIRCUIT_VECTOR_LSB              0
++#define BB_SETUP_CIRCUIT_VECTOR_MASK             0x000000ff
++#define BB_SETUP_CIRCUIT_VECTOR_GET(x)           (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
++#define BB_SETUP_CIRCUIT_VECTOR_SET(x)           (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define SDIO_SETUP_CIRCUIT_ADDRESS               0x0c004320
++#define SDIO_SETUP_CIRCUIT_OFFSET                0x00000320
++#define SDIO_SETUP_CIRCUIT_VECTOR_MSB            7
++#define SDIO_SETUP_CIRCUIT_VECTOR_LSB            0
++#define SDIO_SETUP_CIRCUIT_VECTOR_MASK           0x000000ff
++#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x)         (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
++#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x)         (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define TIMING_SUMMARY_ADDRESS                   0x0c004340
++#define TIMING_SUMMARY_OFFSET                    0x00000340
++#define TIMING_SUMMARY_VECTOR_MSB                7
++#define TIMING_SUMMARY_VECTOR_LSB                0
++#define TIMING_SUMMARY_VECTOR_MASK               0x000000ff
++#define TIMING_SUMMARY_VECTOR_GET(x)             (((x) & TIMING_SUMMARY_VECTOR_MASK) >> TIMING_SUMMARY_VECTOR_LSB)
++#define TIMING_SUMMARY_VECTOR_SET(x)             (((x) << TIMING_SUMMARY_VECTOR_LSB) & TIMING_SUMMARY_VECTOR_MASK)
++
++#define TIMING_INT_ENABLE_ADDRESS                0x0c004344
++#define TIMING_INT_ENABLE_OFFSET                 0x00000344
++#define TIMING_INT_ENABLE_VECTOR_MSB             7
++#define TIMING_INT_ENABLE_VECTOR_LSB             0
++#define TIMING_INT_ENABLE_VECTOR_MASK            0x000000ff
++#define TIMING_INT_ENABLE_VECTOR_GET(x)          (((x) & TIMING_INT_ENABLE_VECTOR_MASK) >> TIMING_INT_ENABLE_VECTOR_LSB)
++#define TIMING_INT_ENABLE_VECTOR_SET(x)          (((x) << TIMING_INT_ENABLE_VECTOR_LSB) & TIMING_INT_ENABLE_VECTOR_MASK)
++
++#define MC_ERROR_STATUS_ADDRESS                  0x0c004348
++#define MC_ERROR_STATUS_OFFSET                   0x00000348
++#define MC_ERROR_STATUS_AHB_MSB                  1
++#define MC_ERROR_STATUS_AHB_LSB                  1
++#define MC_ERROR_STATUS_AHB_MASK                 0x00000002
++#define MC_ERROR_STATUS_AHB_GET(x)               (((x) & MC_ERROR_STATUS_AHB_MASK) >> MC_ERROR_STATUS_AHB_LSB)
++#define MC_ERROR_STATUS_AHB_SET(x)               (((x) << MC_ERROR_STATUS_AHB_LSB) & MC_ERROR_STATUS_AHB_MASK)
++#define MC_ERROR_STATUS_TIMING_MSB               0
++#define MC_ERROR_STATUS_TIMING_LSB               0
++#define MC_ERROR_STATUS_TIMING_MASK              0x00000001
++#define MC_ERROR_STATUS_TIMING_GET(x)            (((x) & MC_ERROR_STATUS_TIMING_MASK) >> MC_ERROR_STATUS_TIMING_LSB)
++#define MC_ERROR_STATUS_TIMING_SET(x)            (((x) << MC_ERROR_STATUS_TIMING_LSB) & MC_ERROR_STATUS_TIMING_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mc_reg_s {
++  volatile unsigned int bank0_addr;
++  volatile unsigned int bank0_config;
++  volatile unsigned int bank0_read;
++  volatile unsigned int bank0_write;
++  volatile unsigned int bank1_addr;
++  volatile unsigned int bank1_config;
++  volatile unsigned int bank1_read;
++  volatile unsigned int bank1_write;
++  volatile unsigned int bank2_addr;
++  volatile unsigned int bank2_config;
++  volatile unsigned int bank2_read;
++  volatile unsigned int bank2_write;
++  unsigned char pad0[80]; /* pad to 0x80 */
++  volatile unsigned int mc_remap_valid[32];
++  volatile unsigned int mc_remap_size[32];
++  volatile unsigned int mc_remap_compare[32];
++  volatile unsigned int mc_remap_target[32];
++  volatile unsigned int g729_rom;
++  volatile unsigned int error_valid;
++  volatile unsigned int ahb_error;
++  volatile unsigned int apb_error;
++  volatile unsigned int perf_config;
++  unsigned char pad1[12]; /* pad to 0x2a0 */
++  volatile unsigned int perf_counter[4];
++  volatile unsigned int cpu_setup_config;
++  volatile unsigned int mc_setup_config;
++  volatile unsigned int bb_setup_config;
++  volatile unsigned int sdio_setup_config;
++  volatile unsigned int cpu_setup_circuit[8];
++  volatile unsigned int mc_setup_circuit[8];
++  volatile unsigned int bb_setup_circuit[8];
++  volatile unsigned int sdio_setup_circuit[8];
++  volatile unsigned int timing_summary;
++  volatile unsigned int timing_int_enable;
++  volatile unsigned int mc_error_status;
++} mc_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MC_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/rtc_reg.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/hw/rtc_reg.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,1204 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _RTC_REG_H_
++#define _RTC_REG_H_
++
++#define RESET_CONTROL_ADDRESS                    0x0c000000
++#define RESET_CONTROL_OFFSET                     0x00000000
++#define RESET_CONTROL_RST_OUT_MSB                9
++#define RESET_CONTROL_RST_OUT_LSB                9
++#define RESET_CONTROL_RST_OUT_MASK               0x00000200
++#define RESET_CONTROL_RST_OUT_GET(x)             (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
++#define RESET_CONTROL_RST_OUT_SET(x)             (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
++#define RESET_CONTROL_COLD_RST_MSB               8
++#define RESET_CONTROL_COLD_RST_LSB               8
++#define RESET_CONTROL_COLD_RST_MASK              0x00000100
++#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
++#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
++#define RESET_CONTROL_WARM_RST_MSB               7
++#define RESET_CONTROL_WARM_RST_LSB               7
++#define RESET_CONTROL_WARM_RST_MASK              0x00000080
++#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
++#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
++#define RESET_CONTROL_CPU_WARM_RST_MSB           6
++#define RESET_CONTROL_CPU_WARM_RST_LSB           6
++#define RESET_CONTROL_CPU_WARM_RST_MASK          0x00000040
++#define RESET_CONTROL_CPU_WARM_RST_GET(x)        (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
++#define RESET_CONTROL_CPU_WARM_RST_SET(x)        (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
++#define RESET_CONTROL_MAC_COLD_RST_MSB           5
++#define RESET_CONTROL_MAC_COLD_RST_LSB           5
++#define RESET_CONTROL_MAC_COLD_RST_MASK          0x00000020
++#define RESET_CONTROL_MAC_COLD_RST_GET(x)        (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
++#define RESET_CONTROL_MAC_COLD_RST_SET(x)        (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
++#define RESET_CONTROL_MAC_WARM_RST_MSB           4
++#define RESET_CONTROL_MAC_WARM_RST_LSB           4
++#define RESET_CONTROL_MAC_WARM_RST_MASK          0x00000010
++#define RESET_CONTROL_MAC_WARM_RST_GET(x)        (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
++#define RESET_CONTROL_MAC_WARM_RST_SET(x)        (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
++#define RESET_CONTROL_MBOX_RST_MSB               2
++#define RESET_CONTROL_MBOX_RST_LSB               2
++#define RESET_CONTROL_MBOX_RST_MASK              0x00000004
++#define RESET_CONTROL_MBOX_RST_GET(x)            (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
++#define RESET_CONTROL_MBOX_RST_SET(x)            (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
++#define RESET_CONTROL_UART_RST_MSB               1
++#define RESET_CONTROL_UART_RST_LSB               1
++#define RESET_CONTROL_UART_RST_MASK              0x00000002
++#define RESET_CONTROL_UART_RST_GET(x)            (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
++#define RESET_CONTROL_UART_RST_SET(x)            (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
++#define RESET_CONTROL_SI0_RST_MSB                0
++#define RESET_CONTROL_SI0_RST_LSB                0
++#define RESET_CONTROL_SI0_RST_MASK               0x00000001
++#define RESET_CONTROL_SI0_RST_GET(x)             (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
++#define RESET_CONTROL_SI0_RST_SET(x)             (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
++
++#define XTAL_CONTROL_ADDRESS                     0x0c000004
++#define XTAL_CONTROL_OFFSET                      0x00000004
++#define XTAL_CONTROL_TCXO_MSB                    0
++#define XTAL_CONTROL_TCXO_LSB                    0
++#define XTAL_CONTROL_TCXO_MASK                   0x00000001
++#define XTAL_CONTROL_TCXO_GET(x)                 (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
++#define XTAL_CONTROL_TCXO_SET(x)                 (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
++
++#define TCXO_DETECT_ADDRESS                      0x0c000008
++#define TCXO_DETECT_OFFSET                       0x00000008
++#define TCXO_DETECT_PRESENT_MSB                  0
++#define TCXO_DETECT_PRESENT_LSB                  0
++#define TCXO_DETECT_PRESENT_MASK                 0x00000001
++#define TCXO_DETECT_PRESENT_GET(x)               (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
++#define TCXO_DETECT_PRESENT_SET(x)               (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
++
++#define XTAL_TEST_ADDRESS                        0x0c00000c
++#define XTAL_TEST_OFFSET                         0x0000000c
++#define XTAL_TEST_NOTCXODET_MSB                  0
++#define XTAL_TEST_NOTCXODET_LSB                  0
++#define XTAL_TEST_NOTCXODET_MASK                 0x00000001
++#define XTAL_TEST_NOTCXODET_GET(x)               (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
++#define XTAL_TEST_NOTCXODET_SET(x)               (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
++
++#define QUADRATURE_ADDRESS                       0x0c000010
++#define QUADRATURE_OFFSET                        0x00000010
++#define QUADRATURE_ADC_MSB                       5
++#define QUADRATURE_ADC_LSB                       4
++#define QUADRATURE_ADC_MASK                      0x00000030
++#define QUADRATURE_ADC_GET(x)                    (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
++#define QUADRATURE_ADC_SET(x)                    (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
++#define QUADRATURE_SEL_MSB                       2
++#define QUADRATURE_SEL_LSB                       2
++#define QUADRATURE_SEL_MASK                      0x00000004
++#define QUADRATURE_SEL_GET(x)                    (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
++#define QUADRATURE_SEL_SET(x)                    (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
++#define QUADRATURE_DAC_MSB                       1
++#define QUADRATURE_DAC_LSB                       0
++#define QUADRATURE_DAC_MASK                      0x00000003
++#define QUADRATURE_DAC_GET(x)                    (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
++#define QUADRATURE_DAC_SET(x)                    (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
++
++#define PLL_CONTROL_ADDRESS                      0x0c000014
++#define PLL_CONTROL_OFFSET                       0x00000014
++#define PLL_CONTROL_DIG_TEST_CLK_MSB             20
++#define PLL_CONTROL_DIG_TEST_CLK_LSB             20
++#define PLL_CONTROL_DIG_TEST_CLK_MASK            0x00100000
++#define PLL_CONTROL_DIG_TEST_CLK_GET(x)          (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
++#define PLL_CONTROL_DIG_TEST_CLK_SET(x)          (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
++#define PLL_CONTROL_MAC_OVERRIDE_MSB             19
++#define PLL_CONTROL_MAC_OVERRIDE_LSB             19
++#define PLL_CONTROL_MAC_OVERRIDE_MASK            0x00080000
++#define PLL_CONTROL_MAC_OVERRIDE_GET(x)          (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
++#define PLL_CONTROL_MAC_OVERRIDE_SET(x)          (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
++#define PLL_CONTROL_NOPWD_MSB                    18
++#define PLL_CONTROL_NOPWD_LSB                    18
++#define PLL_CONTROL_NOPWD_MASK                   0x00040000
++#define PLL_CONTROL_NOPWD_GET(x)                 (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
++#define PLL_CONTROL_NOPWD_SET(x)                 (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
++#define PLL_CONTROL_UPDATING_MSB                 17
++#define PLL_CONTROL_UPDATING_LSB                 17
++#define PLL_CONTROL_UPDATING_MASK                0x00020000
++#define PLL_CONTROL_UPDATING_GET(x)              (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
++#define PLL_CONTROL_UPDATING_SET(x)              (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
++#define PLL_CONTROL_BYPASS_MSB                   16
++#define PLL_CONTROL_BYPASS_LSB                   16
++#define PLL_CONTROL_BYPASS_MASK                  0x00010000
++#define PLL_CONTROL_BYPASS_GET(x)                (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
++#define PLL_CONTROL_BYPASS_SET(x)                (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
++#define PLL_CONTROL_REFDIV_MSB                   15
++#define PLL_CONTROL_REFDIV_LSB                   12
++#define PLL_CONTROL_REFDIV_MASK                  0x0000f000
++#define PLL_CONTROL_REFDIV_GET(x)                (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
++#define PLL_CONTROL_REFDIV_SET(x)                (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
++#define PLL_CONTROL_DIV_MSB                      9
++#define PLL_CONTROL_DIV_LSB                      0
++#define PLL_CONTROL_DIV_MASK                     0x000003ff
++#define PLL_CONTROL_DIV_GET(x)                   (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
++#define PLL_CONTROL_DIV_SET(x)                   (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
++
++#define PLL_SETTLE_ADDRESS                       0x0c000018
++#define PLL_SETTLE_OFFSET                        0x00000018
++#define PLL_SETTLE_TIME_MSB                      10
++#define PLL_SETTLE_TIME_LSB                      0
++#define PLL_SETTLE_TIME_MASK                     0x000007ff
++#define PLL_SETTLE_TIME_GET(x)                   (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
++#define PLL_SETTLE_TIME_SET(x)                   (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
++
++#define XTAL_SETTLE_ADDRESS                      0x0c00001c
++#define XTAL_SETTLE_OFFSET                       0x0000001c
++#define XTAL_SETTLE_TIME_MSB                     6
++#define XTAL_SETTLE_TIME_LSB                     0
++#define XTAL_SETTLE_TIME_MASK                    0x0000007f
++#define XTAL_SETTLE_TIME_GET(x)                  (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
++#define XTAL_SETTLE_TIME_SET(x)                  (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
++
++#define CORE_CLOCK_ADDRESS                       0x0c000020
++#define CORE_CLOCK_OFFSET                        0x00000020
++#define CORE_CLOCK_DIG_TEST_MSB                  12
++#define CORE_CLOCK_DIG_TEST_LSB                  12
++#define CORE_CLOCK_DIG_TEST_MASK                 0x00001000
++#define CORE_CLOCK_DIG_TEST_GET(x)               (((x) & CORE_CLOCK_DIG_TEST_MASK) >> CORE_CLOCK_DIG_TEST_LSB)
++#define CORE_CLOCK_DIG_TEST_SET(x)               (((x) << CORE_CLOCK_DIG_TEST_LSB) & CORE_CLOCK_DIG_TEST_MASK)
++#define CORE_CLOCK_STANDARD_MSB                  9
++#define CORE_CLOCK_STANDARD_LSB                  8
++#define CORE_CLOCK_STANDARD_MASK                 0x00000300
++#define CORE_CLOCK_STANDARD_GET(x)               (((x) & CORE_CLOCK_STANDARD_MASK) >> CORE_CLOCK_STANDARD_LSB)
++#define CORE_CLOCK_STANDARD_SET(x)               (((x) << CORE_CLOCK_STANDARD_LSB) & CORE_CLOCK_STANDARD_MASK)
++#define CORE_CLOCK_REDUCED_MSB                   1
++#define CORE_CLOCK_REDUCED_LSB                   0
++#define CORE_CLOCK_REDUCED_MASK                  0x00000003
++#define CORE_CLOCK_REDUCED_GET(x)                (((x) & CORE_CLOCK_REDUCED_MASK) >> CORE_CLOCK_REDUCED_LSB)
++#define CORE_CLOCK_REDUCED_SET(x)                (((x) << CORE_CLOCK_REDUCED_LSB) & CORE_CLOCK_REDUCED_MASK)
++
++#define CPU_CLOCK_ADDRESS                        0x0c000024
++#define CPU_CLOCK_OFFSET                         0x00000024
++#define CPU_CLOCK_DISABLE_SYNC_MSB               12
++#define CPU_CLOCK_DISABLE_SYNC_LSB               12
++#define CPU_CLOCK_DISABLE_SYNC_MASK              0x00001000
++#define CPU_CLOCK_DISABLE_SYNC_GET(x)            (((x) & CPU_CLOCK_DISABLE_SYNC_MASK) >> CPU_CLOCK_DISABLE_SYNC_LSB)
++#define CPU_CLOCK_DISABLE_SYNC_SET(x)            (((x) << CPU_CLOCK_DISABLE_SYNC_LSB) & CPU_CLOCK_DISABLE_SYNC_MASK)
++#define CPU_CLOCK_STANDARD_MSB                   9
++#define CPU_CLOCK_STANDARD_LSB                   8
++#define CPU_CLOCK_STANDARD_MASK                  0x00000300
++#define CPU_CLOCK_STANDARD_GET(x)                (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
++#define CPU_CLOCK_STANDARD_SET(x)                (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
++#define CPU_CLOCK_REDUCED_MSB                    1
++#define CPU_CLOCK_REDUCED_LSB                    0
++#define CPU_CLOCK_REDUCED_MASK                   0x00000003
++#define CPU_CLOCK_REDUCED_GET(x)                 (((x) & CPU_CLOCK_REDUCED_MASK) >> CPU_CLOCK_REDUCED_LSB)
++#define CPU_CLOCK_REDUCED_SET(x)                 (((x) << CPU_CLOCK_REDUCED_LSB) & CPU_CLOCK_REDUCED_MASK)
++
++#define CLOCK_OUT_ADDRESS                        0x0c000028
++#define CLOCK_OUT_OFFSET                         0x00000028
++#define CLOCK_OUT_SELECT_MSB                     3
++#define CLOCK_OUT_SELECT_LSB                     0
++#define CLOCK_OUT_SELECT_MASK                    0x0000000f
++#define CLOCK_OUT_SELECT_GET(x)                  (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
++#define CLOCK_OUT_SELECT_SET(x)                  (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
++
++#define CLOCK_CONTROL_ADDRESS                    0x0c00002c
++#define CLOCK_CONTROL_OFFSET                     0x0000002c
++#define CLOCK_CONTROL_UART_CLK_MSB               1
++#define CLOCK_CONTROL_UART_CLK_LSB               1
++#define CLOCK_CONTROL_UART_CLK_MASK              0x00000002
++#define CLOCK_CONTROL_UART_CLK_GET(x)            (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
++#define CLOCK_CONTROL_UART_CLK_SET(x)            (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
++#define CLOCK_CONTROL_SI0_CLK_MSB                0
++#define CLOCK_CONTROL_SI0_CLK_LSB                0
++#define CLOCK_CONTROL_SI0_CLK_MASK               0x00000001
++#define CLOCK_CONTROL_SI0_CLK_GET(x)             (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
++#define CLOCK_CONTROL_SI0_CLK_SET(x)             (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
++
++#define BIAS_OVERRIDE_ADDRESS                    0x0c000030
++#define BIAS_OVERRIDE_OFFSET                     0x00000030
++#define BIAS_OVERRIDE_ON_MSB                     0
++#define BIAS_OVERRIDE_ON_LSB                     0
++#define BIAS_OVERRIDE_ON_MASK                    0x00000001
++#define BIAS_OVERRIDE_ON_GET(x)                  (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
++#define BIAS_OVERRIDE_ON_SET(x)                  (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
++
++#define REF_VOLTAGE_TRIM_ADDRESS                 0x0c000034
++#define REF_VOLTAGE_TRIM_OFFSET                  0x00000034
++#define REF_VOLTAGE_TRIM_REFSEL_MSB              3
++#define REF_VOLTAGE_TRIM_REFSEL_LSB              0
++#define REF_VOLTAGE_TRIM_REFSEL_MASK             0x0000000f
++#define REF_VOLTAGE_TRIM_REFSEL_GET(x)           (((x) & REF_VOLTAGE_TRIM_REFSEL_MASK) >> REF_VOLTAGE_TRIM_REFSEL_LSB)
++#define REF_VOLTAGE_TRIM_REFSEL_SET(x)           (((x) << REF_VOLTAGE_TRIM_REFSEL_LSB) & REF_VOLTAGE_TRIM_REFSEL_MASK)
++
++#define LDO_CONTROL_ADDRESS                      0x0c000038
++#define LDO_CONTROL_OFFSET                       0x00000038
++#define LDO_CONTROL_CORE_LIMIT_OFF_MSB           14
++#define LDO_CONTROL_CORE_LIMIT_OFF_LSB           14
++#define LDO_CONTROL_CORE_LIMIT_OFF_MASK          0x00004000
++#define LDO_CONTROL_CORE_LIMIT_OFF_GET(x)        (((x) & LDO_CONTROL_CORE_LIMIT_OFF_MASK) >> LDO_CONTROL_CORE_LIMIT_OFF_LSB)
++#define LDO_CONTROL_CORE_LIMIT_OFF_SET(x)        (((x) << LDO_CONTROL_CORE_LIMIT_OFF_LSB) & LDO_CONTROL_CORE_LIMIT_OFF_MASK)
++#define LDO_CONTROL_CORE_LIMIT_MSB               13
++#define LDO_CONTROL_CORE_LIMIT_LSB               11
++#define LDO_CONTROL_CORE_LIMIT_MASK              0x00003800
++#define LDO_CONTROL_CORE_LIMIT_GET(x)            (((x) & LDO_CONTROL_CORE_LIMIT_MASK) >> LDO_CONTROL_CORE_LIMIT_LSB)
++#define LDO_CONTROL_CORE_LIMIT_SET(x)            (((x) << LDO_CONTROL_CORE_LIMIT_LSB) & LDO_CONTROL_CORE_LIMIT_MASK)
++#define LDO_CONTROL_CORE_REG_Z_MSB               10
++#define LDO_CONTROL_CORE_REG_Z_LSB               8
++#define LDO_CONTROL_CORE_REG_Z_MASK              0x00000700
++#define LDO_CONTROL_CORE_REG_Z_GET(x)            (((x) & LDO_CONTROL_CORE_REG_Z_MASK) >> LDO_CONTROL_CORE_REG_Z_LSB)
++#define LDO_CONTROL_CORE_REG_Z_SET(x)            (((x) << LDO_CONTROL_CORE_REG_Z_LSB) & LDO_CONTROL_CORE_REG_Z_MASK)
++#define LDO_CONTROL_RADIO_LIMIT_OFF_MSB          6
++#define LDO_CONTROL_RADIO_LIMIT_OFF_LSB          6
++#define LDO_CONTROL_RADIO_LIMIT_OFF_MASK         0x00000040
++#define LDO_CONTROL_RADIO_LIMIT_OFF_GET(x)       (((x) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK) >> LDO_CONTROL_RADIO_LIMIT_OFF_LSB)
++#define LDO_CONTROL_RADIO_LIMIT_OFF_SET(x)       (((x) << LDO_CONTROL_RADIO_LIMIT_OFF_LSB) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK)
++#define LDO_CONTROL_RADIO_LIMIT_MSB              5
++#define LDO_CONTROL_RADIO_LIMIT_LSB              3
++#define LDO_CONTROL_RADIO_LIMIT_MASK             0x00000038
++#define LDO_CONTROL_RADIO_LIMIT_GET(x)           (((x) & LDO_CONTROL_RADIO_LIMIT_MASK) >> LDO_CONTROL_RADIO_LIMIT_LSB)
++#define LDO_CONTROL_RADIO_LIMIT_SET(x)           (((x) << LDO_CONTROL_RADIO_LIMIT_LSB) & LDO_CONTROL_RADIO_LIMIT_MASK)
++#define LDO_CONTROL_RADIO_REG_Z_MSB              2
++#define LDO_CONTROL_RADIO_REG_Z_LSB              0
++#define LDO_CONTROL_RADIO_REG_Z_MASK             0x00000007
++#define LDO_CONTROL_RADIO_REG_Z_GET(x)           (((x) & LDO_CONTROL_RADIO_REG_Z_MASK) >> LDO_CONTROL_RADIO_REG_Z_LSB)
++#define LDO_CONTROL_RADIO_REG_Z_SET(x)           (((x) << LDO_CONTROL_RADIO_REG_Z_LSB) & LDO_CONTROL_RADIO_REG_Z_MASK)
++
++#define WDT_CONTROL_ADDRESS                      0x0c00003c
++#define WDT_CONTROL_OFFSET                       0x0000003c
++#define WDT_CONTROL_ACTION_MSB                   2
++#define WDT_CONTROL_ACTION_LSB                   0
++#define WDT_CONTROL_ACTION_MASK                  0x00000007
++#define WDT_CONTROL_ACTION_GET(x)                (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
++#define WDT_CONTROL_ACTION_SET(x)                (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
++
++#define WDT_STATUS_ADDRESS                       0x0c000040
++#define WDT_STATUS_OFFSET                        0x00000040
++#define WDT_STATUS_INTERRUPT_MSB                 0
++#define WDT_STATUS_INTERRUPT_LSB                 0
++#define WDT_STATUS_INTERRUPT_MASK                0x00000001
++#define WDT_STATUS_INTERRUPT_GET(x)              (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
++#define WDT_STATUS_INTERRUPT_SET(x)              (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
++
++#define WDT_ADDRESS                              0x0c000044
++#define WDT_OFFSET                               0x00000044
++#define WDT_TARGET_MSB                           21
++#define WDT_TARGET_LSB                           0
++#define WDT_TARGET_MASK                          0x003fffff
++#define WDT_TARGET_GET(x)                        (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
++#define WDT_TARGET_SET(x)                        (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
++
++#define WDT_COUNT_ADDRESS                        0x0c000048
++#define WDT_COUNT_OFFSET                         0x00000048
++#define WDT_COUNT_VALUE_MSB                      21
++#define WDT_COUNT_VALUE_LSB                      0
++#define WDT_COUNT_VALUE_MASK                     0x003fffff
++#define WDT_COUNT_VALUE_GET(x)                   (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
++#define WDT_COUNT_VALUE_SET(x)                   (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
++
++#define WDT_RESET_ADDRESS                        0x0c00004c
++#define WDT_RESET_OFFSET                         0x0000004c
++#define WDT_RESET_VALUE_MSB                      0
++#define WDT_RESET_VALUE_LSB                      0
++#define WDT_RESET_VALUE_MASK                     0x00000001
++#define WDT_RESET_VALUE_GET(x)                   (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
++#define WDT_RESET_VALUE_SET(x)                   (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
++
++#define INT_STATUS_ADDRESS                       0x0c000050
++#define INT_STATUS_OFFSET                        0x00000050
++#define INT_STATUS_TIMER_MSB                     14
++#define INT_STATUS_TIMER_LSB                     14
++#define INT_STATUS_TIMER_MASK                    0x00004000
++#define INT_STATUS_TIMER_GET(x)                  (((x) & INT_STATUS_TIMER_MASK) >> INT_STATUS_TIMER_LSB)
++#define INT_STATUS_TIMER_SET(x)                  (((x) << INT_STATUS_TIMER_LSB) & INT_STATUS_TIMER_MASK)
++#define INT_STATUS_MAC_MSB                       13
++#define INT_STATUS_MAC_LSB                       13
++#define INT_STATUS_MAC_MASK                      0x00002000
++#define INT_STATUS_MAC_GET(x)                    (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
++#define INT_STATUS_MAC_SET(x)                    (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
++#define INT_STATUS_MAILBOX_MSB                   12
++#define INT_STATUS_MAILBOX_LSB                   12
++#define INT_STATUS_MAILBOX_MASK                  0x00001000
++#define INT_STATUS_MAILBOX_GET(x)                (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
++#define INT_STATUS_MAILBOX_SET(x)                (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
++#define INT_STATUS_RTC_ALARM_MSB                 11
++#define INT_STATUS_RTC_ALARM_LSB                 11
++#define INT_STATUS_RTC_ALARM_MASK                0x00000800
++#define INT_STATUS_RTC_ALARM_GET(x)              (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
++#define INT_STATUS_RTC_ALARM_SET(x)              (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
++#define INT_STATUS_HF_TIMER_MSB                  10
++#define INT_STATUS_HF_TIMER_LSB                  10
++#define INT_STATUS_HF_TIMER_MASK                 0x00000400
++#define INT_STATUS_HF_TIMER_GET(x)               (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
++#define INT_STATUS_HF_TIMER_SET(x)               (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
++#define INT_STATUS_LF_TIMER3_MSB                 9
++#define INT_STATUS_LF_TIMER3_LSB                 9
++#define INT_STATUS_LF_TIMER3_MASK                0x00000200
++#define INT_STATUS_LF_TIMER3_GET(x)              (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
++#define INT_STATUS_LF_TIMER3_SET(x)              (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
++#define INT_STATUS_LF_TIMER2_MSB                 8
++#define INT_STATUS_LF_TIMER2_LSB                 8
++#define INT_STATUS_LF_TIMER2_MASK                0x00000100
++#define INT_STATUS_LF_TIMER2_GET(x)              (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
++#define INT_STATUS_LF_TIMER2_SET(x)              (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
++#define INT_STATUS_LF_TIMER1_MSB                 7
++#define INT_STATUS_LF_TIMER1_LSB                 7
++#define INT_STATUS_LF_TIMER1_MASK                0x00000080
++#define INT_STATUS_LF_TIMER1_GET(x)              (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
++#define INT_STATUS_LF_TIMER1_SET(x)              (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
++#define INT_STATUS_LF_TIMER0_MSB                 6
++#define INT_STATUS_LF_TIMER0_LSB                 6
++#define INT_STATUS_LF_TIMER0_MASK                0x00000040
++#define INT_STATUS_LF_TIMER0_GET(x)              (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
++#define INT_STATUS_LF_TIMER0_SET(x)              (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
++#define INT_STATUS_KEYPAD_MSB                    5
++#define INT_STATUS_KEYPAD_LSB                    5
++#define INT_STATUS_KEYPAD_MASK                   0x00000020
++#define INT_STATUS_KEYPAD_GET(x)                 (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
++#define INT_STATUS_KEYPAD_SET(x)                 (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
++#define INT_STATUS_SI_MSB                        4
++#define INT_STATUS_SI_LSB                        4
++#define INT_STATUS_SI_MASK                       0x00000010
++#define INT_STATUS_SI_GET(x)                     (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
++#define INT_STATUS_SI_SET(x)                     (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
++#define INT_STATUS_GPIO_MSB                      3
++#define INT_STATUS_GPIO_LSB                      3
++#define INT_STATUS_GPIO_MASK                     0x00000008
++#define INT_STATUS_GPIO_GET(x)                   (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
++#define INT_STATUS_GPIO_SET(x)                   (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
++#define INT_STATUS_UART_MSB                      2
++#define INT_STATUS_UART_LSB                      2
++#define INT_STATUS_UART_MASK                     0x00000004
++#define INT_STATUS_UART_GET(x)                   (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
++#define INT_STATUS_UART_SET(x)                   (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
++#define INT_STATUS_ERROR_MSB                     1
++#define INT_STATUS_ERROR_LSB                     1
++#define INT_STATUS_ERROR_MASK                    0x00000002
++#define INT_STATUS_ERROR_GET(x)                  (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
++#define INT_STATUS_ERROR_SET(x)                  (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
++#define INT_STATUS_WDT_INT_MSB                   0
++#define INT_STATUS_WDT_INT_LSB                   0
++#define INT_STATUS_WDT_INT_MASK                  0x00000001
++#define INT_STATUS_WDT_INT_GET(x)                (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
++#define INT_STATUS_WDT_INT_SET(x)                (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
++
++#define LF_TIMER0_ADDRESS                        0x0c000054
++#define LF_TIMER0_OFFSET                         0x00000054
++#define LF_TIMER0_TARGET_MSB                     31
++#define LF_TIMER0_TARGET_LSB                     0
++#define LF_TIMER0_TARGET_MASK                    0xffffffff
++#define LF_TIMER0_TARGET_GET(x)                  (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
++#define LF_TIMER0_TARGET_SET(x)                  (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
++
++#define LF_TIMER_COUNT0_ADDRESS                  0x0c000058
++#define LF_TIMER_COUNT0_OFFSET                   0x00000058
++#define LF_TIMER_COUNT0_VALUE_MSB                31
++#define LF_TIMER_COUNT0_VALUE_LSB                0
++#define LF_TIMER_COUNT0_VALUE_MASK               0xffffffff
++#define LF_TIMER_COUNT0_VALUE_GET(x)             (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
++#define LF_TIMER_COUNT0_VALUE_SET(x)             (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
++
++#define LF_TIMER_CONTROL0_ADDRESS                0x0c00005c
++#define LF_TIMER_CONTROL0_OFFSET                 0x0000005c
++#define LF_TIMER_CONTROL0_ENABLE_MSB             2
++#define LF_TIMER_CONTROL0_ENABLE_LSB             2
++#define LF_TIMER_CONTROL0_ENABLE_MASK            0x00000004
++#define LF_TIMER_CONTROL0_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
++#define LF_TIMER_CONTROL0_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
++#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB       1
++#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB       1
++#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK      0x00000002
++#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL0_RESET_MSB              0
++#define LF_TIMER_CONTROL0_RESET_LSB              0
++#define LF_TIMER_CONTROL0_RESET_MASK             0x00000001
++#define LF_TIMER_CONTROL0_RESET_GET(x)           (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
++#define LF_TIMER_CONTROL0_RESET_SET(x)           (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
++
++#define LF_TIMER_STATUS0_ADDRESS                 0x0c000060
++#define LF_TIMER_STATUS0_OFFSET                  0x00000060
++#define LF_TIMER_STATUS0_INTERRUPT_MSB           0
++#define LF_TIMER_STATUS0_INTERRUPT_LSB           0
++#define LF_TIMER_STATUS0_INTERRUPT_MASK          0x00000001
++#define LF_TIMER_STATUS0_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
++#define LF_TIMER_STATUS0_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
++
++#define LF_TIMER1_ADDRESS                        0x0c000064
++#define LF_TIMER1_OFFSET                         0x00000064
++#define LF_TIMER1_TARGET_MSB                     31
++#define LF_TIMER1_TARGET_LSB                     0
++#define LF_TIMER1_TARGET_MASK                    0xffffffff
++#define LF_TIMER1_TARGET_GET(x)                  (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
++#define LF_TIMER1_TARGET_SET(x)                  (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
++
++#define LF_TIMER_COUNT1_ADDRESS                  0x0c000068
++#define LF_TIMER_COUNT1_OFFSET                   0x00000068
++#define LF_TIMER_COUNT1_VALUE_MSB                31
++#define LF_TIMER_COUNT1_VALUE_LSB                0
++#define LF_TIMER_COUNT1_VALUE_MASK               0xffffffff
++#define LF_TIMER_COUNT1_VALUE_GET(x)             (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
++#define LF_TIMER_COUNT1_VALUE_SET(x)             (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
++
++#define LF_TIMER_CONTROL1_ADDRESS                0x0c00006c
++#define LF_TIMER_CONTROL1_OFFSET                 0x0000006c
++#define LF_TIMER_CONTROL1_ENABLE_MSB             2
++#define LF_TIMER_CONTROL1_ENABLE_LSB             2
++#define LF_TIMER_CONTROL1_ENABLE_MASK            0x00000004
++#define LF_TIMER_CONTROL1_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
++#define LF_TIMER_CONTROL1_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
++#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB       1
++#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB       1
++#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK      0x00000002
++#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL1_RESET_MSB              0
++#define LF_TIMER_CONTROL1_RESET_LSB              0
++#define LF_TIMER_CONTROL1_RESET_MASK             0x00000001
++#define LF_TIMER_CONTROL1_RESET_GET(x)           (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
++#define LF_TIMER_CONTROL1_RESET_SET(x)           (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
++
++#define LF_TIMER_STATUS1_ADDRESS                 0x0c000070
++#define LF_TIMER_STATUS1_OFFSET                  0x00000070
++#define LF_TIMER_STATUS1_INTERRUPT_MSB           0
++#define LF_TIMER_STATUS1_INTERRUPT_LSB           0
++#define LF_TIMER_STATUS1_INTERRUPT_MASK          0x00000001
++#define LF_TIMER_STATUS1_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
++#define LF_TIMER_STATUS1_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
++
++#define LF_TIMER2_ADDRESS                        0x0c000074
++#define LF_TIMER2_OFFSET                         0x00000074
++#define LF_TIMER2_TARGET_MSB                     31
++#define LF_TIMER2_TARGET_LSB                     0
++#define LF_TIMER2_TARGET_MASK                    0xffffffff
++#define LF_TIMER2_TARGET_GET(x)                  (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
++#define LF_TIMER2_TARGET_SET(x)                  (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
++
++#define LF_TIMER_COUNT2_ADDRESS                  0x0c000078
++#define LF_TIMER_COUNT2_OFFSET                   0x00000078
++#define LF_TIMER_COUNT2_VALUE_MSB                31
++#define LF_TIMER_COUNT2_VALUE_LSB                0
++#define LF_TIMER_COUNT2_VALUE_MASK               0xffffffff
++#define LF_TIMER_COUNT2_VALUE_GET(x)             (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
++#define LF_TIMER_COUNT2_VALUE_SET(x)             (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
++
++#define LF_TIMER_CONTROL2_ADDRESS                0x0c00007c
++#define LF_TIMER_CONTROL2_OFFSET                 0x0000007c
++#define LF_TIMER_CONTROL2_ENABLE_MSB             2
++#define LF_TIMER_CONTROL2_ENABLE_LSB             2
++#define LF_TIMER_CONTROL2_ENABLE_MASK            0x00000004
++#define LF_TIMER_CONTROL2_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
++#define LF_TIMER_CONTROL2_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
++#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB       1
++#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB       1
++#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK      0x00000002
++#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL2_RESET_MSB              0
++#define LF_TIMER_CONTROL2_RESET_LSB              0
++#define LF_TIMER_CONTROL2_RESET_MASK             0x00000001
++#define LF_TIMER_CONTROL2_RESET_GET(x)           (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
++#define LF_TIMER_CONTROL2_RESET_SET(x)           (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
++
++#define LF_TIMER_STATUS2_ADDRESS                 0x0c000080
++#define LF_TIMER_STATUS2_OFFSET                  0x00000080
++#define LF_TIMER_STATUS2_INTERRUPT_MSB           0
++#define LF_TIMER_STATUS2_INTERRUPT_LSB           0
++#define LF_TIMER_STATUS2_INTERRUPT_MASK          0x00000001
++#define LF_TIMER_STATUS2_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
++#define LF_TIMER_STATUS2_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
++
++#define LF_TIMER3_ADDRESS                        0x0c000084
++#define LF_TIMER3_OFFSET                         0x00000084
++#define LF_TIMER3_TARGET_MSB                     31
++#define LF_TIMER3_TARGET_LSB                     0
++#define LF_TIMER3_TARGET_MASK                    0xffffffff
++#define LF_TIMER3_TARGET_GET(x)                  (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
++#define LF_TIMER3_TARGET_SET(x)                  (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
++
++#define LF_TIMER_COUNT3_ADDRESS                  0x0c000088
++#define LF_TIMER_COUNT3_OFFSET                   0x00000088
++#define LF_TIMER_COUNT3_VALUE_MSB                31
++#define LF_TIMER_COUNT3_VALUE_LSB                0
++#define LF_TIMER_COUNT3_VALUE_MASK               0xffffffff
++#define LF_TIMER_COUNT3_VALUE_GET(x)             (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
++#define LF_TIMER_COUNT3_VALUE_SET(x)             (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
++
++#define LF_TIMER_CONTROL3_ADDRESS                0x0c00008c
++#define LF_TIMER_CONTROL3_OFFSET                 0x0000008c
++#define LF_TIMER_CONTROL3_ENABLE_MSB             2
++#define LF_TIMER_CONTROL3_ENABLE_LSB             2
++#define LF_TIMER_CONTROL3_ENABLE_MASK            0x00000004
++#define LF_TIMER_CONTROL3_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
++#define LF_TIMER_CONTROL3_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
++#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB       1
++#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB       1
++#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK      0x00000002
++#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL3_RESET_MSB              0
++#define LF_TIMER_CONTROL3_RESET_LSB              0
++#define LF_TIMER_CONTROL3_RESET_MASK             0x00000001
++#define LF_TIMER_CONTROL3_RESET_GET(x)           (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
++#define LF_TIMER_CONTROL3_RESET_SET(x)           (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
++
++#define LF_TIMER_STATUS3_ADDRESS                 0x0c000090
++#define LF_TIMER_STATUS3_OFFSET                  0x00000090
++#define LF_TIMER_STATUS3_INTERRUPT_MSB           0
++#define LF_TIMER_STATUS3_INTERRUPT_LSB           0
++#define LF_TIMER_STATUS3_INTERRUPT_MASK          0x00000001
++#define LF_TIMER_STATUS3_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
++#define LF_TIMER_STATUS3_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
++
++#define HF_TIMER_ADDRESS                         0x0c000094
++#define HF_TIMER_OFFSET                          0x00000094
++#define HF_TIMER_TARGET_MSB                      31
++#define HF_TIMER_TARGET_LSB                      12
++#define HF_TIMER_TARGET_MASK                     0xfffff000
++#define HF_TIMER_TARGET_GET(x)                   (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
++#define HF_TIMER_TARGET_SET(x)                   (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
++
++#define HF_TIMER_COUNT_ADDRESS                   0x0c000098
++#define HF_TIMER_COUNT_OFFSET                    0x00000098
++#define HF_TIMER_COUNT_VALUE_MSB                 31
++#define HF_TIMER_COUNT_VALUE_LSB                 12
++#define HF_TIMER_COUNT_VALUE_MASK                0xfffff000
++#define HF_TIMER_COUNT_VALUE_GET(x)              (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
++#define HF_TIMER_COUNT_VALUE_SET(x)              (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
++
++#define HF_LF_COUNT_ADDRESS                      0x0c00009c
++#define HF_LF_COUNT_OFFSET                       0x0000009c
++#define HF_LF_COUNT_VALUE_MSB                    31
++#define HF_LF_COUNT_VALUE_LSB                    0
++#define HF_LF_COUNT_VALUE_MASK                   0xffffffff
++#define HF_LF_COUNT_VALUE_GET(x)                 (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
++#define HF_LF_COUNT_VALUE_SET(x)                 (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
++
++#define HF_TIMER_CONTROL_ADDRESS                 0x0c0000a0
++#define HF_TIMER_CONTROL_OFFSET                  0x000000a0
++#define HF_TIMER_CONTROL_ENABLE_MSB              3
++#define HF_TIMER_CONTROL_ENABLE_LSB              3
++#define HF_TIMER_CONTROL_ENABLE_MASK             0x00000008
++#define HF_TIMER_CONTROL_ENABLE_GET(x)           (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
++#define HF_TIMER_CONTROL_ENABLE_SET(x)           (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
++#define HF_TIMER_CONTROL_ON_MSB                  2
++#define HF_TIMER_CONTROL_ON_LSB                  2
++#define HF_TIMER_CONTROL_ON_MASK                 0x00000004
++#define HF_TIMER_CONTROL_ON_GET(x)               (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
++#define HF_TIMER_CONTROL_ON_SET(x)               (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
++#define HF_TIMER_CONTROL_AUTO_RESTART_MSB        1
++#define HF_TIMER_CONTROL_AUTO_RESTART_LSB        1
++#define HF_TIMER_CONTROL_AUTO_RESTART_MASK       0x00000002
++#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x)     (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
++#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x)     (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
++#define HF_TIMER_CONTROL_RESET_MSB               0
++#define HF_TIMER_CONTROL_RESET_LSB               0
++#define HF_TIMER_CONTROL_RESET_MASK              0x00000001
++#define HF_TIMER_CONTROL_RESET_GET(x)            (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
++#define HF_TIMER_CONTROL_RESET_SET(x)            (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
++
++#define HF_TIMER_STATUS_ADDRESS                  0x0c0000a4
++#define HF_TIMER_STATUS_OFFSET                   0x000000a4
++#define HF_TIMER_STATUS_INTERRUPT_MSB            0
++#define HF_TIMER_STATUS_INTERRUPT_LSB            0
++#define HF_TIMER_STATUS_INTERRUPT_MASK           0x00000001
++#define HF_TIMER_STATUS_INTERRUPT_GET(x)         (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
++#define HF_TIMER_STATUS_INTERRUPT_SET(x)         (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
++
++#define RTC_CONTROL_ADDRESS                      0x0c0000a8
++#define RTC_CONTROL_OFFSET                       0x000000a8
++#define RTC_CONTROL_ENABLE_MSB                   2
++#define RTC_CONTROL_ENABLE_LSB                   2
++#define RTC_CONTROL_ENABLE_MASK                  0x00000004
++#define RTC_CONTROL_ENABLE_GET(x)                (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
++#define RTC_CONTROL_ENABLE_SET(x)                (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
++#define RTC_CONTROL_LOAD_RTC_MSB                 1
++#define RTC_CONTROL_LOAD_RTC_LSB                 1
++#define RTC_CONTROL_LOAD_RTC_MASK                0x00000002
++#define RTC_CONTROL_LOAD_RTC_GET(x)              (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
++#define RTC_CONTROL_LOAD_RTC_SET(x)              (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
++#define RTC_CONTROL_LOAD_ALARM_MSB               0
++#define RTC_CONTROL_LOAD_ALARM_LSB               0
++#define RTC_CONTROL_LOAD_ALARM_MASK              0x00000001
++#define RTC_CONTROL_LOAD_ALARM_GET(x)            (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
++#define RTC_CONTROL_LOAD_ALARM_SET(x)            (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
++
++#define RTC_TIME_ADDRESS                         0x0c0000ac
++#define RTC_TIME_OFFSET                          0x000000ac
++#define RTC_TIME_WEEK_DAY_MSB                    26
++#define RTC_TIME_WEEK_DAY_LSB                    24
++#define RTC_TIME_WEEK_DAY_MASK                   0x07000000
++#define RTC_TIME_WEEK_DAY_GET(x)                 (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
++#define RTC_TIME_WEEK_DAY_SET(x)                 (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
++#define RTC_TIME_HOUR_MSB                        21
++#define RTC_TIME_HOUR_LSB                        16
++#define RTC_TIME_HOUR_MASK                       0x003f0000
++#define RTC_TIME_HOUR_GET(x)                     (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
++#define RTC_TIME_HOUR_SET(x)                     (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
++#define RTC_TIME_MINUTE_MSB                      14
++#define RTC_TIME_MINUTE_LSB                      8
++#define RTC_TIME_MINUTE_MASK                     0x00007f00
++#define RTC_TIME_MINUTE_GET(x)                   (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
++#define RTC_TIME_MINUTE_SET(x)                   (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
++#define RTC_TIME_SECOND_MSB                      6
++#define RTC_TIME_SECOND_LSB                      0
++#define RTC_TIME_SECOND_MASK                     0x0000007f
++#define RTC_TIME_SECOND_GET(x)                   (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
++#define RTC_TIME_SECOND_SET(x)                   (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
++
++#define RTC_DATE_ADDRESS                         0x0c0000b0
++#define RTC_DATE_OFFSET                          0x000000b0
++#define RTC_DATE_YEAR_MSB                        23
++#define RTC_DATE_YEAR_LSB                        16
++#define RTC_DATE_YEAR_MASK                       0x00ff0000
++#define RTC_DATE_YEAR_GET(x)                     (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
++#define RTC_DATE_YEAR_SET(x)                     (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
++#define RTC_DATE_MONTH_MSB                       12
++#define RTC_DATE_MONTH_LSB                       8
++#define RTC_DATE_MONTH_MASK                      0x00001f00
++#define RTC_DATE_MONTH_GET(x)                    (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
++#define RTC_DATE_MONTH_SET(x)                    (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
++#define RTC_DATE_MONTH_DAY_MSB                   5
++#define RTC_DATE_MONTH_DAY_LSB                   0
++#define RTC_DATE_MONTH_DAY_MASK                  0x0000003f
++#define RTC_DATE_MONTH_DAY_GET(x)                (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
++#define RTC_DATE_MONTH_DAY_SET(x)                (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
++
++#define RTC_SET_TIME_ADDRESS                     0x0c0000b4
++#define RTC_SET_TIME_OFFSET                      0x000000b4
++#define RTC_SET_TIME_WEEK_DAY_MSB                26
++#define RTC_SET_TIME_WEEK_DAY_LSB                24
++#define RTC_SET_TIME_WEEK_DAY_MASK               0x07000000
++#define RTC_SET_TIME_WEEK_DAY_GET(x)             (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
++#define RTC_SET_TIME_WEEK_DAY_SET(x)             (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
++#define RTC_SET_TIME_HOUR_MSB                    21
++#define RTC_SET_TIME_HOUR_LSB                    16
++#define RTC_SET_TIME_HOUR_MASK                   0x003f0000
++#define RTC_SET_TIME_HOUR_GET(x)                 (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
++#define RTC_SET_TIME_HOUR_SET(x)                 (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
++#define RTC_SET_TIME_MINUTE_MSB                  14
++#define RTC_SET_TIME_MINUTE_LSB                  8
++#define RTC_SET_TIME_MINUTE_MASK                 0x00007f00
++#define RTC_SET_TIME_MINUTE_GET(x)               (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
++#define RTC_SET_TIME_MINUTE_SET(x)               (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
++#define RTC_SET_TIME_SECOND_MSB                  6
++#define RTC_SET_TIME_SECOND_LSB                  0
++#define RTC_SET_TIME_SECOND_MASK                 0x0000007f
++#define RTC_SET_TIME_SECOND_GET(x)               (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
++#define RTC_SET_TIME_SECOND_SET(x)               (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
++
++#define RTC_SET_DATE_ADDRESS                     0x0c0000b8
++#define RTC_SET_DATE_OFFSET                      0x000000b8
++#define RTC_SET_DATE_YEAR_MSB                    23
++#define RTC_SET_DATE_YEAR_LSB                    16
++#define RTC_SET_DATE_YEAR_MASK                   0x00ff0000
++#define RTC_SET_DATE_YEAR_GET(x)                 (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
++#define RTC_SET_DATE_YEAR_SET(x)                 (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
++#define RTC_SET_DATE_MONTH_MSB                   12
++#define RTC_SET_DATE_MONTH_LSB                   8
++#define RTC_SET_DATE_MONTH_MASK                  0x00001f00
++#define RTC_SET_DATE_MONTH_GET(x)                (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
++#define RTC_SET_DATE_MONTH_SET(x)                (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
++#define RTC_SET_DATE_MONTH_DAY_MSB               5
++#define RTC_SET_DATE_MONTH_DAY_LSB               0
++#define RTC_SET_DATE_MONTH_DAY_MASK              0x0000003f
++#define RTC_SET_DATE_MONTH_DAY_GET(x)            (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
++#define RTC_SET_DATE_MONTH_DAY_SET(x)            (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
++
++#define RTC_SET_ALARM_ADDRESS                    0x0c0000bc
++#define RTC_SET_ALARM_OFFSET                     0x000000bc
++#define RTC_SET_ALARM_HOUR_MSB                   21
++#define RTC_SET_ALARM_HOUR_LSB                   16
++#define RTC_SET_ALARM_HOUR_MASK                  0x003f0000
++#define RTC_SET_ALARM_HOUR_GET(x)                (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
++#define RTC_SET_ALARM_HOUR_SET(x)                (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
++#define RTC_SET_ALARM_MINUTE_MSB                 14
++#define RTC_SET_ALARM_MINUTE_LSB                 8
++#define RTC_SET_ALARM_MINUTE_MASK                0x00007f00
++#define RTC_SET_ALARM_MINUTE_GET(x)              (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
++#define RTC_SET_ALARM_MINUTE_SET(x)              (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
++#define RTC_SET_ALARM_SECOND_MSB                 6
++#define RTC_SET_ALARM_SECOND_LSB                 0
++#define RTC_SET_ALARM_SECOND_MASK                0x0000007f
++#define RTC_SET_ALARM_SECOND_GET(x)              (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
++#define RTC_SET_ALARM_SECOND_SET(x)              (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
++
++#define RTC_CONFIG_ADDRESS                       0x0c0000c0
++#define RTC_CONFIG_OFFSET                        0x000000c0
++#define RTC_CONFIG_BCD_MSB                       2
++#define RTC_CONFIG_BCD_LSB                       2
++#define RTC_CONFIG_BCD_MASK                      0x00000004
++#define RTC_CONFIG_BCD_GET(x)                    (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
++#define RTC_CONFIG_BCD_SET(x)                    (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
++#define RTC_CONFIG_TWELVE_HOUR_MSB               1
++#define RTC_CONFIG_TWELVE_HOUR_LSB               1
++#define RTC_CONFIG_TWELVE_HOUR_MASK              0x00000002
++#define RTC_CONFIG_TWELVE_HOUR_GET(x)            (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
++#define RTC_CONFIG_TWELVE_HOUR_SET(x)            (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
++#define RTC_CONFIG_DSE_MSB                       0
++#define RTC_CONFIG_DSE_LSB                       0
++#define RTC_CONFIG_DSE_MASK                      0x00000001
++#define RTC_CONFIG_DSE_GET(x)                    (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
++#define RTC_CONFIG_DSE_SET(x)                    (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
++
++#define RTC_ALARM_STATUS_ADDRESS                 0x0c0000c4
++#define RTC_ALARM_STATUS_OFFSET                  0x000000c4
++#define RTC_ALARM_STATUS_ENABLE_MSB              1
++#define RTC_ALARM_STATUS_ENABLE_LSB              1
++#define RTC_ALARM_STATUS_ENABLE_MASK             0x00000002
++#define RTC_ALARM_STATUS_ENABLE_GET(x)           (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
++#define RTC_ALARM_STATUS_ENABLE_SET(x)           (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
++#define RTC_ALARM_STATUS_INTERRUPT_MSB           0
++#define RTC_ALARM_STATUS_INTERRUPT_LSB           0
++#define RTC_ALARM_STATUS_INTERRUPT_MASK          0x00000001
++#define RTC_ALARM_STATUS_INTERRUPT_GET(x)        (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
++#define RTC_ALARM_STATUS_INTERRUPT_SET(x)        (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
++
++#define UART_WAKEUP_ADDRESS                      0x0c0000c8
++#define UART_WAKEUP_OFFSET                       0x000000c8
++#define UART_WAKEUP_ENABLE_MSB                   0
++#define UART_WAKEUP_ENABLE_LSB                   0
++#define UART_WAKEUP_ENABLE_MASK                  0x00000001
++#define UART_WAKEUP_ENABLE_GET(x)                (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
++#define UART_WAKEUP_ENABLE_SET(x)                (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
++
++#define RESET_CAUSE_ADDRESS                      0x0c0000cc
++#define RESET_CAUSE_OFFSET                       0x000000cc
++#define RESET_CAUSE_LAST_MSB                     2
++#define RESET_CAUSE_LAST_LSB                     0
++#define RESET_CAUSE_LAST_MASK                    0x00000007
++#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
++#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
++
++#define SYSTEM_SLEEP_ADDRESS                     0x0c0000d0
++#define SYSTEM_SLEEP_OFFSET                      0x000000d0
++#define SYSTEM_SLEEP_HOST_IF_MSB                 4
++#define SYSTEM_SLEEP_HOST_IF_LSB                 4
++#define SYSTEM_SLEEP_HOST_IF_MASK                0x00000010
++#define SYSTEM_SLEEP_HOST_IF_GET(x)              (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
++#define SYSTEM_SLEEP_HOST_IF_SET(x)              (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
++#define SYSTEM_SLEEP_MBOX_MSB                    3
++#define SYSTEM_SLEEP_MBOX_LSB                    3
++#define SYSTEM_SLEEP_MBOX_MASK                   0x00000008
++#define SYSTEM_SLEEP_MBOX_GET(x)                 (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
++#define SYSTEM_SLEEP_MBOX_SET(x)                 (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
++#define SYSTEM_SLEEP_MAC_IF_MSB                  2
++#define SYSTEM_SLEEP_MAC_IF_LSB                  2
++#define SYSTEM_SLEEP_MAC_IF_MASK                 0x00000004
++#define SYSTEM_SLEEP_MAC_IF_GET(x)               (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
++#define SYSTEM_SLEEP_MAC_IF_SET(x)               (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
++#define SYSTEM_SLEEP_LIGHT_MSB                   1
++#define SYSTEM_SLEEP_LIGHT_LSB                   1
++#define SYSTEM_SLEEP_LIGHT_MASK                  0x00000002
++#define SYSTEM_SLEEP_LIGHT_GET(x)                (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
++#define SYSTEM_SLEEP_LIGHT_SET(x)                (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
++#define SYSTEM_SLEEP_DISABLE_MSB                 0
++#define SYSTEM_SLEEP_DISABLE_LSB                 0
++#define SYSTEM_SLEEP_DISABLE_MASK                0x00000001
++#define SYSTEM_SLEEP_DISABLE_GET(x)              (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
++#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
++
++#define LDO_VOLTAGE_ADDRESS                      0x0c0000d4
++#define LDO_VOLTAGE_OFFSET                       0x000000d4
++#define LDO_VOLTAGE_SLEEP_MSB                    14
++#define LDO_VOLTAGE_SLEEP_LSB                    12
++#define LDO_VOLTAGE_SLEEP_MASK                   0x00007000
++#define LDO_VOLTAGE_SLEEP_GET(x)                 (((x) & LDO_VOLTAGE_SLEEP_MASK) >> LDO_VOLTAGE_SLEEP_LSB)
++#define LDO_VOLTAGE_SLEEP_SET(x)                 (((x) << LDO_VOLTAGE_SLEEP_LSB) & LDO_VOLTAGE_SLEEP_MASK)
++#define LDO_VOLTAGE_WAKEUP_MSB                   10
++#define LDO_VOLTAGE_WAKEUP_LSB                   8
++#define LDO_VOLTAGE_WAKEUP_MASK                  0x00000700
++#define LDO_VOLTAGE_WAKEUP_GET(x)                (((x) & LDO_VOLTAGE_WAKEUP_MASK) >> LDO_VOLTAGE_WAKEUP_LSB)
++#define LDO_VOLTAGE_WAKEUP_SET(x)                (((x) << LDO_VOLTAGE_WAKEUP_LSB) & LDO_VOLTAGE_WAKEUP_MASK)
++#define LDO_VOLTAGE_SOC_ON_MSB                   6
++#define LDO_VOLTAGE_SOC_ON_LSB                   4
++#define LDO_VOLTAGE_SOC_ON_MASK                  0x00000070
++#define LDO_VOLTAGE_SOC_ON_GET(x)                (((x) & LDO_VOLTAGE_SOC_ON_MASK) >> LDO_VOLTAGE_SOC_ON_LSB)
++#define LDO_VOLTAGE_SOC_ON_SET(x)                (((x) << LDO_VOLTAGE_SOC_ON_LSB) & LDO_VOLTAGE_SOC_ON_MASK)
++#define LDO_VOLTAGE_ON_MSB                       2
++#define LDO_VOLTAGE_ON_LSB                       0
++#define LDO_VOLTAGE_ON_MASK                      0x00000007
++#define LDO_VOLTAGE_ON_GET(x)                    (((x) & LDO_VOLTAGE_ON_MASK) >> LDO_VOLTAGE_ON_LSB)
++#define LDO_VOLTAGE_ON_SET(x)                    (((x) << LDO_VOLTAGE_ON_LSB) & LDO_VOLTAGE_ON_MASK)
++
++#define LDO_A_VOLTAGE_ADDRESS                    0x0c0000d8
++#define LDO_A_VOLTAGE_OFFSET                     0x000000d8
++#define LDO_A_VOLTAGE_SLEEP_MSB                  14
++#define LDO_A_VOLTAGE_SLEEP_LSB                  12
++#define LDO_A_VOLTAGE_SLEEP_MASK                 0x00007000
++#define LDO_A_VOLTAGE_SLEEP_GET(x)               (((x) & LDO_A_VOLTAGE_SLEEP_MASK) >> LDO_A_VOLTAGE_SLEEP_LSB)
++#define LDO_A_VOLTAGE_SLEEP_SET(x)               (((x) << LDO_A_VOLTAGE_SLEEP_LSB) & LDO_A_VOLTAGE_SLEEP_MASK)
++#define LDO_A_VOLTAGE_WAKEUP_MSB                 10
++#define LDO_A_VOLTAGE_WAKEUP_LSB                 8
++#define LDO_A_VOLTAGE_WAKEUP_MASK                0x00000700
++#define LDO_A_VOLTAGE_WAKEUP_GET(x)              (((x) & LDO_A_VOLTAGE_WAKEUP_MASK) >> LDO_A_VOLTAGE_WAKEUP_LSB)
++#define LDO_A_VOLTAGE_WAKEUP_SET(x)              (((x) << LDO_A_VOLTAGE_WAKEUP_LSB) & LDO_A_VOLTAGE_WAKEUP_MASK)
++#define LDO_A_VOLTAGE_SOC_ON_MSB                 6
++#define LDO_A_VOLTAGE_SOC_ON_LSB                 4
++#define LDO_A_VOLTAGE_SOC_ON_MASK                0x00000070
++#define LDO_A_VOLTAGE_SOC_ON_GET(x)              (((x) & LDO_A_VOLTAGE_SOC_ON_MASK) >> LDO_A_VOLTAGE_SOC_ON_LSB)
++#define LDO_A_VOLTAGE_SOC_ON_SET(x)              (((x) << LDO_A_VOLTAGE_SOC_ON_LSB) & LDO_A_VOLTAGE_SOC_ON_MASK)
++#define LDO_A_VOLTAGE_ON_MSB                     2
++#define LDO_A_VOLTAGE_ON_LSB                     0
++#define LDO_A_VOLTAGE_ON_MASK                    0x00000007
++#define LDO_A_VOLTAGE_ON_GET(x)                  (((x) & LDO_A_VOLTAGE_ON_MASK) >> LDO_A_VOLTAGE_ON_LSB)
++#define LDO_A_VOLTAGE_ON_SET(x)                  (((x) << LDO_A_VOLTAGE_ON_LSB) & LDO_A_VOLTAGE_ON_MASK)
++
++#define SDIO_LDO_VOLTAGE_ADDRESS                 0x0c0000dc
++#define SDIO_LDO_VOLTAGE_OFFSET                  0x000000dc
++#define SDIO_LDO_VOLTAGE_OFF_MSB                 18
++#define SDIO_LDO_VOLTAGE_OFF_LSB                 16
++#define SDIO_LDO_VOLTAGE_OFF_MASK                0x00070000
++#define SDIO_LDO_VOLTAGE_OFF_GET(x)              (((x) & SDIO_LDO_VOLTAGE_OFF_MASK) >> SDIO_LDO_VOLTAGE_OFF_LSB)
++#define SDIO_LDO_VOLTAGE_OFF_SET(x)              (((x) << SDIO_LDO_VOLTAGE_OFF_LSB) & SDIO_LDO_VOLTAGE_OFF_MASK)
++#define SDIO_LDO_VOLTAGE_SLEEP_MSB               14
++#define SDIO_LDO_VOLTAGE_SLEEP_LSB               12
++#define SDIO_LDO_VOLTAGE_SLEEP_MASK              0x00007000
++#define SDIO_LDO_VOLTAGE_SLEEP_GET(x)            (((x) & SDIO_LDO_VOLTAGE_SLEEP_MASK) >> SDIO_LDO_VOLTAGE_SLEEP_LSB)
++#define SDIO_LDO_VOLTAGE_SLEEP_SET(x)            (((x) << SDIO_LDO_VOLTAGE_SLEEP_LSB) & SDIO_LDO_VOLTAGE_SLEEP_MASK)
++#define SDIO_LDO_VOLTAGE_WAKEUP_MSB              10
++#define SDIO_LDO_VOLTAGE_WAKEUP_LSB              8
++#define SDIO_LDO_VOLTAGE_WAKEUP_MASK             0x00000700
++#define SDIO_LDO_VOLTAGE_WAKEUP_GET(x)           (((x) & SDIO_LDO_VOLTAGE_WAKEUP_MASK) >> SDIO_LDO_VOLTAGE_WAKEUP_LSB)
++#define SDIO_LDO_VOLTAGE_WAKEUP_SET(x)           (((x) << SDIO_LDO_VOLTAGE_WAKEUP_LSB) & SDIO_LDO_VOLTAGE_WAKEUP_MASK)
++#define SDIO_LDO_VOLTAGE_SOC_ON_MSB              6
++#define SDIO_LDO_VOLTAGE_SOC_ON_LSB              4
++#define SDIO_LDO_VOLTAGE_SOC_ON_MASK             0x00000070
++#define SDIO_LDO_VOLTAGE_SOC_ON_GET(x)           (((x) & SDIO_LDO_VOLTAGE_SOC_ON_MASK) >> SDIO_LDO_VOLTAGE_SOC_ON_LSB)
++#define SDIO_LDO_VOLTAGE_SOC_ON_SET(x)           (((x) << SDIO_LDO_VOLTAGE_SOC_ON_LSB) & SDIO_LDO_VOLTAGE_SOC_ON_MASK)
++#define SDIO_LDO_VOLTAGE_ON_MSB                  2
++#define SDIO_LDO_VOLTAGE_ON_LSB                  0
++#define SDIO_LDO_VOLTAGE_ON_MASK                 0x00000007
++#define SDIO_LDO_VOLTAGE_ON_GET(x)               (((x) & SDIO_LDO_VOLTAGE_ON_MASK) >> SDIO_LDO_VOLTAGE_ON_LSB)
++#define SDIO_LDO_VOLTAGE_ON_SET(x)               (((x) << SDIO_LDO_VOLTAGE_ON_LSB) & SDIO_LDO_VOLTAGE_ON_MASK)
++
++#define CORE_PAD_ENABLE_ADDRESS                  0x0c0000e0
++#define CORE_PAD_ENABLE_OFFSET                   0x000000e0
++#define CORE_PAD_ENABLE_SLEEP_MSB                3
++#define CORE_PAD_ENABLE_SLEEP_LSB                3
++#define CORE_PAD_ENABLE_SLEEP_MASK               0x00000008
++#define CORE_PAD_ENABLE_SLEEP_GET(x)             (((x) & CORE_PAD_ENABLE_SLEEP_MASK) >> CORE_PAD_ENABLE_SLEEP_LSB)
++#define CORE_PAD_ENABLE_SLEEP_SET(x)             (((x) << CORE_PAD_ENABLE_SLEEP_LSB) & CORE_PAD_ENABLE_SLEEP_MASK)
++#define CORE_PAD_ENABLE_WAKEUP_MSB               2
++#define CORE_PAD_ENABLE_WAKEUP_LSB               2
++#define CORE_PAD_ENABLE_WAKEUP_MASK              0x00000004
++#define CORE_PAD_ENABLE_WAKEUP_GET(x)            (((x) & CORE_PAD_ENABLE_WAKEUP_MASK) >> CORE_PAD_ENABLE_WAKEUP_LSB)
++#define CORE_PAD_ENABLE_WAKEUP_SET(x)            (((x) << CORE_PAD_ENABLE_WAKEUP_LSB) & CORE_PAD_ENABLE_WAKEUP_MASK)
++#define CORE_PAD_ENABLE_SOC_ON_MSB               1
++#define CORE_PAD_ENABLE_SOC_ON_LSB               1
++#define CORE_PAD_ENABLE_SOC_ON_MASK              0x00000002
++#define CORE_PAD_ENABLE_SOC_ON_GET(x)            (((x) & CORE_PAD_ENABLE_SOC_ON_MASK) >> CORE_PAD_ENABLE_SOC_ON_LSB)
++#define CORE_PAD_ENABLE_SOC_ON_SET(x)            (((x) << CORE_PAD_ENABLE_SOC_ON_LSB) & CORE_PAD_ENABLE_SOC_ON_MASK)
++#define CORE_PAD_ENABLE_ON_MSB                   0
++#define CORE_PAD_ENABLE_ON_LSB                   0
++#define CORE_PAD_ENABLE_ON_MASK                  0x00000001
++#define CORE_PAD_ENABLE_ON_GET(x)                (((x) & CORE_PAD_ENABLE_ON_MASK) >> CORE_PAD_ENABLE_ON_LSB)
++#define CORE_PAD_ENABLE_ON_SET(x)                (((x) << CORE_PAD_ENABLE_ON_LSB) & CORE_PAD_ENABLE_ON_MASK)
++
++#define SDIO_WRAPPER_ADDRESS                     0x0c0000e4
++#define SDIO_WRAPPER_OFFSET                      0x000000e4
++#define SDIO_WRAPPER_SLEEP_MSB                   3
++#define SDIO_WRAPPER_SLEEP_LSB                   3
++#define SDIO_WRAPPER_SLEEP_MASK                  0x00000008
++#define SDIO_WRAPPER_SLEEP_GET(x)                (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
++#define SDIO_WRAPPER_SLEEP_SET(x)                (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
++#define SDIO_WRAPPER_WAKEUP_MSB                  2
++#define SDIO_WRAPPER_WAKEUP_LSB                  2
++#define SDIO_WRAPPER_WAKEUP_MASK                 0x00000004
++#define SDIO_WRAPPER_WAKEUP_GET(x)               (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
++#define SDIO_WRAPPER_WAKEUP_SET(x)               (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
++#define SDIO_WRAPPER_SOC_ON_MSB                  1
++#define SDIO_WRAPPER_SOC_ON_LSB                  1
++#define SDIO_WRAPPER_SOC_ON_MASK                 0x00000002
++#define SDIO_WRAPPER_SOC_ON_GET(x)               (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
++#define SDIO_WRAPPER_SOC_ON_SET(x)               (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
++#define SDIO_WRAPPER_ON_MSB                      0
++#define SDIO_WRAPPER_ON_LSB                      0
++#define SDIO_WRAPPER_ON_MASK                     0x00000001
++#define SDIO_WRAPPER_ON_GET(x)                   (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
++#define SDIO_WRAPPER_ON_SET(x)                   (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
++
++#define MAC_SLEEP_CONTROL_ADDRESS                0x0c0000e8
++#define MAC_SLEEP_CONTROL_OFFSET                 0x000000e8
++#define MAC_SLEEP_CONTROL_ENABLE_MSB             1
++#define MAC_SLEEP_CONTROL_ENABLE_LSB             0
++#define MAC_SLEEP_CONTROL_ENABLE_MASK            0x00000003
++#define MAC_SLEEP_CONTROL_ENABLE_GET(x)          (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
++#define MAC_SLEEP_CONTROL_ENABLE_SET(x)          (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
++
++#define KEEP_AWAKE_ADDRESS                       0x0c0000ec
++#define KEEP_AWAKE_OFFSET                        0x000000ec
++#define KEEP_AWAKE_COUNT_MSB                     7
++#define KEEP_AWAKE_COUNT_LSB                     0
++#define KEEP_AWAKE_COUNT_MASK                    0x000000ff
++#define KEEP_AWAKE_COUNT_GET(x)                  (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
++#define KEEP_AWAKE_COUNT_SET(x)                  (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
++
++#define CHIP_REV_ADDRESS                         0x0c0000f0
++#define CHIP_REV_OFFSET                          0x000000f0
++#define CHIP_REV_ID_MSB                          7
++#define CHIP_REV_ID_LSB                          0
++#define CHIP_REV_ID_MASK                         0x000000ff
++#define CHIP_REV_ID_GET(x)                       (((x) & CHIP_REV_ID_MASK) >> CHIP_REV_ID_LSB)
++#define CHIP_REV_ID_SET(x)                       (((x) << CHIP_REV_ID_LSB) & CHIP_REV_ID_MASK)
++
++#define DERIVED_RTC_CLK_ADDRESS                  0x0c0000f4
++#define DERIVED_RTC_CLK_OFFSET                   0x000000f4
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB      18
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB      18
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK     0x00040000
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)   (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)   (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
++#define DERIVED_RTC_CLK_FORCE_MSB                17
++#define DERIVED_RTC_CLK_FORCE_LSB                16
++#define DERIVED_RTC_CLK_FORCE_MASK               0x00030000
++#define DERIVED_RTC_CLK_FORCE_GET(x)             (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
++#define DERIVED_RTC_CLK_FORCE_SET(x)             (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
++#define DERIVED_RTC_CLK_PERIOD_MSB               15
++#define DERIVED_RTC_CLK_PERIOD_LSB               1
++#define DERIVED_RTC_CLK_PERIOD_MASK              0x0000fffe
++#define DERIVED_RTC_CLK_PERIOD_GET(x)            (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
++#define DERIVED_RTC_CLK_PERIOD_SET(x)            (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
++
++#define ACG_DISABLE_ADDRESS                      0x0c0000f8
++#define ACG_DISABLE_OFFSET                       0x000000f8
++#define ACG_DISABLE_CPU_MSB                      3
++#define ACG_DISABLE_CPU_LSB                      3
++#define ACG_DISABLE_CPU_MASK                     0x00000008
++#define ACG_DISABLE_CPU_GET(x)                   (((x) & ACG_DISABLE_CPU_MASK) >> ACG_DISABLE_CPU_LSB)
++#define ACG_DISABLE_CPU_SET(x)                   (((x) << ACG_DISABLE_CPU_LSB) & ACG_DISABLE_CPU_MASK)
++#define ACG_DISABLE_SDIO_MSB                     2
++#define ACG_DISABLE_SDIO_LSB                     2
++#define ACG_DISABLE_SDIO_MASK                    0x00000004
++#define ACG_DISABLE_SDIO_GET(x)                  (((x) & ACG_DISABLE_SDIO_MASK) >> ACG_DISABLE_SDIO_LSB)
++#define ACG_DISABLE_SDIO_SET(x)                  (((x) << ACG_DISABLE_SDIO_LSB) & ACG_DISABLE_SDIO_MASK)
++#define ACG_DISABLE_BB_AND_BBB_MSB               1
++#define ACG_DISABLE_BB_AND_BBB_LSB               1
++#define ACG_DISABLE_BB_AND_BBB_MASK              0x00000002
++#define ACG_DISABLE_BB_AND_BBB_GET(x)            (((x) & ACG_DISABLE_BB_AND_BBB_MASK) >> ACG_DISABLE_BB_AND_BBB_LSB)
++#define ACG_DISABLE_BB_AND_BBB_SET(x)            (((x) << ACG_DISABLE_BB_AND_BBB_LSB) & ACG_DISABLE_BB_AND_BBB_MASK)
++#define ACG_DISABLE_AMBA_MAC_MSB                 0
++#define ACG_DISABLE_AMBA_MAC_LSB                 0
++#define ACG_DISABLE_AMBA_MAC_MASK                0x00000001
++#define ACG_DISABLE_AMBA_MAC_GET(x)              (((x) & ACG_DISABLE_AMBA_MAC_MASK) >> ACG_DISABLE_AMBA_MAC_LSB)
++#define ACG_DISABLE_AMBA_MAC_SET(x)              (((x) << ACG_DISABLE_AMBA_MAC_LSB) & ACG_DISABLE_AMBA_MAC_MASK)
++
++#define KEY_ENABLE_ADDRESS                       0x0c0000fc
++#define KEY_ENABLE_OFFSET                        0x000000fc
++#define KEY_ENABLE_ON_MSB                        0
++#define KEY_ENABLE_ON_LSB                        0
++#define KEY_ENABLE_ON_MASK                       0x00000001
++#define KEY_ENABLE_ON_GET(x)                     (((x) & KEY_ENABLE_ON_MASK) >> KEY_ENABLE_ON_LSB)
++#define KEY_ENABLE_ON_SET(x)                     (((x) << KEY_ENABLE_ON_LSB) & KEY_ENABLE_ON_MASK)
++
++#define KEY_DEBOUNCE_ADDRESS                     0x0c000100
++#define KEY_DEBOUNCE_OFFSET                      0x00000100
++#define KEY_DEBOUNCE_TIME_MSB                    3
++#define KEY_DEBOUNCE_TIME_LSB                    0
++#define KEY_DEBOUNCE_TIME_MASK                   0x0000000f
++#define KEY_DEBOUNCE_TIME_GET(x)                 (((x) & KEY_DEBOUNCE_TIME_MASK) >> KEY_DEBOUNCE_TIME_LSB)
++#define KEY_DEBOUNCE_TIME_SET(x)                 (((x) << KEY_DEBOUNCE_TIME_LSB) & KEY_DEBOUNCE_TIME_MASK)
++
++#define KEY_LONG_PRESS_ADDRESS                   0x0c000104
++#define KEY_LONG_PRESS_OFFSET                    0x00000104
++#define KEY_LONG_PRESS_TIME_MSB                  5
++#define KEY_LONG_PRESS_TIME_LSB                  0
++#define KEY_LONG_PRESS_TIME_MASK                 0x0000003f
++#define KEY_LONG_PRESS_TIME_GET(x)               (((x) & KEY_LONG_PRESS_TIME_MASK) >> KEY_LONG_PRESS_TIME_LSB)
++#define KEY_LONG_PRESS_TIME_SET(x)               (((x) << KEY_LONG_PRESS_TIME_LSB) & KEY_LONG_PRESS_TIME_MASK)
++
++#define KEY_REPEAT_ADDRESS                       0x0c000108
++#define KEY_REPEAT_OFFSET                        0x00000108
++#define KEY_REPEAT_TIME_MSB                      5
++#define KEY_REPEAT_TIME_LSB                      0
++#define KEY_REPEAT_TIME_MASK                     0x0000003f
++#define KEY_REPEAT_TIME_GET(x)                   (((x) & KEY_REPEAT_TIME_MASK) >> KEY_REPEAT_TIME_LSB)
++#define KEY_REPEAT_TIME_SET(x)                   (((x) << KEY_REPEAT_TIME_LSB) & KEY_REPEAT_TIME_MASK)
++
++#define KEY_MATRIX_LO_ADDRESS                    0x0c00010c
++#define KEY_MATRIX_LO_OFFSET                     0x0000010c
++#define KEY_MATRIX_LO_ROW0_MSB                   31
++#define KEY_MATRIX_LO_ROW0_LSB                   24
++#define KEY_MATRIX_LO_ROW0_MASK                  0xff000000
++#define KEY_MATRIX_LO_ROW0_GET(x)                (((x) & KEY_MATRIX_LO_ROW0_MASK) >> KEY_MATRIX_LO_ROW0_LSB)
++#define KEY_MATRIX_LO_ROW0_SET(x)                (((x) << KEY_MATRIX_LO_ROW0_LSB) & KEY_MATRIX_LO_ROW0_MASK)
++#define KEY_MATRIX_LO_ROW1_MSB                   23
++#define KEY_MATRIX_LO_ROW1_LSB                   16
++#define KEY_MATRIX_LO_ROW1_MASK                  0x00ff0000
++#define KEY_MATRIX_LO_ROW1_GET(x)                (((x) & KEY_MATRIX_LO_ROW1_MASK) >> KEY_MATRIX_LO_ROW1_LSB)
++#define KEY_MATRIX_LO_ROW1_SET(x)                (((x) << KEY_MATRIX_LO_ROW1_LSB) & KEY_MATRIX_LO_ROW1_MASK)
++#define KEY_MATRIX_LO_ROW2_MSB                   15
++#define KEY_MATRIX_LO_ROW2_LSB                   8
++#define KEY_MATRIX_LO_ROW2_MASK                  0x0000ff00
++#define KEY_MATRIX_LO_ROW2_GET(x)                (((x) & KEY_MATRIX_LO_ROW2_MASK) >> KEY_MATRIX_LO_ROW2_LSB)
++#define KEY_MATRIX_LO_ROW2_SET(x)                (((x) << KEY_MATRIX_LO_ROW2_LSB) & KEY_MATRIX_LO_ROW2_MASK)
++#define KEY_MATRIX_LO_ROW3_MSB                   7
++#define KEY_MATRIX_LO_ROW3_LSB                   0
++#define KEY_MATRIX_LO_ROW3_MASK                  0x000000ff
++#define KEY_MATRIX_LO_ROW3_GET(x)                (((x) & KEY_MATRIX_LO_ROW3_MASK) >> KEY_MATRIX_LO_ROW3_LSB)
++#define KEY_MATRIX_LO_ROW3_SET(x)                (((x) << KEY_MATRIX_LO_ROW3_LSB) & KEY_MATRIX_LO_ROW3_MASK)
++
++#define KEY_MATRIX_HI_ADDRESS                    0x0c000110
++#define KEY_MATRIX_HI_OFFSET                     0x00000110
++#define KEY_MATRIX_HI_ROW4_MSB                   31
++#define KEY_MATRIX_HI_ROW4_LSB                   24
++#define KEY_MATRIX_HI_ROW4_MASK                  0xff000000
++#define KEY_MATRIX_HI_ROW4_GET(x)                (((x) & KEY_MATRIX_HI_ROW4_MASK) >> KEY_MATRIX_HI_ROW4_LSB)
++#define KEY_MATRIX_HI_ROW4_SET(x)                (((x) << KEY_MATRIX_HI_ROW4_LSB) & KEY_MATRIX_HI_ROW4_MASK)
++#define KEY_MATRIX_HI_ROW5_MSB                   23
++#define KEY_MATRIX_HI_ROW5_LSB                   16
++#define KEY_MATRIX_HI_ROW5_MASK                  0x00ff0000
++#define KEY_MATRIX_HI_ROW5_GET(x)                (((x) & KEY_MATRIX_HI_ROW5_MASK) >> KEY_MATRIX_HI_ROW5_LSB)
++#define KEY_MATRIX_HI_ROW5_SET(x)                (((x) << KEY_MATRIX_HI_ROW5_LSB) & KEY_MATRIX_HI_ROW5_MASK)
++#define KEY_MATRIX_HI_ROW6_MSB                   15
++#define KEY_MATRIX_HI_ROW6_LSB                   8
++#define KEY_MATRIX_HI_ROW6_MASK                  0x0000ff00
++#define KEY_MATRIX_HI_ROW6_GET(x)                (((x) & KEY_MATRIX_HI_ROW6_MASK) >> KEY_MATRIX_HI_ROW6_LSB)
++#define KEY_MATRIX_HI_ROW6_SET(x)                (((x) << KEY_MATRIX_HI_ROW6_LSB) & KEY_MATRIX_HI_ROW6_MASK)
++#define KEY_MATRIX_HI_ROW7_MSB                   7
++#define KEY_MATRIX_HI_ROW7_LSB                   0
++#define KEY_MATRIX_HI_ROW7_MASK                  0x000000ff
++#define KEY_MATRIX_HI_ROW7_GET(x)                (((x) & KEY_MATRIX_HI_ROW7_MASK) >> KEY_MATRIX_HI_ROW7_LSB)
++#define KEY_MATRIX_HI_ROW7_SET(x)                (((x) << KEY_MATRIX_HI_ROW7_LSB) & KEY_MATRIX_HI_ROW7_MASK)
++
++#define KEY_CODE_ADDRESS                         0x0c000114
++#define KEY_CODE_OFFSET                          0x00000114
++#define KEY_CODE_MULTIPRESS_MSB                  7
++#define KEY_CODE_MULTIPRESS_LSB                  7
++#define KEY_CODE_MULTIPRESS_MASK                 0x00000080
++#define KEY_CODE_MULTIPRESS_GET(x)               (((x) & KEY_CODE_MULTIPRESS_MASK) >> KEY_CODE_MULTIPRESS_LSB)
++#define KEY_CODE_MULTIPRESS_SET(x)               (((x) << KEY_CODE_MULTIPRESS_LSB) & KEY_CODE_MULTIPRESS_MASK)
++#define KEY_CODE_ROW_MSB                         6
++#define KEY_CODE_ROW_LSB                         4
++#define KEY_CODE_ROW_MASK                        0x00000070
++#define KEY_CODE_ROW_GET(x)                      (((x) & KEY_CODE_ROW_MASK) >> KEY_CODE_ROW_LSB)
++#define KEY_CODE_ROW_SET(x)                      (((x) << KEY_CODE_ROW_LSB) & KEY_CODE_ROW_MASK)
++#define KEY_CODE_COL_MSB                         2
++#define KEY_CODE_COL_LSB                         0
++#define KEY_CODE_COL_MASK                        0x00000007
++#define KEY_CODE_COL_GET(x)                      (((x) & KEY_CODE_COL_MASK) >> KEY_CODE_COL_LSB)
++#define KEY_CODE_COL_SET(x)                      (((x) << KEY_CODE_COL_LSB) & KEY_CODE_COL_MASK)
++
++#define KEY_STATUS_ADDRESS                       0x0c000118
++#define KEY_STATUS_OFFSET                        0x00000118
++#define KEY_STATUS_KEY_RELEASE_ENABLE_MSB        7
++#define KEY_STATUS_KEY_RELEASE_ENABLE_LSB        7
++#define KEY_STATUS_KEY_RELEASE_ENABLE_MASK       0x00000080
++#define KEY_STATUS_KEY_RELEASE_ENABLE_GET(x)     (((x) & KEY_STATUS_KEY_RELEASE_ENABLE_MASK) >> KEY_STATUS_KEY_RELEASE_ENABLE_LSB)
++#define KEY_STATUS_KEY_RELEASE_ENABLE_SET(x)     (((x) << KEY_STATUS_KEY_RELEASE_ENABLE_LSB) & KEY_STATUS_KEY_RELEASE_ENABLE_MASK)
++#define KEY_STATUS_FIRST_PRESS_ENABLE_MSB        6
++#define KEY_STATUS_FIRST_PRESS_ENABLE_LSB        6
++#define KEY_STATUS_FIRST_PRESS_ENABLE_MASK       0x00000040
++#define KEY_STATUS_FIRST_PRESS_ENABLE_GET(x)     (((x) & KEY_STATUS_FIRST_PRESS_ENABLE_MASK) >> KEY_STATUS_FIRST_PRESS_ENABLE_LSB)
++#define KEY_STATUS_FIRST_PRESS_ENABLE_SET(x)     (((x) << KEY_STATUS_FIRST_PRESS_ENABLE_LSB) & KEY_STATUS_FIRST_PRESS_ENABLE_MASK)
++#define KEY_STATUS_LONG_PRESS_ENABLE_MSB         5
++#define KEY_STATUS_LONG_PRESS_ENABLE_LSB         5
++#define KEY_STATUS_LONG_PRESS_ENABLE_MASK        0x00000020
++#define KEY_STATUS_LONG_PRESS_ENABLE_GET(x)      (((x) & KEY_STATUS_LONG_PRESS_ENABLE_MASK) >> KEY_STATUS_LONG_PRESS_ENABLE_LSB)
++#define KEY_STATUS_LONG_PRESS_ENABLE_SET(x)      (((x) << KEY_STATUS_LONG_PRESS_ENABLE_LSB) & KEY_STATUS_LONG_PRESS_ENABLE_MASK)
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_MSB       4
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_LSB       4
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_MASK      0x00000010
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_GET(x)    (((x) & KEY_STATUS_REPEAT_PRESS_ENABLE_MASK) >> KEY_STATUS_REPEAT_PRESS_ENABLE_LSB)
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_SET(x)    (((x) << KEY_STATUS_REPEAT_PRESS_ENABLE_LSB) & KEY_STATUS_REPEAT_PRESS_ENABLE_MASK)
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_MSB     3
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB     3
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK    0x00000008
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_GET(x)  (((x) & KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK) >> KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB)
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_SET(x)  (((x) << KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB) & KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK)
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_MSB     2
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB     2
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK    0x00000004
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_GET(x)  (((x) & KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK) >> KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_SET(x)  (((x) << KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB) & KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK)
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_MSB      1
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_LSB      1
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_MASK     0x00000002
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_GET(x)   (((x) & KEY_STATUS_LONG_PRESS_INTERRUPT_MASK) >> KEY_STATUS_LONG_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_SET(x)   (((x) << KEY_STATUS_LONG_PRESS_INTERRUPT_LSB) & KEY_STATUS_LONG_PRESS_INTERRUPT_MASK)
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_MSB    0
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB    0
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK   0x00000001
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_GET(x) (((x) & KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK) >> KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_SET(x) (((x) << KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB) & KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct rtc_reg_s {
++  volatile unsigned int reset_control;
++  volatile unsigned int xtal_control;
++  volatile unsigned int tcxo_detect;
++  volatile unsigned int xtal_test;
++  volatile unsigned int quadrature;
++  volatile unsigned int pll_control;
++  volatile unsigned int pll_settle;
++  volatile unsigned int xtal_settle;
++  volatile unsigned int core_clock;
++  volatile unsigned int cpu_clock;
++  volatile unsigned int clock_out;
++  volatile unsigned int clock_control;
++  volatile unsigned int bias_override;
++  volatile unsigned int ref_voltage_trim;
++  volatile unsigned int ldo_control;
++  volatile unsigned int wdt_control;
++  volatile unsigned int wdt_status;
++  volatile unsigned int wdt;
++  volatile unsigned int wdt_count;
++  volatile unsigned int wdt_reset;
++  volatile unsigned int int_status;
++  volatile unsigned int lf_timer0;
++  volatile unsigned int lf_timer_count0;
++  volatile unsigned int lf_timer_control0;
++  volatile unsigned int lf_timer_status0;
++  volatile unsigned int lf_timer1;
++  volatile unsigned int lf_timer_count1;
++  volatile unsigned int lf_timer_control1;
++  volatile unsigned int lf_timer_status1;
++  volatile unsigned int lf_timer2;
++  volatile unsigned int lf_timer_count2;
++  volatile unsigned int lf_timer_control2;
++  volatile unsigned int lf_timer_status2;
++  volatile unsigned int lf_timer3;
++  volatile unsigned int lf_timer_count3;
++  volatile unsigned int lf_timer_control3;
++  volatile unsigned int lf_timer_status3;
++  volatile unsigned int hf_timer;
++  volatile unsigned int hf_timer_count;
++  volatile unsigned int hf_lf_count;
++  volatile unsigned int hf_timer_control;
++  volatile unsigned int hf_timer_status;
++  volatile unsigned int rtc_control;
++  volatile unsigned int rtc_time;
++  volatile unsigned int rtc_date;
++  volatile unsigned int rtc_set_time;
++  volatile unsigned int rtc_set_date;
++  volatile unsigned int rtc_set_alarm;
++  volatile unsigned int rtc_config;
++  volatile unsigned int rtc_alarm_status;
++  volatile unsigned int uart_wakeup;
++  volatile unsigned int reset_cause;
++  volatile unsigned int system_sleep;
++  volatile unsigned int ldo_voltage;
++  volatile unsigned int ldo_a_voltage;
++  volatile unsigned int sdio_ldo_voltage;
++  volatile unsigned int core_pad_enable;
++  volatile unsigned int sdio_wrapper;
++  volatile unsigned int mac_sleep_control;
++  volatile unsigned int keep_awake;
++  volatile unsigned int chip_rev;
++  volatile unsigned int derived_rtc_clk;
++  volatile unsigned int acg_disable;
++  volatile unsigned int key_enable;
++  volatile unsigned int key_debounce;
++  volatile unsigned int key_long_press;
++  volatile unsigned int key_repeat;
++  volatile unsigned int key_matrix_lo;
++  volatile unsigned int key_matrix_hi;
++  volatile unsigned int key_code;
++  volatile unsigned int key_status;
++} rtc_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _RTC_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,333 @@
++/*-
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 ATheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ * */
++#ifndef _NET80211_IEEE80211_H_
++#define _NET80211_IEEE80211_H_
++
++/*
++ * 802.11 protocol definitions.
++ */
++
++#define IEEE80211_ADDR_LEN  6	/* size of 802.11 address */
++/* is 802.11 address multicast/broadcast? */
++#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
++#define IEEE80211_ADDR_EQ(addr1, addr2)     \
++    (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
++
++#define IEEE80211_KEYBUF_SIZE 16
++#define IEEE80211_MICBUF_SIZE (8+8)	/* space for both tx and rx */
++
++/*
++ * NB: these values are ordered carefully; there are lots of
++ * of implications in any reordering.  In particular beware
++ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
++ */
++#define IEEE80211_CIPHER_WEP            0
++#define IEEE80211_CIPHER_TKIP           1
++#define IEEE80211_CIPHER_AES_OCB        2
++#define IEEE80211_CIPHER_AES_CCM        3
++#define IEEE80211_CIPHER_CKIP           5
++#define IEEE80211_CIPHER_CCKM_KRK       6
++#define IEEE80211_CIPHER_NONE           7	/* pseudo value */
++
++#define IEEE80211_CIPHER_MAX            (IEEE80211_CIPHER_NONE+1)
++
++#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
++        (((len) == 5) || ((len) == 13) || ((len) == 16))
++
++/*
++ * generic definitions for IEEE 802.11 frames
++ */
++struct ieee80211_frame {
++	u8 i_fc[2];
++	u8 i_dur[2];
++	u8 i_addr1[IEEE80211_ADDR_LEN];
++	u8 i_addr2[IEEE80211_ADDR_LEN];
++	u8 i_addr3[IEEE80211_ADDR_LEN];
++	u8 i_seq[2];
++	/* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
++	/* see below */
++} __ATTRIB_PACK;
++
++#define IEEE80211_FC0_VERSION_MASK          0x03
++#define IEEE80211_FC0_VERSION_SHIFT         0
++#define IEEE80211_FC0_VERSION_0             0x00
++#define IEEE80211_FC0_TYPE_MASK             0x0c
++#define IEEE80211_FC0_TYPE_SHIFT            2
++#define IEEE80211_FC0_TYPE_MGT              0x00
++#define IEEE80211_FC0_TYPE_CTL              0x04
++#define IEEE80211_FC0_TYPE_DATA             0x08
++
++#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
++#define IEEE80211_FC0_SUBTYPE_SHIFT         4
++/* for TYPE_MGT */
++#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
++#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
++#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
++#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
++#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
++#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
++#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
++#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
++#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
++#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
++#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
++/* for TYPE_CTL */
++#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
++#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
++#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
++#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
++#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
++#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
++/* for TYPE_DATA (bit combination) */
++#define IEEE80211_FC0_SUBTYPE_DATA          0x00
++#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
++#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
++#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
++#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
++#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
++#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
++#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
++#define IEEE80211_FC0_SUBTYPE_QOS           0x80
++#define IEEE80211_FC0_SUBTYPE_QOS_NULL      0xc0
++
++#define IEEE80211_FC1_DIR_MASK              0x03
++#define IEEE80211_FC1_DIR_NODS              0x00	/* STA->STA */
++#define IEEE80211_FC1_DIR_TODS              0x01	/* STA->AP */
++#define IEEE80211_FC1_DIR_FROMDS            0x02	/* AP ->STA */
++#define IEEE80211_FC1_DIR_DSTODS            0x03	/* AP ->AP */
++
++#define IEEE80211_FC1_MORE_FRAG             0x04
++#define IEEE80211_FC1_RETRY                 0x08
++#define IEEE80211_FC1_PWR_MGT               0x10
++#define IEEE80211_FC1_MORE_DATA             0x20
++#define IEEE80211_FC1_WEP                   0x40
++#define IEEE80211_FC1_ORDER                 0x80
++
++#define IEEE80211_SEQ_FRAG_MASK             0x000f
++#define IEEE80211_SEQ_FRAG_SHIFT            0
++#define IEEE80211_SEQ_SEQ_MASK              0xfff0
++#define IEEE80211_SEQ_SEQ_SHIFT             4
++
++#define IEEE80211_NWID_LEN                  32
++
++/*
++ * 802.11 rate set.
++ */
++#define IEEE80211_RATE_SIZE     8	/* 802.11 standard */
++#define IEEE80211_RATE_MAXSIZE  15	/* max rates we'll handle */
++
++#define WMM_NUM_AC                  4	/* 4 AC categories */
++
++#define WMM_PARAM_ACI_M         0x60	/* Mask for ACI field */
++#define WMM_PARAM_ACI_S         5	/* Shift for ACI field */
++#define WMM_PARAM_ACM_M         0x10	/* Mask for ACM bit */
++#define WMM_PARAM_ACM_S         4	/* Shift for ACM bit */
++#define WMM_PARAM_AIFSN_M       0x0f	/* Mask for aifsn field */
++#define WMM_PARAM_LOGCWMIN_M    0x0f	/* Mask for CwMin field (in log) */
++#define WMM_PARAM_LOGCWMAX_M    0xf0	/* Mask for CwMax field (in log) */
++#define WMM_PARAM_LOGCWMAX_S    4	/* Shift for CwMax field */
++
++#define WMM_AC_TO_TID(_ac) (       \
++    ((_ac) == WMM_AC_VO) ? 6 : \
++    ((_ac) == WMM_AC_VI) ? 5 : \
++    ((_ac) == WMM_AC_BK) ? 1 : \
++    0)
++
++#define TID_TO_WMM_AC(_tid) (      \
++    ((_tid) < 1) ? WMM_AC_BE : \
++    ((_tid) < 3) ? WMM_AC_BK : \
++    ((_tid) < 6) ? WMM_AC_VI : \
++    WMM_AC_VO)
++/*
++ * Management information element payloads.
++ */
++
++enum {
++	IEEE80211_ELEMID_SSID = 0,
++	IEEE80211_ELEMID_RATES = 1,
++	IEEE80211_ELEMID_FHPARMS = 2,
++	IEEE80211_ELEMID_DSPARMS = 3,
++	IEEE80211_ELEMID_CFPARMS = 4,
++	IEEE80211_ELEMID_TIM = 5,
++	IEEE80211_ELEMID_IBSSPARMS = 6,
++	IEEE80211_ELEMID_COUNTRY = 7,
++	IEEE80211_ELEMID_CHALLENGE = 16,
++	/* 17-31 reserved for challenge text extension */
++	IEEE80211_ELEMID_PWRCNSTR = 32,
++	IEEE80211_ELEMID_PWRCAP = 33,
++	IEEE80211_ELEMID_TPCREQ = 34,
++	IEEE80211_ELEMID_TPCREP = 35,
++	IEEE80211_ELEMID_SUPPCHAN = 36,
++	IEEE80211_ELEMID_CHANSWITCH = 37,
++	IEEE80211_ELEMID_MEASREQ = 38,
++	IEEE80211_ELEMID_MEASREP = 39,
++	IEEE80211_ELEMID_QUIET = 40,
++	IEEE80211_ELEMID_IBSSDFS = 41,
++	IEEE80211_ELEMID_ERP = 42,
++	IEEE80211_ELEMID_RSN = 48,
++	IEEE80211_ELEMID_XRATES = 50,
++	IEEE80211_ELEMID_TPC = 150,
++	IEEE80211_ELEMID_CCKM = 156,
++	IEEE80211_ELEMID_VENDOR = 221,	/* vendor private */
++};
++
++#define ATH_OUI             0x7f0300	/* Atheros OUI */
++#define ATH_OUI_TYPE        0x01
++#define ATH_OUI_SUBTYPE     0x01
++#define ATH_OUI_VERSION     0x00
++
++#define WPA_OUI             0xf25000
++#define WPA_OUI_TYPE        0x01
++#define WPA_VERSION         1	/* current supported version */
++
++#define WPA_CSE_NULL        0x00
++#define WPA_CSE_WEP40       0x01
++#define WPA_CSE_TKIP        0x02
++#define WPA_CSE_CCMP        0x04
++#define WPA_CSE_WEP104      0x05
++
++#define WPA_ASE_NONE        0x00
++#define WPA_ASE_8021X_UNSPEC    0x01
++#define WPA_ASE_8021X_PSK   0x02
++
++#define RSN_OUI         0xac0f00
++#define RSN_VERSION     1		/* current supported version */
++
++#define RSN_CSE_NULL        0x00
++#define RSN_CSE_WEP40       0x01
++#define RSN_CSE_TKIP        0x02
++#define RSN_CSE_WRAP        0x03
++#define RSN_CSE_CCMP        0x04
++#define RSN_CSE_WEP104      0x05
++
++#define RSN_ASE_NONE        0x00
++#define RSN_ASE_8021X_UNSPEC    0x01
++#define RSN_ASE_8021X_PSK   0x02
++
++#define RSN_CAP_PREAUTH     0x01
++
++#define WMM_OUI         0xf25000
++#define WMM_OUI_TYPE        0x02
++#define WMM_INFO_OUI_SUBTYPE    0x00
++#define WMM_PARAM_OUI_SUBTYPE   0x01
++#define WMM_VERSION     1
++
++/* WMM stream classes */
++#define WMM_NUM_AC  4
++#define WMM_AC_BE   0			/* best effort */
++#define WMM_AC_BK   1			/* background */
++#define WMM_AC_VI   2			/* video */
++#define WMM_AC_VO   3			/* voice */
++
++/* TSPEC related */
++#define ACTION_CATEGORY_CODE_TSPEC                 17
++#define ACTION_CODE_TSPEC_ADDTS                    0
++#define ACTION_CODE_TSPEC_ADDTS_RESP               1
++#define ACTION_CODE_TSPEC_DELTS                    2
++
++typedef enum {
++	TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
++	TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
++	TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
++	TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
++	TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
++	TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
++	TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
++	TSPEC_STATUS_CODE_DELTS_SENT = 0x30,
++	TSPEC_STATUS_CODE_DELTS_RECV = 0x31,
++} TSPEC_STATUS_CODE;
++
++/*
++ * WMM/802.11e Tspec Element
++ */
++typedef struct wmm_tspec_ie_t {
++	u8 elementId;
++	u8 len;
++	u8 oui[3];
++	u8 ouiType;
++	u8 ouiSubType;
++	u8 version;
++	u16 tsInfo_info;
++	u8 tsInfo_reserved;
++	u16 nominalMSDU;
++	u16 maxMSDU;
++	u32 minServiceInt;
++	u32 maxServiceInt;
++	u32 inactivityInt;
++	u32 suspensionInt;
++	u32 serviceStartTime;
++	u32 minDataRate;
++	u32 meanDataRate;
++	u32 peakDataRate;
++	u32 maxBurstSize;
++	u32 delayBound;
++	u32 minPhyRate;
++	u16 sba;
++	u16 mediumTime;
++} __ATTRIB_PACK WMM_TSPEC_IE;
++
++
++/*
++ * BEACON management packets
++ *
++ *  octet timestamp[8]
++ *  octet beacon interval[2]
++ *  octet capability information[2]
++ *  information element
++ *      octet elemid
++ *      octet length
++ *      octet information[length]
++ */
++
++#define IEEE80211_BEACON_INTERVAL(beacon) \
++    ((beacon)[8] | ((beacon)[9] << 8))
++#define IEEE80211_BEACON_CAPABILITY(beacon) \
++    ((beacon)[10] | ((beacon)[11] << 8))
++
++#define IEEE80211_CAPINFO_ESS               0x0001
++#define IEEE80211_CAPINFO_IBSS              0x0002
++#define IEEE80211_CAPINFO_CF_POLLABLE       0x0004
++#define IEEE80211_CAPINFO_CF_POLLREQ        0x0008
++#define IEEE80211_CAPINFO_PRIVACY           0x0010
++#define IEEE80211_CAPINFO_SHORT_PREAMBLE    0x0020
++#define IEEE80211_CAPINFO_PBCC              0x0040
++#define IEEE80211_CAPINFO_CHNL_AGILITY      0x0080
++/* bits 8-9 are reserved */
++#define IEEE80211_CAPINFO_SHORT_SLOTTIME    0x0400
++#define IEEE80211_CAPINFO_APSD              0x0800
++/* bit 12 is reserved */
++#define IEEE80211_CAPINFO_DSSSOFDM          0x2000
++/* bits 14-15 are reserved */
++
++/*
++ * Authentication Modes
++ */
++
++enum ieee80211_authmode {
++	IEEE80211_AUTH_NONE = 0,
++	IEEE80211_AUTH_OPEN = 1,
++	IEEE80211_AUTH_SHARED = 2,
++	IEEE80211_AUTH_8021X = 3,
++	IEEE80211_AUTH_AUTO = 4,	/* auto-select/accept */
++	/* NB: these are used only for ioctls */
++	IEEE80211_AUTH_WPA = 5,		/* WPA/RSN w/ 802.1x */
++	IEEE80211_AUTH_WPA_PSK = 6,	/* WPA/RSN w/ PSK */
++	IEEE80211_AUTH_WPA_CCKM = 7,	/* WPA/RSN IE w/ CCKM */
++};
++
++#endif							/* _NET80211_IEEE80211_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211_ioctl.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211_ioctl.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,121 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Portions Copyright (c) 2001 Atsushi Onoe,  2002-2005 Sam Leffler, Errno Consulting
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the AR6000 linux driver.
++ *
++ */
++
++#ifndef _IEEE80211_IOCTL_H_
++#define _IEEE80211_IOCTL_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
++ */
++
++/*
++ * WPA/RSN get/set key request.  Specify the key/cipher
++ * type and whether the key is to be used for sending and/or
++ * receiving.  The key index should be set only when working
++ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
++ * Otherwise a unicast/pairwise key is specified by the bssid
++ * (on a station) or mac address (on an ap).  They key length
++ * must include any MIC key data; otherwise it should be no
++ more than IEEE80211_KEYBUF_SIZE.
++ */
++	struct ieee80211req_key {
++		u_int8_t ik_type;		/* key/cipher type */
++		u_int8_t ik_pad;
++		u_int16_t ik_keyix;		/* key index */
++		u_int8_t ik_keylen;		/* key length in bytes */
++		u_int8_t ik_flags;
++#define IEEE80211_KEY_XMIT  0x01
++#define IEEE80211_KEY_RECV  0x02
++#define	IEEE80211_KEY_DEFAULT	0x80	/* default xmit key */
++		u_int8_t ik_macaddr[IEEE80211_ADDR_LEN];
++		u_int64_t ik_keyrsc;	/* key receive sequence counter */
++		u_int64_t ik_keytsc;	/* key transmit sequence counter */
++		u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE + IEEE80211_MICBUF_SIZE];
++	};
++/*
++ * Delete a key either by index or address.  Set the index
++ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
++ */
++	struct ieee80211req_del_key {
++		u_int8_t idk_keyix;		/* key index */
++		u_int8_t idk_macaddr[IEEE80211_ADDR_LEN];
++	};
++/*
++ * MLME state manipulation request.  IEEE80211_MLME_ASSOC
++ * only makes sense when operating as a station.  The other
++ * requests can be used when operating as a station or an
++ * ap (to effect a station).
++ */
++	struct ieee80211req_mlme {
++		u_int8_t im_op;			/* operation to perform */
++#define	IEEE80211_MLME_ASSOC		1	/* associate station */
++#define	IEEE80211_MLME_DISASSOC		2	/* disassociate station */
++#define	IEEE80211_MLME_DEAUTH		3	/* deauthenticate station */
++#define	IEEE80211_MLME_AUTHORIZE	4	/* authorize station */
++#define	IEEE80211_MLME_UNAUTHORIZE	5	/* unauthorize station */
++		u_int16_t im_reason;	/* 802.11 reason code */
++		u_int8_t im_macaddr[IEEE80211_ADDR_LEN];
++	};
++
++	struct ieee80211req_addpmkid {
++		u_int8_t pi_bssid[IEEE80211_ADDR_LEN];
++		u_int8_t pi_enable;
++		u_int8_t pi_pmkid[16];
++	};
++
++#define AUTH_ALG_OPEN_SYSTEM	0x01
++#define AUTH_ALG_SHARED_KEY	0x02
++#define AUTH_ALG_LEAP		0x04
++
++	struct ieee80211req_authalg {
++		u_int8_t auth_alg;
++	};
++
++	enum {
++		IEEE80211_PARAM_AUTHMODE = 3,	/* Authentication Mode */
++		IEEE80211_PARAM_MCASTCIPHER = 5,
++		IEEE80211_PARAM_MCASTKEYLEN = 6,	/* multicast key length */
++		IEEE80211_PARAM_UCASTCIPHER = 8,
++		IEEE80211_PARAM_UCASTKEYLEN = 9,	/* unicast key length */
++		IEEE80211_PARAM_WPA = 10,	/* WPA mode (0,1,2) */
++		IEEE80211_PARAM_ROAMING = 12,	/* roaming mode */
++		IEEE80211_PARAM_PRIVACY = 13,	/* privacy invoked */
++		IEEE80211_PARAM_COUNTERMEASURES = 14,	/* WPA/TKIP
++												   countermeasures */
++		IEEE80211_PARAM_DROPUNENCRYPTED = 15,	/* discard unencrypted
++												   frames */
++	};
++
++/*
++ * Values for IEEE80211_PARAM_WPA
++ */
++#define WPA_MODE_WPA1   1
++#define WPA_MODE_WPA2   2
++#define WPA_MODE_AUTO   3
++#define WPA_MODE_NONE   4
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _IEEE80211_IOCTL_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211_node.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/ieee80211_node.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 ATheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _IEEE80211_NODE_H_
++#define _IEEE80211_NODE_H_
++
++/*
++ * Node locking definitions.
++ */
++#define IEEE80211_NODE_LOCK_INIT(_nt)   A_MUTEX_INIT(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_DESTROY(_nt)
++#define IEEE80211_NODE_LOCK(_nt)        A_MUTEX_LOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_UNLOCK(_nt)      A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_BH(_nt)     A_MUTEX_LOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_UNLOCK_BH(_nt)   A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_ASSERT(_nt)
++
++/*
++ * Node reference counting definitions.
++ *
++ * ieee80211_node_initref   initialize the reference count to 1
++ * ieee80211_node_incref    add a reference
++ * ieee80211_node_decref    remove a reference
++ * ieee80211_node_dectestref    remove a reference and return 1 if this
++ *              is the last reference, otherwise 0
++ * ieee80211_node_refcnt    reference count for printing (only)
++ */
++#define ieee80211_node_initref(_ni)     ((_ni)->ni_refcnt = 1)
++#define ieee80211_node_incref(_ni)      ((_ni)->ni_refcnt++)
++#define ieee80211_node_decref(_ni)      ((_ni)->ni_refcnt--)
++#define ieee80211_node_dectestref(_ni)  (((_ni)->ni_refcnt--) == 0)
++#define ieee80211_node_refcnt(_ni)      ((_ni)->ni_refcnt)
++
++#define IEEE80211_NODE_HASHSIZE 32
++/* simple hash is enough for variation of macaddr */
++#define IEEE80211_NODE_HASH(addr)   \
++    (((const u8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
++        IEEE80211_NODE_HASHSIZE)
++
++/*
++ * Table of ieee80211_node instances.  Each ieee80211com
++ * has at least one for holding the scan candidates.
++ * When operating as an access point or in ibss mode there
++ * is a second table for associated stations or neighbors.
++ */
++struct ieee80211_node_table {
++	void *nt_wmip;				/* back reference */
++	A_MUTEX_T nt_nodelock;		/* on node table */
++	struct bss *nt_node_first;	/* information of all nodes */
++	struct bss *nt_node_last;	/* information of all nodes */
++	struct bss *nt_hash[IEEE80211_NODE_HASHSIZE];
++	const char *nt_name;		/* for debugging */
++	u32 nt_scangen;				/* gen# for timeout scan */
++	A_TIMER nt_inact_timer;
++};
++
++#define WLAN_NODE_INACT_TIMEOUT_MSEC            10000
++
++#endif							/* _IEEE80211_NODE_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/osapi.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/osapi.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,49 @@
++/*
++ * Copyright 2003-2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions of the basic atheros data types.
++ * It is used to map the data types in atheros files to a platform specific
++ * type.
++ *
++ */
++
++#ifndef _OSAPI_H_
++#define _OSAPI_H_
++
++#ifdef __KERNEL__
++
++#ifdef __linux__
++#include "../include/osapi_linux.h"
++#endif
++
++#endif							/* __KERNEL__ */
++
++#ifdef __GNUC__
++#define __ATTRIB_PACK           __attribute__ ((packed))
++#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
++#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
++#ifndef INLINE
++#define INLINE                  __inline__
++#endif
++#else							/* Not GCC */
++#define __ATTRIB_PACK
++#define __ATTRIB_PRINTF
++#define __ATTRIB_NORETURN
++#ifndef INLINE
++#define INLINE                  __inline
++#endif
++#endif							/* End __GNUC__ */
++
++#endif							/* _OSAPI_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/osapi_linux.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/osapi_linux.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,167 @@
++/*
++ * Copyright 2003-2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions of the basic atheros data types.
++ * It is used to map the data types in atheros files to a platform specific
++ * type.
++ *
++ */
++
++#ifndef _OSAPI_LINUX_H_
++#define _OSAPI_LINUX_H_
++
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/jiffies.h>
++#endif
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/wait.h>
++#ifdef KERNEL_2_4
++#include <asm/arch/irq.h>
++#include <asm/irq.h>
++#endif
++
++/*
++ * Endianes macros
++ */
++#define A_BE2CPU8(x)       ntohb(x)
++#define A_BE2CPU16(x)      ntohs(x)
++#define A_BE2CPU32(x)      ntohl(x)
++
++#define A_LE2CPU8(x)       (x)
++#define A_LE2CPU16(x)      (x)
++#define A_LE2CPU32(x)      (x)
++
++#define A_CPU2BE8(x)       htonb(x)
++#define A_CPU2BE16(x)      htons(x)
++#define A_CPU2BE32(x)      htonl(x)
++
++#define A_MEMCPY(dst, src, len)         memcpy((u8 *)(dst), (src), (len))
++#define A_MEMZERO(addr, len)            memset(addr, 0, len)
++#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
++#define A_MALLOC(size)                  kmalloc((size), GFP_KERNEL)
++#define A_MALLOC_NOWAIT(size)           kmalloc((size), GFP_ATOMIC)
++#define A_FREE(addr)                    kfree(addr)
++#define A_PRINTF(args...)               printk(args)
++
++/* Mutual Exclusion */
++typedef spinlock_t A_MUTEX_T;
++#define A_MUTEX_INIT(mutex)             spin_lock_init(mutex)
++#define A_MUTEX_LOCK(mutex)             spin_lock_bh(mutex)
++#define A_MUTEX_UNLOCK(mutex)           spin_unlock_bh(mutex)
++
++/*
++ * Timer Functions
++ */
++#define A_MDELAY(msecs)                 mdelay(msecs)
++typedef struct timer_list A_TIMER;
++
++#define A_INIT_TIMER(pTimer, pFunction, pArg) do {              \
++    init_timer(pTimer);                                         \
++    (pTimer)->function = (pFunction);                           \
++    (pTimer)->data	 = (unsigned long)(pArg);                   \
++} while (0)
++
++/*
++ * Start a Timer that elapses after 'periodMSec' milli-seconds
++ * Support is provided for a one-shot timer. The 'repeatFlag' is
++ * ignored.
++ */
++#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do {                   \
++    if (repeatFlag) {                                                       \
++        printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__);     \
++        panic("Timer Repeat");                                              \
++    }                                                                       \
++    mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000);                \
++} while (0)
++
++/*
++ * Cancel the Timer.
++ */
++#define A_UNTIMEOUT(pTimer) do {                                \
++    del_timer((pTimer));                                        \
++} while (0)
++
++#define A_DELETE_TIMER(pTimer) do {                             \
++} while (0)
++
++/*
++ * Wait Queue related functions
++ */
++typedef wait_queue_head_t A_WAITQUEUE_HEAD;
++#define A_INIT_WAITQUEUE_HEAD(head)     init_waitqueue_head(head)
++#ifdef mvlcee31_2_4_20_omap2420_gsm_gprs
++#ifndef wait_event_interruptible_timeout
++#define __wait_event_interruptible_timeout(wq, condition, ret)          \
++do {                                                                    \
++        wait_queue_t __wait;                                            \
++        init_waitqueue_entry(&__wait, current);                         \
++                                                                        \
++        add_wait_queue(&wq, &__wait);                                   \
++        for (;;) {                                                      \
++                set_current_state(TASK_INTERRUPTIBLE);                  \
++                if (condition)                                          \
++                        break;                                          \
++                if (!signal_pending(current)) {                         \
++                        ret = schedule_timeout(ret);                    \
++                        if (!ret)                                       \
++                                break;                                  \
++                        continue;                                       \
++                }                                                       \
++                ret = -ERESTARTSYS;                                     \
++                break;                                                  \
++        }                                                               \
++        current->state = TASK_RUNNING;                                  \
++        remove_wait_queue(&wq, &__wait);                                \
++} while (0)
++
++#define wait_event_interruptible_timeout(wq, condition, timeout)        \
++({                                                                      \
++        long __ret = timeout;                                           \
++        if (!(condition))                                               \
++                __wait_event_interruptible_timeout(wq, condition, __ret); \
++        __ret;                                                          \
++})
++#endif							/* wait_event_interruptible_timeout */
++
++#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
++    wait_event_interruptible_timeout(head, condition, timeout); \
++} while (0)
++#else
++#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
++    wait_event_interruptible_timeout(head, condition, timeout); \
++} while (0)
++#endif							/* mvlcee31_2_4_20-omap2420_gsm_gprs */
++
++#define A_WAKE_UP(head)                 wake_up(head)
++
++#ifdef CONFIG_AR6K_DEBUG
++#define A_ASSERT(expr)  \
++    if (!(expr)) {   \
++        printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
++        panic(#expr); \
++    }
++
++#else
++#define A_ASSERT(expr)
++#endif							/* DEBUG */
++
++#endif							/* _OSAPI_LINUX_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/queue.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/queue.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,550 @@
++/*
++ * Copyright (c) 1991, 1993
++ *	The Regents of the University of California.  All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ * 4. Neither the name of the University nor the names of its contributors
++ *    may be used to endorse or promote products derived from this software
++ *    without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ *
++ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
++ * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $
++ * $Id: //depot/sw/releases/etnaGPL1.1/host/include/queue.h#1 $
++ */
++
++#ifndef _SYS_QUEUE_H_
++#define	_SYS_QUEUE_H_
++
++/*
++ * This file defines four types of data structures: singly-linked lists,
++ * singly-linked tail queues, lists and tail queues.
++ *
++ * A singly-linked list is headed by a single forward pointer. The elements
++ * are singly linked for minimum space and pointer manipulation overhead at
++ * the expense of O(n) removal for arbitrary elements. New elements can be
++ * added to the list after an existing element or at the head of the list.
++ * Elements being removed from the head of the list should use the explicit
++ * macro for this purpose for optimum efficiency. A singly-linked list may
++ * only be traversed in the forward direction.  Singly-linked lists are ideal
++ * for applications with large datasets and few or no removals or for
++ * implementing a LIFO queue.
++ *
++ * A singly-linked tail queue is headed by a pair of pointers, one to the
++ * head of the list and the other to the tail of the list. The elements are
++ * singly linked for minimum space and pointer manipulation overhead at the
++ * expense of O(n) removal for arbitrary elements. New elements can be added
++ * to the list after an existing element, at the head of the list, or at the
++ * end of the list. Elements being removed from the head of the tail queue
++ * should use the explicit macro for this purpose for optimum efficiency.
++ * A singly-linked tail queue may only be traversed in the forward direction.
++ * Singly-linked tail queues are ideal for applications with large datasets
++ * and few or no removals or for implementing a FIFO queue.
++ *
++ * A list is headed by a single forward pointer (or an array of forward
++ * pointers for a hash table header). The elements are doubly linked
++ * so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before
++ * or after an existing element or at the head of the list. A list
++ * may only be traversed in the forward direction.
++ *
++ * A tail queue is headed by a pair of pointers, one to the head of the
++ * list and the other to the tail of the list. The elements are doubly
++ * linked so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before or
++ * after an existing element, at the head of the list, or at the end of
++ * the list. A tail queue may be traversed in either direction.
++ *
++ * For details on the use of these macros, see the queue(3) manual page.
++ *
++ *
++ *				SLIST	LIST	STAILQ	TAILQ
++ * _HEAD			+	+	+	+
++ * _HEAD_INITIALIZER		+	+	+	+
++ * _ENTRY			+	+	+	+
++ * _INIT			+	+	+	+
++ * _EMPTY			+	+	+	+
++ * _FIRST			+	+	+	+
++ * _NEXT			+	+	+	+
++ * _PREV			-	-	-	+
++ * _LAST			-	-	+	+
++ * _FOREACH			+	+	+	+
++ * _FOREACH_SAFE		+	+	+	+
++ * _FOREACH_REVERSE		-	-	-	+
++ * _FOREACH_REVERSE_SAFE	-	-	-	+
++ * _INSERT_HEAD			+	+	+	+
++ * _INSERT_BEFORE		-	+	-	+
++ * _INSERT_AFTER		+	+	+	+
++ * _INSERT_TAIL			-	-	+	+
++ * _CONCAT			-	-	+	+
++ * _REMOVE_HEAD			+	-	+	-
++ * _REMOVE			+	+	+	+
++ *
++ */
++#define	QUEUE_MACRO_DEBUG 0
++#if QUEUE_MACRO_DEBUG
++/* Store the last 2 places the queue element or head was altered */
++struct qm_trace {
++	char *lastfile;
++	int lastline;
++	char *prevfile;
++	int prevline;
++};
++
++#define	TRACEBUF	struct qm_trace trace;
++#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
++
++#define	QMD_TRACE_HEAD(head) do {					\
++	(head)->trace.prevline = (head)->trace.lastline;		\
++	(head)->trace.prevfile = (head)->trace.lastfile;		\
++	(head)->trace.lastline = __LINE__;				\
++	(head)->trace.lastfile = __FILE__;				\
++} while (0)
++
++#define	QMD_TRACE_ELEM(elem) do {					\
++	(elem)->trace.prevline = (elem)->trace.lastline;		\
++	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
++	(elem)->trace.lastline = __LINE__;				\
++	(elem)->trace.lastfile = __FILE__;				\
++} while (0)
++
++#else
++#define	QMD_TRACE_ELEM(elem)
++#define	QMD_TRACE_HEAD(head)
++#define	TRACEBUF
++#define	TRASHIT(x)
++#endif							/* QUEUE_MACRO_DEBUG */
++
++/*
++ * Singly-linked List declarations.
++ */
++#define	SLIST_HEAD(name, type)						\
++struct name {								\
++	struct type *slh_first;	/* first element */			\
++}
++
++#define	SLIST_HEAD_INITIALIZER(head)					\
++	{ NULL }
++
++#define	SLIST_ENTRY(type)						\
++struct {								\
++	struct type *sle_next;	/* next element */			\
++}
++
++/*
++ * Singly-linked List functions.
++ */
++#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
++
++#define	SLIST_FIRST(head)	((head)->slh_first)
++
++#define	SLIST_FOREACH(var, head, field)					\
++	for ((var) = SLIST_FIRST((head));				\
++	    (var);							\
++	    (var) = SLIST_NEXT((var), field))
++
++#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
++	for ((var) = SLIST_FIRST((head));				\
++	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
++	    (var) = (tvar))
++
++#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
++	for ((varp) = &SLIST_FIRST((head));				\
++	    ((var) = *(varp)) != NULL;					\
++	    (varp) = &SLIST_NEXT((var), field))
++
++#define	SLIST_INIT(head) do {						\
++	SLIST_FIRST((head)) = NULL;					\
++} while (0)
++
++#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
++	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
++	SLIST_NEXT((slistelm), field) = (elm);				\
++} while (0)
++
++#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
++	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
++	SLIST_FIRST((head)) = (elm);					\
++} while (0)
++
++#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
++
++#define	SLIST_REMOVE(head, elm, type, field) do {			\
++	if (SLIST_FIRST((head)) == (elm)) {				\
++		SLIST_REMOVE_HEAD((head), field);			\
++	}								\
++	else {								\
++		struct type *curelm = SLIST_FIRST((head));		\
++		while (SLIST_NEXT(curelm, field) != (elm))		\
++			curelm = SLIST_NEXT(curelm, field);		\
++		SLIST_NEXT(curelm, field) =				\
++		    SLIST_NEXT(SLIST_NEXT(curelm, field), field);	\
++	}								\
++} while (0)
++
++#define	SLIST_REMOVE_HEAD(head, field) do {				\
++	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
++} while (0)
++
++/*
++ * Singly-linked Tail queue declarations.
++ */
++#define	STAILQ_HEAD(name, type)						\
++struct name {								\
++	struct type *stqh_first;/* first element */			\
++	struct type **stqh_last;/* addr of last next element */		\
++}
++
++#define	STAILQ_HEAD_INITIALIZER(head)					\
++	{ NULL, &(head).stqh_first }
++
++#define	STAILQ_ENTRY(type)						\
++struct {								\
++	struct type *stqe_next;	/* next element */			\
++}
++
++/*
++ * Singly-linked Tail queue functions.
++ */
++#define	STAILQ_CONCAT(head1, head2) do {				\
++	if (!STAILQ_EMPTY((head2))) {					\
++		*(head1)->stqh_last = (head2)->stqh_first;		\
++		(head1)->stqh_last = (head2)->stqh_last;		\
++		STAILQ_INIT((head2));					\
++	}								\
++} while (0)
++
++#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
++
++#define	STAILQ_FIRST(head)	((head)->stqh_first)
++
++#define	STAILQ_FOREACH(var, head, field)				\
++	for((var) = STAILQ_FIRST((head));				\
++	   (var);							\
++	   (var) = STAILQ_NEXT((var), field))
++
++
++#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
++	for ((var) = STAILQ_FIRST((head));				\
++	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
++	    (var) = (tvar))
++
++#define	STAILQ_INIT(head) do {						\
++	STAILQ_FIRST((head)) = NULL;					\
++	(head)->stqh_last = &STAILQ_FIRST((head));			\
++} while (0)
++
++#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
++	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
++		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
++	STAILQ_NEXT((tqelm), field) = (elm);				\
++} while (0)
++
++#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
++	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
++		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
++	STAILQ_FIRST((head)) = (elm);					\
++} while (0)
++
++#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
++	STAILQ_NEXT((elm), field) = NULL;				\
++	*(head)->stqh_last = (elm);					\
++	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
++} while (0)
++
++#define	STAILQ_LAST(head, type, field)					\
++	(STAILQ_EMPTY((head)) ?						\
++		NULL :							\
++	        ((struct type *)					\
++		((char *)((head)->stqh_last) - __offsetof(struct type, field))))
++
++#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
++
++#define	STAILQ_REMOVE(head, elm, type, field) do {			\
++	if (STAILQ_FIRST((head)) == (elm)) {				\
++		STAILQ_REMOVE_HEAD((head), field);			\
++	}								\
++	else {								\
++		struct type *curelm = STAILQ_FIRST((head));		\
++		while (STAILQ_NEXT(curelm, field) != (elm))		\
++			curelm = STAILQ_NEXT(curelm, field);		\
++		if ((STAILQ_NEXT(curelm, field) =			\
++		     STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
++			(head)->stqh_last = &STAILQ_NEXT((curelm), field);\
++	}								\
++} while (0)
++
++#define	STAILQ_REMOVE_HEAD(head, field) do {				\
++	if ((STAILQ_FIRST((head)) =					\
++	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
++		(head)->stqh_last = &STAILQ_FIRST((head));		\
++} while (0)
++
++#define	STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do {			\
++	if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL)	\
++		(head)->stqh_last = &STAILQ_FIRST((head));		\
++} while (0)
++
++/*
++ * List declarations.
++ */
++#define	ATH_LIST_HEAD(name, type)					\
++struct name {								\
++	struct type *lh_first;	/* first element */			\
++}
++
++#define	LIST_HEAD_INITIALIZER(head)					\
++	{ NULL }
++
++#define	LIST_ENTRY(type)						\
++struct {								\
++	struct type *le_next;	/* next element */			\
++	struct type **le_prev;	/* address of previous next element */	\
++}
++
++/*
++ * List functions.
++ */
++
++#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
++
++#define	LIST_FIRST(head)	((head)->lh_first)
++
++#define	LIST_FOREACH(var, head, field)					\
++	for ((var) = LIST_FIRST((head));				\
++	    (var);							\
++	    (var) = LIST_NEXT((var), field))
++
++#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
++	for ((var) = LIST_FIRST((head));				\
++	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
++	    (var) = (tvar))
++
++#define	LIST_INIT(head) do {						\
++	LIST_FIRST((head)) = NULL;					\
++} while (0)
++
++#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
++	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
++		LIST_NEXT((listelm), field)->field.le_prev =		\
++		    &LIST_NEXT((elm), field);				\
++	LIST_NEXT((listelm), field) = (elm);				\
++	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
++} while (0)
++
++#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
++	(elm)->field.le_prev = (listelm)->field.le_prev;		\
++	LIST_NEXT((elm), field) = (listelm);				\
++	*(listelm)->field.le_prev = (elm);				\
++	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
++} while (0)
++
++#define	LIST_INSERT_HEAD(head, elm, field) do {				\
++	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
++		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
++	LIST_FIRST((head)) = (elm);					\
++	(elm)->field.le_prev = &LIST_FIRST((head));			\
++} while (0)
++
++#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
++
++#define	LIST_REMOVE(elm, field) do {					\
++	if (LIST_NEXT((elm), field) != NULL)				\
++		LIST_NEXT((elm), field)->field.le_prev = 		\
++		    (elm)->field.le_prev;				\
++	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
++} while (0)
++
++/*
++ * Tail queue declarations.
++ */
++#define	TAILQ_HEAD(name, type)						\
++struct name {								\
++	struct type *tqh_first;	/* first element */			\
++	struct type **tqh_last;	/* addr of last next element */		\
++	TRACEBUF							\
++}
++
++#define	TAILQ_HEAD_INITIALIZER(head)					\
++	{ NULL, &(head).tqh_first }
++
++#define	TAILQ_ENTRY(type)						\
++struct {								\
++	struct type *tqe_next;	/* next element */			\
++	struct type **tqe_prev;	/* address of previous next element */	\
++	TRACEBUF							\
++}
++
++/*
++ * Tail queue functions.
++ */
++#define	TAILQ_CONCAT(head1, head2, field) do {				\
++	if (!TAILQ_EMPTY(head2)) {					\
++		*(head1)->tqh_last = (head2)->tqh_first;		\
++		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
++		(head1)->tqh_last = (head2)->tqh_last;			\
++		TAILQ_INIT((head2));					\
++		QMD_TRACE_HEAD(head);					\
++		QMD_TRACE_HEAD(head2);					\
++	}								\
++} while (0)
++
++#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
++
++#define	TAILQ_FIRST(head)	((head)->tqh_first)
++
++#define	TAILQ_FOREACH(var, head, field)					\
++	for ((var) = TAILQ_FIRST((head));				\
++	    (var);							\
++	    (var) = TAILQ_NEXT((var), field))
++
++#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
++	for ((var) = TAILQ_FIRST((head));				\
++	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
++	    (var) = (tvar))
++
++#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
++	for ((var) = TAILQ_LAST((head), headname);			\
++	    (var);							\
++	    (var) = TAILQ_PREV((var), headname, field))
++
++#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
++	for ((var) = TAILQ_LAST((head), headname);			\
++	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
++	    (var) = (tvar))
++
++#define	TAILQ_INIT(head) do {						\
++	TAILQ_FIRST((head)) = NULL;					\
++	(head)->tqh_last = &TAILQ_FIRST((head));			\
++	QMD_TRACE_HEAD(head);						\
++} while (0)
++
++#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
++	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
++		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
++		    &TAILQ_NEXT((elm), field);				\
++	else {								\
++		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
++		QMD_TRACE_HEAD(head);					\
++	}								\
++	TAILQ_NEXT((listelm), field) = (elm);				\
++	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
++	QMD_TRACE_ELEM(&(elm)->field);					\
++	QMD_TRACE_ELEM(&listelm->field);				\
++} while (0)
++
++#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
++	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
++	TAILQ_NEXT((elm), field) = (listelm);				\
++	*(listelm)->field.tqe_prev = (elm);				\
++	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
++	QMD_TRACE_ELEM(&(elm)->field);					\
++	QMD_TRACE_ELEM(&listelm->field);				\
++} while (0)
++
++#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
++	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
++		TAILQ_FIRST((head))->field.tqe_prev =			\
++		    &TAILQ_NEXT((elm), field);				\
++	else								\
++		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
++	TAILQ_FIRST((head)) = (elm);					\
++	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
++	QMD_TRACE_HEAD(head);						\
++	QMD_TRACE_ELEM(&(elm)->field);					\
++} while (0)
++
++#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
++	TAILQ_NEXT((elm), field) = NULL;				\
++	(elm)->field.tqe_prev = (head)->tqh_last;			\
++	*(head)->tqh_last = (elm);					\
++	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
++	QMD_TRACE_HEAD(head);						\
++	QMD_TRACE_ELEM(&(elm)->field);					\
++} while (0)
++
++#define	TAILQ_LAST(head, headname)					\
++	(*(((struct headname *)((head)->tqh_last))->tqh_last))
++
++#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
++
++#define	TAILQ_PREV(elm, headname, field)				\
++	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
++
++#define	TAILQ_REMOVE(head, elm, field) do {				\
++	if ((TAILQ_NEXT((elm), field)) != NULL)				\
++		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
++		    (elm)->field.tqe_prev;				\
++	else {								\
++		(head)->tqh_last = (elm)->field.tqe_prev;		\
++		QMD_TRACE_HEAD(head);					\
++	}								\
++	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
++	TRASHIT((elm)->field.tqe_next);					\
++	TRASHIT((elm)->field.tqe_prev);					\
++	QMD_TRACE_ELEM(&(elm)->field);					\
++} while (0)
++
++
++#ifdef _KERNEL
++
++/*
++ * XXX insque() and remque() are an old way of handling certain queues.
++ * They bogusly assumes that all queue heads look alike.
++ */
++
++struct quehead {
++	struct quehead *qh_link;
++	struct quehead *qh_rlink;
++};
++
++#if defined(__GNUC__) || defined(__INTEL_COMPILER)
++
++static __inline void insque(void *a, void *b)
++{
++	struct quehead *element = (struct quehead *) a,
++		*head = (struct quehead *) b;
++
++	element->qh_link = head->qh_link;
++	element->qh_rlink = head;
++	head->qh_link = element;
++	element->qh_link->qh_rlink = element;
++}
++
++static __inline void remque(void *a)
++{
++	struct quehead *element = (struct quehead *) a;
++
++	element->qh_link->qh_rlink = element->qh_rlink;
++	element->qh_rlink->qh_link = element->qh_link;
++	element->qh_rlink = 0;
++}
++
++#else							/* !(__GNUC__ || __INTEL_COMPILER) */
++
++void insque(void *a, void *b);
++void remque(void *a);
++
++#endif							/* __GNUC__ || __INTEL_COMPILER */
++
++#endif							/* _KERNEL */
++
++#endif							/* !_SYS_QUEUE_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wlan_api.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wlan_api.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the API for the host wlan module
++ *
++ *
++ */
++
++#ifndef _HOST_WLAN_API_H_
++#define _HOST_WLAN_API_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++	struct ieee80211_node_table;
++	struct ieee80211_frame;
++
++	struct ieee80211_common_ie {
++		u16 ie_chan;
++		u8 *ie_tstamp;
++		u8 *ie_ssid;
++		u8 *ie_rates;
++		u8 *ie_xrates;
++		u8 *ie_country;
++		u8 *ie_wpa;
++		u8 *ie_wmm;
++		u8 *ie_ath;
++		u16 ie_capInfo;
++		u16 ie_beaconInt;
++		u8 *ie_tim;
++		u8 *ie_chswitch;
++		u8 ie_erp;
++	};
++
++	typedef struct bss {
++		u8 ni_macaddr[6];
++		s8 ni_rssi;
++		struct bss *ni_list_next;
++		struct bss *ni_list_prev;
++		struct bss *ni_hash_next;
++		struct bss *ni_hash_prev;
++		struct ieee80211_common_ie ni_cie;
++		u8 *ni_buf;
++		struct ieee80211_node_table *ni_table;
++		u32 ni_refcnt;
++		int ni_scangen;
++		u32 ni_tstamp;
++	} bss_t;
++
++	typedef void wlan_node_iter_func(void *arg, bss_t *);
++
++	bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
++	void wlan_node_free(bss_t * ni);
++	void wlan_setup_node(struct ieee80211_node_table *nt, bss_t * ni,
++						 const u8 * macaddr);
++	bss_t *wlan_find_node(struct ieee80211_node_table *nt,
++						  const u8 * macaddr);
++	void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t * ni);
++	void wlan_free_allnodes(struct ieee80211_node_table *nt);
++	void wlan_iterate_nodes(struct ieee80211_node_table *nt,
++							wlan_node_iter_func * f, void *arg);
++
++	void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
++	void wlan_node_table_reset(struct ieee80211_node_table *nt);
++	void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
++
++	int wlan_parse_beacon(u8 * buf, int framelen,
++						  struct ieee80211_common_ie *cie);
++
++	u16 wlan_ieee2freq(int chan);
++	u32 wlan_freq2ieee(u16 freq);
++
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _HOST_WLAN_API_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi_api.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi_api.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,165 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the Wireless Module Interface (WMI).
++ *
++ *
++ */
++
++#ifndef _WMI_API_H_
++#define _WMI_API_H_
++
++#define WMI_HIGH_PRIORITY_MBOX  ENDPOINT4
++#define WMI_LOW_PRIORITY_MBOX   ENDPOINT3
++#define WMI_BEST_EFFORT_MBOX    ENDPOINT2
++#define WMI_CONTROL_MBOX        ENDPOINT1
++#define WMI_MBOX_COUNT          4
++#define WMI_MAX_NUM_PRI_STREAMS 2
++#define WMI_NOT_MAPPED          (-1)
++#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000	/* 5 seconds */
++
++	typedef enum {
++		CCX_V4_COMPLIANCE = 0x1,
++	} TSPEC_PARAM_COMPLIANCE;
++
++	struct wmi_t;
++
++	void *wmi_init(void *devt);
++
++	void wmi_qos_state_init(struct wmi_t *wmip);
++	void wmi_shutdown(struct wmi_t *wmip);
++	s8 wmi_get_mapped_qos_queue(struct wmi_t *wmip, u8 dir,
++								  u8 trafficClass);
++	int wmi_dix_2_dot3(struct wmi_t *wmip, struct sk_buff *skb);
++	int wmi_data_hdr_add(struct wmi_t *wmip, struct sk_buff *skb, u8 msgType);
++	int wmi_dot3_2_dix(struct wmi_t *wmip, struct sk_buff *skb);
++	int wmi_data_hdr_remove(struct wmi_t *wmip, struct sk_buff *skb);
++	int wmi_syncpoint(struct wmi_t *wmip);
++	int wmi_syncpoint_reset(struct wmi_t *wmip);
++	HTC_ENDPOINT_ID wmi_get_endpoint(struct wmi_t *wmip, u8 trafficClass);
++	u8 wmi_implicit_create_pstream(struct wmi_t *wmip, struct sk_buff *skb,
++								   u8 dir);
++
++	int wmi_control_rx(struct wmi_t *wmip, struct sk_buff *skb);
++	void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func * f,
++						   void *arg);
++
++	typedef enum {
++		NO_SYNC_WMIFLAG = 0,
++		SYNC_BEFORE_WMIFLAG,	/* transmit all queued data before cmd */
++		SYNC_AFTER_WMIFLAG,		/* any new data waits until cmd execs */
++		SYNC_BOTH_WMIFLAG,
++		END_WMIFLAG				/* end marker */
++	} WMI_SYNC_FLAG;
++
++	int wmi_cmd_send(struct wmi_t *wmip, struct sk_buff *skb, WMI_COMMAND_ID cmdId,
++					 WMI_SYNC_FLAG flag);
++	int wmi_connect_cmd(struct wmi_t *wmip,
++						NETWORK_TYPE netType,
++						DOT11_AUTH_MODE dot11AuthMode,
++						AUTH_MODE authMode,
++						CRYPTO_TYPE pairwiseCrypto,
++						u8 pairwiseCryptoLen,
++						CRYPTO_TYPE groupCrypto,
++						u8 groupCryptoLen,
++						int ssidLength,
++						u8 * ssid, u8 * bssid, u16 channel);
++	int wmi_reconnect_cmd(struct wmi_t *wmip, u8 * bssid, u16 channel);
++	int wmi_disconnect_cmd(struct wmi_t *wmip);
++	int wmi_getrev_cmd(struct wmi_t *wmip);
++	int wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType);
++	int wmi_scanparams_cmd(struct wmi_t *wmip, u16 fg_start_sec,
++						   u16 fg_end_sec, u16 bg_sec,
++						   u16 act_chdw_msec, u16 pas_chdw_msec,
++						   u8 shScanRatio);
++	int wmi_bssfilter_cmd(struct wmi_t *wmip, u8 filter);
++	int wmi_probedSsid_cmd(struct wmi_t *wmip, u8 index, u8 flag,
++						   u8 ssidLength, u8 * ssid);
++	int wmi_listeninterval_cmd(struct wmi_t *wmip, u16 listenInterval,
++							   u16 listenBeacons);
++	int wmi_bmisstime_cmd(struct wmi_t *wmip, u16 bmisstime,
++						  u16 bmissbeacons);
++	int wmi_associnfo_cmd(struct wmi_t *wmip, u8 ieType, u8 ieLen,
++						  u8 * ieInfo);
++	int wmi_powermode_cmd(struct wmi_t *wmip, u8 powerMode);
++	int wmi_ibsspmcaps_cmd(struct wmi_t *wmip, u8 pmEnable, u8 ttl,
++						   u16 atim_windows, u16 timeout_value);
++	int wmi_pmparams_cmd(struct wmi_t *wmip, u16 idlePeriod,
++						 u16 psPollNum, u16 dtimPolicy);
++	int wmi_disctimeout_cmd(struct wmi_t *wmip, u8 timeout);
++	int wmi_sync_cmd(struct wmi_t *wmip, u8 syncNumber);
++	int wmi_create_pstream_cmd(struct wmi_t *wmip,
++							   WMI_CREATE_PSTREAM_CMD * pstream);
++	int wmi_delete_pstream_cmd(struct wmi_t *wmip, u8 txQueueNumber,
++							   u8 rxQueueNumber, u8 trafficDirection);
++	int wmi_set_bitrate_cmd(struct wmi_t *wmip, s32 rate);
++	int wmi_get_bitrate_cmd(struct wmi_t *wmip);
++	s8 wmi_validate_bitrate(struct wmi_t *wmip, s32 rate);
++	int wmi_get_regDomain_cmd(struct wmi_t *wmip);
++	int wmi_get_channelList_cmd(struct wmi_t *wmip);
++	int wmi_set_channelParams_cmd(struct wmi_t *wmip, WMI_PHY_MODE mode,
++								  int numChan, u16 * channelList);
++	int wmi_set_link_threshold_params(struct wmi_t *wmip,
++									  u8 highThreshold_upperVal,
++									  u8 highThreshold_lowerVal,
++									  u8 lowThreshold_upperVal,
++									  u8 lowThreshold_lowerVal,
++									  u32 pollTime);
++	int wmi_set_error_report_bitmask(struct wmi_t *wmip, u32 bitmask);
++
++	int wmi_get_stats_cmd(struct wmi_t *wmip);
++	int wmi_addKey_cmd(struct wmi_t *wmip, u8 keyIndex,
++					   CRYPTO_TYPE keyType, u8 keyUsage,
++					   u8 keyLength, u8 * keyRSC,
++					   u8 * keyMaterial, WMI_SYNC_FLAG sync_flag);
++	int wmi_add_krk_cmd(struct wmi_t *wmip, u8 * krk);
++	int wmi_delete_krk_cmd(struct wmi_t *wmip);
++	int wmi_deleteKey_cmd(struct wmi_t *wmip, u8 keyIndex);
++	int wmi_set_txPwr_cmd(struct wmi_t *wmip, u8 dbM);
++	int wmi_get_txPwr_cmd(struct wmi_t *wmip);
++	int wmi_addBadAp_cmd(struct wmi_t *wmip, u8 apIndex, u8 * bssid);
++	int wmi_deleteBadAp_cmd(struct wmi_t *wmip, u8 apIndex);
++	int wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, u8 en);
++	int wmi_setPmkid_cmd(struct wmi_t *wmip, u8 * bssid, u8 * pmkId,
++						 u8 set);
++	int wmi_set_access_params_cmd(struct wmi_t *wmip, u16 txop,
++								  u8 eCWmin, u8 eCWmax, u8 aifsn);
++	int wmi_set_retry_limits_cmd(struct wmi_t *wmip, u8 frameType,
++								 u8 trafficClass, u8 maxRetries);
++
++	void wmi_get_current_bssid(struct wmi_t *wmip, u8 * bssid);
++
++	int wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
++	int wmi_get_roam_data_cmd(struct wmi_t *wmip, u8 roamDataType);
++	int wmi_set_roam_ctrl_cmd(struct wmi_t *wmip,
++							  WMI_SET_ROAM_CTRL_CMD * p, u8 size);
++	int wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
++									 WMI_POWERSAVE_TIMERS_CMD * pCmd,
++									 u8 size);
++
++	int wmi_set_opt_mode_cmd(struct wmi_t *wmip, u8 optMode);
++	int wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
++							 u8 frmType,
++							 u8 * dstMacAddr,
++							 u8 * bssid, u16 optIEDataLen, u8 * optIEData);
++
++	int wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, u16 intvl);
++	int wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, u16 voicePktSize);
++	int wmi_set_max_sp_len_cmd(struct wmi_t *wmip, u8 maxSpLen);
++	u8 convert_userPriority_to_trafficClass(u8 userPriority);
++	u8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
++	int wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD * pCmd,
++								u8 tspecCompliance);
++#endif							/* _WMI_API_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,1133 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * This file contains the definitions of the WMI protocol specified in the
++ * Wireless Module Interface (WMI).  It includes definitions of all the
++ * commands and events. Commands are messages from the host to the WM.
++ * Events and Replies are messages from the WM to the host.
++ *
++ * Ownership of correctness in regards to WMI commands
++ * belongs to the host driver and the WM is not required to validate
++ * parameters for value, proper range, or any other checking.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/include/wmi.h#1 $
++ *
++ */
++
++#ifndef _WMI_H_
++#define _WMI_H_
++
++#include "wmix.h"
++
++#define WMI_PROTOCOL_VERSION    0x0001
++#define WMI_PROTOCOL_REVISION   0x0000
++
++#define ATH_MAC_LEN             6	/* length of mac in bytes */
++#define WMI_CMD_MAX_LEN         100
++#define WMI_CONTROL_MSG_MAX_LEN     256
++#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
++#define IS_ETHERTYPE(_typeOrLen)        ((_typeOrLen) >= 0x0600)
++#define RFC1042OUI      {0x00, 0x00, 0x00}
++
++#define IP_ETHERTYPE 0x0800
++
++/*
++ * Data Path
++ */
++	typedef struct {
++		u8 dstMac[ATH_MAC_LEN];
++		u8 srcMac[ATH_MAC_LEN];
++		u16 typeOrLen;
++	} __ATTRIB_PACK ATH_MAC_HDR;
++
++	typedef struct {
++		u8 dsap;
++		u8 ssap;
++		u8 cntl;
++		u8 orgCode[3];
++		u16 etherType;
++	} __ATTRIB_PACK ATH_LLC_SNAP_HDR;
++
++	typedef enum {
++		DATA_MSGTYPE = 0x0,
++		CNTL_MSGTYPE,
++		SYNC_MSGTYPE
++	} WMI_MSG_TYPE;
++
++
++	typedef struct {
++		s8 rssi;
++		u8 info;				/* WMI_MSG_TYPE in lower 2 bits - b1b0 */
++		/* UP in next 3 bits - b4b3b2 */
++#define WMI_DATA_HDR_MSG_TYPE_MASK  0x03
++#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
++#define WMI_DATA_HDR_UP_MASK        0x07
++#define WMI_DATA_HDR_UP_SHIFT       2
++#define WMI_DATA_HDR_IS_MSG_TYPE(h, t)  (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
++	} __ATTRIB_PACK WMI_DATA_HDR;
++
++/*
++ * Control Path
++ */
++	typedef struct {
++		u16 commandId;
++	} __ATTRIB_PACK WMI_CMD_HDR;	/* used for commands and events */
++
++/*
++ * List of Commnands
++ */
++	typedef enum {
++		WMI_CONNECT_CMDID = 0x0001,
++		WMI_RECONNECT_CMDID,
++		WMI_DISCONNECT_CMDID,
++		WMI_SYNCHRONIZE_CMDID,
++		WMI_CREATE_PSTREAM_CMDID,
++		WMI_DELETE_PSTREAM_CMDID,
++		WMI_START_SCAN_CMDID,
++		WMI_SET_SCAN_PARAMS_CMDID,
++		WMI_SET_BSS_FILTER_CMDID,
++		WMI_SET_PROBED_SSID_CMDID,
++		WMI_SET_LISTEN_INT_CMDID,
++		WMI_SET_BMISS_TIME_CMDID,
++		WMI_SET_DISC_TIMEOUT_CMDID,
++		WMI_GET_CHANNEL_LIST_CMDID,
++		WMI_SET_BEACON_INT_CMDID,
++		WMI_GET_STATISTICS_CMDID,
++		WMI_SET_CHANNEL_PARAMS_CMDID,
++		WMI_SET_POWER_MODE_CMDID,
++		WMI_SET_IBSS_PM_CAPS_CMDID,
++		WMI_SET_POWER_PARAMS_CMDID,
++		WMI_SET_POWERSAVE_TIMERS_CMDID,
++		WMI_ADD_CIPHER_KEY_CMDID,
++		WMI_DELETE_CIPHER_KEY_CMDID,
++		WMI_ADD_KRK_CMDID,
++		WMI_DELETE_KRK_CMDID,
++		WMI_SET_PMKID_CMDID,
++		WMI_SET_TX_PWR_CMDID,
++		WMI_GET_TX_PWR_CMDID,
++		WMI_SET_ASSOC_INFO_CMDID,
++		WMI_ADD_BAD_AP_CMDID,
++		WMI_DELETE_BAD_AP_CMDID,
++		WMI_SET_TKIP_COUNTERMEASURES_CMDID,
++		WMI_RSSI_THRESHOLD_PARAMS_CMDID,
++		WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
++		WMI_SET_ACCESS_PARAMS_CMDID,
++		WMI_SET_RETRY_LIMITS_CMDID,
++		WMI_SET_OPT_MODE_CMDID,
++		WMI_OPT_TX_FRAME_CMDID,
++		WMI_SET_VOICE_PKT_SIZE_CMDID,
++		WMI_SET_MAX_SP_LEN_CMDID,
++		WMI_SET_ROAM_CTRL_CMDID,
++		WMI_GET_ROAM_TBL_CMDID,
++		WMI_GET_ROAM_DATA_CMDID,
++		WMI_ENABLE_RM_CMDID,
++		WMI_SET_MAX_OFFHOME_DURATION_CMDID,
++		WMI_EXTENSION_CMDID,	/* Non-wireless extensions */
++		WMI_SNR_THRESHOLD_PARAMS_CMDID,
++		WMI_LQ_THRESHOLD_PARAMS_CMDID,
++		WMI_SET_LPREAMBLE_CMDID,
++		WMI_SET_RTS_CMDID,
++		WMI_CLR_RSSI_SNR_CMDID,
++		WMI_SET_FIXRATES_CMDID,
++		WMI_GET_FIXRATES_CMDID,
++		WMI_SET_AUTH_MODE_CMDID,
++		/*
++		 * Developer commands starts at 0xF000
++		 */
++		WMI_SET_BITRATE_CMDID = 0xF000,
++		WMI_GET_BITRATE_CMDID,
++	} WMI_COMMAND_ID;
++
++/*
++ * Connect Command
++ */
++	typedef enum {
++		INFRA_NETWORK = 0x01,
++		ADHOC_NETWORK = 0x02,
++	} NETWORK_TYPE;
++
++	typedef enum {
++		OPEN_AUTH = 0x01,
++		SHARED_AUTH = 0x02,
++		LEAP_AUTH = 0x04,
++	} DOT11_AUTH_MODE;
++
++	typedef enum {
++		NONE_AUTH = 0x01,
++		WPA_AUTH = 0x02,
++		WPA_PSK_AUTH = 0x03,
++		WPA2_AUTH = 0x04,
++		WPA2_PSK_AUTH = 0x05,
++		WPA_AUTH_CCKM = 0x06,
++		WPA2_AUTH_CCKM = 0x07,
++	} AUTH_MODE;
++
++	typedef enum {
++		NONE_CRYPT = 0x01,
++		WEP_CRYPT = 0x02,
++		TKIP_CRYPT = 0x03,
++		AES_CRYPT = 0x04,
++	} CRYPTO_TYPE;
++
++#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
++#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
++
++#define WMI_MIN_KEY_INDEX   0
++#define WMI_MAX_KEY_INDEX   3
++
++#define WMI_MAX_KEY_LEN     32
++
++#define WMI_MAX_SSID_LEN    32
++
++	typedef struct {
++		u8 networkType;
++		u8 dot11AuthMode;
++		u8 authMode;
++		u8 pairwiseCryptoType;
++		u8 pairwiseCryptoLen;
++		u8 groupCryptoType;
++		u8 groupCryptoLen;
++		u8 ssidLength;
++		u8 ssid[WMI_MAX_SSID_LEN];
++		u16 channel;
++		u8 bssid[ATH_MAC_LEN];
++	} __ATTRIB_PACK WMI_CONNECT_CMD;
++
++/*
++ * WMI_RECONNECT_CMDID
++ */
++	typedef struct {
++		u16 channel;			/* hint */
++		u8 bssid[ATH_MAC_LEN];	/* mandatory if set */
++	} __ATTRIB_PACK WMI_RECONNECT_CMD;
++
++/*
++ * WMI_ADD_CIPHER_KEY_CMDID
++ */
++	typedef enum {
++		PAIRWISE_USAGE = 0x00,
++		GROUP_USAGE = 0x01,
++		TX_USAGE = 0x02,		/* default Tx Key - Static WEP only */
++	} KEY_USAGE;
++
++	typedef struct {
++		u8 keyIndex;
++		u8 keyType;
++		u8 keyUsage;			/* KEY_USAGE */
++		u8 keyLength;
++		u8 keyRSC[8];			/* key replay sequence counter */
++		u8 key[WMI_MAX_KEY_LEN];
++	} __ATTRIB_PACK WMI_ADD_CIPHER_KEY_CMD;
++
++/*
++ * WMI_DELETE_CIPHER_KEY_CMDID
++ */
++	typedef struct {
++		u8 keyIndex;
++	} __ATTRIB_PACK WMI_DELETE_CIPHER_KEY_CMD;
++
++#define WMI_KRK_LEN     16
++/*
++ * WMI_ADD_KRK_CMDID
++ */
++	typedef struct {
++		u8 krk[WMI_KRK_LEN];
++	} __ATTRIB_PACK WMI_ADD_KRK_CMD;
++
++/*
++ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
++ */
++	typedef enum {
++		WMI_TKIP_CM_DISABLE = 0x0,
++		WMI_TKIP_CM_ENABLE = 0x1,
++	} WMI_TKIP_CM_CONTROL;
++
++	typedef struct {
++		u8 cm_en;				/* WMI_TKIP_CM_CONTROL */
++	} __ATTRIB_PACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
++
++/*
++ * WMI_SET_PMKID_CMDID
++ */
++	typedef enum {
++		PMKID_DISABLE = 0,
++		PMKID_ENABLE = 1,
++	} PMKID_ENABLE_FLG;
++
++	typedef struct {
++		u8 bssid[ATH_MAC_LEN];
++		u8 enable;				/* PMKID_ENABLE_FLG */
++		u8 pmkid[16];
++	} __ATTRIB_PACK WMI_SET_PMKID_CMD;
++
++/*
++ * WMI_START_SCAN_CMD
++ */
++	typedef enum {
++		WMI_LONG_SCAN = 0,
++		WMI_SHORT_SCAN = 1,
++	} WMI_SCAN_TYPE;
++
++	typedef struct {
++		u8 scanType;			/* WMI_SCAN_TYPE */
++	} __ATTRIB_PACK WMI_START_SCAN_CMD;
++
++/*
++ * WMI_SET_SCAN_PARAMS_CMDID
++ */
++#define WMI_SHORTSCANRATIO_DEFAULT      3
++
++	typedef struct {
++		u16 fg_start_period;	/* seconds */
++		u16 fg_end_period;		/* seconds */
++		u16 bg_period;			/* seconds */
++		u16 act_chdwell_time;	/* msec */
++		u16 pas_chdwell_time;	/* msec */
++		u8 shortScanRatio;		/* how many shorts scan for one long */
++	} __ATTRIB_PACK WMI_SCAN_PARAMS_CMD;
++
++/*
++ * WMI_SET_BSS_FILTER_CMDID
++ */
++	typedef enum {
++		NONE_BSS_FILTER = 0x0,	/* no beacons forwarded */
++		ALL_BSS_FILTER,			/* all beacons forwarded */
++		PROFILE_FILTER,			/* only beacons matching profile */
++		ALL_BUT_PROFILE_FILTER,	/* all but beacons matching profile */
++		CURRENT_BSS_FILTER,		/* only beacons matching current BSS */
++		ALL_BUT_BSS_FILTER,		/* all but beacons matching BSS */
++		PROBED_SSID_FILTER,		/* beacons matching probed ssid */
++		LAST_BSS_FILTER,		/* marker only */
++	} WMI_BSS_FILTER;
++
++	typedef struct {
++		u8 bssFilter;			/* see WMI_BSS_FILTER */
++	} __ATTRIB_PACK WMI_BSS_FILTER_CMD;
++
++/*
++ * WMI_SET_PROBED_SSID_CMDID
++ */
++#define MAX_PROBED_SSID_INDEX   5
++
++	typedef enum {
++		DISABLE_SSID_FLAG = 0,	/* disables entry */
++		SPECIFIC_SSID_FLAG = 0x01,	/* probes specified ssid */
++		ANY_SSID_FLAG = 0x02,	/* probes for any ssid */
++	} WMI_SSID_FLAG;
++
++	typedef struct {
++		u8 entryIndex;			/* 0 to MAX_PROBED_SSID_INDEX */
++		u8 flag;				/* WMI_SSID_FLG */
++		u8 ssidLength;
++		u8 ssid[32];
++	} __ATTRIB_PACK WMI_PROBED_SSID_CMD;
++
++/*
++ * WMI_SET_LISTEN_INT_CMDID
++ * The Listen interval is between 100 and 1000 TUs
++ */
++#define MIN_LISTEN_INTERVAL 100
++#define MAX_LISTEN_INTERVAL 1000
++#define MIN_LISTEN_BEACONS 1
++#define MAX_LISTEN_BEACONS 50
++
++	typedef struct {
++		u16 listenInterval;
++		u16 numBeacons;
++	} __ATTRIB_PACK WMI_LISTEN_INT_CMD;
++
++/*
++ * WMI_SET_BEACON_INT_CMDID
++ */
++	typedef struct {
++		u16 beaconInterval;
++	} __ATTRIB_PACK WMI_BEACON_INT_CMD;
++
++/*
++ * WMI_SET_BMISS_TIME_CMDID
++ * valid values are between 1000 and 5000 TUs
++ */
++
++#define MIN_BMISS_TIME     1000
++#define MAX_BMISS_TIME     5000
++#define MIN_BMISS_BEACONS  5
++#define MAX_BMISS_BEACONS  50
++
++	typedef struct {
++		u16 bmissTime;
++		u16 numBeacons;
++	} __ATTRIB_PACK WMI_BMISS_TIME_CMD;
++
++/*
++ * WMI_SET_POWER_MODE_CMDID
++ */
++	typedef enum {
++		REC_POWER = 0x01,
++		MAX_PERF_POWER,
++	} WMI_POWER_MODE;
++
++	typedef struct {
++		u8 powerMode;			/* WMI_POWER_MODE */
++	} __ATTRIB_PACK WMI_POWER_MODE_CMD;
++
++/*
++ * WMI_SET_POWER_PARAMS_CMDID
++ */
++	typedef enum {
++		IGNORE_DTIM = 0x01,
++		NORMAL_DTIM = 0x02,
++		STICK_DTIM = 0x03,
++	} WMI_DTIM_POLICY;
++
++	typedef struct {
++		u16 idle_period;		/* msec */
++		u16 pspoll_number;
++		u16 dtim_policy;
++	} __ATTRIB_PACK WMI_POWER_PARAMS_CMD;
++
++	typedef struct {
++		u8 power_saving;
++		u8 ttl;					/* number of beacon periods */
++		u16 atim_windows;		/* msec */
++		u16 timeout_value;		/* msec */
++	} __ATTRIB_PACK WMI_IBSS_PM_CAPS_CMD;
++
++/*
++ * WMI_SET_POWERSAVE_TIMERS_CMDID
++ */
++	typedef struct {
++		u16 psPollTimeout;		/* msec */
++		u16 eospTimeout;		/* msec */
++	} __ATTRIB_PACK WMI_POWERSAVE_TIMERS_CMD;
++
++/*
++ * WMI_SET_VOICE_PKT_SIZE_CMDID
++ */
++	typedef struct {
++		u16 voicePktSize;
++	} __ATTRIB_PACK WMI_SET_VOICE_PKT_SIZE_CMD;
++
++/*
++ * WMI_SET_MAX_SP_LEN_CMDID
++ */
++	typedef enum {
++		DELIVER_ALL_PKT = 0x0,
++		DELIVER_2_PKT = 0x1,
++		DELIVER_4_PKT = 0x2,
++		DELIVER_6_PKT = 0x3,
++	} APSD_SP_LEN_TYPE;
++
++	typedef struct {
++		u8 maxSPLen;
++	} __ATTRIB_PACK WMI_SET_MAX_SP_LEN_CMD;
++
++/*
++ * WMI_SET_DISC_TIMEOUT_CMDID
++ */
++	typedef struct {
++		u8 disconnectTimeout;	/* seconds */
++	} __ATTRIB_PACK WMI_DISC_TIMEOUT_CMD;
++
++	typedef enum {
++		UPLINK_TRAFFIC = 0,
++		DNLINK_TRAFFIC = 1,
++		BIDIR_TRAFFIC = 2,
++	} DIR_TYPE;
++/*
++ * WMI_CREATE_PSTREAM_CMDID
++ */
++	typedef enum {
++		DISABLE_FOR_THIS_AC = 0,
++		ENABLE_FOR_THIS_AC = 1,
++		ENABLE_FOR_ALL_AC = 2,
++	} VOICEPS_CAP_TYPE;
++
++	typedef enum {
++		TRAFFIC_TYPE_APERIODIC = 0,
++		TRAFFIC_TYPE_PERIODIC = 1,
++	} TRAFFIC_TYPE;
++
++	typedef struct {
++		u8 trafficClass;
++		u8 trafficDirection;	/* DIR_TYPE */
++		u8 rxQueueNum;
++		u8 trafficType;			/* TRAFFIC_TYPE */
++		u8 voicePSCapability;	/* VOICEPS_CAP_TYPE */
++		u8 tsid;
++		u8 userPriority;		/* 802.1D user priority */
++		u16 nominalMSDU;		/* in octects */
++		u16 maxMSDU;			/* in octects */
++		u32 minServiceInt;		/* in milli-sec */
++		u32 maxServiceInt;		/* in milli-sec */
++		u32 inactivityInt;		/* in milli-sec */
++		u32 suspensionInt;		/* in milli-sec */
++		u32 serviceStartTime;
++		u32 minDataRate;		/* in bps */
++		u32 meanDataRate;		/* in bps */
++		u32 peakDataRate;		/* in bps */
++		u32 maxBurstSize;
++		u32 delayBound;
++		u32 minPhyRate;			/* in bps */
++		u32 sba;
++		u32 mediumTime;
++	} __ATTRIB_PACK WMI_CREATE_PSTREAM_CMD;
++
++/*
++ * WMI_DELETE_PSTREAM_CMDID
++ */
++	typedef struct {
++		u8 txQueueNumber;
++		u8 rxQueueNumber;
++		u8 trafficDirection;
++		u8 trafficClass;
++	} __ATTRIB_PACK WMI_DELETE_PSTREAM_CMD;
++
++/*
++ * WMI_SET_CHANNEL_PARAMS_CMDID
++ */
++	typedef enum {
++		WMI_11A_MODE = 0x1,
++		WMI_11G_MODE = 0x2,
++		WMI_11AG_MODE = 0x3,
++		WMI_11B_MODE = 0x4,
++		WMI_11GONLY_MODE = 0x5,
++	} WMI_PHY_MODE;
++
++#define WMI_MAX_CHANNELS        32
++
++	typedef struct {
++		u8 phyMode;				/* see WMI_PHY_MODE */
++		u8 numChannels;			/* how many channels follow */
++		u16 channelList[1];		/* channels in Mhz */
++	} __ATTRIB_PACK WMI_CHANNEL_PARAMS_CMD;
++
++
++/*
++ *  WMI_RSSI_THRESHOLD_PARAMS_CMDID
++ *  Setting the polltime to 0 would disable polling.
++ *  Threshold values are in the ascending order, and should agree to:
++ *  (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
++ *      < highThreshold_upperVal)
++ */
++
++	typedef struct WMI_RSSI_THRESHOLD_PARAMS {
++		u8 highThreshold_upperVal;
++		u8 highThreshold_lowerVal;
++		u8 lowThreshold_upperVal;
++		u8 lowThreshold_lowerVal;
++		u32 pollTime;			/* Polling time in seconds */
++	} __ATTRIB_PACK WMI_RSSI_THRESHOLD_PARAMS_CMD;
++
++/*
++ *  WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
++ *  Sets the error reporting event bitmask in target. Target clears it
++ *  upon an error. Subsequent errors are counted, but not reported
++ *  via event, unless the bitmask is set again.
++ */
++	typedef struct {
++		u32 bitmask;
++	} __ATTRIB_PACK WMI_TARGET_ERROR_REPORT_BITMASK;
++
++/*
++ * WMI_SET_TX_PWR_CMDID
++ */
++	typedef struct {
++		u8 dbM;					/* in dbM units */
++	} __ATTRIB_PACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
++
++/*
++ * WMI_SET_ASSOC_INFO_CMDID
++ *
++ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
++ * A 3rd one, the CCX version IE can also be set from the host.
++ */
++#define WMI_MAX_ASSOC_INFO_TYPE    2
++#define WMI_CCX_VER_IE             2	/* ieType to set CCX Version IE */
++
++#define WMI_MAX_ASSOC_INFO_LEN     240
++
++	typedef struct {
++		u8 ieType;
++		u8 bufferSize;
++		u8 assocInfo[1];		/* up to WMI_MAX_ASSOC_INFO_LEN */
++	} __ATTRIB_PACK WMI_SET_ASSOC_INFO_CMD;
++
++
++/*
++ * WMI_GET_TX_PWR_CMDID does not take any parameters
++ */
++
++/*
++ * WMI_ADD_BAD_AP_CMDID
++ */
++#define WMI_MAX_BAD_AP_INDEX      1
++
++	typedef struct {
++		u8 badApIndex;			/* 0 to WMI_MAX_BAD_AP_INDEX */
++		u8 bssid[ATH_MAC_LEN];
++	} __ATTRIB_PACK WMI_ADD_BAD_AP_CMD;
++
++/*
++ * WMI_DELETE_BAD_AP_CMDID
++ */
++	typedef struct {
++		u8 badApIndex;			/* 0 to WMI_MAX_BAD_AP_INDEX */
++	} __ATTRIB_PACK WMI_DELETE_BAD_AP_CMD;
++
++/*
++ * WMI_SET_ACCESS_PARAMS_CMDID
++ */
++#define WMI_DEFAULT_TXOP_ACPARAM    0	/* implies one MSDU */
++#define WMI_DEFAULT_ECWMIN_ACPARAM  4	/* corresponds to CWmin of 15 */
++#define WMI_DEFAULT_ECWMAX_ACPARAM  10	/* corresponds to CWmax of 1023 */
++#define WMI_MAX_CW_ACPARAM          15	/* maximum eCWmin or eCWmax */
++#define WMI_DEFAULT_AIFSN_ACPARAM   2
++#define WMI_MAX_AIFSN_ACPARAM       15
++	typedef struct {
++		u16 txop;				/* in units of 32 usec */
++		u8 eCWmin;
++		u8 eCWmax;
++		u8 aifsn;
++	} __ATTRIB_PACK WMI_SET_ACCESS_PARAMS_CMD;
++
++
++/*
++ * WMI_SET_RETRY_LIMITS_CMDID
++ *
++ * This command is used to customize the number of retries the
++ * wlan device will perform on a given frame.
++ */
++#define WMI_MIN_RETRIES 2
++#define WMI_MAX_RETRIES 13
++	typedef enum {
++		MGMT_FRAMETYPE = 0,
++		CONTROL_FRAMETYPE = 1,
++		DATA_FRAMETYPE = 2
++	} WMI_FRAMETYPE;
++
++	typedef struct {
++		u8 frameType;			/* WMI_FRAMETYPE */
++		u8 trafficClass;		/* applies only to DATA_FRAMETYPE */
++		u8 maxRetries;
++	} __ATTRIB_PACK WMI_SET_RETRY_LIMITS_CMD;
++/*
++ * WMI_SET_ROAM_CTRL_CMDID
++ *
++ * This command is used to influence the Roaming behaviour
++ * Set the host biases of the BSSs before setting the roam mode as bias
++ * based.
++ */
++
++/*
++ * Different types of Roam Control
++ */
++
++	typedef enum {
++		WMI_FORCE_ROAM = 1,		/* Roam to the specified BSSID */
++		WMI_SET_ROAM_MODE = 2,	/* default ,progd bias, no roam */
++		WMI_SET_HOST_BIAS = 3,	/* Set the Host Bias */
++	} WMI_ROAM_CTRL_TYPE;
++
++#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
++#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_HOST_BIAS
++
++/*
++ * ROAM MODES
++ */
++
++	typedef enum {
++		WMI_DEFAULT_ROAM_MODE = 1,	/* RSSI based ROAM */
++		WMI_HOST_BIAS_ROAM_MODE = 2,	/* HOST BIAS based ROAM */
++		WMI_LOCK_BSS_MODE = 3,	/* Lock to the Current BSS - no Roam */
++		WMI_DISABLE_ROAM = 4	/* disables all auto-nomous roaming
++								   behaviour */
++	} WMI_ROAM_MODE;
++
++/*
++ * BSS HOST BIAS INFO
++ */
++
++	typedef struct {
++		u8 bssid[ATH_MAC_LEN];
++		s8 bias;
++	} __ATTRIB_PACK WMI_BSS_BIAS;
++
++	typedef struct {
++		u8 numBss;
++		WMI_BSS_BIAS bssBias[1];
++	} __ATTRIB_PACK WMI_BSS_BIAS_INFO;
++
++	typedef struct {
++		u8 roamCtrlType;
++		union {
++			u8 bssid[ATH_MAC_LEN];	/* WMI_FORCE_ROAM */
++			u8 roamMode;		/* WMI_SET_ROAM_MODE */
++			WMI_BSS_BIAS_INFO bssBiasInfo;	/* WMI_SET_HOST_BIAS */
++		} __ATTRIB_PACK info;
++	} __ATTRIB_PACK WMI_SET_ROAM_CTRL_CMD;
++
++/*
++ * WMI_ENABLE_RM_CMDID
++ */
++	typedef struct {
++		u8 enable_radio_measurements;
++	} __ATTRIB_PACK WMI_ENABLE_RM_CMD;
++
++/*
++ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
++ */
++	typedef struct {
++		u8 max_offhome_duration;
++	} __ATTRIB_PACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
++
++
++
++/*
++ * Command Replies
++ */
++
++/*
++ * WMI_GET_CHANNEL_LIST_CMDID reply
++ */
++	typedef struct {
++		u8 reserved1;
++		u8 numChannels;			/* number of channels in reply */
++		u16 channelList[1];		/* channel in Mhz */
++	} __ATTRIB_PACK WMI_CHANNEL_LIST_REPLY;
++
++	typedef enum {
++		A_SUCCEEDED = A_OK,
++		A_MBOX1_OK = 1,
++		A_MBOX2_OK = 2,
++		A_MBOX3_OK = 3,
++		A_FAILED_DELETE_INVALID_MBOX = 253,
++		A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
++	} PSTREAM_REPLY_STATUS;
++
++	typedef struct {
++		u8 status;				/* PSTREAM_REPLY_STATUS */
++		u8 txQueueNumber;
++		u8 rxQueueNumber;
++		u8 trafficClass;
++		u8 trafficDirection;	/* DIR_TYPE */
++	} __ATTRIB_PACK WMI_CRE_PRIORITY_STREAM_REPLY;
++
++	typedef struct {
++		u8 status;				/* PSTREAM_REPLY_STATUS */
++		u8 txQueueNumber;
++		u8 rxQueueNumber;
++		u8 trafficDirection;	/* DIR_TYPE */
++		u8 trafficClass;
++	} __ATTRIB_PACK WMI_DEL_PRIORITY_STREAM_REPLY;
++
++
++/*
++ * List of Events (target to host)
++ */
++	typedef enum {
++		WMI_READY_EVENTID = 0x1001,
++		WMI_CONNECT_EVENTID,
++		WMI_DISCONNECT_EVENTID,
++		WMI_BSSINFO_EVENTID,
++		WMI_CMDERROR_EVENTID,
++		WMI_REGDOMAIN_EVENTID,
++		WMI_PSTREAM_TIMEOUT_EVENTID,
++		WMI_NEIGHBOR_REPORT_EVENTID,
++		WMI_TKIP_MICERR_EVENTID,
++		WMI_SCAN_COMPLETE_EVENTID,
++		WMI_REPORT_STATISTICS_EVENTID,
++		WMI_RSSI_THRESHOLD_EVENTID,
++		WMI_ERROR_REPORT_EVENTID,
++		WMI_OPT_RX_FRAME_EVENTID,
++		WMI_REPORT_ROAM_TBL_EVENTID,
++		WMI_EXTENSION_EVENTID,
++		WMI_CAC_EVENTID,
++		WMI_SNR_THRESHOLD_EVENTID,
++		WMI_LQ_THRESHOLD_EVENTID,
++		WMI_TX_RETRY_ERR_EVENTID,
++		WMI_REPORT_ROAM_DATA_EVENTID,
++	} WMI_EVENT_ID;
++
++	typedef enum {
++		WMI_11A_CAPABILITY = 1,
++		WMI_11G_CAPABILITY = 2,
++		WMI_11AG_CAPABILITY = 3,
++	} WMI_PHY_CAPABILITY;
++
++	typedef struct {
++		u8 macaddr[ATH_MAC_LEN];
++		u8 phyCapability;		/* WMI_PHY_CAPABILITY */
++	} __ATTRIB_PACK WMI_READY_EVENT;
++
++/*
++ * Connect Event
++ */
++	typedef struct {
++		u16 channel;
++		u8 bssid[ATH_MAC_LEN];
++		u16 listenInterval;
++		u8 beaconIeLen;
++		u8 assocReqLen;
++		u8 assocRespLen;
++		u8 assocInfo[1];
++	} __ATTRIB_PACK WMI_CONNECT_EVENT;
++
++/*
++ * Disconnect Event
++ */
++	typedef enum {
++		NO_NETWORK_AVAIL = 0x01,
++		LOST_LINK = 0x02,		/* bmiss */
++		DISCONNECT_CMD = 0x03,
++		BSS_DISCONNECTED = 0x04,
++		AUTH_FAILED = 0x05,
++		ASSOC_FAILED = 0x06,
++		NO_RESOURCES_AVAIL = 0x07,
++		CSERV_DISCONNECT = 0x08,
++		INVALID_PROFILE = 0x0a,
++	} WMI_DISCONNECT_REASON;
++
++	typedef struct {
++		u8 disconnectReason;	/* see WMI_DISCONNECT_REASON */
++		u8 bssid[ATH_MAC_LEN];	/* set if known */
++		u8 assocRespLen;
++		u8 assocInfo[1];
++	} __ATTRIB_PACK WMI_DISCONNECT_EVENT;
++
++/*
++ * BSS Info Event.
++ * Mechanism used to inform host of the presence and characteristic of
++ * wireless networks present.  Consists of bss info header followed by
++ * the beacon or probe-response frame body.  The 802.11 header is not included.
++ */
++	typedef enum {
++		BEACON_FTYPE = 0x1,
++		PROBERESP_FTYPE,
++	} WMI_BI_FTYPE;
++
++	typedef struct {
++		u16 channel;
++		u8 frameType;			/* see WMI_BI_FTYPE */
++		s8 rssi;
++		u8 bssid[ATH_MAC_LEN];
++	} __ATTRIB_PACK WMI_BSS_INFO_HDR;
++
++/*
++ * Command Error Event
++ */
++	typedef enum {
++		INVALID_PARAM = 0x01,
++		ILLEGAL_STATE = 0x02,
++		INTERNAL_ERROR = 0x03,
++	} WMI_ERROR_CODE;
++
++	typedef struct {
++		u16 commandId;
++		u8 errorCode;
++	} __ATTRIB_PACK WMI_CMD_ERROR_EVENT;
++
++/*
++ * New Regulatory Domain Event
++ */
++	typedef struct {
++		u32 regDomain;
++	} __ATTRIB_PACK WMI_REG_DOMAIN_EVENT;
++
++	typedef struct {
++		u8 txQueueNumber;
++		u8 rxQueueNumber;
++		u8 trafficDirection;
++	} __ATTRIB_PACK WMI_PSTREAM_TIMEOUT_EVENT;
++
++/*
++ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
++ * the host of BSS's it has found that matches the current profile.
++ * It can be used by the host to cache PMKs and/to initiate pre-authentication
++ * if the BSS supports it.  The first bssid is always the current associated
++ * BSS.
++ * The bssid and bssFlags information repeats according to the number
++ * or APs reported.
++ */
++	typedef enum {
++		WMI_DEFAULT_BSS_FLAGS = 0x00,
++		WMI_PREAUTH_CAPABLE_BSS = 0x01,
++		WMI_PMKID_VALID_BSS = 0x02,
++	} WMI_BSS_FLAGS;
++
++	typedef struct {
++		u8 bssid[ATH_MAC_LEN];
++		u8 bssFlags;			/* see WMI_BSS_FLAGS */
++	} __ATTRIB_PACK WMI_NEIGHBOR_INFO;
++
++	typedef struct {
++		int numberOfAps;
++		WMI_NEIGHBOR_INFO neighbor[1];
++	} __ATTRIB_PACK WMI_NEIGHBOR_REPORT_EVENT;
++
++/*
++ * TKIP MIC Error Event
++ */
++	typedef struct {
++		u8 keyid;
++		u8 ismcast;
++	} __ATTRIB_PACK WMI_TKIP_MICERR_EVENT;
++
++/*
++ * WMI_SCAN_COMPLETE_EVENTID - no parameters
++ */
++
++#define MAX_OPT_DATA_LEN 1400
++
++/*
++ * WMI_SET_ADHOC_BSSID_CMDID
++ */
++	typedef struct {
++		u8 bssid[ATH_MAC_LEN];
++	} __ATTRIB_PACK WMI_SET_ADHOC_BSSID_CMD;
++
++/*
++ * WMI_SET_OPT_MODE_CMDID
++ */
++	typedef enum {
++		SPECIAL_OFF,
++		SPECIAL_ON,
++	} OPT_MODE_TYPE;
++
++	typedef struct {
++		u8 optMode;
++	} __ATTRIB_PACK WMI_SET_OPT_MODE_CMD;
++
++/*
++ * WMI_TX_OPT_FRAME_CMDID
++ */
++	typedef enum {
++		OPT_PROBE_REQ = 0x01,
++		OPT_PROBE_RESP = 0x02,
++		OPT_CPPP_START = 0x03,
++		OPT_CPPP_STOP = 0x04,
++	} __ATTRIB_PACK WMI_OPT_FTYPE;
++
++	typedef struct {
++		u8 frmType;
++		u8 dstAddr[ATH_MAC_LEN];
++		u8 bssid[ATH_MAC_LEN];
++		u16 optIEDataLen;
++		u8 *optIEData;
++	} __ATTRIB_PACK WMI_OPT_TX_FRAME_CMD;
++
++/*
++ * Special frame receive Event.
++ * Mechanism used to inform host of the receiption of the special frames.
++ * Consists of special frame info header followed by special frame body.
++ * The 802.11 header is not included.
++ */
++	typedef struct {
++		u16 channel;
++		u8 frameType;			/* see WMI_OPT_FTYPE */
++		s8 rssi;
++		u8 srcAddr[ATH_MAC_LEN];
++		u8 bssid[ATH_MAC_LEN];
++	} __ATTRIB_PACK WMI_OPT_RX_INFO_HDR;
++
++/*
++ * Reporting statistics.
++ */
++	typedef struct {
++		u32 tx_packets;
++		u32 tx_bytes;
++		u32 tx_unicast_pkts;
++		u32 tx_unicast_bytes;
++		u32 tx_multicast_pkts;
++		u32 tx_multicast_bytes;
++		u32 tx_broadcast_pkts;
++		u32 tx_broadcast_bytes;
++		u32 tx_rts_success_cnt;
++		u32 tx_packet_per_ac[4];
++
++		u32 tx_errors;
++		u32 tx_failed_cnt;
++		u32 tx_retry_cnt;
++		u32 tx_rts_fail_cnt;
++	} __ATTRIB_PACK tx_stats_t;
++
++	typedef struct {
++		u32 rx_packets;
++		u32 rx_bytes;
++		u32 rx_unicast_pkts;
++		u32 rx_unicast_bytes;
++		u32 rx_multicast_pkts;
++		u32 rx_multicast_bytes;
++		u32 rx_broadcast_pkts;
++		u32 rx_broadcast_bytes;
++		u32 rx_fragment_pkt;
++
++		u32 rx_errors;
++		u32 rx_crcerr;
++		u32 rx_key_cache_miss;
++		u32 rx_decrypt_err;
++		u32 rx_duplicate_frames;
++	} __ATTRIB_PACK rx_stats_t;
++
++	typedef struct {
++		u32 tkip_local_mic_failure;
++		u32 tkip_counter_measures_invoked;
++		u32 tkip_replays;
++		u32 tkip_format_errors;
++		u32 ccmp_format_errors;
++		u32 ccmp_replays;
++	} __ATTRIB_PACK tkip_ccmp_stats_t;
++
++	typedef struct {
++		u32 power_save_failure_cnt;
++	} __ATTRIB_PACK pm_stats_t;
++
++	typedef struct {
++		u32 cs_bmiss_cnt;
++		u32 cs_lowRssi_cnt;
++		u16 cs_connect_cnt;
++		u16 cs_disconnect_cnt;
++		u8 cs_aveBeacon_rssi;
++		u8 cs_lastRoam_msec;
++	} __ATTRIB_PACK cserv_stats_t;
++
++	typedef struct {
++		tx_stats_t tx_stats;
++		rx_stats_t rx_stats;
++		tkip_ccmp_stats_t tkipCcmpStats;
++	} __ATTRIB_PACK wlan_net_stats_t;
++
++	typedef struct {
++		wlan_net_stats_t txrxStats;
++		cserv_stats_t cservStats;
++		pm_stats_t pmStats;
++		s16 noise_floor_calibation;
++	} __ATTRIB_PACK WMI_TARGET_STATS;
++
++/*
++ * WMI_RSSI_THRESHOLD_EVENTID.
++ * Indicate the RSSI events to host. Events are indicated when we breach a
++ * thresold value.
++ */
++	typedef enum {
++		WMI_RSSI_LOWTHRESHOLD_BELOW_LOWERVAL = 1,
++		WMI_RSSI_LOWTHRESHOLD_LOWERVAL,
++		WMI_RSSI_LOWTHRESHOLD_UPPERVAL,
++		WMI_RSSI_HIGHTHRESHOLD_LOWERVAL,
++		WMI_RSSI_HIGHTHRESHOLD_HIGHERVAL
++	} WMI_RSSI_THRESHOLD_VAL;
++
++	typedef struct {
++		u8 range;
++	} __ATTRIB_PACK WMI_RSSI_THRESHOLD_EVENT;
++
++/*
++ *  WMI_ERROR_REPORT_EVENTID
++ */
++	typedef enum {
++		WMI_TARGET_PM_ERR_FAIL = 0x00000001,
++		WMI_TARGET_KEY_NOT_FOUND = 0x00000002,
++		WMI_TARGET_DECRYPTION_ERR = 0x00000004,
++		WMI_TARGET_BMISS = 0x00000008,
++		WMI_PSDISABLE_NODE_JOIN = 0x00000010
++	} __ATTRIB_PACK WMI_TARGET_ERROR_VAL;
++
++	typedef struct {
++		u32 errorVal;
++	} __ATTRIB_PACK WMI_TARGET_ERROR_REPORT_EVENT;
++
++/*
++ * WMI_REPORT_ROAM_TBL_EVENTID
++ */
++#define MAX_ROAM_TBL_CAND   5
++
++	typedef struct {
++		u8 bssid[ATH_MAC_LEN];
++		s8 rssi;
++		s8 rssidt;
++		s8 last_rssi;
++		s32 roam_util;
++		s8 util;
++		s8 bias;
++	} __ATTRIB_PACK WMI_BSS_ROAM_INFO;
++
++
++	typedef struct {
++		u8 roamMode;
++		u8 numEntries;
++		WMI_BSS_ROAM_INFO bssRoamInfo[1];
++	} __ATTRIB_PACK WMI_TARGET_ROAM_TBL;
++
++/*
++ *  WMI_CAC_EVENTID
++ */
++	typedef enum {
++		CAC_INDICATION_ADMISSION = 0x00,
++		CAC_INDICATION_ADMISSION_RESP = 0x01,
++		CAC_INDICATION_DELETE = 0x02,
++		CAC_INDICATION_NO_RESP = 0x03,
++	} CAC_INDICATION;
++
++#define WMM_TSPEC_IE_LEN   63
++
++	typedef struct {
++		u8 ac;
++		u8 cac_indication;
++		u8 statusCode;
++		u8 tspecSuggestion[WMM_TSPEC_IE_LEN];
++	} __ATTRIB_PACK WMI_CAC_EVENT;
++
++/*
++ * developer commands
++ */
++
++/*
++ * WMI_SET_BITRATE_CMDID
++ *
++ * Get bit rate cmd uses same definition as set bit rate cmd
++ */
++	typedef enum {
++		RATE_AUTO = -1,
++		RATE_1Mb = 0,
++		RATE_2Mb = 1,
++		RATE_5_5Mb = 2,
++		RATE_11Mb = 3,
++		RATE_6Mb = 4,
++		RATE_9Mb = 5,
++		RATE_12Mb = 6,
++		RATE_18Mb = 7,
++		RATE_24Mb = 8,
++		RATE_36Mb = 9,
++		RATE_48Mb = 10,
++		RATE_54Mb = 11,
++	} WMI_BIT_RATE;
++
++	typedef struct {
++		s8 rateIndex;			/* see WMI_BIT_RATE */
++	} __ATTRIB_PACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY;
++
++	typedef enum {
++		ROAM_DATA_TIME = 1,		/* Get The Roam Time Data */
++	} ROAM_DATA_TYPE;
++
++	typedef struct {
++		u32 disassoc_time;
++		u8 disassoc_bssid[ATH_MAC_LEN];
++		s8 disassoc_bss_rssi;
++		u32 no_txrx_time;
++		u32 assoc_time;
++		u8 assoc_bssid[ATH_MAC_LEN];
++		s8 assoc_bss_rssi;
++		u32 allow_txrx_time;
++		u32 last_data_txrx_time;
++		u32 first_data_txrx_time;
++	} __ATTRIB_PACK WMI_TARGET_ROAM_TIME;
++
++	typedef struct {
++		u8 roamDataType;
++		union {
++			WMI_TARGET_ROAM_TIME roamTime;
++		} u;
++	} __ATTRIB_PACK WMI_TARGET_ROAM_DATA;
++
++#endif							/* _WMI_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi_host.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmi_host.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This file contains local definitios for the wmi host module.
++ *
++ */
++
++#ifndef _WMI_HOST_H_
++#define _WMI_HOST_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * IP QoS Field definitions according to 802.1p
++ */
++#define BEST_EFFORT_PRI         0
++#define BACKGROUND_PRI          1
++#define EXCELLENT_EFFORT_PRI    3
++#define CONTROLLED_LOAD_PRI     4
++#define VIDEO_PRI               5
++#define VOICE_PRI               6
++#define NETWORK_CONTROL_PRI     7
++
++	struct wmi_stats {
++		u32 cmd_len_err;
++		u32 cmd_id_err;
++	};
++
++	struct wmi_priority_state {
++		u8 inUse;
++		u8 mbox;
++	};
++
++	struct wmi_mbox_state {
++		u8 trafficClass;
++		s8 priorityNum;
++	};
++
++	struct wmi_t {
++		u8 wmi_ready;
++		u8 wmi_numQoSStream;
++		struct wmi_priority_state wmi_priority[WMI_MAX_NUM_PRI_STREAMS];
++		struct wmi_mbox_state wmi_mboxMap[2][WMI_MBOX_COUNT];
++		s8 wmi_trafficClassMap[2][WMM_NUM_AC];
++		u8 wmi_olderPriRxMbox;
++		u8 wmi_newerPriRxMbox;
++		void *wmi_devt;
++		struct wmi_stats wmi_stats;
++		struct ieee80211_node_table wmi_scan_table;
++		u8 wmi_pstreamCmdInProgress[2][WMM_NUM_AC];
++		u8 wmi_cpstreamCmdInProgress;
++		u8 wmi_bssid[ATH_MAC_LEN];
++		u8 wmi_powerMode;
++		u8 wmi_phyMode;
++	};
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _WMI_HOST_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmix.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/include/wmix.h	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,196 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * This file contains extensions of the WMI protocol specified in the
++ * Wireless Module Interface (WMI).  It includes definitions of all
++ * extended commands and events.  Extensions include useful commands
++ * that are not directly related to wireless activities.  They may
++ * be hardware-specific, and they might not be supported on all
++ * implementations.
++ *
++ * Extended WMIX commands are encapsulated in a WMI message with
++ * cmd=WMI_EXTENSION_CMD.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/include/wmix.h#1 $
++ *
++ */
++
++#ifndef _WMIX_H_
++#define _WMIX_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * Extended WMI commands are those that are needed during wireless
++ * operation, but which are not really wireless commands.  This allows,
++ * for instance, platform-specific commands.  Extended WMI commands are
++ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
++ * Extended WMI events are similarly embedded in a WMI event message with
++ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
++ */
++	typedef struct {
++		u16 commandId;
++	} __ATTRIB_PACK WMIX_CMD_HDR;
++
++	typedef enum {
++		WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
++		WMIX_DSETDATA_REPLY_CMDID,
++		WMIX_GPIO_OUTPUT_SET_CMDID,
++		WMIX_GPIO_INPUT_GET_CMDID,
++		WMIX_GPIO_REGISTER_SET_CMDID,
++		WMIX_GPIO_REGISTER_GET_CMDID,
++		WMIX_GPIO_INTR_ACK_CMDID,
++	} WMIX_COMMAND_ID;
++
++	typedef enum {
++		WMIX_DSETOPENREQ_EVENTID = 0x3001,
++		WMIX_DSETCLOSE_EVENTID,
++		WMIX_DSETDATAREQ_EVENTID,
++		WMIX_GPIO_INTR_EVENTID,
++		WMIX_GPIO_DATA_EVENTID,
++		WMIX_GPIO_ACK_EVENTID,
++	} WMIX_EVENT_ID;
++
++/*
++ * =============DataSet support=================
++ */
++
++/*
++ * WMIX_DSETOPENREQ_EVENTID
++ * DataSet Open Request Event
++ */
++	typedef struct {
++		u32 dset_id;
++		u32 targ_dset_handle;	/* echo'ed, not used by Host, */
++		u32 targ_reply_fn;		/* echo'ed, not used by Host, */
++		u32 targ_reply_arg;		/* echo'ed, not used by Host, */
++	} __ATTRIB_PACK WMIX_DSETOPENREQ_EVENT;
++
++/*
++ * WMIX_DSETCLOSE_EVENTID
++ * DataSet Close Event
++ */
++	typedef struct {
++		u32 access_cookie;
++	} __ATTRIB_PACK WMIX_DSETCLOSE_EVENT;
++
++/*
++ * WMIX_DSETDATAREQ_EVENTID
++ * DataSet Data Request Event
++ */
++	typedef struct {
++		u32 access_cookie;
++		u32 offset;
++		u32 length;
++		u32 targ_buf;			/* echo'ed, not used by Host, */
++		u32 targ_reply_fn;		/* echo'ed, not used by Host, */
++		u32 targ_reply_arg;		/* echo'ed, not used by Host, */
++	} __ATTRIB_PACK WMIX_DSETDATAREQ_EVENT;
++
++	typedef struct {
++		u32 status;
++		u32 targ_dset_handle;
++		u32 targ_reply_fn;
++		u32 targ_reply_arg;
++		u32 access_cookie;
++		u32 size;
++		u32 version;
++	} __ATTRIB_PACK WMIX_DSETOPEN_REPLY_CMD;
++
++	typedef struct {
++		u32 status;
++		u32 targ_buf;
++		u32 targ_reply_fn;
++		u32 targ_reply_arg;
++		u32 length;
++		u8 buf[1];
++	} __ATTRIB_PACK WMIX_DSETDATA_REPLY_CMD;
++
++
++/*
++ * =============GPIO support=================
++ * All masks are 18-bit masks with bit N operating on GPIO pin N.
++ */
++
++#if defined(AR6000)
++#include "AR6000/AR6000_gpio.h"
++#endif							/* AR6000 */
++
++/*
++ * Set GPIO pin output state.
++ * In order for output to be driven, a pin must be enabled for output.
++ * This can be done during initialization through the GPIO Configuration
++ * DataSet, or during operation with the enable_mask.
++ *
++ * If a request is made to simultaneously set/clear or set/disable or
++ * clear/disable or disable/enable, results are undefined.
++ */
++	typedef struct {
++		u32 set_mask;			/* pins to set */
++		u32 clear_mask;			/* pins to clear */
++		u32 enable_mask;		/* pins to enable for output */
++		u32 disable_mask;		/* pins to disable/tristate */
++	} __ATTRIB_PACK WMIX_GPIO_OUTPUT_SET_CMD;
++
++/*
++ * Set a GPIO register.  For debug/exceptional cases.
++ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
++ * platform-dependent header.
++ */
++	typedef struct {
++		u32 gpioreg_id;			/* GPIO register ID */
++		u32 value;				/* value to write */
++	} __ATTRIB_PACK WMIX_GPIO_REGISTER_SET_CMD;
++
++/* Get a GPIO register.  For debug/exceptional cases. */
++	typedef struct {
++		u32 gpioreg_id;			/* GPIO register to read */
++	} __ATTRIB_PACK WMIX_GPIO_REGISTER_GET_CMD;
++
++/*
++ * Host acknowledges and re-arms GPIO interrupts.  A single
++ * message should be used to acknowledge all interrupts that
++ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
++ */
++	typedef struct {
++		u32 ack_mask;			/* interrupts to acknowledge */
++	} __ATTRIB_PACK WMIX_GPIO_INTR_ACK_CMD;
++
++/*
++ * Target informs Host of GPIO interrupts that have ocurred since the
++ * last WMIX_GIPO_INTR_ACK_CMD was received.  Additional information --
++ * the current GPIO input values is provided -- in order to support
++ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
++ */
++	typedef struct {
++		u32 intr_mask;			/* pending GPIO interrupts */
++		u32 input_values;		/* recent GPIO input values */
++	} __ATTRIB_PACK WMIX_GPIO_INTR_EVENT;
++
++/*
++ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
++ * using a GPIO_DATA_EVENT with
++ *   value set to the mask of GPIO pin inputs and
++ *   reg_id set to GPIO_ID_NONE
++ *
++ *
++ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
++ * using a GPIO_DATA_EVENT with
++ *   value set to the value of the requested register and
++ *   reg_id identifying the register (reflects the original request)
++ * NB: reg_id supports the future possibility of unsolicited
++ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
++ * simplify Host GPIO support.
++ */
++	typedef struct {
++		u32 value;
++		u32 reg_id;
++	} __ATTRIB_PACK WMIX_GPIO_DATA_EVENT;
++
++#ifdef __cplusplus
++}
++#endif
++#endif							/* _WMIX_H_ */
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/install
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/install	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,3 @@
++make
++sudo cp ar6k.ko /lib/modules/2.6.24-rc1/kernel/drivers/net/wireless/
++sudo depmod -a
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/Kconfig
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/Kconfig	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,11 @@
++config AR6K
++	tristate "Atheros AR600x driver"
++	select WIRELESS_EXT
++
++	---help---
++	  Good luck
++
++config AR6K_DEBUG
++	bool "AR6K debugging"
++	depends on AR6K
++
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/Makefile	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,19 @@
++#
++#  AR6K Kernel Module makefile.
++#
++obj-$(CONFIG_AR6K) += ar6k.o
++
++obj-dir		:= /htc
++ar6k-objs += \
++	ar6k_main.o		\
++	hif.o			\
++	bmi.o			\
++	htc/htc.o		\
++	htc/htc_send.o			\
++	htc/htc_recv.o			\
++	htc/htc_utils.o			\
++	htc/htc_events.o		\
++	wmi.o			\
++	wlan/wlan_node.o		\
++	wlan/wlan_recv_beacon.o		\
++	wlan/wlan_utils.o
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/Makefile	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_AR6K) += wlan_node.o  wlan_recv_beacon.o  wlan_utils.o
++
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_node.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_node.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,259 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright (c) 2004-2006 Atheros Communications
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ */
++/*
++ * IEEE 802.11 node handling support.
++ */
++#include "../include/athdefs.h"
++#include "../include/osapi.h"
++#include "../include/ieee80211.h"
++#include "../include/wlan_api.h"
++#include "../include/ieee80211_node.h"
++#include "../include/htc.h"
++#include "../include/wmi.h"
++#include "../include/wmi_api.h"
++
++#ifdef CONFIG_AR6K_DEBUG
++static int wlan_node_debug = 1;
++#define ND_PRINTF      if (wlan_node_debug) A_PRINTF
++#else
++#define ND_PRINTF(args...)
++#endif
++
++static void wlan_node_timeout(unsigned long arg);
++static bss_t *_ieee80211_find_node(struct ieee80211_node_table *nt,
++								   const u8 * macaddr);
++
++bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
++{
++	bss_t *ni;
++
++	ni = A_MALLOC_NOWAIT(sizeof(bss_t));
++
++	if (ni != NULL) {
++		ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
++		if (ni->ni_buf == NULL) {
++			A_FREE(ni);
++			ni = NULL;
++		}
++	}
++
++	/* Make sure our lists are clean */
++	ni->ni_list_next = NULL;
++	ni->ni_list_prev = NULL;
++	ni->ni_hash_next = NULL;
++	ni->ni_hash_prev = NULL;
++
++	return ni;
++}
++
++void wlan_node_free(bss_t * ni)
++{
++	if (ni->ni_buf != NULL) {
++		A_FREE(ni->ni_buf);
++	}
++
++	A_FREE(ni);
++}
++
++void
++wlan_setup_node(struct ieee80211_node_table *nt, bss_t * ni,
++				const u8 * macaddr)
++{
++	int hash;
++
++	A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
++	hash = IEEE80211_NODE_HASH(macaddr);
++	ieee80211_node_initref(ni);	/* mark referenced */
++
++	ni->ni_tstamp = jiffies + (WLAN_NODE_INACT_TIMEOUT_MSEC / 1000) * HZ;
++	IEEE80211_NODE_LOCK_BH(nt);
++
++	/* Insert at the end of the node list */
++	ni->ni_list_next = NULL;
++	ni->ni_list_prev = nt->nt_node_last;
++	if (nt->nt_node_last != NULL) {
++		nt->nt_node_last->ni_list_next = ni;
++	}
++	nt->nt_node_last = ni;
++	if (nt->nt_node_first == NULL) {
++		nt->nt_node_first = ni;
++	}
++
++	/* Insert into the hash list i.e. the bucket */
++	if ((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) {
++		nt->nt_hash[hash]->ni_hash_prev = ni;
++	}
++	ni->ni_hash_prev = NULL;
++	nt->nt_hash[hash] = ni;
++
++	IEEE80211_NODE_UNLOCK_BH(nt);
++}
++
++static bss_t *_ieee80211_find_node(struct ieee80211_node_table *nt,
++								   const u8 * macaddr)
++{
++	bss_t *ni;
++	int hash;
++
++	IEEE80211_NODE_LOCK_ASSERT(nt);
++
++	hash = IEEE80211_NODE_HASH(macaddr);
++	for (ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
++		if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
++			ieee80211_node_incref(ni);	/* mark referenced */
++			return ni;
++		}
++	}
++	return NULL;
++}
++
++bss_t *wlan_find_node(struct ieee80211_node_table * nt, const u8 * macaddr)
++{
++	bss_t *ni;
++
++	IEEE80211_NODE_LOCK(nt);
++	ni = _ieee80211_find_node(nt, macaddr);
++	IEEE80211_NODE_UNLOCK(nt);
++	return ni;
++}
++
++/*
++ * Reclaim a node.  If this is the last reference count then
++ * do the normal free work.  Otherwise remove it from the node
++ * table and mark it gone by clearing the back-reference.
++ */
++void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t * ni)
++{
++	IEEE80211_NODE_LOCK(nt);
++
++	if (ni->ni_list_prev == NULL) {
++		/* First in list so fix the list head */
++		nt->nt_node_first = ni->ni_list_next;
++	} else {
++		ni->ni_list_prev->ni_list_next = ni->ni_list_next;
++	}
++
++	if (ni->ni_list_next == NULL) {
++		/* Last in list so fix list tail */
++		nt->nt_node_last = ni->ni_list_prev;
++	} else {
++		ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
++	}
++
++	if (ni->ni_hash_prev == NULL) {
++		/* First in list so fix the list head */
++		int hash;
++		hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
++		nt->nt_hash[hash] = ni->ni_hash_next;
++	} else {
++		ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
++	}
++
++	if (ni->ni_hash_next != NULL) {
++		ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
++	}
++	wlan_node_free(ni);
++
++	IEEE80211_NODE_UNLOCK(nt);
++}
++
++static void wlan_node_dec_free(bss_t * ni)
++{
++	if (ieee80211_node_dectestref(ni)) {
++		wlan_node_free(ni);
++	}
++}
++
++void wlan_free_allnodes(struct ieee80211_node_table *nt)
++{
++	bss_t *ni;
++
++	while ((ni = nt->nt_node_first) != NULL) {
++		wlan_node_reclaim(nt, ni);
++	}
++}
++
++void
++wlan_iterate_nodes(struct ieee80211_node_table *nt,
++				   wlan_node_iter_func * f, void *arg)
++{
++	bss_t *ni;
++	u32 gen;
++
++	gen = nt->nt_scangen++;
++	IEEE80211_NODE_LOCK(nt);
++	for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
++		if (ni->ni_scangen != gen) {
++			ni->ni_scangen = gen;
++			(void) ieee80211_node_incref(ni);
++			(*f) (arg, ni);
++			wlan_node_dec_free(ni);
++		}
++	}
++	IEEE80211_NODE_UNLOCK(nt);
++}
++
++/*
++ * Node table support.
++ */
++void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
++{
++	int i;
++	ND_PRINTF("node table = 0x%x\n", (u32) nt);
++	IEEE80211_NODE_LOCK_INIT(nt);
++
++	nt->nt_node_first = nt->nt_node_last = NULL;
++	for (i = 0; i < IEEE80211_NODE_HASHSIZE; i++) {
++		nt->nt_hash[i] = NULL;
++	}
++	A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
++	A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
++	nt->nt_wmip = wmip;
++}
++
++static void wlan_node_timeout(unsigned long arg)
++{
++	struct ieee80211_node_table *nt = (struct ieee80211_node_table *) arg;
++	bss_t *bss, *nextBss;
++	u8 myBssid[IEEE80211_ADDR_LEN];
++
++	wmi_get_current_bssid(nt->nt_wmip, myBssid);
++
++	bss = nt->nt_node_first;
++	while (bss != NULL) {
++		nextBss = bss->ni_list_next;
++		if ((A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) &&
++			(bss->ni_tstamp <= jiffies)) {
++			/*
++			 * free up all but the current bss - if set
++			 */
++			wlan_node_reclaim(nt, bss);
++		}
++		bss = nextBss;
++	}
++
++	A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
++}
++
++void wlan_node_table_cleanup(struct ieee80211_node_table *nt)
++{
++	A_UNTIMEOUT(&nt->nt_inact_timer);
++	wlan_free_allnodes(nt);
++	IEEE80211_NODE_LOCK_DESTROY(nt);
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_recv_beacon.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_recv_beacon.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,169 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ */
++/*
++ * IEEE 802.11 input handling.
++ */
++
++#include "../include/athdefs.h"
++#include "../include/osapi.h"
++#include "../include/wmi.h"
++#include "../include/ieee80211.h"
++#include "../include/wlan_api.h"
++
++#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do {         \
++    if ((_len) < (_minlen)) {                   \
++        return A_EINVAL;                         \
++    }                               \
++} while (0)
++
++#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do {         \
++    if ((__elem) == NULL) {                     \
++        return A_EINVAL;                         \
++    }                               \
++    if ((__elem)[1] > (__maxlen)) {                 \
++        return A_EINVAL;                         \
++    }                               \
++} while (0)
++
++
++/* unaligned little endian access */
++#define LE_READ_2(p)                            \
++    ((u16)                            \
++     ((((u8 *)(p))[0]      ) | (((u8 *)(p))[1] <<  8)))
++
++#define LE_READ_4(p)                            \
++    ((u32)                            \
++     ((((u8 *)(p))[0]      ) | (((u8 *)(p))[1] <<  8) | \
++      (((u8 *)(p))[2] << 16) | (((u8 *)(p))[3] << 24)))
++
++
++static int __inline iswpaoui(const u8 * frm)
++{
++	return frm[1] > 3
++		&& LE_READ_4(frm + 2) == ((WPA_OUI_TYPE << 24) | WPA_OUI);
++}
++
++static int __inline iswmmoui(const u8 * frm)
++{
++	return frm[1] > 3
++		&& LE_READ_4(frm + 2) == ((WMM_OUI_TYPE << 24) | WMM_OUI);
++}
++
++static int __inline iswmmparam(const u8 * frm)
++{
++	return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
++}
++
++static int __inline iswmminfo(const u8 * frm)
++{
++	return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
++}
++
++static int __inline isatherosoui(const u8 * frm)
++{
++	return frm[1] > 3
++		&& LE_READ_4(frm + 2) == ((ATH_OUI_TYPE << 24) | ATH_OUI);
++}
++
++int
++wlan_parse_beacon(u8 * buf, int framelen, struct ieee80211_common_ie *cie)
++{
++	u8 *frm, *efrm;
++
++	frm = buf;
++	efrm = (u8 *) (frm + framelen);
++
++	/*
++	 * beacon/probe response frame format
++	 *  [8] time stamp
++	 *  [2] beacon interval
++	 *  [2] capability information
++	 *  [tlv] ssid
++	 *  [tlv] supported rates
++	 *  [tlv] country information
++	 *  [tlv] parameter set (FH/DS)
++	 *  [tlv] erp information
++	 *  [tlv] extended supported rates
++	 *  [tlv] WMM
++	 *  [tlv] WPA or RSN
++	 *  [tlv] Atheros Advanced Capabilities
++	 */
++	IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
++	A_MEMZERO(cie, sizeof(*cie));
++
++	cie->ie_tstamp = frm;
++	frm += 8;
++	cie->ie_beaconInt = A_LE2CPU16(*(u16 *) frm);
++	frm += 2;
++	cie->ie_capInfo = A_LE2CPU16(*(u16 *) frm);
++	frm += 2;
++	cie->ie_chan = 0;
++
++	while (frm < efrm) {
++		switch (*frm) {
++		case IEEE80211_ELEMID_SSID:
++			cie->ie_ssid = frm;
++			break;
++		case IEEE80211_ELEMID_RATES:
++			cie->ie_rates = frm;
++			break;
++		case IEEE80211_ELEMID_COUNTRY:
++			cie->ie_country = frm;
++			break;
++		case IEEE80211_ELEMID_FHPARMS:
++			break;
++		case IEEE80211_ELEMID_DSPARMS:
++			cie->ie_chan = frm[2];
++			break;
++		case IEEE80211_ELEMID_TIM:
++			cie->ie_tim = frm;
++			break;
++		case IEEE80211_ELEMID_IBSSPARMS:
++			break;
++		case IEEE80211_ELEMID_XRATES:
++			cie->ie_xrates = frm;
++			break;
++		case IEEE80211_ELEMID_ERP:
++			if (frm[1] != 1) {
++				A_PRINTF("Discarding ERP Element - Bad Len\n");
++				return A_EINVAL;
++			}
++			cie->ie_erp = frm[2];
++			break;
++		case IEEE80211_ELEMID_RSN:
++			cie->ie_wpa = frm;
++			break;
++		case IEEE80211_ELEMID_VENDOR:
++			if (iswpaoui(frm)) {
++				cie->ie_wpa = frm;
++			} else if (iswmmoui(frm)) {
++				cie->ie_wmm = frm;
++			} else if (isatherosoui(frm)) {
++				cie->ie_ath = frm;
++			}
++			break;
++		default:
++			break;
++		}
++		frm += frm[1] + 2;
++	}
++	IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
++	IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
++
++	return A_OK;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_utils.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wlan/wlan_utils.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,53 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This module implements frequently used wlan utilies
++ *
++ */
++
++#include "../include/athdefs.h"
++#include "../include/osapi.h"
++
++/*
++ * converts ieee channel number to frequency
++ */
++u16 wlan_ieee2freq(int chan)
++{
++	if (chan == 14) {
++		return 2484;
++	}
++	if (chan < 14) {			/* 0-13 */
++		return (2407 + (chan * 5));
++	}
++	if (chan < 27) {			/* 15-26 */
++		return (2512 + ((chan - 15) * 20));
++	}
++	return (5000 + (chan * 5));
++}
++
++/*
++ * Converts MHz frequency to IEEE channel number.
++ */
++u32 wlan_freq2ieee(u16 freq)
++{
++	if (freq == 2484)
++		return 14;
++	if (freq < 2484)
++		return (freq - 2407) / 5;
++	if (freq < 5000)
++		return 15 + ((freq - 2512) / 20);
++	return (freq - 5000) / 5;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wmi.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/ar6k/wmi.c	2007-12-11 02:30:20.000000000 +0100
+@@ -0,0 +1,2834 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ *  Wireless Network driver for Atheros AR6001
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation;
++ *
++ *  Software distributed under the License is distributed on an "AS
++ *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ *  implied. See the License for the specific language governing
++ *  rights and limitations under the License.
++ *
++ *
++ * This module implements the hardware independent layer of the
++ * Wireless Module Interface (WMI) protocol.
++ *
++ */
++
++#include "ar6k.h"
++#include "include/athdefs.h"
++#include "include/osapi.h"
++#include "include/htc.h"
++#include "include/wmi.h"
++#include "include/ieee80211.h"
++#include "include/ieee80211_node.h"
++#include "include/wlan_api.h"
++#include "include/wmi_api.h"
++#include "include/dset_api.h"
++#include "include/gpio_api.h"
++#include "include/wmi_host.h"
++#include "include/athdrv.h"
++#include "include/ar6k_api.h"
++
++#ifdef CONFIG_AR6K_DEBUG
++int wmi_debug = 2;
++#define WMI_DEBUG_PRINTF(args...)        if (wmi_debug) printk(args);
++#define WMI_DEBUG_PRINTF2(args...)       if (wmi_debug > 1) printk(args);
++#else
++#define WMI_DEBUG_PRINTF(args...)
++#define WMI_DEBUG_PRINTF2(args...)
++#endif
++
++static int wmi_ready_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++
++static int wmi_connect_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_disconnect_event_rx(struct wmi_t *wmip, u8 * datap,
++								   int len);
++static int wmi_tkip_micerr_event_rx(struct wmi_t *wmip, u8 * datap,
++									int len);
++static int wmi_bssInfo_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_opt_frame_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_pstream_timeout_event_rx(struct wmi_t *wmip, u8 * datap,
++										int len);
++static int wmi_sync_point(struct wmi_t *wmip);
++
++static int wmi_create_pstream_reply_rx(struct wmi_t *wmip, u8 * datap,
++									   int len);
++static int wmi_delete_pstream_reply_rx(struct wmi_t *wmip, u8 * datap,
++									   int len);
++static int wmi_bitrate_reply_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_channelList_reply_rx(struct wmi_t *wmip, u8 * datap,
++									int len);
++static int wmi_regDomain_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_txPwr_reply_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_neighborReport_event_rx(struct wmi_t *wmip, u8 * datap,
++									   int len);
++static int wmi_dset_open_req_rx(struct wmi_t *wmip, u8 * datap, int len);
++#if CONFIG_HOST_DSET_SUPPORT
++static int wmi_dset_close_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_dset_data_req_rx(struct wmi_t *wmip, u8 * datap, int len);
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++static int wmi_scanComplete_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_errorEvent_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_statsEvent_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, u8 * datap,
++									 int len);
++static int wmi_reportErrorEvent_rx(struct wmi_t *wmip, u8 * datap,
++								   int len);
++static int wmi_cac_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_roam_tbl_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_roam_data_event_rx(struct wmi_t *wmip, u8 * datap, int len);
++#if CONFIG_HOST_GPIO_SUPPORT
++static int wmi_gpio_intr_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_gpio_data_rx(struct wmi_t *wmip, u8 * datap, int len);
++static int wmi_gpio_ack_rx(struct wmi_t *wmip, u8 * datap, int len);
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++static const s32 wmi_rateTable[] = {
++	1000,
++	2000,
++	5500,
++	11000,
++	6000,
++	9000,
++	12000,
++	18000,
++	24000,
++	36000,
++	48000,
++	54000,
++	0
++};
++
++#define MODE_A_SUPPORT_RATE_START       4
++#define MODE_A_SUPPORT_RATE_STOP        11
++
++#define MODE_GONLY_SUPPORT_RATE_START   MODE_A_SUPPORT_RATE_START
++#define MODE_GONLY_SUPPORT_RATE_STOP    MODE_A_SUPPORT_RATE_STOP
++
++#define MODE_B_SUPPORT_RATE_START       0
++#define MODE_B_SUPPORT_RATE_STOP        3
++
++
++/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
++const u8 up_to_ac[] = {
++	WMM_AC_BE,
++	WMM_AC_BK,
++	WMM_AC_BK,
++	WMM_AC_BE,
++	WMM_AC_VI,
++	WMM_AC_VI,
++	WMM_AC_VO,
++	WMM_AC_VO,
++};
++void *wmi_init(void *devt)
++{
++	struct wmi_t *wmip;
++
++	u8 i;
++	wmip = A_MALLOC(sizeof(struct wmi_t));
++	if (wmip == NULL) {
++		return (NULL);
++	}
++	A_MEMZERO(wmip, sizeof(*wmip));
++
++	wmip->wmi_devt = devt;
++	wlan_node_table_init(wmip, &wmip->wmi_scan_table);
++	for (i = UPLINK_TRAFFIC; i < BIDIR_TRAFFIC; i++) {
++		wmip->wmi_pstreamCmdInProgress[i][WMM_AC_BE] = FALSE;
++		wmip->wmi_pstreamCmdInProgress[i][WMM_AC_BK] = FALSE;
++		wmip->wmi_pstreamCmdInProgress[i][WMM_AC_VI] = FALSE;
++		wmip->wmi_pstreamCmdInProgress[i][WMM_AC_VO] = FALSE;
++	}
++	wmip->wmi_cpstreamCmdInProgress = FALSE;
++	wmi_qos_state_init(wmip);
++	wmip->wmi_powerMode = REC_POWER;
++	wmip->wmi_phyMode = WMI_11G_MODE;
++
++	return (wmip);
++}
++
++void wmi_qos_state_init(struct wmi_t *wmip)
++{
++	u8 i;
++
++	if (wmip == NULL) {
++		return;
++	}
++
++	/* Initialize QoS States */
++	wmip->wmi_numQoSStream = 0;
++
++	for (i = 0; i < WMI_MAX_NUM_PRI_STREAMS; i++) {
++		wmip->wmi_priority[i].inUse = 0;
++		wmip->wmi_priority[i].mbox = WMI_BEST_EFFORT_MBOX;
++	}
++
++	for (i = 0; i < WMM_NUM_AC; i++) {
++		wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][i] = WMI_NOT_MAPPED;
++		wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][i] = WMI_NOT_MAPPED;
++	}
++	wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][WMM_AC_BE] =
++		WMI_BEST_EFFORT_MBOX;
++	wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][WMM_AC_BE] =
++		WMI_BEST_EFFORT_MBOX;
++
++	for (i = 0; i < WMI_MBOX_COUNT; i++) {
++		wmip->wmi_mboxMap[UPLINK_TRAFFIC][i].trafficClass = WMM_AC_BE;
++		wmip->wmi_mboxMap[UPLINK_TRAFFIC][i].priorityNum = WMI_NOT_MAPPED;
++		wmip->wmi_mboxMap[DNLINK_TRAFFIC][i].trafficClass = WMM_AC_BE;
++		wmip->wmi_mboxMap[DNLINK_TRAFFIC][i].priorityNum = WMI_NOT_MAPPED;
++	}
++
++	wmip->wmi_olderPriRxMbox = WMI_HIGH_PRIORITY_MBOX;
++	wmip->wmi_newerPriRxMbox = WMI_LOW_PRIORITY_MBOX;
++	ar6k_set_numdataendpts(wmip->wmi_devt, 1);
++}
++
++void wmi_shutdown(struct wmi_t *wmip)
++{
++	if (wmip != NULL) {
++		wlan_node_table_cleanup(&wmip->wmi_scan_table);
++		A_FREE(wmip);
++	}
++}
++
++/*
++ *  performs DIX to 802.3 encapsulation for transmit packets.
++ *  uses passed in buffer.  Returns buffer or NULL if failed.
++ *  Assumes the entire DIX header is contigous and that there is
++ *  enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
++ */
++int wmi_dix_2_dot3(struct wmi_t *wmip, struct sk_buff *skb)
++{
++	u8 *datap;
++	u16 typeorlen;
++	ATH_MAC_HDR macHdr;
++	ATH_LLC_SNAP_HDR *llcHdr;
++
++	A_ASSERT(skb != NULL);
++
++	if (skb_headroom(skb) <
++		(sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) {
++		return A_NO_MEMORY;
++	}
++
++	datap = skb->data;
++
++	typeorlen = *(u16 *) (datap + ATH_MAC_LEN + ATH_MAC_LEN);
++
++	if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
++		/*
++		 * packet is already in 802.3 format - return success
++		 */
++		WMI_DEBUG_PRINTF("packet already 802.3\n");
++		return (A_OK);
++	}
++
++	/*
++	 * Save mac fields and length to be inserted later
++	 */
++	A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
++	A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
++	macHdr.typeOrLen =
++		A_CPU2BE16(skb->len - sizeof(ATH_MAC_HDR) +
++				   sizeof(ATH_LLC_SNAP_HDR));
++
++	/*
++	 * Make room for LLC+SNAP headers
++	 */
++	skb_push(skb, sizeof(ATH_LLC_SNAP_HDR));
++	datap = skb->data;
++
++	A_MEMCPY(datap, &macHdr, sizeof(ATH_MAC_HDR));
++
++	llcHdr = (ATH_LLC_SNAP_HDR *) (datap + sizeof(ATH_MAC_HDR));
++	llcHdr->dsap = 0xAA;
++	llcHdr->ssap = 0xAA;
++	llcHdr->cntl = 0x03;
++	llcHdr->orgCode[0] = 0x0;
++	llcHdr->orgCode[1] = 0x0;
++	llcHdr->orgCode[2] = 0x0;
++	llcHdr->etherType = typeorlen;
++
++	return (A_OK);
++}
++
++/*
++ * Adds a WMI data header
++ * Assumes there is enough room in the buffer to add header.
++ */
++int wmi_data_hdr_add(struct wmi_t *wmip, struct sk_buff *skb, u8 msgType)
++{
++	WMI_DATA_HDR *dtHdr;
++
++	A_ASSERT(skb != NULL);
++
++	skb_push(skb, sizeof(WMI_DATA_HDR));
++	dtHdr = (WMI_DATA_HDR *) skb->data;
++	dtHdr->info = msgType;
++	dtHdr->rssi = 0;
++
++	return (A_OK);
++}
++
++u8 wmi_implicit_create_pstream(struct wmi_t * wmip, struct sk_buff *skb, u8 dir)
++{
++	u8 *datap;
++	u8 trafficClass, userPriority = 0;
++	ATH_LLC_SNAP_HDR *llcHdr;
++	u16 ipType = IP_ETHERTYPE;
++	WMI_DATA_HDR *dtHdr;
++	WMI_CREATE_PSTREAM_CMD cmd;
++
++	A_ASSERT(skb != NULL);
++	A_ASSERT(dir == DNLINK_TRAFFIC || dir == UPLINK_TRAFFIC);
++	datap = skb->data;
++	llcHdr = (ATH_LLC_SNAP_HDR *) (datap + sizeof(WMI_DATA_HDR) +
++								   sizeof(ATH_MAC_HDR));
++
++	if (llcHdr->etherType == htons(ipType)) {
++		/* Extract the endpoint info from the TOS field in the IP header */
++		userPriority =
++			ar6k_iptos_to_userPriority(((u8 *) llcHdr) +
++										 sizeof(ATH_LLC_SNAP_HDR));
++		trafficClass = convert_userPriority_to_trafficClass(userPriority);
++	} else {
++		trafficClass = WMM_AC_BE;
++	}
++
++
++	dtHdr = (WMI_DATA_HDR *) datap;
++	if (dir == UPLINK_TRAFFIC)
++		dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT;	/* lower
++																						   3-bits
++																						   are
++																						   802.1d
++																						   priority
++																						 */
++
++	/* Implicitly determine whether a create_pstream_cmd is needed for
++	   this trafficClass */
++	if (!
++		((trafficClass == WMM_AC_BE)
++		 || (wmip->wmi_trafficClassMap[dir][trafficClass] !=
++			 WMI_NOT_MAPPED))) {
++		u8 reqMbox;
++		/*
++		 * If the data pkt is tagged with a priority that doesn't have a MBOX created,
++		 * we must first call create_pstream_cmd
++		 * Originally, assume traffic goes to BE MBox,
++		 * until the driver receives the reply from the create_pstream cmd
++		 */
++		wmip->wmi_trafficClassMap[dir][trafficClass] =
++			WMI_BEST_EFFORT_MBOX;
++		if (dir == DNLINK_TRAFFIC) {
++			/* determine which mailbox to use */
++			reqMbox = wmip->wmi_olderPriRxMbox;
++		} else {
++			reqMbox = WMI_BEST_EFFORT_MBOX;
++		}
++
++		A_MEMZERO(&cmd, sizeof(cmd));
++		cmd.trafficClass = trafficClass;
++		cmd.rxQueueNum = reqMbox;
++		cmd.userPriority = userPriority;
++		cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
++
++		if (wmi_create_pstream_cmd(wmip, &cmd) != A_OK) {
++			wmip->wmi_trafficClassMap[dir][trafficClass] = WMI_NOT_MAPPED;
++			trafficClass = WMM_AC_BE;
++		}
++
++	}
++	return trafficClass;
++}
++
++HTC_ENDPOINT_ID wmi_get_endpoint(struct wmi_t * wmip, u8 trafficClass)
++{
++	WMI_DEBUG_PRINTF2("1 pkt of traffic class(%d) to mbox(%d)\n",
++					  trafficClass,
++					  wmip->
++					  wmi_trafficClassMap[UPLINK_TRAFFIC][trafficClass]);
++	return wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][trafficClass];
++}
++
++/*
++ *  performs 802.3 to DIX encapsulation for received packets.
++ *  Assumes the entire 802.3 header is contigous.
++ */
++int wmi_dot3_2_dix(struct wmi_t *wmip, struct sk_buff *skb)
++{
++	u8 *datap;
++	ATH_MAC_HDR macHdr;
++	ATH_LLC_SNAP_HDR *llcHdr;
++
++	A_ASSERT(skb != NULL);
++	datap = skb->data;
++
++	A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
++	llcHdr = (ATH_LLC_SNAP_HDR *) (datap + sizeof(ATH_MAC_HDR));
++	macHdr.typeOrLen = llcHdr->etherType;
++
++	skb_pull(skb, sizeof(ATH_LLC_SNAP_HDR));
++	datap = skb->data;
++
++	A_MEMCPY(datap, &macHdr, sizeof(ATH_MAC_HDR));
++
++	return (A_OK);
++}
++
++/*
++ * Removes a WMI data header
++ */
++int wmi_data_hdr_remove(struct wmi_t *wmip, struct sk_buff *skb)
++{
++	A_ASSERT(skb != NULL);
++	skb_pull(skb, sizeof(WMI_DATA_HDR));
++	return A_OK;
++}
++
++void
++wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func * f, void *arg)
++{
++	wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
++}
++
++/*
++ * WMI Extended Event received from Target.
++ */
++int wmi_control_rx_xtnd(struct wmi_t *wmip, struct sk_buff *skb)
++{
++	WMIX_CMD_HDR *cmd;
++	u16 id;
++	u8 *datap;
++	u32 len;
++	int status = A_OK;
++
++	if (skb->len < sizeof(WMIX_CMD_HDR)) {
++		WMI_DEBUG_PRINTF("wmi extended event rx: bad packet\n");
++		wmip->wmi_stats.cmd_len_err++;
++		dev_kfree_skb(skb);
++		return A_ERROR;
++	}
++
++	cmd = (WMIX_CMD_HDR *) skb->data;
++	id = cmd->commandId;
++
++	skb_pull(skb, sizeof(WMIX_CMD_HDR));
++	datap = skb->data;
++	len = skb->len;
++
++	switch (id) {
++	case (WMIX_DSETOPENREQ_EVENTID):
++		status = wmi_dset_open_req_rx(wmip, datap, len);
++		break;
++#if CONFIG_HOST_DSET_SUPPORT
++	case (WMIX_DSETCLOSE_EVENTID):
++		status = wmi_dset_close_rx(wmip, datap, len);
++		break;
++	case (WMIX_DSETDATAREQ_EVENTID):
++		status = wmi_dset_data_req_rx(wmip, datap, len);
++		break;
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++#if CONFIG_HOST_GPIO_SUPPORT
++	case (WMIX_GPIO_INTR_EVENTID):
++		wmi_gpio_intr_rx(wmip, datap, len);
++		break;
++	case (WMIX_GPIO_DATA_EVENTID):
++		wmi_gpio_data_rx(wmip, datap, len);
++		break;
++	case (WMIX_GPIO_ACK_EVENTID):
++		wmi_gpio_ack_rx(wmip, datap, len);
++		break;
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++	default:
++		WMI_DEBUG_PRINTF
++			("Host received unknown extended reply/event with id 0x%x\n",
++			 id);
++		wmip->wmi_stats.cmd_id_err++;
++		status = A_ERROR;
++		break;
++	}
++
++	return status;
++}
++
++/*
++ * Control Path
++ */
++int wmi_control_rx(struct wmi_t *wmip, struct sk_buff *skb)
++{
++	WMI_CMD_HDR *cmd;
++	u16 id;
++	u8 *datap;
++	u32 len;
++	int status = A_ERROR;
++
++	A_ASSERT(skb != NULL);
++	if (skb->len < sizeof(WMI_CMD_HDR)) {
++		WMI_DEBUG_PRINTF("wmi event rx: bad packet\n");
++		wmip->wmi_stats.cmd_len_err++;
++		goto done;
++	}
++
++	cmd = (WMI_CMD_HDR *) skb->data;
++	id = cmd->commandId;
++
++	skb_pull(skb, sizeof(WMI_CMD_HDR));
++	datap = skb->data;
++	len = skb->len;
++
++	switch (id) {
++	case (WMI_CREATE_PSTREAM_CMDID):
++		status = wmi_create_pstream_reply_rx(wmip, datap, len);
++		break;
++	case (WMI_DELETE_PSTREAM_CMDID):
++		status = wmi_delete_pstream_reply_rx(wmip, datap, len);
++		break;
++	case (WMI_GET_BITRATE_CMDID):
++		status = wmi_bitrate_reply_rx(wmip, datap, len);
++		break;
++	case (WMI_GET_CHANNEL_LIST_CMDID):
++		status = wmi_channelList_reply_rx(wmip, datap, len);
++		break;
++	case (WMI_GET_TX_PWR_CMDID):
++		status = wmi_txPwr_reply_rx(wmip, datap, len);
++		break;
++	case (WMI_READY_EVENTID):
++		status = wmi_ready_event_rx(wmip, datap, len);
++		break;
++	case (WMI_CONNECT_EVENTID):
++		status = wmi_connect_event_rx(wmip, datap, len);
++		break;
++	case (WMI_DISCONNECT_EVENTID):
++		status = wmi_disconnect_event_rx(wmip, datap, len);
++		break;
++	case (WMI_TKIP_MICERR_EVENTID):
++		status = wmi_tkip_micerr_event_rx(wmip, datap, len);
++		break;
++	case (WMI_BSSINFO_EVENTID):
++		status = wmi_bssInfo_event_rx(wmip, datap, len);
++		break;
++	case (WMI_REGDOMAIN_EVENTID):
++		status = wmi_regDomain_event_rx(wmip, datap, len);
++		break;
++	case (WMI_PSTREAM_TIMEOUT_EVENTID):
++		status = wmi_pstream_timeout_event_rx(wmip, datap, len);
++		break;
++	case (WMI_NEIGHBOR_REPORT_EVENTID):
++		status = wmi_neighborReport_event_rx(wmip, datap, len);
++		break;
++	case (WMI_SCAN_COMPLETE_EVENTID):
++		status = wmi_scanComplete_rx(wmip, datap, len);
++		break;
++	case (WMI_CMDERROR_EVENTID):
++		status = wmi_errorEvent_rx(wmip, datap, len);
++		break;
++	case (WMI_REPORT_STATISTICS_EVENTID):
++		status = wmi_statsEvent_rx(wmip, datap, len);
++		break;
++	case (WMI_RSSI_THRESHOLD_EVENTID):
++		status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
++		break;
++	case (WMI_ERROR_REPORT_EVENTID):
++		status = wmi_reportErrorEvent_rx(wmip, datap, len);
++		break;
++	case (WMI_OPT_RX_FRAME_EVENTID):
++		status = wmi_opt_frame_event_rx(wmip, datap, len);
++		break;
++	case (WMI_REPORT_ROAM_TBL_EVENTID):
++		status = wmi_roam_tbl_event_rx(wmip, datap, len);
++		break;
++	case (WMI_EXTENSION_EVENTID):
++		status = wmi_control_rx_xtnd(wmip, skb);
++		break;
++	case (WMI_CAC_EVENTID):
++		status = wmi_cac_event_rx(wmip, datap, len);
++		break;
++	case (WMI_REPORT_ROAM_DATA_EVENTID):
++		status = wmi_roam_data_event_rx(wmip, datap, len);
++		break;
++	default:
++		WMI_DEBUG_PRINTF
++			("Host received unknown reply/event with id 0x%x\n", id);
++		wmip->wmi_stats.cmd_id_err++;
++		break;
++	}
++done:
++	dev_kfree_skb(skb);
++
++	return status;
++}
++
++static int
++wmi_create_pstream_reply_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_CRE_PRIORITY_STREAM_REPLY *reply;
++	int priNum = 0, i;
++	u8 dir;
++
++	if (len < sizeof(WMI_CRE_PRIORITY_STREAM_REPLY)) {
++		WMI_DEBUG_PRINTF("wmi: create pstream reply too short (%d)!!\n",
++						 len);
++		return A_EINVAL;
++	}
++
++	reply = (WMI_CRE_PRIORITY_STREAM_REPLY *) datap;
++	WMI_DEBUG_PRINTF
++		("wmi: create pstream reply: status = %d, tx mbox = %d rx mbox %d\n",
++		 reply->status, reply->txQueueNumber, reply->rxQueueNumber);
++
++	dir = reply->trafficDirection;
++	if (dir == BIDIR_TRAFFIC) {
++		wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][reply->
++													   trafficClass] =
++			FALSE;
++		wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][reply->
++													   trafficClass] =
++			FALSE;
++	} else {
++		wmip->wmi_pstreamCmdInProgress[dir][reply->trafficClass] = FALSE;
++	}
++	wmip->wmi_cpstreamCmdInProgress = FALSE;
++
++	if (reply->status == A_FAILED_CREATE_REMOVE_PSTREAM_FIRST) {
++		/* do nothing */
++		return A_OK;
++	}
++
++	if (reply->status == A_SUCCEEDED) {
++		if (reply->trafficDirection == DNLINK_TRAFFIC ||
++			reply->trafficDirection == BIDIR_TRAFFIC) {
++			wmip->wmi_olderPriRxMbox = wmip->wmi_newerPriRxMbox;
++			wmip->wmi_newerPriRxMbox = reply->rxQueueNumber;
++			wmip->wmi_mboxMap[DNLINK_TRAFFIC][reply->rxQueueNumber].
++				trafficClass = reply->trafficClass;
++			wmip->wmi_mboxMap[DNLINK_TRAFFIC][reply->rxQueueNumber].
++				priorityNum = 0;
++			wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][reply->
++													  trafficClass] =
++				reply->rxQueueNumber;
++		}
++
++		if (reply->trafficDirection == UPLINK_TRAFFIC ||
++			reply->trafficDirection == BIDIR_TRAFFIC) {
++			wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][reply->
++													  trafficClass] =
++				reply->txQueueNumber;
++			/* In case of 3rd pstreams being created, target automatically
++			   deletes the old pstream and accomodates the this one.
++			   Though, the host does not know of this implicit deletion, */
++			if (wmip->wmi_numQoSStream < WMI_MAX_NUM_PRI_STREAMS)
++				wmip->wmi_numQoSStream++;
++			for (i = 0; i < WMI_MAX_NUM_PRI_STREAMS; i++) {
++				if (!wmip->wmi_priority[i].inUse) {
++					priNum = i;
++					wmip->wmi_priority[i].inUse = 1;
++					wmip->wmi_priority[i].mbox = reply->txQueueNumber;
++					break;
++				}
++			}
++			wmip->wmi_mboxMap[UPLINK_TRAFFIC][reply->txQueueNumber].
++				trafficClass = reply->trafficClass;
++			wmip->wmi_mboxMap[UPLINK_TRAFFIC][reply->txQueueNumber].
++				priorityNum = priNum;
++			ar6k_set_numdataendpts(wmip->wmi_devt,
++									 wmip->wmi_numQoSStream + 1);
++		}
++	}
++
++	return reply->status;
++}
++
++static int
++wmi_delete_pstream_reply_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_DEL_PRIORITY_STREAM_REPLY *reply;
++	u8 dir;
++
++	if (len < sizeof(WMI_DEL_PRIORITY_STREAM_REPLY)) {
++		return A_EINVAL;
++	}
++
++	reply = (WMI_DEL_PRIORITY_STREAM_REPLY *) datap;
++	WMI_DEBUG_PRINTF
++		("wmi: delete pstream reply: status = %d, rx mbox = %d tx mbox = %d\n",
++		 reply->status, reply->rxQueueNumber, reply->txQueueNumber);
++
++	dir = reply->trafficDirection;
++	if (dir == BIDIR_TRAFFIC) {
++		wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][reply->
++													   trafficClass] =
++			FALSE;
++		wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][reply->
++													   trafficClass] =
++			FALSE;
++	} else {
++		wmip->wmi_pstreamCmdInProgress[dir][reply->trafficClass] = FALSE;
++	}
++
++	if (reply->status == A_OK) {
++		/* update internal states for Rx Path */
++		if (reply->trafficDirection == DNLINK_TRAFFIC
++			|| reply->trafficDirection == BIDIR_TRAFFIC) {
++			u8 qNum = reply->rxQueueNumber;
++			u8 class =
++				wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].trafficClass;
++			wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][class] =
++				WMI_NOT_MAPPED;
++			wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].priorityNum =
++				WMI_NOT_MAPPED;
++			wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].trafficClass =
++				WMM_AC_BE;
++			if (wmip->wmi_newerPriRxMbox == qNum) {
++				wmip->wmi_newerPriRxMbox = wmip->wmi_olderPriRxMbox;
++				wmip->wmi_olderPriRxMbox = qNum;
++			}
++		}
++	}
++
++	return reply->status;
++}
++
++static int wmi_ready_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_READY_EVENT *ev = (WMI_READY_EVENT *) datap;
++
++	if (len < sizeof(WMI_READY_EVENT)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi: ready event\n");
++	wmip->wmi_ready = TRUE;
++	ar6k_ready_event(wmip->wmi_devt, ev->macaddr, ev->phyCapability);
++
++	return A_OK;
++}
++
++static int wmi_connect_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_CONNECT_EVENT *ev;
++
++	if (len < sizeof(WMI_CONNECT_EVENT)) {
++		return A_EINVAL;
++	}
++	ev = (WMI_CONNECT_EVENT *) datap;
++#ifdef CONFIG_AR6K_DEBUG
++	WMI_DEBUG_PRINTF("wmi: connected event at freq %d ", ev->channel);
++	WMI_DEBUG_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
++					 ev->bssid[0], ev->bssid[1], ev->bssid[2],
++					 ev->bssid[3], ev->bssid[4], ev->bssid[5]);
++#endif							/* DEBUG */
++
++	A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
++
++	ar6k_connect_event(wmip->wmi_devt, ev->channel, ev->bssid,
++						 ev->listenInterval, ev->beaconIeLen,
++						 ev->assocReqLen, ev->assocRespLen, ev->assocInfo);
++
++	return A_OK;
++}
++
++static int wmi_regDomain_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_REG_DOMAIN_EVENT *ev;
++
++	if (len < sizeof(*ev)) {
++		return A_EINVAL;
++	}
++	ev = (WMI_REG_DOMAIN_EVENT *) datap;
++
++	ar6k_regDomain_event(wmip->wmi_devt, ev->regDomain);
++
++	return A_OK;
++}
++
++static int
++wmi_neighborReport_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_NEIGHBOR_REPORT_EVENT *ev;
++	int numAps;
++
++	if (len < sizeof(*ev)) {
++		return A_EINVAL;
++	}
++	ev = (WMI_NEIGHBOR_REPORT_EVENT *) datap;
++	numAps = ev->numberOfAps;
++
++	if (len < (sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
++		return A_EINVAL;
++	}
++
++	ar6k_neighborReport_event(wmip->wmi_devt, numAps, ev->neighbor);
++
++	return A_OK;
++}
++
++static int wmi_disconnect_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_DISCONNECT_EVENT *ev;
++
++	if (len < sizeof(WMI_DISCONNECT_EVENT)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi: disconnected event\n");
++
++	ev = (WMI_DISCONNECT_EVENT *) datap;
++
++	A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
++
++	ar6k_disconnect_event(wmip->wmi_devt, ev->disconnectReason,
++							ev->bssid, ev->assocRespLen, ev->assocInfo);
++
++	return A_OK;
++}
++
++static int
++wmi_tkip_micerr_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TKIP_MICERR_EVENT *ev;
++
++	if (len < sizeof(*ev)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi: tkip micerr event\n");
++
++	ev = (WMI_TKIP_MICERR_EVENT *) datap;
++	ar6k_tkip_micerr_event(wmip->wmi_devt, ev->keyid, ev->ismcast);
++
++	return A_OK;
++}
++
++static int wmi_bssInfo_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	bss_t *bss;
++	WMI_BSS_INFO_HDR *bih;
++	u8 *buf;
++
++	if (len <= sizeof(WMI_BSS_INFO_HDR)) {
++		return A_EINVAL;
++	}
++
++	bih = (WMI_BSS_INFO_HDR *) datap;
++	buf = datap + sizeof(WMI_BSS_INFO_HDR);
++	len -= sizeof(WMI_BSS_INFO_HDR);
++
++	WMI_DEBUG_PRINTF2("wmi: bssInfo event %2.2x:%2.2x\n",
++					  bih->bssid[4], bih->bssid[5]);
++
++	bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
++	if (bss != NULL) {
++		/*
++		 * Free up the node.  Not the most efficient process given
++		 * we are about to allocate a new node but it is simple and should be
++		 * adequate.
++		 */
++		wlan_node_reclaim(&wmip->wmi_scan_table, bss);
++	}
++
++	bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
++	if (bss == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	bss->ni_rssi = bih->rssi;
++	A_ASSERT(bss->ni_buf != NULL);
++	A_MEMCPY(bss->ni_buf, buf, len);
++
++	if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
++		wlan_node_free(bss);
++		return A_EINVAL;
++	}
++
++	/*
++	 * Update the frequency in ie_chan, overwriting of channel number
++	 * which is done in wlan_parse_beacon
++	 */
++	bss->ni_cie.ie_chan = bih->channel;
++	wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
++
++	return A_OK;
++}
++
++static int wmi_opt_frame_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	bss_t *bss;
++	WMI_OPT_RX_INFO_HDR *bih;
++	u8 *buf;
++
++	if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
++		return A_EINVAL;
++	}
++
++	bih = (WMI_OPT_RX_INFO_HDR *) datap;
++	buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
++	len -= sizeof(WMI_OPT_RX_INFO_HDR);
++
++	WMI_DEBUG_PRINTF2("wmi: opt frame event %2.2x:%2.2x\n",
++					  bih->bssid[4], bih->bssid[5]);
++
++	bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
++	if (bss != NULL) {
++		/*
++		 * Free up the node.  Not the most efficient process given
++		 * we are about to allocate a new node but it is simple and should be
++		 * adequate.
++		 */
++		wlan_node_reclaim(&wmip->wmi_scan_table, bss);
++	}
++
++	bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
++	if (bss == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	bss->ni_rssi = bih->rssi;
++	bss->ni_cie.ie_chan = bih->channel;
++	A_ASSERT(bss->ni_buf != NULL);
++	A_MEMCPY(bss->ni_buf, buf, len);
++	wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
++
++	return A_OK;
++}
++
++static int
++wmi_pstream_timeout_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_PSTREAM_TIMEOUT_EVENT *ev;
++
++	if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
++		return A_EINVAL;
++	}
++
++	WMI_DEBUG_PRINTF("wmi: pstream timeout event\n");
++
++	ev = (WMI_PSTREAM_TIMEOUT_EVENT *) datap;
++
++	wmi_delete_pstream_cmd(wmip, ev->txQueueNumber, ev->rxQueueNumber,
++						   ev->trafficDirection);
++
++	return A_OK;
++}
++
++static int wmi_bitrate_reply_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_BIT_RATE_CMD *reply;
++	s32 rate;
++
++	if (len < sizeof(WMI_BIT_RATE_CMD)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_BIT_RATE_CMD *) datap;
++	WMI_DEBUG_PRINTF("wmi: get bit rate reply %d\n", reply->rateIndex);
++
++	if (reply->rateIndex == RATE_AUTO) {
++		rate = RATE_AUTO;
++	} else {
++		rate = wmi_rateTable[reply->rateIndex];
++	}
++
++	ar6k_bitrate_rx(wmip->wmi_devt, rate);
++
++	return A_OK;
++}
++
++static int
++wmi_channelList_reply_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_CHANNEL_LIST_REPLY *reply;
++
++	if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_CHANNEL_LIST_REPLY *) datap;
++	WMI_DEBUG_PRINTF("wmi: get channel list reply\n");
++
++	ar6k_channelList_rx(wmip->wmi_devt, reply->numChannels,
++						  reply->channelList);
++
++	return A_OK;
++}
++
++static int wmi_txPwr_reply_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TX_PWR_REPLY *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_TX_PWR_REPLY *) datap;
++	WMI_DEBUG_PRINTF("wmi: get tx pwr reply\n");
++
++	ar6k_txPwr_rx(wmip->wmi_devt, reply->dbM);
++
++	return A_OK;
++}
++
++static int wmi_dset_open_req_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMIX_DSETOPENREQ_EVENT *dsetopenreq;
++
++	if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi_dset_open_req_rx: DataSet Open Request event\n");
++
++	dsetopenreq = (WMIX_DSETOPENREQ_EVENT *) datap;
++	WMI_DEBUG_PRINTF("wmi_dset_open_req_rx: dset_id=0x%x\n",
++					 dsetopenreq->dset_id);
++	ar6k_dset_open_req(wmip->wmi_devt, dsetopenreq->dset_id,
++						 dsetopenreq->targ_dset_handle,
++						 dsetopenreq->targ_reply_fn,
++						 dsetopenreq->targ_reply_arg);
++
++	return A_OK;
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++static int wmi_dset_close_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMIX_DSETCLOSE_EVENT *dsetclose;
++
++	if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi: DataSet Close event\n");
++
++	dsetclose = (WMIX_DSETCLOSE_EVENT *) datap;
++	ar6k_dset_close(wmip->wmi_devt, dsetclose->access_cookie);
++
++	return A_OK;
++}
++
++static int wmi_dset_data_req_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMIX_DSETDATAREQ_EVENT *dsetdatareq;
++
++	if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
++		return A_EINVAL;
++	}
++	WMI_DEBUG_PRINTF("wmi: DataSet Data Request event\n");
++
++	dsetdatareq = (WMIX_DSETDATAREQ_EVENT *) datap;
++	ar6k_dset_data_req(wmip->wmi_devt,
++						 dsetdatareq->access_cookie,
++						 dsetdatareq->offset,
++						 dsetdatareq->length,
++						 dsetdatareq->targ_buf,
++						 dsetdatareq->targ_reply_fn,
++						 dsetdatareq->targ_reply_arg);
++
++	return A_OK;
++}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++static int wmi_scanComplete_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	ar6k_scanComplete_event(wmip->wmi_devt);
++
++	return A_OK;
++}
++
++/*
++ * Target is reporting a programming error.  This is for
++ * developer aid only.  Target only checks a few common violations
++ * and it is responsibility of host to do all error checking.
++ * Behavior of target after wmi error event is undefined.
++ * A reset is recommended.
++ */
++static int wmi_errorEvent_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_CMD_ERROR_EVENT *ev;
++
++	ev = (WMI_CMD_ERROR_EVENT *) datap;
++	A_PRINTF("Programming Error: cmd=%d ", ev->commandId);
++	switch (ev->errorCode) {
++	case (INVALID_PARAM):
++		A_PRINTF("Illegal Parameter\n");
++		break;
++	case (ILLEGAL_STATE):
++		A_PRINTF("Illegal State\n");
++		break;
++	case (INTERNAL_ERROR):
++		A_PRINTF("Internal Error\n");
++		break;
++	}
++
++	return A_OK;
++}
++
++
++static int wmi_statsEvent_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TARGET_STATS *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_TARGET_STATS *) datap;
++	WMI_DEBUG_PRINTF("wmi: target stats event\n");
++
++	ar6k_targetStats_event(wmip->wmi_devt, reply);
++
++	return A_OK;
++}
++
++
++
++static int
++wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_RSSI_THRESHOLD_EVENT *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_RSSI_THRESHOLD_EVENT *) datap;
++	WMI_DEBUG_PRINTF("wmi: rssi threshold event\n");
++
++	ar6k_rssiThreshold_event(wmip->wmi_devt, reply->range);
++
++	return A_OK;
++}
++
++
++static int wmi_reportErrorEvent_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TARGET_ERROR_REPORT_EVENT *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_TARGET_ERROR_REPORT_EVENT *) datap;
++	WMI_DEBUG_PRINTF("wmi: report error event\n");
++
++	ar6k_reportError_event(wmip->wmi_devt, reply->errorVal);
++
++	return A_OK;
++}
++
++static int wmi_cac_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_CAC_EVENT *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_CAC_EVENT *) datap;
++	WMI_DEBUG_PRINTF("wmi: report CAC event\n");
++
++	ar6k_cac_event(wmip->wmi_devt, reply->ac,
++					 reply->cac_indication, reply->statusCode,
++					 reply->tspecSuggestion);
++
++	return A_OK;
++}
++
++static int wmi_roam_tbl_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TARGET_ROAM_TBL *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_TARGET_ROAM_TBL *) datap;
++	WMI_DEBUG_PRINTF("wmi: target ROAM TABLE event\n");
++
++	ar6k_roam_tbl_event(wmip->wmi_devt, reply);
++
++	return A_OK;
++}
++
++static int wmi_roam_data_event_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_TARGET_ROAM_DATA *reply;
++
++	if (len < sizeof(*reply)) {
++		return A_EINVAL;
++	}
++	reply = (WMI_TARGET_ROAM_DATA *) datap;
++	WMI_DEBUG_PRINTF("wmi: target ROAM DATA event\n");
++
++	ar6k_roam_data_event(wmip->wmi_devt, reply);
++
++	return A_OK;
++}
++
++#if CONFIG_HOST_GPIO_SUPPORT
++static int wmi_gpio_intr_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *) datap;
++
++	WMI_DEBUG_PRINTF
++		("wmi GPIO interrupt received intrmask=0x%x input=0x%x.\n",
++		 gpio_intr->intr_mask, gpio_intr->input_values);
++
++	ar6k_gpio_intr_rx(gpio_intr->intr_mask, gpio_intr->input_values);
++
++	return A_OK;
++}
++
++static int wmi_gpio_data_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *) datap;
++
++	WMI_DEBUG_PRINTF("wmi GPIO data received reg=%d value=0x%x.\n",
++					 gpio_data->reg_id, gpio_data->value);
++
++	ar6k_gpio_data_rx(gpio_data->reg_id, gpio_data->value);
++
++	return A_OK;
++}
++
++static int wmi_gpio_ack_rx(struct wmi_t *wmip, u8 * datap, int len)
++{
++	WMI_DEBUG_PRINTF("wmi GPIO ACK received.\n");
++
++	ar6k_gpio_ack_rx();
++
++	return A_OK;
++}
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++/*
++ * Called to send a wmi command. Command specific data is already built
++ * on skb and current skb->data points to it.
++ */
++int
++wmi_cmd_send(struct wmi_t *wmip, struct sk_buff *skb, WMI_COMMAND_ID cmdId,
++			 WMI_SYNC_FLAG syncflag)
++{
++#define IS_LONG_CMD(cmdId) (cmdId == WMI_OPT_TX_FRAME_CMDID)
++	WMI_CMD_HDR *cHdr;
++	u8 mbox = WMI_CONTROL_MBOX;
++
++	A_ASSERT(skb != NULL);
++
++	if (syncflag >= END_WMIFLAG) {
++		return A_EINVAL;
++	}
++
++	if ((syncflag == SYNC_BEFORE_WMIFLAG)
++		|| (syncflag == SYNC_BOTH_WMIFLAG)) {
++		/*
++		 * We want to make sure all data currently queued is transmitted before
++		 * the cmd execution.  Establish a new sync point.
++		 */
++		wmi_sync_point(wmip);
++	}
++
++	skb_push(skb, sizeof(WMI_CMD_HDR));
++	cHdr = (WMI_CMD_HDR *) skb->data;
++	cHdr->commandId = cmdId;
++
++	/*
++	 * Send cmd, some via control pipe, others via data pipe
++	 */
++	if (IS_LONG_CMD(cmdId)) {
++		wmi_data_hdr_add(wmip, skb, CNTL_MSGTYPE);
++		mbox = WMI_BEST_EFFORT_MBOX;
++	}
++	ar6k_control_tx(wmip->wmi_devt, skb, mbox);
++
++	if ((syncflag == SYNC_AFTER_WMIFLAG)
++		|| (syncflag == SYNC_BOTH_WMIFLAG)) {
++		/*
++		 * We want to make sure all new data queued waits for the command to
++		 * execute. Establish a new sync point.
++		 */
++		wmi_sync_point(wmip);
++	}
++
++	return (A_OK);
++#undef IS_LONG_CMD
++}
++
++int
++wmi_cmd_send_xtnd(struct wmi_t *wmip, struct sk_buff *skb, WMI_COMMAND_ID cmdId,
++				  WMI_SYNC_FLAG syncflag)
++{
++	WMIX_CMD_HDR *cHdr;
++
++	skb_push(skb, sizeof(WMIX_CMD_HDR));
++	cHdr = (WMIX_CMD_HDR *) skb->data;
++	cHdr->commandId = cmdId;
++
++	return wmi_cmd_send(wmip, skb, WMI_EXTENSION_CMDID, syncflag);
++}
++
++int
++wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
++				DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
++				CRYPTO_TYPE pairwiseCrypto, u8 pairwiseCryptoLen,
++				CRYPTO_TYPE groupCrypto, u8 groupCryptoLen,
++				int ssidLength, u8 * ssid, u8 * bssid, u16 channel)
++{
++	struct sk_buff *skb;
++	WMI_CONNECT_CMD *cc;
++
++	if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
++		return A_EINVAL;
++	}
++	if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(WMI_CONNECT_CMD));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(WMI_CONNECT_CMD));
++
++	cc = (WMI_CONNECT_CMD *) (skb->data);
++	A_MEMZERO(cc, sizeof(*cc));
++
++	A_MEMCPY(cc->ssid, ssid, ssidLength);
++	cc->ssidLength = ssidLength;
++	cc->networkType = netType;
++	cc->dot11AuthMode = dot11AuthMode;
++	cc->authMode = authMode;
++	cc->pairwiseCryptoType = pairwiseCrypto;
++	cc->pairwiseCryptoLen = pairwiseCryptoLen;
++	cc->groupCryptoType = groupCrypto;
++	cc->groupCryptoLen = groupCryptoLen;
++	cc->channel = channel;
++
++	if (bssid != NULL) {
++		A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
++	}
++
++	return (wmi_cmd_send(wmip, skb, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_reconnect_cmd(struct wmi_t *wmip, u8 * bssid, u16 channel)
++{
++	struct sk_buff *skb;
++	WMI_RECONNECT_CMD *cc;
++
++	skb = ar6k_alloc_skb(sizeof(WMI_RECONNECT_CMD));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(WMI_RECONNECT_CMD));
++
++	cc = (WMI_RECONNECT_CMD *) (skb->data);
++	A_MEMZERO(cc, sizeof(*cc));
++
++	cc->channel = channel;
++
++	if (bssid != NULL) {
++		A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_disconnect_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++	int status;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	status = (wmi_cmd_send(wmip, skb, WMI_DISCONNECT_CMDID,
++						   SYNC_BEFORE_WMIFLAG));
++	wmi_qos_state_init(wmip);
++	return status;
++}
++
++int wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType)
++{
++	struct sk_buff *skb;
++	WMI_START_SCAN_CMD *sc;
++
++	if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*sc));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*sc));
++
++	sc = (WMI_START_SCAN_CMD *) (skb->data);
++	sc->scanType = scanType;
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_scanparams_cmd(struct wmi_t *wmip, u16 fg_start_sec,
++				   u16 fg_end_sec, u16 bg_sec,
++				   u16 act_chdw_msec, u16 pas_chdw_msec, u8 shScanRatio)
++{
++	struct sk_buff *skb;
++	WMI_SCAN_PARAMS_CMD *sc;
++
++	skb = ar6k_alloc_skb(sizeof(*sc));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*sc));
++
++	sc = (WMI_SCAN_PARAMS_CMD *) (skb->data);
++	A_MEMZERO(sc, sizeof(*sc));
++	sc->fg_start_period = fg_start_sec;
++	sc->fg_end_period = fg_end_sec;
++	sc->bg_period = bg_sec;
++	sc->act_chdwell_time = act_chdw_msec;
++	sc->pas_chdwell_time = pas_chdw_msec;
++	sc->shortScanRatio = shScanRatio;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_SCAN_PARAMS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_bssfilter_cmd(struct wmi_t *wmip, u8 filter)
++{
++	struct sk_buff *skb;
++	WMI_BSS_FILTER_CMD *cmd;
++
++	if (filter >= LAST_BSS_FILTER) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_BSS_FILTER_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->bssFilter = filter;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_BSS_FILTER_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_probedSsid_cmd(struct wmi_t *wmip, u8 index, u8 flag,
++				   u8 ssidLength, u8 * ssid)
++{
++	struct sk_buff *skb;
++	WMI_PROBED_SSID_CMD *cmd;
++
++	if (index > MAX_PROBED_SSID_INDEX) {
++		return A_EINVAL;
++	}
++	if (ssidLength > sizeof(cmd->ssid)) {
++		return A_EINVAL;
++	}
++	if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
++		return A_EINVAL;
++	}
++	if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_PROBED_SSID_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->entryIndex = index;
++	cmd->flag = flag;
++	cmd->ssidLength = ssidLength;
++	A_MEMCPY(cmd->ssid, ssid, ssidLength);
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_PROBED_SSID_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_listeninterval_cmd(struct wmi_t *wmip, u16 listenInterval,
++					   u16 listenBeacons)
++{
++	struct sk_buff *skb;
++	WMI_LISTEN_INT_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_LISTEN_INT_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->listenInterval = listenInterval;
++	cmd->numBeacons = listenBeacons;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_LISTEN_INT_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_bmisstime_cmd(struct wmi_t *wmip, u16 bmissTime, u16 bmissBeacons)
++{
++	struct sk_buff *skb;
++	WMI_BMISS_TIME_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_BMISS_TIME_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->bmissTime = bmissTime;
++	cmd->numBeacons = bmissBeacons;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_BMISS_TIME_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_associnfo_cmd(struct wmi_t *wmip, u8 ieType, u8 ieLen, u8 * ieInfo)
++{
++	struct sk_buff *skb;
++	WMI_SET_ASSOC_INFO_CMD *cmd;
++	u16 cmdLen;
++
++	cmdLen = sizeof(*cmd) + ieLen - 1;
++	skb = ar6k_alloc_skb(cmdLen);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, cmdLen);
++
++	cmd = (WMI_SET_ASSOC_INFO_CMD *) (skb->data);
++	A_MEMZERO(cmd, cmdLen);
++	cmd->ieType = ieType;
++	cmd->bufferSize = ieLen;
++	A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_ASSOC_INFO_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_powermode_cmd(struct wmi_t *wmip, u8 powerMode)
++{
++	struct sk_buff *skb;
++	WMI_POWER_MODE_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_POWER_MODE_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->powerMode = powerMode;
++	wmip->wmi_powerMode = powerMode;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_POWER_MODE_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_ibsspmcaps_cmd(struct wmi_t *wmip, u8 pmEnable, u8 ttl,
++				   u16 atim_windows, u16 timeout_value)
++{
++	struct sk_buff *skb;
++	WMI_IBSS_PM_CAPS_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_IBSS_PM_CAPS_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->power_saving = pmEnable;
++	cmd->ttl = ttl;
++	cmd->atim_windows = atim_windows;
++	cmd->timeout_value = timeout_value;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_IBSS_PM_CAPS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_pmparams_cmd(struct wmi_t *wmip, u16 idlePeriod,
++				 u16 psPollNum, u16 dtimPolicy)
++{
++	struct sk_buff *skb;
++	WMI_POWER_PARAMS_CMD *pm;
++
++	skb = ar6k_alloc_skb(sizeof(*pm));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*pm));
++
++	pm = (WMI_POWER_PARAMS_CMD *) (skb->data);
++	A_MEMZERO(pm, sizeof(*pm));
++	pm->idle_period = idlePeriod;
++	pm->pspoll_number = psPollNum;
++	pm->dtim_policy = dtimPolicy;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_POWER_PARAMS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_disctimeout_cmd(struct wmi_t *wmip, u8 timeout)
++{
++	struct sk_buff *skb;
++	WMI_DISC_TIMEOUT_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_DISC_TIMEOUT_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->disconnectTimeout = timeout;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_DISC_TIMEOUT_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_addKey_cmd(struct wmi_t *wmip, u8 keyIndex, CRYPTO_TYPE keyType,
++			   u8 keyUsage, u8 keyLength, u8 * keyRSC,
++			   u8 * keyMaterial, WMI_SYNC_FLAG sync_flag)
++{
++	struct sk_buff *skb;
++	WMI_ADD_CIPHER_KEY_CMD *cmd;
++
++	if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
++		(keyMaterial == NULL)) {
++		return A_EINVAL;
++	}
++
++	if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_ADD_CIPHER_KEY_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->keyIndex = keyIndex;
++	cmd->keyType = keyType;
++	cmd->keyUsage = keyUsage;
++	cmd->keyLength = keyLength;
++	A_MEMCPY(cmd->key, keyMaterial, keyLength);
++	if (NULL != keyRSC) {
++		A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
++}
++
++int wmi_add_krk_cmd(struct wmi_t *wmip, u8 * krk)
++{
++	struct sk_buff *skb;
++	WMI_ADD_KRK_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_ADD_KRK_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
++
++	return (wmi_cmd_send(wmip, skb, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_delete_krk_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);
++
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_DELETE_KRK_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_deleteKey_cmd(struct wmi_t *wmip, u8 keyIndex)
++{
++	struct sk_buff *skb;
++	WMI_DELETE_CIPHER_KEY_CMD *cmd;
++
++	if (keyIndex > WMI_MAX_KEY_INDEX) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_DELETE_CIPHER_KEY_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->keyIndex = keyIndex;
++
++	return (wmi_cmd_send(wmip, skb, WMI_DELETE_CIPHER_KEY_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_setPmkid_cmd(struct wmi_t *wmip, u8 * bssid, u8 * pmkId, u8 set)
++{
++	struct sk_buff *skb;
++	WMI_SET_PMKID_CMD *cmd;
++
++	if (bssid == NULL) {
++		return A_EINVAL;
++	}
++
++	if ((set == TRUE) && (pmkId == NULL)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_PMKID_CMD *) (skb->data);
++	A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++	if (set == TRUE) {
++		A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
++		cmd->enable = PMKID_ENABLE;
++	} else {
++		A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
++		cmd->enable = PMKID_DISABLE;
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, u8 en)
++{
++	struct sk_buff *skb;
++	WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *) (skb->data);
++	cmd->cm_en = (en == TRUE) ? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_dataSync_send(struct wmi_t *wmip, struct sk_buff *skb, int endPoint)
++{
++	WMI_DATA_HDR *dtHdr;
++
++	A_ASSERT(endPoint != WMI_CONTROL_MBOX);
++	A_ASSERT(skb != NULL);
++
++	skb_push(skb, sizeof(WMI_DATA_HDR));
++	dtHdr = (WMI_DATA_HDR *) skb->data;
++	dtHdr->info =
++		(SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) <<
++		WMI_DATA_HDR_MSG_TYPE_SHIFT;
++
++	WMI_DEBUG_PRINTF("wmi sync pkt sent on mbox %d\n", endPoint);
++
++	return (ar6k_control_tx(wmip->wmi_devt, skb, endPoint));
++}
++
++static int wmi_sync_point(struct wmi_t *wmip)
++{
++	struct sk_buff *cmd_skb, *be_skb, *pri_skb[WMI_MAX_NUM_PRI_STREAMS];
++	u8 i;
++	int status;
++
++	WMI_DEBUG_PRINTF("wmi_sync_point\n");
++	/*
++	 * We allocate all network buffers needed so we will be able to
++	 * send all required frames.
++	 */
++	cmd_skb = ar6k_alloc_skb(0);	/* no payload */
++	if (cmd_skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	be_skb = ar6k_alloc_skb(0);	/* no payload */
++	if (be_skb == NULL) {
++		dev_kfree_skb(cmd_skb);
++		return A_NO_MEMORY;
++	}
++
++	for (i = 0; i < wmip->wmi_numQoSStream; i++) {
++		pri_skb[i] = ar6k_alloc_skb(0);	/* no payload */
++		if (pri_skb[i] == NULL) {
++			u8 j;
++			dev_kfree_skb(be_skb);
++			dev_kfree_skb(cmd_skb);
++			/* free previously allocated bufs */
++			for (j = 0; j < i; j++) {
++				dev_kfree_skb(pri_skb[j]);
++			}
++			return A_NO_MEMORY;
++		}
++	}
++
++	/*
++	 * Send sync cmd followed by sync data messages on all endpoints being
++	 * used
++	 */
++	status = wmi_cmd_send(wmip, cmd_skb, WMI_SYNCHRONIZE_CMDID,
++						  NO_SYNC_WMIFLAG);
++
++	if (status == A_OK) {
++		status = wmi_dataSync_send(wmip, be_skb, WMI_BEST_EFFORT_MBOX);
++	}
++
++	if (status == A_OK) {
++		u8 priIndex = 0;
++		for (i = 0; i < wmip->wmi_numQoSStream; i++) {
++			while (priIndex < WMI_MAX_NUM_PRI_STREAMS &&
++				   (!wmip->wmi_priority[priIndex].inUse)) {
++				priIndex++;
++			}
++			if (priIndex >= WMI_MAX_NUM_PRI_STREAMS) {
++				break;
++			}
++			status =
++				wmi_dataSync_send(wmip, pri_skb[i],
++								  wmip->wmi_priority[priIndex].mbox);
++			if (status != A_OK) {
++				break;
++			}
++			priIndex++;
++		}
++	}
++
++	return (status);
++}
++
++int
++wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD * params)
++{
++	struct sk_buff *skb;
++	WMI_CREATE_PSTREAM_CMD *cmd;
++
++	/* Validate all the parameters. */
++	if (!((params->userPriority < 8) &&
++		  (params->trafficDirection == BIDIR_TRAFFIC ||
++		   params->trafficDirection == UPLINK_TRAFFIC ||
++		   params->trafficDirection == DNLINK_TRAFFIC) &&
++		  (params->userPriority <= 0x7) &&
++		  (convert_userPriority_to_trafficClass(params->userPriority) ==
++		   params->trafficClass) && (params->trafficClass != WMM_AC_BE)
++		  && (params->trafficType == TRAFFIC_TYPE_APERIODIC
++			  || params->trafficType == TRAFFIC_TYPE_PERIODIC)
++		  && (params->voicePSCapability == DISABLE_FOR_THIS_AC
++			  || params->voicePSCapability == ENABLE_FOR_THIS_AC
++			  || params->voicePSCapability == ENABLE_FOR_ALL_AC)
++		  && (params->tsid < 15))) {
++		return A_EINVAL;
++	}
++
++
++	if (params->trafficDirection == BIDIR_TRAFFIC) {
++		if (wmip->
++			wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][params->trafficClass]
++			|| wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][params->
++															  trafficClass]
++			|| wmip->wmi_cpstreamCmdInProgress) {
++			WMI_DEBUG_PRINTF("create %d too busy !\n",
++							 params->trafficClass);
++			return A_EBUSY;
++		}
++		wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][params->
++													   trafficClass] =
++			TRUE;
++		wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][params->
++													   trafficClass] =
++			TRUE;
++	} else {
++		if (wmip->
++			wmi_pstreamCmdInProgress[params->trafficDirection][params->
++															   trafficClass]
++			|| wmip->wmi_cpstreamCmdInProgress) {
++			WMI_DEBUG_PRINTF("create %d too busy !\n",
++							 params->trafficClass);
++			return A_EBUSY;
++		}
++		wmip->wmi_pstreamCmdInProgress[params->trafficDirection][params->
++																 trafficClass]
++			= TRUE;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	wmip->wmi_cpstreamCmdInProgress = TRUE;
++	skb_put(skb, sizeof(*cmd));
++
++	WMI_DEBUG_PRINTF("Sending create_pstream_cmd: ac=%d, rxQ=%d, dir=%d\n",
++					 params->trafficClass, params->rxQueueNum,
++					 params->trafficDirection);
++	cmd = (WMI_CREATE_PSTREAM_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	A_MEMCPY(cmd, params, sizeof(*cmd));
++
++	if (params->rxQueueNum == 0xFF) {
++		if (wmip->
++			wmi_trafficClassMap[DNLINK_TRAFFIC][params->trafficClass] !=
++			WMI_NOT_MAPPED)
++			cmd->rxQueueNum =
++				wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][params->
++														  trafficClass];
++		else
++			cmd->rxQueueNum = wmip->wmi_olderPriRxMbox;
++	} else {
++		cmd->rxQueueNum = params->rxQueueNum;
++	}
++
++	/* mike: should be SYNC_BEFORE_WMIFLAG */
++	return (wmi_cmd_send(wmip, skb, WMI_CREATE_PSTREAM_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_delete_pstream_cmd(struct wmi_t *wmip, u8 txQueueNumber,
++					   u8 rxQueueNumber, u8 dir)
++{
++	struct sk_buff *skb;
++	WMI_DELETE_PSTREAM_CMD *cmd;
++	int status;
++	u8 class;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	if (dir == BIDIR_TRAFFIC) {
++		class =
++			wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].trafficClass;
++		if (wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][class]
++			|| wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][class]) {
++			return A_EBUSY;
++		}
++		wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][class] = TRUE;
++		wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][class] = TRUE;
++	} else {
++		if (dir == UPLINK_TRAFFIC) {
++			class =
++				wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].
++				trafficClass;
++		} else {
++			class =
++				wmip->wmi_mboxMap[DNLINK_TRAFFIC][rxQueueNumber].
++				trafficClass;
++		}
++		if (wmip->wmi_pstreamCmdInProgress[dir][class]) {
++			return A_EBUSY;
++		}
++		wmip->wmi_pstreamCmdInProgress[dir][class] = TRUE;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_DELETE_PSTREAM_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->txQueueNumber = txQueueNumber;
++	cmd->rxQueueNumber = rxQueueNumber;
++	cmd->trafficDirection = dir;
++	cmd->trafficClass = class;
++	WMI_DEBUG_PRINTF
++		("Sending delete_pstream_cmd: txQ=%d, rxQ=%d, dir=%d\n",
++		 txQueueNumber, rxQueueNumber, dir);
++	status =
++		(wmi_cmd_send
++		 (wmip, skb, WMI_DELETE_PSTREAM_CMDID,
++		  (dir == UPLINK_TRAFFIC
++		   || dir ==
++		   BIDIR_TRAFFIC) ? SYNC_BEFORE_WMIFLAG : NO_SYNC_WMIFLAG));
++
++	if (class != WMM_AC_BE) {
++		/* Update internal states */
++		if (dir == UPLINK_TRAFFIC || dir == BIDIR_TRAFFIC) {
++			wmip->wmi_numQoSStream--;
++			ar6k_set_numdataendpts(wmip->wmi_devt,
++									 wmip->wmi_numQoSStream + 1);
++			wmip->wmi_priority[wmip->
++							   wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].
++							   priorityNum].inUse = 0;
++			wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][class] =
++				WMI_NOT_MAPPED;
++			wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].priorityNum =
++				WMI_NOT_MAPPED;
++			wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].trafficClass =
++				WMM_AC_BE;
++		}
++	}
++
++	return status;
++}
++
++
++/*
++ * used to set the bit rate.  rate is in Kbps.  If rate == -1
++ * then auto selection is used.
++ */
++int wmi_set_bitrate_cmd(struct wmi_t *wmip, s32 rate)
++{
++	struct sk_buff *skb;
++	WMI_BIT_RATE_CMD *cmd;
++	int index;
++
++	index = wmi_validate_bitrate(wmip, rate);
++	if (index == A_EINVAL) {
++		return A_EINVAL;
++	}
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_BIT_RATE_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++
++	cmd->rateIndex = index;
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_get_bitrate_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_GET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
++}
++
++s8 wmi_validate_bitrate(struct wmi_t *wmip, s32 rate)
++{
++	int i;
++	if (rate != -1) {
++		for (i = 0;; i++) {
++			if (wmi_rateTable[i] == 0) {
++				return A_EINVAL;
++			}
++			if (wmi_rateTable[i] == rate) {
++				break;
++			}
++		}
++	} else {
++		i = -1;
++	}
++
++	if (wmip->wmi_phyMode == WMI_11A_MODE &&
++		(i < MODE_A_SUPPORT_RATE_START || i > MODE_A_SUPPORT_RATE_STOP)) {
++		return A_EINVAL;
++	} else if (wmip->wmi_phyMode == WMI_11B_MODE &&
++			   (i < MODE_B_SUPPORT_RATE_START
++				|| i > MODE_B_SUPPORT_RATE_STOP)) {
++		return A_EINVAL;
++	} else if (wmip->wmi_phyMode == WMI_11GONLY_MODE &&
++			   (i < MODE_GONLY_SUPPORT_RATE_START
++				|| i > MODE_GONLY_SUPPORT_RATE_STOP)) {
++		return A_EINVAL;
++	}
++
++	return i;
++}
++
++int wmi_get_channelList_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send(wmip, skb, WMI_GET_CHANNEL_LIST_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++/*
++ * used to generate a wmi sey channel Parameters cmd.
++ * mode should always be specified and corresponds to the phy mode of the
++ * wlan.
++ * numChan should alway sbe specified. If zero indicates that all available
++ * channels should be used.
++ * channelList is an array of channel frequencies (in Mhz) which the radio
++ * should limit its operation to.  It should be NULL if numChan == 0.  Size of
++ * array should correspond to numChan entries.
++ */
++int
++wmi_set_channelParams_cmd(struct wmi_t *wmip, WMI_PHY_MODE mode,
++						  int numChan, u16 * channelList)
++{
++	struct sk_buff *skb;
++	WMI_CHANNEL_PARAMS_CMD *cmd;
++	int size;
++
++	size = sizeof(*cmd);
++
++	if (numChan) {
++		if (numChan > WMI_MAX_CHANNELS) {
++			return A_EINVAL;
++		}
++		size += sizeof(u16) * (numChan - 1);
++	}
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_CHANNEL_PARAMS_CMD *) (skb->data);
++	A_MEMZERO(cmd, size);
++
++	wmip->wmi_phyMode = mode;
++	cmd->phyMode = mode;
++	cmd->numChannels = numChan;
++	A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(u16));
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_CHANNEL_PARAMS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_set_link_threshold_params(struct wmi_t *wmip,
++							  u8 highThreshold_upperVal,
++							  u8 highThreshold_lowerVal,
++							  u8 lowThreshold_upperVal,
++							  u8 lowThreshold_lowerVal, u32 pollTime)
++{
++	struct sk_buff *skb;
++	int size;
++	WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
++
++	/* These values are in ascending order */
++	if (highThreshold_upperVal <= highThreshold_lowerVal ||
++		lowThreshold_upperVal <= lowThreshold_lowerVal ||
++		highThreshold_lowerVal <= lowThreshold_upperVal)
++		return A_EINVAL;
++
++	size = sizeof(*cmd);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *) (skb->data);
++	A_MEMZERO(cmd, size);
++
++	cmd->highThreshold_upperVal = highThreshold_upperVal;
++	cmd->highThreshold_lowerVal = highThreshold_lowerVal;
++	cmd->lowThreshold_upperVal = lowThreshold_upperVal;
++	cmd->lowThreshold_lowerVal = lowThreshold_lowerVal;
++	cmd->pollTime = pollTime;
++
++	return (wmi_cmd_send(wmip, skb, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++
++int wmi_set_error_report_bitmask(struct wmi_t *wmip, u32 mask)
++{
++	struct sk_buff *skb;
++	int size;
++	WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
++
++	size = sizeof(*cmd);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *) (skb->data);
++	A_MEMZERO(cmd, size);
++
++	cmd->bitmask = mask;
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
++			 NO_SYNC_WMIFLAG));
++}
++
++
++int wmi_get_stats_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send(wmip, skb, WMI_GET_STATISTICS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_addBadAp_cmd(struct wmi_t *wmip, u8 apIndex, u8 * bssid)
++{
++	struct sk_buff *skb;
++	WMI_ADD_BAD_AP_CMD *cmd;
++
++	if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_ADD_BAD_AP_CMD *) (skb->data);
++	cmd->badApIndex = apIndex;
++	A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_ADD_BAD_AP_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_deleteBadAp_cmd(struct wmi_t *wmip, u8 apIndex)
++{
++	struct sk_buff *skb;
++	WMI_DELETE_BAD_AP_CMD *cmd;
++
++	if (apIndex > WMI_MAX_BAD_AP_INDEX) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_DELETE_BAD_AP_CMD *) (skb->data);
++	cmd->badApIndex = apIndex;
++
++	return (wmi_cmd_send(wmip, skb, WMI_DELETE_BAD_AP_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_set_txPwr_cmd(struct wmi_t *wmip, u8 dbM)
++{
++	struct sk_buff *skb;
++	WMI_SET_TX_PWR_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_TX_PWR_CMD *) (skb->data);
++	cmd->dbM = dbM;
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
++}
++
++int wmi_get_txPwr_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send
++			(wmip, skb, WMI_GET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
++}
++
++s8 wmi_get_mapped_qos_queue(struct wmi_t *wmip, u8 dir, u8 trafficClass)
++{
++	if ((dir == UPLINK_TRAFFIC || dir == DNLINK_TRAFFIC) &&
++		(trafficClass <= WMM_AC_VO)) {
++		return wmip->wmi_trafficClassMap[dir][trafficClass];
++	} else {
++		return WMI_NOT_MAPPED;
++	}
++}
++
++int wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	skb = ar6k_alloc_skb(0);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send(wmip, skb, WMI_GET_ROAM_TBL_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_get_roam_data_cmd(struct wmi_t *wmip, u8 roamDataType)
++{
++	struct sk_buff *skb;
++	u32 size = sizeof(u8);
++	WMI_TARGET_ROAM_DATA *cmd;
++
++	skb = ar6k_alloc_skb(size);	/* no payload */
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_TARGET_ROAM_DATA *) (skb->data);
++	cmd->roamDataType = roamDataType;
++
++	return (wmi_cmd_send(wmip, skb, WMI_GET_ROAM_DATA_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD * p,
++					  u8 size)
++{
++	struct sk_buff *skb;
++	WMI_SET_ROAM_CTRL_CMD *cmd;
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_SET_ROAM_CTRL_CMD *) (skb->data);
++	A_MEMZERO(cmd, size);
++
++	A_MEMCPY(cmd, p, size);
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_ROAM_CTRL_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
++							 WMI_POWERSAVE_TIMERS_CMD * pCmd, u8 size)
++{
++	struct sk_buff *skb;
++	WMI_POWERSAVE_TIMERS_CMD *cmd;
++
++	/* These timers can't be zero */
++	if (!pCmd->psPollTimeout || !pCmd->eospTimeout)
++		return A_EINVAL;
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, size);
++
++	cmd = (WMI_POWERSAVE_TIMERS_CMD *) (skb->data);
++	A_MEMZERO(cmd, size);
++
++	A_MEMCPY(cmd, pCmd, size);
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_POWERSAVE_TIMERS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_dset_open_reply(struct wmi_t *wmip,
++					u32 status,
++					u32 access_cookie,
++					u32 dset_size,
++					u32 dset_version,
++					u32 targ_handle, u32 targ_reply_fn, u32 targ_reply_arg)
++{
++	struct sk_buff *skb;
++	WMIX_DSETOPEN_REPLY_CMD *open_reply;
++
++	WMI_DEBUG_PRINTF("wmi_dset_open_reply: wmip=0x%x\n", (int) wmip);
++
++	skb = ar6k_alloc_skb(sizeof(*open_reply));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*open_reply));
++	open_reply = (WMIX_DSETOPEN_REPLY_CMD *) (skb->data);
++
++	open_reply->status = status;
++	open_reply->targ_dset_handle = targ_handle;
++	open_reply->targ_reply_fn = targ_reply_fn;
++	open_reply->targ_reply_arg = targ_reply_arg;
++	open_reply->access_cookie = access_cookie;
++	open_reply->size = dset_size;
++	open_reply->version = dset_version;
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_DSETOPEN_REPLY_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++int
++wmi_dset_data_reply(struct wmi_t *wmip,
++					u32 status,
++					u8 * user_buf,
++					u32 length,
++					u32 targ_buf, u32 targ_reply_fn, u32 targ_reply_arg)
++{
++	struct sk_buff *skb;
++	WMIX_DSETDATA_REPLY_CMD *data_reply;
++	int size;
++
++	size = sizeof(*data_reply) + length;
++
++	WMI_DEBUG_PRINTF("wmi_dset_data_reply: length=%d status=%d\n", length,
++					 status);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	skb_put(skb, size);
++	data_reply = (WMIX_DSETDATA_REPLY_CMD *) (skb->data);
++
++	data_reply->status = status;
++	data_reply->targ_buf = targ_buf;
++	data_reply->targ_reply_fn = targ_reply_fn;
++	data_reply->targ_reply_arg = targ_reply_arg;
++	data_reply->length = length;
++
++	if (status == A_OK) {
++		if (copy_from_user(data_reply->buf, user_buf, length)) {
++			return A_ERROR;
++		}
++	}
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_DSETDATA_REPLY_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++#endif							/* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++/* Send a command to Target to change GPIO output pins. */
++int
++wmi_gpio_output_set(struct wmi_t *wmip,
++					u32 set_mask,
++					u32 clear_mask, u32 enable_mask, u32 disable_mask)
++{
++	struct sk_buff *skb;
++	WMIX_GPIO_OUTPUT_SET_CMD *output_set;
++	int size;
++
++	size = sizeof(*output_set);
++
++	WMI_DEBUG_PRINTF
++		("wmi_gpio_output_set: set=0x%x clear=0x%x enb=0x%x dis=0x%x\n",
++		 set_mask, clear_mask, enable_mask, disable_mask);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	skb_put(skb, size);
++	output_set = (WMIX_GPIO_OUTPUT_SET_CMD *) (skb->data);
++
++	output_set->set_mask = set_mask;
++	output_set->clear_mask = clear_mask;
++	output_set->enable_mask = enable_mask;
++	output_set->disable_mask = disable_mask;
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_GPIO_OUTPUT_SET_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target requesting state of the GPIO input pins */
++int wmi_gpio_input_get(struct wmi_t *wmip)
++{
++	struct sk_buff *skb;
++
++	WMI_DEBUG_PRINTF("wmi_gpio_input_get\n");
++
++	skb = ar6k_alloc_skb(0);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_GPIO_INPUT_GET_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target that changes the value of a GPIO register. */
++int wmi_gpio_register_set(struct wmi_t *wmip, u32 gpioreg_id, u32 value)
++{
++	struct sk_buff *skb;
++	WMIX_GPIO_REGISTER_SET_CMD *register_set;
++	int size;
++
++	size = sizeof(*register_set);
++
++	WMI_DEBUG_PRINTF("wmi_gpio_register_set: reg=%d value=0x%x\n",
++					 gpioreg_id, value);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	skb_put(skb, size);
++	register_set =
++		(WMIX_GPIO_REGISTER_SET_CMD *) (skb->data);
++
++	register_set->gpioreg_id = gpioreg_id;
++	register_set->value = value;
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_GPIO_REGISTER_SET_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target to fetch the value of a GPIO register. */
++int wmi_gpio_register_get(struct wmi_t *wmip, u32 gpioreg_id)
++{
++	struct sk_buff *skb;
++	WMIX_GPIO_REGISTER_GET_CMD *register_get;
++	int size;
++
++	size = sizeof(*register_get);
++
++	WMI_DEBUG_PRINTF("wmi_gpio_register_get: reg=%d\n", gpioreg_id);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	skb_put(skb, size);
++	register_get =
++		(WMIX_GPIO_REGISTER_GET_CMD *) (skb->data);
++
++	register_get->gpioreg_id = gpioreg_id;
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_GPIO_REGISTER_GET_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target acknowledging some GPIO interrupts. */
++int wmi_gpio_intr_ack(struct wmi_t *wmip, u32 ack_mask)
++{
++	struct sk_buff *skb;
++	WMIX_GPIO_INTR_ACK_CMD *intr_ack;
++	int size;
++
++	size = sizeof(*intr_ack);
++
++	WMI_DEBUG_PRINTF("wmi_gpio_intr_ack: ack_mask=0x%x\n", ack_mask);
++
++	skb = ar6k_alloc_skb(size);
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++	skb_put(skb, size);
++	intr_ack = (WMIX_GPIO_INTR_ACK_CMD *) (skb->data);
++
++	intr_ack->ack_mask = ack_mask;
++
++	return (wmi_cmd_send_xtnd(wmip, skb, WMIX_GPIO_INTR_ACK_CMDID,
++							  NO_SYNC_WMIFLAG));
++}
++#endif							/* CONFIG_HOST_GPIO_SUPPORT */
++
++int
++wmi_set_access_params_cmd(struct wmi_t *wmip, u16 txop, u8 eCWmin,
++						  u8 eCWmax, u8 aifsn)
++{
++	struct sk_buff *skb;
++	WMI_SET_ACCESS_PARAMS_CMD *cmd;
++
++	if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
++		(aifsn > WMI_MAX_AIFSN_ACPARAM)) {
++		return A_EINVAL;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_ACCESS_PARAMS_CMD *) (skb->data);
++	cmd->txop = txop;
++	cmd->eCWmin = eCWmin;
++	cmd->eCWmax = eCWmax;
++	cmd->aifsn = aifsn;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_ACCESS_PARAMS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int
++wmi_set_retry_limits_cmd(struct wmi_t *wmip, u8 frameType,
++						 u8 trafficClass, u8 maxRetries)
++{
++	struct sk_buff *skb;
++	WMI_SET_RETRY_LIMITS_CMD *cmd;
++
++	if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE)
++		&& (frameType != DATA_FRAMETYPE)) {
++		return A_EINVAL;
++	}
++
++	if (maxRetries > WMI_MAX_RETRIES) {
++		return A_EINVAL;
++	}
++
++	if (frameType != DATA_FRAMETYPE) {
++		trafficClass = 0;
++	}
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_RETRY_LIMITS_CMD *) (skb->data);
++	cmd->frameType = frameType;
++	cmd->trafficClass = trafficClass;
++	cmd->maxRetries = maxRetries;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_RETRY_LIMITS_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++void wmi_get_current_bssid(struct wmi_t *wmip, u8 * bssid)
++{
++	if (bssid != NULL) {
++		A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
++	}
++}
++
++int wmi_set_opt_mode_cmd(struct wmi_t *wmip, u8 optMode)
++{
++	struct sk_buff *skb;
++	WMI_SET_OPT_MODE_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_OPT_MODE_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->optMode = optMode;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_OPT_MODE_CMDID,
++						 SYNC_BOTH_WMIFLAG));
++}
++
++int
++wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
++					 u8 frmType,
++					 u8 * dstMacAddr,
++					 u8 * bssid, u16 optIEDataLen, u8 * optIEData)
++{
++	struct sk_buff *skb;
++	WMI_OPT_TX_FRAME_CMD *cmd;
++	skb = ar6k_alloc_skb(optIEDataLen + sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, (optIEDataLen + sizeof(*cmd)));
++
++	cmd = (WMI_OPT_TX_FRAME_CMD *) (skb->data);
++	A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)));
++
++	cmd->frmType = frmType;
++	cmd->optIEDataLen = optIEDataLen;
++	cmd->optIEData = (u8 *) ((int) cmd + sizeof(*cmd));
++	A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++	A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
++	A_MEMCPY(cmd->optIEData, optIEData, optIEDataLen);
++
++	return (wmi_cmd_send(wmip, skb, WMI_OPT_TX_FRAME_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++int wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, u16 intvl)
++{
++	struct sk_buff *skb;
++	WMI_BEACON_INT_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_BEACON_INT_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->beaconInterval = intvl;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_BEACON_INT_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++
++int wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, u16 voicePktSize)
++{
++	struct sk_buff *skb;
++	WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->voicePktSize = voicePktSize;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_VOICE_PKT_SIZE_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++
++int wmi_set_max_sp_len_cmd(struct wmi_t *wmip, u8 maxSPLen)
++{
++	struct sk_buff *skb;
++	WMI_SET_MAX_SP_LEN_CMD *cmd;
++
++	/* maxSPLen is a two-bit value. If user trys to set anything other
++	   than this, then its invalid */
++	if (maxSPLen & ~0x03)
++		return A_EINVAL;
++
++	skb = ar6k_alloc_skb(sizeof(*cmd));
++	if (skb == NULL) {
++		return A_NO_MEMORY;
++	}
++
++	skb_put(skb, sizeof(*cmd));
++
++	cmd = (WMI_SET_MAX_SP_LEN_CMD *) (skb->data);
++	A_MEMZERO(cmd, sizeof(*cmd));
++	cmd->maxSPLen = maxSPLen;
++
++	return (wmi_cmd_send(wmip, skb, WMI_SET_MAX_SP_LEN_CMDID,
++						 NO_SYNC_WMIFLAG));
++}
++
++u8 convert_userPriority_to_trafficClass(u8 userPriority)
++{
++	return (up_to_ac[userPriority & 0x7]);
++}
++
++u8 wmi_get_power_mode_cmd(struct wmi_t * wmip)
++{
++	return wmip->wmi_powerMode;
++}
++
++int
++wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD * pCmd, u8 tspecCompliance)
++{
++	int ret = A_OK;
++
++#define TSPEC_SUSPENSION_INTERVAL_CCXV4_DEF (~0)
++#define TSPEC_SERVICE_START_TIME_CCXV4_DEF  0
++#define TSPEC_MAX_BURST_SIZE_CCXV4_DEF      0
++#define TSPEC_DELAY_BOUND_CCXV4_DEF         0
++#define TSPEC_MEDIUM_TIME_CCXV4_DEF         0
++#define TSPEC_SBA_CCXV4_DEF                 0x2000	/* factor is 1 */
++
++	/* Verify TSPEC params for CCX v4 compliance */
++	if (tspecCompliance == CCX_V4_COMPLIANCE) {
++		if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_CCXV4_DEF) ||
++			(pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_CCXV4_DEF)
++			|| (pCmd->minDataRate != pCmd->meanDataRate)
++			|| (pCmd->minDataRate != pCmd->peakDataRate)
++			|| (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_CCXV4_DEF)
++			|| (pCmd->delayBound != TSPEC_DELAY_BOUND_CCXV4_DEF)
++			|| (pCmd->sba != TSPEC_SBA_CCXV4_DEF)
++			|| (pCmd->mediumTime != TSPEC_MEDIUM_TIME_CCXV4_DEF)) {
++
++			WMI_DEBUG_PRINTF("%s: Invalid TSPEC params\n", __FUNCTION__);
++			A_PRINTF("%s: Invalid TSPEC params\n", __FUNCTION__);
++			ret = A_EINVAL;
++		}
++	}
++
++	return ret;
++}
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/Kconfig
+===================================================================
+--- linux-2.6.22-atheros-ng.orig/drivers/net/wireless/Kconfig	2007-12-11 02:31:12.000000000 +0100
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/Kconfig	2007-12-11 02:31:17.000000000 +0100
+@@ -549,5 +549,6 @@
+ source "drivers/net/wireless/hostap/Kconfig"
+ source "drivers/net/wireless/bcm43xx/Kconfig"
+ source "drivers/net/wireless/zd1211rw/Kconfig"
++source "drivers/net/wireless/ar6k/Kconfig"
+ 
+ endmenu
+Index: linux-2.6.22-atheros-ng/drivers/net/wireless/Makefile
+===================================================================
+--- linux-2.6.22-atheros-ng.orig/drivers/net/wireless/Makefile	2007-12-11 02:31:44.000000000 +0100
++++ linux-2.6.22-atheros-ng/drivers/net/wireless/Makefile	2007-12-11 02:31:58.000000000 +0100
+@@ -37,6 +37,7 @@
+ obj-$(CONFIG_HOSTAP)		+= hostap/
+ obj-$(CONFIG_BCM43XX)		+= bcm43xx/
+ obj-$(CONFIG_ZD1211RW)		+= zd1211rw/
++obj-$(CONFIG_AR6K)		+= ar6k/
+ 
+ # 16-bit wireless PCMCIA client drivers
+ obj-$(CONFIG_PCMCIA_RAYCS)	+= ray_cs.o





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