r2229 - trunk/src/target/u-boot/patches

[laforge at sita.openmoko.org]

Author: laforge
Date: 2007-06-12 18:21:24 +0200 (Tue, 12 Jun 2007)
New Revision: 2229

Modified:
   trunk/src/target/u-boot/patches/uboot-s3c2440.patch
Log:
use correct PLL dividers for 12MHz (hxd8 has 16.9344, gta02 12 DUH!)


Modified: trunk/src/target/u-boot/patches/uboot-s3c2440.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2440.patch	2007-06-12 16:09:05 UTC (rev 2228)
+++ trunk/src/target/u-boot/patches/uboot-s3c2440.patch	2007-06-12 16:21:24 UTC (rev 2229)
@@ -483,7 +483,7 @@
 ===================================================================
 --- u-boot.orig/include/common.h
 +++ u-boot/include/common.h
-@@ -452,7 +452,7 @@
+@@ -454,7 +454,7 @@
  ulong	get_OPB_freq (void);
  ulong	get_PCI_freq (void);
  #endif
@@ -752,7 +752,7 @@
  
  
  /*
-@@ -142,14 +146,27 @@
+@@ -142,14 +146,32 @@
  # define pWTCON		0x15300000
  # define INTMSK		0x14400008	/* Interupt-Controller base addresses */
  # define CLKDIVN	0x14800014	/* clock divisor register */
@@ -772,8 +772,13 @@
 +# define CLKDIVN_val	3 /* FCLK:HCLK:PCLK = 1:2:4 */
 +#elif defined(CONFIG_S3C2440)
 +# define INTSUBMSK_val	0xffff
++#if (CONFIG_SYS_CLK_FREQ == 16934400)
 +# define MPLLCON_val	((0x61 << 12) + (0x1 << 4) + 0x2)	/* 296.35 MHz */
-+# define UPLLCON_val	((0x3c << 12) + (0x4 << 4) + 0x2)
++# define UPLLCON_val	((0x3c << 12) + (0x4 << 4) + 0x2)	/*  47.98 MHz */
++#else if (CONFIG_SYS_CLK_FREQ == 12000000)
++# define MPLLCON_val	((0x44 << 12) + (0x1 << 4) + 0x1)	/* 304.00 MHz */
++# define UPLLCON_val	((0x38 << 12) + (0x2 << 4) + 0x2)	/*  48.00 MHz */
++#endif
 +# define CLKDIVN_val	7 /* FCLK:HCLK:PCLK = 1:3:6 */
 +# define CAMDIVN	0x4C000018
 +#endif
@@ -782,7 +787,7 @@
  	ldr     r0, =pWTCON
  	mov     r1, #0x0
  	str     r1, [r0]
-@@ -160,24 +177,34 @@
+@@ -160,24 +182,34 @@
  	mov	r1, #0xffffffff
  	ldr	r0, =INTMSK
  	str	r1, [r0]
@@ -824,7 +829,7 @@
  	str	r1, [r0]
  
  	/* Page 7-19, seven nops between UPLL and MPLL */
-@@ -189,12 +216,12 @@
+@@ -189,12 +221,12 @@
  	nop
  	nop
  
@@ -839,7 +844,7 @@
  	str	r1, [r0]
  
  #if 1
-@@ -222,7 +249,7 @@
+@@ -222,7 +254,7 @@
  	str	r1, [r0, #0x28]
  #endif
  
@@ -848,7 +853,7 @@
  
  #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  #ifndef CONFIG_LL_INIT_NAND_ONLY
-@@ -274,7 +301,7 @@
+@@ -279,7 +311,7 @@
  #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
  	bl	cpu_init_crit
  #endif
@@ -857,7 +862,7 @@
  	/* ensure some refresh has happened */
  	ldr	r1, =0xfffff
  1:	subs	r1, r1, #1
-@@ -285,11 +312,12 @@
+@@ -290,11 +322,12 @@
  	ldr	r0, [ r1 ]
  	tst	r0, #0x02		/* is this resume from power down */
  	ldrne	pc, [r1, #4]		/* gstatus3 */
@@ -871,7 +876,7 @@
  	@ reset NAND
  	mov	r1, #S3C2410_NAND_BASE
  	ldr	r2, =0xf842		@ initial value enable tacls=3,rph0=6,rph1=0
-@@ -309,6 +337,17 @@
+@@ -314,6 +347,17 @@
  	ldr	r2, [r1, #oNFCONF]
  	orr	r2, r2, #0x800		@ disable chip
  	str	r2, [r1, #oNFCONF]
@@ -889,7 +894,7 @@
  
  #if 0
  	@ get ready to call C functions (for nand_read())
-@@ -377,7 +416,7 @@
+@@ -382,7 +426,7 @@
  #endif /* CONFIG_S3C2410_NAND_BOOT */
  done_relocate: