r1542 - trunk/src/target/u-boot/patches
laforge at sita.openmoko.org
laforge at sita.openmoko.org
Wed Mar 28 18:58:51 CEST 2007
Author: laforge
Date: 2007-03-28 18:58:51 +0200 (Wed, 28 Mar 2007)
New Revision: 1542
Added:
trunk/src/target/u-boot/patches/uboot-hxd8.patch
trunk/src/target/u-boot/patches/uboot-smdk2440.patch
Modified:
trunk/src/target/u-boot/patches/series
Log:
add SMDK2440 and HXD8 support (untested)
Modified: trunk/src/target/u-boot/patches/series
===================================================================
--- trunk/src/target/u-boot/patches/series 2007-03-28 16:58:18 UTC (rev 1541)
+++ trunk/src/target/u-boot/patches/series 2007-03-28 16:58:51 UTC (rev 1542)
@@ -67,3 +67,5 @@
mmc-fixes.patch
usbdcore-multiple_configs.patch
neo1973-chargefast.patch
+uboot-smdk2440.patch
+uboot-hxd8.patch
Added: trunk/src/target/u-boot/patches/uboot-hxd8.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-hxd8.patch 2007-03-28 16:58:18 UTC (rev 1541)
+++ trunk/src/target/u-boot/patches/uboot-hxd8.patch 2007-03-28 16:58:51 UTC (rev 1542)
@@ -0,0 +1,871 @@
+Patch to add HXD8 support
+
+Index: u-boot/Makefile
+===================================================================
+--- u-boot.orig/Makefile 2007-03-28 18:41:51.000000000 +0200
++++ u-boot/Makefile 2007-03-28 18:41:52.000000000 +0200
+@@ -1988,6 +1988,9 @@
+ qt2410_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0
+
++hxd8_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm920t hxd8 NULL s3c24x0
++
+ scb9328_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
+
+Index: u-boot/board/hxd8/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/Makefile 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,51 @@
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := hxd8.o udc.o
++SOBJS := lowlevel_init.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot/board/hxd8/hxd8.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/hxd8.c 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,152 @@
++/*
++ * (C) Copyright 2007 by OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger at sysgo.de>
++ *
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <s3c2440.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define FCLK_SPEED 1
++
++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
++#define M_MDIV 0xC3
++#define M_PDIV 0x4
++#define M_SDIV 0x1
++#elif FCLK_SPEED==1 /* Fout = 399.65MHz */
++#define M_MDIV 0x6e
++#define M_PDIV 0x3
++#define M_SDIV 0x1
++#endif
++
++#define USB_CLOCK 1
++
++#if USB_CLOCK==0
++#define U_M_MDIV 0xA1
++#define U_M_PDIV 0x3
++#define U_M_SDIV 0x1
++#elif USB_CLOCK==1
++#define U_M_MDIV 0x3c
++#define U_M_PDIV 0x4
++#define U_M_SDIV 0x2
++#endif
++
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ /* to reduce PLL lock time, adjust the LOCKTIME register */
++ clk_power->LOCKTIME = 0xFFFFFF;
++
++ /* configure MPLL */
++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (4000);
++
++ /* configure UPLL */
++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (8000);
++
++ /* set up the I/O ports */
++ gpio->GPACON = 0x005E0FFE;
++ gpio->GPBCON = 0x00045542;
++ gpio->GPBUP = 0x000007FF;
++ gpio->GPCCON = 0xAAAA55A9;
++ gpio->GPCUP = 0x0000FFFF;
++ gpio->GPDCON = 0xAAAAAAAA;
++ gpio->GPDUP = 0x0000FFFF;
++ gpio->GPECON = 0xAAAAAAAA;
++ gpio->GPEUP = 0x0000FFFF;
++ gpio->GPFCON = 0x0000AAA9;
++ gpio->GPFUP = 0x000000FF;
++ gpio->GPGCON = 0x027D0016;
++ gpio->GPGUP = 0x0000FFFF;
++ gpio->GPHCON = 0x0014AAAA;
++ gpio->GPHUP = 0x000007FF;
++ gpio->GPJCON = 0x00000000;
++
++#if 0
++ /* USB Device Part */
++ /*GPGCON is reset for USB Device */
++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
++
++ gpio->GPGDAT |= ( 1 << 12);
++ gpio->GPGDAT &= ~( 1 << 12);
++ udelay(20000);
++ gpio->GPGDAT |= ( 1 << 12);
++#endif
++
++ /* arch number of SMDK2440-Board */
++ gd->bd->bi_arch_number = MACH_TYPE_HXD8;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0x30000100;
++
++ icache_enable();
++ dcache_enable();
++
++ return 0;
++}
++
++int board_late_init(void)
++{
++ /* Initialize the Power Management Unit with a safe register set */
++ pcf50606_init();
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++u_int32_t get_board_rev(void)
++{
++ return 0x00000110;
++}
+Index: u-boot/board/hxd8/lowlevel_init.S
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/lowlevel_init.S 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,166 @@
++/*
++ * Memory Setup stuff - taken from blob memsetup.S
++ *
++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
++ * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
++ *
++ * Modified for the FIC HXD8 by Harald Welte <laforge at openmoko.org>
++ * (C) Copyright 2007 by OpenMoko, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++
++
++/* some parameters for the board */
++
++/*
++ *
++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
++ *
++ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar at sec.samsung.com>
++ *
++ */
++
++#define BWSCON 0x48000000
++
++/* BWSCON */
++#define DW8 (0x0)
++#define DW16 (0x1)
++#define DW32 (0x2)
++#define WAIT (0x1<<2)
++#define UBLB (0x1<<3)
++
++#define B1_BWSCON (DW32)
++#define B2_BWSCON (DW16)
++#define B3_BWSCON (DW16 + WAIT + UBLB)
++#define B4_BWSCON (DW16)
++#define B5_BWSCON (DW16)
++#define B6_BWSCON (DW32)
++#define B7_BWSCON (DW32)
++
++/* BANK0CON */
++#define B0_Tacs 0x0 /* 0clk */
++#define B0_Tcos 0x0 /* 0clk */
++#define B0_Tacc 0x7 /* 14clk */
++#define B0_Tcoh 0x0 /* 0clk */
++#define B0_Tah 0x0 /* 0clk */
++#define B0_Tacp 0x0
++#define B0_PMC 0x0 /* normal */
++
++/* BANK1CON */
++#define B1_Tacs 0x0 /* 0clk */
++#define B1_Tcos 0x0 /* 0clk */
++#define B1_Tacc 0x7 /* 14clk */
++#define B1_Tcoh 0x0 /* 0clk */
++#define B1_Tah 0x0 /* 0clk */
++#define B1_Tacp 0x0
++#define B1_PMC 0x0
++
++#define B2_Tacs 0x0
++#define B2_Tcos 0x0
++#define B2_Tacc 0x7
++#define B2_Tcoh 0x0
++#define B2_Tah 0x0
++#define B2_Tacp 0x0
++#define B2_PMC 0x0
++
++#define B3_Tacs 0x0 /* 0clk */
++#define B3_Tcos 0x3 /* 4clk */
++#define B3_Tacc 0x7 /* 14clk */
++#define B3_Tcoh 0x1 /* 1clk */
++#define B3_Tah 0x0 /* 0clk */
++#define B3_Tacp 0x3 /* 6clk */
++#define B3_PMC 0x0 /* normal */
++
++#define B4_Tacs 0x0 /* 0clk */
++#define B4_Tcos 0x0 /* 0clk */
++#define B4_Tacc 0x7 /* 14clk */
++#define B4_Tcoh 0x0 /* 0clk */
++#define B4_Tah 0x0 /* 0clk */
++#define B4_Tacp 0x0
++#define B4_PMC 0x0 /* normal */
++
++#define B5_Tacs 0x0 /* 0clk */
++#define B5_Tcos 0x0 /* 0clk */
++#define B5_Tacc 0x7 /* 14clk */
++#define B5_Tcoh 0x0 /* 0clk */
++#define B5_Tah 0x0 /* 0clk */
++#define B5_Tacp 0x0
++#define B5_PMC 0x0 /* normal */
++
++#define B6_MT 0x3 /* SDRAM */
++#define B6_Trcd 0x1
++#define B6_SCAN 0x1 /* 9bit */
++
++#define B7_MT 0x3 /* SDRAM */
++#define B7_Trcd 0x1 /* 3clk */
++#define B7_SCAN 0x1 /* 9bit */
++
++/* REFRESH parameter */
++#define REFEN 0x1 /* Refresh enable */
++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
++#define Trp 0x0 /* 2clk */
++#define Trc 0x3 /* 7clk */
++#define Tchr 0x2 /* 3clk */
++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
++/**************************************/
++
++_TEXT_BASE:
++ .word TEXT_BASE
++
++.globl lowlevel_init
++lowlevel_init:
++ /* memory control configuration */
++ /* make r0 relative the current location so that it */
++ /* reads SMRDATA out of FLASH rather than memory ! */
++ ldr r0, =SMRDATA
++ ldr r1, _TEXT_BASE
++ sub r0, r0, r1
++ ldr r1, =BWSCON /* Bus Width Status Controller */
++ add r2, r0, #13*4
++0:
++ ldr r3, [r0], #4
++ str r3, [r1], #4
++ cmp r2, r0
++ bne 0b
++
++ /* everything is fine now */
++ mov pc, lr
++
++ .ltorg
++/* the literal pools origin */
++
++SMRDATA:
++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
++ .word 0x32
++ .word 0x30
++ .word 0x30
+Index: u-boot/include/configs/hxd8.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/include/configs/hxd8.h 2007-03-28 18:45:57.000000000 +0200
+@@ -0,0 +1,268 @@
++/*
++ * (C) Copyright 2007 OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * Configuation settings for the FIC HXD8
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* we want to be able to start u-boot directly from within NAND flash */
++#define CONFIG_LL_INIT_NAND_ONLY
++#define CONFIG_S3C2410_NAND_BOOT 1
++#define CONFIG_S3C2410_NAND_SKIP_BAD 1
++
++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC */
++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */
++
++/* input clock of PLL */
++#define CONFIG_SYS_CLK_FREQ 16934400/* the HXD8 has this input clock */
++
++
++#define USE_920T_MMU 1
++#define CONFIG_USE_IRQ 1
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024)
++ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/*
++ * Hardware drivers
++ */
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on GTA01 */
++
++/************************************************************
++ * RTC
++ ************************************************************/
++#define CONFIG_RTC_S3C24X0 1
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++#define CONFIG_COMMANDS (\
++ CFG_CMD_BDI | \
++ CFG_CMD_LOADS | \
++ CFG_CMD_LAODB | \
++ CFG_CMD_IMI | \
++ CFG_CMD_CACHE | \
++ CFG_CMD_MEMORY | \
++ CFG_CMD_ENV | \
++ /* CFG_CMD_IRQ | */ \
++ CFG_CMD_BOOTD | \
++ CFG_CMD_CONSOLE | \
++ CFG_CMD_BMP | \
++ CFG_CMD_ASKENV | \
++ CFG_CMD_RUN | \
++ CFG_CMD_ECHO | \
++ CFG_CMD_I2C | \
++ CFG_CMD_REGINFO | \
++ CFG_CMD_IMMAP | \
++ CFG_CMD_DATE | \
++ CFG_CMD_AUTOSCRIPT | \
++ CFG_CMD_BSP | \
++ CFG_CMD_ELF | \
++ CFG_CMD_MISC | \
++ /* CFG_CMD_USB | */ \
++ CFG_CMD_JFFS2 | \
++ CFG_CMD_DIAG | \
++ /* CFG_CMD_HWFLOW | */ \
++ CFG_CMD_SAVES | \
++ CFG_CMD_NAND | \
++ CFG_CMD_PORTIO | \
++ CFG_CMD_MMC | \
++ CFG_CMD_FAT | \
++ CFG_CMD_EXT2 | \
++ 0)
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTARGS ""
++#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
++
++#define CONFIG_DOS_PARTITION 1
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
++/* what's this ? it's not used anywhere */
++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "HXD8 # " /* Monitor Command Prompt */
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 64 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0x33000000 /* default load address */
++
++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
++/* it to wrap 100 times (total 1562500) to get 1 sec. */
++#define CFG_HZ 1562500
++
++/* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++#if 0
++#define CONFIG_USB_OHCI 1
++#endif
++
++#define CONFIG_USB_DEVICE 1
++#define CONFIG_USB_TTY 1
++#define CFG_CONSOLE_IS_IN_ENV 1
++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc"
++#define CONFIG_USBD_PRODUCT_NAME "HXD8 Bootloader " U_BOOT_VERSION
++#define CONFIG_USBD_DFU 1
++#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
++#define CONFIG_USBD_DFU_INTERFACE 2
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "usbtty=cdc_acm\0" \
++ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8\0" \
++ ""
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++/* No NOR flash in this device */
++#define CFG_NO_FLASH 1
++
++#define CFG_ENV_IS_IN_NAND 1
++#define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */
++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
++#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
++
++#define NAND_MAX_CHIPS 1
++#define CFG_NAND_BASE 0x4e000000
++#define CFG_MAX_NAND_DEVICE 1
++
++#define CONFIG_MMC 1
++#define CFG_MMC_BASE 0xff000000
++
++/* EXT2 driver */
++#define CONFIG_EXT2 1
++
++#define CONFIG_FAT 1
++#define CONFIG_SUPPORT_VFAT
++
++#if 1
++/* JFFS2 driver */
++#define CONFIG_JFFS2_CMDLINE 1
++#define CONFIG_JFFS2_NAND 1
++#define CONFIG_JFFS2_NAND_DEV 0
++//#define CONFIG_JFFS2_NAND_OFF 0x634000
++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
++#endif
++
++/* ATAG configuration */
++#define CONFIG_INITRD_TAG 1
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_CMDLINE_TAG 1
++#define CONFIG_REVISION_TAG 1
++#if 0
++#define CONFIG_SERIAL_TAG 1
++#endif
++
++#define CONFIG_DRIVER_S3C24X0_I2C 1
++#define CONFIG_HARD_I2C 1
++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */
++#define CFG_I2C_SLAVE 0x7f
++
++/* we have a board_late_init() function */
++#define BOARD_LATE_INIT 1
++
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_S3C2410
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_SPLASH_SCREEN
++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
++#define CONFIG_VIDEO_BMP_GZIP
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++#define CONFIG_UNZIP
++
++#define VIDEO_KBD_INIT_FCT 0
++#define VIDEO_TSTC_FCT serial_tstc
++#define VIDEO_GETC_FCT serial_getc
++
++#define LCD_VIDEO_ADDR 0x33d00000
++
++#define CONFIG_S3C2410_NAND_BBT 1
++#define CONFIG_S3C2410_NAND_HWECC 1
++
++#define CONFIG_DRIVER_PCF50606 1
++
++#define MTDIDS_DEFAULT "nand0=hxd8-nand"
++#define MTPARTS_DEFAULT "hxd8-nand:256k(u-boot),16k(u-boot_env),2M(kernel),640k(splash),-(jffs2)"
++
++#endif /* __CONFIG_H */
+Index: u-boot/board/hxd8/udc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/udc.c 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,30 @@
++
++#include <common.h>
++#include <usbdcore.h>
++#include <s3c2440.h>
++
++#if defined(CONFIG_USB_DEVICE)
++
++void udc_ctrl(enum usbd_event event, int param)
++{
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ switch (event) {
++ case UDC_CTRL_PULLUP_ENABLE:
++ if (param)
++ gpio->GPBDAT |= (1 << 9); /* GPB9 */
++ else
++ gpio->GPBDAT &= ~(1 << 9); /* GPB9 */
++ break;
++ case UDC_CTRL_500mA_ENABLE:
++ if (param)
++ gpio->GPADAT |= (1 << 0); /* GPA0 */
++ else
++ gpio->GPADAT &= ~(1 << 0); /* GPA0 */
++ break;
++ default:
++ break;
++ }
++}
++
++#endif /* CONFIG_USB_DEVICE */
+Index: u-boot/board/hxd8/pcf50606.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/pcf50606.c 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,68 @@
++
++#include <common.h>
++#include <pcf50606.h>
++
++/* initial register set for PCF50606 in HXD8 devices */
++const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = {
++ [PCF50606_REG_OOCS] = 0x00,
++ /* gap */
++ [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND |
++ PCF50606_INT1_CHGFOK |
++ PCF50606_INT1_CHGERR |
++ PCF50606_INT1_CHGFRDY |
++ PCF50606_INT1_CHGPROT |
++ PCF50606_INT1_CHGWD10S |
++ PCF50606_INT1_CHGWDEXP,
++ [PCF50606_REG_INT2M] = 0x00,
++ [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES,
++ [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK |
++ PCF50606_OOCC1_CHGWAK |
++ PCF50606_OOCC1_EXTONWAK_HIGH,
++ [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms |
++ PCF50606_OOCC2_EXTONDB_14ms,
++ /* gap */
++ [PCF50606_REG_PSSC] = 0x00,
++ [PCF50606_REG_PWROKM] = 0x00,
++ /* gap */
++ [PCF50606_REG_DCDC1] = 0xf0, /* CORE_1V3: on */
++ [PCF50606_REG_DCDC2] = 0x00,
++ [PCF50606_REG_DCDC3] = 0x00,
++ [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */
++
++ [PCF50606_REG_DCDEC1] = 0xe8, /* IO1_3V3: off */
++ [PCF50606_REG_DCDEC2] = 0x00,
++
++ [PCF50606_REG_DCUDC1] = 0xe8, /* RF_3V3: on */
++ [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */
++
++ [PCF50606_REG_IOREGC] = 0xf8, /* AUDIO_3V3: on */
++
++ [PCF50606_REG_D1REGC1] = 0xf8, /* RC_3V3: on */
++
++ [PCF50606_REG_D2REGC1] = 0x18, /* GPS_3V3: off */
++
++ [PCF50606_REG_D3REGC1] = 0xf8, /* IO2_3V3: off */
++
++ [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */
++ [PCF50606_REG_LPREGC2] = 0x00,
++
++ [PCF50606_REG_MBCC1] = 0x00, /* charger unused */
++ [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */
++ [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */
++ [PCF50606_REG_BBCC] = 0x1f, /* 400uA */
++ [PCF50606_REG_ADCC1] = 0x00,
++ [PCF50606_REG_ADCC2] = 0x00,
++ /* gap */
++ [PCF50606_REG_ACDC1] = 0x00,
++ [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3,
++ [PCF50606_REG_PWMC1] = 0x00,
++ [PCF50606_REG_LEDC1] = 0x00,
++ [PCF50606_REG_LEDC2] = 0x00,
++ [PCF50606_REG_GPOC1] = 0x00,
++ [PCF50606_REG_GPOC2] = 0x00,
++ [PCF50606_REG_GPOC3] = 0x00,
++ [PCF50606_REG_GPOC4] = 0x00,
++ [PCF50606_REG_GPOC5] = 0x00,
++};
++
++
+Index: u-boot/board/hxd8/config.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/config.mk 2007-03-28 18:41:52.000000000 +0200
+@@ -0,0 +1,22 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++# David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++#
++# FIC HXD8 board with S3C2440X (ARM920T) cpu
++#
++# see http://www.samsung.com/ for more information on SAMSUNG
++#
++
++# HXD81v011 or later has 1 bank of 128 MB SDRAM
++#
++# 3000'0000 to 3800'0000
++# we load ourself to 37F8'0000
++#
++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
++# optionally with a ramdisk at 3080'0000
++#
++# download area is 3200'0000 or 3300'0000
++
++# FIXME: TEXT_BASE = 0x37F80000
++TEXT_BASE = 0x33F80000
+Index: u-boot/board/hxd8/u-boot.lds
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/hxd8/u-boot.lds 2007-03-28 18:44:45.000000000 +0200
+@@ -0,0 +1,58 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm920t/start.o (.text)
++ cpu/arm920t/s3c24x0/nand_read.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
Added: trunk/src/target/u-boot/patches/uboot-smdk2440.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-smdk2440.patch 2007-03-28 16:58:18 UTC (rev 1541)
+++ trunk/src/target/u-boot/patches/uboot-smdk2440.patch 2007-03-28 16:58:51 UTC (rev 1542)
@@ -0,0 +1,2011 @@
+Add support for the Samsung SMDK2440 development board
+
+Index: u-boot/Makefile
+===================================================================
+--- u-boot.orig/Makefile 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/Makefile 2007-03-28 18:32:42.000000000 +0200
+@@ -1997,6 +1997,9 @@
+ smdk2410_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
+
++smdk2440_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0
++
+ SX1_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm925t sx1
+
+Index: u-boot/include/s3c24x0.h
+===================================================================
+--- u-boot.orig/include/s3c24x0.h 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/include/s3c24x0.h 2007-03-28 18:25:50.000000000 +0200
+@@ -82,7 +82,7 @@
+ S3C24X0_REG32 PRIORITY;
+ S3C24X0_REG32 INTPND;
+ S3C24X0_REG32 INTOFFSET;
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ S3C24X0_REG32 SUBSRCPND;
+ S3C24X0_REG32 INTSUBMSK;
+ #endif
+@@ -92,11 +92,11 @@
+ /* DMAS (see manual chapter 8) */
+ typedef struct {
+ S3C24X0_REG32 DISRC;
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ S3C24X0_REG32 DISRCC;
+ #endif
+ S3C24X0_REG32 DIDST;
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ S3C24X0_REG32 DIDSTC;
+ #endif
+ S3C24X0_REG32 DCON;
+@@ -107,7 +107,7 @@
+ #ifdef CONFIG_S3C2400
+ S3C24X0_REG32 res[1];
+ #endif
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ S3C24X0_REG32 res[7];
+ #endif
+ } /*__attribute__((__packed__))*/ S3C24X0_DMA;
+@@ -126,6 +126,9 @@
+ S3C24X0_REG32 CLKCON;
+ S3C24X0_REG32 CLKSLOW;
+ S3C24X0_REG32 CLKDIVN;
++#ifdef CONFIG_S3C2440
++ S3C24X0_REG32 CAMDIVN;
++#endif
+ } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+
+
+@@ -145,7 +148,7 @@
+ S3C24X0_REG32 res[8];
+ S3C24X0_REG32 DITHMODE;
+ S3C24X0_REG32 TPAL;
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ S3C24X0_REG32 LCDINTPND;
+ S3C24X0_REG32 LCDSRCPND;
+ S3C24X0_REG32 LCDINTMSK;
+@@ -157,6 +160,9 @@
+ /* NAND FLASH (see S3C2410 manual chapter 6) */
+ typedef struct {
+ S3C24X0_REG32 NFCONF;
++#ifdef CONFIG_S3C2440
++ S3C24X0_REG32 NFCONT;
++#endif
+ S3C24X0_REG32 NFCMD;
+ S3C24X0_REG32 NFADDR;
+ S3C24X0_REG32 NFDATA;
+@@ -164,6 +170,15 @@
+ S3C24X0_REG32 NFECC;
+ } /*__attribute__((__packed__))*/ S3C2410_NAND;
+
++/* NAND FLASH (see S3C2440 manual chapter 6) */
++typedef struct {
++ S3C24X0_REG32 NFCONF;
++ S3C24X0_REG32 NFCMD;
++ S3C24X0_REG32 NFADDR;
++ S3C24X0_REG32 NFDATA;
++ S3C24X0_REG32 NFSTAT;
++ S3C24X0_REG32 NFECC;
++} /*__attribute__((__packed__))*/ S3C2440_NAND;
+
+ /* UART (see manual chapter 11) */
+ typedef struct {
+@@ -451,6 +466,65 @@
+ S3C24X0_REG32 GSTATUS3;
+ S3C24X0_REG32 GSTATUS4;
+ #endif
++#ifdef CONFIG_S3C2440
++ S3C24X0_REG32 GPACON;
++ S3C24X0_REG32 GPADAT;
++ S3C24X0_REG32 res1[2];
++ S3C24X0_REG32 GPBCON;
++ S3C24X0_REG32 GPBDAT;
++ S3C24X0_REG32 GPBUP;
++ S3C24X0_REG32 res2;
++ S3C24X0_REG32 GPCCON;
++ S3C24X0_REG32 GPCDAT;
++ S3C24X0_REG32 GPCUP;
++ S3C24X0_REG32 res3;
++ S3C24X0_REG32 GPDCON;
++ S3C24X0_REG32 GPDDAT;
++ S3C24X0_REG32 GPDUP;
++ S3C24X0_REG32 res4;
++ S3C24X0_REG32 GPECON;
++ S3C24X0_REG32 GPEDAT;
++ S3C24X0_REG32 GPEUP;
++ S3C24X0_REG32 res5;
++ S3C24X0_REG32 GPFCON;
++ S3C24X0_REG32 GPFDAT;
++ S3C24X0_REG32 GPFUP;
++ S3C24X0_REG32 res6;
++ S3C24X0_REG32 GPGCON;
++ S3C24X0_REG32 GPGDAT;
++ S3C24X0_REG32 GPGUP;
++ S3C24X0_REG32 res7;
++ S3C24X0_REG32 GPHCON;
++ S3C24X0_REG32 GPHDAT;
++ S3C24X0_REG32 GPHUP;
++ S3C24X0_REG32 res8;
++
++ S3C24X0_REG32 MISCCR;
++ S3C24X0_REG32 DCLKCON;
++ S3C24X0_REG32 EXTINT0;
++ S3C24X0_REG32 EXTINT1;
++ S3C24X0_REG32 EXTINT2;
++ S3C24X0_REG32 EINTFLT0;
++ S3C24X0_REG32 EINTFLT1;
++ S3C24X0_REG32 EINTFLT2;
++ S3C24X0_REG32 EINTFLT3;
++ S3C24X0_REG32 EINTMASK;
++ S3C24X0_REG32 EINTPEND;
++ S3C24X0_REG32 GSTATUS0;
++ S3C24X0_REG32 GSTATUS1;
++ S3C24X0_REG32 GSTATUS2;
++ S3C24X0_REG32 GSTATUS3;
++ S3C24X0_REG32 GSTATUS4;
++
++ S3C24X0_REG32 res9;
++ S3C24X0_REG32 DSC0;
++ S3C24X0_REG32 DSC1;
++ S3C24X0_REG32 MSLCON;
++ S3C24X0_REG32 GPJCON;
++ S3C24X0_REG32 GPJDAT;
++ S3C24X0_REG32 GPJUP;
++ S3C24X0_REG32 res10;
++#endif
+ } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
+
+
+Index: u-boot/rtc/s3c24x0_rtc.c
+===================================================================
+--- u-boot.orig/rtc/s3c24x0_rtc.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/rtc/s3c24x0_rtc.c 2007-03-28 18:25:50.000000000 +0200
+@@ -34,6 +34,8 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+
+ #include <rtc.h>
+Index: u-boot/include/s3c2440.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/include/s3c2440.h 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,295 @@
++/*
++ * (C) Copyright 2003
++ * David Müller ELSOFT AG Switzerland. d.mueller at elsoft.ch
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/************************************************
++ * NAME : s3c2440.h
++ * Version : 2007.
++ *
++ * Based on S3C2410X User's manual Rev 1.1
++ ************************************************/
++
++#ifndef __S3C2440_H__
++#define __S3C2440_H__
++
++#define S3C24X0_UART_CHANNELS 3
++#define S3C24X0_SPI_CHANNELS 2
++
++/* S3C2440 only supports 512 Byte HW ECC */
++#define S3C2440_ECCSIZE 512
++#define S3C2440_ECCBYTES 3
++
++typedef enum {
++ S3C24X0_UART0,
++ S3C24X0_UART1,
++ S3C24X0_UART2
++} S3C24X0_UARTS_NR;
++
++/* S3C2440 device base addresses */
++#define S3C24X0_MEMCTL_BASE 0x48000000
++#define S3C24X0_USB_HOST_BASE 0x49000000
++#define S3C24X0_INTERRUPT_BASE 0x4A000000
++#define S3C24X0_DMA_BASE 0x4B000000
++#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
++#define S3C24X0_LCD_BASE 0x4D000000
++#define S3C2440_NAND_BASE 0x4E000000
++#define S3C24X0_UART_BASE 0x50000000
++#define S3C24X0_TIMER_BASE 0x51000000
++#define S3C24X0_USB_DEVICE_BASE 0x52000140
++#define USB_DEVICE_PHYS_ADR 0x52000000
++#define S3C24X0_WATCHDOG_BASE 0x53000000
++#define S3C24X0_I2C_BASE 0x54000000
++#define S3C24X0_I2S_BASE 0x55000000
++#define S3C24X0_GPIO_BASE 0x56000000
++#define S3C24X0_RTC_BASE 0x57000000
++#define S3C2440_ADC_BASE 0x58000000
++#define S3C24X0_SPI_BASE 0x59000000
++#define S3C2440_SDI_BASE 0x5A000000
++
++
++/* include common stuff */
++#include <s3c24x0.h>
++
++
++static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
++{
++ return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
++}
++static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
++{
++ return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
++}
++static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
++{
++ return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
++}
++static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
++{
++ return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
++}
++static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
++{
++ return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
++}
++static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
++{
++ return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
++}
++static inline S3C2440_NAND * S3C2440_GetBase_NAND(void)
++{
++ return (S3C2440_NAND * const)S3C2440_NAND_BASE;
++}
++static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
++{
++ return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
++}
++static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
++{
++ return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
++}
++static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
++{
++ return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
++}
++static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
++{
++ return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
++}
++static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
++{
++ return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
++}
++static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
++{
++ return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
++}
++static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
++{
++ return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
++}
++static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
++{
++ return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
++}
++/*
++static inline S3C2440_ADC * S3C2440_GetBase_ADC(void)
++{
++ return (S3C2440_ADC * const)S3C2440_ADC_BASE;
++}
++static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
++{
++ return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
++}
++*/
++static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
++{
++ return (S3C2410_SDI * const)S3C2440_SDI_BASE;
++}
++
++/* ISR */
++#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
++#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
++#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
++#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
++#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
++#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
++#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
++#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
++
++#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
++#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
++#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
++#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
++#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
++#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
++#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
++#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
++#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
++#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
++#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
++#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
++#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
++#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
++#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
++#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
++#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
++#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
++#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
++#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
++#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
++#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
++#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
++#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
++#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
++#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
++#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
++#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
++#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
++#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
++
++
++/* PENDING BIT */
++#define BIT_EINT0 (0x1)
++#define BIT_EINT1 (0x1<<1)
++#define BIT_EINT2 (0x1<<2)
++#define BIT_EINT3 (0x1<<3)
++#define BIT_EINT4_7 (0x1<<4)
++#define BIT_EINT8_23 (0x1<<5)
++#define BIT_BAT_FLT (0x1<<7)
++#define BIT_TICK (0x1<<8)
++#define BIT_WDT (0x1<<9)
++#define BIT_TIMER0 (0x1<<10)
++#define BIT_TIMER1 (0x1<<11)
++#define BIT_TIMER2 (0x1<<12)
++#define BIT_TIMER3 (0x1<<13)
++#define BIT_TIMER4 (0x1<<14)
++#define BIT_UART2 (0x1<<15)
++#define BIT_LCD (0x1<<16)
++#define BIT_DMA0 (0x1<<17)
++#define BIT_DMA1 (0x1<<18)
++#define BIT_DMA2 (0x1<<19)
++#define BIT_DMA3 (0x1<<20)
++#define BIT_SDI (0x1<<21)
++#define BIT_SPI0 (0x1<<22)
++#define BIT_UART1 (0x1<<23)
++#define BIT_USBD (0x1<<25)
++#define BIT_USBH (0x1<<26)
++#define BIT_IIC (0x1<<27)
++#define BIT_UART0 (0x1<<28)
++#define BIT_SPI1 (0x1<<29)
++#define BIT_RTC (0x1<<30)
++#define BIT_ADC (0x1<<31)
++#define BIT_ALLMSK (0xFFFFFFFF)
++
++#define ClearPending(bit) {\
++ rSRCPND = bit;\
++ rINTPND = bit;\
++ rINTPND;\
++ }
++/* Wait until rINTPND is changed for the case that the ISR is very short. */
++
++#define __REG(x) (*(volatile unsigned long *)(x))
++#define __REGl(x) (*(volatile unsigned long *)(x))
++#define __REGw(x) (*(volatile unsigned short *)(x))
++#define __REGb(x) (*(volatile unsigned char *)(x))
++#define __REG2(x,y) (*(volatile unsigned long *)((x) + (y)))
++
++/*
++ * * Nand flash controller
++ * */
++
++#define NFDATA8 (*(volatile unsigned char *)0x4E000010)
++#define NFDATA16 (*(volatile unsigned short *)0x4E000010)
++#define NFDATA32 (*(volatile unsigned *)0x4E000010)
++
++#define NFCONF __REG(0x4E000000)
++#define NFCONT __REG(0x4E000004)
++#define NFCMD __REG(0x4E000008)
++#define NFADDR __REGb(0x4E00000C)
++#define NFMECCD0 __REG(0x4E000014)
++#define NFMECCD1 __REG(0x4E000018)
++#define NFSECCD __REG(0x4E00001C)
++#define NFSTAT __REG(0x4E000020)
++#define NFESTAT0 __REG(0x4E000024)
++#define NFESTAT1 __REG(0x4E000028)
++#define NFMECC0 __REG(0x4E00002C)
++#define NFMECC1 __REG(0x4E000030)
++#define NFSECC __REG(0x4E000034)
++#define NFSBLK __REG(0x4E000038)
++
++
++#define S3C2410_MISCCR_USBDEV (0<<3)
++#define S3C2410_MISCCR_USBHOST (1<<3)
++
++#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
++#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
++#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
++#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
++#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
++#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
++#define S3C2410_MISCCR_CLK0_MASK (7<<4)
++
++#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
++#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
++#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
++#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
++#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
++#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
++#define S3C2410_MISCCR_CLK1_MASK (7<<8)
++
++#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
++#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
++
++#define S3C2410_MISCCR_nRSTCON (1<<16)
++
++#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
++#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
++#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
++#define S3C2410_MISCCR_SDSLEEP (7<<17)
++
++#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
++#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
++#define S3C2410_CLKSLOW_SLOW (1<<4)
++#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
++#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
++
++#endif /*__S3C2440_H__*/
+Index: u-boot/include/configs/smdk2440.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/include/configs/smdk2440.h 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,294 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger at sysgo.de>
++ * Gary Jennejohn <gj at denx.de>
++ * David Mueller <d.mueller at elsoft.ch>
++ *
++ * Configuation settings for the SAMSUNG SMDK2410 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#if 0
++/* If we want to start u-boot from usb bootloader in NOR flash */
++#define CONFIG_SKIP_RELOCATE_UBOOT 1
++#define CONFIG_SKIP_LOWLEVEL_INIT 1
++#else
++/* If we want to start u-boot directly from within NAND flash */
++#define CONFIG_LL_INIT_NAND_ONLY
++#define CONFIG_S3C2410_NAND_BOOT 1
++#define CONFIG_S3C2410_NAND_SKIP_BAD 1
++#endif
++
++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */
++
++/* input clock of PLL */
++#define CONFIG_SYS_CLK_FREQ 16934400/* the SMDK2410 has 12MHz input clock */
++
++
++#define USE_920T_MMU 1
++#define CONFIG_USE_IRQ 1
++//#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
++#define CS8900_BASE 0x19000300
++#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL3 1 /* we use SERIAL 1 on SMDK2410 */
++//#define CONFIG_HWFLOW 1
++
++/************************************************************
++ * RTC
++ ************************************************************/
++#define CONFIG_RTC_S3C24X0 1
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++#define CONFIG_COMMANDS \
++ (CONFIG_CMD_DFL | \
++ /*CFG_CMD_BSP | */ \
++ CFG_CMD_CACHE | \
++ CFG_CMD_DATE | \
++ /*CFG_CMD_DHCP | */ \
++ CFG_CMD_DIAG | \
++ CFG_CMD_ELF | \
++ /*CFG_CMD_EXT2 | */ \
++ /*CFG_CMD_FAT | */ \
++ /*CFG_CMD_HWFLOW | */ \
++ /* CFG_CMD_IDE | */ \
++ /* CFG_CMD_IRQ | */ \
++ CFG_CMD_JFFS2 | \
++ /*CFG_CMD_MMC | */ \
++ CFG_CMD_NAND | \
++ CFG_CMD_PING | \
++ /*CFG_CMD_PORTIO | */ \
++ CFG_CMD_REGINFO | \
++ /*CFG_CMD_SAVES | */ \
++ CFG_CMD_USB)
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8"
++#define CONFIG_ETHADDR 00:0c:20:02:0a:5b
++#define CONFIG_NETMASK 255.255.255.0
++#define CONFIG_IPADDR 192.168.1.100
++#define CONFIG_SERVERIP 192.168.1.21
++/*#define CONFIG_BOOTFILE "elinos-lart" */
++//#define CONFIG_BOOTCOMMAND "nand read 0x32000000 0x34000 0x200000; bootm"
++#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm"
++
++#define CONFIG_DOS_PARTITION 1
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
++/* what's this ? it's not used anywhere */
++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "HXD8 # " /* Monitor Command Prompt */
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 32 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0x32000000 /* default load address */
++
++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
++/* it to wrap 100 times (total 1562500) to get 1 sec. */
++#define CFG_HZ 1562500
++
++/* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (512*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/* IDE/ATA config */
++
++#if 0
++#define CFG_IDE_MAXBUS 1
++#define CFG_IDE_MAXDEVICE 2
++#define CFG_IDE_PREINIT 0
++
++#define CFG_ATA_BASE_ADDR
++#endif
++
++#define CONFIG_USB_OHCI 1
++
++#define CONFIG_USB_DEVICE 1
++#define CONFIG_USB_TTY 1
++#define CFG_CONSOLE_IS_IN_ENV 1
++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
++#define CONFIG_USBD_MANUFACTURER "FiWin"
++#define CONFIG_USBD_PRODUCT_NAME "S2C2440 Bootloader " U_BOOT_VERSION
++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0"
++#define CONFIG_USBD_DFU 1
++#define CONFIG_USBD_DFU_XFER_SIZE 4096
++#define CONFIG_USBD_DFU_INTERFACE 2
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++
++#define CFG_FLASH_BASE PHYS_FLASH_1
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
++#if 0
++#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
++#endif
++
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#ifdef CONFIG_AMD_LV800
++#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
++#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
++#endif
++#ifdef CONFIG_AMD_LV400
++#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
++#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
++#endif
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
++
++#define CFG_ENV_IS_IN_NAND 1
++#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */
++#define CFG_ENV_OFFSET 0xa0000 /* environment after bootloader */
++#define NAND_ENV_BADBLOCK_CHK 1 /* Check for Environment Badblock*/
++#ifdef NAND_ENV_BADBLOCK_CHK
++#define CFG_ENV_END 0xe0000 /*The last block for Environment*/
++#endif
++
++#define NAND_MAX_CHIPS 1
++#define CFG_NAND_BASE 0x4e000000
++#define CFG_MAX_NAND_DEVICE 1
++
++#define CONFIG_MMC 1
++#define CFG_MMC_BASE 0xff000000
++
++#define CONFIG_EXT2 1
++
++#define CONFIG_NEW_QT2440 0
++
++/* FAT driver in u-boot is broken currently */
++#define CONFIG_FAT 1
++#define CONFIG_SUPPORT_VFAT
++
++#if 1
++/* JFFS2 driver */
++#define CONFIG_JFFS2_CMDLINE 1
++#define CONFIG_JFFS2_NAND 1
++#define CONFIG_JFFS2_NAND_DEV 0
++//#define CONFIG_JFFS2_NAND_OFF 0x634000
++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
++#endif
++
++/* ATAG configuration */
++#define CONFIG_INITRD_TAG 1
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_CMDLINE_TAG 1
++#if 0
++#define CONFIG_SERIAL_TAG 1
++#define CONFIG_REVISION_TAG 1
++#endif
++
++
++#if 0
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_S3C2410
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++
++#define VIDEO_KBD_INIT_FCT 0
++#define VIDEO_TSTC_FCT serial_tstc
++#define VIDEO_GETC_FCT serial_getc
++
++#define LCD_VIDEO_ADDR 0x33d00000
++#endif
++
++#define CFG_NAND_YAFFS_WRITE
++#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT
++
++#define MTDIDS_DEFAULT "nand0=qt2440-nand"
++#define MTPARTS_DEFAULT "qt2440-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)"
++
++#endif /* __CONFIG_H */
+Index: u-boot/include/configs/smdk2440nand.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/include/configs/smdk2440nand.h 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,47 @@
++/*
++ * (C) Copyright 2004
++ * Samsung Electronics : SW.LEE <hitchcar at samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++
++#ifndef __SMDK2440_NAND_H
++#define __SMDK2440_NAND_H
++
++#define CFG_ENV_NAND_BLOCK 8
++
++#if 0 //old flash
++#define NAND_OOB_SIZE (16)
++#define NAND_PAGES_IN_BLOCK (32)
++#define NAND_PAGE_SIZE (512)
++
++#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK)
++#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1)
++#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1)
++#else //new flash
++#define NAND_OOB_SIZE (64)
++#define NAND_PAGES_IN_BLOCK (64)
++#define NAND_PAGE_SIZE (2048)
++
++#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK)
++#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1)
++#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1)
++
++#endif
++
++
++
++//#define NAND_3_ADDR_CYCLE 1
++//#define S3C24X0_16BIT_NAND 1
++
++#ifdef KINGFISH
++#undef S3C24X0_16BIT_NAND
++#define S3C24X0_16BIT_NAND 1
++#endif
++
++#endif
++
+Index: u-boot/include/common.h
+===================================================================
+--- u-boot.orig/include/common.h 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/include/common.h 2007-03-28 18:25:50.000000000 +0200
+@@ -452,7 +452,7 @@
+ ulong get_OPB_freq (void);
+ ulong get_PCI_freq (void);
+ #endif
+-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_LH7A40X)
+ void s3c2410_irq(void);
+ #define ARM920_IRQ_CALLBACK s3c2410_irq
+ ulong get_FCLK (void);
+Index: u-boot/cpu/arm920t/s3c24x0/usb_ohci.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/usb_ohci.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/cpu/arm920t/s3c24x0/usb_ohci.c 2007-03-28 18:25:50.000000000 +0200
+@@ -44,6 +44,8 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+
+ #include <malloc.h>
+Index: u-boot/cpu/arm920t/s3c24x0/speed.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/cpu/arm920t/s3c24x0/speed.c 2007-03-28 18:25:50.000000000 +0200
+@@ -30,12 +30,15 @@
+ */
+
+ #include <common.h>
+-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
++ defined (CONFIG_S3C2440) || defined (CONFIG_TRAB)
+
+ #if defined(CONFIG_S3C2400)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+
+ #define MPLL 0
+@@ -66,8 +69,12 @@
+ m = ((r & 0xFF000) >> 12) + 8;
+ p = ((r & 0x003F0) >> 4) + 2;
+ s = r & 0x3;
+-
++#ifndef CONFIG_S3C2440
+ return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
++#else
++ /* To avoid integer overflow, changed the calc order */
++ return( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
++#endif
+ }
+
+ /* return FCLK frequency */
+@@ -81,7 +88,21 @@
+ {
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+
++#ifndef CONFIG_S3C2440
+ return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
++#else
++ switch (clk_power->CLKDIVN & 0x6) {
++ case 0x0:
++ return get_FCLK();
++ case 0x2:
++ return get_FCLK()/2;
++ case 0x4:
++ return (clk_power->CAMDIVN & 0x200) ? get_FCLK()/8 : get_FCLK()/4;
++ case 0x6:
++ return (clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3;
++ }
++ return 0;
++#endif
+ }
+
+ /* return PCLK frequency */
+@@ -98,4 +119,5 @@
+ return(get_PLLCLK(UPLL));
+ }
+
+-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c 2007-03-28 18:25:50.000000000 +0200
+@@ -30,13 +30,16 @@
+ */
+
+ #include <common.h>
+-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
+
+ #include <arm920t.h>
+ #if defined(CONFIG_S3C2400)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+
+ int timer_load_val = 0;
+@@ -59,6 +62,7 @@
+ /* use PWM Timer 4 because it has no output */
+ /* prescaler for Timer 4 is 16 */
+ timers->TCFG0 = 0x0f00;
++#ifndef CONFIG_S3C2440
+ if (timer_load_val == 0)
+ {
+ /*
+@@ -68,6 +72,9 @@
+ */
+ timer_load_val = get_PCLK()/(2 * 16 * 100);
+ }
++#else
++ timer_load_val = get_PCLK()/(2 * 16 * 100);
++#endif
+ /* load value for 10 ms timeout */
+ lastdec = timers->TCNTB4 = timer_load_val;
+ /* auto load, manual update of Timer 4 */
+@@ -178,6 +185,7 @@
+ tbclk = timer_load_val * 100;
+ #elif defined(CONFIG_SBC2410X) || \
+ defined(CONFIG_SMDK2410) || \
++ defined(CONFIG_SMDK2440) || \
+ defined(CONFIG_VCMA9)
+ tbclk = CFG_HZ;
+ #else
+@@ -232,4 +240,5 @@
+ }
+ #endif /* USE_IRQ */
+
+-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/serial.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/cpu/arm920t/s3c24x0/serial.c 2007-03-28 18:25:50.000000000 +0200
+@@ -19,12 +19,15 @@
+ */
+
+ #include <common.h>
+-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
+
+ #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+
+ DECLARE_GLOBAL_DATA_PTR;
+@@ -180,4 +183,5 @@
+ }
+ }
+
+-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/i2c.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/cpu/arm920t/s3c24x0/i2c.c 2007-03-28 18:25:50.000000000 +0200
+@@ -34,6 +34,8 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
+ #endif
+ #include <i2c.h>
+
+@@ -63,7 +65,7 @@
+ {
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ return (gpio->GPEDAT & 0x8000) >> 15;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -82,7 +84,7 @@
+ {
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -139,7 +141,7 @@
+ }
+
+ if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ ulong old_gpecon = gpio->GPECON;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -147,7 +149,7 @@
+ #endif
+ /* bus still busy probably by (most) previously interrupted transfer */
+
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
+ gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
+ #endif
+@@ -171,7 +173,7 @@
+ udelay (1000);
+
+ /* restore pin functions */
+-#ifdef CONFIG_S3C2410
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ gpio->GPECON = old_gpecon;
+ #endif
+ #ifdef CONFIG_S3C2400
+Index: u-boot/board/smdk2440/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/Makefile 2007-03-28 18:33:40.000000000 +0200
+@@ -0,0 +1,51 @@
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := smdk2440.o flash.o udc.o
++SOBJS := lowlevel_init.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot/board/smdk2440/config.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/config.mk 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,25 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++# David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++#
++# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
++#
++# see http://www.samsung.com/ for more information on SAMSUNG
++#
++
++#
++# SMDK2410 has 1 bank of 64 MB DRAM
++#
++# 3000'0000 to 3400'0000
++#
++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
++# optionally with a ramdisk at 3080'0000
++#
++# we load ourself to 33F8'0000
++#
++# download area is 3300'0000
++#
++
++
++TEXT_BASE = 0x33F80000
+Index: u-boot/board/smdk2440/flash.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/flash.c 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,433 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Alex Zuepke <azu at sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++
++ulong myflush (void);
++
++
++#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
++#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++
++
++#define CMD_READ_ARRAY 0x000000F0
++#define CMD_UNLOCK1 0x000000AA
++#define CMD_UNLOCK2 0x00000055
++#define CMD_ERASE_SETUP 0x00000080
++#define CMD_ERASE_CONFIRM 0x00000030
++#define CMD_PROGRAM 0x000000A0
++#define CMD_UNLOCK_BYPASS 0x00000020
++
++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
++
++#define BIT_ERASE_DONE 0x00000080
++#define BIT_RDY_MASK 0x00000080
++#define BIT_PROGRAM_ERROR 0x00000020
++#define BIT_TIMEOUT 0x80000000 /* our flag */
++
++#define READY 1
++#define ERR 2
++#define TMO 4
++
++/*-----------------------------------------------------------------------
++ */
++
++ulong flash_init (void)
++{
++ int i, j;
++ ulong size = 0;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
++ ulong flashbase = 0;
++
++ flash_info[i].flash_id =
++#if defined(CONFIG_AMD_LV400)
++ (AMD_MANUFACT & FLASH_VENDMASK) |
++ (AMD_ID_LV400B & FLASH_TYPEMASK);
++#elif defined(CONFIG_AMD_LV800)
++ (AMD_MANUFACT & FLASH_VENDMASK) |
++ (AMD_ID_LV800B & FLASH_TYPEMASK);
++#else
++#error "Unknown flash configured"
++#endif
++ flash_info[i].size = FLASH_BANK_SIZE;
++ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
++ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
++ if (i == 0)
++ flashbase = PHYS_FLASH_1;
++ else
++ panic ("configured too many flash banks!\n");
++ for (j = 0; j < flash_info[i].sector_count; j++) {
++ if (j <= 3) {
++ /* 1st one is 16 KB */
++ if (j == 0) {
++ flash_info[i].start[j] =
++ flashbase + 0;
++ }
++
++ /* 2nd and 3rd are both 8 KB */
++ if ((j == 1) || (j == 2)) {
++ flash_info[i].start[j] =
++ flashbase + 0x4000 + (j -
++ 1) *
++ 0x2000;
++ }
++
++ /* 4th 32 KB */
++ if (j == 3) {
++ flash_info[i].start[j] =
++ flashbase + 0x8000;
++ }
++ } else {
++ flash_info[i].start[j] =
++ flashbase + (j - 3) * MAIN_SECT_SIZE;
++ }
++ }
++ size += flash_info[i].size;
++ }
++
++ flash_protect (FLAG_PROTECT_SET,
++ CFG_FLASH_BASE,
++ CFG_FLASH_BASE + monitor_flash_len - 1,
++ &flash_info[0]);
++
++ flash_protect (FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
++
++ return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t * info)
++{
++ int i;
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case (AMD_MANUFACT & FLASH_VENDMASK):
++ printf ("AMD: ");
++ break;
++ default:
++ printf ("Unknown Vendor ");
++ break;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case (AMD_ID_LV400B & FLASH_TYPEMASK):
++ printf ("1x Amd29LV400BB (4Mbit)\n");
++ break;
++ case (AMD_ID_LV800B & FLASH_TYPEMASK):
++ printf ("1x Amd29LV800BB (8Mbit)\n");
++ break;
++ default:
++ printf ("Unknown Chip Type\n");
++ goto Done;
++ break;
++ }
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; i++) {
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++ printf (" %08lX%s", info->start[i],
++ info->protect[i] ? " (RO)" : " ");
++ }
++ printf ("\n");
++
++ Done:;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t * info, int s_first, int s_last)
++{
++ ushort result;
++ int iflag, cflag, prot, sect;
++ int rc = ERR_OK;
++ int chip;
++
++ /* first look for protection bits */
++
++ if (info->flash_id == FLASH_UNKNOWN)
++ return ERR_UNKNOWN_FLASH_TYPE;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ return ERR_INVAL;
++ }
++
++ if ((info->flash_id & FLASH_VENDMASK) !=
++ (AMD_MANUFACT & FLASH_VENDMASK)) {
++ return ERR_UNKNOWN_FLASH_VENDOR;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++ if (prot)
++ return ERR_PROTECTED;
++
++ /*
++ * Disable interrupts which might cause a timeout
++ * here. Remember that our exception vectors are
++ * at address 0 in the flash, and we don't want a
++ * (ticker) exception to happen while the flash
++ * chip is in programming mode.
++ */
++ cflag = icache_status ();
++ icache_disable ();
++ iflag = disable_interrupts ();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
++ printf ("Erasing sector %2d ... ", sect);
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ if (info->protect[sect] == 0) { /* not protected */
++ vu_short *addr = (vu_short *) (info->start[sect]);
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ *addr = CMD_ERASE_CONFIRM;
++
++ /* wait until flash is ready */
++ chip = 0;
++
++ do {
++ result = *addr;
++
++ /* check timeout */
++ if (get_timer_masked () >
++ CFG_FLASH_ERASE_TOUT) {
++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++ chip = TMO;
++ break;
++ }
++
++ if (!chip
++ && (result & 0xFFFF) & BIT_ERASE_DONE)
++ chip = READY;
++
++ if (!chip
++ && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
++ chip = ERR;
++
++ } while (!chip);
++
++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++
++ if (chip == ERR) {
++ rc = ERR_PROG_ERROR;
++ goto outahere;
++ }
++ if (chip == TMO) {
++ rc = ERR_TIMOUT;
++ goto outahere;
++ }
++
++ printf ("ok.\n");
++ } else { /* it was protected */
++
++ printf ("protected!\n");
++ }
++ }
++
++ if (ctrlc ())
++ printf ("User Interrupt!\n");
++
++ outahere:
++ /* allow flash to settle - wait 10 ms */
++ udelay_masked (10000);
++
++ if (iflag)
++ enable_interrupts ();
++
++ if (cflag)
++ icache_enable ();
++
++ return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash
++ */
++
++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
++{
++ vu_short *addr = (vu_short *) dest;
++ ushort result;
++ int rc = ERR_OK;
++ int cflag, iflag;
++ int chip;
++
++ /*
++ * Check if Flash is (sufficiently) erased
++ */
++ result = *addr;
++ if ((result & data) != data)
++ return ERR_NOT_ERASED;
++
++
++ /*
++ * Disable interrupts which might cause a timeout
++ * here. Remember that our exception vectors are
++ * at address 0 in the flash, and we don't want a
++ * (ticker) exception to happen while the flash
++ * chip is in programming mode.
++ */
++ cflag = icache_status ();
++ icache_disable ();
++ iflag = disable_interrupts ();
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
++ *addr = CMD_PROGRAM;
++ *addr = data;
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ /* wait until flash is ready */
++ chip = 0;
++ do {
++ result = *addr;
++
++ /* check timeout */
++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++ chip = ERR | TMO;
++ break;
++ }
++ if (!chip && ((result & 0x80) == (data & 0x80)))
++ chip = READY;
++
++ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
++ result = *addr;
++
++ if ((result & 0x80) == (data & 0x80))
++ chip = READY;
++ else
++ chip = ERR;
++ }
++
++ } while (!chip);
++
++ *addr = CMD_READ_ARRAY;
++
++ if (chip == ERR || *addr != data)
++ rc = ERR_PROG_ERROR;
++
++ if (iflag)
++ enable_interrupts ();
++
++ if (cflag)
++ icache_enable ();
++
++ return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash.
++ */
++
++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
++{
++ ulong cp, wp;
++ int l;
++ int i, rc;
++ ushort data;
++
++ wp = (addr & ~1); /* get lower word aligned address */
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++ for (; i < 2 && cnt > 0; ++i) {
++ data = (data >> 8) | (*src++ << 8);
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < 2; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++
++ if ((rc = write_hword (info, wp, data)) != 0) {
++ return (rc);
++ }
++ wp += 2;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ while (cnt >= 2) {
++ data = *((vu_short *) src);
++ if ((rc = write_hword (info, wp, data)) != 0) {
++ return (rc);
++ }
++ src += 2;
++ wp += 2;
++ cnt -= 2;
++ }
++
++ if (cnt == 0) {
++ return ERR_OK;
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
++ data = (data >> 8) | (*src++ << 8);
++ --cnt;
++ }
++ for (; i < 2; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++
++ return write_hword (info, wp, data);
++}
+Index: u-boot/board/smdk2440/lowlevel_init.S
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/lowlevel_init.S 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,167 @@
++/*
++ * Memory Setup stuff - taken from blob memsetup.S
++ *
++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
++ * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
++ *
++ * Modified for the Samsung SMDK2410 by
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++
++
++/* some parameters for the board */
++
++/*
++ *
++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
++ *
++ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar at sec.samsung.com>
++ *
++ */
++
++#define BWSCON 0x48000000
++
++/* BWSCON */
++#define DW8 (0x0)
++#define DW16 (0x1)
++#define DW32 (0x2)
++#define WAIT (0x1<<2)
++#define UBLB (0x1<<3)
++
++#define B1_BWSCON (DW32)
++#define B2_BWSCON (DW16)
++#define B3_BWSCON (DW16 + WAIT + UBLB)
++#define B4_BWSCON (DW16)
++#define B5_BWSCON (DW16)
++#define B6_BWSCON (DW32)
++#define B7_BWSCON (DW32)
++
++/* BANK0CON */
++#define B0_Tacs 0x0 /* 0clk */
++#define B0_Tcos 0x0 /* 0clk */
++#define B0_Tacc 0x7 /* 14clk */
++#define B0_Tcoh 0x0 /* 0clk */
++#define B0_Tah 0x0 /* 0clk */
++#define B0_Tacp 0x0
++#define B0_PMC 0x0 /* normal */
++
++/* BANK1CON */
++#define B1_Tacs 0x0 /* 0clk */
++#define B1_Tcos 0x0 /* 0clk */
++#define B1_Tacc 0x7 /* 14clk */
++#define B1_Tcoh 0x0 /* 0clk */
++#define B1_Tah 0x0 /* 0clk */
++#define B1_Tacp 0x0
++#define B1_PMC 0x0
++
++#define B2_Tacs 0x0
++#define B2_Tcos 0x0
++#define B2_Tacc 0x7
++#define B2_Tcoh 0x0
++#define B2_Tah 0x0
++#define B2_Tacp 0x0
++#define B2_PMC 0x0
++
++#define B3_Tacs 0x0 /* 0clk */
++#define B3_Tcos 0x3 /* 4clk */
++#define B3_Tacc 0x7 /* 14clk */
++#define B3_Tcoh 0x1 /* 1clk */
++#define B3_Tah 0x0 /* 0clk */
++#define B3_Tacp 0x3 /* 6clk */
++#define B3_PMC 0x0 /* normal */
++
++#define B4_Tacs 0x0 /* 0clk */
++#define B4_Tcos 0x0 /* 0clk */
++#define B4_Tacc 0x7 /* 14clk */
++#define B4_Tcoh 0x0 /* 0clk */
++#define B4_Tah 0x0 /* 0clk */
++#define B4_Tacp 0x0
++#define B4_PMC 0x0 /* normal */
++
++#define B5_Tacs 0x0 /* 0clk */
++#define B5_Tcos 0x0 /* 0clk */
++#define B5_Tacc 0x7 /* 14clk */
++#define B5_Tcoh 0x0 /* 0clk */
++#define B5_Tah 0x0 /* 0clk */
++#define B5_Tacp 0x0
++#define B5_PMC 0x0 /* normal */
++
++#define B6_MT 0x3 /* SDRAM */
++#define B6_Trcd 0x1
++#define B6_SCAN 0x1 /* 9bit */
++
++#define B7_MT 0x3 /* SDRAM */
++#define B7_Trcd 0x1 /* 3clk */
++#define B7_SCAN 0x1 /* 9bit */
++
++/* REFRESH parameter */
++#define REFEN 0x1 /* Refresh enable */
++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
++#define Trp 0x0 /* 2clk */
++#define Trc 0x3 /* 7clk */
++#define Tchr 0x2 /* 3clk */
++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
++/**************************************/
++
++_TEXT_BASE:
++ .word TEXT_BASE
++
++.globl lowlevel_init
++lowlevel_init:
++ /* memory control configuration */
++ /* make r0 relative the current location so that it */
++ /* reads SMRDATA out of FLASH rather than memory ! */
++ ldr r0, =SMRDATA
++ ldr r1, _TEXT_BASE
++ sub r0, r0, r1
++ ldr r1, =BWSCON /* Bus Width Status Controller */
++ add r2, r0, #13*4
++0:
++ ldr r3, [r0], #4
++ str r3, [r1], #4
++ cmp r2, r0
++ bne 0b
++
++ /* everything is fine now */
++ mov pc, lr
++
++ .ltorg
++/* the literal pools origin */
++
++SMRDATA:
++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
++ .word 0x32
++ .word 0x30
++ .word 0x30
+Index: u-boot/board/smdk2440/smdk2440.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/smdk2440.c 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,139 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger at sysgo.de>
++ *
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <s3c2440.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define FCLK_SPEED 1
++
++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
++#define M_MDIV 0xC3
++#define M_PDIV 0x4
++#define M_SDIV 0x1
++#elif FCLK_SPEED==1 /* Fout = 399.65MHz */
++#define M_MDIV 0x6e
++#define M_PDIV 0x3
++#define M_SDIV 0x1
++#endif
++
++#define USB_CLOCK 1
++
++#if USB_CLOCK==0
++#define U_M_MDIV 0xA1
++#define U_M_PDIV 0x3
++#define U_M_SDIV 0x1
++#elif USB_CLOCK==1
++#define U_M_MDIV 0x3c
++#define U_M_PDIV 0x4
++#define U_M_SDIV 0x2
++#endif
++
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ /* to reduce PLL lock time, adjust the LOCKTIME register */
++ clk_power->LOCKTIME = 0xFFFFFF;
++
++ /* configure MPLL */
++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (4000);
++
++ /* configure UPLL */
++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (8000);
++
++ /* set up the I/O ports */
++ gpio->GPACON = 0x007FFFFF;
++ gpio->GPBCON = 0x00044555;
++ gpio->GPBUP = 0x000007FF;
++ gpio->GPCCON = 0xAAAAAAAA;
++ gpio->GPCUP = 0x0000FFFF;
++ gpio->GPDCON = 0xAAAAAAAA;
++ gpio->GPDUP = 0x0000FFFF;
++ gpio->GPECON = 0xAAAAAAAA;
++ gpio->GPEUP = 0x0000FFFF;
++ gpio->GPFCON = 0x000055AA;
++ gpio->GPFUP = 0x000000FF;
++ gpio->GPGCON = 0xFF95FFBA;
++ gpio->GPGUP = 0x0000FFFF;
++#ifdef CONFIG_SERIAL3
++ gpio->GPHCON = 0x002AAAAA;
++#else
++ gpio->GPHCON = 0x002AFAAA;
++#endif
++ gpio->GPHUP = 0x000007FF;
++
++#if 0
++ /* USB Device Part */
++ /*GPGCON is reset for USB Device */
++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
++
++ gpio->GPGDAT |= ( 1 << 12) ;
++ gpio->GPGDAT &= ~( 1 << 12) ;
++ udelay(20000);
++ gpio->GPGDAT |= ( 1 << 12) ;
++#endif
++
++ /* arch number of SMDK2440-Board */
++ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0x30000100;
++
++ icache_enable();
++ dcache_enable();
++
++ return 0;
++}
++
++int dram_init (void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
+Index: u-boot/board/smdk2440/u-boot.lds
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/u-boot.lds 2007-03-28 18:25:50.000000000 +0200
+@@ -0,0 +1,57 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm920t/start.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+Index: u-boot/drivers/usbdcore_s3c2410.c
+===================================================================
+--- u-boot.orig/drivers/usbdcore_s3c2410.c 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/drivers/usbdcore_s3c2410.c 2007-03-28 18:25:50.000000000 +0200
+@@ -24,7 +24,7 @@
+
+ #include <config.h>
+
+-#if defined(CONFIG_S3C2410) && defined(CONFIG_USB_DEVICE)
++#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE)
+
+ #include <common.h>
+
+Index: u-boot/drivers/usbtty.h
+===================================================================
+--- u-boot.orig/drivers/usbtty.h 2007-03-28 18:25:44.000000000 +0200
++++ u-boot/drivers/usbtty.h 2007-03-28 18:25:50.000000000 +0200
+@@ -29,7 +29,7 @@
+ #include "usbdcore_mpc8xx.h"
+ #elif defined(CONFIG_OMAP1510)
+ #include "usbdcore_omap1510.h"
+-#elif defined(CONFIG_S3C2410)
++#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ #include "usbdcore_s3c2410.h"
+ #endif
+
+Index: u-boot/board/smdk2440/udc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot/board/smdk2440/udc.c 2007-03-28 18:34:29.000000000 +0200
+@@ -0,0 +1,20 @@
++
++#include <common.h>
++#include <usbdcore.h>
++#include <s3c2440.h>
++
++void udc_ctrl(enum usbd_event event, int param)
++{
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ switch (event) {
++ case UDC_CTRL_PULLUP_ENABLE:
++ /* FIXME: implement this */
++ break;
++ case UDC_CTRL_500mA_ENABLE:
++ /* IGNORE */
++ break;
++ default:
++ break;
++ }
++}
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