r3443 - in trunk/src/host/qemu-neo1973: . audio darwin-user fpu hw linux-user linux-user/i386 linux-user/x86_64 pc-bios target-arm/nwfpe target-i386 target-m68k target-mips target-ppc target-sparc tests
andrew at sita.openmoko.org
andrew at sita.openmoko.org
Mon Nov 19 19:55:59 CET 2007
Author: andrew
Date: 2007-11-19 19:54:17 +0100 (Mon, 19 Nov 2007)
New Revision: 3443
Added:
trunk/src/host/qemu-neo1973/console.h
trunk/src/host/qemu-neo1973/hw/arm-misc.h
trunk/src/host/qemu-neo1973/hw/audiodev.h
trunk/src/host/qemu-neo1973/hw/boards.h
trunk/src/host/qemu-neo1973/hw/devices.h
trunk/src/host/qemu-neo1973/hw/fdc.h
trunk/src/host/qemu-neo1973/hw/firmware_abi.h
trunk/src/host/qemu-neo1973/hw/flash.h
trunk/src/host/qemu-neo1973/hw/gumstix.c
trunk/src/host/qemu-neo1973/hw/hw.h
trunk/src/host/qemu-neo1973/hw/isa.h
trunk/src/host/qemu-neo1973/hw/mcf.h
trunk/src/host/qemu-neo1973/hw/mips.h
trunk/src/host/qemu-neo1973/hw/nvram.h
trunk/src/host/qemu-neo1973/hw/pc.h
trunk/src/host/qemu-neo1973/hw/pci.h
trunk/src/host/qemu-neo1973/hw/pcmcia.h
trunk/src/host/qemu-neo1973/hw/pflash_cfi01.c
trunk/src/host/qemu-neo1973/hw/ppc.h
trunk/src/host/qemu-neo1973/hw/primecell.h
trunk/src/host/qemu-neo1973/hw/ps2.h
trunk/src/host/qemu-neo1973/hw/scsi-disk.h
trunk/src/host/qemu-neo1973/hw/sh.h
trunk/src/host/qemu-neo1973/hw/sparc32_dma.h
trunk/src/host/qemu-neo1973/hw/stellaris_input.c
trunk/src/host/qemu-neo1973/hw/sun4m.h
trunk/src/host/qemu-neo1973/net.h
trunk/src/host/qemu-neo1973/qemu-char.h
trunk/src/host/qemu-neo1973/qemu-timer.h
trunk/src/host/qemu-neo1973/sysemu.h
Removed:
trunk/src/host/qemu-neo1973/hw/arm_pic.h
trunk/src/host/qemu-neo1973/hw/m48t59.h
trunk/src/host/qemu-neo1973/vl.h
Modified:
trunk/src/host/qemu-neo1973/Makefile
trunk/src/host/qemu-neo1973/Makefile.target
trunk/src/host/qemu-neo1973/arm-semi.c
trunk/src/host/qemu-neo1973/audio/alsaaudio.c
trunk/src/host/qemu-neo1973/audio/audio.c
trunk/src/host/qemu-neo1973/audio/audio.h
trunk/src/host/qemu-neo1973/audio/coreaudio.c
trunk/src/host/qemu-neo1973/audio/dsoundaudio.c
trunk/src/host/qemu-neo1973/audio/fmodaudio.c
trunk/src/host/qemu-neo1973/audio/mixeng.c
trunk/src/host/qemu-neo1973/audio/noaudio.c
trunk/src/host/qemu-neo1973/audio/ossaudio.c
trunk/src/host/qemu-neo1973/audio/sdlaudio.c
trunk/src/host/qemu-neo1973/audio/wavaudio.c
trunk/src/host/qemu-neo1973/audio/wavcapture.c
trunk/src/host/qemu-neo1973/block-raw.c
trunk/src/host/qemu-neo1973/block-vvfat.c
trunk/src/host/qemu-neo1973/block.c
trunk/src/host/qemu-neo1973/block.h
trunk/src/host/qemu-neo1973/check_ops.sh
trunk/src/host/qemu-neo1973/cocoa.m
trunk/src/host/qemu-neo1973/configure
trunk/src/host/qemu-neo1973/console.c
trunk/src/host/qemu-neo1973/cpu-all.h
trunk/src/host/qemu-neo1973/cpu-defs.h
trunk/src/host/qemu-neo1973/darwin-user/main.c
trunk/src/host/qemu-neo1973/darwin-user/qemu.h
trunk/src/host/qemu-neo1973/dyngen-exec.h
trunk/src/host/qemu-neo1973/dyngen.c
trunk/src/host/qemu-neo1973/dyngen.h
trunk/src/host/qemu-neo1973/elf_ops.h
trunk/src/host/qemu-neo1973/exec-all.h
trunk/src/host/qemu-neo1973/exec.c
trunk/src/host/qemu-neo1973/fpu/softfloat-specialize.h
trunk/src/host/qemu-neo1973/fpu/softfloat.c
trunk/src/host/qemu-neo1973/fpu/softfloat.h
trunk/src/host/qemu-neo1973/gdbstub.c
trunk/src/host/qemu-neo1973/hw/acpi.c
trunk/src/host/qemu-neo1973/hw/adb.c
trunk/src/host/qemu-neo1973/hw/adlib.c
trunk/src/host/qemu-neo1973/hw/ads7846.c
trunk/src/host/qemu-neo1973/hw/an5206.c
trunk/src/host/qemu-neo1973/hw/apb_pci.c
trunk/src/host/qemu-neo1973/hw/apic.c
trunk/src/host/qemu-neo1973/hw/arm_boot.c
trunk/src/host/qemu-neo1973/hw/arm_pic.c
trunk/src/host/qemu-neo1973/hw/arm_sysctl.c
trunk/src/host/qemu-neo1973/hw/arm_timer.c
trunk/src/host/qemu-neo1973/hw/armv7m.c
trunk/src/host/qemu-neo1973/hw/armv7m_nvic.c
trunk/src/host/qemu-neo1973/hw/bt-hci.c
trunk/src/host/qemu-neo1973/hw/cdrom.c
trunk/src/host/qemu-neo1973/hw/cirrus_vga.c
trunk/src/host/qemu-neo1973/hw/cs4231.c
trunk/src/host/qemu-neo1973/hw/cuda.c
trunk/src/host/qemu-neo1973/hw/dma.c
trunk/src/host/qemu-neo1973/hw/ds1225y.c
trunk/src/host/qemu-neo1973/hw/dummy_m68k.c
trunk/src/host/qemu-neo1973/hw/ecc.c
trunk/src/host/qemu-neo1973/hw/eepro100.c
trunk/src/host/qemu-neo1973/hw/eeprom93xx.c
trunk/src/host/qemu-neo1973/hw/eeprom93xx.h
trunk/src/host/qemu-neo1973/hw/es1370.c
trunk/src/host/qemu-neo1973/hw/esp.c
trunk/src/host/qemu-neo1973/hw/etraxfs.c
trunk/src/host/qemu-neo1973/hw/etraxfs_ser.c
trunk/src/host/qemu-neo1973/hw/etraxfs_timer.c
trunk/src/host/qemu-neo1973/hw/fdc.c
trunk/src/host/qemu-neo1973/hw/gps.c
trunk/src/host/qemu-neo1973/hw/grackle_pci.c
trunk/src/host/qemu-neo1973/hw/gt64xxx.c
trunk/src/host/qemu-neo1973/hw/heathrow_pic.c
trunk/src/host/qemu-neo1973/hw/i2c.c
trunk/src/host/qemu-neo1973/hw/i2c.h
trunk/src/host/qemu-neo1973/hw/i8254.c
trunk/src/host/qemu-neo1973/hw/i8259.c
trunk/src/host/qemu-neo1973/hw/ide.c
trunk/src/host/qemu-neo1973/hw/integratorcp.c
trunk/src/host/qemu-neo1973/hw/iommu.c
trunk/src/host/qemu-neo1973/hw/irq.c
trunk/src/host/qemu-neo1973/hw/irq.h
trunk/src/host/qemu-neo1973/hw/isa_mmio.c
trunk/src/host/qemu-neo1973/hw/jazz_led.c
trunk/src/host/qemu-neo1973/hw/jbt6k74.c
trunk/src/host/qemu-neo1973/hw/lsi53c895a.c
trunk/src/host/qemu-neo1973/hw/m48t59.c
trunk/src/host/qemu-neo1973/hw/mac_dbdma.c
trunk/src/host/qemu-neo1973/hw/mac_nvram.c
trunk/src/host/qemu-neo1973/hw/macio.c
trunk/src/host/qemu-neo1973/hw/max111x.c
trunk/src/host/qemu-neo1973/hw/max7310.c
trunk/src/host/qemu-neo1973/hw/mc146818rtc.c
trunk/src/host/qemu-neo1973/hw/mcf5206.c
trunk/src/host/qemu-neo1973/hw/mcf5208.c
trunk/src/host/qemu-neo1973/hw/mcf_fec.c
trunk/src/host/qemu-neo1973/hw/mcf_intc.c
trunk/src/host/qemu-neo1973/hw/mcf_uart.c
trunk/src/host/qemu-neo1973/hw/mips_int.c
trunk/src/host/qemu-neo1973/hw/mips_malta.c
trunk/src/host/qemu-neo1973/hw/mips_mipssim.c
trunk/src/host/qemu-neo1973/hw/mips_pica61.c
trunk/src/host/qemu-neo1973/hw/mips_r4k.c
trunk/src/host/qemu-neo1973/hw/mips_timer.c
trunk/src/host/qemu-neo1973/hw/mipsnet.c
trunk/src/host/qemu-neo1973/hw/modem.c
trunk/src/host/qemu-neo1973/hw/mpcore.c
trunk/src/host/qemu-neo1973/hw/nand.c
trunk/src/host/qemu-neo1973/hw/ne2000.c
trunk/src/host/qemu-neo1973/hw/neo1973.c
trunk/src/host/qemu-neo1973/hw/omap.c
trunk/src/host/qemu-neo1973/hw/omap.h
trunk/src/host/qemu-neo1973/hw/omap1_clk.c
trunk/src/host/qemu-neo1973/hw/omap_i2c.c
trunk/src/host/qemu-neo1973/hw/omap_lcdc.c
trunk/src/host/qemu-neo1973/hw/omap_mmc.c
trunk/src/host/qemu-neo1973/hw/openpic.c
trunk/src/host/qemu-neo1973/hw/palm.c
trunk/src/host/qemu-neo1973/hw/parallel.c
trunk/src/host/qemu-neo1973/hw/pc.c
trunk/src/host/qemu-neo1973/hw/pcf5060x.c
trunk/src/host/qemu-neo1973/hw/pci.c
trunk/src/host/qemu-neo1973/hw/pckbd.c
trunk/src/host/qemu-neo1973/hw/pcnet.c
trunk/src/host/qemu-neo1973/hw/pcspk.c
trunk/src/host/qemu-neo1973/hw/pflash_cfi02.c
trunk/src/host/qemu-neo1973/hw/piix_pci.c
trunk/src/host/qemu-neo1973/hw/pl011.c
trunk/src/host/qemu-neo1973/hw/pl022.c
trunk/src/host/qemu-neo1973/hw/pl031.c
trunk/src/host/qemu-neo1973/hw/pl050.c
trunk/src/host/qemu-neo1973/hw/pl061.c
trunk/src/host/qemu-neo1973/hw/pl080.c
trunk/src/host/qemu-neo1973/hw/pl110.c
trunk/src/host/qemu-neo1973/hw/pl181.c
trunk/src/host/qemu-neo1973/hw/pl190.c
trunk/src/host/qemu-neo1973/hw/ppc.c
trunk/src/host/qemu-neo1973/hw/ppc405_boards.c
trunk/src/host/qemu-neo1973/hw/ppc405_uc.c
trunk/src/host/qemu-neo1973/hw/ppc4xx_devs.c
trunk/src/host/qemu-neo1973/hw/ppc_chrp.c
trunk/src/host/qemu-neo1973/hw/ppc_mac.h
trunk/src/host/qemu-neo1973/hw/ppc_oldworld.c
trunk/src/host/qemu-neo1973/hw/ppc_prep.c
trunk/src/host/qemu-neo1973/hw/prep_pci.c
trunk/src/host/qemu-neo1973/hw/ps2.c
trunk/src/host/qemu-neo1973/hw/ptimer.c
trunk/src/host/qemu-neo1973/hw/pxa.h
trunk/src/host/qemu-neo1973/hw/pxa2xx.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_dma.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_gpio.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_lcd.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_mmci.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_pcmcia.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_pic.c
trunk/src/host/qemu-neo1973/hw/pxa2xx_timer.c
trunk/src/host/qemu-neo1973/hw/r2d.c
trunk/src/host/qemu-neo1973/hw/realview.c
trunk/src/host/qemu-neo1973/hw/realview_gic.c
trunk/src/host/qemu-neo1973/hw/rtl8139.c
trunk/src/host/qemu-neo1973/hw/s3c.h
trunk/src/host/qemu-neo1973/hw/s3c2410.c
trunk/src/host/qemu-neo1973/hw/s3c24xx_gpio.c
trunk/src/host/qemu-neo1973/hw/s3c24xx_lcd.c
trunk/src/host/qemu-neo1973/hw/s3c24xx_mmci.c
trunk/src/host/qemu-neo1973/hw/s3c24xx_rtc.c
trunk/src/host/qemu-neo1973/hw/s3c24xx_udc.c
trunk/src/host/qemu-neo1973/hw/sb16.c
trunk/src/host/qemu-neo1973/hw/scsi-disk.c
trunk/src/host/qemu-neo1973/hw/sd.c
trunk/src/host/qemu-neo1973/hw/sd.h
trunk/src/host/qemu-neo1973/hw/serial.c
trunk/src/host/qemu-neo1973/hw/sh7750.c
trunk/src/host/qemu-neo1973/hw/sh7750_regnames.c
trunk/src/host/qemu-neo1973/hw/sh_intc.c
trunk/src/host/qemu-neo1973/hw/sh_serial.c
trunk/src/host/qemu-neo1973/hw/sh_timer.c
trunk/src/host/qemu-neo1973/hw/shix.c
trunk/src/host/qemu-neo1973/hw/slavio_intctl.c
trunk/src/host/qemu-neo1973/hw/slavio_misc.c
trunk/src/host/qemu-neo1973/hw/slavio_serial.c
trunk/src/host/qemu-neo1973/hw/slavio_timer.c
trunk/src/host/qemu-neo1973/hw/smbus.c
trunk/src/host/qemu-neo1973/hw/smbus.h
trunk/src/host/qemu-neo1973/hw/smbus_eeprom.c
trunk/src/host/qemu-neo1973/hw/smc91c111.c
trunk/src/host/qemu-neo1973/hw/sparc32_dma.c
trunk/src/host/qemu-neo1973/hw/spitz.c
trunk/src/host/qemu-neo1973/hw/ssd0303.c
trunk/src/host/qemu-neo1973/hw/ssd0323.c
trunk/src/host/qemu-neo1973/hw/stellaris.c
trunk/src/host/qemu-neo1973/hw/sun4m.c
trunk/src/host/qemu-neo1973/hw/sun4u.c
trunk/src/host/qemu-neo1973/hw/tc58128.c
trunk/src/host/qemu-neo1973/hw/tcx.c
trunk/src/host/qemu-neo1973/hw/tsc210x.c
trunk/src/host/qemu-neo1973/hw/unin_pci.c
trunk/src/host/qemu-neo1973/hw/usb-bt.c
trunk/src/host/qemu-neo1973/hw/usb-hid.c
trunk/src/host/qemu-neo1973/hw/usb-hub.c
trunk/src/host/qemu-neo1973/hw/usb-msd.c
trunk/src/host/qemu-neo1973/hw/usb-net.c
trunk/src/host/qemu-neo1973/hw/usb-ohci.c
trunk/src/host/qemu-neo1973/hw/usb-uhci.c
trunk/src/host/qemu-neo1973/hw/usb-wacom.c
trunk/src/host/qemu-neo1973/hw/usb.c
trunk/src/host/qemu-neo1973/hw/usb.h
trunk/src/host/qemu-neo1973/hw/versatile_pci.c
trunk/src/host/qemu-neo1973/hw/versatilepb.c
trunk/src/host/qemu-neo1973/hw/vga.c
trunk/src/host/qemu-neo1973/hw/vmmouse.c
trunk/src/host/qemu-neo1973/hw/vmport.c
trunk/src/host/qemu-neo1973/hw/vmware_vga.c
trunk/src/host/qemu-neo1973/hw/wm8750.c
trunk/src/host/qemu-neo1973/hw/wm8753.c
trunk/src/host/qemu-neo1973/i386-dis.c
trunk/src/host/qemu-neo1973/linux-user/elfload.c
trunk/src/host/qemu-neo1973/linux-user/flatload.c
trunk/src/host/qemu-neo1973/linux-user/i386/syscall.h
trunk/src/host/qemu-neo1973/linux-user/linuxload.c
trunk/src/host/qemu-neo1973/linux-user/main.c
trunk/src/host/qemu-neo1973/linux-user/mmap.c
trunk/src/host/qemu-neo1973/linux-user/qemu.h
trunk/src/host/qemu-neo1973/linux-user/strace.c
trunk/src/host/qemu-neo1973/linux-user/syscall.c
trunk/src/host/qemu-neo1973/linux-user/syscall_defs.h
trunk/src/host/qemu-neo1973/linux-user/uaccess.c
trunk/src/host/qemu-neo1973/linux-user/x86_64/syscall.h
trunk/src/host/qemu-neo1973/loader.c
trunk/src/host/qemu-neo1973/m68k-semi.c
trunk/src/host/qemu-neo1973/monitor.c
trunk/src/host/qemu-neo1973/osdep.c
trunk/src/host/qemu-neo1973/osdep.h
trunk/src/host/qemu-neo1973/pc-bios/README
trunk/src/host/qemu-neo1973/pc-bios/openbios-sparc32
trunk/src/host/qemu-neo1973/pc-bios/openbios-sparc64
trunk/src/host/qemu-neo1973/qemu-common.h
trunk/src/host/qemu-neo1973/readline.c
trunk/src/host/qemu-neo1973/sdl.c
trunk/src/host/qemu-neo1973/softmmu-semi.h
trunk/src/host/qemu-neo1973/softmmu_template.h
trunk/src/host/qemu-neo1973/tap-win32.c
trunk/src/host/qemu-neo1973/target-arm/nwfpe/double_cpdo.c
trunk/src/host/qemu-neo1973/target-arm/nwfpe/fpa11_cpdt.c
trunk/src/host/qemu-neo1973/target-arm/nwfpe/single_cpdo.c
trunk/src/host/qemu-neo1973/target-i386/cpu.h
trunk/src/host/qemu-neo1973/target-i386/helper.c
trunk/src/host/qemu-neo1973/target-m68k/helper.c
trunk/src/host/qemu-neo1973/target-m68k/op.c
trunk/src/host/qemu-neo1973/target-mips/fop_template.c
trunk/src/host/qemu-neo1973/target-mips/op.c
trunk/src/host/qemu-neo1973/target-mips/op_helper.c
trunk/src/host/qemu-neo1973/target-mips/translate.c
trunk/src/host/qemu-neo1973/target-mips/translate_init.c
trunk/src/host/qemu-neo1973/target-ppc/cpu.h
trunk/src/host/qemu-neo1973/target-ppc/exec.h
trunk/src/host/qemu-neo1973/target-ppc/helper.c
trunk/src/host/qemu-neo1973/target-ppc/helper_regs.h
trunk/src/host/qemu-neo1973/target-ppc/op.c
trunk/src/host/qemu-neo1973/target-ppc/op_helper.c
trunk/src/host/qemu-neo1973/target-ppc/op_helper.h
trunk/src/host/qemu-neo1973/target-ppc/op_mem.h
trunk/src/host/qemu-neo1973/target-ppc/translate.c
trunk/src/host/qemu-neo1973/target-ppc/translate_init.c
trunk/src/host/qemu-neo1973/target-sparc/helper.c
trunk/src/host/qemu-neo1973/target-sparc/op_helper.c
trunk/src/host/qemu-neo1973/tests/Makefile
trunk/src/host/qemu-neo1973/thunk.c
trunk/src/host/qemu-neo1973/thunk.h
trunk/src/host/qemu-neo1973/translate-all.c
trunk/src/host/qemu-neo1973/translate-op.c
trunk/src/host/qemu-neo1973/usb-linux-gadget.c
trunk/src/host/qemu-neo1973/usb-linux.c
trunk/src/host/qemu-neo1973/vl.c
trunk/src/host/qemu-neo1973/vnc.c
trunk/src/host/qemu-neo1973/x_keymap.c
Log:
Heavy merge with cvs.savannah.nongnu.org:/sources/qemu.
Modified: trunk/src/host/qemu-neo1973/Makefile
===================================================================
--- trunk/src/host/qemu-neo1973/Makefile 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/Makefile 2007-11-19 18:54:17 UTC (rev 3443)
@@ -3,8 +3,10 @@
include config-host.mak
.PHONY: all clean distclean dvi info install install-doc tar tarbin \
- speed test test2 html dvi info
+ speed test html dvi info
+VPATH=$(SRC_PATH):$(SRC_PATH)/hw
+
BASE_CFLAGS=
BASE_LDFLAGS=
@@ -48,9 +50,16 @@
# CPUs and machines.
OBJS=$(BLOCK_OBJS)
-OBJS+=readline.o console.o
+OBJS+=readline.o console.o
OBJS+=block.o
+OBJS+=irq.o
+OBJS+=i2c.o smbus.o smbus_eeprom.o max7310.o max111x.o wm8750.o wm8753.o
+OBJS+=ssd0303.o ssd0323.o ads7846.o pcf5060x.o stellaris_input.o
+OBJS+=scsi-disk.o cdrom.o
+OBJS+=usb.o usb-hub.o usb-linux.o usb-linux-gadget.o
+OBJS+=usb-hid.o usb-msd.o usb-wacom.o usb-net.o usb-bt.o
+
ifdef CONFIG_WIN32
OBJS+=tap-win32.o
endif
@@ -102,7 +111,7 @@
$(CC) $(CFLAGS) $(CPPFLAGS) $(SDL_CFLAGS) $(BASE_CFLAGS) -c -o $@ $<
vnc.o: vnc.c keymaps.c sdl_keysym.h vnchextile.h d3des.c d3des.h
- $(CC) $(CFLAGS) $(CPPFLAGS) $(BASE_CFLAGS) -c -o $@ $<
+ $(CC) $(CFLAGS) $(CPPFLAGS) $(BASE_CFLAGS) $(CONFIG_VNC_TLS_CFLAGS) -c -o $@ $<
audio/sdlaudio.o: audio/sdlaudio.c
$(CC) $(CFLAGS) $(CPPFLAGS) $(SDL_CFLAGS) $(BASE_CFLAGS) -c -o $@ $<
@@ -193,7 +202,7 @@
done
# various test targets
-test speed test2: all
+test speed: all
$(MAKE) -C tests $@
TAGS:
Modified: trunk/src/host/qemu-neo1973/Makefile.target
===================================================================
--- trunk/src/host/qemu-neo1973/Makefile.target 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/Makefile.target 2007-11-19 18:54:17 UTC (rev 3443)
@@ -140,15 +140,15 @@
endif
ifeq ($(ARCH),x86_64)
-BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
+ ifneq ($(CONFIG_SOLARIS),yes)
+ BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
+ endif
endif
ifeq ($(ARCH),ppc)
CPPFLAGS+= -D__powerpc__
-ifdef CONFIG_LINUX_USER
BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
endif
-endif
ifeq ($(ARCH),s390)
BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
@@ -399,7 +399,6 @@
VL_OBJS=vl.o osdep.o monitor.o pci.o loader.o isa_mmio.o
# XXX: suppress QEMU_TOOL tests
VL_OBJS+=block-raw.o
-VL_OBJS+=irq.o
ifdef CONFIG_ALSA
LIBS += -lasound
@@ -421,14 +420,11 @@
LIBS += $(CONFIG_VNC_TLS_LIBS)
endif
-VL_OBJS += i2c.o smbus.o
-
# SCSI layer
-VL_OBJS+= scsi-disk.o cdrom.o lsi53c895a.o
+VL_OBJS+= lsi53c895a.o
# USB layer
-VL_OBJS+= usb.o usb-hub.o usb-linux.o usb-hid.o usb-ohci.o usb-msd.o usb-net.o
-VL_OBJS+= usb-linux-gadget.o usb-bt.o usb-wacom.o
+VL_OBJS+= usb-ohci.o
# EEPROM emulation
VL_OBJS += eeprom93xx.o
@@ -452,7 +448,7 @@
VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o
VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
VL_OBJS+= cirrus_vga.o apic.o parallel.o acpi.o piix_pci.o
-VL_OBJS+= usb-uhci.o smbus_eeprom.o vmmouse.o vmport.o vmware_vga.o
+VL_OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o
CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
endif
ifeq ($(TARGET_BASE_ARCH), ppc)
@@ -476,7 +472,7 @@
VL_OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
VL_OBJS+= jazz_led.o
VL_OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
-VL_OBJS+= piix_pci.o smbus_eeprom.o parallel.o cirrus_vga.o $(SOUND_HW)
+VL_OBJS+= piix_pci.o parallel.o cirrus_vga.o $(SOUND_HW)
VL_OBJS+= mipsnet.o
CPPFLAGS += -DHAS_AUDIO
endif
@@ -502,15 +498,16 @@
VL_OBJS+= arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
VL_OBJS+= versatile_pci.o sd.o ptimer.o
VL_OBJS+= realview_gic.o realview.o arm_sysctl.o mpcore.o
-VL_OBJS+= armv7m.o armv7m_nvic.o stellaris.o ssd0303.o pl022.o
-VL_OBJS+= ssd0323.o pl061.o
+VL_OBJS+= armv7m.o armv7m_nvic.o stellaris.o pl022.o
+VL_OBJS+= pl061.o
VL_OBJS+= arm-semi.o
VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
-VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o max111x.o max7310.o
-VL_OBJS+= spitz.o ads7846.o ide.o serial.o nand.o ecc.o wm8750.o wm8753.o
+VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o
+VL_OBJS+= pflash_cfi01.o gumstix.o
+VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o
VL_OBJS+= s3c2410.o s3c24xx_gpio.o s3c24xx_lcd.o s3c24xx_mmci.o s3c24xx_rtc.o
-VL_OBJS+= s3c24xx_udc.o neo1973.o pcf5060x.o jbt6k74.o gps.o
-VL_OBJS+= $(GSM_OBJS) modem.o
+VL_OBJS+= s3c24xx_udc.o
+VL_OBJS+= neo1973.o jbt6k74.o gps.o $(GSM_OBJS) modem.o
VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
VL_OBJS+= palm.o tsc210x.o
CPPFLAGS+= -DHAS_AUDIO $(GSM_CPPFLAGS)
@@ -568,6 +565,13 @@
endif
endif
+ifeq ($(ARCH),x86_64)
+ VL_LDFLAGS+=-m64
+ ifneq ($(CONFIG_SOLARIS),yes)
+ VL_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
+ endif
+endif
+
ifdef CONFIG_WIN32
SDL_LIBS := $(filter-out -mwindows, $(SDL_LIBS)) -mconsole
endif
Modified: trunk/src/host/qemu-neo1973/arm-semi.c
===================================================================
--- trunk/src/host/qemu-neo1973/arm-semi.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/arm-semi.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -33,7 +33,9 @@
#define ARM_ANGEL_HEAP_SIZE (128 * 1024 * 1024)
#else
-#include "vl.h"
+#include "qemu-common.h"
+#include "sysemu.h"
+#include "gdbstub.h"
#endif
#define SYS_OPEN 0x01
@@ -165,8 +167,14 @@
#endif
}
-#define ARG(n) tget32(args + (n) * 4)
-#define SET_ARG(n, val) tput32(args + (n) * 4,val)
+#define ARG(n) \
+({ \
+ target_ulong __arg; \
+ /* FIXME - handle get_user() failure */ \
+ get_user_ual(__arg, args + (n) * 4); \
+ __arg; \
+})
+#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
uint32_t do_arm_semihosting(CPUState *env)
{
target_ulong args;
@@ -213,7 +221,11 @@
}
case SYS_WRITEC:
{
- char c = tget8(args);
+ char c;
+
+ if (get_user_u8(c, args))
+ /* FIXME - should this error code be -TARGET_EFAULT ? */
+ return (uint32_t)-1;
/* Write to debug console. stderr is near enough. */
if (use_gdb_syscalls()) {
gdb_do_syscall(arm_semi_cb, "write,2,%x,1", args);
Modified: trunk/src/host/qemu-neo1973/audio/alsaaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/alsaaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/alsaaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,8 @@
* THE SOFTWARE.
*/
#include <alsa/asoundlib.h>
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "alsa"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/audio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/audio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/audio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw/hw.h"
+#include "audio.h"
+#include "console.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
#define AUDIO_CAP "audio"
#include "audio_int.h"
@@ -234,7 +238,7 @@
return r;
}
-const char *audio_audfmt_to_string (audfmt_e fmt)
+static const char *audio_audfmt_to_string (audfmt_e fmt)
{
switch (fmt) {
case AUD_FMT_U8:
@@ -260,7 +264,8 @@
return "S16";
}
-audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval, int *defaultp)
+static audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval,
+ int *defaultp)
{
if (!strcasecmp (s, "u8")) {
*defaultp = 0;
Modified: trunk/src/host/qemu-neo1973/audio/audio.h
===================================================================
--- trunk/src/host/qemu-neo1973/audio/audio.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/audio.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -73,7 +73,6 @@
LIST_ENTRY (CaptureState) entries;
} CaptureState;
-typedef struct AudioState AudioState;
typedef struct SWVoiceOut SWVoiceOut;
typedef struct CaptureVoiceOut CaptureVoiceOut;
typedef struct SWVoiceIn SWVoiceIn;
Modified: trunk/src/host/qemu-neo1973/audio/coreaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/coreaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/coreaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,8 @@
#include <string.h> /* strerror */
#include <pthread.h> /* pthread_X */
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "coreaudio"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/dsoundaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/dsoundaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/dsoundaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,8 @@
* SEAL 1.07 by Carlos 'pel' Hasan was used as documentation
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "dsound"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/fmodaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/fmodaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/fmodaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,7 +23,8 @@
*/
#include <fmod.h>
#include <fmod_errors.h>
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "fmod"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/mixeng.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/mixeng.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/mixeng.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "mixeng"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/noaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/noaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/noaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
+#include "qemu-timer.h"
#define AUDIO_CAP "noaudio"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/ossaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/ossaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/ossaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -30,7 +30,8 @@
#else
#include <sys/soundcard.h>
#endif
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#define AUDIO_CAP "oss"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/sdlaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/sdlaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/sdlaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,7 +23,8 @@
*/
#include <SDL.h>
#include <SDL_thread.h>
-#include "vl.h"
+#include "qemu-common.h"
+#include "audio.h"
#ifndef _WIN32
#ifdef __sun__
Modified: trunk/src/host/qemu-neo1973/audio/wavaudio.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/wavaudio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/wavaudio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw/hw.h"
+#include "qemu-timer.h"
+#include "audio.h"
#define AUDIO_CAP "wav"
#include "audio_int.h"
Modified: trunk/src/host/qemu-neo1973/audio/wavcapture.c
===================================================================
--- trunk/src/host/qemu-neo1973/audio/wavcapture.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/audio/wavcapture.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,4 +1,6 @@
-#include "vl.h"
+#include "hw/hw.h"
+#include "console.h"
+#include "audio.h"
typedef struct {
QEMUFile *f;
Modified: trunk/src/host/qemu-neo1973/block-raw.c
===================================================================
--- trunk/src/host/qemu-neo1973/block-raw.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/block-raw.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,10 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifdef QEMU_IMG
#include "qemu-common.h"
-#else
-#include "vl.h"
+#ifndef QEMU_IMG
+#include "qemu-timer.h"
#include "exec-all.h"
#endif
#include "block_int.h"
Modified: trunk/src/host/qemu-neo1973/block-vvfat.c
===================================================================
--- trunk/src/host/qemu-neo1973/block-vvfat.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/block-vvfat.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -175,7 +175,7 @@
return 0;
}
-inline int array_remove_slice(array_t* array,int index, int count)
+static inline int array_remove_slice(array_t* array,int index, int count)
{
assert(index >=0);
assert(count > 0);
@@ -186,13 +186,13 @@
return 0;
}
-int array_remove(array_t* array,int index)
+static int array_remove(array_t* array,int index)
{
return array_remove_slice(array, index, 1);
}
/* return the index for a given member */
-int array_index(array_t* array, void* pointer)
+static int array_index(array_t* array, void* pointer)
{
size_t offset = (char*)pointer - array->pointer;
assert(offset >= 0);
Modified: trunk/src/host/qemu-neo1973/block.c
===================================================================
--- trunk/src/host/qemu-neo1973/block.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/block.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,10 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifdef QEMU_IMG
#include "qemu-common.h"
-#else
-#include "vl.h"
+#ifndef QEMU_IMG
+#include "console.h"
#endif
#include "block_int.h"
@@ -125,7 +124,7 @@
}
-void bdrv_register(BlockDriver *bdrv)
+static void bdrv_register(BlockDriver *bdrv)
{
if (!bdrv->bdrv_aio_read) {
/* add AIO emulation layer */
Modified: trunk/src/host/qemu-neo1973/block.h
===================================================================
--- trunk/src/host/qemu-neo1973/block.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/block.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -2,7 +2,6 @@
#define BLOCK_H
/* block.c */
-typedef struct BlockDriverState BlockDriverState;
typedef struct BlockDriver BlockDriver;
extern BlockDriver bdrv_raw;
Modified: trunk/src/host/qemu-neo1973/check_ops.sh
===================================================================
--- trunk/src/host/qemu-neo1973/check_ops.sh 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/check_ops.sh 2007-11-19 18:54:17 UTC (rev 3443)
@@ -35,6 +35,9 @@
mips*)
ret='\tjr.*ra'
;;
+ s390*)
+ ret='\tbr.*'
+ ;;
*)
echo "Unknown machine `uname -m`"
;;
Modified: trunk/src/host/qemu-neo1973/cocoa.m
===================================================================
--- trunk/src/host/qemu-neo1973/cocoa.m 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/cocoa.m 2007-11-19 18:54:17 UTC (rev 3443)
@@ -37,7 +37,9 @@
#import <Cocoa/Cocoa.h>
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
+#include "sysemu.h"
NSWindow *window = NULL;
NSQuickDrawView *qd_view = NULL;
Modified: trunk/src/host/qemu-neo1973/configure
===================================================================
--- trunk/src/host/qemu-neo1973/configure 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/configure 2007-11-19 18:54:17 UTC (rev 3443)
@@ -320,6 +320,8 @@
;;
--disable-werror) werror="no"
;;
+ *) echo "ERROR: unknown option $opt"; show_help="yes"
+ ;;
esac
done
@@ -358,11 +360,15 @@
ARCH_LDFLAGS="${SP_LDFLAGS}"
fi
;;
+ s390)
+ ARCH_CFLAGS="-march=z900"
+ ;;
esac
if [ "$solaris" = "yes" -a "$cpu" = "x86_64" ] ; then
CFLAGS="${CFLAGS} -m64"
OS_CFLAGS="${OS_CFLAGS} -m64"
+ OS_LDFLAGS="${OS_LDFLAGS} -m64"
fi
if [ "$solaris" = "yes" -a "$cpu" = "i386" ] ; then
@@ -598,7 +604,7 @@
#undef main /* We don't want SDL to override our main() */
int main( void ) { return SDL_Init (SDL_INIT_VIDEO); }
EOF
- if $cc -o $TMPE `$sdl_config --cflags 2> /dev/null` $TMPC `$sdl_config --libs 2> /dev/null` 2> /tmp/qemu-$$-sdl-config.log ; then
+ if $cc -o $TMPE ${OS_CFLAGS} `$sdl_config --cflags 2> /dev/null` $TMPC `$sdl_config --libs 2> /dev/null` 2> /tmp/qemu-$$-sdl-config.log ; then
_sdlversion=`$sdl_config --version | sed 's/[^0-9]//g'`
if test "$_sdlversion" -lt 121 ; then
sdl_too_old=yes
@@ -617,7 +623,7 @@
sdl_static_libs="$sdl_static_libs `aalib-config --static-libs`"
fi
- if $cc -o $TMPE `$sdl_config --cflags 2> /dev/null` $TMPC $sdl_static_libs 2> /dev/null; then
+ if $cc -o $TMPE ${OS_CFLAGS} `$sdl_config --cflags 2> /dev/null` $TMPC $sdl_static_libs 2> /dev/null; then
sdl_static=yes
fi
fi # static link
@@ -1035,7 +1041,6 @@
[ "$target_cpu" = "ppcemb" ] && target_bigendian=yes
[ "$target_cpu" = "ppc64" ] && target_bigendian=yes
[ "$target_cpu" = "ppc64abi32" ] && target_bigendian=yes
-[ "$target_cpu" = "ppc64h" ] && target_bigendian=yes
[ "$target_cpu" = "mips" ] && target_bigendian=yes
[ "$target_cpu" = "mipsn32" ] && target_bigendian=yes
[ "$target_cpu" = "mips64" ] && target_bigendian=yes
@@ -1144,24 +1149,17 @@
echo "#define TARGET_PPCEMB 1" >> $config_h
elif test "$target_cpu" = "ppc64" ; then
echo "TARGET_ARCH=ppc64" >> $config_mak
- echo "#define TARGET_ARCH \"ppc64\"" >> $config_h
echo "TARGET_ABI_DIR=ppc" >> $config_mak
+ echo "#define TARGET_ARCH \"ppc64\"" >> $config_h
echo "#define TARGET_PPC 1" >> $config_h
echo "#define TARGET_PPC64 1" >> $config_h
elif test "$target_cpu" = "ppc64abi32" ; then
echo "TARGET_ARCH=ppc64" >> $config_mak
- echo "#define TARGET_ARCH \"ppc64\"" >> $config_h
echo "TARGET_ABI_DIR=ppc" >> $config_mak
+ echo "#define TARGET_ARCH \"ppc64\"" >> $config_h
echo "#define TARGET_PPC 1" >> $config_h
echo "#define TARGET_PPC64 1" >> $config_h
echo "#define TARGET_ABI32 1" >> $config_h
-elif test "$target_cpu" = "ppc64h" ; then
- echo "TARGET_ARCH=ppc64h" >> $config_mak
- echo "#define TARGET_ARCH \"ppc64h\"" >> $config_h
- echo "TARGET_ABI_DIR=ppc" >> $config_mak
- echo "#define TARGET_PPC 1" >> $config_h
- echo "#define TARGET_PPC64 1" >> $config_h
- echo "#define TARGET_PPC64H 1" >> $config_h
elif test "$target_cpu" = "x86_64" ; then
echo "TARGET_ARCH=x86_64" >> $config_mak
echo "#define TARGET_ARCH \"x86_64\"" >> $config_h
Modified: trunk/src/host/qemu-neo1973/console.c
===================================================================
--- trunk/src/host/qemu-neo1973/console.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/console.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
+#include "qemu-timer.h"
//#define DEBUG_CONSOLE
#define DEFAULT_BACKSCROLL 512
@@ -59,7 +61,7 @@
int count, wptr, rptr;
} QEMUFIFO;
-int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
+static int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
{
int l, len;
@@ -82,7 +84,7 @@
return len1;
}
-int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
+static int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
{
int l, len;
Added: trunk/src/host/qemu-neo1973/console.h
===================================================================
--- trunk/src/host/qemu-neo1973/console.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/console.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,156 @@
+#ifndef CONSOLE_H
+#define CONSOLE_H
+
+#include "qemu-char.h"
+
+/* keyboard/mouse support */
+
+#define MOUSE_EVENT_LBUTTON 0x01
+#define MOUSE_EVENT_RBUTTON 0x02
+#define MOUSE_EVENT_MBUTTON 0x04
+
+typedef void QEMUPutKBDEvent(void *opaque, int keycode);
+typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
+
+typedef struct QEMUPutMouseEntry {
+ QEMUPutMouseEvent *qemu_put_mouse_event;
+ void *qemu_put_mouse_event_opaque;
+ int qemu_put_mouse_event_absolute;
+ char *qemu_put_mouse_event_name;
+
+ /* used internally by qemu for handling mice */
+ struct QEMUPutMouseEntry *next;
+} QEMUPutMouseEntry;
+
+void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
+QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
+ void *opaque, int absolute,
+ const char *name);
+void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
+
+void kbd_put_keycode(int keycode);
+void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
+int kbd_mouse_is_absolute(void);
+
+void do_info_mice(void);
+void do_mouse_set(int index);
+
+/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
+ constants) */
+#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
+#define QEMU_KEY_BACKSPACE 0x007f
+#define QEMU_KEY_UP QEMU_KEY_ESC1('A')
+#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
+#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
+#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
+#define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
+#define QEMU_KEY_END QEMU_KEY_ESC1(4)
+#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
+#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
+#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
+
+#define QEMU_KEY_CTRL_UP 0xe400
+#define QEMU_KEY_CTRL_DOWN 0xe401
+#define QEMU_KEY_CTRL_LEFT 0xe402
+#define QEMU_KEY_CTRL_RIGHT 0xe403
+#define QEMU_KEY_CTRL_HOME 0xe404
+#define QEMU_KEY_CTRL_END 0xe405
+#define QEMU_KEY_CTRL_PAGEUP 0xe406
+#define QEMU_KEY_CTRL_PAGEDOWN 0xe407
+
+void kbd_put_keysym(int keysym);
+
+/* consoles */
+
+struct DisplayState {
+ uint8_t *data;
+ int linesize;
+ int depth;
+ int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
+ int width;
+ int height;
+ void *opaque;
+ struct QEMUTimer *gui_timer;
+
+ void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
+ void (*dpy_resize)(struct DisplayState *s, int w, int h);
+ void (*dpy_refresh)(struct DisplayState *s);
+ void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
+ int dst_x, int dst_y, int w, int h);
+ void (*dpy_fill)(struct DisplayState *s, int x, int y,
+ int w, int h, uint32_t c);
+ void (*mouse_set)(int x, int y, int on);
+ void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
+ uint8_t *image, uint8_t *mask);
+};
+
+static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
+{
+ s->dpy_update(s, x, y, w, h);
+}
+
+static inline void dpy_resize(DisplayState *s, int w, int h)
+{
+ s->dpy_resize(s, w, h);
+}
+
+typedef void (*vga_hw_update_ptr)(void *);
+typedef void (*vga_hw_invalidate_ptr)(void *);
+typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
+
+TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
+ vga_hw_invalidate_ptr invalidate,
+ vga_hw_screen_dump_ptr screen_dump,
+ void *opaque);
+void vga_hw_update(void);
+void vga_hw_invalidate(void);
+void vga_hw_screen_dump(const char *filename);
+
+int is_graphic_console(void);
+CharDriverState *text_console_init(DisplayState *ds, const char *p);
+void console_select(unsigned int index);
+void console_color_init(DisplayState *ds);
+
+/* sdl.c */
+void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
+
+/* cocoa.m */
+void cocoa_display_init(DisplayState *ds, int full_screen);
+
+/* vnc.c */
+void vnc_display_init(DisplayState *ds);
+void vnc_display_close(DisplayState *ds);
+int vnc_display_open(DisplayState *ds, const char *display);
+int vnc_display_password(DisplayState *ds, const char *password);
+void do_info_vnc(void);
+
+/* x_keymap.c */
+extern uint8_t _translate_keycode(const int key);
+
+/* FIXME: term_printf et al should probably go elsewhere so everything
+ does not need to include console.h */
+/* monitor.c */
+void monitor_init(CharDriverState *hd, int show_banner);
+void term_puts(const char *str);
+void term_vprintf(const char *fmt, va_list ap);
+void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
+void term_print_filename(const char *filename);
+void term_flush(void);
+void term_print_help(void);
+void monitor_readline(const char *prompt, int is_password,
+ char *buf, int buf_size);
+
+/* readline.c */
+typedef void ReadLineFunc(void *opaque, const char *str);
+
+extern int completion_index;
+void add_completion(const char *str);
+void readline_handle_byte(int ch);
+void readline_find_completion(const char *cmdline);
+const char *readline_get_history(unsigned int index);
+void readline_start(const char *prompt, int is_password,
+ ReadLineFunc *readline_func, void *opaque);
+void readline_history_save(void);
+void readline_history_restore(void);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/cpu-all.h
===================================================================
--- trunk/src/host/qemu-neo1973/cpu-all.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/cpu-all.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -690,7 +690,6 @@
void page_dump(FILE *f);
int page_get_flags(target_ulong address);
void page_set_flags(target_ulong start, target_ulong end, int flags);
-void page_unprotect_range(target_ulong data, target_ulong data_size);
int page_check_range(target_ulong start, target_ulong len, int flags);
CPUState *cpu_copy(CPUState *env);
Modified: trunk/src/host/qemu-neo1973/cpu-defs.h
===================================================================
--- trunk/src/host/qemu-neo1973/cpu-defs.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/cpu-defs.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -20,6 +20,10 @@
#ifndef CPU_DEFS_H
#define CPU_DEFS_H
+#ifndef NEED_CPU_H
+#error cpu.h included from common code
+#endif
+
#include "config.h"
#include <setjmp.h>
#include <inttypes.h>
Modified: trunk/src/host/qemu-neo1973/darwin-user/main.c
===================================================================
--- trunk/src/host/qemu-neo1973/darwin-user/main.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/darwin-user/main.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -386,7 +386,6 @@
cpu_abort(env, "Reset interrupt while in user mode. "
"Aborting\n");
break;
-#if defined(TARGET_PPC64) /* PowerPC 64 */
case POWERPC_EXCP_DSEG: /* Data segment exception */
cpu_abort(env, "Data segment exception while in user mode. "
"Aborting\n");
@@ -395,19 +394,15 @@
cpu_abort(env, "Instruction segment exception "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64) */
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
cpu_abort(env, "Hypervisor decrementer interrupt "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_TRACE: /* Trace exception */
/* Nothing to do:
* we use this exception to emulate step-by-step execution mode.
*/
break;
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
cpu_abort(env, "Hypervisor data storage exception "
"while in user mode. Aborting\n");
@@ -424,7 +419,6 @@
cpu_abort(env, "Hypervisor instruction segment exception "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
EXCP_DUMP(env, "No Altivec instructions allowed\n");
info.si_signo = SIGILL;
@@ -840,6 +834,15 @@
} else
if (!strcmp(r, "g")) {
use_gdbstub = 1;
+ } else if (!strcmp(r, "cpu")) {
+ cpu_model = argv[optind++];
+ if (strcmp(cpu_model, "?") == 0) {
+/* XXX: implement xxx_cpu_list for targets that still miss it */
+#if defined(cpu_list)
+ cpu_list(stdout, &fprintf);
+#endif
+ _exit(1);
+ }
} else
{
usage();
@@ -852,16 +855,26 @@
/* Zero out regs */
memset(regs, 0, sizeof(struct target_pt_regs));
- /* NOTE: we need to init the CPU at this stage to get
- qemu_host_page_size */
+ if (cpu_model == NULL) {
#if defined(TARGET_I386)
- cpu_model = "qemu32";
+#ifdef TARGET_X86_64
+ cpu_model = "qemu64";
+#else
+ cpu_model = "qemu32";
+#endif
#elif defined(TARGET_PPC)
- cpu_model = "750";
+#ifdef TARGET_PPC64
+ cpu_model = "970";
#else
+ cpu_model = "750";
+#endif
+#else
#error unsupported CPU
#endif
+ }
+ /* NOTE: we need to init the CPU at this stage to get
+ qemu_host_page_size */
env = cpu_init(cpu_model);
printf("Starting %s with qemu\n----------------\n", filename);
@@ -1003,6 +1016,14 @@
#elif defined(TARGET_PPC)
{
int i;
+
+#if defined(TARGET_PPC64)
+#if defined(TARGET_ABI32)
+ env->msr &= ~((target_ulong)1 << MSR_SF);
+#else
+ env->msr |= (target_ulong)1 << MSR_SF;
+#endif
+#endif
env->nip = regs->nip;
for(i = 0; i < 32; i++) {
env->gpr[i] = regs->gpr[i];
Modified: trunk/src/host/qemu-neo1973/darwin-user/qemu.h
===================================================================
--- trunk/src/host/qemu-neo1973/darwin-user/qemu.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/darwin-user/qemu.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,13 +1,13 @@
#ifndef GEMU_H
#define GEMU_H
-#include "thunk.h"
-
#include <signal.h>
#include <string.h>
#include "cpu.h"
+#include "thunk.h"
+
#include "gdbstub.h"
typedef siginfo_t target_siginfo_t;
Modified: trunk/src/host/qemu-neo1973/dyngen-exec.h
===================================================================
--- trunk/src/host/qemu-neo1973/dyngen-exec.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/dyngen-exec.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -38,7 +38,7 @@
// Linux/Sparc64 defines uint64_t
#if !(defined (__sparc_v9__) && defined(__linux__))
/* XXX may be done for all 64 bits targets ? */
-#if defined (__x86_64__) || defined(__ia64)
+#if defined (__x86_64__) || defined(__ia64) || defined(__s390x__)
typedef unsigned long uint64_t;
#else
typedef unsigned long long uint64_t;
@@ -55,7 +55,7 @@
typedef signed int int32_t;
// Linux/Sparc64 defines int64_t
#if !(defined (__sparc_v9__) && defined(__linux__))
-#if defined (__x86_64__) || defined(__ia64)
+#if defined (__x86_64__) || defined(__ia64) || defined(__s390x__)
typedef signed long int64_t;
#else
typedef signed long long int64_t;
@@ -205,7 +205,7 @@
#define stringify(s) tostring(s)
#define tostring(s) #s
-#ifdef __alpha__
+#if defined(__alpha__) || defined(__s390__)
/* the symbols are considered non exported so a br immediate is generated */
#define __hidden __attribute__((visibility("hidden")))
#else
@@ -224,6 +224,13 @@
#define PARAM1 ({ int _r; asm("" : "=r"(_r) : "0" (&__op_param1)); _r; })
#define PARAM2 ({ int _r; asm("" : "=r"(_r) : "0" (&__op_param2)); _r; })
#define PARAM3 ({ int _r; asm("" : "=r"(_r) : "0" (&__op_param3)); _r; })
+#elif defined(__s390__)
+extern int __op_param1 __hidden;
+extern int __op_param2 __hidden;
+extern int __op_param3 __hidden;
+#define PARAM1 ({ int _r; asm("bras %0,8; .long " ASM_NAME(__op_param1) "; l %0,0(%0)" : "=r"(_r) : ); _r; })
+#define PARAM2 ({ int _r; asm("bras %0,8; .long " ASM_NAME(__op_param2) "; l %0,0(%0)" : "=r"(_r) : ); _r; })
+#define PARAM3 ({ int _r; asm("bras %0,8; .long " ASM_NAME(__op_param3) "; l %0,0(%0)" : "=r"(_r) : ); _r; })
#else
#if defined(__APPLE__)
static int __op_param1, __op_param2, __op_param3;
@@ -254,7 +261,7 @@
#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n)
#elif defined(__s390__)
#define EXIT_TB() asm volatile ("br %r14")
-#define GOTO_LABEL_PARAM(n) asm volatile ("bras %r7,8; .long " ASM_NAME(__op_gen_label) #n "; l %r7, 0(%r7); br %r7")
+#define GOTO_LABEL_PARAM(n) asm volatile ("larl %r7,12; l %r7,0(%r7); br %r7; .long " ASM_NAME(__op_gen_label) #n)
#elif defined(__alpha__)
#define EXIT_TB() asm volatile ("ret")
#elif defined(__ia64__)
Modified: trunk/src/host/qemu-neo1973/dyngen.c
===================================================================
--- trunk/src/host/qemu-neo1973/dyngen.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/dyngen.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -232,7 +232,7 @@
int do_swap;
-void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
+static void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
@@ -243,7 +243,7 @@
exit(1);
}
-void *load_data(int fd, long offset, unsigned int size)
+static void *load_data(int fd, long offset, unsigned int size)
{
char *data;
@@ -1495,8 +1495,8 @@
p = (void *)(p_end - 2);
if (p == p_start)
error("empty code for %s", name);
- if (get16((uint16_t *)p) != 0x07fe && get16((uint16_t *)p) != 0x07f4)
- error("br %%r14 expected at the end of %s", name);
+ if ((get16((uint16_t *)p) & 0xfff0) != 0x07f0)
+ error("br expected at the end of %s", name);
copy_size = p - p_start;
}
#elif defined(HOST_ALPHA)
@@ -2120,6 +2120,19 @@
fprintf(outfile, " *(uint8_t *)(gen_code_ptr + %d) = %s + %d;\n",
reloc_offset, relname, addend);
break;
+ case R_390_PC32DBL:
+ if (ELF32_ST_TYPE(symtab[ELFW(R_SYM)(rel->r_info)].st_info) == STT_SECTION) {
+ fprintf(outfile,
+ " *(uint32_t *)(gen_code_ptr + %d) += "
+ "((long)&%s - (long)gen_code_ptr) >> 1;\n",
+ reloc_offset, name);
+ }
+ else
+ fprintf(outfile,
+ " *(uint32_t *)(gen_code_ptr + %d) = "
+ "(%s + %d - ((uint32_t)gen_code_ptr + %d)) >> 1;\n",
+ reloc_offset, relname, addend, reloc_offset);
+ break;
default:
error("unsupported s390 relocation (%d)", type);
}
Modified: trunk/src/host/qemu-neo1973/dyngen.h
===================================================================
--- trunk/src/host/qemu-neo1973/dyngen.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/dyngen.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -45,7 +45,7 @@
#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
unsigned long p;
@@ -68,7 +68,7 @@
asm ("imb");
}
#elif defined(__sparc__)
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
unsigned long p;
Modified: trunk/src/host/qemu-neo1973/elf_ops.h
===================================================================
--- trunk/src/host/qemu-neo1973/elf_ops.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/elf_ops.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -138,9 +138,9 @@
return -1;
}
-int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
- int must_swab, uint64_t *pentry,
- uint64_t *lowaddr, uint64_t *highaddr)
+static int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
+ int must_swab, uint64_t *pentry,
+ uint64_t *lowaddr, uint64_t *highaddr)
{
struct elfhdr ehdr;
struct elf_phdr *phdr = NULL, *ph;
Modified: trunk/src/host/qemu-neo1973/exec-all.h
===================================================================
--- trunk/src/host/qemu-neo1973/exec-all.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/exec-all.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,36 +21,6 @@
/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS
-#ifndef glue
-#define xglue(x, y) x ## y
-#define glue(x, y) xglue(x, y)
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-#endif
-
-#ifndef likely
-#if __GNUC__ < 3
-#define __builtin_expect(x, n) (x)
-#endif
-
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#endif
-
-#ifndef always_inline
-#if (__GNUC__ < 3) || defined(__APPLE__)
-#define always_inline inline
-#else
-#define always_inline __attribute__ (( always_inline )) inline
-#endif
-#endif
-
-#ifdef __i386__
-#define REGPARM(n) __attribute((regparm(n)))
-#else
-#define REGPARM(n)
-#endif
-
/* is_jmp field values */
#define DISAS_NEXT 0 /* next instruction can be analyzed */
#define DISAS_JUMP 1 /* only pc was modified dynamically */
@@ -350,24 +320,6 @@
"1:\n");\
} while (0)
-#elif defined(__s390__)
-/* GCC spills R13, so we have to restore it before branching away */
-
-#define GOTO_TB(opname, tbparam, n)\
-do {\
- static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
- static void __attribute__((used)) *__op_label ## n \
- __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
- __asm__ __volatile__ ( \
- "l %%r13,52(%%r15)\n" \
- "br %0\n" \
- : : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\
- \
- for(;*((int*)0);); /* just to keep GCC busy */ \
-label ## n: ;\
-dummy_label ## n: ;\
-} while(0)
-
#else
/* jump to next block operations (more portable code, does not need
Modified: trunk/src/host/qemu-neo1973/exec.c
===================================================================
--- trunk/src/host/qemu-neo1973/exec.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/exec.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1894,10 +1894,19 @@
if( !(p->flags & PAGE_VALID) )
return -1;
- if (!(p->flags & PAGE_READ) && (flags & PAGE_READ) )
+ if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
return -1;
- if (!(p->flags & PAGE_WRITE) && (flags & PAGE_WRITE) )
- return -1;
+ if (flags & PAGE_WRITE) {
+ if (!(p->flags & PAGE_WRITE_ORG))
+ return -1;
+ /* unprotect the page if it was put read-only because it
+ contains translated code */
+ if (!(p->flags & PAGE_WRITE)) {
+ if (!page_unprotect(addr, 0, NULL))
+ return -1;
+ }
+ return 0;
+ }
}
return 0;
}
@@ -1942,21 +1951,6 @@
return 0;
}
-/* call this function when system calls directly modify a memory area */
-/* ??? This should be redundant now we have lock_user. */
-void page_unprotect_range(target_ulong data, target_ulong data_size)
-{
- target_ulong start, end, addr;
-
- start = data;
- end = start + data_size;
- start &= TARGET_PAGE_MASK;
- end = TARGET_PAGE_ALIGN(end);
- for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
- page_unprotect(addr, 0, NULL);
- }
-}
-
static inline void tlb_set_dirty(CPUState *env,
unsigned long addr, target_ulong vaddr)
{
Modified: trunk/src/host/qemu-neo1973/fpu/softfloat-specialize.h
===================================================================
--- trunk/src/host/qemu-neo1973/fpu/softfloat-specialize.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/fpu/softfloat-specialize.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -30,6 +30,12 @@
=============================================================================*/
+#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+#define SNAN_BIT_IS_ONE 1
+#else
+#define SNAN_BIT_IS_ONE 0
+#endif
+
/*----------------------------------------------------------------------------
| Underflow tininess-detection mode, statically initialized to default value.
| (The declaration in `softfloat.h' must match the `int8' type here.)
@@ -45,9 +51,7 @@
void float_raise( int8 flags STATUS_PARAM )
{
-
STATUS(float_exception_flags) |= flags;
-
}
/*----------------------------------------------------------------------------
@@ -61,20 +65,21 @@
/*----------------------------------------------------------------------------
| The pattern for a default generated single-precision NaN.
*----------------------------------------------------------------------------*/
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
-#define float32_default_nan 0xFF800000
+#if SNAN_BIT_IS_ONE
+#define float32_default_nan make_float32(0x7FBFFFFF)
#else
-#define float32_default_nan 0xFFC00000
+#define float32_default_nan make_float32(0xFFC00000)
#endif
/*----------------------------------------------------------------------------
-| Returns 1 if the single-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
+| Returns 1 if the single-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float32_is_nan( float32 a )
+int float32_is_nan( float32 a_ )
{
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+ uint32_t a = float32_val(a_);
+#if SNAN_BIT_IS_ONE
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
#else
return ( 0xFF800000 <= (bits32) ( a<<1 ) );
@@ -86,9 +91,10 @@
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float32_is_signaling_nan( float32 a )
+int float32_is_signaling_nan( float32 a_ )
{
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+ uint32_t a = float32_val(a_);
+#if SNAN_BIT_IS_ONE
return ( 0xFF800000 <= (bits32) ( a<<1 ) );
#else
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
@@ -106,11 +112,10 @@
commonNaNT z;
if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR );
- z.sign = a>>31;
+ z.sign = float32_val(a)>>31;
z.low = 0;
- z.high = ( (bits64) a )<<41;
+ z.high = ( (bits64) float32_val(a) )<<41;
return z;
-
}
/*----------------------------------------------------------------------------
@@ -120,9 +125,8 @@
static float32 commonNaNToFloat32( commonNaNT a )
{
-
- return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
-
+ return make_float32(
+ ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 ) );
}
/*----------------------------------------------------------------------------
@@ -134,53 +138,63 @@
static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
{
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+ bits32 av, bv, res;
aIsNaN = float32_is_nan( a );
aIsSignalingNaN = float32_is_signaling_nan( a );
bIsNaN = float32_is_nan( b );
bIsSignalingNaN = float32_is_signaling_nan( b );
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
- a &= ~0x00400000;
- b &= ~0x00400000;
+ av = float32_val(a);
+ bv = float32_val(b);
+#if SNAN_BIT_IS_ONE
+ av &= ~0x00400000;
+ bv &= ~0x00400000;
#else
- a |= 0x00400000;
- b |= 0x00400000;
+ av |= 0x00400000;
+ bv |= 0x00400000;
#endif
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
if ( aIsSignalingNaN ) {
if ( bIsSignalingNaN ) goto returnLargerSignificand;
- return bIsNaN ? b : a;
+ res = bIsNaN ? bv : av;
}
else if ( aIsNaN ) {
- if ( bIsSignalingNaN | ! bIsNaN ) return a;
+ if ( bIsSignalingNaN | ! bIsNaN )
+ res = av;
+ else {
returnLargerSignificand:
- if ( (bits32) ( a<<1 ) < (bits32) ( b<<1 ) ) return b;
- if ( (bits32) ( b<<1 ) < (bits32) ( a<<1 ) ) return a;
- return ( a < b ) ? a : b;
+ if ( (bits32) ( av<<1 ) < (bits32) ( bv<<1 ) )
+ res = bv;
+ else if ( (bits32) ( bv<<1 ) < (bits32) ( av<<1 ) )
+ res = av;
+ else
+ res = ( av < bv ) ? av : bv;
+ }
}
else {
- return b;
+ res = bv;
}
-
+ return make_float32(res);
}
/*----------------------------------------------------------------------------
| The pattern for a default generated double-precision NaN.
*----------------------------------------------------------------------------*/
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
-#define float64_default_nan LIT64( 0xFFF0000000000000 )
+#if SNAN_BIT_IS_ONE
+#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
#else
-#define float64_default_nan LIT64( 0xFFF8000000000000 )
+#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
#endif
/*----------------------------------------------------------------------------
-| Returns 1 if the double-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
+| Returns 1 if the double-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float64_is_nan( float64 a )
+int float64_is_nan( float64 a_ )
{
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+ bits64 a = float64_val(a_);
+#if SNAN_BIT_IS_ONE
return
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
&& ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
@@ -194,9 +208,10 @@
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float64_is_signaling_nan( float64 a )
+int float64_is_signaling_nan( float64 a_ )
{
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+ bits64 a = float64_val(a_);
+#if SNAN_BIT_IS_ONE
return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) );
#else
return
@@ -216,11 +231,10 @@
commonNaNT z;
if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR);
- z.sign = a>>63;
+ z.sign = float64_val(a)>>63;
z.low = 0;
- z.high = a<<12;
+ z.high = float64_val(a)<<12;
return z;
-
}
/*----------------------------------------------------------------------------
@@ -230,12 +244,10 @@
static float64 commonNaNToFloat64( commonNaNT a )
{
-
- return
+ return make_float64(
( ( (bits64) a.sign )<<63 )
| LIT64( 0x7FF8000000000000 )
- | ( a.high>>12 );
-
+ | ( a.high>>12 ));
}
/*----------------------------------------------------------------------------
@@ -247,34 +259,43 @@
static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
{
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+ bits64 av, bv, res;
aIsNaN = float64_is_nan( a );
aIsSignalingNaN = float64_is_signaling_nan( a );
bIsNaN = float64_is_nan( b );
bIsSignalingNaN = float64_is_signaling_nan( b );
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
- a &= ~LIT64( 0x0008000000000000 );
- b &= ~LIT64( 0x0008000000000000 );
+ av = float64_val(a);
+ bv = float64_val(b);
+#if SNAN_BIT_IS_ONE
+ av &= ~LIT64( 0x0008000000000000 );
+ bv &= ~LIT64( 0x0008000000000000 );
#else
- a |= LIT64( 0x0008000000000000 );
- b |= LIT64( 0x0008000000000000 );
+ av |= LIT64( 0x0008000000000000 );
+ bv |= LIT64( 0x0008000000000000 );
#endif
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
if ( aIsSignalingNaN ) {
if ( bIsSignalingNaN ) goto returnLargerSignificand;
- return bIsNaN ? b : a;
+ res = bIsNaN ? bv : av;
}
else if ( aIsNaN ) {
- if ( bIsSignalingNaN | ! bIsNaN ) return a;
+ if ( bIsSignalingNaN | ! bIsNaN )
+ res = av;
+ else {
returnLargerSignificand:
- if ( (bits64) ( a<<1 ) < (bits64) ( b<<1 ) ) return b;
- if ( (bits64) ( b<<1 ) < (bits64) ( a<<1 ) ) return a;
- return ( a < b ) ? a : b;
+ if ( (bits64) ( av<<1 ) < (bits64) ( bv<<1 ) )
+ res = bv;
+ else if ( (bits64) ( bv<<1 ) < (bits64) ( av<<1 ) )
+ res = av;
+ else
+ res = ( av < bv ) ? av : bv;
+ }
}
else {
- return b;
+ res = bv;
}
-
+ return make_float64(res);
}
#ifdef FLOATX80
@@ -284,19 +305,32 @@
| `high' and `low' values hold the most- and least-significant bits,
| respectively.
*----------------------------------------------------------------------------*/
+#if SNAN_BIT_IS_ONE
+#define floatx80_default_nan_high 0x7FFF
+#define floatx80_default_nan_low LIT64( 0xBFFFFFFFFFFFFFFF )
+#else
#define floatx80_default_nan_high 0xFFFF
#define floatx80_default_nan_low LIT64( 0xC000000000000000 )
+#endif
/*----------------------------------------------------------------------------
| Returns 1 if the extended double-precision floating-point value `a' is a
-| NaN; otherwise returns 0.
+| quiet NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
int floatx80_is_nan( floatx80 a )
{
+#if SNAN_BIT_IS_ONE
+ bits64 aLow;
+ aLow = a.low & ~ LIT64( 0x4000000000000000 );
+ return
+ ( ( a.high & 0x7FFF ) == 0x7FFF )
+ && (bits64) ( aLow<<1 )
+ && ( a.low == aLow );
+#else
return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
-
+#endif
}
/*----------------------------------------------------------------------------
@@ -306,6 +340,9 @@
int floatx80_is_signaling_nan( floatx80 a )
{
+#if SNAN_BIT_IS_ONE
+ return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
+#else
bits64 aLow;
aLow = a.low & ~ LIT64( 0x4000000000000000 );
@@ -313,7 +350,7 @@
( ( a.high & 0x7FFF ) == 0x7FFF )
&& (bits64) ( aLow<<1 )
&& ( a.low == aLow );
-
+#endif
}
/*----------------------------------------------------------------------------
@@ -331,7 +368,6 @@
z.low = 0;
z.high = a.low<<1;
return z;
-
}
/*----------------------------------------------------------------------------
@@ -346,7 +382,6 @@
z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
return z;
-
}
/*----------------------------------------------------------------------------
@@ -363,8 +398,13 @@
aIsSignalingNaN = floatx80_is_signaling_nan( a );
bIsNaN = floatx80_is_nan( b );
bIsSignalingNaN = floatx80_is_signaling_nan( b );
+#if SNAN_BIT_IS_ONE
+ a.low &= ~LIT64( 0xC000000000000000 );
+ b.low &= ~LIT64( 0xC000000000000000 );
+#else
a.low |= LIT64( 0xC000000000000000 );
b.low |= LIT64( 0xC000000000000000 );
+#endif
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
if ( aIsSignalingNaN ) {
if ( bIsSignalingNaN ) goto returnLargerSignificand;
@@ -380,7 +420,6 @@
else {
return b;
}
-
}
#endif
@@ -391,21 +430,30 @@
| The pattern for a default generated quadruple-precision NaN. The `high' and
| `low' values hold the most- and least-significant bits, respectively.
*----------------------------------------------------------------------------*/
+#if SNAN_BIT_IS_ONE
+#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
+#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
+#else
#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
#define float128_default_nan_low LIT64( 0x0000000000000000 )
+#endif
/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
+| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
int float128_is_nan( float128 a )
{
-
+#if SNAN_BIT_IS_ONE
return
+ ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
+ && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
+#else
+ return
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
-
+#endif
}
/*----------------------------------------------------------------------------
@@ -415,11 +463,15 @@
int float128_is_signaling_nan( float128 a )
{
-
+#if SNAN_BIT_IS_ONE
return
+ ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
+ && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
+#else
+ return
( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
&& ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
-
+#endif
}
/*----------------------------------------------------------------------------
@@ -436,7 +488,6 @@
z.sign = a.high>>63;
shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
return z;
-
}
/*----------------------------------------------------------------------------
@@ -451,7 +502,6 @@
shift128Right( a.high, a.low, 16, &z.high, &z.low );
z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );
return z;
-
}
/*----------------------------------------------------------------------------
@@ -468,8 +518,13 @@
aIsSignalingNaN = float128_is_signaling_nan( a );
bIsNaN = float128_is_nan( b );
bIsSignalingNaN = float128_is_signaling_nan( b );
+#if SNAN_BIT_IS_ONE
+ a.high &= ~LIT64( 0x0000800000000000 );
+ b.high &= ~LIT64( 0x0000800000000000 );
+#else
a.high |= LIT64( 0x0000800000000000 );
b.high |= LIT64( 0x0000800000000000 );
+#endif
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
if ( aIsSignalingNaN ) {
if ( bIsSignalingNaN ) goto returnLargerSignificand;
@@ -485,8 +540,6 @@
else {
return b;
}
-
}
#endif
-
Modified: trunk/src/host/qemu-neo1973/fpu/softfloat.c
===================================================================
--- trunk/src/host/qemu-neo1973/fpu/softfloat.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/fpu/softfloat.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -175,7 +175,7 @@
INLINE bits32 extractFloat32Frac( float32 a )
{
- return a & 0x007FFFFF;
+ return float32_val(a) & 0x007FFFFF;
}
@@ -186,7 +186,7 @@
INLINE int16 extractFloat32Exp( float32 a )
{
- return ( a>>23 ) & 0xFF;
+ return ( float32_val(a)>>23 ) & 0xFF;
}
@@ -197,7 +197,7 @@
INLINE flag extractFloat32Sign( float32 a )
{
- return a>>31;
+ return float32_val(a)>>31;
}
@@ -233,7 +233,8 @@
INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )
{
- return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;
+ return make_float32(
+ ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig);
}
@@ -290,7 +291,7 @@
&& ( (sbits32) ( zSig + roundIncrement ) < 0 ) )
) {
float_raise( float_flag_overflow | float_flag_inexact STATUS_VAR);
- return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );
+ return packFloat32( zSign, 0xFF, - ( roundIncrement == 0 ));
}
if ( zExp < 0 ) {
isTiny =
@@ -337,7 +338,7 @@
INLINE bits64 extractFloat64Frac( float64 a )
{
- return a & LIT64( 0x000FFFFFFFFFFFFF );
+ return float64_val(a) & LIT64( 0x000FFFFFFFFFFFFF );
}
@@ -348,7 +349,7 @@
INLINE int16 extractFloat64Exp( float64 a )
{
- return ( a>>52 ) & 0x7FF;
+ return ( float64_val(a)>>52 ) & 0x7FF;
}
@@ -359,7 +360,7 @@
INLINE flag extractFloat64Sign( float64 a )
{
- return a>>63;
+ return float64_val(a)>>63;
}
@@ -395,7 +396,8 @@
INLINE float64 packFloat64( flag zSign, int16 zExp, bits64 zSig )
{
- return ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig;
+ return make_float64(
+ ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig);
}
@@ -452,7 +454,7 @@
&& ( (sbits64) ( zSig + roundIncrement ) < 0 ) )
) {
float_raise( float_flag_overflow | float_flag_inexact STATUS_VAR);
- return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );
+ return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 ));
}
if ( zExp < 0 ) {
isTiny =
@@ -1050,7 +1052,7 @@
{
flag zSign;
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float32_zero;
if ( a == (sbits32) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
zSign = ( a < 0 );
return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a STATUS_VAR );
@@ -1070,7 +1072,7 @@
int8 shiftCount;
bits64 zSig;
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float64_zero;
zSign = ( a < 0 );
absA = zSign ? - a : a;
shiftCount = countLeadingZeros32( absA ) + 21;
@@ -1144,7 +1146,7 @@
uint64 absA;
int8 shiftCount;
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float32_zero;
zSign = ( a < 0 );
absA = zSign ? - a : a;
shiftCount = countLeadingZeros64( absA ) - 40;
@@ -1168,7 +1170,7 @@
{
int8 shiftCount;
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float32_zero;
shiftCount = countLeadingZeros64( a ) - 40;
if ( 0 <= shiftCount ) {
return packFloat32( 1 > 0, 0x95 - shiftCount, a<<shiftCount );
@@ -1195,7 +1197,7 @@
{
flag zSign;
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float64_zero;
if ( a == (sbits64) LIT64( 0x8000000000000000 ) ) {
return packFloat64( 1, 0x43E, 0 );
}
@@ -1206,7 +1208,7 @@
float64 uint64_to_float64( uint64 a STATUS_PARAM )
{
- if ( a == 0 ) return 0;
+ if ( a == 0 ) return float64_zero;
return normalizeRoundAndPackFloat64( 0, 0x43C, a STATUS_VAR );
}
@@ -1325,7 +1327,7 @@
aSign = extractFloat32Sign( a );
shiftCount = aExp - 0x9E;
if ( 0 <= shiftCount ) {
- if ( a != 0xCF000000 ) {
+ if ( float32_val(a) != 0xCF000000 ) {
float_raise( float_flag_invalid STATUS_VAR);
if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;
}
@@ -1404,7 +1406,7 @@
aSign = extractFloat32Sign( a );
shiftCount = aExp - 0xBE;
if ( 0 <= shiftCount ) {
- if ( a != 0xDF000000 ) {
+ if ( float32_val(a) != 0xDF000000 ) {
float_raise( float_flag_invalid STATUS_VAR);
if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {
return LIT64( 0x7FFFFFFFFFFFFFFF );
@@ -1535,7 +1537,7 @@
int16 aExp;
bits32 lastBitMask, roundBitsMask;
int8 roundingMode;
- float32 z;
+ bits32 z;
aExp = extractFloat32Exp( a );
if ( 0x96 <= aExp ) {
@@ -1545,7 +1547,7 @@
return a;
}
if ( aExp <= 0x7E ) {
- if ( (bits32) ( a<<1 ) == 0 ) return a;
+ if ( (bits32) ( float32_val(a)<<1 ) == 0 ) return a;
STATUS(float_exception_flags) |= float_flag_inexact;
aSign = extractFloat32Sign( a );
switch ( STATUS(float_rounding_mode) ) {
@@ -1555,29 +1557,29 @@
}
break;
case float_round_down:
- return aSign ? 0xBF800000 : 0;
+ return make_float32(aSign ? 0xBF800000 : 0);
case float_round_up:
- return aSign ? 0x80000000 : 0x3F800000;
+ return make_float32(aSign ? 0x80000000 : 0x3F800000);
}
return packFloat32( aSign, 0, 0 );
}
lastBitMask = 1;
lastBitMask <<= 0x96 - aExp;
roundBitsMask = lastBitMask - 1;
- z = a;
+ z = float32_val(a);
roundingMode = STATUS(float_rounding_mode);
if ( roundingMode == float_round_nearest_even ) {
z += lastBitMask>>1;
if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
}
else if ( roundingMode != float_round_to_zero ) {
- if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {
+ if ( extractFloat32Sign( make_float32(z) ) ^ ( roundingMode == float_round_up ) ) {
z += roundBitsMask;
}
}
z &= ~ roundBitsMask;
- if ( z != a ) STATUS(float_exception_flags) |= float_flag_inexact;
- return z;
+ if ( z != float32_val(a) ) STATUS(float_exception_flags) |= float_flag_inexact;
+ return make_float32(z);
}
@@ -2008,7 +2010,7 @@
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
if ( aExp == 0xFF ) {
- if ( aSig ) return propagateFloat32NaN( a, 0 STATUS_VAR );
+ if ( aSig ) return propagateFloat32NaN( a, float32_zero STATUS_VAR );
if ( ! aSign ) return a;
float_raise( float_flag_invalid STATUS_VAR);
return float32_default_nan;
@@ -2019,7 +2021,7 @@
return float32_default_nan;
}
if ( aExp == 0 ) {
- if ( aSig == 0 ) return 0;
+ if ( aSig == 0 ) return float32_zero;
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
}
zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;
@@ -2062,7 +2064,8 @@
}
return 0;
}
- return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
+ return ( float32_val(a) == float32_val(b) ) ||
+ ( (bits32) ( ( float32_val(a) | float32_val(b) )<<1 ) == 0 );
}
@@ -2076,6 +2079,7 @@
int float32_le( float32 a, float32 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits32 av, bv;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
@@ -2085,8 +2089,10 @@
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
- if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
- return ( a == b ) || ( aSign ^ ( a < b ) );
+ av = float32_val(a);
+ bv = float32_val(b);
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
}
@@ -2099,6 +2105,7 @@
int float32_lt( float32 a, float32 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits32 av, bv;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
@@ -2108,8 +2115,10 @@
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
- if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
- return ( a != b ) && ( aSign ^ ( a < b ) );
+ av = float32_val(a);
+ bv = float32_val(b);
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
}
@@ -2122,6 +2131,7 @@
int float32_eq_signaling( float32 a, float32 b STATUS_PARAM )
{
+ bits32 av, bv;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
@@ -2129,7 +2139,9 @@
float_raise( float_flag_invalid STATUS_VAR);
return 0;
}
- return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
+ av = float32_val(a);
+ bv = float32_val(b);
+ return ( av == bv ) || ( (bits32) ( ( av | bv )<<1 ) == 0 );
}
@@ -2143,6 +2155,7 @@
int float32_le_quiet( float32 a, float32 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits32 av, bv;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
@@ -2154,8 +2167,10 @@
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
- if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
- return ( a == b ) || ( aSign ^ ( a < b ) );
+ av = float32_val(a);
+ bv = float32_val(b);
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
}
@@ -2169,6 +2184,7 @@
int float32_lt_quiet( float32 a, float32 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits32 av, bv;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
@@ -2180,8 +2196,10 @@
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
- if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
- return ( a != b ) && ( aSign ^ ( a < b ) );
+ av = float32_val(a);
+ bv = float32_val(b);
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
}
@@ -2324,7 +2342,7 @@
shiftCount = aExp - 0x433;
if ( 0 <= shiftCount ) {
if ( 0x43E <= aExp ) {
- if ( a != LIT64( 0xC3E0000000000000 ) ) {
+ if ( float64_val(a) != LIT64( 0xC3E0000000000000 ) ) {
float_raise( float_flag_invalid STATUS_VAR);
if ( ! aSign
|| ( ( aExp == 0x7FF )
@@ -2464,7 +2482,7 @@
int16 aExp;
bits64 lastBitMask, roundBitsMask;
int8 roundingMode;
- float64 z;
+ bits64 z;
aExp = extractFloat64Exp( a );
if ( 0x433 <= aExp ) {
@@ -2474,7 +2492,7 @@
return a;
}
if ( aExp < 0x3FF ) {
- if ( (bits64) ( a<<1 ) == 0 ) return a;
+ if ( (bits64) ( float64_val(a)<<1 ) == 0 ) return a;
STATUS(float_exception_flags) |= float_flag_inexact;
aSign = extractFloat64Sign( a );
switch ( STATUS(float_rounding_mode) ) {
@@ -2484,30 +2502,31 @@
}
break;
case float_round_down:
- return aSign ? LIT64( 0xBFF0000000000000 ) : 0;
+ return make_float64(aSign ? LIT64( 0xBFF0000000000000 ) : 0);
case float_round_up:
- return
- aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 );
+ return make_float64(
+ aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 ));
}
return packFloat64( aSign, 0, 0 );
}
lastBitMask = 1;
lastBitMask <<= 0x433 - aExp;
roundBitsMask = lastBitMask - 1;
- z = a;
+ z = float64_val(a);
roundingMode = STATUS(float_rounding_mode);
if ( roundingMode == float_round_nearest_even ) {
z += lastBitMask>>1;
if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
}
else if ( roundingMode != float_round_to_zero ) {
- if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) {
+ if ( extractFloat64Sign( make_float64(z) ) ^ ( roundingMode == float_round_up ) ) {
z += roundBitsMask;
}
}
z &= ~ roundBitsMask;
- if ( z != a ) STATUS(float_exception_flags) |= float_flag_inexact;
- return z;
+ if ( z != float64_val(a) )
+ STATUS(float_exception_flags) |= float_flag_inexact;
+ return make_float64(z);
}
@@ -2951,7 +2970,7 @@
return float64_default_nan;
}
if ( aExp == 0 ) {
- if ( aSig == 0 ) return 0;
+ if ( aSig == 0 ) return float64_zero;
normalizeFloat64Subnormal( aSig, &aExp, &aSig );
}
zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;
@@ -2982,6 +3001,7 @@
int float64_eq( float64 a, float64 b STATUS_PARAM )
{
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -2991,7 +3011,9 @@
}
return 0;
}
- return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
+ av = float64_val(a);
+ bv = float64_val(a);
+ return ( av == bv ) || ( (bits64) ( ( av | bv )<<1 ) == 0 );
}
@@ -3005,6 +3027,7 @@
int float64_le( float64 a, float64 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -3014,8 +3037,10 @@
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
- if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
- return ( a == b ) || ( aSign ^ ( a < b ) );
+ av = float64_val(a);
+ bv = float64_val(a);
+ if ( aSign != bSign ) return aSign || ( (bits64) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
}
@@ -3028,6 +3053,7 @@
int float64_lt( float64 a, float64 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -3037,8 +3063,10 @@
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
- if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
- return ( a != b ) && ( aSign ^ ( a < b ) );
+ av = float64_val(a);
+ bv = float64_val(a);
+ if ( aSign != bSign ) return aSign && ( (bits64) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
}
@@ -3051,6 +3079,7 @@
int float64_eq_signaling( float64 a, float64 b STATUS_PARAM )
{
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -3058,7 +3087,9 @@
float_raise( float_flag_invalid STATUS_VAR);
return 0;
}
- return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
+ av = float64_val(a);
+ bv = float64_val(a);
+ return ( av == bv ) || ( (bits64) ( ( av | bv )<<1 ) == 0 );
}
@@ -3072,6 +3103,7 @@
int float64_le_quiet( float64 a, float64 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -3083,8 +3115,10 @@
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
- if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
- return ( a == b ) || ( aSign ^ ( a < b ) );
+ av = float64_val(a);
+ bv = float64_val(a);
+ if ( aSign != bSign ) return aSign || ( (bits64) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
}
@@ -3098,6 +3132,7 @@
int float64_lt_quiet( float64 a, float64 b STATUS_PARAM )
{
flag aSign, bSign;
+ bits64 av, bv;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
@@ -3109,8 +3144,10 @@
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
- if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
- return ( a != b ) && ( aSign ^ ( a < b ) );
+ av = float64_val(a);
+ bv = float64_val(a);
+ if ( aSign != bSign ) return aSign && ( (bits64) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
}
@@ -5310,12 +5347,14 @@
return res;
}
+/* FIXME: This looks broken. */
uint64_t float64_to_uint64 (float64 a STATUS_PARAM)
{
int64_t v;
- v = int64_to_float64(INT64_MIN STATUS_VAR);
- v = float64_to_int64((a + v) STATUS_VAR);
+ v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
+ v += float64_val(a);
+ v = float64_to_int64(make_float64(v) STATUS_VAR);
return v - INT64_MIN;
}
@@ -5324,8 +5363,9 @@
{
int64_t v;
- v = int64_to_float64(INT64_MIN STATUS_VAR);
- v = float64_to_int64_round_to_zero((a + v) STATUS_VAR);
+ v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
+ v += float64_val(a);
+ v = float64_to_int64_round_to_zero(make_float64(v) STATUS_VAR);
return v - INT64_MIN;
}
@@ -5335,6 +5375,7 @@
int is_quiet STATUS_PARAM ) \
{ \
flag aSign, bSign; \
+ bits ## s av, bv; \
\
if (( ( extractFloat ## s ## Exp( a ) == nan_exp ) && \
extractFloat ## s ## Frac( a ) ) || \
@@ -5349,18 +5390,20 @@
} \
aSign = extractFloat ## s ## Sign( a ); \
bSign = extractFloat ## s ## Sign( b ); \
+ av = float ## s ## _val(a); \
+ bv = float ## s ## _val(a); \
if ( aSign != bSign ) { \
- if ( (bits ## s) ( ( a | b )<<1 ) == 0 ) { \
+ if ( (bits ## s) ( ( av | bv )<<1 ) == 0 ) { \
/* zero case */ \
return float_relation_equal; \
} else { \
return 1 - (2 * aSign); \
} \
} else { \
- if (a == b) { \
+ if (av == bv) { \
return float_relation_equal; \
} else { \
- return 1 - 2 * (aSign ^ ( a < b )); \
+ return 1 - 2 * (aSign ^ ( av < bv )); \
} \
} \
} \
Modified: trunk/src/host/qemu-neo1973/fpu/softfloat.h
===================================================================
--- trunk/src/host/qemu-neo1973/fpu/softfloat.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/fpu/softfloat.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -111,8 +111,31 @@
/*----------------------------------------------------------------------------
| Software IEC/IEEE floating-point types.
*----------------------------------------------------------------------------*/
+/* Use structures for soft-float types. This prevents accidentally mixing
+ them with native int/float types. A sufficiently clever compiler and
+ sane ABI should be able to see though these structs. However
+ x86/gcc 3.x seems to struggle a bit, so leave them disabled by default. */
+//#define USE_SOFTFLOAT_STRUCT_TYPES
+#ifdef USE_SOFTFLOAT_STRUCT_TYPES
+typedef struct {
+ uint32_t v;
+} float32;
+/* The cast ensures an error if the wrong type is passed. */
+#define float32_val(x) (((float32)(x)).v)
+#define make_float32(x) __extension__ ({ float32 f32_val = {x}; f32_val; })
+typedef struct {
+ uint64_t v;
+} float64;
+#define float64_val(x) (((float64)(x)).v)
+#define make_float64(x) __extension__ ({ float64 f64_val = {x}; f64_val; })
+#else
typedef uint32_t float32;
typedef uint64_t float64;
+#define float32_val(x) (x)
+#define float64_val(x) (x)
+#define make_float32(x) (x)
+#define make_float64(x) (x)
+#endif
#ifdef FLOATX80
typedef struct {
uint64_t low;
@@ -248,14 +271,16 @@
INLINE float32 float32_abs(float32 a)
{
- return a & 0x7fffffff;
+ return make_float32(float32_val(a) & 0x7fffffff);
}
INLINE float32 float32_chs(float32 a)
{
- return a ^ 0x80000000;
+ return make_float32(float32_val(a) ^ 0x80000000);
}
+#define float32_zero make_float32(0)
+
/*----------------------------------------------------------------------------
| Software IEC/IEEE double-precision conversion routines.
*----------------------------------------------------------------------------*/
@@ -300,14 +325,16 @@
INLINE float64 float64_abs(float64 a)
{
- return a & 0x7fffffffffffffffLL;
+ return make_float64(float64_val(a) & 0x7fffffffffffffffLL);
}
INLINE float64 float64_chs(float64 a)
{
- return a ^ 0x8000000000000000LL;
+ return make_float64(float64_val(a) ^ 0x8000000000000000LL);
}
+#define float64_zero make_float64(0)
+
#ifdef FLOATX80
/*----------------------------------------------------------------------------
Modified: trunk/src/host/qemu-neo1973/gdbstub.c
===================================================================
--- trunk/src/host/qemu-neo1973/gdbstub.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/gdbstub.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -29,7 +29,10 @@
#include "qemu.h"
#else
-#include "vl.h"
+#include "qemu-common.h"
+#include "qemu-char.h"
+#include "sysemu.h"
+#include "gdbstub.h"
#endif
#include "qemu_socket.h"
Modified: trunk/src/host/qemu-neo1973/hw/acpi.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/acpi.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/acpi.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -16,7 +16,13 @@
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
//#define DEBUG
Modified: trunk/src/host/qemu-neo1973/hw/adb.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/adb.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/adb.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc_mac.h"
+#include "console.h"
/* ADB commands */
#define ADB_BUSRESET 0x00
Modified: trunk/src/host/qemu-neo1973/hw/adlib.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/adlib.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/adlib.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,8 @@
* THE SOFTWARE.
*/
#include <assert.h>
-#include "vl.h"
+#include "hw.h"
+#include "audiodev.h"
#define ADLIB_KILL_TIMERS 1
Modified: trunk/src/host/qemu-neo1973/hw/ads7846.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ads7846.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ads7846.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licensed under the GNU GPL v2.
*/
-#include <vl.h>
+#include "hw.h"
+#include "devices.h"
+#include "console.h"
struct ads7846_state_s {
qemu_irq interrupt;
Modified: trunk/src/host/qemu-neo1973/hw/an5206.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/an5206.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/an5206.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,7 +6,10 @@
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
+#include "sysemu.h"
+#include "boards.h"
#define KERNEL_LOAD_ADDR 0x10000
#define AN5206_MBAR_ADDR 0x10000000
@@ -27,8 +30,8 @@
/* Board init. */
-static void an5206_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+static void an5206_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/apb_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/apb_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/apb_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,8 @@
Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
the secondary PCI bridge. */
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
Modified: trunk/src/host/qemu-neo1973/hw/apic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/apic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/apic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -17,7 +17,9 @@
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "qemu-timer.h"
//#define DEBUG_APIC
//#define DEBUG_IOAPIC
Added: trunk/src/host/qemu-neo1973/hw/arm-misc.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm-misc.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm-misc.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,32 @@
+/*
+ * Misc ARM declarations
+ *
+ * Copyright (c) 2006 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licenced under the LGPL.
+ *
+ */
+
+#ifndef ARM_MISC_H
+#define ARM_MISC_H 1
+
+/* The CPU is also modeled as an interrupt controller. */
+#define ARM_PIC_CPU_IRQ 0
+#define ARM_PIC_CPU_FIQ 1
+qemu_irq *arm_pic_init_cpu(CPUState *env);
+
+/* armv7m.c */
+qemu_irq *armv7m_init(int flash_size, int sram_size,
+ const char *kernel_filename, const char *cpu_model);
+
+/* arm_boot.c */
+
+void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
+ const char *kernel_cmdline, const char *initrd_filename,
+ int board_id, target_phys_addr_t loader_start);
+
+/* armv7m_nvic.c */
+qemu_irq *armv7m_nvic_init(CPUState *env);
+
+#endif /* !ARM_MISC_H */
Modified: trunk/src/host/qemu-neo1973/hw/arm_boot.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm_boot.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm_boot.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "sysemu.h"
#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x00010000
Modified: trunk/src/host/qemu-neo1973/hw/arm_pic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm_pic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm_pic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,8 @@
* This code is licenced under the LGPL
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "arm-misc.h"
/* Stub functions for hardware that doesn't exist. */
void pic_info(void)
Deleted: trunk/src/host/qemu-neo1973/hw/arm_pic.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm_pic.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm_pic.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,23 +0,0 @@
-/*
- * Generic ARM Programmable Interrupt Controller support.
- *
- * Copyright (c) 2006 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licenced under the LGPL.
- *
- * Arm hardware uses a wide variety of interrupt handling hardware.
- * This provides a generic framework for connecting interrupt sources and
- * inputs.
- */
-
-#ifndef ARM_INTERRUPT_H
-#define ARM_INTERRUPT_H 1
-
-/* The CPU is also modeled as an interrupt controller. */
-#define ARM_PIC_CPU_IRQ 0
-#define ARM_PIC_CPU_FIQ 1
-qemu_irq *arm_pic_init_cpu(CPUState *env);
-
-#endif /* !ARM_INTERRUPT_H */
-
Modified: trunk/src/host/qemu-neo1973/hw/arm_sysctl.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm_sysctl.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm_sysctl.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "primecell.h"
+#include "sysemu.h"
#define LOCK_VALUE 0xa05f
Modified: trunk/src/host/qemu-neo1973/hw/arm_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/arm_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/arm_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "primecell.h"
/* Common timer implementation. */
@@ -42,7 +43,7 @@
}
}
-uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
Modified: trunk/src/host/qemu-neo1973/hw/armv7m.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/armv7m.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/armv7m.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "sysemu.h"
/* Bitbanded IO. Each word corresponds to a single bit. */
Modified: trunk/src/host/qemu-neo1973/hw/armv7m_nvic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/armv7m_nvic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/armv7m_nvic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -10,8 +10,9 @@
* NVIC. Much of that is also implemented here.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "arm-misc.h"
#define GIC_NIRQ 64
#define NCPU 1
Added: trunk/src/host/qemu-neo1973/hw/audiodev.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/audiodev.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/audiodev.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,12 @@
+/* es1370.c */
+int es1370_init (PCIBus *bus, AudioState *s);
+
+/* sb16.c */
+int SB16_init (AudioState *s, qemu_irq *pic);
+
+/* adlib.c */
+int Adlib_init (AudioState *s, qemu_irq *pic);
+
+/* gus.c */
+int GUS_init (AudioState *s, qemu_irq *pic);
+
Added: trunk/src/host/qemu-neo1973/hw/boards.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/boards.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/boards.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,98 @@
+/* Declarations for use by board files for creating devices. */
+
+#ifndef HW_BOARDS_H
+#define HW_BOARDS_H
+
+typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model);
+
+typedef struct QEMUMachine {
+ const char *name;
+ const char *desc;
+ QEMUMachineInitFunc *init;
+ struct QEMUMachine *next;
+} QEMUMachine;
+
+int qemu_register_machine(QEMUMachine *m);
+
+/* Axis ETRAX. */
+extern QEMUMachine bareetraxfs_machine;
+
+/* pc.c */
+extern QEMUMachine pc_machine;
+extern QEMUMachine isapc_machine;
+
+/* ppc.c */
+extern QEMUMachine prep_machine;
+extern QEMUMachine core99_machine;
+extern QEMUMachine heathrow_machine;
+extern QEMUMachine ref405ep_machine;
+extern QEMUMachine taihu_machine;
+
+/* mips_r4k.c */
+extern QEMUMachine mips_machine;
+
+/* mips_malta.c */
+extern QEMUMachine mips_malta_machine;
+
+/* mips_pica61.c */
+extern QEMUMachine mips_pica61_machine;
+
+/* mips_mipssim.c */
+extern QEMUMachine mips_mipssim_machine;
+
+/* shix.c */
+extern QEMUMachine shix_machine;
+
+/* r2d.c */
+extern QEMUMachine r2d_machine;
+
+/* sun4m.c */
+extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
+
+/* sun4u.c */
+extern QEMUMachine sun4u_machine;
+
+/* integratorcp.c */
+extern QEMUMachine integratorcp_machine;
+
+/* versatilepb.c */
+extern QEMUMachine versatilepb_machine;
+extern QEMUMachine versatileab_machine;
+
+/* realview.c */
+extern QEMUMachine realview_machine;
+
+/* spitz.c */
+extern QEMUMachine akitapda_machine;
+extern QEMUMachine spitzpda_machine;
+extern QEMUMachine borzoipda_machine;
+extern QEMUMachine terrierpda_machine;
+
+/* neo1973.c */
+extern QEMUMachine neo1973_machine;
+
+/* palm.c */
+extern QEMUMachine palmte_machine;
+
+/* gumstix.c */
+extern QEMUMachine connex_machine;
+
+/* stellaris.c */
+extern QEMUMachine lm3s811evb_machine;
+extern QEMUMachine lm3s6965evb_machine;
+
+/* an5206.c */
+extern QEMUMachine an5206_machine;
+
+/* mcf5208.c */
+extern QEMUMachine mcf5208evb_machine;
+
+/* dummy_m68k.c */
+extern QEMUMachine dummy_m68k_machine;
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/bt-hci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/bt-hci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/bt-hci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -19,8 +19,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "qemu-timer.h"
+#include "usb.h"
+#include "bt.h"
+
void bt_submit_lmp(struct bt_device_s *bt, int length, uint8_t *data)
{
int resp, resplen, error, op, tr;
Modified: trunk/src/host/qemu-neo1973/hw/cdrom.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/cdrom.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/cdrom.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -25,7 +25,8 @@
/* ??? Most of the ATAPI emulation is still in ide.c. It should be moved
here. */
-#include <vl.h>
+#include "qemu-common.h"
+#include "scsi-disk.h"
static void lba_to_msf(uint8_t *buf, int lba)
{
Modified: trunk/src/host/qemu-neo1973/hw/cirrus_vga.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/cirrus_vga.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/cirrus_vga.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,10 @@
* Reference: Finn Thogersons' VGADOC4b
* available at http://home.worldonline.dk/~finth/
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "console.h"
#include "vga_int.h"
/*
Modified: trunk/src/host/qemu-neo1973/hw/cs4231.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/cs4231.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/cs4231.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
/* debug CS4231 */
//#define DEBUG_CS
Modified: trunk/src/host/qemu-neo1973/hw/cuda.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/cuda.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/cuda.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,8 +22,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
/* XXX: implement all timer modes */
Added: trunk/src/host/qemu-neo1973/hw/devices.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/devices.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/devices.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,43 @@
+#ifndef QEMU_DEVICES_H
+#define QEMU_DEVICES_H
+
+/* Devices that have nowhere better to go. */
+
+/* smc91c111.c */
+void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
+
+/* ssd0323.c */
+int ssd0323_xfer_ssi(void *opaque, int data);
+void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
+
+/* ads7846.c */
+struct ads7846_state_s;
+uint32_t ads7846_read(void *opaque);
+void ads7846_write(void *opaque, uint32_t value);
+struct ads7846_state_s *ads7846_init(qemu_irq penirq);
+
+/* stellaris_input.c */
+void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
+
+/* jbt6k74.c */
+uint8_t jbt6k74_txrx(void *opaque, uint8_t value);
+uint8_t jbt6k74_btxrx(void *opaque, uint8_t value);
+void *jbt6k74_init();
+
+/* modem.c */
+CharDriverState *modem_init();
+void modem_enable(CharDriverState *chr, int enable);
+
+/* gps.c */
+CharDriverState *gps_antaris_serial_init();
+void gps_enable(CharDriverState *chr, int enable);
+
+#ifdef NEED_CPU_H
+
+/* usb-ohci.c */
+void usb_ohci_init_memio(target_phys_addr_t base, int num_ports, int devfn,
+ qemu_irq irq);
+
+#endif
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/dma.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/dma.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/dma.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "isa.h"
/* #define DEBUG_DMA */
Modified: trunk/src/host/qemu-neo1973/hw/ds1225y.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ds1225y.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ds1225y.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,9 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "nvram.h"
typedef enum
{
Modified: trunk/src/host/qemu-neo1973/hw/dummy_m68k.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/dummy_m68k.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/dummy_m68k.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,7 +6,9 @@
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "sysemu.h"
+#include "boards.h"
#define KERNEL_LOAD_ADDR 0x10000
@@ -14,7 +16,6 @@
static void dummy_m68k_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/ecc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ecc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ecc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,8 @@
* This code is licensed under the GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "flash.h"
/*
* Pre-calculated 256-way 1 byte column parity. Table borrowed from Linux.
Modified: trunk/src/host/qemu-neo1973/hw/eepro100.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/eepro100.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/eepro100.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -40,7 +40,9 @@
#include <assert.h>
#include <stddef.h> /* offsetof */
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "net.h"
#include "eeprom93xx.h"
/* Common declarations for all PCI devices. */
Modified: trunk/src/host/qemu-neo1973/hw/eeprom93xx.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/eeprom93xx.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/eeprom93xx.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -37,6 +37,7 @@
*/
#include <assert.h>
+#include "hw.h"
#include "eeprom93xx.h"
/* Debug EEPROM emulation. */
Modified: trunk/src/host/qemu-neo1973/hw/eeprom93xx.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/eeprom93xx.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/eeprom93xx.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,6 @@
#ifndef EEPROM93XX_H
#define EEPROM93XX_H
-#include "vl.h"
-
typedef struct _eeprom_t eeprom_t;
/* Create a new EEPROM with (nwords * 2) bytes. */
Modified: trunk/src/host/qemu-neo1973/hw/es1370.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/es1370.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/es1370.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,10 @@
/* #define VERBOSE_ES1370 */
#define SILENT_ES1370
-#include "vl.h"
+#include "hw.h"
+#include "audiodev.h"
+#include "audio/audio.h"
+#include "pci.h"
/* Missing stuff:
SCTRL_P[12](END|ST)INC
Modified: trunk/src/host/qemu-neo1973/hw/esp.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/esp.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/esp.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,12 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "block.h"
+#include "scsi-disk.h"
+#include "sun4m.h"
+/* FIXME: Only needed for MAX_DISKS, which is probably wrong. */
+#include "sysemu.h"
/* debug ESP card */
//#define DEBUG_ESP
Modified: trunk/src/host/qemu-neo1973/hw/etraxfs.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/etraxfs.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/etraxfs.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,7 +23,9 @@
*/
#include <time.h>
#include <sys/time.h>
-#include "vl.h"
+#include "hw.h"
+#include "sysemu.h"
+#include "boards.h"
extern FILE *logfile;
@@ -107,8 +109,8 @@
}
static
-void bareetraxfs_init (int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+void bareetraxfs_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/etraxfs_ser.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/etraxfs_ser.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/etraxfs_ser.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,7 +24,7 @@
#include <stdio.h>
#include <ctype.h>
-#include "vl.h"
+#include "hw.h"
#define RW_TR_DMA_EN 0xb0026004
#define RW_DOUT 0xb002601c
Modified: trunk/src/host/qemu-neo1973/hw/etraxfs_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/etraxfs_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/etraxfs_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,7 +23,8 @@
*/
#include <stdio.h>
#include <sys/time.h>
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
void etrax_ack_irq(CPUState *env, uint32_t mask);
Modified: trunk/src/host/qemu-neo1973/hw/fdc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/fdc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/fdc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -25,7 +25,11 @@
* The controller is used in Sun4m systems in a slightly different
* way. There are changes in DOR register and DMA is not available.
*/
-#include "vl.h"
+#include "hw.h"
+#include "fdc.h"
+#include "block.h"
+#include "qemu-timer.h"
+#include "isa.h"
/********************************************************/
/* debug Floppy devices */
Added: trunk/src/host/qemu-neo1973/hw/fdc.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/fdc.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/fdc.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,12 @@
+/* fdc.c */
+#define MAX_FD 2
+extern BlockDriverState *fd_table[MAX_FD];
+
+typedef struct fdctrl_t fdctrl_t;
+
+fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
+ target_phys_addr_t io_base,
+ BlockDriverState **fds);
+fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
+ BlockDriverState **fds);
+int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
Added: trunk/src/host/qemu-neo1973/hw/firmware_abi.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/firmware_abi.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/firmware_abi.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,198 @@
+#ifndef FIRMWARE_ABI_H
+#define FIRMWARE_ABI_H
+
+#ifndef __ASSEMBLY__
+/* Open Hack'Ware NVRAM configuration structure */
+
+/* Version 3 */
+typedef struct ohwcfg_v3_t ohwcfg_v3_t;
+struct ohwcfg_v3_t {
+ /* 0x00: structure identifier */
+ uint8_t struct_ident[0x10];
+ /* 0x10: structure version and NVRAM description */
+ uint32_t struct_version;
+ uint16_t nvram_size;
+ uint16_t pad0;
+ uint16_t nvram_arch_ptr;
+ uint16_t nvram_arch_size;
+ uint16_t nvram_arch_crc;
+ uint8_t pad1[0x02];
+ /* 0x20: host architecture */
+ uint8_t arch[0x10];
+ /* 0x30: RAM/ROM description */
+ uint64_t RAM0_base;
+ uint64_t RAM0_size;
+ uint64_t RAM1_base;
+ uint64_t RAM1_size;
+ uint64_t RAM2_base;
+ uint64_t RAM2_size;
+ uint64_t RAM3_base;
+ uint64_t RAM3_size;
+ uint64_t ROM_base;
+ uint64_t ROM_size;
+ /* 0x80: Kernel description */
+ uint64_t kernel_image;
+ uint64_t kernel_size;
+ /* 0x90: Kernel command line */
+ uint64_t cmdline;
+ uint64_t cmdline_size;
+ /* 0xA0: Kernel boot image */
+ uint64_t initrd_image;
+ uint64_t initrd_size;
+ /* 0xB0: NVRAM image */
+ uint64_t NVRAM_image;
+ uint8_t pad2[8];
+ /* 0xC0: graphic configuration */
+ uint16_t width;
+ uint16_t height;
+ uint16_t depth;
+ uint16_t graphic_flags;
+ /* 0xC8: CPUs description */
+ uint8_t nb_cpus;
+ uint8_t boot_cpu;
+ uint8_t nboot_devices;
+ uint8_t pad3[5];
+ /* 0xD0: boot devices */
+ uint8_t boot_devices[0x10];
+ /* 0xE0 */
+ uint8_t pad4[0x1C]; /* 28 */
+ /* 0xFC: checksum */
+ uint16_t crc;
+ uint8_t pad5[0x02];
+} __attribute__ (( packed ));
+
+#define OHW_GF_NOGRAPHICS 0x0001
+
+static inline uint16_t
+OHW_crc_update (uint16_t prev, uint16_t value)
+{
+ uint16_t tmp;
+ uint16_t pd, pd1, pd2;
+
+ tmp = prev >> 8;
+ pd = prev ^ value;
+ pd1 = pd & 0x000F;
+ pd2 = ((pd >> 4) & 0x000F) ^ pd1;
+ tmp ^= (pd1 << 3) | (pd1 << 8);
+ tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
+
+ return tmp;
+}
+
+static inline uint16_t
+OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
+{
+ uint32_t i;
+ uint16_t crc = 0xFFFF;
+ uint8_t *ptr = (uint8_t *)header;
+ int odd;
+
+ odd = count & 1;
+ count &= ~1;
+ for (i = 0; i != count; i++) {
+ crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
+ }
+ if (odd) {
+ crc = OHW_crc_update(crc, ptr[start + i] << 8);
+ }
+
+ return crc;
+}
+
+/* Sparc32 runtime NVRAM structure for SMP CPU boot */
+struct sparc_arch_cfg {
+ uint32_t smp_ctx;
+ uint32_t smp_ctxtbl;
+ uint32_t smp_entry;
+ uint8_t valid;
+ uint8_t unused[51];
+};
+
+/* OpenBIOS NVRAM partition */
+struct OpenBIOS_nvpart_v1 {
+ uint8_t signature;
+ uint8_t checksum;
+ uint16_t len; // BE, length divided by 16
+ char name[12];
+};
+
+#define OPENBIOS_PART_SYSTEM 0x70
+#define OPENBIOS_PART_FREE 0x7f
+
+static inline void
+OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size)
+{
+ unsigned int i, sum;
+ uint8_t *tmpptr;
+
+ // Length divided by 16
+ header->len = cpu_to_be16(size >> 4);
+
+ // Checksum
+ tmpptr = (uint8_t *)header;
+ sum = *tmpptr;
+ for (i = 0; i < 14; i++) {
+ sum += tmpptr[2 + i];
+ sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
+ }
+ header->checksum = sum & 0xff;
+}
+
+static inline uint32_t
+OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const unsigned char *str)
+{
+ uint32_t len;
+
+ len = strlen(str) + 1;
+ memcpy(&nvram[addr], str, len);
+
+ return addr + len;
+}
+
+/* Sun IDPROM structure at the end of NVRAM */
+struct Sun_nvram {
+ uint8_t type;
+ uint8_t machine_id;
+ uint8_t macaddr[6];
+ uint8_t unused[7];
+ uint8_t checksum;
+};
+
+static inline void
+Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id)
+{
+ uint8_t tmp, *tmpptr;
+ unsigned int i;
+
+ header->type = 1;
+ header->machine_id = machine_id & 0xff;
+ memcpy(&header->macaddr, macaddr, 6);
+ /* Calculate checksum */
+ tmp = 0;
+ tmpptr = (uint8_t *)header;
+ for (i = 0; i < 15; i++)
+ tmp ^= tmpptr[i];
+
+ header->checksum = tmp;
+}
+
+#else /* __ASSEMBLY__ */
+
+/* Structure offsets for asm use */
+
+/* Open Hack'Ware NVRAM configuration structure */
+#define OHW_ARCH_PTR 0x18
+#define OHW_RAM_SIZE 0x38
+#define OHW_BOOT_CPU 0xC9
+
+/* Sparc32 runtime NVRAM structure for SMP CPU boot */
+#define SPARC_SMP_CTX 0x0
+#define SPARC_SMP_CTXTBL 0x4
+#define SPARC_SMP_ENTRY 0x8
+#define SPARC_SMP_VALID 0xc
+
+/* Sun IDPROM structure at the end of NVRAM */
+#define SPARC_MACHINE_ID 0x1fd9
+
+#endif /* __ASSEMBLY__ */
+#endif /* FIRMWARE_ABI_H */
Added: trunk/src/host/qemu-neo1973/hw/flash.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/flash.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/flash.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,40 @@
+/* NOR flash devices */
+typedef struct pflash_t pflash_t;
+
+pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
+ BlockDriverState *bs,
+ uint32_t sector_len, int nb_blocs, int width,
+ uint16_t id0, uint16_t id1,
+ uint16_t id2, uint16_t id3);
+
+/* nand.c */
+struct nand_flash_s;
+struct nand_flash_s *nand_init(int manf_id, int chip_id);
+void nand_done(struct nand_flash_s *s);
+void nand_setpins(struct nand_flash_s *s,
+ int cle, int ale, int ce, int wp, int gnd);
+void nand_getpins(struct nand_flash_s *s, int *rb);
+void nand_setio(struct nand_flash_s *s, uint8_t value);
+uint8_t nand_getio(struct nand_flash_s *s);
+
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+
+/* ecc.c */
+struct ecc_state_s {
+ uint8_t cp; /* Column parity */
+ uint16_t lp[2]; /* Line parity */
+ uint16_t count;
+};
+
+uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
+void ecc_reset(struct ecc_state_s *s);
+void ecc_put(QEMUFile *f, struct ecc_state_s *s);
+void ecc_get(QEMUFile *f, struct ecc_state_s *s);
+
Modified: trunk/src/host/qemu-neo1973/hw/gps.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/gps.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/gps.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,8 +23,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+
#include <math.h>
#define GPS_MAX_SATS 32
Modified: trunk/src/host/qemu-neo1973/hw/grackle_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/grackle_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/grackle_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,8 +23,10 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
+#include "pci.h"
+
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
Modified: trunk/src/host/qemu-neo1973/hw/gt64xxx.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/gt64xxx.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/gt64xxx.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,10 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "pci.h"
+#include "pc.h"
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
@@ -905,7 +908,7 @@
}
-void gt64120_reset(void *opaque)
+static void gt64120_reset(void *opaque)
{
GT64120State *s = opaque;
Added: trunk/src/host/qemu-neo1973/hw/gumstix.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/gumstix.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/gumstix.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,72 @@
+/*
+ * Gumstix Platforms
+ *
+ * Copyright (c) 2007 by Thorsten Zitterell <info at bitmux.org>
+ *
+ * Code based on spitz platform by Andrzej Zaborowski <balrog at zabor.org>
+ *
+ * This code is licensed under the GNU GPL v2.
+ */
+
+#include "hw.h"
+#include "pxa.h"
+#include "net.h"
+#include "flash.h"
+#include "sysemu.h"
+#include "devices.h"
+#include "boards.h"
+
+/* Board init. */
+enum gumstix_model_e { connex };
+
+static void gumstix_common_init(int ram_size, int vga_ram_size,
+ DisplayState *ds, const char *kernel_filename,
+ const char *kernel_cmdline, const char *initrd_filename,
+ const char *cpu_model, enum gumstix_model_e model)
+{
+ struct pxa2xx_state_s *cpu;
+
+ uint32_t gumstix_rom = 0x02000000;
+ uint32_t gumstix_ram = 0x08000000;
+
+ if (ram_size < (gumstix_ram + gumstix_rom + PXA2XX_INTERNAL_SIZE)) {
+ fprintf(stderr, "This platform requires %i bytes of memory\n",
+ gumstix_ram + gumstix_rom + PXA2XX_INTERNAL_SIZE);
+ exit(1);
+ }
+
+ cpu = pxa255_init(gumstix_ram, ds);
+
+ if (pflash_table[0] == NULL) {
+ fprintf(stderr, "A flash image must be given with the "
+ "'pflash' parameter\n");
+ exit(1);
+ }
+
+ if (!pflash_register(0x00000000, gumstix_ram + PXA2XX_INTERNAL_SIZE,
+ pflash_table[0], 128 * 1024, 128, 2, 0, 0, 0, 0)) {
+ fprintf(stderr, "qemu: Error register flash memory.\n");
+ exit(1);
+ }
+
+ cpu->env->regs[15] = 0x00000000;
+
+ /* Interrupt line of NIC is connected to GPIO line 36 */
+ smc91c111_init(&nd_table[0], 0x04000300,
+ pxa2xx_gpio_in_get(cpu->gpio)[36]);
+}
+
+static void connex_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ gumstix_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ kernel_cmdline, initrd_filename, cpu_model, connex);
+}
+
+QEMUMachine connex_machine = {
+ "connex",
+ "Gumstix Connex (PXA255)",
+ connex_init,
+};
Modified: trunk/src/host/qemu-neo1973/hw/heathrow_pic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/heathrow_pic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/heathrow_pic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
//#define DEBUG
Added: trunk/src/host/qemu-neo1973/hw/hw.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/hw.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/hw.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,99 @@
+/* Declarations for use by hardware emulation. */
+#ifndef QEMU_HW_H
+#define QEMU_HW_H
+
+#include "qemu-common.h"
+#include "irq.h"
+
+/* VM Load/Save */
+
+QEMUFile *qemu_fopen(const char *filename, const char *mode);
+void qemu_fflush(QEMUFile *f);
+void qemu_fclose(QEMUFile *f);
+void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
+void qemu_put_byte(QEMUFile *f, int v);
+void qemu_put_be16(QEMUFile *f, unsigned int v);
+void qemu_put_be32(QEMUFile *f, unsigned int v);
+void qemu_put_be64(QEMUFile *f, uint64_t v);
+int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
+int qemu_get_byte(QEMUFile *f);
+unsigned int qemu_get_be16(QEMUFile *f);
+unsigned int qemu_get_be32(QEMUFile *f);
+uint64_t qemu_get_be64(QEMUFile *f);
+
+static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
+{
+ qemu_put_be64(f, *pv);
+}
+
+static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
+{
+ qemu_put_be32(f, *pv);
+}
+
+static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
+{
+ qemu_put_be16(f, *pv);
+}
+
+static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
+{
+ qemu_put_byte(f, *pv);
+}
+
+static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
+{
+ *pv = qemu_get_be64(f);
+}
+
+static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
+{
+ *pv = qemu_get_be32(f);
+}
+
+static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
+{
+ *pv = qemu_get_be16(f);
+}
+
+static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
+{
+ *pv = qemu_get_byte(f);
+}
+
+#ifdef NEED_CPU_H
+#if TARGET_LONG_BITS == 64
+#define qemu_put_betl qemu_put_be64
+#define qemu_get_betl qemu_get_be64
+#define qemu_put_betls qemu_put_be64s
+#define qemu_get_betls qemu_get_be64s
+#else
+#define qemu_put_betl qemu_put_be32
+#define qemu_get_betl qemu_get_be32
+#define qemu_put_betls qemu_put_be32s
+#define qemu_get_betls qemu_get_be32s
+#endif
+#endif
+
+int64_t qemu_ftell(QEMUFile *f);
+int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
+
+typedef void SaveStateHandler(QEMUFile *f, void *opaque);
+typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
+
+int register_savevm(const char *idstr,
+ int instance_id,
+ int version_id,
+ SaveStateHandler *save_state,
+ LoadStateHandler *load_state,
+ void *opaque);
+
+typedef void QEMUResetHandler(void *opaque);
+
+void qemu_register_reset(QEMUResetHandler *func, void *opaque);
+
+/* These should really be in isa.h, but are here to make pc.h happy. */
+typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
+typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/i2c.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/i2c.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/i2c.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licenced under the LGPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
struct i2c_bus
{
@@ -30,7 +31,7 @@
i2c_slave *dev;
if (size < sizeof(i2c_slave))
- cpu_abort(cpu_single_env, "I2C struct too small");
+ hw_error("I2C struct too small");
dev = (i2c_slave *)qemu_mallocz(size);
dev->address = address;
Modified: trunk/src/host/qemu-neo1973/hw/i2c.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/i2c.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/i2c.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -13,8 +13,6 @@
I2C_NACK /* Masker NACKed a receive byte. */
};
-typedef struct i2c_slave i2c_slave;
-
/* Master to slave. */
typedef int (*i2c_send_cb)(i2c_slave *s, uint8_t data);
/* Slave to master. */
@@ -34,8 +32,6 @@
void *next;
};
-typedef struct i2c_bus i2c_bus;
-
i2c_bus *i2c_init_bus(void);
i2c_slave *i2c_slave_init(i2c_bus *bus, int address, int size);
void i2c_set_slave_address(i2c_slave *dev, int address);
@@ -50,6 +46,14 @@
void i2c_slave_save(QEMUFile *f, i2c_slave *dev);
void i2c_slave_load(QEMUFile *f, i2c_slave *dev);
+/* max111x.c */
+struct max111x_s;
+uint32_t max111x_read(void *opaque);
+void max111x_write(void *opaque, uint32_t value);
+struct max111x_s *max1110_init(qemu_irq cb);
+struct max111x_s *max1111_init(qemu_irq cb);
+void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
+
/* max7310.c */
i2c_slave *max7310_init(i2c_bus *bus);
void max7310_reset(i2c_slave *i2c);
@@ -81,4 +85,7 @@
void pcf_onkey_set(i2c_slave *i2c, int level);
void pcf_exton_set(i2c_slave *i2c, int level);
+/* ssd0303.c */
+void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address);
+
#endif
Modified: trunk/src/host/qemu-neo1973/hw/i8254.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/i8254.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/i8254.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "isa.h"
+#include "qemu-timer.h"
//#define DEBUG_PIT
Modified: trunk/src/host/qemu-neo1973/hw/i8259.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/i8259.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/i8259.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "isa.h"
+#include "console.h"
/* debug PIC */
//#define DEBUG_PIC
@@ -175,7 +178,7 @@
int64_t irq_time[16];
#endif
-void i8259_set_irq(void *opaque, int irq, int level)
+static void i8259_set_irq(void *opaque, int irq, int level)
{
PicState2 *s = opaque;
Modified: trunk/src/host/qemu-neo1973/hw/ide.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ide.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ide.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,15 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "scsi-disk.h"
+#include "pcmcia.h"
+#include "block.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "ppc_mac.h"
/* debug IDE devices */
//#define DEBUG_IDE
Modified: trunk/src/host/qemu-neo1973/hw/integratorcp.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/integratorcp.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/integratorcp.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,13 @@
* This code is licenced under the GPL
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "primecell.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "arm-misc.h"
+#include "net.h"
void DMA_run (void)
{
@@ -466,7 +471,6 @@
static void integratorcp_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/iommu.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/iommu.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/iommu.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
/* debug iommu */
//#define DEBUG_IOMMU
@@ -37,7 +38,6 @@
#define IOMMU_CTRL (0x0000 >> 2)
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
-#define IOMMU_VERSION 0x04000000
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
@@ -104,6 +104,7 @@
target_phys_addr_t addr;
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
+ uint32_t version;
} IOMMUState;
static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
@@ -158,7 +159,7 @@
break;
}
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
- s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
+ s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
break;
case IOMMU_BASE:
s->regs[saddr] = val & IOMMU_BASE_MASK;
@@ -308,10 +309,11 @@
memset(s->regs, 0, IOMMU_NREGS * 4);
s->iostart = 0;
- s->regs[IOMMU_CTRL] = IOMMU_VERSION;
+ s->regs[IOMMU_CTRL] = s->version;
+ s->regs[IOMMU_ARBEN] = IOMMU_MID;
}
-void *iommu_init(target_phys_addr_t addr)
+void *iommu_init(target_phys_addr_t addr, uint32_t version)
{
IOMMUState *s;
int iommu_io_memory;
@@ -321,12 +323,14 @@
return NULL;
s->addr = addr;
+ s->version = version;
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
qemu_register_reset(iommu_reset, s);
+ iommu_reset(s);
return s;
}
Modified: trunk/src/host/qemu-neo1973/hw/irq.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/irq.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/irq.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "irq.h"
struct IRQState {
qemu_irq_handler handler;
@@ -64,5 +65,7 @@
qemu_irq qemu_irq_invert(qemu_irq irq)
{
+ /* The default state for IRQs is low, so raise the output now. */
+ qemu_irq_raise(irq);
return qemu_allocate_irqs(qemu_notirq, irq, 1)[0];
}
Modified: trunk/src/host/qemu-neo1973/hw/irq.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/irq.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/irq.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,9 +1,12 @@
+#ifndef QEMU_IRQ_H
+#define QEMU_IRQ_H
+
/* Generic IRQ/GPIO pin infrastructure. */
+/* FIXME: Rmove one of these. */
typedef void (*qemu_irq_handler)(void *opaque, int n, int level);
+typedef void SetIRQFunc(void *opaque, int irq_num, int level);
-typedef struct IRQState *qemu_irq;
-
void qemu_set_irq(qemu_irq irq, int level);
static inline void qemu_irq_raise(qemu_irq irq)
@@ -21,3 +24,5 @@
/* Returns a new IRQ with opposite polarity. */
qemu_irq qemu_irq_invert(qemu_irq irq);
+
+#endif
Added: trunk/src/host/qemu-neo1973/hw/isa.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/isa.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/isa.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,24 @@
+/* ISA bus */
+
+extern target_phys_addr_t isa_mem_base;
+
+int register_ioport_read(int start, int length, int size,
+ IOPortReadFunc *func, void *opaque);
+int register_ioport_write(int start, int length, int size,
+ IOPortWriteFunc *func, void *opaque);
+void isa_unassign_ioport(int start, int length);
+
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
+
+/* dma.c */
+int DMA_get_channel_mode (int nchan);
+int DMA_read_memory (int nchan, void *buf, int pos, int size);
+int DMA_write_memory (int nchan, void *buf, int pos, int size);
+void DMA_hold_DREQ (int nchan);
+void DMA_release_DREQ (int nchan);
+void DMA_schedule(int nchan);
+void DMA_run (void);
+void DMA_init (int high_page_enable);
+void DMA_register_channel (int nchan,
+ DMA_transfer_handler transfer_handler,
+ void *opaque);
Modified: trunk/src/host/qemu-neo1973/hw/isa_mmio.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/isa_mmio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/isa_mmio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,8 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "isa.h"
static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
uint32_t val)
Modified: trunk/src/host/qemu-neo1973/hw/jazz_led.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/jazz_led.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/jazz_led.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,9 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "console.h"
#include "pixel_ops.h"
//#define DEBUG_LED
Modified: trunk/src/host/qemu-neo1973/hw/jbt6k74.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/jbt6k74.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/jbt6k74.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,7 @@
* This file is licensed under GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
struct jbt6k74_s {
uint8_t command;
Modified: trunk/src/host/qemu-neo1973/hw/lsi53c895a.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/lsi53c895a.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/lsi53c895a.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -10,7 +10,9 @@
/* ??? Need to check if the {read,write}[wl] routines work properly on
big-endian targets. */
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "scsi-disk.h"
//#define DEBUG_LSI
//#define DEBUG_LSI_REG
Modified: trunk/src/host/qemu-neo1973/hw/m48t59.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/m48t59.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/m48t59.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
-#include "m48t59.h"
+#include "hw.h"
+#include "nvram.h"
+#include "isa.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
//#define DEBUG_NVRAM
Deleted: trunk/src/host/qemu-neo1973/hw/m48t59.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/m48t59.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/m48t59.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,13 +0,0 @@
-#if !defined (__M48T59_H__)
-#define __M48T59_H__
-
-typedef struct m48t59_t m48t59_t;
-
-void m48t59_write (void *private, uint32_t addr, uint32_t val);
-uint32_t m48t59_read (void *private, uint32_t addr);
-void m48t59_toggle_lock (void *private, int lock);
-m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size,
- int type);
-
-#endif /* !defined (__M48T59_H__) */
Modified: trunk/src/host/qemu-neo1973/hw/mac_dbdma.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mac_dbdma.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mac_dbdma.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
/* DBDMA: currently no op - should suffice right now */
Modified: trunk/src/host/qemu-neo1973/hw/mac_nvram.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mac_nvram.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mac_nvram.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
struct MacIONVRAMState {
Modified: trunk/src/host/qemu-neo1973/hw/macio.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/macio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/macio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,8 +22,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
#include "ppc_mac.h"
+#include "pci.h"
typedef struct macio_state_t macio_state_t;
struct macio_state_t {
Modified: trunk/src/host/qemu-neo1973/hw/max111x.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/max111x.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/max111x.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licensed under the GNU GPLv2.
*/
-#include <vl.h>
+#include "hw.h"
+#include "i2c.h"
struct max111x_s {
qemu_irq interrupt;
Modified: trunk/src/host/qemu-neo1973/hw/max7310.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/max7310.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/max7310.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This file is licensed under GNU GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
struct max7310_s {
i2c_slave i2c;
@@ -182,7 +183,7 @@
{
struct max7310_s *s = (struct max7310_s *) opaque;
if (line >= sizeof(s->handler) / sizeof(*s->handler) || line < 0)
- cpu_abort(cpu_single_env, "bad GPIO line");
+ hw_error("bad GPIO line");
if (level)
s->level |= s->direction & (1 << line);
@@ -220,7 +221,7 @@
{
struct max7310_s *s = (struct max7310_s *) i2c;
if (line >= sizeof(s->handler) / sizeof(*s->handler) || line < 0)
- cpu_abort(cpu_single_env, "bad GPIO line");
+ hw_error("bad GPIO line");
s->handler[line] = handler;
}
Modified: trunk/src/host/qemu-neo1973/hw/mc146818rtc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mc146818rtc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mc146818rtc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "pc.h"
+#include "isa.h"
//#define DEBUG_CMOS
@@ -386,7 +390,7 @@
#define REG_IBM_CENTURY_BYTE 0x32
#define REG_IBM_PS2_CENTURY_BYTE 0x37
-void rtc_set_date_from_host(RTCState *s)
+static void rtc_set_date_from_host(RTCState *s)
{
time_t ti;
struct tm *tm;
@@ -494,22 +498,22 @@
}
/* Memory mapped interface */
-uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}
-void cmos_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writeb (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}
-uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -521,8 +525,8 @@
return val;
}
-void cmos_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writew (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -531,7 +535,7 @@
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}
-uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -543,8 +547,8 @@
return val;
}
-void cmos_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writel (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
Added: trunk/src/host/qemu-neo1973/hw/mcf.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,21 @@
+#ifndef HW_MCF_H
+#define HW_MCF_H
+/* Motorola ColdFire device prototypes. */
+
+/* mcf_uart.c */
+uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
+void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
+void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
+void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
+ CharDriverState *chr);
+
+/* mcf_intc.c */
+qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
+
+/* mcf_fec.c */
+void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
+
+/* mcf5206.c */
+qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/mcf5206.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf5206.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf5206.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,10 @@
*
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
/* General purpose timer module. */
typedef struct {
Modified: trunk/src/host/qemu-neo1973/hw/mcf5208.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf5208.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf5208.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,12 @@
*
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "net.h"
+#include "boards.h"
#define SYS_FREQ 66000000
@@ -199,7 +204,6 @@
static void mcf5208evb_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/mcf_fec.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf_fec.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf_fec.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,9 @@
*
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "net.h"
+#include "mcf.h"
/* For crc32 */
#include <zlib.h>
@@ -249,7 +251,7 @@
}
}
-void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
Modified: trunk/src/host/qemu-neo1973/hw/mcf_intc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf_intc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf_intc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,8 @@
*
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
typedef struct {
uint64_t ipr;
Modified: trunk/src/host/qemu-neo1973/hw/mcf_uart.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mcf_uart.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mcf_uart.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,9 @@
*
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
+#include "qemu-char.h"
typedef struct {
uint8_t mr[2];
Added: trunk/src/host/qemu-neo1973/hw/mips.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,25 @@
+#ifndef HW_MIPS_H
+#define HW_MIPS_H
+/* Definitions for mips board emulation. */
+
+/* gt64xxx.c */
+PCIBus *pci_gt64120_init(qemu_irq *pic);
+
+/* ds1225y.c */
+typedef struct ds1225y_t ds1225y_t;
+ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
+
+/* mipsnet.c */
+void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
+
+/* jazz_led.c */
+extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
+
+/* mips_int.c */
+extern void cpu_mips_irq_init_cpu(CPUState *env);
+
+/* mips_timer.c */
+extern void cpu_mips_clock_init(CPUState *);
+extern void cpu_mips_irqctrl_init (void);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/mips_int.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_int.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_int.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,4 +1,5 @@
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
#include "cpu.h"
/* Raise IRQ to CPU if necessary. It must be called every time the active
Modified: trunk/src/host/qemu-neo1973/hw/mips_malta.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_malta.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_malta.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,17 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "net.h"
+#include "boards.h"
+#include "smbus.h"
+#include "mips.h"
+#include "pci.h"
+#include "qemu-char.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "boards.h"
#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
@@ -388,7 +398,7 @@
malta_fpga_writel
};
-void malta_fpga_reset(void *opaque)
+static void malta_fpga_reset(void *opaque)
{
MaltaFPGAState *s = opaque;
@@ -405,7 +415,7 @@
malta_fpga_update_display(s);
}
-MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
+static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
{
MaltaFPGAState *s;
CharDriverState *uart_chr;
@@ -746,8 +756,8 @@
}
static
-void mips_malta_init (int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+void mips_malta_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/mips_mipssim.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_mipssim.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_mipssim.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,7 +24,13 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "pc.h"
+#include "isa.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
@@ -100,8 +106,8 @@
}
static void
-mips_mipssim_init (int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+mips_mipssim_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/mips_pica61.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_pica61.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_pica61.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,13 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "isa.h"
+#include "pc.h"
+#include "fdc.h"
+#include "sysemu.h"
+#include "boards.h"
#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
@@ -54,8 +60,8 @@
}
static
-void mips_pica61_init (int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+void mips_pica61_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/mips_r4k.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_r4k.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_r4k.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,13 @@
* All peripherial devices are attached to this "bus" with
* the standard PC ISA addresses.
*/
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "pc.h"
+#include "isa.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
@@ -137,8 +143,8 @@
}
static
-void mips_r4k_init (int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+void mips_r4k_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/mips_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mips_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mips_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,4 +1,6 @@
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "qemu-timer.h"
void cpu_mips_irqctrl_init (void)
{
Modified: trunk/src/host/qemu-neo1973/hw/mipsnet.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mipsnet.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mipsnet.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,4 +1,7 @@
-#include "vl.h"
+#include "hw.h"
+#include "mips.h"
+#include "net.h"
+#include "isa.h"
//#define DEBUG_MIPSNET_SEND
//#define DEBUG_MIPSNET_RECEIVE
Modified: trunk/src/host/qemu-neo1973/hw/modem.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/modem.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/modem.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,12 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "qemu-char.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+
#include "misc.h"
#include "gnokii.h"
#include "compat.h"
Modified: trunk/src/host/qemu-neo1973/hw/mpcore.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/mpcore.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/mpcore.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "primecell.h"
#define MPCORE_PRIV_BASE 0x10100000
#define NCPU 4
Modified: trunk/src/host/qemu-neo1973/hw/nand.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/nand.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/nand.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -11,7 +11,11 @@
#ifndef NAND_IO
-# include "vl.h"
+# include "hw.h"
+# include "flash.h"
+# include "block.h"
+/* FIXME: Pass block device as an argument. */
+# include "sysemu.h"
# define NAND_CMD_READ0 0x00
# define NAND_CMD_READ1 0x01
Modified: trunk/src/host/qemu-neo1973/hw/ne2000.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ne2000.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ne2000.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "pc.h"
+#include "net.h"
/* debug NE2000 card */
//#define DEBUG_NE2000
Modified: trunk/src/host/qemu-neo1973/hw/neo1973.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/neo1973.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/neo1973.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,18 @@
* This code is licensed under the GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "s3c.h"
+#include "arm-misc.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "qemu-timer.h"
+#include "devices.h"
+#include "audio/audio.h"
+#include "boards.h"
+#include "console.h"
+#include "usb.h"
+#include "net.h"
#define neo_printf(format, ...) \
fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
@@ -416,9 +427,9 @@
/* Board init. */
static void neo_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+ DisplayState *ds, const char *kernel_filename,
+ const char *kernel_cmdline, const char *initrd_filename,
+ const char *cpu_model)
{
struct neo_board_s *s = (struct neo_board_s *)
qemu_mallocz(sizeof(struct neo_board_s));
Added: trunk/src/host/qemu-neo1973/hw/nvram.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/nvram.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/nvram.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,42 @@
+#ifndef NVRAM_H
+#define NVRAM_H
+
+/* NVRAM helpers */
+typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
+typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
+typedef struct nvram_t {
+ void *opaque;
+ nvram_read_t read_fn;
+ nvram_write_t write_fn;
+} nvram_t;
+
+void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
+uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
+uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
+uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
+ const unsigned char *str, uint32_t max);
+int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
+void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
+ uint32_t start, uint32_t count);
+int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
+ const unsigned char *arch,
+ uint32_t RAM_size, int boot_device,
+ uint32_t kernel_image, uint32_t kernel_size,
+ const char *cmdline,
+ uint32_t initrd_image, uint32_t initrd_size,
+ uint32_t NVRAM_image,
+ int width, int height, int depth);
+typedef struct m48t59_t m48t59_t;
+
+void m48t59_write (void *private, uint32_t addr, uint32_t val);
+uint32_t m48t59_read (void *private, uint32_t addr);
+void m48t59_toggle_lock (void *private, int lock);
+m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
+ uint32_t io_base, uint16_t size,
+ int type);
+void m48t59_set_addr (void *opaque, uint32_t addr);
+
+#endif /* !NVRAM_H */
Modified: trunk/src/host/qemu-neo1973/hw/omap.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -18,8 +18,13 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "omap.h"
+#include "sysemu.h"
+#include "qemu-timer.h"
+/* We use pc-style serial ports. */
+#include "pc.h"
/* Should signal the TCMI */
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
@@ -992,7 +997,8 @@
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
if (on) {
- s->delay = ticks_per_sec >> 7;
+ /* TODO: make a clever calculation */
+ s->delay = ticks_per_sec >> 8;
if (s->run_count)
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
} else {
@@ -3036,7 +3042,7 @@
omap_badwidth_write16,
};
-void omap_mpuio_reset(struct omap_mpuio_s *s)
+static void omap_mpuio_reset(struct omap_mpuio_s *s)
{
s->inputs = 0;
s->outputs = 0;
@@ -3252,7 +3258,7 @@
omap_badwidth_write16,
};
-void omap_gpio_reset(struct omap_gpio_s *s)
+static void omap_gpio_reset(struct omap_gpio_s *s)
{
s->inputs = 0;
s->outputs = ~0;
@@ -3424,7 +3430,7 @@
omap_badwidth_write16,
};
-void omap_uwire_reset(struct omap_uwire_s *s)
+static void omap_uwire_reset(struct omap_uwire_s *s)
{
s->control = 0;
s->setup[0] = 0;
@@ -3465,7 +3471,7 @@
}
/* Pseudonoise Pulse-Width Light Modulator */
-void omap_pwl_update(struct omap_mpu_state_s *s)
+static void omap_pwl_update(struct omap_mpu_state_s *s)
{
int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
@@ -3523,7 +3529,7 @@
omap_badwidth_write8,
};
-void omap_pwl_reset(struct omap_mpu_state_s *s)
+static void omap_pwl_reset(struct omap_mpu_state_s *s)
{
s->pwl.output = 0;
s->pwl.level = 0;
@@ -3627,7 +3633,7 @@
omap_badwidth_write8,
};
-void omap_pwt_reset(struct omap_mpu_state_s *s)
+static void omap_pwt_reset(struct omap_mpu_state_s *s)
{
s->pwt.frc = 0;
s->pwt.vrc = 0;
@@ -4032,7 +4038,7 @@
qemu_mod_timer(s->clk, s->tick);
}
-void omap_rtc_reset(struct omap_rtc_s *s)
+static void omap_rtc_reset(struct omap_rtc_s *s)
{
s->interrupts = 0;
s->comp_reg = 0;
@@ -4092,8 +4098,11 @@
int tx_rate;
int rx_rate;
int tx_req;
+ int rx_req;
struct i2s_codec_s *codec;
+ QEMUTimer *source_timer;
+ QEMUTimer *sink_timer;
};
static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
@@ -4129,90 +4138,151 @@
qemu_set_irq(s->txirq, irq);
}
-static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
+static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
{
- int prev = s->tx_req;
-
- s->tx_req = (s->tx_rate ||
- (s->spcr[0] & (1 << 12))) && /* CLKSTP */
- (s->spcr[1] & (1 << 6)) && /* GRST */
- (s->spcr[1] & (1 << 0)); /* XRST */
-
- if (!s->tx_req && prev) {
- s->spcr[1] &= ~(1 << 1); /* XRDY */
- qemu_irq_lower(s->txdrq);
- omap_mcbsp_intr_update(s);
-
- if (s->codec)
- s->codec->tx_swallow(s->codec->opaque);
- } else if (s->codec && s->tx_req && !prev) {
- s->spcr[1] |= 1 << 1; /* XRDY */
- qemu_irq_raise(s->txdrq);
- omap_mcbsp_intr_update(s);
- }
+ if ((s->spcr[0] >> 1) & 1) /* RRDY */
+ s->spcr[0] |= 1 << 2; /* RFULL */
+ s->spcr[0] |= 1 << 1; /* RRDY */
+ qemu_irq_raise(s->rxdrq);
+ omap_mcbsp_intr_update(s);
}
-static void omap_mcbsp_rate_update(struct omap_mcbsp_s *s)
+static void omap_mcbsp_source_tick(void *opaque)
{
- int rx_clk = 0, tx_clk = 0;
- int cpu_rate = 1500000; /* XXX */
- if (!s->codec)
+ struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
+
+ if (!s->rx_rate)
return;
+ if (s->rx_req)
+ printf("%s: Rx FIFO overrun\n", __FUNCTION__);
- if (s->spcr[1] & (1 << 6)) { /* GRST */
- if (s->spcr[0] & (1 << 0)) /* RRST */
- if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
- (s->pcr & (1 << 8))) /* CLKRM */
- if (~s->pcr & (1 << 7)) /* SCLKME */
- rx_clk = cpu_rate /
- ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
- if (s->spcr[1] & (1 << 0)) /* XRST */
- if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
- (s->pcr & (1 << 9))) /* CLKXM */
- if (~s->pcr & (1 << 7)) /* SCLKME */
- tx_clk = cpu_rate /
- ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
- }
+ s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
- s->codec->set_rate(s->codec->opaque, rx_clk, tx_clk);
+ omap_mcbsp_rx_newdata(s);
+ qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
}
static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
{
- if (!(s->spcr[0] & 1)) { /* RRST */
- if (s->codec)
- s->codec->in.len = 0;
- return;
+ if (!s->codec || !s->codec->rts)
+ omap_mcbsp_source_tick(s);
+ else if (s->codec->in.len) {
+ s->rx_req = s->codec->in.len;
+ omap_mcbsp_rx_newdata(s);
}
-
- if ((s->spcr[0] >> 1) & 1) /* RRDY */
- s->spcr[0] |= 1 << 2; /* RFULL */
- s->spcr[0] |= 1 << 1; /* RRDY */
- qemu_irq_raise(s->rxdrq);
- omap_mcbsp_intr_update(s);
}
static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
{
+ qemu_del_timer(s->source_timer);
+}
+
+static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
+{
s->spcr[0] &= ~(1 << 1); /* RRDY */
qemu_irq_lower(s->rxdrq);
omap_mcbsp_intr_update(s);
}
-static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
+static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
{
- if (s->tx_rate)
+ s->spcr[1] |= 1 << 1; /* XRDY */
+ qemu_irq_raise(s->txdrq);
+ omap_mcbsp_intr_update(s);
+}
+
+static void omap_mcbsp_sink_tick(void *opaque)
+{
+ struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
+
+ if (!s->tx_rate)
return;
- s->tx_rate = 1;
- omap_mcbsp_req_update(s);
+ if (s->tx_req)
+ printf("%s: Tx FIFO underrun\n", __FUNCTION__);
+
+ s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
+
+ omap_mcbsp_tx_newdata(s);
+ qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
}
+static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
+{
+ if (!s->codec || !s->codec->cts)
+ omap_mcbsp_sink_tick(s);
+ else if (s->codec->out.size) {
+ s->tx_req = s->codec->out.size;
+ omap_mcbsp_tx_newdata(s);
+ }
+}
+
+static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
+{
+ s->spcr[1] &= ~(1 << 1); /* XRDY */
+ qemu_irq_lower(s->txdrq);
+ omap_mcbsp_intr_update(s);
+ if (s->codec && s->codec->cts)
+ s->codec->tx_swallow(s->codec->opaque);
+}
+
static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
{
- s->tx_rate = 0;
- omap_mcbsp_req_update(s);
+ s->tx_req = 0;
+ omap_mcbsp_tx_done(s);
+ qemu_del_timer(s->sink_timer);
}
+static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
+{
+ int prev_rx_rate, prev_tx_rate;
+ int rx_rate = 0, tx_rate = 0;
+ int cpu_rate = 1500000; /* XXX */
+
+ /* TODO: check CLKSTP bit */
+ if (s->spcr[1] & (1 << 6)) { /* GRST */
+ if (s->spcr[0] & (1 << 0)) { /* RRST */
+ if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
+ (s->pcr & (1 << 8))) { /* CLKRM */
+ if (~s->pcr & (1 << 7)) /* SCLKME */
+ rx_rate = cpu_rate /
+ ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
+ } else
+ if (s->codec)
+ rx_rate = s->codec->rx_rate;
+ }
+
+ if (s->spcr[1] & (1 << 0)) { /* XRST */
+ if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
+ (s->pcr & (1 << 9))) { /* CLKXM */
+ if (~s->pcr & (1 << 7)) /* SCLKME */
+ tx_rate = cpu_rate /
+ ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
+ } else
+ if (s->codec)
+ tx_rate = s->codec->tx_rate;
+ }
+ }
+ prev_tx_rate = s->tx_rate;
+ prev_rx_rate = s->rx_rate;
+ s->tx_rate = tx_rate;
+ s->rx_rate = rx_rate;
+
+ if (s->codec)
+ s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
+
+ if (!prev_tx_rate && tx_rate)
+ omap_mcbsp_tx_start(s);
+ else if (s->tx_rate && !tx_rate)
+ omap_mcbsp_tx_stop(s);
+
+ if (!prev_rx_rate && rx_rate)
+ omap_mcbsp_rx_start(s);
+ else if (prev_tx_rate && !tx_rate)
+ omap_mcbsp_rx_stop(s);
+}
+
static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -4225,17 +4295,19 @@
return 0x0000;
/* Fall through. */
case 0x02: /* DRR1 */
- if (!s->codec)
- return 0x0000;
- if (s->codec->in.len < 2) {
+ if (s->rx_req < 2) {
printf("%s: Rx FIFO underrun\n", __FUNCTION__);
- omap_mcbsp_rx_stop(s);
+ omap_mcbsp_rx_done(s);
} else {
- s->codec->in.len -= 2;
- ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
- ret |= s->codec->in.fifo[s->codec->in.start ++];
- if (!s->codec->in.len)
- omap_mcbsp_rx_stop(s);
+ s->tx_req -= 2;
+ if (s->codec && s->codec->in.len >= 2) {
+ ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
+ ret |= s->codec->in.fifo[s->codec->in.start ++];
+ s->codec->in.len -= 2;
+ } else
+ ret = 0x0000;
+ if (!s->tx_req)
+ omap_mcbsp_rx_done(s);
return ret;
}
return 0x0000;
@@ -4304,7 +4376,7 @@
return 0;
}
-static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -4321,18 +4393,14 @@
return;
/* Fall through. */
case 0x06: /* DXR1 */
- if (!s->codec)
- return;
- if (s->tx_req) {
- if (s->codec->out.len > s->codec->out.size - 2) {
- printf("%s: Tx FIFO overrun\n", __FUNCTION__);
- omap_mcbsp_tx_stop(s);
- } else {
+ if (s->tx_req > 1) {
+ s->tx_req -= 2;
+ if (s->codec && s->codec->cts) {
s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
- if (s->codec->out.len >= s->codec->out.size)
- omap_mcbsp_tx_stop(s);
}
+ if (s->tx_req < 2)
+ omap_mcbsp_tx_done(s);
} else
printf("%s: Tx FIFO overrun\n", __FUNCTION__);
return;
@@ -4341,14 +4409,8 @@
s->spcr[1] &= 0x0002;
s->spcr[1] |= 0x03f9 & value;
s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
- if (~value & 1) { /* XRST */
+ if (~value & 1) /* XRST */
s->spcr[1] &= ~6;
- qemu_irq_lower(s->rxdrq);
- if (s->codec)
- s->codec->out.len = 0;
- }
- if (s->codec)
- omap_mcbsp_rate_update(s);
omap_mcbsp_req_update(s);
return;
case 0x0a: /* SPCR1 */
@@ -4358,12 +4420,9 @@
printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
if (~value & 1) { /* RRST */
s->spcr[0] &= ~6;
- qemu_irq_lower(s->txdrq);
- if (s->codec)
- s->codec->in.len = 0;
+ s->rx_req = 0;
+ omap_mcbsp_rx_done(s);
}
- if (s->codec)
- omap_mcbsp_rate_update(s);
omap_mcbsp_req_update(s);
return;
@@ -4381,11 +4440,11 @@
return;
case 0x14: /* SRGR2 */
s->srgr[1] = value & 0xffff;
- omap_mcbsp_rate_update(s);
+ omap_mcbsp_req_update(s);
return;
case 0x16: /* SRGR1 */
s->srgr[0] = value & 0xffff;
- omap_mcbsp_rate_update(s);
+ omap_mcbsp_req_update(s);
return;
case 0x18: /* MCR2 */
s->mcr[1] = value & 0x03e3;
@@ -4455,6 +4514,37 @@
OMAP_BAD_REG(addr);
}
+static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ int offset = addr & OMAP_MPUI_REG_MASK;
+
+ if (offset == 0x04) { /* DXR */
+ if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
+ return;
+ if (s->tx_req > 3) {
+ s->tx_req -= 4;
+ if (s->codec && s->codec->cts) {
+ s->codec->out.fifo[s->codec->out.len ++] =
+ (value >> 24) & 0xff;
+ s->codec->out.fifo[s->codec->out.len ++] =
+ (value >> 16) & 0xff;
+ s->codec->out.fifo[s->codec->out.len ++] =
+ (value >> 8) & 0xff;
+ s->codec->out.fifo[s->codec->out.len ++] =
+ (value >> 0) & 0xff;
+ }
+ if (s->tx_req < 4)
+ omap_mcbsp_tx_done(s);
+ } else
+ printf("%s: Tx FIFO overrun\n", __FUNCTION__);
+ return;
+ }
+
+ omap_badwidth_write16(opaque, addr, value);
+}
+
static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
omap_badwidth_read16,
omap_mcbsp_read,
@@ -4463,8 +4553,8 @@
static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
omap_badwidth_write16,
- omap_mcbsp_write,
- omap_badwidth_write16,
+ omap_mcbsp_writeh,
+ omap_mcbsp_writew,
};
static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
@@ -4479,8 +4569,11 @@
memset(&s->rcer, 0, sizeof(s->rcer));
memset(&s->xcer, 0, sizeof(s->xcer));
s->tx_req = 0;
+ s->rx_req = 0;
s->tx_rate = 0;
s->rx_rate = 0;
+ qemu_del_timer(s->source_timer);
+ qemu_del_timer(s->sink_timer);
}
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
@@ -4495,6 +4588,8 @@
s->rxirq = irq[1];
s->txdrq = dma[0];
s->rxdrq = dma[1];
+ s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
+ s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
@@ -4504,18 +4599,24 @@
return s;
}
-void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
- omap_mcbsp_rx_start(s);
+ if (s->rx_rate) {
+ s->rx_req = s->codec->in.len;
+ omap_mcbsp_rx_newdata(s);
+ }
}
-void omap_mcbsp_i2s_start(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
- omap_mcbsp_tx_start(s);
+ if (s->tx_rate) {
+ s->tx_req = s->codec->out.size;
+ omap_mcbsp_tx_newdata(s);
+ }
}
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
@@ -4716,7 +4817,7 @@
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
- s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN],
+ s->mmc = omap_mmc_init(0xfffb7800, sd_bdrv, s->irq[1][OMAP_INT_OQN],
&s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
s->mpuio = omap_mpuio_init(0xfffb5000,
Modified: trunk/src/host/qemu-neo1973/hw/omap.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -491,6 +491,11 @@
qemu_irq rx_swallow;
qemu_irq tx_start;
+ int tx_rate;
+ int cts;
+ int rx_rate;
+ int rts;
+
struct i2s_fifo_s {
uint8_t *fifo;
int len;
@@ -513,6 +518,7 @@
/* omap_mmc.c */
struct omap_mmc_s;
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+ BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
void omap_mmc_reset(struct omap_mmc_s *s);
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
@@ -661,6 +667,9 @@
# error TARGET_PHYS_ADDR_BITS undefined
# endif
+uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+ uint32_t value);
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value);
@@ -788,4 +797,10 @@
# define cpu_register_io_memory debug_register_io_memory
# endif
+/* Not really omap specific, but is the only thing that uses the
+ uwire interface. */
+/* tsc210x.c */
+struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
+struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
+
#endif /* hw_omap_h */
Modified: trunk/src/host/qemu-neo1973/hw/omap1_clk.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap1_clk.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap1_clk.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -20,7 +20,8 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "omap.h"
struct clk {
const char *name;
Modified: trunk/src/host/qemu-neo1973/hw/omap_i2c.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap_i2c.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap_i2c.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -18,7 +18,9 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "omap.h"
struct omap_i2c_s {
target_phys_addr_t base;
Modified: trunk/src/host/qemu-neo1973/hw/omap_lcdc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap_lcdc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap_lcdc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -18,7 +18,9 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "omap.h"
struct omap_lcd_panel_s {
target_phys_addr_t base;
@@ -112,7 +114,7 @@
[32] = draw_line16_32,
};
-void omap_update_display(void *opaque)
+static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
draw_line_func *draw_line;
@@ -287,7 +289,7 @@
return 0;
}
-void omap_screen_dump(void *opaque, const char *filename) {
+static void omap_screen_dump(void *opaque, const char *filename) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_update_display(opaque);
if (omap_lcd && omap_lcd->state->data)
@@ -296,12 +298,12 @@
omap_lcd->state->linesize);
}
-void omap_invalidate_display(void *opaque) {
+static void omap_invalidate_display(void *opaque) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_lcd->invalidate = 1;
}
-void omap_lcd_update(struct omap_lcd_panel_s *s) {
+static void omap_lcd_update(struct omap_lcd_panel_s *s) {
if (!s->enable) {
s->dma->current_frame = -1;
s->sync_error = 0;
Modified: trunk/src/host/qemu-neo1973/hw/omap_mmc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/omap_mmc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/omap_mmc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -18,14 +18,14 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "omap.h"
#include "sd.h"
struct omap_mmc_s {
target_phys_addr_t base;
qemu_irq irq;
qemu_irq *dma;
- qemu_irq handler[2];
omap_clk clk;
SDState *card;
uint16_t last_cmd;
@@ -507,23 +507,8 @@
host->transfer = 0;
}
-static void omap_mmc_ro_cb(void *opaque, int level)
-{
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
-
- if (s->handler[0])
- qemu_set_irq(s->handler[0], level);
-}
-
-static void omap_mmc_cover_cb(void *opaque, int level)
-{
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
-
- if (s->handler[1])
- qemu_set_irq(s->handler[1], level);
-}
-
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+ BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
int iomemtype;
@@ -540,15 +525,12 @@
cpu_register_physical_memory(s->base, 0x800, iomemtype);
/* Instantiate the storage */
- s->card = sd_init(sd_bdrv);
+ s->card = sd_init(bd);
- sd_set_cb(s->card, s, omap_mmc_ro_cb, omap_mmc_cover_cb);
-
return s;
}
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
{
- s->handler[0] = ro;
- s->handler[1] = cover;
+ sd_set_cb(s->card, ro, cover);
}
Modified: trunk/src/host/qemu-neo1973/hw/openpic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/openpic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/openpic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -32,7 +32,9 @@
* Serial interrupts, as implemented in Raven chipset are not supported yet.
*
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc_mac.h"
+#include "pci.h"
//#define DEBUG_OPENPIC
Modified: trunk/src/host/qemu-neo1973/hw/palm.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/palm.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/palm.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -18,7 +18,13 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "audio/audio.h"
+#include "sysemu.h"
+#include "console.h"
+#include "omap.h"
+#include "boards.h"
+#include "arm-misc.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
@@ -179,7 +185,6 @@
static void palmte_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/parallel.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/parallel.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/parallel.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-char.h"
+#include "isa.h"
+#include "pc.h"
//#define DEBUG_PARALLEL
@@ -455,45 +458,45 @@
}
/* Memory mapped interface */
-uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
}
-void parallel_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writeb (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}
-uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}
-void parallel_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writew (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}
-uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
}
-void parallel_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writel (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
Modified: trunk/src/host/qemu-neo1973/hw/pc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,16 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "block.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
@@ -308,7 +317,7 @@
/***********************************************************/
/* Bochs BIOS debug ports */
-void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
+static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
{
static const char shutdown_str[8] = "Shutdown";
static int shutdown_index = 0;
@@ -352,7 +361,7 @@
}
}
-void bochs_bios_init(void)
+static void bochs_bios_init(void)
{
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
@@ -422,8 +431,8 @@
bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));
}
-int load_kernel(const char *filename, uint8_t *addr,
- uint8_t *real_addr)
+static int load_kernel(const char *filename, uint8_t *addr,
+ uint8_t *real_addr)
{
int fd, size;
int setup_sects;
@@ -684,8 +693,8 @@
}
/* PC hardware initialisation */
-static void pc_init1(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+static void pc_init1(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
int pci_enabled, const char *cpu_model)
@@ -973,30 +982,26 @@
#endif
}
-static void pc_init_pci(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename,
- int snapshot,
+static void pc_init_pci(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
- pc_init1(ram_size, vga_ram_size, boot_device,
- ds, fd_filename, snapshot,
+ pc_init1(ram_size, vga_ram_size, boot_device, ds,
kernel_filename, kernel_cmdline,
initrd_filename, 1, cpu_model);
}
-static void pc_init_isa(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename,
- int snapshot,
+static void pc_init_isa(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
- pc_init1(ram_size, vga_ram_size, boot_device,
- ds, fd_filename, snapshot,
+ pc_init1(ram_size, vga_ram_size, boot_device, ds,
kernel_filename, kernel_cmdline,
initrd_filename, 0, cpu_model);
}
Added: trunk/src/host/qemu-neo1973/hw/pc.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pc.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pc.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,145 @@
+#ifndef HW_PC_H
+#define HW_PC_H
+/* PC-style peripherals (also used by other machines). */
+
+/* serial.c */
+
+SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
+SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
+ qemu_irq irq, CharDriverState *chr,
+ int ioregister);
+uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
+void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
+uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
+void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
+uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
+void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
+
+/* parallel.c */
+
+typedef struct ParallelState ParallelState;
+ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
+ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
+
+/* i8259.c */
+
+typedef struct PicState2 PicState2;
+extern PicState2 *isa_pic;
+void pic_set_irq(int irq, int level);
+void pic_set_irq_new(void *opaque, int irq, int level);
+qemu_irq *i8259_init(qemu_irq parent_irq);
+void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
+ void *alt_irq_opaque);
+int pic_read_irq(PicState2 *s);
+void pic_update_irq(PicState2 *s);
+uint32_t pic_intack_read(PicState2 *s);
+void pic_info(void);
+void irq_info(void);
+
+/* APIC */
+typedef struct IOAPICState IOAPICState;
+
+int apic_init(CPUState *env);
+int apic_accept_pic_intr(CPUState *env);
+int apic_get_interrupt(CPUState *env);
+IOAPICState *ioapic_init(void);
+void ioapic_set_irq(void *opaque, int vector, int level);
+
+/* i8254.c */
+
+#define PIT_FREQ 1193182
+
+typedef struct PITState PITState;
+
+PITState *pit_init(int base, qemu_irq irq);
+void pit_set_gate(PITState *pit, int channel, int val);
+int pit_get_gate(PITState *pit, int channel);
+int pit_get_initial_count(PITState *pit, int channel);
+int pit_get_mode(PITState *pit, int channel);
+int pit_get_out(PITState *pit, int channel, int64_t current_time);
+
+/* vmport.c */
+void vmport_init(CPUState *env);
+void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
+
+/* vmmouse.c */
+void *vmmouse_init(void *m);
+
+/* pckbd.c */
+
+void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
+void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
+ target_phys_addr_t base, int it_shift);
+
+/* mc146818rtc.c */
+
+typedef struct RTCState RTCState;
+
+RTCState *rtc_init(int base, qemu_irq irq);
+RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
+void rtc_set_memory(RTCState *s, int addr, int val);
+void rtc_set_date(RTCState *s, const struct tm *tm);
+
+/* pc.c */
+extern int fd_bootchk;
+
+void ioport_set_a20(int enable);
+int ioport_get_a20(void);
+
+/* acpi.c */
+extern int acpi_enabled;
+i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
+void acpi_bios_init(void);
+
+/* pcspk.c */
+void pcspk_init(PITState *);
+int pcspk_audio_init(AudioState *, qemu_irq *pic);
+
+/* piix_pci.c */
+PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
+void i440fx_set_smm(PCIDevice *d, int val);
+int piix3_init(PCIBus *bus, int devfn);
+void i440fx_init_memory_mappings(PCIDevice *d);
+
+int piix4_init(PCIBus *bus, int devfn);
+
+/* vga.c */
+
+#ifndef TARGET_SPARC
+#define VGA_RAM_SIZE (8192 * 1024)
+#else
+#define VGA_RAM_SIZE (9 * 1024 * 1024)
+#endif
+
+int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size);
+int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size,
+ unsigned long vga_bios_offset, int vga_bios_size);
+int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size,
+ target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
+ int it_shift);
+
+/* cirrus_vga.c */
+void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size);
+void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size);
+
+/* ide.c */
+void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
+ BlockDriverState *hd0, BlockDriverState *hd1);
+void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
+ int secondary_ide_enabled);
+void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic);
+void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic);
+
+/* ne2000.c */
+
+void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/pcf5060x.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pcf5060x.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pcf5060x.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,11 @@
* This file is licensed under GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "i2c.h"
+#include "sysemu.h"
+#include "console.h"
#define VERBOSE 1
@@ -949,8 +953,10 @@
void pcf_gpo_handler_set(i2c_slave *i2c, int line, qemu_irq handler)
{
struct pcf_s *s = (struct pcf_s *) i2c;
- if (line >= 6 || line < 0)
- cpu_abort(cpu_single_env, "%s: No GPO line %i\n", __FUNCTION__, line);
+ if (line >= 6 || line < 0) {
+ fprintf(stderr, "%s: No GPO line %i\n", __FUNCTION__, line);
+ exit(-1);
+ }
s->gpo_handler[line] = handler;
}
Modified: trunk/src/host/qemu-neo1973/hw/pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "console.h"
+#include "net.h"
//#define DEBUG_PCI
@@ -62,7 +65,7 @@
return bus;
}
-PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
+static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
{
PCIBus *bus;
bus = qemu_mallocz(sizeof(PCIBus));
@@ -156,7 +159,7 @@
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
}
-target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
+static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
{
return addr + pci_mem_base;
}
@@ -603,7 +606,7 @@
PCIBus *bus;
} PCIBridge;
-void pci_bridge_write_config(PCIDevice *d,
+static void pci_bridge_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
PCIBridge *s = (PCIBridge *)d;
Added: trunk/src/host/qemu-neo1973/hw/pci.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pci.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pci.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,138 @@
+#ifndef QEMU_PCI_H
+#define QEMU_PCI_H
+
+/* PCI includes legacy ISA access. */
+#include "isa.h"
+
+/* PCI bus */
+
+extern target_phys_addr_t pci_mem_base;
+
+typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
+ uint32_t address, uint32_t data, int len);
+typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
+ uint32_t address, int len);
+typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
+ uint32_t addr, uint32_t size, int type);
+
+#define PCI_ADDRESS_SPACE_MEM 0x00
+#define PCI_ADDRESS_SPACE_IO 0x01
+#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
+
+typedef struct PCIIORegion {
+ uint32_t addr; /* current PCI mapping address. -1 means not mapped */
+ uint32_t size;
+ uint8_t type;
+ PCIMapIORegionFunc *map_func;
+} PCIIORegion;
+
+#define PCI_ROM_SLOT 6
+#define PCI_NUM_REGIONS 7
+
+#define PCI_DEVICES_MAX 64
+
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#define PCI_COMMAND 0x04 /* 16 bits */
+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_CLASS_DEVICE 0x0a /* Device class */
+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
+#define PCI_MIN_GNT 0x3e /* 8 bits */
+#define PCI_MAX_LAT 0x3f /* 8 bits */
+
+struct PCIDevice {
+ /* PCI config space */
+ uint8_t config[256];
+
+ /* the following fields are read only */
+ PCIBus *bus;
+ int devfn;
+ char name[64];
+ PCIIORegion io_regions[PCI_NUM_REGIONS];
+
+ /* do not access the following fields */
+ PCIConfigReadFunc *config_read;
+ PCIConfigWriteFunc *config_write;
+ /* ??? This is a PC-specific hack, and should be removed. */
+ int irq_index;
+
+ /* IRQ objects for the INTA-INTD pins. */
+ qemu_irq *irq;
+
+ /* Current IRQ levels. Used internally by the generic PCI code. */
+ int irq_state[4];
+};
+
+PCIDevice *pci_register_device(PCIBus *bus, const char *name,
+ int instance_size, int devfn,
+ PCIConfigReadFunc *config_read,
+ PCIConfigWriteFunc *config_write);
+
+void pci_register_io_region(PCIDevice *pci_dev, int region_num,
+ uint32_t size, int type,
+ PCIMapIORegionFunc *map_func);
+
+uint32_t pci_default_read_config(PCIDevice *d,
+ uint32_t address, int len);
+void pci_default_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len);
+void pci_device_save(PCIDevice *s, QEMUFile *f);
+int pci_device_load(PCIDevice *s, QEMUFile *f);
+
+typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
+typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
+PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+ qemu_irq *pic, int devfn_min, int nirq);
+
+void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
+void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
+uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
+int pci_bus_num(PCIBus *s);
+void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
+
+void pci_info(void);
+PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
+ pci_map_irq_fn map_irq, const char *name);
+
+/* lsi53c895a.c */
+void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
+void *lsi_scsi_init(PCIBus *bus, int devfn);
+
+/* vmware_vga.c */
+void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size);
+
+/* usb-uhci.c */
+void usb_uhci_piix3_init(PCIBus *bus, int devfn);
+void usb_uhci_piix4_init(PCIBus *bus, int devfn);
+
+/* usb-ohci.c */
+void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
+
+/* eepro100.c */
+
+void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
+void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
+void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
+
+/* ne2000.c */
+
+void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
+
+/* rtl8139.c */
+
+void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
+
+/* pcnet.c */
+void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
+
+/* prep_pci.c */
+PCIBus *pci_prep_init(qemu_irq *pic);
+
+/* apb_pci.c */
+PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
+ qemu_irq *pic);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/pckbd.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pckbd.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pckbd.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "isa.h"
+#include "pc.h"
+#include "ps2.h"
+#include "sysemu.h"
/* debug PC keyboard */
//#define DEBUG_KBD
@@ -286,7 +290,7 @@
return ps2_read_data(s->kbd);
}
-void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
+static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
@@ -381,7 +385,7 @@
}
/* Memory mapped interface */
-uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
{
KBDState *s = opaque;
@@ -395,7 +399,7 @@
}
}
-void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
KBDState *s = opaque;
Added: trunk/src/host/qemu-neo1973/hw/pcmcia.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pcmcia.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pcmcia.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,50 @@
+/* PCMCIA/Cardbus */
+
+struct pcmcia_socket_s {
+ qemu_irq irq;
+ int attached;
+ const char *slot_string;
+ const char *card_string;
+};
+
+void pcmcia_socket_register(struct pcmcia_socket_s *socket);
+void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
+void pcmcia_info(void);
+
+struct pcmcia_card_s {
+ void *state;
+ struct pcmcia_socket_s *slot;
+ int (*attach)(void *state);
+ int (*detach)(void *state);
+ const uint8_t *cis;
+ int cis_len;
+
+ /* Only valid if attached */
+ uint8_t (*attr_read)(void *state, uint32_t address);
+ void (*attr_write)(void *state, uint32_t address, uint8_t value);
+ uint16_t (*common_read)(void *state, uint32_t address);
+ void (*common_write)(void *state, uint32_t address, uint16_t value);
+ uint16_t (*io_read)(void *state, uint32_t address);
+ void (*io_write)(void *state, uint32_t address, uint16_t value);
+};
+
+#define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
+#define CISTPL_NO_LINK 0x14 /* No Link Tuple */
+#define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
+#define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
+#define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
+#define CISTPL_CONFIG 0x1a /* Configuration Tuple */
+#define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
+#define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
+#define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
+#define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
+#define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
+#define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
+#define CISTPL_FUNCID 0x21 /* Function ID Tuple */
+#define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
+#define CISTPL_END 0xff /* Tuple End */
+#define CISTPL_ENDMARK 0xff
+
+/* dscm1xxxx.c */
+struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
+
Modified: trunk/src/host/qemu-neo1973/hw/pcnet.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pcnet.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pcnet.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -35,7 +35,10 @@
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "net.h"
+#include "qemu-timer.h"
//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
@@ -2008,6 +2011,7 @@
/* SPARC32 interface */
#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
+#include "sun4m.h"
static void parent_lance_reset(void *opaque, int irq, int level)
{
Modified: trunk/src/host/qemu-neo1973/hw/pcspk.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pcspk.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pcspk.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,11 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "isa.h"
+#include "audio/audio.h"
+#include "qemu-timer.h"
#define PCSPK_BUF_LEN 1792
#define PCSPK_SAMPLE_RATE 32000
Added: trunk/src/host/qemu-neo1973/hw/pflash_cfi01.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pflash_cfi01.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pflash_cfi01.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,614 @@
+/*
+ * CFI parallel flash with Intel command set emulation
+ *
+ * Copyright (c) 2006 Thorsten Zitterell
+ * Copyright (c) 2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
+ * Supported commands/modes are:
+ * - flash read
+ * - flash write
+ * - flash ID read
+ * - sector erase
+ * - CFI queries
+ *
+ * It does not support timings
+ * It does not support flash interleaving
+ * It does not implement software data protection as found in many real chips
+ * It does not implement erase suspend/resume commands
+ * It does not implement multiple sectors erase
+ *
+ * It does not implement much more ...
+ */
+
+#include "hw.h"
+#include "flash.h"
+#include "block.h"
+#include "qemu-timer.h"
+
+#define PFLASH_BUG(fmt, args...) \
+do { \
+ printf("PFLASH: Possible BUG - " fmt, ##args); \
+ exit(1); \
+} while(0)
+
+/* #define PFLASH_DEBUG */
+#ifdef PFLASH_DEBUG
+#define DPRINTF(fmt, args...) \
+do { \
+ printf("PFLASH: " fmt , ##args); \
+} while (0)
+#else
+#define DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+struct pflash_t {
+ BlockDriverState *bs;
+ target_ulong base;
+ target_ulong sector_len;
+ target_ulong total_len;
+ int width;
+ int wcycle; /* if 0, the flash is read normally */
+ int bypass;
+ int ro;
+ uint8_t cmd;
+ uint8_t status;
+ uint16_t ident[4];
+ uint8_t cfi_len;
+ uint8_t cfi_table[0x52];
+ target_ulong counter;
+ QEMUTimer *timer;
+ ram_addr_t off;
+ int fl_mem;
+ void *storage;
+};
+
+static void pflash_timer (void *opaque)
+{
+ pflash_t *pfl = opaque;
+
+ DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
+ /* Reset flash */
+ pfl->status ^= 0x80;
+ if (pfl->bypass) {
+ pfl->wcycle = 2;
+ } else {
+ cpu_register_physical_memory(pfl->base, pfl->total_len,
+ pfl->off | IO_MEM_ROMD | pfl->fl_mem);
+ pfl->wcycle = 0;
+ }
+ pfl->cmd = 0;
+}
+
+static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
+{
+ target_ulong boff;
+ uint32_t ret;
+ uint8_t *p;
+
+ ret = -1;
+ offset -= pfl->base;
+ boff = offset & 0xFF; /* why this here ?? */
+
+ if (pfl->width == 2)
+ boff = boff >> 1;
+ else if (pfl->width == 4)
+ boff = boff >> 2;
+
+ DPRINTF("%s: reading offset %08x under cmd %02x\n",
+ __func__, boff, pfl->cmd);
+
+ switch (pfl->cmd) {
+ case 0x00:
+ /* Flash area read */
+ p = pfl->storage;
+ switch (width) {
+ case 1:
+ ret = p[offset];
+ DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
+ break;
+ case 2:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ ret = p[offset] << 8;
+ ret |= p[offset + 1];
+#else
+ ret = p[offset];
+ ret |= p[offset + 1] << 8;
+#endif
+ DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
+ break;
+ case 4:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ ret = p[offset] << 24;
+ ret |= p[offset + 1] << 16;
+ ret |= p[offset + 2] << 8;
+ ret |= p[offset + 3];
+#else
+ ret = p[offset];
+ ret |= p[offset + 1] << 8;
+ ret |= p[offset + 1] << 8;
+ ret |= p[offset + 2] << 16;
+ ret |= p[offset + 3] << 24;
+#endif
+ DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
+ break;
+ default:
+ DPRINTF("BUG in %s\n", __func__);
+ }
+
+ break;
+ case 0x20: /* Block erase */
+ case 0x50: /* Clear status register */
+ case 0x60: /* Block /un)lock */
+ case 0x70: /* Status Register */
+ case 0xe8: /* Write block */
+ /* Status register read */
+ ret = pfl->status;
+ DPRINTF("%s: status %x\n", __func__, ret);
+ break;
+ case 0x98: /* Query mode */
+ if (boff > pfl->cfi_len)
+ ret = 0;
+ else
+ ret = pfl->cfi_table[boff];
+ break;
+ default:
+ /* This should never happen : reset state & treat it as a read */
+ DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
+ pfl->wcycle = 0;
+ pfl->cmd = 0;
+ }
+ return ret;
+}
+
+/* update flash content on disk */
+static void pflash_update(pflash_t *pfl, int offset,
+ int size)
+{
+ int offset_end;
+ if (pfl->bs) {
+ offset_end = offset + size;
+ /* round to sectors */
+ offset = offset >> 9;
+ offset_end = (offset_end + 511) >> 9;
+ bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
+ offset_end - offset);
+ }
+}
+
+static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
+ int width)
+{
+ target_ulong boff;
+ uint8_t *p;
+ uint8_t cmd;
+
+ /* WARNING: when the memory area is in ROMD mode, the offset is a
+ ram offset, not a physical address */
+ cmd = value;
+
+ if (pfl->wcycle == 0)
+ offset -= (target_ulong)(long)pfl->storage;
+ else
+ offset -= pfl->base;
+
+ DPRINTF("%s: offset %08x %08x %d wcycle 0x%x\n",
+ __func__, offset, value, width, pfl->wcycle);
+
+ /* Set the device in I/O access mode */
+ cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
+ boff = offset & (pfl->sector_len - 1);
+
+ if (pfl->width == 2)
+ boff = boff >> 1;
+ else if (pfl->width == 4)
+ boff = boff >> 2;
+
+ switch (pfl->wcycle) {
+ case 0:
+ /* read mode */
+ switch (cmd) {
+ case 0x00: /* ??? */
+ goto reset_flash;
+ case 0x20: /* Block erase */
+ p = pfl->storage;
+ offset &= ~(pfl->sector_len - 1);
+
+ DPRINTF("%s: block erase at 0x%x bytes 0x%x\n", __func__,
+ offset, pfl->sector_len);
+
+ memset(p + offset, 0xff, pfl->sector_len);
+ pflash_update(pfl, offset, pfl->sector_len);
+ pfl->status |= 0x80; /* Ready! */
+ break;
+ case 0x50: /* Clear status bits */
+ DPRINTF("%s: Clear status bits\n", __func__);
+ pfl->status = 0x0;
+ goto reset_flash;
+ case 0x60: /* Block (un)lock */
+ DPRINTF("%s: Block unlock\n", __func__);
+ break;
+ case 0x70: /* Status Register */
+ DPRINTF("%s: Read status register\n", __func__);
+ pfl->cmd = cmd;
+ return;
+ case 0x98: /* CFI query */
+ DPRINTF("%s: CFI query\n", __func__);
+ break;
+ case 0xe8: /* Write to buffer */
+ DPRINTF("%s: Write to buffer\n", __func__);
+ pfl->status |= 0x80; /* Ready! */
+ break;
+ case 0xff: /* Read array mode */
+ DPRINTF("%s: Read array mode\n", __func__);
+ goto reset_flash;
+ default:
+ goto error_flash;
+ }
+ pfl->wcycle++;
+ pfl->cmd = cmd;
+ return;
+ case 1:
+ switch (pfl->cmd) {
+ case 0x20: /* Block erase */
+ case 0x28:
+ if (cmd == 0xd0) { /* confirm */
+ pfl->wcycle = 1;
+ pfl->status |= 0x80;
+ } if (cmd == 0xff) { /* read array mode */
+ goto reset_flash;
+ } else
+ goto error_flash;
+
+ break;
+ case 0xe8:
+ DPRINTF("%s: block write of 0x%x bytes\n", __func__, cmd);
+ pfl->counter = cmd;
+ pfl->wcycle++;
+ break;
+ case 0x60:
+ if (cmd == 0xd0) {
+ pfl->wcycle = 0;
+ pfl->status |= 0x80;
+ } else if (cmd == 0x01) {
+ pfl->wcycle = 0;
+ pfl->status |= 0x80;
+ } else if (cmd == 0xff) {
+ goto reset_flash;
+ } else {
+ DPRINTF("%s: Unknown (un)locking command\n", __func__);
+ goto reset_flash;
+ }
+ break;
+ case 0x98:
+ if (cmd == 0xff) {
+ goto reset_flash;
+ } else {
+ DPRINTF("%s: leaving query mode\n", __func__);
+ }
+ break;
+ default:
+ goto error_flash;
+ }
+ return;
+ case 2:
+ switch (pfl->cmd) {
+ case 0xe8: /* Block write */
+ p = pfl->storage;
+ DPRINTF("%s: block write offset 0x%x value 0x%x counter 0x%x\n",
+ __func__, offset, value, pfl->counter);
+ switch (width) {
+ case 1:
+ p[offset] = value;
+ pflash_update(pfl, offset, 1);
+ break;
+ case 2:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ p[offset] = value >> 8;
+ p[offset + 1] = value;
+#else
+ p[offset] = value;
+ p[offset + 1] = value >> 8;
+#endif
+ pflash_update(pfl, offset, 2);
+ break;
+ case 4:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ p[offset] = value >> 24;
+ p[offset + 1] = value >> 16;
+ p[offset + 2] = value >> 8;
+ p[offset + 3] = value;
+#else
+ p[offset] = value;
+ p[offset + 1] = value >> 8;
+ p[offset + 2] = value >> 16;
+ p[offset + 3] = value >> 24;
+#endif
+ pflash_update(pfl, offset, 4);
+ break;
+ }
+
+ pfl->status |= 0x80;
+
+ if (!pfl->counter) {
+ DPRINTF("%s: block write finished\n", __func__);
+ pfl->wcycle++;
+ }
+
+ pfl->counter--;
+ break;
+ default:
+ goto error_flash;
+ }
+ return;
+ case 3: /* Confirm mode */
+ switch (pfl->cmd) {
+ case 0xe8: /* Block write */
+ if (cmd == 0xd0) {
+ pfl->wcycle = 0;
+ pfl->status |= 0x80;
+ } else {
+ DPRINTF("%s: unknown command for \"write block\"\n", __func__);
+ PFLASH_BUG("Write block confirm");
+ goto reset_flash;
+ }
+ break;
+ default:
+ goto error_flash;
+ }
+ return;
+ default:
+ /* Should never happen */
+ DPRINTF("%s: invalid write state\n", __func__);
+ goto reset_flash;
+ }
+ return;
+
+ error_flash:
+ printf("%s: Unimplemented flash cmd sequence "
+ "(offset 0x%x, wcycle 0x%x cmd 0x%x value 0x%x\n",
+ __func__, offset, pfl->wcycle, pfl->cmd, value);
+
+ reset_flash:
+ cpu_register_physical_memory(pfl->base, pfl->total_len,
+ pfl->off | IO_MEM_ROMD | pfl->fl_mem);
+
+ pfl->bypass = 0;
+ pfl->wcycle = 0;
+ pfl->cmd = 0;
+ return;
+}
+
+
+static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
+{
+ return pflash_read(opaque, addr, 1);
+}
+
+static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
+{
+ pflash_t *pfl = opaque;
+
+ return pflash_read(pfl, addr, 2);
+}
+
+static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
+{
+ pflash_t *pfl = opaque;
+
+ return pflash_read(pfl, addr, 4);
+}
+
+static void pflash_writeb (void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ pflash_write(opaque, addr, value, 1);
+}
+
+static void pflash_writew (void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ pflash_t *pfl = opaque;
+
+ pflash_write(pfl, addr, value, 2);
+}
+
+static void pflash_writel (void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ pflash_t *pfl = opaque;
+
+ pflash_write(pfl, addr, value, 4);
+}
+
+static CPUWriteMemoryFunc *pflash_write_ops[] = {
+ &pflash_writeb,
+ &pflash_writew,
+ &pflash_writel,
+};
+
+static CPUReadMemoryFunc *pflash_read_ops[] = {
+ &pflash_readb,
+ &pflash_readw,
+ &pflash_readl,
+};
+
+/* Count trailing zeroes of a 32 bits quantity */
+static int ctz32 (uint32_t n)
+{
+ int ret;
+
+ ret = 0;
+ if (!(n & 0xFFFF)) {
+ ret += 16;
+ n = n >> 16;
+ }
+ if (!(n & 0xFF)) {
+ ret += 8;
+ n = n >> 8;
+ }
+ if (!(n & 0xF)) {
+ ret += 4;
+ n = n >> 4;
+ }
+ if (!(n & 0x3)) {
+ ret += 2;
+ n = n >> 2;
+ }
+ if (!(n & 0x1)) {
+ ret++;
+ n = n >> 1;
+ }
+#if 0 /* This is not necessary as n is never 0 */
+ if (!n)
+ ret++;
+#endif
+
+ return ret;
+}
+
+pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
+ BlockDriverState *bs,
+ target_ulong sector_len, int nb_blocs, int width,
+ uint16_t id0, uint16_t id1,
+ uint16_t id2, uint16_t id3)
+{
+ pflash_t *pfl;
+ target_long total_len;
+
+ total_len = sector_len * nb_blocs;
+
+ /* XXX: to be fixed */
+ if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
+ total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
+ return NULL;
+
+ pfl = qemu_mallocz(sizeof(pflash_t));
+
+ if (pfl == NULL)
+ return NULL;
+ pfl->storage = phys_ram_base + off;
+ pfl->fl_mem = cpu_register_io_memory(0,
+ pflash_read_ops, pflash_write_ops, pfl);
+ pfl->off = off;
+ cpu_register_physical_memory(base, total_len,
+ off | pfl->fl_mem | IO_MEM_ROMD);
+
+ pfl->bs = bs;
+ if (pfl->bs) {
+ /* read the initial flash content */
+ bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
+ }
+#if 0 /* XXX: there should be a bit to set up read-only,
+ * the same way the hardware does (with WP pin).
+ */
+ pfl->ro = 1;
+#else
+ pfl->ro = 0;
+#endif
+ pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
+ pfl->base = base;
+ pfl->sector_len = sector_len;
+ pfl->total_len = total_len;
+ pfl->width = width;
+ pfl->wcycle = 0;
+ pfl->cmd = 0;
+ pfl->status = 0;
+ pfl->ident[0] = id0;
+ pfl->ident[1] = id1;
+ pfl->ident[2] = id2;
+ pfl->ident[3] = id3;
+ /* Hardcoded CFI table */
+ pfl->cfi_len = 0x52;
+ /* Standard "QRY" string */
+ pfl->cfi_table[0x10] = 'Q';
+ pfl->cfi_table[0x11] = 'R';
+ pfl->cfi_table[0x12] = 'Y';
+ /* Command set (Intel) */
+ pfl->cfi_table[0x13] = 0x01;
+ pfl->cfi_table[0x14] = 0x00;
+ /* Primary extended table address (none) */
+ pfl->cfi_table[0x15] = 0x31;
+ pfl->cfi_table[0x16] = 0x00;
+ /* Alternate command set (none) */
+ pfl->cfi_table[0x17] = 0x00;
+ pfl->cfi_table[0x18] = 0x00;
+ /* Alternate extended table (none) */
+ pfl->cfi_table[0x19] = 0x00;
+ pfl->cfi_table[0x1A] = 0x00;
+ /* Vcc min */
+ pfl->cfi_table[0x1B] = 0x45;
+ /* Vcc max */
+ pfl->cfi_table[0x1C] = 0x55;
+ /* Vpp min (no Vpp pin) */
+ pfl->cfi_table[0x1D] = 0x00;
+ /* Vpp max (no Vpp pin) */
+ pfl->cfi_table[0x1E] = 0x00;
+ /* Reserved */
+ pfl->cfi_table[0x1F] = 0x07;
+ /* Timeout for min size buffer write */
+ pfl->cfi_table[0x20] = 0x07;
+ /* Typical timeout for block erase */
+ pfl->cfi_table[0x21] = 0x0a;
+ /* Typical timeout for full chip erase (4096 ms) */
+ pfl->cfi_table[0x22] = 0x00;
+ /* Reserved */
+ pfl->cfi_table[0x23] = 0x04;
+ /* Max timeout for buffer write */
+ pfl->cfi_table[0x24] = 0x04;
+ /* Max timeout for block erase */
+ pfl->cfi_table[0x25] = 0x04;
+ /* Max timeout for chip erase */
+ pfl->cfi_table[0x26] = 0x00;
+ /* Device size */
+ pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
+ /* Flash device interface (8 & 16 bits) */
+ pfl->cfi_table[0x28] = 0x02;
+ pfl->cfi_table[0x29] = 0x00;
+ /* Max number of bytes in multi-bytes write */
+ pfl->cfi_table[0x2A] = 0x04;
+ pfl->cfi_table[0x2B] = 0x00;
+ /* Number of erase block regions (uniform) */
+ pfl->cfi_table[0x2C] = 0x01;
+ /* Erase block region 1 */
+ pfl->cfi_table[0x2D] = nb_blocs - 1;
+ pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
+ pfl->cfi_table[0x2F] = sector_len >> 8;
+ pfl->cfi_table[0x30] = sector_len >> 16;
+
+ /* Extended */
+ pfl->cfi_table[0x31] = 'P';
+ pfl->cfi_table[0x32] = 'R';
+ pfl->cfi_table[0x33] = 'I';
+
+ pfl->cfi_table[0x34] = '1';
+ pfl->cfi_table[0x35] = '1';
+
+ pfl->cfi_table[0x36] = 0x00;
+ pfl->cfi_table[0x37] = 0x00;
+ pfl->cfi_table[0x38] = 0x00;
+ pfl->cfi_table[0x39] = 0x00;
+
+ pfl->cfi_table[0x3a] = 0x00;
+
+ pfl->cfi_table[0x3b] = 0x00;
+ pfl->cfi_table[0x3c] = 0x00;
+
+ return pfl;
+}
Modified: trunk/src/host/qemu-neo1973/hw/pflash_cfi02.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pflash_cfi02.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pflash_cfi02.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -36,7 +36,10 @@
* It does not implement multiple sectors erase
*/
-#include "vl.h"
+#include "hw.h"
+#include "flash.h"
+#include "qemu-timer.h"
+#include "block.h"
//#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG
Modified: trunk/src/host/qemu-neo1973/hw/piix_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/piix_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/piix_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,10 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+
typedef uint32_t pci_addr_t;
#include "pci_host.h"
@@ -311,7 +314,7 @@
return pci_device_load(d, f);
}
-int piix_init(PCIBus *bus, int devfn)
+static int piix_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
uint8_t *pci_conf;
Modified: trunk/src/host/qemu-neo1973/hw/pl011.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl011.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl011.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-char.h"
+#include "primecell.h"
typedef struct {
uint32_t base;
Modified: trunk/src/host/qemu-neo1973/hw/pl022.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl022.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl022.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
//#define DEBUG_PL022 1
Modified: trunk/src/host/qemu-neo1973/hw/pl031.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl031.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl031.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -9,7 +9,10 @@
*
*/
-#include"vl.h"
+#include "hw.h"
+#include "primecell.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
//#define DEBUG_PL031
Modified: trunk/src/host/qemu-neo1973/hw/pl050.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl050.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl050.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
+#include "ps2.h"
typedef struct {
void *dev;
Modified: trunk/src/host/qemu-neo1973/hw/pl061.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl061.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl061.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
//#define DEBUG_PL061 1
@@ -208,7 +209,7 @@
s->cr = 0xff;
}
-void pl061_set_irq(void * opaque, int irq, int level)
+static void pl061_set_irq(void * opaque, int irq, int level)
{
pl061_state *s = (pl061_state *)opaque;
uint8_t mask;
Modified: trunk/src/host/qemu-neo1973/hw/pl080.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl080.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl080.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
Modified: trunk/src/host/qemu-neo1973/hw/pl110.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl110.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl110.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GNU LGPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
+#include "console.h"
#define PL110_CR_EN 0x001
#define PL110_CR_BGR 0x100
Modified: trunk/src/host/qemu-neo1973/hw/pl181.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl181.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl181.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "primecell.h"
#include "sd.h"
//#define DEBUG_PL181 1
Modified: trunk/src/host/qemu-neo1973/hw/pl190.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pl190.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pl190.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "primecell.h"
+#include "arm-misc.h"
/* The number of virtual priority levels. 16 user vectors plus the
unvectored IRQ. Chained interrupts would require an additional level
@@ -215,7 +216,7 @@
pl190_write
};
-void pl190_reset(pl190_state *s)
+static void pl190_reset(pl190_state *s)
{
int i;
Modified: trunk/src/host/qemu-neo1973/hw/ppc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "nvram.h"
//#define PPC_DEBUG_IRQ
//#define PPC_DEBUG_TB
@@ -172,7 +176,8 @@
void ppc6xx_irq_init (CPUState *env)
{
- env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
+ PPC6xx_INPUT_NB);
}
#if defined(TARGET_PPC64)
@@ -295,7 +300,8 @@
void ppc970_irq_init (CPUState *env)
{
- env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
+ PPC970_INPUT_NB);
}
#endif /* defined(TARGET_PPC64) */
@@ -428,13 +434,11 @@
uint64_t decr_next; /* Tick for next decr interrupt */
uint32_t decr_freq; /* decrementer frequency */
struct QEMUTimer *decr_timer;
-#if defined(TARGET_PPC64H)
/* Hypervisor decrementer management */
uint64_t hdecr_next; /* Tick for next hdecr interrupt */
struct QEMUTimer *hdecr_timer;
uint64_t purr_load;
uint64_t purr_start;
-#endif
void *opaque;
};
@@ -643,7 +647,6 @@
return _cpu_ppc_load_decr(env, &tb_env->decr_next);
}
-#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -660,7 +663,6 @@
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
}
-#endif /* defined(TARGET_PPC64H) */
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
@@ -736,14 +738,15 @@
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
-#if defined(TARGET_PPC64H)
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
- __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
- &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
+ if (tb_env->hdecr_timer != NULL) {
+ __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
+ &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
+ }
}
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
@@ -763,7 +766,6 @@
tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock(vm_clock);
}
-#endif /* defined(TARGET_PPC64H) */
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
@@ -777,10 +779,8 @@
* it's not ready to handle it...
*/
_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
-#if defined(TARGET_PPC64H)
_cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
cpu_ppc_store_purr(env, 0x0000000000000000ULL);
-#endif /* defined(TARGET_PPC64H) */
}
/* Set up (once) timebase frequency (in Hz) */
@@ -794,9 +794,13 @@
env->tb_env = tb_env;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
-#if defined(TARGET_PPC64H)
- tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
-#endif /* defined(TARGET_PPC64H) */
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor decrementer
+ */
+ tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
+ } else {
+ tb_env->hdecr_timer = NULL;
+ }
cpu_ppc_set_tb_clk(env, freq);
return &cpu_ppc_set_tb_clk;
Added: trunk/src/host/qemu-neo1973/hw/ppc.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,31 @@
+/* PowerPC hardware exceptions management helpers */
+typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
+typedef struct clk_setup_t clk_setup_t;
+struct clk_setup_t {
+ clk_setup_cb cb;
+ void *opaque;
+};
+static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
+{
+ if (clk->cb != NULL)
+ (*clk->cb)(clk->opaque, freq);
+}
+
+clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
+/* Embedded PowerPC DCR management */
+typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
+typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
+int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
+ int (*dcr_write_error)(int dcrn));
+int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
+ dcr_read_cb drc_read, dcr_write_cb dcr_write);
+clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
+/* Embedded PowerPC reset */
+void ppc40x_core_reset (CPUState *env);
+void ppc40x_chip_reset (CPUState *env);
+void ppc40x_system_reset (CPUState *env);
+void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
+
+extern CPUWriteMemoryFunc *PPC_io_write[];
+extern CPUReadMemoryFunc *PPC_io_read[];
+void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
Modified: trunk/src/host/qemu-neo1973/hw/ppc405_boards.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc405_boards.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc405_boards.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,14 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
#include "ppc405.h"
+#include "nvram.h"
+#include "flash.h"
+#include "sysemu.h"
+#include "block.h"
+#include "boards.h"
extern int loglevel;
extern FILE *logfile;
@@ -173,7 +179,6 @@
static void ref405ep_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
@@ -499,7 +504,6 @@
static void taihu_405ep_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
Modified: trunk/src/host/qemu-neo1973/hw/ppc405_uc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc405_uc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc405_uc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,12 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
#include "ppc405.h"
+#include "pc.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
extern int loglevel;
extern FILE *logfile;
Modified: trunk/src/host/qemu-neo1973/hw/ppc4xx_devs.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc4xx_devs.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc4xx_devs.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
#include "ppc4xx.h"
+#include "sysemu.h"
extern int loglevel;
extern FILE *logfile;
Modified: trunk/src/host/qemu-neo1973/hw/ppc_chrp.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc_chrp.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc_chrp.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,8 +22,15 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
#include "ppc_mac.h"
+#include "nvram.h"
+#include "pc.h"
+#include "pci.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
/* UniN device */
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
@@ -50,7 +57,6 @@
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
Modified: trunk/src/host/qemu-neo1973/hw/ppc_mac.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc_mac.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc_mac.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -68,4 +68,58 @@
uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
+/* adb.c */
+
+#define MAX_ADB_DEVICES 16
+
+#define ADB_MAX_OUT_LEN 16
+
+typedef struct ADBDevice ADBDevice;
+
+/* buf = NULL means polling */
+typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
+ const uint8_t *buf, int len);
+typedef int ADBDeviceReset(ADBDevice *d);
+
+struct ADBDevice {
+ struct ADBBusState *bus;
+ int devaddr;
+ int handler;
+ ADBDeviceRequest *devreq;
+ ADBDeviceReset *devreset;
+ void *opaque;
+};
+
+typedef struct ADBBusState {
+ ADBDevice devices[MAX_ADB_DEVICES];
+ int nb_devices;
+ int poll_index;
+} ADBBusState;
+
+int adb_request(ADBBusState *s, uint8_t *buf_out,
+ const uint8_t *buf, int len);
+int adb_poll(ADBBusState *s, uint8_t *buf_out);
+
+ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
+ ADBDeviceRequest *devreq,
+ ADBDeviceReset *devreset,
+ void *opaque);
+void adb_kbd_init(ADBBusState *bus);
+void adb_mouse_init(ADBBusState *bus);
+
+extern ADBBusState adb_bus;
+
+/* openpic.c */
+/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
+enum {
+ OPENPIC_OUTPUT_INT = 0, /* IRQ */
+ OPENPIC_OUTPUT_CINT, /* critical IRQ */
+ OPENPIC_OUTPUT_MCK, /* Machine check event */
+ OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
+ OPENPIC_OUTPUT_RESET, /* Core reset event */
+ OPENPIC_OUTPUT_NB,
+};
+qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
+ qemu_irq **irqs, qemu_irq irq_out);
+
#endif /* !defined(__PPC_MAC_H__) */
Modified: trunk/src/host/qemu-neo1973/hw/ppc_oldworld.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc_oldworld.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc_oldworld.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,8 +22,16 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc.h"
#include "ppc_mac.h"
+#include "nvram.h"
+#include "pc.h"
+#include "sysemu.h"
+#include "net.h"
+#include "isa.h"
+#include "pci.h"
+#include "boards.h"
/* temporary frame buffer OSI calls for the video.x driver. The right
solution is to modify the driver to use VGA PCI I/Os */
@@ -94,7 +102,6 @@
static void ppc_heathrow_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
Modified: trunk/src/host/qemu-neo1973/hw/ppc_prep.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ppc_prep.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ppc_prep.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,16 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "nvram.h"
+#include "pc.h"
+#include "fdc.h"
+#include "net.h"
+#include "sysemu.h"
+#include "isa.h"
+#include "pci.h"
+#include "ppc.h"
+#include "boards.h"
//#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO
@@ -522,9 +531,8 @@
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (int ram_size, int vga_ram_size,
- const char *boot_device,
- DisplayState *ds, const char **fd_filename,
- int snapshot, const char *kernel_filename,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
@@ -556,8 +564,13 @@
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);
}
- /* Set time-base frequency to 100 Mhz */
- cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+ if (env->flags & POWERPC_FLAG_RTC_CLK) {
+ /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
+ cpu_ppc_tb_init(env, 7812500UL);
+ } else {
+ /* Set time-base frequency to 100 Mhz */
+ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+ }
qemu_register_reset(&cpu_ppc_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
envs[i] = env;
Modified: trunk/src/host/qemu-neo1973/hw/prep_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/prep_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/prep_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,9 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+
typedef uint32_t pci_addr_t;
#include "pci_host.h"
Added: trunk/src/host/qemu-neo1973/hw/primecell.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/primecell.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/primecell.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,59 @@
+#ifndef PRIMECELL_H
+#define PRIMECELL_H
+
+/* Declarations for ARM PrimeCell based periperals. */
+/* Also includes some devices that are currently only used by the
+ ARM boards. */
+
+/* pl031.c */
+void pl031_init(uint32_t base, qemu_irq irq);
+
+/* pl110.c */
+void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
+
+/* pl011.c */
+enum pl011_type {
+ PL011_ARM,
+ PL011_LUMINARY
+};
+
+void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr,
+ enum pl011_type type);
+
+/* pl022.c */
+void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int),
+ void *opaque);
+
+/* pl050.c */
+void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
+
+/* pl061.c */
+qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
+
+/* pl080.c */
+void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
+
+/* pl181.c */
+void pl181_init(uint32_t base, BlockDriverState *bd,
+ qemu_irq irq0, qemu_irq irq1);
+
+/* pl190.c */
+qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
+
+/* realview_gic.c */
+qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
+
+/* mpcore.c */
+extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
+
+/* arm-timer.c */
+void sp804_init(uint32_t base, qemu_irq irq);
+void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
+
+/* arm_sysctl.c */
+void arm_sysctl_init(uint32_t base, uint32_t sys_id);
+
+/* versatile_pci.c */
+PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/ps2.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ps2.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ps2.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ps2.h"
+#include "console.h"
/* debug PC keyboard */
//#define DEBUG_KBD
Added: trunk/src/host/qemu-neo1973/hw/ps2.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ps2.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ps2.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,10 @@
+/* ps2.c */
+void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
+void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
+void ps2_write_mouse(void *, int val);
+void ps2_write_keyboard(void *, int val);
+uint32_t ps2_read_data(void *);
+void ps2_queue(void *, int b);
+void ps2_keyboard_set_translation(void *opaque, int mode);
+void ps2_mouse_fake_event(void *opaque);
+
Modified: trunk/src/host/qemu-neo1973/hw/ptimer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ptimer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ptimer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -5,7 +5,8 @@
*
* This code is licenced under the GNU LGPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
struct ptimer_state
Modified: trunk/src/host/qemu-neo1973/hw/pxa.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -72,11 +72,10 @@
struct pxa2xx_gpio_info_s;
struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, qemu_irq *pic, int lines);
-void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
-void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
- gpio_handler_t handler, void *opaque);
-void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
- void (*handler)(void *opaque), void *opaque);
+qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
+void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
+ int line, qemu_irq handler);
+void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
/* pxa2xx_dma.c */
struct pxa2xx_dma_state_s;
@@ -90,17 +89,15 @@
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
qemu_irq irq, DisplayState *ds);
-void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
- void (*cb)(void *opaque), void *opaque);
+void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
struct pxa2xx_mmci_s;
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
- qemu_irq irq, void *dma);
-void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
- void (*readonly_cb)(void *, int),
- void (*coverswitch_cb)(void *, int));
+ BlockDriverState *bd, qemu_irq irq, void *dma);
+void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
+ qemu_irq coverswitch);
/* pxa2xx_pcmcia.c */
struct pxa2xx_pcmcia_s;
@@ -126,6 +123,7 @@
struct pxa2xx_state_s {
CPUState *env;
qemu_irq *pic;
+ qemu_irq reset;
struct pxa2xx_dma_state_s *dma;
struct pxa2xx_gpio_info_s *gpio;
struct pxa2xx_lcdc_s *lcd;
@@ -209,6 +207,4 @@
const char *revision);
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);
-void pxa2xx_reset(int line, int level, void *opaque);
-
#endif /* PXA_H */
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,14 @@
* This code is licenced under the GPL.
*/
-# include "vl.h"
+#include "hw.h"
+#include "pxa.h"
+#include "sysemu.h"
+#include "pc.h"
+#include "i2c.h"
+#include "qemu-timer.h"
+#include "qemu-char.h"
+#include "devices.h"
static struct {
target_phys_addr_t io_base;
@@ -2013,9 +2020,10 @@
return s;
}
-void pxa2xx_reset(int line, int level, void *opaque)
+static void pxa2xx_reset(void *opaque, int line, int level)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
cpu_reset(s->env);
/* TODO: reset peripherals */
@@ -2046,6 +2054,8 @@
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
s->env);
+ s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
+
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
@@ -2061,7 +2071,8 @@
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
- s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
+ s->mmc = pxa2xx_mmci_init(0x41100000, sd_bdrv, s->pic[PXA2XX_PIC_MMC],
+ s->dma);
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
@@ -2139,7 +2150,7 @@
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
- pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
+ pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
return s;
}
@@ -2161,6 +2172,8 @@
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
s->env);
+ s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
+
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
@@ -2175,7 +2188,8 @@
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
- s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
+ s->mmc = pxa2xx_mmci_init(0x41100000, sd_bdrv, s->pic[PXA2XX_PIC_MMC],
+ s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
if (serial_hds[i])
@@ -2253,6 +2267,6 @@
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
- pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
+ pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
return s;
}
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_dma.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_dma.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_dma.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pxa.h"
struct pxa2xx_dma_channel_s {
target_phys_addr_t descr;
@@ -347,8 +348,10 @@
if (value & DCSR_NODESCFETCH) {
/* No-descriptor-fetch mode */
- if (value & DCSR_RUN)
+ if (value & DCSR_RUN) {
+ s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_run(s);
+ }
} else {
/* Descriptor-fetch mode */
if (value & DCSR_RUN) {
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_gpio.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_gpio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_gpio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licensed under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pxa.h"
#define PXA2XX_GPIO_BANKS 4
@@ -16,6 +17,7 @@
qemu_irq *pic;
int lines;
CPUState *cpu_env;
+ qemu_irq *in;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@@ -28,13 +30,8 @@
uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
uint32_t prev_level[PXA2XX_GPIO_BANKS];
- struct {
- gpio_handler_t fn;
- void *opaque;
- } handler[PXA2XX_GPIO_BANKS * 32];
-
- void (*read_notify)(void *opaque);
- void *opaque;
+ qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
+ qemu_irq read_notify;
};
static struct {
@@ -86,12 +83,13 @@
}
/* Bitmap of pins used as standby and sleep wake-up sources. */
-const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
+static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};
-void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level)
+static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
+ struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
int bank;
uint32_t mask;
@@ -130,9 +128,7 @@
for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
bit = ffs(diff) - 1;
line = bit + 32 * i;
- if (s->handler[line].fn)
- s->handler[line].fn(line, (level >> bit) & 1,
- s->handler[line].opaque);
+ qemu_set_irq(s->handler[line], (level >> bit) & 1);
}
s->prev_level[i] = level;
@@ -158,6 +154,11 @@
__FUNCTION__, offset);
return s->gpsr[bank]; /* Return last written value. */
+ case GPCR: /* GPIO Pin-Output Clear registers */
+ printf("%s: Read from a write-only register " REG_FMT "\n",
+ __FUNCTION__, offset);
+ return 31337; /* Specified as unpredictable in the docs. */
+
case GRER: /* GPIO Rising-Edge Detect Enable registers */
return s->rising[bank];
@@ -173,8 +174,7 @@
case GPLR: /* GPIO Pin-Level registers */
ret = (s->olevel[bank] & s->dir[bank]) |
(s->ilevel[bank] & ~s->dir[bank]);
- if (s->read_notify)
- s->read_notify(s->opaque);
+ qemu_irq_raise(s->read_notify);
return ret;
case GEDR: /* GPIO Edge Detect Status registers */
@@ -312,6 +312,7 @@
s->pic = pic;
s->lines = lines;
s->cpu_env = env;
+ s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
pxa2xx_gpio_writefn, s);
@@ -323,23 +324,27 @@
return s;
}
-void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
- gpio_handler_t handler, void *opaque) {
+qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s)
+{
+ return s->in;
+}
+
+void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
+ int line, qemu_irq handler)
+{
if (line >= s->lines) {
printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
return;
}
- s->handler[line].fn = handler;
- s->handler[line].opaque = opaque;
+ s->handler[line] = handler;
}
/*
* Registers a callback to notify on GPLR reads. This normally
* shouldn't be needed but it is used for the hack on Spitz machines.
*/
-void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
- void (*handler)(void *opaque), void *opaque) {
+void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
+{
s->read_notify = handler;
- s->opaque = opaque;
}
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_lcd.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_lcd.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_lcd.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,12 @@
* This code is licensed under the GPLv2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "pxa.h"
#include "pixel_ops.h"
+/* FIXME: For graphic_rotate. Should probably be done in common code. */
+#include "sysemu.h"
typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
@@ -62,8 +66,7 @@
uint32_t command;
} dma_ch[7];
- void (*vsync_cb)(void *opaque);
- void *opaque;
+ qemu_irq vsync_cb;
int orientation;
};
@@ -865,8 +868,7 @@
dpy_update(s->ds, 0, miny, s->xres, maxy);
pxa2xx_lcdc_int_update(s);
- if (s->vsync_cb)
- s->vsync_cb(s->opaque);
+ qemu_irq_raise(s->vsync_cb);
}
static void pxa2xx_invalidate_display(void *opaque)
@@ -880,7 +882,7 @@
/* TODO */
}
-void pxa2xx_lcdc_orientation(void *opaque, int angle)
+static void pxa2xx_lcdc_orientation(void *opaque, int angle)
{
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
@@ -1042,8 +1044,7 @@
return s;
}
-void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
- void (*cb)(void *opaque), void *opaque) {
- s->vsync_cb = cb;
- s->opaque = opaque;
+void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
+{
+ s->vsync_cb = handler;
}
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_mmci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_mmci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_mmci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,8 @@
* This code is licensed under the GPLv2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pxa.h"
#include "sd.h"
struct pxa2xx_mmci_s {
@@ -522,7 +523,7 @@
}
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
- qemu_irq irq, void *dma)
+ BlockDriverState *bd, qemu_irq irq, void *dma)
{
int iomemtype;
struct pxa2xx_mmci_s *s;
@@ -537,7 +538,7 @@
cpu_register_physical_memory(base, 0x00100000, iomemtype);
/* Instantiate the actual storage */
- s->card = sd_init(sd_bdrv);
+ s->card = sd_init(bd);
register_savevm("pxa2xx_mmci", 0, 0,
pxa2xx_mmci_save, pxa2xx_mmci_load, s);
@@ -545,9 +546,8 @@
return s;
}
-void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
- void (*readonly_cb)(void *, int),
- void (*coverswitch_cb)(void *, int))
+void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
+ qemu_irq coverswitch)
{
- sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb);
+ sd_set_cb(s->card, readonly, coverswitch);
}
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_pcmcia.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_pcmcia.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_pcmcia.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licensed under the GPLv2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pcmcia.h"
+#include "pxa.h"
struct pxa2xx_pcmcia_s {
struct pcmcia_socket_s slot;
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_pic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_pic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_pic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pxa.h"
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
#define ICMR 0x04 /* Interrupt Controller Mask register */
Modified: trunk/src/host/qemu-neo1973/hw/pxa2xx_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/pxa2xx_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/pxa2xx_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,10 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "pxa.h"
#define OSMR0 0x00
#define OSMR1 0x04
Modified: trunk/src/host/qemu-neo1973/hw/r2d.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/r2d.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/r2d.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,13 +22,16 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "sysemu.h"
+#include "boards.h"
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
-static void r2d_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState * ds, const char **fd_filename, int snapshot,
+static void r2d_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/realview.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/realview.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/realview.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,14 +7,19 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "primecell.h"
+#include "devices.h"
+#include "pci.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
/* Board init. */
static void realview_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/realview_gic.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/realview_gic.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/realview_gic.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,8 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "primecell.h"
#define GIC_NIRQ 96
#define NCPU 1
Modified: trunk/src/host/qemu-neo1973/hw/rtl8139.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/rtl8139.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/rtl8139.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -43,7 +43,10 @@
* Added rx/tx buffer reset when enabling rx/tx operation
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "net.h"
/* debug RTL8139 card */
//#define DEBUG_RTL8139 1
@@ -494,7 +497,7 @@
} RTL8139State;
-void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
+static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
{
DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
@@ -540,7 +543,7 @@
}
}
-void prom9346_shift_clock(EEprom9346 *eeprom)
+static void prom9346_shift_clock(EEprom9346 *eeprom)
{
int bit = eeprom->eedi?1:0;
@@ -632,7 +635,7 @@
}
}
-int prom9346_get_wire(RTL8139State *s)
+static int prom9346_get_wire(RTL8139State *s)
{
EEprom9346 *eeprom = &s->eeprom;
if (!eeprom->eecs)
@@ -641,7 +644,8 @@
return eeprom->eedo;
}
-void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
+/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
+static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
{
EEprom9346 *eeprom = &s->eeprom;
uint8_t old_eecs = eeprom->eecs;
@@ -1445,7 +1449,7 @@
return ret;
}
-int rtl8139_config_writeable(RTL8139State *s)
+static int rtl8139_config_writeable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{
Modified: trunk/src/host/qemu-neo1973/hw/s3c.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -9,7 +9,8 @@
#ifndef S3C_H
# define S3C_H "s3c.h"
-# include "arm_pic.h"
+# include "qemu-common.h"
+# include "flash.h"
/* Interrupt numbers */
# define S3C_PIC_EINT0 0
@@ -110,6 +111,9 @@
struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic);
qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s);
+/* GPIO TODO: remove this out, replace with qemu_irq or sumpthin */
+typedef void (*gpio_handler_t)(int line, int level, void *opaque);
+
struct s3c_timers_state_s;
struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
qemu_irq *pic, qemu_irq *dma);
Modified: trunk/src/host/qemu-neo1973/hw/s3c2410.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c2410.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c2410.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,17 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "s3c.h"
+#include "qemu-timer.h"
+#include "qemu-char.h"
+#include "hw.h"
+#include "console.h"
+#include "devices.h"
+#include "arm-misc.h"
+#include "i2c.h"
+#include "sysemu.h"
+
/* Interrupt controller */
struct s3c_pic_state_s {
target_phys_addr_t base;
Modified: trunk/src/host/qemu-neo1973/hw/s3c24xx_gpio.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c24xx_gpio.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c24xx_gpio.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,10 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "s3c.h"
+#include "hw.h"
+
#define S3C_IO_BANKS 8
struct s3c_gpio_state_s { /* Modelled as an interrupt controller */
Modified: trunk/src/host/qemu-neo1973/hw/s3c24xx_lcd.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c24xx_lcd.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c24xx_lcd.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,11 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "s3c.h"
+#include "hw.h"
+#include "console.h"
+
typedef void (*s3c_drawfn_t)(uint32_t *, uint8_t *, const uint8_t *, int, int);
struct s3c_lcd_state_s {
Modified: trunk/src/host/qemu-neo1973/hw/s3c24xx_mmci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c24xx_mmci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c24xx_mmci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,11 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+
+#include "s3c.h"
#include "sd.h"
+#include "hw.h"
+#include "sysemu.h"
struct s3c_mmci_state_s {
target_phys_addr_t base;
@@ -440,5 +443,5 @@
void (*readonly_cb)(void *, int),
void (*coverswitch_cb)(void *, int))
{
- sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb);
+ /*sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb);*/
}
Modified: trunk/src/host/qemu-neo1973/hw/s3c24xx_rtc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c24xx_rtc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c24xx_rtc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,12 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "s3c.h"
+#include "qemu-timer.h"
+#include "hw.h"
+#include "sysemu.h"
+
struct s3c_rtc_state_s {
target_phys_addr_t base;
qemu_irq irq;
Modified: trunk/src/host/qemu-neo1973/hw/s3c24xx_udc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/s3c24xx_udc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/s3c24xx_udc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -6,8 +6,11 @@
*
* This code is licenced under the GNU GPL v2.
*/
-#include "vl.h"
+#include "s3c.h"
+#include "usb.h"
+#include "hw.h"
+
#define S3C_USB_FIFO_LEN 4096
struct s3c_udc_state_s {
Modified: trunk/src/host/qemu-neo1973/hw/sb16.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sb16.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sb16.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "audiodev.h"
+#include "audio/audio.h"
+#include "isa.h"
+#include "qemu-timer.h"
#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
Modified: trunk/src/host/qemu-neo1973/hw/scsi-disk.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/scsi-disk.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/scsi-disk.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -25,7 +25,9 @@
#define BADF(fmt, args...) \
do { fprintf(stderr, "scsi-disk: " fmt , ##args); } while (0)
-#include "vl.h"
+#include "qemu-common.h"
+#include "block.h"
+#include "scsi-disk.h"
#define SENSE_NO_SENSE 0
#define SENSE_NOT_READY 2
Added: trunk/src/host/qemu-neo1973/hw/scsi-disk.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/scsi-disk.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/scsi-disk.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,33 @@
+#ifndef SCSI_DISK_H
+#define SCSI_DISK_H
+
+/* scsi-disk.c */
+enum scsi_reason {
+ SCSI_REASON_DONE, /* Command complete. */
+ SCSI_REASON_DATA /* Transfer complete, more data required. */
+};
+
+typedef struct SCSIDevice SCSIDevice;
+typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
+ uint32_t arg);
+
+SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
+ int tcq,
+ scsi_completionfn completion,
+ void *opaque);
+void scsi_disk_destroy(SCSIDevice *s);
+
+int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
+/* SCSI data transfers are asynchrnonous. However, unlike the block IO
+ layer the completion routine may be called directly by
+ scsi_{read,write}_data. */
+void scsi_read_data(SCSIDevice *s, uint32_t tag);
+int scsi_write_data(SCSIDevice *s, uint32_t tag);
+void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
+uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
+
+/* cdrom.c */
+int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
+int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/sd.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sd.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sd.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -29,6 +29,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "hw.h"
+#include "block.h"
#include "sd.h"
//#define DEBUG_SD 1
@@ -90,9 +92,8 @@
uint32_t data_start;
uint32_t data_offset;
uint8_t data[512];
- void (*readonly_cb)(void *, int);
- void (*inserted_cb)(void *, int);
- void *opaque;
+ qemu_irq readonly_cb;
+ qemu_irq inserted_cb;
BlockDriverState *bdrv;
};
@@ -307,8 +308,8 @@
return sd_crc7(buffer, 5) != req->crc; /* TODO */
}
-void sd_response_r1_make(SDState *sd,
- uint8_t *response, uint32_t last_status)
+static void sd_response_r1_make(SDState *sd,
+ uint8_t *response, uint32_t last_status)
{
uint32_t mask = CARD_STATUS_B ^ ILLEGAL_COMMAND;
uint32_t status;
@@ -322,7 +323,7 @@
response[3] = (status >> 0) & 0xff;
}
-void sd_response_r3_make(SDState *sd, uint8_t *response)
+static void sd_response_r3_make(SDState *sd, uint8_t *response)
{
response[0] = (sd->ocr >> 24) & 0xff;
response[1] = (sd->ocr >> 16) & 0xff;
@@ -330,7 +331,7 @@
response[3] = (sd->ocr >> 0) & 0xff;
}
-void sd_response_r6_make(SDState *sd, uint8_t *response)
+static void sd_response_r6_make(SDState *sd, uint8_t *response)
{
uint16_t arg;
uint16_t status;
@@ -372,9 +373,10 @@
sd->bdrv = bdrv;
+ if (sd->wp_groups)
+ qemu_free(sd->wp_groups);
sd->wp_switch = bdrv_is_read_only(bdrv);
sd->wp_groups = (int *) qemu_mallocz(sizeof(int) * sect);
- memset(sd->wp_groups, 0, sizeof(int) * sect);
memset(sd->function_group, 0, sizeof(int) * 6);
sd->erase_start = 0;
sd->erase_end = 0;
@@ -386,12 +388,10 @@
static void sd_cardchange(void *opaque)
{
SDState *sd = opaque;
- if (sd->inserted_cb)
- sd->inserted_cb(sd->opaque, bdrv_is_inserted(sd->bdrv));
+ qemu_set_irq(sd->inserted_cb, bdrv_is_inserted(sd->bdrv));
if (bdrv_is_inserted(sd->bdrv)) {
sd_reset(sd, sd->bdrv);
- if (sd->readonly_cb)
- sd->readonly_cb(sd->opaque, sd->wp_switch);
+ qemu_set_irq(sd->readonly_cb, sd->wp_switch);
}
}
@@ -401,21 +401,16 @@
sd = (SDState *) qemu_mallocz(sizeof(SDState));
sd_reset(sd, bs);
+ bdrv_set_change_cb(sd->bdrv, sd_cardchange, sd);
return sd;
}
-void sd_set_cb(SDState *sd, void *opaque,
- void (*readonly_cb)(void *, int),
- void (*inserted_cb)(void *, int))
+void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert)
{
- sd->opaque = opaque;
- sd->readonly_cb = readonly_cb;
- sd->inserted_cb = inserted_cb;
- if (sd->readonly_cb)
- sd->readonly_cb(sd->opaque, bdrv_is_read_only(sd->bdrv));
- if (sd->inserted_cb)
- sd->inserted_cb(sd->opaque, bdrv_is_inserted(sd->bdrv));
- bdrv_set_change_cb(sd->bdrv, sd_cardchange, sd);
+ sd->readonly_cb = readonly;
+ sd->inserted_cb = insert;
+ qemu_set_irq(readonly, bdrv_is_read_only(sd->bdrv));
+ qemu_set_irq(insert, bdrv_is_inserted(sd->bdrv));
}
static void sd_erase(SDState *sd)
Modified: trunk/src/host/qemu-neo1973/hw/sd.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sd.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sd.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -29,8 +29,6 @@
#ifndef __hw_sd_h
#define __hw_sd_h 1
-#include <vl.h>
-
#define OUT_OF_RANGE (1 << 31)
#define ADDRESS_ERROR (1 << 30)
#define BLOCK_LEN_ERROR (1 << 29)
@@ -74,9 +72,7 @@
uint8_t *response);
void sd_write_data(SDState *sd, uint8_t value);
uint8_t sd_read_data(SDState *sd);
-void sd_set_cb(SDState *sd, void *opaque,
- void (*readonly_cb)(void *, int),
- void (*inserted_cb)(void *, int));
+void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert);
int sd_data_ready(SDState *sd);
#endif /* __hw_sd_h */
Modified: trunk/src/host/qemu-neo1973/hw/serial.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/serial.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/serial.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-char.h"
+#include "isa.h"
+#include "pc.h"
//#define DEBUG_SERIAL
Added: trunk/src/host/qemu-neo1973/hw/sh.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,38 @@
+#ifndef QEMU_SH_H
+#define QEMU_SH_H
+/* Definitions for SH board emulation. */
+
+/* sh7750.c */
+struct SH7750State;
+
+struct SH7750State *sh7750_init(CPUState * cpu);
+
+typedef struct {
+ /* The callback will be triggered if any of the designated lines change */
+ uint16_t portamask_trigger;
+ uint16_t portbmask_trigger;
+ /* Return 0 if no action was taken */
+ int (*port_change_cb) (uint16_t porta, uint16_t portb,
+ uint16_t * periph_pdtra,
+ uint16_t * periph_portdira,
+ uint16_t * periph_pdtrb,
+ uint16_t * periph_portdirb);
+} sh7750_io_device;
+
+int sh7750_register_io_device(struct SH7750State *s,
+ sh7750_io_device * device);
+/* sh_timer.c */
+#define TMU012_FEAT_TOCR (1 << 0)
+#define TMU012_FEAT_3CHAN (1 << 1)
+#define TMU012_FEAT_EXTCLK (1 << 2)
+void tmu012_init(uint32_t base, int feat, uint32_t freq);
+
+/* sh_serial.c */
+#define SH_SERIAL_FEAT_SCIF (1 << 0)
+void sh_serial_init (target_phys_addr_t base, int feat,
+ uint32_t freq, CharDriverState *chr);
+
+/* tc58128.c */
+int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/sh7750.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh7750.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh7750.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,7 +24,9 @@
*/
#include <stdio.h>
#include <assert.h>
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "sysemu.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
#include "sh_intc.h"
Modified: trunk/src/host/qemu-neo1973/hw/sh7750_regnames.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh7750_regnames.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh7750_regnames.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,4 +1,5 @@
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
#include "sh7750_regs.h"
#define REGNAME(r) {r, #r},
Modified: trunk/src/host/qemu-neo1973/hw/sh_intc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh_intc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh_intc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -10,7 +10,8 @@
#include <assert.h>
#include "sh_intc.h"
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
//#define DEBUG_INTC
Modified: trunk/src/host/qemu-neo1973/hw/sh_serial.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh_serial.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh_serial.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,7 +24,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "qemu-char.h"
#include <assert.h>
//#define DEBUG_SERIAL
@@ -250,14 +252,14 @@
sh_serial_receive_break(s);
}
-uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
+static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
sh_serial_state *s = opaque;
return sh_serial_ioport_read(s, addr - s->base);
}
-void sh_serial_write (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void sh_serial_write (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
{
sh_serial_state *s = opaque;
sh_serial_ioport_write(s, addr - s->base, value);
Modified: trunk/src/host/qemu-neo1973/hw/sh_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sh_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sh_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -8,7 +8,9 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "qemu-timer.h"
//#define DEBUG_TIMER
@@ -50,7 +52,7 @@
#endif
}
-uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
Modified: trunk/src/host/qemu-neo1973/hw/shix.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/shix.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/shix.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -27,7 +27,10 @@
More information in target-sh4/README.sh4
*/
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "sysemu.h"
+#include "boards.h"
#define BIOS_FILENAME "shix_bios.bin"
#define BIOS_ADDRESS 0xA0000000
@@ -62,8 +65,8 @@
/* XXXXX */
}
-static void shix_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState * ds, const char **fd_filename, int snapshot,
+static void shix_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/slavio_intctl.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/slavio_intctl.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/slavio_intctl.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "console.h"
+
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ
@@ -65,6 +68,12 @@
#define INTCTLM_MAXADDR 0x13
#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
#define INTCTLM_MASK 0x1f
+#define MASTER_IRQ_MASK ~0x4fb2007f
+#define MASTER_DISABLE 0x80000000
+#define CPU_IRQ_MASK 0xfffe0000
+#define CPU_IRQ_INT15_IN 0x0004000
+#define CPU_IRQ_INT15_MASK 0x80000000
+
static void slavio_check_interrupts(void *opaque);
// per-cpu interrupt controller
@@ -100,15 +109,15 @@
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
switch (saddr) {
case 1: // clear pending softints
- if (val & 0x4000)
- val |= 80000000;
- val &= 0xfffe0000;
+ if (val & CPU_IRQ_INT15_IN)
+ val |= CPU_IRQ_INT15_MASK;
+ val &= CPU_IRQ_MASK;
s->intreg_pending[cpu] &= ~val;
slavio_check_interrupts(s);
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
break;
case 2: // set softint
- val &= 0xfffe0000;
+ val &= CPU_IRQ_MASK;
s->intreg_pending[cpu] |= val;
slavio_check_interrupts(s);
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
@@ -139,7 +148,7 @@
saddr = (addr & INTCTLM_MAXADDR) >> 2;
switch (saddr) {
case 0:
- ret = s->intregm_pending & 0x7fffffff;
+ ret = s->intregm_pending & ~MASTER_DISABLE;
break;
case 1:
ret = s->intregm_disabled;
@@ -166,14 +175,14 @@
switch (saddr) {
case 2: // clear (enable)
// Force clear unused bits
- val &= ~0x4fb2007f;
+ val &= MASTER_IRQ_MASK;
s->intregm_disabled &= ~val;
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
slavio_check_interrupts(s);
break;
case 3: // set (disable, clear pending)
// Force clear unused bits
- val &= ~0x4fb2007f;
+ val &= MASTER_IRQ_MASK;
s->intregm_disabled |= val;
s->intregm_pending &= ~val;
slavio_check_interrupts(s);
@@ -241,14 +250,14 @@
DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
for (i = 0; i < MAX_CPUS; i++) {
pil_pending = 0;
- if (pending && !(s->intregm_disabled & 0x80000000) &&
+ if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
(i == s->target_cpu)) {
for (j = 0; j < 32; j++) {
if (pending & (1 << j))
pil_pending |= 1 << s->intbit_to_level[j];
}
}
- pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe;
+ pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16;
for (j = 0; j < MAX_PILS; j++) {
if (pil_pending & (1 << j)) {
@@ -343,7 +352,7 @@
for (i = 0; i < MAX_CPUS; i++) {
s->intreg_pending[i] = 0;
}
- s->intregm_disabled = ~0xffb2007f;
+ s->intregm_disabled = ~MASTER_IRQ_MASK;
s->intregm_pending = 0;
s->target_cpu = 0;
slavio_check_interrupts(s);
Modified: trunk/src/host/qemu-neo1973/hw/slavio_misc.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/slavio_misc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/slavio_misc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "sysemu.h"
+
/* debug misc */
//#define DEBUG_MISC
Modified: trunk/src/host/qemu-neo1973/hw/slavio_serial.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/slavio_serial.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/slavio_serial.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "qemu-char.h"
+#include "console.h"
+
/* debug serial */
//#define DEBUG_SERIAL
Modified: trunk/src/host/qemu-neo1973/hw/slavio_timer.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/slavio_timer.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/slavio_timer.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "qemu-timer.h"
//#define DEBUG_TIMER
Modified: trunk/src/host/qemu-neo1973/hw/smbus.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/smbus.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/smbus.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -9,7 +9,9 @@
/* TODO: Implement PEC. */
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "smbus.h"
//#define DEBUG_SMBUS 1
@@ -59,7 +61,7 @@
}
}
-void smbus_i2c_event(i2c_slave *s, enum i2c_event event)
+static void smbus_i2c_event(i2c_slave *s, enum i2c_event event)
{
SMBusDevice *dev = (SMBusDevice *)s;
switch (event) {
@@ -194,7 +196,7 @@
SMBusDevice *dev;
if (size < sizeof(SMBusDevice))
- cpu_abort(cpu_single_env, "SMBus struct too small");
+ hw_error("SMBus struct too small");
dev = (SMBusDevice *)i2c_slave_init(bus, address, size);
dev->i2c.event = smbus_i2c_event;
Modified: trunk/src/host/qemu-neo1973/hw/smbus.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/smbus.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/smbus.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,7 @@
* THE SOFTWARE.
*/
-typedef struct SMBusDevice SMBusDevice;
+#include "i2c.h"
struct SMBusDevice {
/* The SMBus protocol is implemented on top of I2C. */
Modified: trunk/src/host/qemu-neo1973/hw/smbus_eeprom.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/smbus_eeprom.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/smbus_eeprom.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,9 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "smbus.h"
//#define DEBUG
Modified: trunk/src/host/qemu-neo1973/hw/smc91c111.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/smc91c111.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/smc91c111.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the GPL
*/
-#include "vl.h"
+#include "hw.h"
+#include "net.h"
+#include "devices.h"
/* For crc32 */
#include <zlib.h>
Modified: trunk/src/host/qemu-neo1973/hw/sparc32_dma.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sparc32_dma.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sparc32_dma.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sparc32_dma.h"
+#include "sun4m.h"
/* debug DMA */
//#define DEBUG_DMA
Added: trunk/src/host/qemu-neo1973/hw/sparc32_dma.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sparc32_dma.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sparc32_dma.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,14 @@
+#ifndef SPARC32_DMA_H
+#define SPARC32_DMA_H
+
+/* sparc32_dma.c */
+void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+ void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
+void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+ uint8_t *buf, int len, int do_bswap);
+void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+ uint8_t *buf, int len, int do_bswap);
+void espdma_memory_read(void *opaque, uint8_t *buf, int len);
+void espdma_memory_write(void *opaque, uint8_t *buf, int len);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/spitz.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/spitz.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/spitz.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,19 @@
* This code is licensed under the GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pxa.h"
+#include "arm-misc.h"
+#include "sysemu.h"
+#include "pcmcia.h"
+#include "i2c.h"
+#include "flash.h"
+#include "qemu-timer.h"
+#include "devices.h"
+#include "console.h"
+#include "block.h"
+#include "audio/audio.h"
+#include "boards.h"
#define spitz_printf(format, ...) \
fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
@@ -217,7 +229,9 @@
static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
struct spitz_keyboard_s {
- struct pxa2xx_state_s *cpu;
+ qemu_irq sense[SPITZ_KEY_SENSE_NUM];
+ qemu_irq *strobe;
+ qemu_irq gpiomap[5];
int keymap[0x80];
uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
uint16_t strobe_state;
@@ -240,28 +254,23 @@
if (strobe) {
sense |= 1 << i;
if (!(s->sense_state & (1 << i)))
- pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 1);
+ qemu_irq_raise(s->sense[i]);
} else if (s->sense_state & (1 << i))
- pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 0);
+ qemu_irq_lower(s->sense[i]);
}
s->sense_state = sense;
}
-static void spitz_keyboard_strobe(int line, int level,
- struct spitz_keyboard_s *s)
+static void spitz_keyboard_strobe(void *opaque, int line, int level)
{
- int i;
- for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
- if (spitz_gpio_key_strobe[i] == line) {
- if (level)
- s->strobe_state |= 1 << i;
- else
- s->strobe_state &= ~(1 << i);
+ struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
- spitz_keyboard_sense_update(s);
- break;
- }
+ if (level)
+ s->strobe_state |= 1 << line;
+ else
+ s->strobe_state &= ~(1 << line);
+ spitz_keyboard_sense_update(s);
}
static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
@@ -272,8 +281,7 @@
/* Handle the additional keys */
if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
- pxa2xx_gpio_set(s->cpu->gpio, spitz_gpiomap[spitz_keycode & 0xf],
- (keycode < 0x80) ^
+ qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
spitz_gpio_invert[spitz_keycode & 0xf]);
return;
}
@@ -486,7 +494,6 @@
s = (struct spitz_keyboard_s *)
qemu_mallocz(sizeof(struct spitz_keyboard_s));
memset(s, 0, sizeof(struct spitz_keyboard_s));
- s->cpu = cpu;
for (i = 0; i < 0x80; i ++)
s->keymap[i] = -1;
@@ -495,9 +502,16 @@
if (spitz_keymap[i][j] != -1)
s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
+ for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
+ s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
+
+ for (i = 0; i < 5; i ++)
+ s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
+
+ s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
+ SPITZ_KEY_STROBE_NUM);
for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
- pxa2xx_gpio_handler_set(cpu->gpio, spitz_gpio_key_strobe[i],
- (gpio_handler_t) spitz_keyboard_strobe, s);
+ pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
spitz_keyboard_pre_map(s);
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
@@ -510,15 +524,13 @@
struct scoop_info_s {
target_phys_addr_t target_base;
+ qemu_irq handler[16];
+ qemu_irq *in;
uint16_t status;
uint16_t power;
uint32_t gpio_level;
uint32_t gpio_dir;
uint32_t prev_level;
- struct {
- gpio_handler_t fn;
- void *opaque;
- } handler[16];
uint16_t mcr;
uint16_t cdr;
@@ -548,9 +560,7 @@
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
bit = ffs(diff) - 1;
- if (s->handler[bit].fn)
- s->handler[bit].fn(bit, (level >> bit) & 1,
- s->handler[bit].opaque);
+ qemu_set_irq(s->handler[bit], (level >> bit) & 1);
}
s->prev_level = level;
@@ -648,12 +658,9 @@
scoop_writeb,
};
-static inline void scoop_gpio_set(struct scoop_info_s *s, int line, int level)
+static void scoop_gpio_set(void *opaque, int line, int level)
{
- if (line >= 16) {
- spitz_printf("No GPIO pin %i\n", line);
- return;
- }
+ struct scoop_info_s *s = (struct scoop_info_s *) s;
if (level)
s->gpio_level |= (1 << line);
@@ -661,15 +668,19 @@
s->gpio_level &= ~(1 << line);
}
-static inline void scoop_gpio_handler_set(struct scoop_info_s *s, int line,
- gpio_handler_t handler, void *opaque) {
+static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
+{
+ return s->in;
+}
+
+static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line,
+ qemu_irq handler) {
if (line >= 16) {
spitz_printf("No GPIO pin %i\n", line);
return;
}
- s->handler[line].fn = handler;
- s->handler[line].opaque = opaque;
+ s->handler[line] = handler;
}
static void scoop_save(QEMUFile *f, void *opaque)
@@ -723,6 +734,7 @@
s[0].status = 0x02;
s[1].status = 0x02;
+ s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, &s[0]);
cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
@@ -731,6 +743,7 @@
if (count < 2)
return s;
+ s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, &s[1]);
cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
@@ -760,7 +773,7 @@
spitz_printf("LCD Backlight now off\n");
}
-static void spitz_bl_bit5(int line, int level, void *opaque)
+static inline void spitz_bl_bit5(void *opaque, int line, int level)
{
int prev = bl_intensity;
@@ -773,7 +786,7 @@
spitz_bl_update((struct pxa2xx_state_s *) opaque);
}
-static void spitz_bl_power(int line, int level, void *opaque)
+static inline void spitz_bl_power(void *opaque, int line, int level)
{
bl_power = !!level;
spitz_bl_update((struct pxa2xx_state_s *) opaque);
@@ -841,14 +854,19 @@
max111x_write(max1111, value);
}
-static void corgi_ssp_gpio_cs(int line, int level, struct pxa2xx_state_s *s)
+static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
{
- if (line == SPITZ_GPIO_LCDCON_CS)
+ switch (line) {
+ case 0:
lcd_en = !level;
- else if (line == SPITZ_GPIO_ADS7846_CS)
+ break;
+ case 1:
ads_en = !level;
- else if (line == SPITZ_GPIO_MAX1111_CS)
+ break;
+ case 2:
max_en = !level;
+ break;
+ }
}
#define MAX1111_BATT_VOLT 1
@@ -859,7 +877,7 @@
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
-static void spitz_adc_temp_on(int line, int level, void *opaque)
+static void spitz_adc_temp_on(void *opaque, int line, int level)
{
if (!max1111)
return;
@@ -870,12 +888,6 @@
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
}
-static void spitz_pendown_set(void *opaque, int line, int level)
-{
- struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_TP_INT, level);
-}
-
static void spitz_ssp_save(QEMUFile *f, void *opaque)
{
qemu_put_be32(f, lcd_en);
@@ -898,9 +910,11 @@
static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
{
+ qemu_irq *chipselects;
+
lcd_en = ads_en = max_en = 0;
- ads7846 = ads7846_init(qemu_allocate_irqs(spitz_pendown_set, cpu, 1)[0]);
+ ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
max1111 = max1111_init(0);
max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
@@ -910,12 +924,10 @@
pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
corgi_ssp_write, cpu);
- pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
- (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
- pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
- (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
- pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
- (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
+ chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
+ pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
+ pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
+ pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
bl_intensity = 0x20;
bl_power = 0;
@@ -945,7 +957,7 @@
#define SPITZ_GPIO_WM 5
#ifdef HAS_AUDIO
-static void spitz_wm8750_addr(int line, int level, void *opaque)
+static void spitz_wm8750_addr(void *opaque, int line, int level)
{
i2c_slave *wm = (i2c_slave *) opaque;
if (level)
@@ -970,8 +982,9 @@
/* Attach a WM8750 to the bus */
wm = wm8750_init(bus, audio);
- spitz_wm8750_addr(0, 0, wm);
- pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_WM, spitz_wm8750_addr, wm);
+ spitz_wm8750_addr(wm, 0, 0);
+ pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
+ qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
/* .. and to the sound interface. */
cpu->i2s->opaque = wm;
cpu->i2s->codec_out = wm8750_dac_dat;
@@ -989,26 +1002,33 @@
/* Other peripherals */
-static void spitz_charge_switch(int line, int level, void *opaque)
+static void spitz_out_switch(void *opaque, int line, int level)
{
- spitz_printf("Charging %s.\n", level ? "off" : "on");
+ switch (line) {
+ case 0:
+ spitz_printf("Charging %s.\n", level ? "off" : "on");
+ break;
+ case 1:
+ spitz_printf("Discharging %s.\n", level ? "on" : "off");
+ break;
+ case 2:
+ spitz_printf("Green LED %s.\n", level ? "on" : "off");
+ break;
+ case 3:
+ spitz_printf("Orange LED %s.\n", level ? "on" : "off");
+ break;
+ case 4:
+ spitz_bl_bit5(opaque, line, level);
+ break;
+ case 5:
+ spitz_bl_power(opaque, line, level);
+ break;
+ case 6:
+ spitz_adc_temp_on(opaque, line, level);
+ break;
+ }
}
-static void spitz_discharge_switch(int line, int level, void *opaque)
-{
- spitz_printf("Discharging %s.\n", level ? "on" : "off");
-}
-
-static void spitz_greenled_switch(int line, int level, void *opaque)
-{
- spitz_printf("Green LED %s.\n", level ? "on" : "off");
-}
-
-static void spitz_orangeled_switch(int line, int level, void *opaque)
-{
- spitz_printf("Orange LED %s.\n", level ? "on" : "off");
-}
-
#define SPITZ_SCP_LED_GREEN 1
#define SPITZ_SCP_JK_B 2
#define SPITZ_SCP_CHRG_ON 3
@@ -1027,24 +1047,19 @@
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
struct scoop_info_s *scp, int num)
{
- scoop_gpio_handler_set(&scp[0], SPITZ_SCP_CHRG_ON,
- spitz_charge_switch, cpu);
- scoop_gpio_handler_set(&scp[0], SPITZ_SCP_JK_B,
- spitz_discharge_switch, cpu);
- scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_GREEN,
- spitz_greenled_switch, cpu);
- scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_ORANGE,
- spitz_orangeled_switch, cpu);
+ qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
+ scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]);
+ scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]);
+ scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]);
+ scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]);
+
if (num >= 2) {
- scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT,
- spitz_bl_bit5, cpu);
- scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON,
- spitz_bl_power, cpu);
+ scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
+ scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
}
- scoop_gpio_handler_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON,
- spitz_adc_temp_on, cpu);
+ scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
}
#define SPITZ_GPIO_HSYNC 22
@@ -1057,40 +1072,18 @@
#define SPITZ_GPIO_CF2_IRQ 106
#define SPITZ_GPIO_CF2_CD 93
-int spitz_hsync;
+static int spitz_hsync;
-static void spitz_lcd_hsync_handler(void *opaque)
+static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
{
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_HSYNC, spitz_hsync);
+ qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
spitz_hsync ^= 1;
}
-static void spitz_mmc_coverswitch_change(void *opaque, int in)
-{
- struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_DETECT, in);
-}
-
-static void spitz_mmc_writeprotect_change(void *opaque, int wp)
-{
- struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_WP, wp);
-}
-
-static void spitz_pcmcia_cb(void *opaque, int line, int level)
-{
- struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
- static const int gpio_map[] = {
- SPITZ_GPIO_CF1_IRQ, SPITZ_GPIO_CF1_CD,
- SPITZ_GPIO_CF2_IRQ, SPITZ_GPIO_CF2_CD,
- };
- pxa2xx_gpio_set(cpu->gpio, gpio_map[line], level);
-}
-
static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
{
- qemu_irq *pcmcia_cb;
+ qemu_irq lcd_hsync;
/*
* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
* read to satisfy broken guests that poll-wait for hsync.
@@ -1098,25 +1091,30 @@
* wouldn't guarantee that a guest ever exits the loop.
*/
spitz_hsync = 0;
- pxa2xx_gpio_read_notifier(cpu->gpio, spitz_lcd_hsync_handler, cpu);
- pxa2xx_lcd_vsync_cb(cpu->lcd, spitz_lcd_hsync_handler, cpu);
+ lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
+ pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
+ pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
/* MMC/SD host */
- pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change,
- spitz_mmc_coverswitch_change);
+ pxa2xx_mmci_handlers(cpu->mmc,
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
/* Battery lock always closed */
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_BAT_COVER, 1);
+ qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
/* Handle reset */
- pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ON_RESET, pxa2xx_reset, cpu);
+ pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
/* PCMCIA signals: card's IRQ and Card-Detect */
- pcmcia_cb = qemu_allocate_irqs(spitz_pcmcia_cb, cpu, slots * 2);
if (slots >= 1)
- pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], pcmcia_cb[0], pcmcia_cb[1]);
+ pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
if (slots >= 2)
- pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], pcmcia_cb[2], pcmcia_cb[3]);
+ pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
+ pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
/* Initialise the screen rotation related signals */
spitz_gpio_invert[3] = 0; /* Always open */
@@ -1125,8 +1123,10 @@
} else { /* Portrait mode */
spitz_gpio_invert[4] = 1;
}
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWA, spitz_gpio_invert[3]);
- pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWB, spitz_gpio_invert[4]);
+ qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
+ spitz_gpio_invert[3]);
+ qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
+ spitz_gpio_invert[4]);
}
/* Write the bootloader parameters memory area. */
@@ -1234,7 +1234,6 @@
static void spitz_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@@ -1244,7 +1243,6 @@
static void borzoi_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@@ -1254,7 +1252,6 @@
static void akita_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@@ -1264,7 +1261,6 @@
static void terrier_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Modified: trunk/src/host/qemu-neo1973/hw/ssd0303.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ssd0303.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ssd0303.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -10,7 +10,9 @@
/* The controller can support a variety of different displays, but we only
implement one. Most of the commends relating to brightness and geometry
setup are ignored. */
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "console.h"
//#define DEBUG_SSD0303 1
Modified: trunk/src/host/qemu-neo1973/hw/ssd0323.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/ssd0323.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/ssd0323.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -10,7 +10,9 @@
/* The controller can support a variety of different displays, but we only
implement one. Most of the commends relating to brightness and geometry
setup are ignored. */
-#include "vl.h"
+#include "hw.h"
+#include "devices.h"
+#include "console.h"
//#define DEBUG_SSD0323 1
@@ -28,6 +30,12 @@
/* Scaling factor for pixels. */
#define MAGNIFY 4
+#define REMAP_SWAP_COLUMN 0x01
+#define REMAP_SWAP_NYBBLE 0x02
+#define REMAP_VERTICAL 0x04
+#define REMAP_SWAP_COM 0x10
+#define REMAP_SPLIT_COM 0x40
+
enum ssd0323_mode
{
SSD0323_CMD,
@@ -47,6 +55,7 @@
int col_start;
int col_end;
int redraw;
+ int remap;
enum ssd0323_mode mode;
uint8_t framebuffer[128 * 80 / 2];
} ssd0323_state;
@@ -58,14 +67,25 @@
case SSD0323_DATA:
DPRINTF("data 0x%02x\n", data);
s->framebuffer[s->col + s->row * 64] = data;
- s->col++;
- if (s->col > s->col_end) {
+ if (s->remap & REMAP_VERTICAL) {
s->row++;
- s->col = s->col_start;
+ if (s->row > s->row_end) {
+ s->row = s->row_start;
+ s->col++;
+ }
+ if (s->col > s->col_end) {
+ s->col = s->col_start;
+ }
+ } else {
+ s->col++;
+ if (s->col > s->col_end) {
+ s->row++;
+ s->col = s->col_start;
+ }
+ if (s->row > s->row_end) {
+ s->row = s->row_start;
+ }
}
- if (s->row > s->row_end) {
- s->row = s->row_start;
- }
s->redraw = 1;
break;
case SSD0323_CMD:
@@ -80,12 +100,12 @@
#define DATA(x) if (s->cmd_len <= (x)) return 0
case 0x15: /* Set column. */
DATA(2);
- s->col_start = s->cmd_data[0] % 64;
+ s->col = s->col_start = s->cmd_data[0] % 64;
s->col_end = s->cmd_data[1] % 64;
break;
case 0x75: /* Set row. */
DATA(2);
- s->row_start = s->cmd_data[0] % 80;
+ s->row = s->row_start = s->cmd_data[0] % 80;
s->row_end = s->cmd_data[1] % 80;
break;
case 0x81: /* Set contrast */
@@ -97,6 +117,7 @@
case 0xa0: /* Set remapping. */
/* FIXME: Implement this. */
DATA(1);
+ s->remap = s->cmd_data[0];
break;
case 0xa1: /* Set display start line. */
case 0xa2: /* Set display offset. */
@@ -205,6 +226,7 @@
}
p += dest_width;
}
+ /* TODO: Implement row/column remapping. */
dest = s->ds->data;
for (y = 0; y < 64; y++) {
line = y;
Modified: trunk/src/host/qemu-neo1973/hw/stellaris.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/stellaris.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/stellaris.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,9 +7,27 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "primecell.h"
+#include "devices.h"
+#include "qemu-timer.h"
+#include "i2c.h"
+#include "sysemu.h"
+#include "boards.h"
+#define GPIO_A 0
+#define GPIO_B 1
+#define GPIO_C 2
+#define GPIO_D 3
+#define GPIO_E 4
+#define GPIO_F 5
+#define GPIO_G 6
+
+#define BP_OLED_I2C 0x01
+#define BP_OLED_SSI 0x02
+#define BP_GAMEPAD 0x04
+
typedef const struct {
const char *name;
uint32_t did0;
@@ -19,7 +37,7 @@
uint32_t dc2;
uint32_t dc3;
uint32_t dc4;
- enum {OLED_I2C, OLED_SSI} oled;
+ uint32_t peripherals;
} stellaris_board_info;
/* General purpose timer module. */
@@ -425,7 +443,7 @@
case 0x160: /* LDOARST */
return s->ldoarst;
default:
- cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
+ cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
return 0;
}
}
@@ -498,7 +516,7 @@
s->ldoarst = value;
break;
default:
- cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
+ cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
}
ssys_update(s);
}
@@ -515,7 +533,7 @@
ssys_write
};
-void ssys_reset(void *opaque)
+static void ssys_reset(void *opaque)
{
ssys_state *s = (ssys_state *)opaque;
@@ -985,7 +1003,7 @@
0x01071013,
0x3f0f01ff,
0x0000001f,
- OLED_I2C
+ BP_OLED_I2C
},
{ "LM3S6965EVB",
0x10010002,
@@ -995,7 +1013,7 @@
0x030f5317,
0x0f0f87ff,
0x5000007f,
- OLED_SSI
+ BP_OLED_SSI | BP_GAMEPAD
}
};
@@ -1046,7 +1064,7 @@
if (board->dc2 & (1 << 12)) {
i2c = i2c_init_bus();
stellaris_i2c_init(0x40020000, pic[8], i2c);
- if (board->oled == OLED_I2C) {
+ if (board->peripherals & BP_OLED_I2C) {
ssd0303_init(ds, i2c, 0x3d);
}
}
@@ -1058,21 +1076,32 @@
}
}
if (board->dc2 & (1 << 4)) {
- if (board->oled == OLED_SSI) {
+ if (board->peripherals & BP_OLED_SSI) {
void * oled;
/* FIXME: Implement chip select for OLED/MMC. */
- oled = ssd0323_init(ds, &gpio_out[2][7]);
+ oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
pl022_init(0x40008000, pic[7], ssd0323_xfer_ssi, oled);
} else {
pl022_init(0x40008000, pic[7], NULL, NULL);
}
}
+ if (board->peripherals & BP_GAMEPAD) {
+ qemu_irq gpad_irq[5];
+ static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
+
+ gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
+ gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
+ gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
+ gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
+ gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
+
+ stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
+ }
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
static void lm3s811evb_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@@ -1081,7 +1110,6 @@
static void lm3s6965evb_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Added: trunk/src/host/qemu-neo1973/hw/stellaris_input.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/stellaris_input.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/stellaris_input.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,66 @@
+/*
+ * Gamepad style buttons connected to IRQ/GPIO lines
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licenced under the GPL.
+ */
+#include "hw.h"
+#include "devices.h"
+#include "console.h"
+
+typedef struct {
+ qemu_irq irq;
+ int keycode;
+ int pressed;
+} gamepad_button;
+
+typedef struct {
+ gamepad_button *buttons;
+ int num_buttons;
+ int extension;
+} gamepad_state;
+
+static void stellaris_gamepad_put_key(void * opaque, int keycode)
+{
+ gamepad_state *s = (gamepad_state *)opaque;
+ int i;
+ int down;
+
+ if (keycode == 0xe0 && !s->extension) {
+ s->extension = 0x80;
+ return;
+ }
+
+ down = (keycode & 0x80) == 0;
+ keycode = (keycode & 0x7f) | s->extension;
+
+ for (i = 0; i < s->num_buttons; i++) {
+ if (s->buttons[i].keycode == keycode
+ && s->buttons[i].pressed != down) {
+ s->buttons[i].pressed = down;
+ qemu_set_irq(s->buttons[i].irq, down);
+ }
+ }
+
+ s->extension = 0;
+}
+
+/* Returns an array 5 ouput slots. */
+void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
+{
+ gamepad_state *s;
+ int i;
+
+ s = (gamepad_state *)qemu_mallocz(sizeof (gamepad_state));
+ s->buttons = (gamepad_button *)qemu_mallocz(n * sizeof (gamepad_button));
+ for (i = 0; i < n; i++) {
+ s->buttons[i].irq = irq[i];
+ s->buttons[i].keycode = keycode[i];
+ }
+ s->num_buttons = n;
+ qemu_add_kbd_event_handler(stellaris_gamepad_put_key, s);
+}
+
+
Modified: trunk/src/host/qemu-neo1973/hw/sun4m.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sun4m.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sun4m.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,17 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "sun4m.h"
+#include "nvram.h"
+#include "sparc32_dma.h"
+#include "fdc.h"
+#include "sysemu.h"
+#include "net.h"
+#include "boards.h"
+#include "firmware_abi.h"
+
//#define DEBUG_IRQ
/*
@@ -69,6 +79,7 @@
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
+ uint32_t iommu_version;
uint32_t intbit_to_level[32];
};
@@ -102,131 +113,87 @@
{
}
-static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
-{
- m48t59_write(nvram, addr++, (value >> 8) & 0xff);
- m48t59_write(nvram, addr++, value & 0xff);
-}
-
-static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
-{
- m48t59_write(nvram, addr++, value >> 24);
- m48t59_write(nvram, addr++, (value >> 16) & 0xff);
- m48t59_write(nvram, addr++, (value >> 8) & 0xff);
- m48t59_write(nvram, addr++, value & 0xff);
-}
-
-static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
- const unsigned char *str, uint32_t max)
-{
- unsigned int i;
-
- for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t59_write(nvram, addr + i, str[i]);
- }
- m48t59_write(nvram, addr + max - 1, '\0');
-}
-
-static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
- const unsigned char *str)
-{
- uint32_t len;
-
- len = strlen(str) + 1;
- nvram_set_string(nvram, addr, str, len);
-
- return addr + len;
-}
-
-static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
- uint32_t end)
-{
- unsigned int i, sum;
-
- // Length divided by 16
- m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
- m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
- // Checksum
- sum = m48t59_read(nvram, start);
- for (i = 0; i < 14; i++) {
- sum += m48t59_read(nvram, start + 2 + i);
- sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
- }
- m48t59_write(nvram, start + 1, sum & 0xff);
-}
-
extern int nographic;
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
- const char *boot_device, uint32_t RAM_size,
+ const char *boot_devices, uint32_t RAM_size,
uint32_t kernel_size,
int width, int height, int depth,
int machine_id)
{
- unsigned char tmp = 0;
- unsigned int i, j;
+ unsigned int i;
uint32_t start, end;
+ uint8_t image[0x1ff0];
+ ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
+ struct sparc_arch_cfg *sparc_header;
+ struct OpenBIOS_nvpart_v1 *part_header;
+ memset(image, '\0', sizeof(image));
+
// Try to match PPC NVRAM
- nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
- nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
- // NVRAM_size, arch not applicable
- m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
- m48t59_write(nvram, 0x2E, 0);
- m48t59_write(nvram, 0x2F, nographic & 0xff);
- nvram_set_lword(nvram, 0x30, RAM_size);
- m48t59_write(nvram, 0x34, boot_device[0] & 0xff);
- nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
- nvram_set_lword(nvram, 0x3C, kernel_size);
+ strcpy(header->struct_ident, "QEMU_BIOS");
+ header->struct_version = cpu_to_be32(3); /* structure v3 */
+
+ header->nvram_size = cpu_to_be16(0x2000);
+ header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
+ header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
+ strcpy(header->arch, "sun4m");
+ header->nb_cpus = smp_cpus & 0xff;
+ header->RAM0_base = 0;
+ header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
+ strcpy(header->boot_devices, boot_devices);
+ header->nboot_devices = strlen(boot_devices) & 0xff;
+ header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
+ header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
if (cmdline) {
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
- nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
- nvram_set_lword(nvram, 0x44, strlen(cmdline));
+ header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
+ header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
}
- // initrd_image, initrd_size passed differently
- nvram_set_word(nvram, 0x54, width);
- nvram_set_word(nvram, 0x56, height);
- nvram_set_word(nvram, 0x58, depth);
+ // XXX add initrd_image, initrd_size
+ header->width = cpu_to_be16(width);
+ header->height = cpu_to_be16(height);
+ header->depth = cpu_to_be16(depth);
+ if (nographic)
+ header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
+ header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
+
+ // Architecture specific header
+ start = sizeof(ohwcfg_v3_t);
+ sparc_header = (struct sparc_arch_cfg *)&image[start];
+ sparc_header->valid = 0;
+ start += sizeof(struct sparc_arch_cfg);
+
// OpenBIOS nvram variables
// Variable partition
- start = 252;
- m48t59_write(nvram, start, 0x70);
- nvram_set_string(nvram, start + 4, "system", 12);
+ part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
+ part_header->signature = OPENBIOS_PART_SYSTEM;
+ strcpy(part_header->name, "system");
- end = start + 16;
+ end = start + sizeof(struct OpenBIOS_nvpart_v1);
for (i = 0; i < nb_prom_envs; i++)
- end = nvram_set_var(nvram, end, prom_envs[i]);
+ end = OpenBIOS_set_var(image, end, prom_envs[i]);
- m48t59_write(nvram, end++ , 0);
+ // End marker
+ image[end++] = '\0';
+
end = start + ((end - start + 15) & ~15);
- nvram_finish_partition(nvram, start, end);
+ OpenBIOS_finish_partition(part_header, end - start);
// free partition
start = end;
- m48t59_write(nvram, start, 0x7f);
- nvram_set_string(nvram, start + 4, "free", 12);
+ part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
+ part_header->signature = OPENBIOS_PART_FREE;
+ strcpy(part_header->name, "free");
end = 0x1fd0;
- nvram_finish_partition(nvram, start, end);
+ OpenBIOS_finish_partition(part_header, end - start);
- // Sun4m specific use
- start = i = 0x1fd8;
- m48t59_write(nvram, i++, 0x01);
- m48t59_write(nvram, i++, machine_id);
- j = 0;
- m48t59_write(nvram, i++, macaddr[j++]);
- m48t59_write(nvram, i++, macaddr[j++]);
- m48t59_write(nvram, i++, macaddr[j++]);
- m48t59_write(nvram, i++, macaddr[j++]);
- m48t59_write(nvram, i++, macaddr[j++]);
- m48t59_write(nvram, i, macaddr[j]);
+ Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
- /* Calculate checksum */
- for (i = start; i < start + 15; i++) {
- tmp ^= m48t59_read(nvram, i);
- }
- m48t59_write(nvram, start + 15, tmp);
+ for (i = 0; i < sizeof(image); i++)
+ m48t59_write(nvram, i, image[i]);
}
static void *slavio_intctl;
@@ -343,7 +310,7 @@
/* allocate RAM */
cpu_register_physical_memory(0, RAM_size, 0);
- iommu = iommu_init(hwdef->iommu_base);
+ iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
&hwdef->intbit_to_level[0],
@@ -509,6 +476,7 @@
.me_irq = 30,
.cs_irq = 5,
.machine_id = 0x80,
+ .iommu_version = 0x04000000,
.intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
@@ -542,6 +510,7 @@
.me_irq = 30,
.cs_irq = -1,
.machine_id = 0x72,
+ .iommu_version = 0x03000000,
.intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
@@ -575,6 +544,7 @@
.me_irq = 30,
.cs_irq = -1,
.machine_id = 0x71,
+ .iommu_version = 0x01000000,
.intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
@@ -603,10 +573,10 @@
}
/* SPARCstation 5 hardware initialisation */
-static void ss5_init(int RAM_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void ss5_init(int RAM_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
{
if (cpu_model == NULL)
cpu_model = "Fujitsu MB86904";
@@ -616,10 +586,10 @@
}
/* SPARCstation 10 hardware initialisation */
-static void ss10_init(int RAM_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void ss10_init(int RAM_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
{
if (cpu_model == NULL)
cpu_model = "TI SuperSparc II";
@@ -629,8 +599,8 @@
}
/* SPARCserver 600MP hardware initialisation */
-static void ss600mp_init(int RAM_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+static void ss600mp_init(int RAM_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
Added: trunk/src/host/qemu-neo1973/hw/sun4m.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sun4m.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sun4m.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,73 @@
+#ifndef SUN4M_H
+#define SUN4M_H
+
+/* Devices used by sparc32 system. */
+
+/* iommu.c */
+void *iommu_init(target_phys_addr_t addr, uint32_t version);
+void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+ uint8_t *buf, int len, int is_write);
+static inline void sparc_iommu_memory_read(void *opaque,
+ target_phys_addr_t addr,
+ uint8_t *buf, int len)
+{
+ sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
+}
+
+static inline void sparc_iommu_memory_write(void *opaque,
+ target_phys_addr_t addr,
+ uint8_t *buf, int len)
+{
+ sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
+}
+
+/* tcx.c */
+void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
+ unsigned long vram_offset, int vram_size, int width, int height,
+ int depth);
+
+/* slavio_intctl.c */
+void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
+ const uint32_t *intbit_to_level,
+ qemu_irq **irq, qemu_irq **cpu_irq,
+ qemu_irq **parent_irq, unsigned int cputimer);
+void slavio_pic_info(void *opaque);
+void slavio_irq_info(void *opaque);
+
+/* slavio_timer.c */
+void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
+ qemu_irq *cpu_irqs);
+
+/* slavio_serial.c */
+SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
+ CharDriverState *chr1, CharDriverState *chr2);
+void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
+
+/* slavio_misc.c */
+void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
+ qemu_irq irq);
+void slavio_set_power_fail(void *opaque, int power_failing);
+
+/* esp.c */
+void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
+void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
+ void *dma_opaque, qemu_irq irq, qemu_irq *reset);
+
+/* cs4231.c */
+void cs_init(target_phys_addr_t base, int irq, void *intctl);
+
+/* sparc32_dma.c */
+void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+ void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
+void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+ uint8_t *buf, int len, int do_bswap);
+void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+ uint8_t *buf, int len, int do_bswap);
+void espdma_memory_read(void *opaque, uint8_t *buf, int len);
+void espdma_memory_write(void *opaque, uint8_t *buf, int len);
+
+/* pcnet.c */
+void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
+ qemu_irq irq, qemu_irq *reset);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/hw/sun4u.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/sun4u.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/sun4u.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,16 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
-#include "m48t59.h"
+#include "hw.h"
+#include "pci.h"
+#include "pc.h"
+#include "nvram.h"
+#include "fdc.h"
+#include "net.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "firmware_abi.h"
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
@@ -66,180 +74,92 @@
{
}
-/* NVRAM helpers */
-static void nvram_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
-{
- m48t59_write(nvram, addr, value);
-}
-
-static uint8_t nvram_get_byte (m48t59_t *nvram, uint32_t addr)
-{
- return m48t59_read(nvram, addr);
-}
-
-static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
-{
- m48t59_write(nvram, addr++, (value >> 8) & 0xff);
- m48t59_write(nvram, addr++, value & 0xff);
-}
-
-static uint16_t nvram_get_word (m48t59_t *nvram, uint32_t addr)
-{
- uint16_t tmp;
-
- tmp = m48t59_read(nvram, addr) << 8;
- tmp |= m48t59_read(nvram, addr + 1);
-
- return tmp;
-}
-
-static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
-{
- m48t59_write(nvram, addr++, value >> 24);
- m48t59_write(nvram, addr++, (value >> 16) & 0xff);
- m48t59_write(nvram, addr++, (value >> 8) & 0xff);
- m48t59_write(nvram, addr++, value & 0xff);
-}
-
-static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
- const unsigned char *str, uint32_t max)
-{
- unsigned int i;
-
- for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t59_write(nvram, addr + i, str[i]);
- }
- m48t59_write(nvram, addr + max - 1, '\0');
-}
-
-static uint16_t nvram_crc_update (uint16_t prev, uint16_t value)
-{
- uint16_t tmp;
- uint16_t pd, pd1, pd2;
-
- tmp = prev >> 8;
- pd = prev ^ value;
- pd1 = pd & 0x000F;
- pd2 = ((pd >> 4) & 0x000F) ^ pd1;
- tmp ^= (pd1 << 3) | (pd1 << 8);
- tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
-
- return tmp;
-}
-
-static uint16_t nvram_compute_crc (m48t59_t *nvram, uint32_t start,
- uint32_t count)
-{
- uint32_t i;
- uint16_t crc = 0xFFFF;
- int odd;
-
- odd = count & 1;
- count &= ~1;
- for (i = 0; i != count; i++) {
- crc = nvram_crc_update(crc, nvram_get_word(nvram, start + i));
- }
- if (odd) {
- crc = nvram_crc_update(crc, nvram_get_byte(nvram, start + i) << 8);
- }
-
- return crc;
-}
-
-static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
- const unsigned char *str)
-{
- uint32_t len;
-
- len = strlen(str) + 1;
- nvram_set_string(nvram, addr, str, len);
-
- return addr + len;
-}
-
-static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
- uint32_t end)
-{
- unsigned int i, sum;
-
- // Length divided by 16
- m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
- m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
- // Checksum
- sum = m48t59_read(nvram, start);
- for (i = 0; i < 14; i++) {
- sum += m48t59_read(nvram, start + 2 + i);
- sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
- }
- m48t59_write(nvram, start + 1, sum & 0xff);
-}
-
extern int nographic;
-int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
- const unsigned char *arch,
- uint32_t RAM_size, int boot_device,
- uint32_t kernel_image, uint32_t kernel_size,
- const char *cmdline,
- uint32_t initrd_image, uint32_t initrd_size,
- uint32_t NVRAM_image,
- int width, int height, int depth)
+static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
+ const unsigned char *arch,
+ uint32_t RAM_size, const char *boot_devices,
+ uint32_t kernel_image, uint32_t kernel_size,
+ const char *cmdline,
+ uint32_t initrd_image, uint32_t initrd_size,
+ uint32_t NVRAM_image,
+ int width, int height, int depth)
{
- uint16_t crc;
unsigned int i;
uint32_t start, end;
+ uint8_t image[0x1ff0];
+ ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
+ struct sparc_arch_cfg *sparc_header;
+ struct OpenBIOS_nvpart_v1 *part_header;
- /* Set parameters for Open Hack'Ware BIOS */
- nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
- nvram_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
- nvram_set_word(nvram, 0x14, NVRAM_size);
- nvram_set_string(nvram, 0x20, arch, 16);
- nvram_set_byte(nvram, 0x2f, nographic & 0xff);
- nvram_set_lword(nvram, 0x30, RAM_size);
- nvram_set_byte(nvram, 0x34, boot_device);
- nvram_set_lword(nvram, 0x38, kernel_image);
- nvram_set_lword(nvram, 0x3C, kernel_size);
+ memset(image, '\0', sizeof(image));
+
+ // Try to match PPC NVRAM
+ strcpy(header->struct_ident, "QEMU_BIOS");
+ header->struct_version = cpu_to_be32(3); /* structure v3 */
+
+ header->nvram_size = cpu_to_be16(NVRAM_size);
+ header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
+ header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
+ strcpy(header->arch, arch);
+ header->nb_cpus = smp_cpus & 0xff;
+ header->RAM0_base = 0;
+ header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
+ strcpy(header->boot_devices, boot_devices);
+ header->nboot_devices = strlen(boot_devices) & 0xff;
+ header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
+ header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
if (cmdline) {
- /* XXX: put the cmdline in NVRAM too ? */
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
- nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
- nvram_set_lword(nvram, 0x44, strlen(cmdline));
- } else {
- nvram_set_lword(nvram, 0x40, 0);
- nvram_set_lword(nvram, 0x44, 0);
+ header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
+ header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
}
- nvram_set_lword(nvram, 0x48, initrd_image);
- nvram_set_lword(nvram, 0x4C, initrd_size);
- nvram_set_lword(nvram, 0x50, NVRAM_image);
+ header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
+ header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
+ header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
- nvram_set_word(nvram, 0x54, width);
- nvram_set_word(nvram, 0x56, height);
- nvram_set_word(nvram, 0x58, depth);
- crc = nvram_compute_crc(nvram, 0x00, 0xF8);
- nvram_set_word(nvram, 0xFC, crc);
+ header->width = cpu_to_be16(width);
+ header->height = cpu_to_be16(height);
+ header->depth = cpu_to_be16(depth);
+ if (nographic)
+ header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
+ header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
+
+ // Architecture specific header
+ start = sizeof(ohwcfg_v3_t);
+ sparc_header = (struct sparc_arch_cfg *)&image[start];
+ sparc_header->valid = 0;
+ start += sizeof(struct sparc_arch_cfg);
+
// OpenBIOS nvram variables
// Variable partition
- start = 256;
- m48t59_write(nvram, start, 0x70);
- nvram_set_string(nvram, start + 4, "system", 12);
+ part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
+ part_header->signature = OPENBIOS_PART_SYSTEM;
+ strcpy(part_header->name, "system");
- end = start + 16;
+ end = start + sizeof(struct OpenBIOS_nvpart_v1);
for (i = 0; i < nb_prom_envs; i++)
- end = nvram_set_var(nvram, end, prom_envs[i]);
+ end = OpenBIOS_set_var(image, end, prom_envs[i]);
- m48t59_write(nvram, end++ , 0);
+ // End marker
+ image[end++] = '\0';
+
end = start + ((end - start + 15) & ~15);
- nvram_finish_partition(nvram, start, end);
+ OpenBIOS_finish_partition(part_header, end - start);
// free partition
start = end;
- m48t59_write(nvram, start, 0x7f);
- nvram_set_string(nvram, start + 4, "free", 12);
+ part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
+ part_header->signature = OPENBIOS_PART_FREE;
+ strcpy(part_header->name, "free");
end = 0x1fd0;
- nvram_finish_partition(nvram, start, end);
+ OpenBIOS_finish_partition(part_header, end - start);
+ for (i = 0; i < sizeof(image); i++)
+ m48t59_write(nvram, i, image[i]);
+
return 0;
}
@@ -306,10 +226,10 @@
static fdctrl_t *floppy_controller;
/* Sun4u hardware initialisation */
-static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void sun4u_init(int ram_size, int vga_ram_size,
+ const char *boot_devices, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
char buf[1024];
@@ -428,7 +348,7 @@
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
- sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0],
+ sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
KERNEL_LOAD_ADDR, kernel_size,
kernel_cmdline,
INITRD_LOAD_ADDR, initrd_size,
Modified: trunk/src/host/qemu-neo1973/hw/tc58128.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/tc58128.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/tc58128.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,5 +1,7 @@
#include <assert.h>
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "sysemu.h"
#define CE1 0x0100
#define CE2 0x0200
Modified: trunk/src/host/qemu-neo1973/hw/tcx.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/tcx.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/tcx.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "console.h"
#include "pixel_ops.h"
#define MAXX 1024
Modified: trunk/src/host/qemu-neo1973/hw/tsc210x.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/tsc210x.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/tsc210x.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -19,7 +19,11 @@
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "hw.h"
+#include "audio/audio.h"
+#include "qemu-timer.h"
+#include "console.h"
+#include "omap.h"
#define TSC_DATA_REGISTERS_PAGE 0x0
#define TSC_CONTROL_REGISTERS_PAGE 0x1
@@ -279,10 +283,30 @@
qemu_irq_raise(s->codec.tx_start);
}
-static void tsc2102_audio_set_format(struct tsc210x_state_s *s)
+static void tsc2102_audio_rate_update(struct tsc210x_state_s *s)
{
+ const struct tsc210x_rate_info_s *rate;
+
+ s->codec.tx_rate = 0;
+ s->codec.rx_rate = 0;
+ if (s->dac_power & (1 << 15)) /* PWDNC */
+ return;
+
+ for (rate = tsc2102_rates; rate->rate; rate ++)
+ if (rate->dsor == (s->audio_ctrl1 & 0x3f) && /* DACFS */
+ rate->fsref == ((s->audio_ctrl3 >> 13) & 1))/* REFFS */
+ break;
+ if (!rate->rate) {
+ printf("%s: unknown sampling rate configured\n", __FUNCTION__);
+ return;
+ }
+
+ s->codec.tx_rate = rate->rate;
+}
+
+static void tsc2102_audio_output_update(struct tsc210x_state_s *s)
+{
int enable;
- const struct tsc210x_rate_info_s *rate;
audsettings_t fmt;
if (s->dac_voice[0]) {
@@ -292,32 +316,26 @@
AUD_close_out(&s->card, s->dac_voice[0]);
s->dac_voice[0] = 0;
}
+ s->codec.cts = 0;
enable =
(~s->dac_power & (1 << 15)) && /* PWDNC */
(~s->dac_power & (1 << 10)); /* DAPWDN */
- if (!enable)
+ if (!enable || !s->codec.tx_rate)
return;
- for (rate = tsc2102_rates; rate->rate; rate ++)
- if (rate->dsor == (s->audio_ctrl1 & 0x3f) && /* DACFS */
- rate->fsref == ((s->audio_ctrl3 >> 13) & 1))/* REFFS */
- break;
- if (!rate->rate) {
- printf("%s: unknown sampling rate configured\n", __FUNCTION__);
- return;
- }
-
/* Force our own sampling rate even in slave DAC mode */
fmt.endianness = 0;
fmt.nchannels = 2;
- fmt.freq = rate->rate;
+ fmt.freq = s->codec.tx_rate;
fmt.fmt = AUD_FMT_S16;
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
"tsc2102.sink", s, (void *) tsc210x_audio_out_cb, &fmt);
- if (s->dac_voice[0])
+ if (s->dac_voice[0]) {
+ s->codec.cts = 1;
AUD_set_active_out(s->dac_voice[0], 1);
+ }
}
static uint16_t tsc2102_data_register_read(struct tsc210x_state_s *s, int reg)
@@ -583,8 +601,9 @@
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 1\n");
#endif
+ tsc2102_audio_rate_update(s);
if (s->audio)
- tsc2102_audio_set_format(s);
+ tsc2102_audio_output_update(s);
return;
case 0x01:
@@ -627,8 +646,9 @@
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Power\n");
#endif
+ tsc2102_audio_rate_update(s);
if (s->audio)
- tsc2102_audio_set_format(s);
+ tsc2102_audio_output_update(s);
return;
case 0x06: /* Audio Control 3 */
@@ -640,7 +660,7 @@
"wrong value written into Audio 3\n");
#endif
if (s->audio)
- tsc2102_audio_set_format(s);
+ tsc2102_audio_output_update(s);
return;
case 0x07: /* LCH_BASS_BOOST_N0 */
Modified: trunk/src/host/qemu-neo1973/hw/unin_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/unin_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/unin_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "ppc_mac.h"
+#include "pci.h"
+
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
Modified: trunk/src/host/qemu-neo1973/hw/usb-bt.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-bt.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-bt.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -19,8 +19,11 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "usb.h"
+#include "bt.h"
+
struct USBBtState {
int altsetting;
USBDevice dev;
Modified: trunk/src/host/qemu-neo1973/hw/usb-hid.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-hid.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-hid.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "usb.h"
/* HID interface requests */
#define GET_REPORT 0xa101
Modified: trunk/src/host/qemu-neo1973/hw/usb-hub.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-hub.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-hub.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "usb.h"
//#define DEBUG
Modified: trunk/src/host/qemu-neo1973/hw/usb-msd.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-msd.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-msd.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,10 @@
* This code is licenced under the LGPL.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "usb.h"
+#include "block.h"
+#include "scsi-disk.h"
//#define DEBUG_MSD
Modified: trunk/src/host/qemu-neo1973/hw/usb-net.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-net.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-net.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -22,7 +22,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+
+#include "qemu-common.h"
+#include "usb.h"
+#include "net.h"
#include "../audio/sys-queue.h"
typedef uint32_t __le32;
Modified: trunk/src/host/qemu-neo1973/hw/usb-ohci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-ohci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-ohci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -27,7 +27,11 @@
* o BIOS work to boot from USB storage
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "usb.h"
+#include "pci.h"
+#include "pxa.h"
//#define DEBUG_OHCI
/* Dump packet contents. */
Modified: trunk/src/host/qemu-neo1973/hw/usb-uhci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-uhci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-uhci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "usb.h"
+#include "pci.h"
+#include "qemu-timer.h"
//#define DEBUG
//#define DEBUG_PACKET
Modified: trunk/src/host/qemu-neo1973/hw/usb-wacom.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb-wacom.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb-wacom.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -25,7 +25,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "usb.h"
/* Interface requests */
#define WACOM_GET_REPORT 0x2101
Modified: trunk/src/host/qemu-neo1973/hw/usb.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "usb.h"
void usb_attach(USBPort *port, USBDevice *dev)
{
Modified: trunk/src/host/qemu-neo1973/hw/usb.h
===================================================================
--- trunk/src/host/qemu-neo1973/hw/usb.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/usb.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -203,15 +203,6 @@
/* usb hub */
USBDevice *usb_hub_init(int nb_ports);
-/* usb-uhci.c */
-void usb_uhci_piix3_init(PCIBus *bus, int devfn);
-void usb_uhci_piix4_init(PCIBus *bus, int devfn);
-
-/* usb-ohci.c */
-void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
-void usb_ohci_init_memio(target_phys_addr_t base, int num_ports, int devfn,
- qemu_irq irq);
-
/* usb-linux.c */
USBDevice *usb_host_device_open(const char *devname);
void usb_host_info(void);
@@ -232,7 +223,19 @@
USBDevice *usb_net_init(NICInfo *nd);
/* usb-bt.c */
+struct bt_piconet_s;
USBDevice *usb_bt_init(struct bt_piconet_s *net);
/* usb-wacom.c */
USBDevice *usb_wacom_init(void);
+
+/* usb ports of the VM */
+
+#define USB_INDEX_HOST -1
+void qemu_register_usb_port(USBPort *port, void *opaque, int index,
+ usb_attachfn attach);
+void qemu_register_usb_gadget(USBDevice *device);
+
+#define VM_USB_HUB_SIZE 8
+
+int usb_device_attach(USBDevice *dev);
Modified: trunk/src/host/qemu-neo1973/hw/versatile_pci.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/versatile_pci.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/versatile_pci.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This code is licenced under the LGPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
+#include "primecell.h"
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
{
Modified: trunk/src/host/qemu-neo1973/hw/versatilepb.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/versatilepb.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/versatilepb.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,8 +7,14 @@
* This code is licenced under the GPL.
*/
-#include "vl.h"
-#include "arm_pic.h"
+#include "hw.h"
+#include "arm-misc.h"
+#include "primecell.h"
+#include "devices.h"
+#include "net.h"
+#include "sysemu.h"
+#include "pci.h"
+#include "boards.h"
/* Primary interrupt controller. */
@@ -153,7 +159,6 @@
static void versatile_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
- const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
int board_id)
@@ -270,24 +275,24 @@
initrd_filename, board_id, 0x0);
}
-static void vpb_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+static void vpb_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- versatile_init(ram_size, vga_ram_size, boot_device,
- ds, fd_filename, snapshot,
+ versatile_init(ram_size, vga_ram_size,
+ boot_device, ds,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x183);
}
-static void vab_init(int ram_size, int vga_ram_size, const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
+static void vab_init(int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- versatile_init(ram_size, vga_ram_size, boot_device,
- ds, fd_filename, snapshot,
+ versatile_init(ram_size, vga_ram_size,
+ boot_device, ds,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x25e);
}
Modified: trunk/src/host/qemu-neo1973/hw/vga.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/vga.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/vga.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "pc.h"
+#include "pci.h"
#include "vga_int.h"
#include "pixel_ops.h"
Modified: trunk/src/host/qemu-neo1973/hw/vmmouse.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/vmmouse.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/vmmouse.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "ps2.h"
+#include "pc.h"
/* debug only vmmouse */
//#define DEBUG_VMMOUSE
Modified: trunk/src/host/qemu-neo1973/hw/vmport.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/vmport.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/vmport.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
-#include "cpu-all.h"
+#include "hw.h"
+#include "isa.h"
+#include "pc.h"
+#include "sysemu.h"
#define VMPORT_CMD_GETVERSION 0x0a
#define VMPORT_CMD_GETRAMSIZE 0x14
Modified: trunk/src/host/qemu-neo1973/hw/vmware_vga.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/vmware_vga.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/vmware_vga.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "console.h"
+#include "pci.h"
#define VERBOSE
#define EMBED_STDVGA
Modified: trunk/src/host/qemu-neo1973/hw/wm8750.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/wm8750.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/wm8750.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This file is licensed under GNU GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "audio/audio.h"
#define IN_PORT_N 3
#define OUT_PORT_N 3
@@ -122,7 +124,7 @@
{ 192, 88200, 128, 88200 }, /* SR: 11111 */
};
-void wm8750_set_format(struct wm8750_s *s)
+static void wm8750_set_format(struct wm8750_s *s)
{
int i;
audsettings_t in_fmt;
@@ -192,7 +194,7 @@
AUD_set_active_out(*s->out[0], 1);
}
-void inline wm8750_mask_update(struct wm8750_s *s)
+static void inline wm8750_mask_update(struct wm8750_s *s)
{
#define R_ONLY 0x0000ffff
#define L_ONLY 0xffff0000
@@ -594,7 +596,7 @@
return &s->i2c;
}
-void wm8750_fini(i2c_slave *i2c)
+static void wm8750_fini(i2c_slave *i2c)
{
struct wm8750_s *s = (struct wm8750_s *) i2c;
wm8750_reset(&s->i2c);
Modified: trunk/src/host/qemu-neo1973/hw/wm8753.c
===================================================================
--- trunk/src/host/qemu-neo1973/hw/wm8753.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/hw/wm8753.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -7,7 +7,9 @@
* This file is licensed under GNU GPL v2.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "audio/audio.h"
#define IN_PORT_N 3
#define OUT_PORT_N 3
Modified: trunk/src/host/qemu-neo1973/i386-dis.c
===================================================================
--- trunk/src/host/qemu-neo1973/i386-dis.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/i386-dis.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1838,30 +1838,7 @@
static char separator_char;
static char scale_char;
-/* Here for backwards compatibility. When gdb stops using
- print_insn_i386_att and print_insn_i386_intel these functions can
- disappear, and print_insn_i386 be merged into print_insn. */
int
-print_insn_i386_att (pc, info)
- bfd_vma pc;
- disassemble_info *info;
-{
- intel_syntax = 0;
-
- return print_insn (pc, info);
-}
-
-int
-print_insn_i386_intel (pc, info)
- bfd_vma pc;
- disassemble_info *info;
-{
- intel_syntax = 1;
-
- return print_insn (pc, info);
-}
-
-int
print_insn_i386 (pc, info)
bfd_vma pc;
disassemble_info *info;
Modified: trunk/src/host/qemu-neo1973/linux-user/elfload.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/elfload.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/elfload.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -179,8 +179,9 @@
regs->ARM_cpsr |= CPSR_T;
regs->ARM_pc = infop->entry & 0xfffffffe;
regs->ARM_sp = infop->start_stack;
- regs->ARM_r2 = tgetl(stack + 8); /* envp */
- regs->ARM_r1 = tgetl(stack + 4); /* envp */
+ /* FIXME - what to for failure of get_user()? */
+ get_user_ual(regs->ARM_r2, stack + 8); /* envp */
+ get_user_ual(regs->ARM_r1, stack + 4); /* envp */
/* XXX: it seems that r0 is zeroed after ! */
regs->ARM_r0 = 0;
/* For uClinux PIC binaries. */
@@ -341,7 +342,8 @@
* but this is what the ABI wants and is needed to allow
* execution of PPC BSD programs.
*/
- _regs->gpr[3] = tgetl(pos);
+ /* FIXME - what to for failure of get_user()? */
+ get_user_ual(_regs->gpr[3], pos);
pos += sizeof(abi_ulong);
_regs->gpr[4] = pos;
for (tmp = 1; tmp != 0; pos += sizeof(abi_ulong))
@@ -733,7 +735,8 @@
if (nbyte) {
nbyte = qemu_host_page_size - nbyte;
do {
- tput8(elf_bss, 0);
+ /* FIXME - what to do if put_user() fails? */
+ put_user_u8(0, elf_bss);
elf_bss++;
} while (--nbyte);
}
@@ -782,17 +785,11 @@
/* This is correct because Linux defines
* elf_addr_t as Elf32_Off / Elf64_Off
*/
-#if ELF_CLASS == ELFCLASS32
-#define NEW_AUX_ENT(id, val) do { \
- sp -= n; tput32(sp, val); \
- sp -= n; tput32(sp, id); \
+#define NEW_AUX_ENT(id, val) do { \
+ sp -= n; put_user_ual(val, sp); \
+ sp -= n; put_user_ual(id, sp); \
} while(0)
-#else
-#define NEW_AUX_ENT(id, val) do { \
- sp -= n; tput64(sp, val); \
- sp -= n; tput64(sp, id); \
- } while(0)
-#endif
+
NEW_AUX_ENT (AT_NULL, 0);
/* There must be exactly DLINFO_ITEMS entries here. */
Modified: trunk/src/host/qemu-neo1973/linux-user/flatload.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/flatload.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/flatload.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -598,14 +598,16 @@
rp = datapos;
while (1) {
abi_ulong addr;
- addr = tgetl(rp);
+ if (get_user_ual(addr, rp))
+ return -EFAULT;
if (addr == -1)
break;
if (addr) {
addr = calc_reloc(addr, libinfo, id, 0);
if (addr == RELOC_FAILED)
return -ENOEXEC;
- tputl(rp, addr);
+ if (put_user_ual(addr, rp))
+ return -EFAULT;
}
rp += sizeof(abi_ulong);
}
@@ -629,14 +631,16 @@
/* Get the address of the pointer to be
relocated (of course, the address has to be
relocated first). */
- relval = tgetl(reloc + i * sizeof (abi_ulong));
+ if (get_user_ual(relval, reloc + i * sizeof(abi_ulong)))
+ return -EFAULT;
addr = flat_get_relocate_addr(relval);
rp = calc_reloc(addr, libinfo, id, 1);
if (rp == RELOC_FAILED)
return -ENOEXEC;
/* Get the pointer's value. */
- addr = tgetl(rp);
+ if (get_user_ual(addr, rp))
+ return -EFAULT;
if (addr != 0) {
/*
* Do the relocation. PIC relocs in the data section are
@@ -652,13 +656,15 @@
return -ENOEXEC;
/* Write back the relocated pointer. */
- tputl(rp, addr);
+ if (put_user_ual(addr, rp))
+ return -EFAULT;
}
}
} else {
for (i = 0; i < relocs; i++) {
abi_ulong relval;
- relval = tgetl(reloc + i * sizeof (abi_ulong));
+ if (get_user_ual(relval, reloc + i * sizeof(abi_ulong)))
+ return -EFAULT;
old_reloc(&libinfo[0], relval);
}
}
@@ -744,9 +750,12 @@
p = libinfo[i].start_data;
for (j=0; j<MAX_SHARED_LIBS; j++) {
p -= 4;
- tput32(p, libinfo[j].loaded
- ? libinfo[j].start_data
- : UNLOADED_LIB);
+ /* FIXME - handle put_user() failures */
+ if (put_user_ual(libinfo[j].loaded
+ ? libinfo[j].start_data
+ : UNLOADED_LIB,
+ p))
+ return -EFAULT;
}
}
}
@@ -779,7 +788,9 @@
for (i = MAX_SHARED_LIBS-1; i>0; i--) {
if (libinfo[i].loaded) {
/* Push previos first to call address */
- --sp; put_user(start_addr, sp);
+ --sp;
+ if (put_user_ual(start_addr, sp))
+ return -EFAULT;
start_addr = libinfo[i].entry;
}
}
Modified: trunk/src/host/qemu-neo1973/linux-user/i386/syscall.h
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/i386/syscall.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/i386/syscall.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -25,6 +25,7 @@
#define TARGET_LDT_ENTRIES 8192
#define TARGET_LDT_ENTRY_SIZE 8
+#define TARGET_GDT_ENTRIES 9
#define TARGET_GDT_ENTRY_TLS_ENTRIES 3
#define TARGET_GDT_ENTRY_TLS_MIN 6
#define TARGET_GDT_ENTRY_TLS_MAX (TARGET_GDT_ENTRY_TLS_MIN + TARGET_GDT_ENTRY_TLS_ENTRIES - 1)
Modified: trunk/src/host/qemu-neo1973/linux-user/linuxload.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/linuxload.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/linuxload.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -124,21 +124,32 @@
sp -= (argc + 1) * n;
argv = sp;
if (push_ptr) {
- sp -= n; tputl(sp, envp);
- sp -= n; tputl(sp, argv);
+ /* FIXME - handle put_user() failures */
+ sp -= n;
+ put_user_ual(envp, sp);
+ sp -= n;
+ put_user_ual(argv, sp);
}
- sp -= n; tputl(sp, argc);
+ sp -= n;
+ /* FIXME - handle put_user() failures */
+ put_user_ual(argc, sp);
while (argc-- > 0) {
- tputl(argv, stringp); argv += n;
+ /* FIXME - handle put_user() failures */
+ put_user_ual(stringp, argv);
+ argv += n;
stringp += target_strlen(stringp) + 1;
}
- tputl(argv, 0);
+ /* FIXME - handle put_user() failures */
+ put_user_ual(0, argv);
while (envc-- > 0) {
- tputl(envp, stringp); envp += n;
+ /* FIXME - handle put_user() failures */
+ put_user_ual(stringp, envp);
+ envp += n;
stringp += target_strlen(stringp) + 1;
}
- tputl(envp, 0);
+ /* FIXME - handle put_user() failures */
+ put_user_ual(0, envp);
return sp;
}
Modified: trunk/src/host/qemu-neo1973/linux-user/main.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/main.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/main.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -147,26 +147,46 @@
p[1] = tswapl(e2);
}
+#if TARGET_X86_64
+uint64_t idt_table[512];
+
+static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
+ uint64_t addr, unsigned int sel)
+{
+ uint32_t *p, e1, e2;
+ e1 = (addr & 0xffff) | (sel << 16);
+ e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
+ p = ptr;
+ p[0] = tswap32(e1);
+ p[1] = tswap32(e2);
+ p[2] = tswap32(addr >> 32);
+ p[3] = 0;
+}
+/* only dpl matters as we do only user space emulation */
+static void set_idt(int n, unsigned int dpl)
+{
+ set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
+}
+#else
+uint64_t idt_table[256];
+
static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
- unsigned long addr, unsigned int sel)
+ uint32_t addr, unsigned int sel)
{
- unsigned int e1, e2;
- uint32_t *p;
+ uint32_t *p, e1, e2;
e1 = (addr & 0xffff) | (sel << 16);
e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
p = ptr;
- p[0] = tswapl(e1);
- p[1] = tswapl(e2);
+ p[0] = tswap32(e1);
+ p[1] = tswap32(e2);
}
-uint64_t gdt_table[6];
-uint64_t idt_table[256];
-
/* only dpl matters as we do only user space emulation */
static void set_idt(int n, unsigned int dpl)
{
set_gate(idt_table + n, 0, dpl, 0, 0);
}
+#endif
void cpu_loop(CPUX86State *env)
{
@@ -178,7 +198,7 @@
trapnr = cpu_x86_exec(env);
switch(trapnr) {
case 0x80:
- /* linux syscall */
+ /* linux syscall from int $0x80 */
env->regs[R_EAX] = do_syscall(env,
env->regs[R_EAX],
env->regs[R_EBX],
@@ -188,6 +208,20 @@
env->regs[R_EDI],
env->regs[R_EBP]);
break;
+#ifndef TARGET_ABI32
+ case EXCP_SYSCALL:
+ /* linux syscall from syscall intruction */
+ env->regs[R_EAX] = do_syscall(env,
+ env->regs[R_EAX],
+ env->regs[R_EDI],
+ env->regs[R_ESI],
+ env->regs[R_EDX],
+ env->regs[10],
+ env->regs[8],
+ env->regs[9]);
+ env->eip = env->exception_next_eip;
+ break;
+#endif
case EXCP0B_NOSEG:
case EXCP0C_STACK:
info.si_signo = SIGBUS;
@@ -197,6 +231,7 @@
queue_signal(info.si_signo, &info);
break;
case EXCP0D_GPF:
+ /* XXX: potential problem if ABI32 */
#ifndef TARGET_X86_64
if (env->eflags & VM_MASK) {
handle_vm86_fault(env);
@@ -345,7 +380,8 @@
/* we handle the FPU emulation here, as Linux */
/* we get the opcode */
- opcode = tget32(env->regs[15]);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_u32(opcode, env->regs[15]);
if (EmulateAll(opcode, &ts->fpa, env) == 0) {
info.si_signo = SIGILL;
@@ -366,20 +402,24 @@
/* system call */
if (trapnr == EXCP_BKPT) {
if (env->thumb) {
- insn = tget16(env->regs[15]);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_u16(insn, env->regs[15]);
n = insn & 0xff;
env->regs[15] += 2;
} else {
- insn = tget32(env->regs[15]);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_u32(insn, env->regs[15]);
n = (insn & 0xf) | ((insn >> 4) & 0xff0);
env->regs[15] += 4;
}
} else {
if (env->thumb) {
- insn = tget16(env->regs[15] - 2);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_u16(insn, env->regs[15] - 2);
n = insn & 0xff;
} else {
- insn = tget32(env->regs[15] - 4);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_u32(insn, env->regs[15] - 4);
n = insn & 0xffffff;
}
}
@@ -485,7 +525,8 @@
(int)sp_ptr, cwp1);
#endif
for(i = 0; i < 16; i++) {
- tputl(sp_ptr, env->regbase[get_reg_index(env, cwp1, 8 + i)]);
+ /* FIXME - what to do if put_user() fails? */
+ put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
sp_ptr += sizeof(abi_ulong);
}
}
@@ -521,7 +562,8 @@
(int)sp_ptr, cwp1);
#endif
for(i = 0; i < 16; i++) {
- env->regbase[get_reg_index(env, cwp1, 8 + i)] = tgetl(sp_ptr);
+ /* FIXME - what to do if get_user() fails? */
+ get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
sp_ptr += sizeof(abi_ulong);
}
env->wim = new_wim;
@@ -1005,7 +1047,6 @@
cpu_abort(env, "Reset interrupt while in user mode. "
"Aborting\n");
break;
-#if defined(TARGET_PPC64) && !defined(TARGET_ABI32) /* PowerPC 64 */
case POWERPC_EXCP_DSEG: /* Data segment exception */
cpu_abort(env, "Data segment exception while in user mode. "
"Aborting\n");
@@ -1014,20 +1055,16 @@
cpu_abort(env, "Instruction segment exception "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64) && !defined(TARGET_ABI32) */
-#if defined(TARGET_PPC64H) && !defined(TARGET_ABI32)
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
cpu_abort(env, "Hypervisor decrementer interrupt "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64H) && !defined(TARGET_ABI32) */
case POWERPC_EXCP_TRACE: /* Trace exception */
/* Nothing to do:
* we use this exception to emulate step-by-step execution mode.
*/
break;
-#if defined(TARGET_PPC64H) && !defined(TARGET_ABI32)
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
cpu_abort(env, "Hypervisor data storage exception "
@@ -1045,7 +1082,6 @@
cpu_abort(env, "Hypervisor instruction segment exception "
"while in user mode. Aborting\n");
break;
-#endif /* defined(TARGET_PPC64H) && !defined(TARGET_ABI32) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
EXCP_DUMP(env, "No Altivec instructions allowed\n");
info.si_signo = TARGET_SIGILL;
@@ -1498,10 +1534,11 @@
sp_reg = env->gpr[29][env->current_tc];
switch (nb_args) {
/* these arguments are taken from the stack */
- case 8: arg8 = tgetl(sp_reg + 28);
- case 7: arg7 = tgetl(sp_reg + 24);
- case 6: arg6 = tgetl(sp_reg + 20);
- case 5: arg5 = tgetl(sp_reg + 16);
+ /* FIXME - what to do if get_user() fails? */
+ case 8: get_user_ual(arg8, sp_reg + 28);
+ case 7: get_user_ual(arg7, sp_reg + 24);
+ case 6: get_user_ual(arg6, sp_reg + 20);
+ case 5: get_user_ual(arg5, sp_reg + 16);
default:
break;
}
@@ -1997,7 +2034,11 @@
cpu_model = "24Kf";
#endif
#elif defined(TARGET_PPC)
+#ifdef TARGET_PPC64
+ cpu_model = "970";
+#else
cpu_model = "750";
+#endif
#else
cpu_model = "any";
#endif
@@ -2076,12 +2117,22 @@
env->cr[4] |= CR4_OSFXSR_MASK;
env->hflags |= HF_OSFXSR_MASK;
}
+#ifndef TARGET_ABI32
+ /* enable 64 bit mode if possible */
+ if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
+ fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
+ exit(1);
+ }
+ env->cr[4] |= CR4_PAE_MASK;
+ env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
+ env->hflags |= HF_LMA_MASK;
+#endif
/* flags setup : we activate the IRQs by default as in user mode */
env->eflags |= IF_MASK;
/* linux register setup */
-#if defined(TARGET_X86_64)
+#ifndef TARGET_ABI32
env->regs[R_EAX] = regs->rax;
env->regs[R_EBX] = regs->rbx;
env->regs[R_ECX] = regs->rcx;
@@ -2129,23 +2180,41 @@
set_idt(0x80, 3);
/* linux segment setup */
- env->gdt.base = h2g(gdt_table);
- env->gdt.limit = sizeof(gdt_table) - 1;
- write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
- DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
- (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
- write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
- DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
- (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
+ {
+ uint64_t *gdt_table;
+ gdt_table = qemu_mallocz(sizeof(uint64_t) * TARGET_GDT_ENTRIES);
+ env->gdt.base = h2g((unsigned long)gdt_table);
+ env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
+#ifdef TARGET_ABI32
+ write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
+ (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
+#else
+ /* 64 bit code segment */
+ write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
+ DESC_L_MASK |
+ (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
+#endif
+ write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
+ (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
+ }
cpu_x86_load_seg(env, R_CS, __USER_CS);
+ cpu_x86_load_seg(env, R_SS, __USER_DS);
+#ifdef TARGET_ABI32
cpu_x86_load_seg(env, R_DS, __USER_DS);
cpu_x86_load_seg(env, R_ES, __USER_DS);
- cpu_x86_load_seg(env, R_SS, __USER_DS);
cpu_x86_load_seg(env, R_FS, __USER_DS);
cpu_x86_load_seg(env, R_GS, __USER_DS);
-
/* This hack makes Wine work... */
env->segs[R_FS].selector = 0;
+#else
+ cpu_x86_load_seg(env, R_DS, 0);
+ cpu_x86_load_seg(env, R_ES, 0);
+ cpu_x86_load_seg(env, R_FS, 0);
+ cpu_x86_load_seg(env, R_GS, 0);
+#endif
#elif defined(TARGET_ARM)
{
int i;
Modified: trunk/src/host/qemu-neo1973/linux-user/mmap.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/mmap.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/mmap.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -151,19 +151,53 @@
return 0;
}
+#if defined(__CYGWIN__)
+/* Cygwin doesn't have a whole lot of address space. */
+static abi_ulong mmap_next_start = 0x18000000;
+#else
+static abi_ulong mmap_next_start = 0x40000000;
+#endif
+
+/* find a free memory area of size 'size'. The search starts at
+ 'start'. If 'start' == 0, then a default start address is used.
+ Return -1 if error.
+*/
+/* XXX: should mark pages used by the host as reserved to be sure not
+ to use them. */
+static abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size)
+{
+ abi_ulong addr, addr1, addr_start;
+ int prot;
+
+ size = HOST_PAGE_ALIGN(size);
+ start = start & qemu_host_page_mask;
+ addr = start;
+ if (addr == 0)
+ addr = mmap_next_start;
+ addr_start = addr;
+ for(;;) {
+ prot = 0;
+ for(addr1 = addr; addr1 < (addr + size); addr1 += TARGET_PAGE_SIZE) {
+ prot |= page_get_flags(addr1);
+ }
+ if (prot == 0)
+ break;
+ addr += qemu_host_page_size;
+ /* we found nothing */
+ if (addr == addr_start)
+ return (abi_ulong)-1;
+ }
+ if (start == 0)
+ mmap_next_start = addr + size;
+ return addr;
+}
+
/* NOTE: all the constants are the HOST ones */
abi_long target_mmap(abi_ulong start, abi_ulong len, int prot,
int flags, int fd, abi_ulong offset)
{
abi_ulong ret, end, real_start, real_end, retaddr, host_offset, host_len;
unsigned long host_start;
-#if defined(__alpha__) || defined(__sparc__) || defined(__x86_64__) || \
- defined(__ia64) || defined(__mips__)
- static abi_ulong last_start = 0x40000000;
-#elif defined(__CYGWIN__)
- /* Cygwin doesn't have a whole lot of address space. */
- static abi_ulong last_start = 0x18000000;
-#endif
#ifdef DEBUG_MMAP
{
@@ -203,147 +237,101 @@
real_start = start & qemu_host_page_mask;
if (!(flags & MAP_FIXED)) {
-#if defined(__alpha__) || defined(__sparc__) || defined(__x86_64__) || \
- defined(__ia64) || defined(__mips__) || defined(__CYGWIN__)
- /* tell the kernel to search at the same place as i386 */
- if (real_start == 0) {
- real_start = last_start;
- last_start += HOST_PAGE_ALIGN(len);
+ abi_ulong mmap_start;
+ void *p;
+ host_offset = offset & qemu_host_page_mask;
+ host_len = len + offset - host_offset;
+ host_len = HOST_PAGE_ALIGN(host_len);
+ mmap_start = mmap_find_vma(real_start, host_len);
+ if (mmap_start == (abi_ulong)-1) {
+ errno = ENOMEM;
+ return -1;
}
-#endif
- host_offset = offset & qemu_host_page_mask;
- host_len = len + offset - host_offset;
-
- if (qemu_host_page_size > qemu_real_host_page_size) {
- /*
- * The guest expects to see mmapped areas aligned to it's pagesize.
- * If the host's real page size is smaller than the guest's, we need
- * to fixup the maps. It is done by allocating a larger area,
- * displacing the map (if needed) and finally chopping off the spare
- * room at the edges.
- */
-
- /*
- * We assume qemu_host_page_size is always the same as
- * TARGET_PAGE_SIZE, see exec.c. qemu_real_host_page_size is the
- * hosts real page size.
- */
- abi_ulong host_end;
- unsigned long host_aligned_start;
- void *p;
-
- host_len = HOST_PAGE_ALIGN(host_len + qemu_host_page_size
- - qemu_real_host_page_size);
- p = mmap(real_start ? g2h(real_start) : NULL,
- host_len, prot, flags, fd, host_offset);
- if (p == MAP_FAILED)
- return -1;
-
- host_start = (unsigned long)p;
- host_end = host_start + host_len;
-
- /* Find start and end, aligned to the targets pagesize with-in the
- large mmaped area. */
- host_aligned_start = TARGET_PAGE_ALIGN(host_start);
- if (!(flags & MAP_ANONYMOUS))
- host_aligned_start += offset - host_offset;
-
- start = h2g(host_aligned_start);
- end = start + TARGET_PAGE_ALIGN(len);
-
- /* Chop off the leftovers, if any. */
- if (host_aligned_start > host_start)
- munmap((void *)host_start, host_aligned_start - host_start);
- if (end < host_end)
- munmap((void *)g2h(end), host_end - end);
-
- goto the_end1;
- } else {
- /* if not fixed, no need to do anything */
- void *p = mmap(real_start ? g2h(real_start) : NULL,
- host_len, prot, flags, fd, host_offset);
- if (p == MAP_FAILED)
- return -1;
- /* update start so that it points to the file position at 'offset' */
- host_start = (unsigned long)p;
- if (!(flags & MAP_ANONYMOUS))
- host_start += offset - host_offset;
- start = h2g(host_start);
- goto the_end1;
- }
- }
-
- if (start & ~TARGET_PAGE_MASK) {
- errno = EINVAL;
- return -1;
- }
- end = start + len;
- real_end = HOST_PAGE_ALIGN(end);
-
- /* worst case: we cannot map the file because the offset is not
- aligned, so we read it */
- if (!(flags & MAP_ANONYMOUS) &&
- (offset & ~qemu_host_page_mask) != (start & ~qemu_host_page_mask)) {
- /* msync() won't work here, so we return an error if write is
- possible while it is a shared mapping */
- if ((flags & MAP_TYPE) == MAP_SHARED &&
- (prot & PROT_WRITE)) {
+ /* Note: we prefer to control the mapping address. It is
+ especially important if qemu_host_page_size >
+ qemu_real_host_page_size */
+ p = mmap(g2h(mmap_start),
+ host_len, prot, flags | MAP_FIXED, fd, host_offset);
+ if (p == MAP_FAILED)
+ return -1;
+ /* update start so that it points to the file position at 'offset' */
+ host_start = (unsigned long)p;
+ if (!(flags & MAP_ANONYMOUS))
+ host_start += offset - host_offset;
+ start = h2g(host_start);
+ } else {
+ if (start & ~TARGET_PAGE_MASK) {
errno = EINVAL;
return -1;
}
- retaddr = target_mmap(start, len, prot | PROT_WRITE,
- MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
- -1, 0);
- if (retaddr == -1)
- return -1;
- pread(fd, g2h(start), len, offset);
- if (!(prot & PROT_WRITE)) {
- ret = target_mprotect(start, len, prot);
- if (ret != 0)
- return ret;
+ end = start + len;
+ real_end = HOST_PAGE_ALIGN(end);
+
+ /* worst case: we cannot map the file because the offset is not
+ aligned, so we read it */
+ if (!(flags & MAP_ANONYMOUS) &&
+ (offset & ~qemu_host_page_mask) != (start & ~qemu_host_page_mask)) {
+ /* msync() won't work here, so we return an error if write is
+ possible while it is a shared mapping */
+ if ((flags & MAP_TYPE) == MAP_SHARED &&
+ (prot & PROT_WRITE)) {
+ errno = EINVAL;
+ return -1;
+ }
+ retaddr = target_mmap(start, len, prot | PROT_WRITE,
+ MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
+ -1, 0);
+ if (retaddr == -1)
+ return -1;
+ pread(fd, g2h(start), len, offset);
+ if (!(prot & PROT_WRITE)) {
+ ret = target_mprotect(start, len, prot);
+ if (ret != 0)
+ return ret;
+ }
+ goto the_end;
}
- goto the_end;
- }
-
- /* handle the start of the mapping */
- if (start > real_start) {
- if (real_end == real_start + qemu_host_page_size) {
- /* one single host page */
- ret = mmap_frag(real_start, start, end,
+
+ /* handle the start of the mapping */
+ if (start > real_start) {
+ if (real_end == real_start + qemu_host_page_size) {
+ /* one single host page */
+ ret = mmap_frag(real_start, start, end,
+ prot, flags, fd, offset);
+ if (ret == -1)
+ return ret;
+ goto the_end1;
+ }
+ ret = mmap_frag(real_start, start, real_start + qemu_host_page_size,
prot, flags, fd, offset);
if (ret == -1)
return ret;
- goto the_end1;
+ real_start += qemu_host_page_size;
}
- ret = mmap_frag(real_start, start, real_start + qemu_host_page_size,
- prot, flags, fd, offset);
- if (ret == -1)
- return ret;
- real_start += qemu_host_page_size;
- }
- /* handle the end of the mapping */
- if (end < real_end) {
- ret = mmap_frag(real_end - qemu_host_page_size,
- real_end - qemu_host_page_size, real_end,
- prot, flags, fd,
- offset + real_end - qemu_host_page_size - start);
- if (ret == -1)
- return -1;
- real_end -= qemu_host_page_size;
- }
+ /* handle the end of the mapping */
+ if (end < real_end) {
+ ret = mmap_frag(real_end - qemu_host_page_size,
+ real_end - qemu_host_page_size, real_end,
+ prot, flags, fd,
+ offset + real_end - qemu_host_page_size - start);
+ if (ret == -1)
+ return -1;
+ real_end -= qemu_host_page_size;
+ }
- /* map the middle (easier) */
- if (real_start < real_end) {
- void *p;
- unsigned long offset1;
- if (flags & MAP_ANONYMOUS)
- offset1 = 0;
- else
- offset1 = offset + real_start - start;
- p = mmap(g2h(real_start), real_end - real_start,
- prot, flags, fd, offset1);
- if (p == MAP_FAILED)
- return -1;
+ /* map the middle (easier) */
+ if (real_start < real_end) {
+ void *p;
+ unsigned long offset1;
+ if (flags & MAP_ANONYMOUS)
+ offset1 = 0;
+ else
+ offset1 = offset + real_start - start;
+ p = mmap(g2h(real_start), real_end - real_start,
+ prot, flags, fd, offset1);
+ if (p == MAP_FAILED)
+ return -1;
+ }
}
the_end1:
page_set_flags(start, start + len, prot | PAGE_VALID);
Modified: trunk/src/host/qemu-neo1973/linux-user/qemu.h
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/qemu.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/qemu.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -20,7 +20,11 @@
#define TARGET_ABI_FMT_ld TARGET_FMT_ld
#define TARGET_ABI_FMT_lu TARGET_FMT_lu
#define TARGET_ABI_BITS TARGET_LONG_BITS
+/* for consistency, define ABI32 too */
+#if TARGET_ABI_BITS == 32
+#define TARGET_ABI32 1
#endif
+#endif
#include "thunk.h"
#include "syscall_defs.h"
@@ -207,8 +211,11 @@
#define VERIFY_READ 0
#define VERIFY_WRITE 1 /* implies read access */
-#define access_ok(type,addr,size) \
- (page_check_range((target_ulong)addr,size,(type==VERIFY_READ)?PAGE_READ:PAGE_WRITE)==0)
+static inline int access_ok(int type, abi_ulong addr, abi_ulong size)
+{
+ return page_check_range((target_ulong)addr, size,
+ (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0;
+}
/* NOTE __get_user and __put_user use host pointers and don't check access. */
/* These are usually used to access struct data members once the
@@ -219,7 +226,7 @@
int size = sizeof(*hptr);\
switch(size) {\
case 1:\
- *(uint8_t *)(hptr) = (typeof(*hptr))(x);\
+ *(uint8_t *)(hptr) = (uint8_t)(typeof(*hptr))(x);\
break;\
case 2:\
*(uint16_t *)(hptr) = tswap16((typeof(*hptr))(x));\
@@ -253,6 +260,8 @@
x = (typeof(*hptr))tswap64(*(uint64_t *)(hptr));\
break;\
default:\
+ /* avoid warning */\
+ x = 0;\
abort();\
}\
0;\
@@ -284,11 +293,36 @@
if ((__hptr = lock_user(VERIFY_READ, __gaddr, sizeof(target_type), 1))) { \
__ret = __get_user((x), __hptr); \
unlock_user(__hptr, __gaddr, 0); \
- } else \
+ } else { \
+ /* avoid warning */ \
+ (x) = 0; \
__ret = -TARGET_EFAULT; \
+ } \
__ret; \
})
+#define put_user_ual(x, gaddr) put_user((x), (gaddr), abi_ulong)
+#define put_user_sal(x, gaddr) put_user((x), (gaddr), abi_long)
+#define put_user_u64(x, gaddr) put_user((x), (gaddr), uint64_t)
+#define put_user_s64(x, gaddr) put_user((x), (gaddr), int64_t)
+#define put_user_u32(x, gaddr) put_user((x), (gaddr), uint32_t)
+#define put_user_s32(x, gaddr) put_user((x), (gaddr), int32_t)
+#define put_user_u16(x, gaddr) put_user((x), (gaddr), uint16_t)
+#define put_user_s16(x, gaddr) put_user((x), (gaddr), int16_t)
+#define put_user_u8(x, gaddr) put_user((x), (gaddr), uint8_t)
+#define put_user_s8(x, gaddr) put_user((x), (gaddr), int8_t)
+
+#define get_user_ual(x, gaddr) get_user((x), (gaddr), abi_ulong)
+#define get_user_sal(x, gaddr) get_user((x), (gaddr), abi_long)
+#define get_user_u64(x, gaddr) get_user((x), (gaddr), uint64_t)
+#define get_user_s64(x, gaddr) get_user((x), (gaddr), int64_t)
+#define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t)
+#define get_user_s32(x, gaddr) get_user((x), (gaddr), int32_t)
+#define get_user_u16(x, gaddr) get_user((x), (gaddr), uint16_t)
+#define get_user_s16(x, gaddr) get_user((x), (gaddr), int16_t)
+#define get_user_u8(x, gaddr) get_user((x), (gaddr), uint8_t)
+#define get_user_s8(x, gaddr) get_user((x), (gaddr), int8_t)
+
/* copy_from_user() and copy_to_user() are usually used to copy data
* buffers between the target and host. These internally perform
* locking/unlocking of the memory.
@@ -361,20 +395,4 @@
#define unlock_user_struct(host_ptr, guest_addr, copy) \
unlock_user(host_ptr, guest_addr, (copy) ? sizeof(*host_ptr) : 0)
-#define tget8(addr) ldub(addr)
-#define tput8(addr, val) stb(addr, val)
-#define tget16(addr) lduw(addr)
-#define tput16(addr, val) stw(addr, val)
-#define tget32(addr) ldl(addr)
-#define tput32(addr, val) stl(addr, val)
-#define tget64(addr) ldq(addr)
-#define tput64(addr, val) stq(addr, val)
-#if TARGET_ABI_BITS == 64
-#define tgetl(addr) ldq(addr)
-#define tputl(addr, val) stq(addr, val)
-#else
-#define tgetl(addr) ldl(addr)
-#define tputl(addr, val) stl(addr, val)
-#endif
-
#endif /* QEMU_H */
Modified: trunk/src/host/qemu-neo1973/linux-user/strace.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/strace.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/strace.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -271,7 +271,7 @@
abi_long arg4, abi_long arg5, abi_long arg6)
{
int i;
- char *format="%s(%ld,%ld,%ld,%ld,%ld,%ld)";
+ char *format="%s(" TARGET_ABI_FMT_ld "," TARGET_ABI_FMT_ld "," TARGET_ABI_FMT_ld "," TARGET_ABI_FMT_ld "," TARGET_ABI_FMT_ld "," TARGET_ABI_FMT_ld ")";
gemu_log("%d ", getpid() );
@@ -280,6 +280,8 @@
if( scnames[i].call != NULL ) {
scnames[i].call(&scnames[i],arg1,arg2,arg3,arg4,arg5,arg6);
} else {
+ /* XXX: this format system is broken because it uses
+ host types and host pointers for strings */
if( scnames[i].format != NULL )
format = scnames[i].format;
gemu_log(format,scnames[i].name, arg1,arg2,arg3,arg4,arg5,arg6);
Modified: trunk/src/host/qemu-neo1973/linux-user/syscall.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/syscall.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/syscall.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -783,7 +783,7 @@
/* do_setsockopt() Must return target values and target errnos. */
static abi_long do_setsockopt(int sockfd, int level, int optname,
- abi_ulong optval, socklen_t optlen)
+ abi_ulong optval_addr, socklen_t optlen)
{
abi_long ret;
int val;
@@ -794,7 +794,8 @@
if (optlen < sizeof(uint32_t))
return -TARGET_EINVAL;
- val = tget32(optval);
+ if (get_user_u32(val, optval_addr))
+ return -TARGET_EFAULT;
ret = get_errno(setsockopt(sockfd, level, optname, &val, sizeof(val)));
break;
case SOL_IP:
@@ -816,9 +817,11 @@
case IP_MULTICAST_LOOP:
val = 0;
if (optlen >= sizeof(uint32_t)) {
- val = tget32(optval);
+ if (get_user_u32(val, optval_addr))
+ return -TARGET_EFAULT;
} else if (optlen >= 1) {
- val = tget8(optval);
+ if (get_user_u8(val, optval_addr))
+ return -TARGET_EFAULT;
}
ret = get_errno(setsockopt(sockfd, level, optname, &val, sizeof(val)));
break;
@@ -890,9 +893,10 @@
goto unimplemented;
}
if (optlen < sizeof(uint32_t))
- return -TARGET_EINVAL;
+ return -TARGET_EINVAL;
- val = tget32(optval);
+ if (get_user_u32(val, optval_addr))
+ return -TARGET_EFAULT;
ret = get_errno(setsockopt(sockfd, SOL_SOCKET, optname, &val, sizeof(val)));
break;
default:
@@ -905,7 +909,7 @@
/* do_getsockopt() Must return target values and target errnos. */
static abi_long do_getsockopt(int sockfd, int level, int optname,
- abi_ulong optval, abi_ulong optlen)
+ abi_ulong optval_addr, abi_ulong optlen)
{
abi_long ret;
int len, lv, val;
@@ -928,7 +932,8 @@
case SOL_TCP:
/* TCP options all take an 'int' value. */
int_case:
- len = tget32(optlen);
+ if (get_user_u32(len, optlen))
+ return -TARGET_EFAULT;
if (len < 0)
return -TARGET_EINVAL;
lv = sizeof(int);
@@ -938,11 +943,15 @@
val = tswap32(val);
if (len > lv)
len = lv;
- if (len == 4)
- tput32(optval, val);
- else
- tput8(optval, val);
- tput32(optlen, len);
+ if (len == 4) {
+ if (put_user_u32(val, optval_addr))
+ return -TARGET_EFAULT;
+ } else {
+ if (put_user_u8(val, optval_addr))
+ return -TARGET_EFAULT;
+ }
+ if (put_user_u32(len, optlen))
+ return -TARGET_EFAULT;
break;
case SOL_IP:
switch(optname) {
@@ -961,7 +970,8 @@
#endif
case IP_MULTICAST_TTL:
case IP_MULTICAST_LOOP:
- len = tget32(optlen);
+ if (get_user_u32(len, optlen))
+ return -TARGET_EFAULT;
if (len < 0)
return -TARGET_EINVAL;
lv = sizeof(int);
@@ -970,13 +980,15 @@
return ret;
if (len < sizeof(int) && len > 0 && val >= 0 && val < 255) {
len = 1;
- tput32(optlen, len);
- tput8(optval, val);
+ if (put_user_u32(len, optlen)
+ || put_user_u8(val, optval_addr))
+ return -TARGET_EFAULT;
} else {
if (len > sizeof(int))
len = sizeof(int);
- tput32(optlen, len);
- tput32(optval, val);
+ if (put_user_u32(len, optlen)
+ || put_user_u32(val, optval_addr))
+ return -TARGET_EFAULT;
}
break;
default:
@@ -1148,63 +1160,82 @@
/* do_accept() Must return target values and target errnos. */
static abi_long do_accept(int fd, abi_ulong target_addr,
- abi_ulong target_addrlen)
+ abi_ulong target_addrlen_addr)
{
- socklen_t addrlen = tget32(target_addrlen);
- void *addr = alloca(addrlen);
+ socklen_t addrlen;
+ void *addr;
abi_long ret;
+ if (get_user_u32(addrlen, target_addrlen_addr))
+ return -TARGET_EFAULT;
+
+ addr = alloca(addrlen);
+
ret = get_errno(accept(fd, addr, &addrlen));
if (!is_error(ret)) {
host_to_target_sockaddr(target_addr, addr, addrlen);
- tput32(target_addrlen, addrlen);
+ if (put_user_u32(addrlen, target_addrlen_addr))
+ ret = -TARGET_EFAULT;
}
return ret;
}
/* do_getpeername() Must return target values and target errnos. */
static abi_long do_getpeername(int fd, abi_ulong target_addr,
- abi_ulong target_addrlen)
+ abi_ulong target_addrlen_addr)
{
- socklen_t addrlen = tget32(target_addrlen);
- void *addr = alloca(addrlen);
+ socklen_t addrlen;
+ void *addr;
abi_long ret;
+ if (get_user_u32(addrlen, target_addrlen_addr))
+ return -TARGET_EFAULT;
+
+ addr = alloca(addrlen);
+
ret = get_errno(getpeername(fd, addr, &addrlen));
if (!is_error(ret)) {
host_to_target_sockaddr(target_addr, addr, addrlen);
- tput32(target_addrlen, addrlen);
+ if (put_user_u32(addrlen, target_addrlen_addr))
+ ret = -TARGET_EFAULT;
}
return ret;
}
/* do_getsockname() Must return target values and target errnos. */
static abi_long do_getsockname(int fd, abi_ulong target_addr,
- abi_ulong target_addrlen)
+ abi_ulong target_addrlen_addr)
{
- socklen_t addrlen = tget32(target_addrlen);
- void *addr = alloca(addrlen);
+ socklen_t addrlen;
+ void *addr;
abi_long ret;
+ if (get_user_u32(addrlen, target_addrlen_addr))
+ return -TARGET_EFAULT;
+
+ addr = alloca(addrlen);
+
ret = get_errno(getsockname(fd, addr, &addrlen));
if (!is_error(ret)) {
host_to_target_sockaddr(target_addr, addr, addrlen);
- tput32(target_addrlen, addrlen);
+ if (put_user_u32(addrlen, target_addrlen_addr))
+ ret = -TARGET_EFAULT;
}
return ret;
}
/* do_socketpair() Must return target values and target errnos. */
static abi_long do_socketpair(int domain, int type, int protocol,
- abi_ulong target_tab)
+ abi_ulong target_tab_addr)
{
int tab[2];
abi_long ret;
ret = get_errno(socketpair(domain, type, protocol, tab));
if (!is_error(ret)) {
- tput32(target_tab, tab[0]);
- tput32(target_tab + 4, tab[1]);
+ if (put_user_s32(tab[0], target_tab_addr)
+ || put_user_s32(tab[1], target_tab_addr + sizeof(tab[0])))
+ ret = -TARGET_EFAULT;
}
return ret;
}
@@ -1245,7 +1276,10 @@
if (!host_msg)
return -TARGET_EFAULT;
if (target_addr) {
- addrlen = tget32(target_addrlen);
+ if (get_user_u32(addrlen, target_addrlen)) {
+ ret = -TARGET_EFAULT;
+ goto fail;
+ }
addr = alloca(addrlen);
ret = get_errno(recvfrom(fd, host_msg, len, flags, addr, &addrlen));
} else {
@@ -1255,10 +1289,14 @@
if (!is_error(ret)) {
if (target_addr) {
host_to_target_sockaddr(target_addr, addr, addrlen);
- tput32(target_addrlen, addrlen);
+ if (put_user_u32(addrlen, target_addrlen)) {
+ ret = -TARGET_EFAULT;
+ goto fail;
+ }
}
unlock_user(host_msg, msg, len);
} else {
+fail:
unlock_user(host_msg, msg, 0);
}
return ret;
@@ -1274,113 +1312,188 @@
switch(num) {
case SOCKOP_socket:
{
- int domain = tgetl(vptr);
- int type = tgetl(vptr + n);
- int protocol = tgetl(vptr + 2 * n);
+ int domain, type, protocol;
+
+ if (get_user_s32(domain, vptr)
+ || get_user_s32(type, vptr + n)
+ || get_user_s32(protocol, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_socket(domain, type, protocol);
}
break;
case SOCKOP_bind:
{
- int sockfd = tgetl(vptr);
- abi_ulong target_addr = tgetl(vptr + n);
- socklen_t addrlen = tgetl(vptr + 2 * n);
+ int sockfd;
+ abi_ulong target_addr;
+ socklen_t addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(target_addr, vptr + n)
+ || get_user_u32(addrlen, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_bind(sockfd, target_addr, addrlen);
}
break;
case SOCKOP_connect:
{
- int sockfd = tgetl(vptr);
- abi_ulong target_addr = tgetl(vptr + n);
- socklen_t addrlen = tgetl(vptr + 2 * n);
+ int sockfd;
+ abi_ulong target_addr;
+ socklen_t addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(target_addr, vptr + n)
+ || get_user_u32(addrlen, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_connect(sockfd, target_addr, addrlen);
}
break;
case SOCKOP_listen:
{
- int sockfd = tgetl(vptr);
- int backlog = tgetl(vptr + n);
+ int sockfd, backlog;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_s32(backlog, vptr + n))
+ return -TARGET_EFAULT;
+
ret = get_errno(listen(sockfd, backlog));
}
break;
case SOCKOP_accept:
{
- int sockfd = tgetl(vptr);
- abi_ulong target_addr = tgetl(vptr + n);
- abi_ulong target_addrlen = tgetl(vptr + 2 * n);
+ int sockfd;
+ abi_ulong target_addr, target_addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(target_addr, vptr + n)
+ || get_user_u32(target_addrlen, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_accept(sockfd, target_addr, target_addrlen);
}
break;
case SOCKOP_getsockname:
{
- int sockfd = tgetl(vptr);
- abi_ulong target_addr = tgetl(vptr + n);
- abi_ulong target_addrlen = tgetl(vptr + 2 * n);
+ int sockfd;
+ abi_ulong target_addr, target_addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(target_addr, vptr + n)
+ || get_user_u32(target_addrlen, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_getsockname(sockfd, target_addr, target_addrlen);
}
break;
case SOCKOP_getpeername:
{
- int sockfd = tgetl(vptr);
- abi_ulong target_addr = tgetl(vptr + n);
- abi_ulong target_addrlen = tgetl(vptr + 2 * n);
+ int sockfd;
+ abi_ulong target_addr, target_addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(target_addr, vptr + n)
+ || get_user_u32(target_addrlen, vptr + 2 * n))
+ return -TARGET_EFAULT;
+
ret = do_getpeername(sockfd, target_addr, target_addrlen);
}
break;
case SOCKOP_socketpair:
{
- int domain = tgetl(vptr);
- int type = tgetl(vptr + n);
- int protocol = tgetl(vptr + 2 * n);
- abi_ulong tab = tgetl(vptr + 3 * n);
+ int domain, type, protocol;
+ abi_ulong tab;
+
+ if (get_user_s32(domain, vptr)
+ || get_user_s32(type, vptr + n)
+ || get_user_s32(protocol, vptr + 2 * n)
+ || get_user_ual(tab, vptr + 3 * n))
+ return -TARGET_EFAULT;
+
ret = do_socketpair(domain, type, protocol, tab);
}
break;
case SOCKOP_send:
{
- int sockfd = tgetl(vptr);
- abi_ulong msg = tgetl(vptr + n);
- size_t len = tgetl(vptr + 2 * n);
- int flags = tgetl(vptr + 3 * n);
+ int sockfd;
+ abi_ulong msg;
+ size_t len;
+ int flags;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(msg, vptr + n)
+ || get_user_ual(len, vptr + 2 * n)
+ || get_user_s32(flags, vptr + 3 * n))
+ return -TARGET_EFAULT;
+
ret = do_sendto(sockfd, msg, len, flags, 0, 0);
}
break;
case SOCKOP_recv:
{
- int sockfd = tgetl(vptr);
- abi_ulong msg = tgetl(vptr + n);
- size_t len = tgetl(vptr + 2 * n);
- int flags = tgetl(vptr + 3 * n);
+ int sockfd;
+ abi_ulong msg;
+ size_t len;
+ int flags;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(msg, vptr + n)
+ || get_user_ual(len, vptr + 2 * n)
+ || get_user_s32(flags, vptr + 3 * n))
+ return -TARGET_EFAULT;
+
ret = do_recvfrom(sockfd, msg, len, flags, 0, 0);
}
break;
case SOCKOP_sendto:
{
- int sockfd = tgetl(vptr);
- abi_ulong msg = tgetl(vptr + n);
- size_t len = tgetl(vptr + 2 * n);
- int flags = tgetl(vptr + 3 * n);
- abi_ulong addr = tgetl(vptr + 4 * n);
- socklen_t addrlen = tgetl(vptr + 5 * n);
+ int sockfd;
+ abi_ulong msg;
+ size_t len;
+ int flags;
+ abi_ulong addr;
+ socklen_t addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(msg, vptr + n)
+ || get_user_ual(len, vptr + 2 * n)
+ || get_user_s32(flags, vptr + 3 * n)
+ || get_user_ual(addr, vptr + 4 * n)
+ || get_user_u32(addrlen, vptr + 5 * n))
+ return -TARGET_EFAULT;
+
ret = do_sendto(sockfd, msg, len, flags, addr, addrlen);
}
break;
case SOCKOP_recvfrom:
{
- int sockfd = tgetl(vptr);
- abi_ulong msg = tgetl(vptr + n);
- size_t len = tgetl(vptr + 2 * n);
- int flags = tgetl(vptr + 3 * n);
- abi_ulong addr = tgetl(vptr + 4 * n);
- abi_ulong addrlen = tgetl(vptr + 5 * n);
+ int sockfd;
+ abi_ulong msg;
+ size_t len;
+ int flags;
+ abi_ulong addr;
+ socklen_t addrlen;
+
+ if (get_user_s32(sockfd, vptr)
+ || get_user_ual(msg, vptr + n)
+ || get_user_ual(len, vptr + 2 * n)
+ || get_user_s32(flags, vptr + 3 * n)
+ || get_user_ual(addr, vptr + 4 * n)
+ || get_user_u32(addrlen, vptr + 5 * n))
+ return -TARGET_EFAULT;
+
ret = do_recvfrom(sockfd, msg, len, flags, addr, addrlen);
}
break;
case SOCKOP_shutdown:
{
- int sockfd = tgetl(vptr);
- int how = tgetl(vptr + n);
+ int sockfd, how;
+ if (get_user_s32(sockfd, vptr)
+ || get_user_s32(how, vptr + n))
+ return -TARGET_EFAULT;
+
ret = get_errno(shutdown(sockfd, how));
}
break;
@@ -1391,9 +1504,10 @@
abi_ulong target_msg;
int flags;
- fd = tgetl(vptr);
- target_msg = tgetl(vptr + n);
- flags = tgetl(vptr + 2 * n);
+ if (get_user_s32(fd, vptr)
+ || get_user_ual(target_msg, vptr + n)
+ || get_user_s32(flags, vptr + 2 * n))
+ return -TARGET_EFAULT;
ret = do_sendrecvmsg(fd, target_msg, flags,
(num == SOCKOP_sendmsg));
@@ -1401,24 +1515,38 @@
break;
case SOCKOP_setsockopt:
{
- int sockfd = tgetl(vptr);
- int level = tgetl(vptr + n);
- int optname = tgetl(vptr + 2 * n);
- abi_ulong optval = tgetl(vptr + 3 * n);
- socklen_t optlen = tgetl(vptr + 4 * n);
+ int sockfd;
+ int level;
+ int optname;
+ abi_ulong optval;
+ socklen_t optlen;
+ if (get_user_s32(sockfd, vptr)
+ || get_user_s32(level, vptr + n)
+ || get_user_s32(optname, vptr + 2 * n)
+ || get_user_ual(optval, vptr + 3 * n)
+ || get_user_u32(optlen, vptr + 4 * n))
+ return -TARGET_EFAULT;
+
ret = do_setsockopt(sockfd, level, optname, optval, optlen);
}
break;
case SOCKOP_getsockopt:
{
- int sockfd = tgetl(vptr);
- int level = tgetl(vptr + n);
- int optname = tgetl(vptr + 2 * n);
- abi_ulong optval = tgetl(vptr + 3 * n);
- abi_ulong poptlen = tgetl(vptr + 4 * n);
+ int sockfd;
+ int level;
+ int optname;
+ abi_ulong optval;
+ socklen_t optlen;
- ret = do_getsockopt(sockfd, level, optname, optval, poptlen);
+ if (get_user_s32(sockfd, vptr)
+ || get_user_s32(level, vptr + n)
+ || get_user_s32(optname, vptr + 2 * n)
+ || get_user_ual(optval, vptr + 3 * n)
+ || get_user_u32(optlen, vptr + 4 * n))
+ return -TARGET_EFAULT;
+
+ ret = do_getsockopt(sockfd, level, optname, optval, optlen);
}
break;
default:
@@ -1883,7 +2011,7 @@
break;
}
}
- if (put_user(raddr, third, abi_ulong))
+ if (put_user_ual(raddr, third))
return -TARGET_EFAULT;
ret = 0;
}
@@ -2285,7 +2413,7 @@
struct target_modify_ldt_ldt_s ldt_info;
struct target_modify_ldt_ldt_s *target_ldt_info;
int seg_32bit, contents, read_exec_only, limit_in_pages;
- int seg_not_present, useable;
+ int seg_not_present, useable, lm;
uint32_t *lp, entry_1, entry_2;
if (bytecount != sizeof(ldt_info))
@@ -2306,7 +2434,11 @@
limit_in_pages = (ldt_info.flags >> 4) & 1;
seg_not_present = (ldt_info.flags >> 5) & 1;
useable = (ldt_info.flags >> 6) & 1;
-
+#ifdef TARGET_ABI32
+ lm = 0;
+#else
+ lm = (ldt_info.flags >> 7) & 1;
+#endif
if (contents == 3) {
if (oldmode)
return -TARGET_EINVAL;
@@ -2349,6 +2481,7 @@
((seg_not_present ^ 1) << 15) |
(seg_32bit << 22) |
(limit_in_pages << 23) |
+ (lm << 21) |
0x7000;
if (!oldmode)
entry_2 |= (useable << 20);
@@ -2384,6 +2517,173 @@
return ret;
}
+abi_long do_set_thread_area(CPUX86State *env, abi_ulong ptr)
+{
+ uint64_t *gdt_table = g2h(env->gdt.base);
+ struct target_modify_ldt_ldt_s ldt_info;
+ struct target_modify_ldt_ldt_s *target_ldt_info;
+ int seg_32bit, contents, read_exec_only, limit_in_pages;
+ int seg_not_present, useable, lm;
+ uint32_t *lp, entry_1, entry_2;
+ int i;
+
+ lock_user_struct(VERIFY_WRITE, target_ldt_info, ptr, 1);
+ if (!target_ldt_info)
+ return -TARGET_EFAULT;
+ ldt_info.entry_number = tswap32(target_ldt_info->entry_number);
+ ldt_info.base_addr = tswapl(target_ldt_info->base_addr);
+ ldt_info.limit = tswap32(target_ldt_info->limit);
+ ldt_info.flags = tswap32(target_ldt_info->flags);
+ if (ldt_info.entry_number == -1) {
+ for (i=TARGET_GDT_ENTRY_TLS_MIN; i<=TARGET_GDT_ENTRY_TLS_MAX; i++) {
+ if (gdt_table[i] == 0) {
+ ldt_info.entry_number = i;
+ target_ldt_info->entry_number = tswap32(i);
+ break;
+ }
+ }
+ }
+ unlock_user_struct(target_ldt_info, ptr, 1);
+
+ if (ldt_info.entry_number < TARGET_GDT_ENTRY_TLS_MIN ||
+ ldt_info.entry_number > TARGET_GDT_ENTRY_TLS_MAX)
+ return -TARGET_EINVAL;
+ seg_32bit = ldt_info.flags & 1;
+ contents = (ldt_info.flags >> 1) & 3;
+ read_exec_only = (ldt_info.flags >> 3) & 1;
+ limit_in_pages = (ldt_info.flags >> 4) & 1;
+ seg_not_present = (ldt_info.flags >> 5) & 1;
+ useable = (ldt_info.flags >> 6) & 1;
+#ifdef TARGET_ABI32
+ lm = 0;
+#else
+ lm = (ldt_info.flags >> 7) & 1;
+#endif
+
+ if (contents == 3) {
+ if (seg_not_present == 0)
+ return -TARGET_EINVAL;
+ }
+
+ /* NOTE: same code as Linux kernel */
+ /* Allow LDTs to be cleared by the user. */
+ if (ldt_info.base_addr == 0 && ldt_info.limit == 0) {
+ if ((contents == 0 &&
+ read_exec_only == 1 &&
+ seg_32bit == 0 &&
+ limit_in_pages == 0 &&
+ seg_not_present == 1 &&
+ useable == 0 )) {
+ entry_1 = 0;
+ entry_2 = 0;
+ goto install;
+ }
+ }
+
+ entry_1 = ((ldt_info.base_addr & 0x0000ffff) << 16) |
+ (ldt_info.limit & 0x0ffff);
+ entry_2 = (ldt_info.base_addr & 0xff000000) |
+ ((ldt_info.base_addr & 0x00ff0000) >> 16) |
+ (ldt_info.limit & 0xf0000) |
+ ((read_exec_only ^ 1) << 9) |
+ (contents << 10) |
+ ((seg_not_present ^ 1) << 15) |
+ (seg_32bit << 22) |
+ (limit_in_pages << 23) |
+ (useable << 20) |
+ (lm << 21) |
+ 0x7000;
+
+ /* Install the new entry ... */
+install:
+ lp = (uint32_t *)(gdt_table + ldt_info.entry_number);
+ lp[0] = tswap32(entry_1);
+ lp[1] = tswap32(entry_2);
+ return 0;
+}
+
+abi_long do_get_thread_area(CPUX86State *env, abi_ulong ptr)
+{
+ struct target_modify_ldt_ldt_s *target_ldt_info;
+ uint64_t *gdt_table = g2h(env->gdt.base);
+ uint32_t base_addr, limit, flags;
+ int seg_32bit, contents, read_exec_only, limit_in_pages, idx;
+ int seg_not_present, useable, lm;
+ uint32_t *lp, entry_1, entry_2;
+
+ lock_user_struct(VERIFY_WRITE, target_ldt_info, ptr, 1);
+ if (!target_ldt_info)
+ return -TARGET_EFAULT;
+ idx = tswap32(target_ldt_info->entry_number);
+ if (idx < TARGET_GDT_ENTRY_TLS_MIN ||
+ idx > TARGET_GDT_ENTRY_TLS_MAX) {
+ unlock_user_struct(target_ldt_info, ptr, 1);
+ return -TARGET_EINVAL;
+ }
+ lp = (uint32_t *)(gdt_table + idx);
+ entry_1 = tswap32(lp[0]);
+ entry_2 = tswap32(lp[1]);
+
+ read_exec_only = ((entry_2 >> 9) & 1) ^ 1;
+ contents = (entry_2 >> 10) & 3;
+ seg_not_present = ((entry_2 >> 15) & 1) ^ 1;
+ seg_32bit = (entry_2 >> 22) & 1;
+ limit_in_pages = (entry_2 >> 23) & 1;
+ useable = (entry_2 >> 20) & 1;
+#ifdef TARGET_ABI32
+ lm = 0;
+#else
+ lm = (entry_2 >> 21) & 1;
+#endif
+ flags = (seg_32bit << 0) | (contents << 1) |
+ (read_exec_only << 3) | (limit_in_pages << 4) |
+ (seg_not_present << 5) | (useable << 6) | (lm << 7);
+ limit = (entry_1 & 0xffff) | (entry_2 & 0xf0000);
+ base_addr = (entry_1 >> 16) |
+ (entry_2 & 0xff000000) |
+ ((entry_2 & 0xff) << 16);
+ target_ldt_info->base_addr = tswapl(base_addr);
+ target_ldt_info->limit = tswap32(limit);
+ target_ldt_info->flags = tswap32(flags);
+ unlock_user_struct(target_ldt_info, ptr, 1);
+ return 0;
+}
+
+#ifndef TARGET_ABI32
+abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
+{
+ abi_long ret;
+ abi_ulong val;
+ int idx;
+
+ switch(code) {
+ case TARGET_ARCH_SET_GS:
+ case TARGET_ARCH_SET_FS:
+ if (code == TARGET_ARCH_SET_GS)
+ idx = R_GS;
+ else
+ idx = R_FS;
+ cpu_x86_load_seg(env, idx, 0);
+ env->segs[idx].base = addr;
+ break;
+ case TARGET_ARCH_GET_GS:
+ case TARGET_ARCH_GET_FS:
+ if (code == TARGET_ARCH_GET_GS)
+ idx = R_GS;
+ else
+ idx = R_FS;
+ val = env->segs[idx].base;
+ if (put_user(val, addr, abi_ulong))
+ return -TARGET_EFAULT;
+ break;
+ default:
+ ret = -TARGET_EINVAL;
+ break;
+ }
+ return 0;
+}
+#endif
+
#endif /* defined(TARGET_I386) */
/* this stack is the equivalent of the kernel stack associated with a
@@ -2660,7 +2960,7 @@
target_to_host_errno_table[host_to_target_errno_table[i]] = i;
/* automatic consistency check if same arch */
-#if defined(__i386__) && defined(TARGET_I386)
+#if defined(__i386__) && defined(TARGET_I386) && defined(TARGET_ABI32)
if (ie->target_cmd != ie->host_cmd) {
fprintf(stderr, "ERROR: ioctl: target=0x%x host=0x%x\n",
ie->target_cmd, ie->host_cmd);
@@ -2773,7 +3073,6 @@
ret = 0; /* avoid warning */
break;
case TARGET_NR_read:
- page_unprotect_range(arg2, arg3);
if (!(p = lock_user(VERIFY_WRITE, arg2, arg3, 0)))
goto efault;
ret = get_errno(read(arg1, p, arg3));
@@ -2786,10 +3085,8 @@
unlock_user(p, arg2, 0);
break;
case TARGET_NR_open:
- if (!(p = lock_user_string(arg1))) {
- return -TARGET_EFAULT;
- goto fail;
- }
+ if (!(p = lock_user_string(arg1)))
+ goto efault;
ret = get_errno(open(path(p),
target_to_host_bitmask(arg2, fcntl_flags_tbl),
arg3));
@@ -2820,8 +3117,9 @@
{
int status;
ret = get_errno(waitpid(arg1, &status, arg3));
- if (!is_error(ret) && arg2)
- tput32(arg2, status);
+ if (!is_error(ret) && arg2
+ && put_user_s32(status, arg2))
+ goto efault;
}
break;
#endif
@@ -2888,56 +3186,71 @@
argc = 0;
guest_argp = arg2;
- for (gp = guest_argp; tgetl(gp); gp++)
+ for (gp = guest_argp; ; gp++) {
+ if (get_user_ual(guest_argp, gp))
+ goto efault;
+ if (!guest_argp)
+ break;
argc++;
+ }
envc = 0;
guest_envp = arg3;
- for (gp = guest_envp; tgetl(gp); gp++)
+ for (gp = guest_envp; ; gp++) {
+ if (get_user_ual(guest_envp, gp))
+ goto efault;
+ if (!guest_envp)
+ break;
envc++;
+ }
argp = alloca((argc + 1) * sizeof(void *));
envp = alloca((envc + 1) * sizeof(void *));
for (gp = guest_argp, q = argp; ;
gp += sizeof(abi_ulong), q++) {
- addr = tgetl(gp);
+ if (get_user_ual(addr, gp))
+ goto execve_efault;
if (!addr)
break;
- if (!(*q = lock_user_string(addr))) {
- ret = -TARGET_EFAULT;
- goto execve_fail;
- }
+ if (!(*q = lock_user_string(addr)))
+ goto execve_efault;
}
*q = NULL;
for (gp = guest_envp, q = envp; ;
gp += sizeof(abi_ulong), q++) {
- addr = tgetl(gp);
+ if (get_user_ual(addr, gp))
+ goto execve_efault;
if (!addr)
break;
- if (!(*q = lock_user_string(addr))) {
- ret = -TARGET_EFAULT;
- goto execve_fail;
- }
+ if (!(*q = lock_user_string(addr)))
+ goto execve_efault;
}
*q = NULL;
- if (!(p = lock_user_string(arg1))) {
- ret = -TARGET_EFAULT;
- goto execve_fail;
- }
+ if (!(p = lock_user_string(arg1)))
+ goto execve_efault;
ret = get_errno(execve(p, argp, envp));
unlock_user(p, arg1, 0);
- execve_fail:
+ goto execve_end;
+
+ execve_efault:
+ ret = -TARGET_EFAULT;
+
+ execve_end:
for (gp = guest_argp, q = argp; *q;
gp += sizeof(abi_ulong), q++) {
- addr = tgetl(gp);
+ if (get_user_ual(addr, gp)
+ || !addr)
+ break;
unlock_user(*q, addr, 0);
}
for (gp = guest_envp, q = envp; *q;
gp += sizeof(abi_ulong), q++) {
- addr = tgetl(gp);
+ if (get_user_ual(addr, gp)
+ || !addr)
+ break;
unlock_user(*q, addr, 0);
}
}
@@ -2953,8 +3266,10 @@
{
time_t host_time;
ret = get_errno(time(&host_time));
- if (!is_error(ret) && arg1)
- tputl(arg1, host_time);
+ if (!is_error(ret)
+ && arg1
+ && put_user_sal(host_time, arg1))
+ goto efault;
}
break;
#endif
@@ -3028,7 +3343,8 @@
case TARGET_NR_stime:
{
time_t host_time;
- host_time = tgetl(arg1);
+ if (get_user_sal(host_time, arg1))
+ goto efault;
ret = get_errno(stime(&host_time));
}
break;
@@ -3187,8 +3503,9 @@
env->gpr[3][env->current_tc] = host_pipe[1];
ret = host_pipe[0];
#else
- tput32(arg1, host_pipe[0]);
- tput32(arg1 + 4, host_pipe[1]);
+ if (put_user_s32(host_pipe[0], arg1)
+ || put_user_s32(host_pipe[1], arg1 + sizeof(host_pipe[0])))
+ goto efault;
#endif
}
}
@@ -3725,7 +4042,7 @@
#endif
#ifdef TARGET_NR_mmap
case TARGET_NR_mmap:
-#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_CRIS)
+#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_CRIS)
{
abi_ulong *v;
abi_ulong v1, v2, v3, v4, v5, v6;
@@ -4047,42 +4364,19 @@
if (!lock_user_struct(VERIFY_WRITE, target_st, arg2, 0))
goto efault;
-#if defined(TARGET_MIPS) || (defined(TARGET_SPARC64) && !defined(TARGET_ABI32))
- target_st->st_dev = tswap32(st.st_dev);
-#else
- target_st->st_dev = tswap16(st.st_dev);
-#endif
- target_st->st_ino = tswapl(st.st_ino);
-#if defined(TARGET_PPC) || defined(TARGET_MIPS)
- target_st->st_mode = tswapl(st.st_mode); /* XXX: check this */
- target_st->st_uid = tswap32(st.st_uid);
- target_st->st_gid = tswap32(st.st_gid);
-#elif defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
- target_st->st_mode = tswap32(st.st_mode);
- target_st->st_uid = tswap32(st.st_uid);
- target_st->st_gid = tswap32(st.st_gid);
-#else
- target_st->st_mode = tswap16(st.st_mode);
- target_st->st_uid = tswap16(st.st_uid);
- target_st->st_gid = tswap16(st.st_gid);
-#endif
-#if defined(TARGET_MIPS)
- /* If this is the same on PPC, then just merge w/ the above ifdef */
- target_st->st_nlink = tswapl(st.st_nlink);
- target_st->st_rdev = tswapl(st.st_rdev);
-#elif defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
- target_st->st_nlink = tswap32(st.st_nlink);
- target_st->st_rdev = tswap32(st.st_rdev);
-#else
- target_st->st_nlink = tswap16(st.st_nlink);
- target_st->st_rdev = tswap16(st.st_rdev);
-#endif
- target_st->st_size = tswapl(st.st_size);
- target_st->st_blksize = tswapl(st.st_blksize);
- target_st->st_blocks = tswapl(st.st_blocks);
- target_st->target_st_atime = tswapl(st.st_atime);
- target_st->target_st_mtime = tswapl(st.st_mtime);
- target_st->target_st_ctime = tswapl(st.st_ctime);
+ __put_user(st.st_dev, &target_st->st_dev);
+ __put_user(st.st_ino, &target_st->st_ino);
+ __put_user(st.st_mode, &target_st->st_mode);
+ __put_user(st.st_uid, &target_st->st_uid);
+ __put_user(st.st_gid, &target_st->st_gid);
+ __put_user(st.st_nlink, &target_st->st_nlink);
+ __put_user(st.st_rdev, &target_st->st_rdev);
+ __put_user(st.st_size, &target_st->st_size);
+ __put_user(st.st_blksize, &target_st->st_blksize);
+ __put_user(st.st_blocks, &target_st->st_blocks);
+ __put_user(st.st_atime, &target_st->target_st_atime);
+ __put_user(st.st_mtime, &target_st->target_st_mtime);
+ __put_user(st.st_ctime, &target_st->target_st_ctime);
unlock_user_struct(target_st, arg2, 1);
}
}
@@ -4119,11 +4413,12 @@
rusage_ptr = NULL;
ret = get_errno(wait4(arg1, &status, arg3, rusage_ptr));
if (!is_error(ret)) {
- if (status_ptr)
- tputl(status_ptr, status);
- if (target_rusage) {
+ if (status_ptr) {
+ if (put_user_s32(status, status_ptr))
+ goto efault;
+ }
+ if (target_rusage)
host_to_target_rusage(target_rusage, &rusage);
- }
}
}
break;
@@ -4256,11 +4551,13 @@
{
#if defined (__x86_64__)
ret = get_errno(lseek(arg1, ((uint64_t )arg2 << 32) | arg3, arg5));
- tput64(arg4, ret);
+ if (put_user_s64(ret, arg4))
+ goto efault;
#else
int64_t res;
ret = get_errno(_llseek(arg1, arg2, arg3, &res, arg5));
- tput64(arg4, res);
+ if (put_user_s64(res, arg4))
+ goto efault;
#endif
}
break;
@@ -4526,8 +4823,9 @@
{
int deathsig;
ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5));
- if (!is_error(ret) && arg2)
- tput32(arg2, deathsig);
+ if (!is_error(ret) && arg2
+ && put_user_ual(deathsig, arg2))
+ goto efault;
}
break;
default:
@@ -4535,9 +4833,17 @@
break;
}
break;
+#ifdef TARGET_NR_arch_prctl
+ case TARGET_NR_arch_prctl:
+#if defined(TARGET_I386) && !defined(TARGET_ABI32)
+ ret = do_arch_prctl(cpu_env, arg1, arg2);
+ break;
+#else
+ goto unimplemented;
+#endif
+#endif
#ifdef TARGET_NR_pread
case TARGET_NR_pread:
- page_unprotect_range(arg2, arg3);
if (!(p = lock_user(VERIFY_WRITE, arg2, arg3, 0)))
goto efault;
ret = get_errno(pread(arg1, p, arg3, arg4));
@@ -4776,9 +5082,10 @@
uid_t ruid, euid, suid;
ret = get_errno(getresuid(&ruid, &euid, &suid));
if (!is_error(ret)) {
- tput16(arg1, tswap16(high2lowuid(ruid)));
- tput16(arg2, tswap16(high2lowuid(euid)));
- tput16(arg3, tswap16(high2lowuid(suid)));
+ if (put_user_u16(high2lowuid(ruid), arg1)
+ || put_user_u16(high2lowuid(euid), arg2)
+ || put_user_u16(high2lowuid(suid), arg3))
+ goto efault;
}
}
break;
@@ -4796,9 +5103,10 @@
gid_t rgid, egid, sgid;
ret = get_errno(getresgid(&rgid, &egid, &sgid));
if (!is_error(ret)) {
- tput16(arg1, tswap16(high2lowgid(rgid)));
- tput16(arg2, tswap16(high2lowgid(egid)));
- tput16(arg3, tswap16(high2lowgid(sgid)));
+ if (put_user_u16(high2lowgid(rgid), arg1)
+ || put_user_u16(high2lowgid(egid), arg2)
+ || put_user_u16(high2lowgid(sgid), arg3))
+ goto efault;
}
}
break;
@@ -4921,9 +5229,10 @@
uid_t ruid, euid, suid;
ret = get_errno(getresuid(&ruid, &euid, &suid));
if (!is_error(ret)) {
- tput32(arg1, tswap32(ruid));
- tput32(arg2, tswap32(euid));
- tput32(arg3, tswap32(suid));
+ if (put_user_u32(ruid, arg1)
+ || put_user_u32(euid, arg2)
+ || put_user_u32(suid, arg3))
+ goto efault;
}
}
break;
@@ -4939,9 +5248,10 @@
gid_t rgid, egid, sgid;
ret = get_errno(getresgid(&rgid, &egid, &sgid));
if (!is_error(ret)) {
- tput32(arg1, tswap32(rgid));
- tput32(arg2, tswap32(egid));
- tput32(arg3, tswap32(sgid));
+ if (put_user_u32(rgid, arg1)
+ || put_user_u32(egid, arg2)
+ || put_user_u32(sgid, arg3))
+ goto efault;
}
}
break;
@@ -5138,18 +5448,25 @@
#endif
#ifdef TARGET_NR_set_thread_area
case TARGET_NR_set_thread_area:
-#ifdef TARGET_MIPS
+#if defined(TARGET_MIPS)
((CPUMIPSState *) cpu_env)->tls_value = arg1;
ret = 0;
break;
+#elif defined(TARGET_I386) && defined(TARGET_ABI32)
+ ret = do_set_thread_area(cpu_env, arg1);
+ break;
#else
goto unimplemented_nowarn;
#endif
#endif
#ifdef TARGET_NR_get_thread_area
case TARGET_NR_get_thread_area:
+#if defined(TARGET_I386) && defined(TARGET_ABI32)
+ ret = do_get_thread_area(cpu_env, arg1);
+#else
goto unimplemented_nowarn;
#endif
+#endif
#ifdef TARGET_NR_getdomainname
case TARGET_NR_getdomainname:
goto unimplemented_nowarn;
Modified: trunk/src/host/qemu-neo1973/linux-user/syscall_defs.h
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/syscall_defs.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/syscall_defs.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -881,7 +881,7 @@
#define TARGET_MAP_NONBLOCK 0x10000 /* do not block on IO */
#endif
-#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_CRIS)
+#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_ARM) || defined(TARGET_CRIS)
struct target_stat {
unsigned short st_dev;
unsigned short __pad1;
@@ -1474,6 +1474,30 @@
unsigned long long st_ino;
};
+#elif defined(TARGET_I386) && !defined(TARGET_ABI32)
+struct target_stat {
+ abi_ulong st_dev;
+ abi_ulong st_ino;
+ abi_ulong st_nlink;
+
+ unsigned int st_mode;
+ unsigned int st_uid;
+ unsigned int st_gid;
+ unsigned int __pad0;
+ abi_ulong st_rdev;
+ abi_long st_size;
+ abi_long st_blksize;
+ abi_long st_blocks; /* Number 512-byte blocks allocated. */
+
+ abi_ulong target_st_atime;
+ abi_ulong target_st_atime_nsec;
+ abi_ulong target_st_mtime;
+ abi_ulong target_st_mtime_nsec;
+ abi_ulong target_st_ctime;
+ abi_ulong target_st_ctime_nsec;
+
+ abi_long __unused[3];
+};
#else
#error unsupported CPU
#endif
Modified: trunk/src/host/qemu-neo1973/linux-user/uaccess.c
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/uaccess.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/uaccess.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -37,15 +37,40 @@
return ret;
}
+/* XXX: use host strnlen if available ? */
+static int qemu_strnlen(const char *s, int max_len)
+{
+ int i;
+ for(i = 0; i < max_len; i++) {
+ if (s[i] == '\0')
+ break;
+ }
+ return i;
+}
-/* Return the length of a string in target memory. */
-/* FIXME - this doesn't check access_ok() - it's rather complicated to
- * do it correctly because we need to check the bytes in a page and then
- * skip to the next page and check the bytes there until we find the
- * terminator. There should be a general function to do this that
- * can look for any byte terminator in a buffer - not strlen().
- */
-abi_long target_strlen(abi_ulong gaddr)
+/* Return the length of a string in target memory or -TARGET_EFAULT if
+ access error */
+abi_long target_strlen(abi_ulong guest_addr1)
{
- return strlen(g2h(gaddr));
+ uint8_t *ptr;
+ abi_ulong guest_addr;
+ int max_len, len;
+
+ guest_addr = guest_addr1;
+ for(;;) {
+ max_len = TARGET_PAGE_SIZE - (guest_addr & ~TARGET_PAGE_MASK);
+ ptr = lock_user(VERIFY_READ, guest_addr, max_len, 1);
+ if (!ptr)
+ return -TARGET_EFAULT;
+ len = qemu_strnlen(ptr, max_len);
+ unlock_user(ptr, guest_addr, 0);
+ guest_addr += len;
+ /* we don't allow wrapping or integer overflow */
+ if (guest_addr == 0 ||
+ (guest_addr - guest_addr1) > 0x7fffffff)
+ return -TARGET_EFAULT;
+ if (len != max_len)
+ break;
+ }
+ return guest_addr - guest_addr1;
}
Modified: trunk/src/host/qemu-neo1973/linux-user/x86_64/syscall.h
===================================================================
--- trunk/src/host/qemu-neo1973/linux-user/x86_64/syscall.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/linux-user/x86_64/syscall.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -34,6 +34,7 @@
/* The size of each LDT entry. */
#define TARGET_LDT_ENTRY_SIZE 8
+#define TARGET_GDT_ENTRIES 16
#define TARGET_GDT_ENTRY_TLS_ENTRIES 3
#define TARGET_GDT_ENTRY_TLS_MIN 12
#define TARGET_GDT_ENTRY_TLS_MAX 14
@@ -90,3 +91,8 @@
};
#define UNAME_MACHINE "x86_64"
+
+#define TARGET_ARCH_SET_GS 0x1001
+#define TARGET_ARCH_SET_FS 0x1002
+#define TARGET_ARCH_GET_FS 0x1003
+#define TARGET_ARCH_GET_GS 0x1004
Modified: trunk/src/host/qemu-neo1973/loader.c
===================================================================
--- trunk/src/host/qemu-neo1973/loader.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/loader.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,8 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
#include "disas.h"
+#include "sysemu.h"
#include "uboot_image.h"
/* return the size or -1 if error */
Modified: trunk/src/host/qemu-neo1973/m68k-semi.c
===================================================================
--- trunk/src/host/qemu-neo1973/m68k-semi.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/m68k-semi.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -33,7 +33,9 @@
#include "qemu.h"
#define SEMIHOSTING_HEAP_SIZE (128 * 1024 * 1024)
#else
-#include "vl.h"
+#include "qemu-common.h"
+#include "sysemu.h"
+#include "gdbstub.h"
#include "softmmu-semi.h"
#endif
@@ -142,15 +144,23 @@
if (m68k_semi_is_fseek) {
/* FIXME: We've already lost the high bits of the fseek
return value. */
- tput32(args, 0);
+ /* FIXME - handle put_user() failure */
+ put_user_u32(0, args);
args += 4;
m68k_semi_is_fseek = 0;
}
- tput32(args, ret);
- tput32(args + 4, errno);
+ /* FIXME - handle put_user() failure */
+ put_user_u32(ret, args);
+ put_user_u32(errno, args + 4);
}
-#define ARG(x) tget32(args + (x) * 4)
+#define ARG(n) \
+({ \
+ target_ulong __arg; \
+ /* FIXME - handle get_user() failure */ \
+ get_user_ual(__arg, args + (n) * 4); \
+ __arg; \
+})
#define PARG(x) ((unsigned long)ARG(x))
void do_m68k_semihosting(CPUM68KState *env, int nr)
{
@@ -237,9 +247,10 @@
ARG(0), off, ARG(3));
} else {
off = lseek(ARG(0), off, ARG(3));
- tput32(args, off >> 32);
- tput32(args + 4, off);
- tput32(args + 8, errno);
+ /* FIXME - handle put_user() failure */
+ put_user_u32(off >> 32, args);
+ put_user_u32(off, args + 4);
+ put_user_u32(errno, args + 8);
}
return;
}
@@ -390,6 +401,7 @@
cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
result = 0;
}
- tput32(args, result);
- tput32(args + 4, errno);
+ /* FIXME - handle put_user() failure */
+ put_user_u32(result, args);
+ put_user_u32(errno, args + 4);
}
Modified: trunk/src/host/qemu-neo1973/monitor.c
===================================================================
--- trunk/src/host/qemu-neo1973/monitor.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/monitor.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,18 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw/hw.h"
+#include "hw/usb.h"
+#include "hw/pcmcia.h"
+#include "hw/pc.h"
+#include "hw/pci.h"
+#include "gdbstub.h"
+#include "net.h"
+#include "qemu-char.h"
+#include "sysemu.h"
+#include "console.h"
+#include "block.h"
+#include "audio/audio.h"
#include "disas.h"
#include <dirent.h>
@@ -253,7 +264,7 @@
}
/* get the current CPU defined by the user */
-int mon_set_cpu(int cpu_index)
+static int mon_set_cpu(int cpu_index)
{
CPUState *env;
@@ -266,7 +277,7 @@
return -1;
}
-CPUState *mon_get_cpu(void)
+static CPUState *mon_get_cpu(void)
{
if (!mon_cpu) {
mon_set_cpu(0);
Added: trunk/src/host/qemu-neo1973/net.h
===================================================================
--- trunk/src/host/qemu-neo1973/net.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/net.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,54 @@
+#ifndef QEMU_NET_H
+#define QEMU_NET_H
+
+/* VLANs support */
+
+typedef struct VLANClientState VLANClientState;
+
+struct VLANClientState {
+ IOReadHandler *fd_read;
+ /* Packets may still be sent if this returns zero. It's used to
+ rate-limit the slirp code. */
+ IOCanRWHandler *fd_can_read;
+ void *opaque;
+ struct VLANClientState *next;
+ struct VLANState *vlan;
+ char info_str[256];
+};
+
+struct VLANState {
+ int id;
+ VLANClientState *first_client;
+ struct VLANState *next;
+ unsigned int nb_guest_devs, nb_host_devs;
+};
+
+VLANState *qemu_find_vlan(int id);
+VLANClientState *qemu_new_vlan_client(VLANState *vlan,
+ IOReadHandler *fd_read,
+ IOCanRWHandler *fd_can_read,
+ void *opaque);
+int qemu_can_send_packet(VLANClientState *vc);
+void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
+void qemu_handler_true(void *opaque);
+
+void do_info_network(void);
+
+/* NIC info */
+
+#define MAX_NICS 8
+
+struct NICInfo {
+ uint8_t macaddr[6];
+ const char *model;
+ VLANState *vlan;
+};
+
+extern int nb_nics;
+extern NICInfo nd_table[MAX_NICS];
+
+/* Bluetooth support */
+#include "hw/bt.h"
+extern struct bt_piconet_s *local_piconet;
+
+#endif
Modified: trunk/src/host/qemu-neo1973/osdep.c
===================================================================
--- trunk/src/host/qemu-neo1973/osdep.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/osdep.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -33,10 +33,8 @@
#include <sys/statvfs.h>
#endif
-#include "cpu.h"
-#if defined(USE_KQEMU)
-#include "vl.h"
-#endif
+#include "qemu-common.h"
+#include "sysemu.h"
#ifdef _WIN32
#include <windows.h>
@@ -84,7 +82,7 @@
#include <sys/mman.h>
#include <fcntl.h>
-void *kqemu_vmalloc(size_t size)
+static void *kqemu_vmalloc(size_t size)
{
static int phys_ram_fd = -1;
static int phys_ram_size = 0;
@@ -166,7 +164,7 @@
return ptr;
}
-void kqemu_vfree(void *ptr)
+static void kqemu_vfree(void *ptr)
{
/* may be useful some day, but currently we do not need to free */
}
Modified: trunk/src/host/qemu-neo1973/osdep.h
===================================================================
--- trunk/src/host/qemu-neo1973/osdep.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/osdep.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -3,6 +3,44 @@
#include <stdarg.h>
+#ifndef glue
+#define xglue(x, y) x ## y
+#define glue(x, y) xglue(x, y)
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+#endif
+
+#ifndef likely
+#if __GNUC__ < 3
+#define __builtin_expect(x, n) (x)
+#endif
+
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+#ifndef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef always_inline
+#if (__GNUC__ < 3) || defined(__APPLE__)
+#define always_inline inline
+#else
+#define always_inline __attribute__ (( always_inline )) __inline__
+#endif
+#endif
+#define inline always_inline
+
+#ifdef __i386__
+#define REGPARM(n) __attribute((regparm(n)))
+#else
+#define REGPARM(n)
+#endif
+
#define qemu_printf printf
void *qemu_malloc(size_t size);
Modified: trunk/src/host/qemu-neo1973/pc-bios/README
===================================================================
--- trunk/src/host/qemu-neo1973/pc-bios/README 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/pc-bios/README 2007-11-19 18:54:17 UTC (rev 3443)
@@ -14,8 +14,8 @@
- OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable
firmware implementation. The goal is to implement a 100% IEEE
1275-1994 (referred to as Open Firmware) compliant firmware.
- The included Sparc32 image is built from SVN revision 171 and
- Sparc64 image from revision 169.
+ The included Sparc32 and Sparc64 images are built from SVN
+ revision 176.
- The PXE roms come from Rom-o-Matic etherboot 5.4.2.
pcnet32:pcnet32 -- [0x1022,0x2000]
Modified: trunk/src/host/qemu-neo1973/pc-bios/openbios-sparc32
===================================================================
(Binary files differ)
Modified: trunk/src/host/qemu-neo1973/pc-bios/openbios-sparc64
===================================================================
(Binary files differ)
Added: trunk/src/host/qemu-neo1973/qemu-char.h
===================================================================
--- trunk/src/host/qemu-neo1973/qemu-char.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/qemu-char.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,77 @@
+#ifndef QEMU_CHAR_H
+#define QEMU_CHAR_H
+
+/* character device */
+
+#define CHR_EVENT_BREAK 0 /* serial break char */
+#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
+#define CHR_EVENT_RESET 2 /* new connection established */
+
+
+#define CHR_IOCTL_SERIAL_SET_PARAMS 1
+typedef struct {
+ int speed;
+ int parity;
+ int data_bits;
+ int stop_bits;
+} QEMUSerialSetParams;
+
+#define CHR_IOCTL_SERIAL_SET_BREAK 2
+
+#define CHR_IOCTL_PP_READ_DATA 3
+#define CHR_IOCTL_PP_WRITE_DATA 4
+#define CHR_IOCTL_PP_READ_CONTROL 5
+#define CHR_IOCTL_PP_WRITE_CONTROL 6
+#define CHR_IOCTL_PP_READ_STATUS 7
+#define CHR_IOCTL_PP_EPP_READ_ADDR 8
+#define CHR_IOCTL_PP_EPP_READ 9
+#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
+#define CHR_IOCTL_PP_EPP_WRITE 11
+
+#define CHR_IOCTL_MODEM_HANDSHAKE 12
+
+typedef void IOEventHandler(void *opaque, int event);
+
+struct CharDriverState {
+ int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
+ void (*chr_update_read_handler)(struct CharDriverState *s);
+ int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
+ IOEventHandler *chr_event;
+ IOCanRWHandler *chr_can_read;
+ IOReadHandler *chr_read;
+ void *handler_opaque;
+ void (*chr_send_event)(struct CharDriverState *chr, int event);
+ void (*chr_close)(struct CharDriverState *chr);
+ void *opaque;
+ int focus;
+ QEMUBH *bh;
+};
+
+CharDriverState *qemu_chr_open(const char *filename);
+void qemu_chr_close(CharDriverState *chr);
+void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
+int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
+void qemu_chr_send_event(CharDriverState *s, int event);
+void qemu_chr_add_handlers(CharDriverState *s,
+ IOCanRWHandler *fd_can_read,
+ IOReadHandler *fd_read,
+ IOEventHandler *fd_event,
+ void *opaque);
+int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
+void qemu_chr_reset(CharDriverState *s);
+int qemu_chr_can_read(CharDriverState *s);
+void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
+
+/* async I/O support */
+
+int qemu_set_fd_handler2(int fd,
+ IOCanRWHandler *fd_read_poll,
+ IOHandler *fd_read,
+ IOHandler *fd_write,
+ void *opaque);
+int qemu_set_fd_handler(int fd,
+ IOHandler *fd_read,
+ IOHandler *fd_write,
+ void *opaque);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/qemu-common.h
===================================================================
--- trunk/src/host/qemu-neo1973/qemu-common.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/qemu-common.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -73,6 +73,8 @@
void qemu_bh_delete(QEMUBH *bh);
int qemu_bh_poll(void);
+uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
+
/* cutils.c */
void pstrcpy(char *buf, int buf_size, const char *str);
char *pstrcat(char *buf, int buf_size, const char *s);
@@ -80,4 +82,42 @@
int stristart(const char *str, const char *val, const char **ptr);
time_t mktimegm(struct tm *tm);
+/* Error handling. */
+
+void hw_error(const char *fmt, ...)
+ __attribute__ ((__format__ (__printf__, 1, 2)))
+ __attribute__ ((__noreturn__));
+
+/* IO callbacks. */
+typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
+typedef int IOCanRWHandler(void *opaque);
+typedef void IOHandler(void *opaque);
+
+struct ParallelIOArg {
+ void *buffer;
+ int count;
+};
+
+typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
+
+/* A load of opaque types so that device init declarations don't have to
+ pull in all the real definitions. */
+typedef struct NICInfo NICInfo;
+typedef struct AudioState AudioState;
+typedef struct BlockDriverState BlockDriverState;
+typedef struct DisplayState DisplayState;
+typedef struct TextConsole TextConsole;
+typedef struct CharDriverState CharDriverState;
+typedef struct VLANState VLANState;
+typedef struct QEMUFile QEMUFile;
+typedef struct i2c_bus i2c_bus;
+typedef struct i2c_slave i2c_slave;
+typedef struct SMBusDevice SMBusDevice;
+typedef struct QEMUTimer QEMUTimer;
+typedef struct PCIBus PCIBus;
+typedef struct PCIDevice PCIDevice;
+typedef struct SerialState SerialState;
+typedef struct IRQState *qemu_irq;
+struct pcmcia_card_s;
+
#endif
Added: trunk/src/host/qemu-neo1973/qemu-timer.h
===================================================================
--- trunk/src/host/qemu-neo1973/qemu-timer.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/qemu-timer.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,48 @@
+#ifndef QEMU_TIMER_H
+#define QEMU_TIMER_H
+
+/* timers */
+
+typedef struct QEMUClock QEMUClock;
+typedef void QEMUTimerCB(void *opaque);
+
+/* The real time clock should be used only for stuff which does not
+ change the virtual machine state, as it is run even if the virtual
+ machine is stopped. The real time clock has a frequency of 1000
+ Hz. */
+extern QEMUClock *rt_clock;
+
+/* The virtual clock is only run during the emulation. It is stopped
+ when the virtual machine is stopped. Virtual timers use a high
+ precision clock, usually cpu cycles (use ticks_per_sec). */
+extern QEMUClock *vm_clock;
+
+int64_t qemu_get_clock(QEMUClock *clock);
+
+QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
+void qemu_free_timer(QEMUTimer *ts);
+void qemu_del_timer(QEMUTimer *ts);
+void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
+int qemu_timer_pending(QEMUTimer *ts);
+
+extern int64_t ticks_per_sec;
+
+void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
+void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
+
+/* ptimer.c */
+typedef struct ptimer_state ptimer_state;
+typedef void (*ptimer_cb)(void *opaque);
+
+ptimer_state *ptimer_init(QEMUBH *bh);
+void ptimer_set_period(ptimer_state *s, int64_t period);
+void ptimer_set_freq(ptimer_state *s, uint32_t freq);
+void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
+uint64_t ptimer_get_count(ptimer_state *s);
+void ptimer_set_count(ptimer_state *s, uint64_t count);
+void ptimer_run(ptimer_state *s, int oneshot);
+void ptimer_stop(ptimer_state *s);
+void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
+void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
+
+#endif
Modified: trunk/src/host/qemu-neo1973/readline.c
===================================================================
--- trunk/src/host/qemu-neo1973/readline.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/readline.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
#define TERM_CMD_BUF_SIZE 4095
#define TERM_MAX_CMDS 64
Modified: trunk/src/host/qemu-neo1973/sdl.c
===================================================================
--- trunk/src/host/qemu-neo1973/sdl.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/sdl.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
+#include "sysemu.h"
#include <SDL.h>
Modified: trunk/src/host/qemu-neo1973/softmmu-semi.h
===================================================================
--- trunk/src/host/qemu-neo1973/softmmu-semi.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/softmmu-semi.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,15 +21,18 @@
cpu_memory_rw_debug(env, addr, &val, 1, 0);
return val;
}
-#define tget32(p) softmmu_tget32(env, p)
-#define tget8(p) softmmu_tget8(env, p)
+#define get_user_u32(arg, p) ({ arg = softmmu_tget32(env, p) ; 0; })
+#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
+#define get_user_ual(arg, p) get_user_u32(arg, p)
+
static inline void softmmu_tput32(CPUState *env, uint32_t addr, uint32_t val)
{
val = tswap32(val);
cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 1);
}
-#define tput32(p, val) softmmu_tput32(env, p, val)
+#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
+#define put_user_ual(arg, p) put_user_u32(arg, p)
static void *softmmu_lock_user(CPUState *env, uint32_t addr, uint32_t len,
int copy)
Modified: trunk/src/host/qemu-neo1973/softmmu_template.h
===================================================================
--- trunk/src/host/qemu-neo1973/softmmu_template.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/softmmu_template.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -282,7 +282,9 @@
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* XXX: not efficient, but simple */
- for(i = 0;i < DATA_SIZE; i++) {
+ /* Note: relies on the fact that tlb_fill() does not remove the
+ * previous page from the TLB cache. */
+ for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
mmu_idx, retaddr);
Added: trunk/src/host/qemu-neo1973/sysemu.h
===================================================================
--- trunk/src/host/qemu-neo1973/sysemu.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/sysemu.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -0,0 +1,176 @@
+#ifndef SYSEMU_H
+#define SYSEMU_H
+/* Misc. things related to the system emulator. */
+
+/* vl.c */
+extern const char *bios_name;
+extern const char *bios_dir;
+
+extern int vm_running;
+extern const char *qemu_name;
+
+typedef struct vm_change_state_entry VMChangeStateEntry;
+typedef void VMChangeStateHandler(void *opaque, int running);
+typedef void VMStopHandler(void *opaque, int reason);
+
+VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
+ void *opaque);
+void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
+
+int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
+void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
+
+void vm_start(void);
+void vm_stop(int reason);
+
+int64_t cpu_get_ticks(void);
+void cpu_enable_ticks(void);
+void cpu_disable_ticks(void);
+
+void qemu_system_reset_request(void);
+void qemu_system_shutdown_request(void);
+void qemu_system_powerdown_request(void);
+#if !defined(TARGET_SPARC)
+// Please implement a power failure function to signal the OS
+#define qemu_system_powerdown() do{}while(0)
+#else
+void qemu_system_powerdown(void);
+#endif
+
+void cpu_save(QEMUFile *f, void *opaque);
+int cpu_load(QEMUFile *f, void *opaque, int version_id);
+
+void do_savevm(const char *name);
+void do_loadvm(const char *name);
+void do_delvm(const char *name);
+void do_info_snapshots(void);
+
+void main_loop_wait(int timeout);
+
+/* Polling handling */
+
+/* return TRUE if no sleep should be done afterwards */
+typedef int PollingFunc(void *opaque);
+
+int qemu_add_polling_cb(PollingFunc *func, void *opaque);
+void qemu_del_polling_cb(PollingFunc *func, void *opaque);
+
+#ifdef _WIN32
+/* Wait objects handling */
+typedef void WaitObjectFunc(void *opaque);
+
+int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
+void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
+#endif
+
+/* TAP win32 */
+int tap_win32_init(VLANState *vlan, const char *ifname);
+
+/* SLIRP */
+void do_info_slirp(void);
+
+extern int ram_size;
+extern int bios_size;
+extern int rtc_utc;
+extern int rtc_start_date;
+extern int cirrus_vga_enabled;
+extern int vmsvga_enabled;
+extern int graphic_width;
+extern int graphic_height;
+extern int graphic_depth;
+extern const char *keyboard_layout;
+extern int win2k_install_hack;
+extern int alt_grab;
+extern int usb_enabled;
+extern int smp_cpus;
+extern int cursor_hide;
+extern int graphic_rotate;
+extern int no_quit;
+extern int semihosting_enabled;
+extern int autostart;
+extern int old_param;
+extern const char *bootp_filename;
+
+
+#ifdef USE_KQEMU
+extern int kqemu_allowed;
+#endif
+
+#define MAX_OPTION_ROMS 16
+extern const char *option_rom[MAX_OPTION_ROMS];
+extern int nb_option_roms;
+
+#ifdef TARGET_SPARC
+#define MAX_PROM_ENVS 128
+extern const char *prom_envs[MAX_PROM_ENVS];
+extern unsigned int nb_prom_envs;
+#endif
+
+/* XXX: make it dynamic */
+#define MAX_BIOS_SIZE (4 * 1024 * 1024)
+#if defined (TARGET_PPC)
+#define BIOS_SIZE (1024 * 1024)
+#elif defined (TARGET_SPARC64)
+#define BIOS_SIZE ((512 + 32) * 1024)
+#elif defined(TARGET_MIPS)
+#define BIOS_SIZE (4 * 1024 * 1024)
+#endif
+
+#define MAX_DISKS 4
+
+extern BlockDriverState *bs_table[MAX_DISKS + 1];
+extern BlockDriverState *sd_bdrv;
+extern BlockDriverState *mtd_bdrv;
+
+/* NOR flash devices */
+#define MAX_PFLASH 4
+extern BlockDriverState *pflash_table[MAX_PFLASH];
+
+/* serial ports */
+
+#define MAX_SERIAL_PORTS 4
+
+extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
+
+/* parallel ports */
+
+#define MAX_PARALLEL_PORTS 3
+
+extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
+
+#ifdef NEED_CPU_H
+/* loader.c */
+int get_image_size(const char *filename);
+int load_image(const char *filename, uint8_t *addr);
+int load_elf(const char *filename, int64_t virt_to_phys_addend,
+ uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
+int load_aout(const char *filename, uint8_t *addr);
+int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
+#endif
+
+#ifdef HAS_AUDIO
+struct soundhw {
+ const char *name;
+ const char *descr;
+ int enabled;
+ int isa;
+ union {
+ int (*init_isa) (AudioState *s, qemu_irq *pic);
+ int (*init_pci) (PCIBus *bus, AudioState *s);
+ } init;
+};
+
+extern struct soundhw soundhw[];
+#endif
+
+void do_usb_add(const char *devname);
+void do_usb_del(const char *devname);
+void usb_info(void);
+void usb_slave_info(void);
+
+extern struct modem_ops_s {
+ void *opaque;
+ void (*ring)(void *opaque);
+} modem_ops;
+
+#endif
Modified: trunk/src/host/qemu-neo1973/tap-win32.c
===================================================================
--- trunk/src/host/qemu-neo1973/tap-win32.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/tap-win32.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -26,7 +26,9 @@
* distribution); if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "net.h"
+#include "sysemu.h"
#include <stdio.h>
#include <windows.h>
Modified: trunk/src/host/qemu-neo1973/target-arm/nwfpe/double_cpdo.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-arm/nwfpe/double_cpdo.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-arm/nwfpe/double_cpdo.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -38,7 +38,7 @@
unsigned int DoubleCPDO(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
- float64 rFm, rFn = 0;
+ float64 rFm, rFn = float64_zero;
unsigned int Fd, Fm, Fn, nRc = 1;
//printk("DoubleCPDO(0x%08x)\n",opcode);
Modified: trunk/src/host/qemu-neo1973/target-arm/nwfpe/fpa11_cpdt.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-arm/nwfpe/fpa11_cpdt.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-arm/nwfpe/fpa11_cpdt.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -34,7 +34,8 @@
target_ulong addr = (target_ulong)(long)pMem;
FPA11 *fpa11 = GET_FPA11();
fpa11->fType[Fn] = typeSingle;
- fpa11->fpreg[Fn].fSingle = tget32(addr);
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(fpa11->fpreg[Fn].fSingle, addr);
}
static inline
@@ -46,11 +47,13 @@
p = (unsigned int*)&fpa11->fpreg[Fn].fDouble;
fpa11->fType[Fn] = typeDouble;
#ifdef WORDS_BIGENDIAN
- p[0] = tget32(addr); /* sign & exponent */
- p[1] = tget32(addr + 4);
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(p[0], addr); /* sign & exponent */
+ get_user_u32(p[1], addr + 4);
#else
- p[0] = tget32(addr + 4);
- p[1] = tget32(addr); /* sign & exponent */
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(p[0], addr + 4);
+ get_user_u32(p[1], addr); /* sign & exponent */
#endif
}
@@ -62,9 +65,10 @@
unsigned int *p;
p = (unsigned int*)&fpa11->fpreg[Fn].fExtended;
fpa11->fType[Fn] = typeExtended;
- p[0] = tget32(addr); /* sign & exponent */
- p[1] = tget32(addr + 8); /* ls bits */
- p[2] = tget32(addr + 4); /* ms bits */
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(p[0], addr); /* sign & exponent */
+ get_user_u32(p[1], addr + 8); /* ls bits */
+ get_user_u32(p[2], addr + 4); /* ms bits */
}
static inline
@@ -76,7 +80,8 @@
unsigned long x;
p = (unsigned int*)&(fpa11->fpreg[Fn]);
- x = tget32(addr);
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(x, addr);
fpa11->fType[Fn] = (x >> 14) & 0x00000003;
switch (fpa11->fType[Fn])
@@ -84,16 +89,18 @@
case typeSingle:
case typeDouble:
{
- p[0] = tget32(addr + 8); /* Single */
- p[1] = tget32(addr + 4); /* double msw */
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(p[0], addr + 8); /* Single */
+ get_user_u32(p[1], addr + 4); /* double msw */
p[2] = 0; /* empty */
}
break;
case typeExtended:
{
- p[1] = tget32(addr + 8);
- p[2] = tget32(addr + 4); /* msw */
+ /* FIXME - handle failure of get_user() */
+ get_user_u32(p[1], addr + 8);
+ get_user_u32(p[2], addr + 4); /* msw */
p[0] = (x & 0x80003fff);
}
break;
@@ -121,7 +128,8 @@
default: val = fpa11->fpreg[Fn].fSingle;
}
- tput32(addr, p[0]);
+ /* FIXME - handle put_user() failures */
+ put_user_u32(p[0], addr);
}
static inline
@@ -144,12 +152,13 @@
default: val = fpa11->fpreg[Fn].fDouble;
}
+ /* FIXME - handle put_user() failures */
#ifdef WORDS_BIGENDIAN
- tput32(addr, p[0]); /* msw */
- tput32(addr + 4, p[1]); /* lsw */
+ put_user_u32(p[0], addr); /* msw */
+ put_user_u32(p[1], addr + 4); /* lsw */
#else
- tput32(addr, p[1]); /* msw */
- tput32(addr + 4, p[0]); /* lsw */
+ put_user_u32(p[1], addr); /* msw */
+ put_user_u32(p[0], addr + 4); /* lsw */
#endif
}
@@ -174,9 +183,10 @@
default: val = fpa11->fpreg[Fn].fExtended;
}
- tput32(addr, p[0]); /* sign & exp */
- tput32(addr + 8, p[1]);
- tput32(addr + 4, p[2]); /* msw */
+ /* FIXME - handle put_user() failures */
+ put_user_u32(p[0], addr); /* sign & exp */
+ put_user_u32(p[1], addr + 8);
+ put_user_u32(p[2], addr + 4); /* msw */
}
static inline
@@ -194,17 +204,17 @@
case typeSingle:
case typeDouble:
{
- tput32(addr + 8, p[0]); /* single */
- tput32(addr + 4, p[1]); /* double msw */
- tput32(addr, nType << 14);
+ put_user_u32(p[0], addr + 8); /* single */
+ put_user_u32(p[1], addr + 4); /* double msw */
+ put_user_u32(nType << 14, addr);
}
break;
case typeExtended:
{
- tput32(addr + 4, p[2]); /* msw */
- tput32(addr + 8, p[1]);
- tput32(addr, (p[0] & 0x80003fff) | (nType << 14));
+ put_user_u32(p[2], addr + 4); /* msw */
+ put_user_u32(p[1], addr + 8);
+ put_user_u32((p[0] & 0x80003fff) | (nType << 14), addr);
}
break;
}
Modified: trunk/src/host/qemu-neo1973/target-arm/nwfpe/single_cpdo.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-arm/nwfpe/single_cpdo.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-arm/nwfpe/single_cpdo.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -38,7 +38,7 @@
unsigned int SingleCPDO(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
- float32 rFm, rFn = 0;
+ float32 rFm, rFn = float32_zero;
unsigned int Fd, Fm, Fn, nRc = 1;
Fm = getFm(opcode);
@@ -128,13 +128,11 @@
break;
case MNF_CODE:
- rFm ^= 0x80000000;
- fpa11->fpreg[Fd].fSingle = rFm;
+ fpa11->fpreg[Fd].fSingle = float32_chs(rFm);
break;
case ABS_CODE:
- rFm &= 0x7fffffff;
- fpa11->fpreg[Fd].fSingle = rFm;
+ fpa11->fpreg[Fd].fSingle = float32_abs(rFm);
break;
case RND_CODE:
Modified: trunk/src/host/qemu-neo1973/target-i386/cpu.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-i386/cpu.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-i386/cpu.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -340,6 +340,9 @@
#define EXCP11_ALGN 17
#define EXCP12_MCHK 18
+#define EXCP_SYSCALL 0x100 /* only happens in user only emulation
+ for syscall instruction */
+
enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
Modified: trunk/src/host/qemu-neo1973/target-i386/helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-i386/helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-i386/helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -971,8 +971,16 @@
}
#endif
+#if defined(CONFIG_USER_ONLY)
void helper_syscall(int next_eip_addend)
{
+ env->exception_index = EXCP_SYSCALL;
+ env->exception_next_eip = env->eip + next_eip_addend;
+ cpu_loop_exit();
+}
+#else
+void helper_syscall(int next_eip_addend)
+{
int selector;
if (!(env->efer & MSR_EFER_SCE)) {
@@ -1024,6 +1032,7 @@
env->eip = (uint32_t)env->star;
}
}
+#endif
void helper_sysret(int dflag)
{
@@ -1143,18 +1152,23 @@
{
SegmentCache *dt;
target_ulong ptr;
- int dpl, cpl;
+ int dpl, cpl, shift;
uint32_t e2;
dt = &env->idt;
- ptr = dt->base + (intno * 8);
+ if (env->hflags & HF_LMA_MASK) {
+ shift = 4;
+ } else {
+ shift = 3;
+ }
+ ptr = dt->base + (intno << shift);
e2 = ldl_kernel(ptr + 4);
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
cpl = env->hflags & HF_CPL_MASK;
/* check privledge if software int */
if (is_int && dpl < cpl)
- raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
+ raise_exception_err(EXCP0D_GPF, (intno << shift) + 2);
/* Since we emulate only user space, we cannot do more than
exiting the emulation with the suitable exception and error
@@ -1221,7 +1235,7 @@
* needed. It should only be called, if this is not an interrupt.
* Returns the new exception number.
*/
-int check_exception(int intno, int *error_code)
+static int check_exception(int intno, int *error_code)
{
char first_contributory = env->old_exception == 0 ||
(env->old_exception >= 10 &&
@@ -3037,7 +3051,7 @@
helper_fstt(ST0, A0);
}
-void fpu_set_exception(int mask)
+static void fpu_set_exception(int mask)
{
env->fpus |= mask;
if (env->fpus & (~env->fpuc & FPUC_EM))
Modified: trunk/src/host/qemu-neo1973/target-m68k/helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-m68k/helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-m68k/helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -255,7 +255,7 @@
/* +/-inf compares equal against itself, but sub returns nan. */
if (!float64_is_nan(src0)
&& !float64_is_nan(src1)) {
- res = 0;
+ res = float64_zero;
if (float64_lt_quiet(src0, res, &env->fp_status))
res = float64_chs(res);
}
Modified: trunk/src/host/qemu-neo1973/target-m68k/op.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-m68k/op.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-m68k/op.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -108,7 +108,7 @@
OP(zerof64)
{
- set_opf64(PARAM1, 0);
+ set_opf64(PARAM1, float64_zero);
FORCE_RET();
}
Modified: trunk/src/host/qemu-neo1973/target-mips/fop_template.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-mips/fop_template.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-mips/fop_template.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,14 +24,14 @@
#define OP_WLOAD_FREG(treg, tregname, FREG) \
void glue(glue(op_load_fpr_,tregname), FREG) (void) \
{ \
- treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX]; \
+ treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \
FORCE_RET(); \
}
#define OP_WSTORE_FREG(treg, tregname, FREG) \
void glue(glue(op_store_fpr_,tregname), FREG) (void) \
{ \
- env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg; \
+ env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \
FORCE_RET(); \
}
@@ -50,10 +50,10 @@
void glue(glue(op_load_fpr_,tregname), FREG) (void) \
{ \
if (env->hflags & MIPS_HFLAG_F64) \
- treg = env->fpu->fpr[FREG].fd; \
+ treg = env->fpu->fpr[FREG].d; \
else \
- treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
- env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
+ treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \
+ env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \
FORCE_RET(); \
}
@@ -61,10 +61,10 @@
void glue(glue(op_store_fpr_,tregname), FREG) (void) \
{ \
if (env->hflags & MIPS_HFLAG_F64) \
- env->fpu->fpr[FREG].fd = treg; \
+ env->fpu->fpr[FREG].d = treg; \
else { \
- env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
- env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg; \
+ env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \
+ env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \
} \
FORCE_RET(); \
}
@@ -81,14 +81,14 @@
#define OP_PSLOAD_FREG(treg, tregname, FREG) \
void glue(glue(op_load_fpr_,tregname), FREG) (void) \
{ \
- treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX]; \
+ treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \
FORCE_RET(); \
}
#define OP_PSSTORE_FREG(treg, tregname, FREG) \
void glue(glue(op_store_fpr_,tregname), FREG) (void) \
{ \
- env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg; \
+ env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \
FORCE_RET(); \
}
Modified: trunk/src/host/qemu-neo1973/target-mips/op.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-mips/op.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-mips/op.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -683,8 +683,8 @@
target_ulong tmp;
if (T1) {
- tmp = T0 << (0x40 - T1);
- T0 = (T0 >> T1) | tmp;
+ tmp = T0 << (0x40 - T1);
+ T0 = (T0 >> T1) | tmp;
}
FORCE_RET();
}
@@ -693,10 +693,8 @@
{
target_ulong tmp;
- if (T1) {
- tmp = T0 << (0x40 - (32 + T1));
- T0 = (T0 >> (32 + T1)) | tmp;
- }
+ tmp = T0 << (0x40 - (32 + T1));
+ T0 = (T0 >> (32 + T1)) | tmp;
FORCE_RET();
}
@@ -724,10 +722,10 @@
T0 &= 0x3F;
if (T0) {
- tmp = T1 << (0x40 - T0);
- T0 = (T1 >> T0) | tmp;
+ tmp = T1 << (0x40 - T0);
+ T0 = (T1 >> T0) | tmp;
} else
- T0 = T1;
+ T0 = T1;
FORCE_RET();
}
@@ -2682,7 +2680,7 @@
{ \
FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
- FDT2 ^= 1ULL << 63; \
+ FDT2 = float64_chs(FDT2); \
DEBUG_FPU_STATE(); \
FORCE_RET(); \
} \
@@ -2690,7 +2688,7 @@
{ \
FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
- FST2 ^= 1 << 31; \
+ FST2 = float32_chs(FST2); \
DEBUG_FPU_STATE(); \
FORCE_RET(); \
} \
@@ -2700,8 +2698,8 @@
FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
- FST2 ^= 1 << 31; \
- FSTH2 ^= 1 << 31; \
+ FST2 = float32_chs(FST2); \
+ FSTH2 = float32_chs(FSTH2); \
DEBUG_FPU_STATE(); \
FORCE_RET(); \
}
@@ -3091,7 +3089,7 @@
unsigned int pos = PARAM1;
unsigned int size = PARAM2;
- T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
+ T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
FORCE_RET();
}
@@ -3101,13 +3099,13 @@
unsigned int size = PARAM2;
target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
- T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
+ T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask));
FORCE_RET();
}
void op_wsbh(void)
{
- T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
+ T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF));
FORCE_RET();
}
@@ -3117,7 +3115,7 @@
unsigned int pos = PARAM1;
unsigned int size = PARAM2;
- T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
+ T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
FORCE_RET();
}
@@ -3125,7 +3123,7 @@
{
unsigned int pos = PARAM1;
unsigned int size = PARAM2;
- target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
+ target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
T0 = (T0 & ~mask) | ((T1 << pos) & mask);
FORCE_RET();
@@ -3139,7 +3137,8 @@
void op_dshd(void)
{
- T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
+ T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
+ T0 = (T1 << 32) | (T1 >> 32);
FORCE_RET();
}
#endif
Modified: trunk/src/host/qemu-neo1973/target-mips/op_helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-mips/op_helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-mips/op_helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -106,8 +106,8 @@
target_ulong tmp;
if (T1) {
- tmp = T0 << (0x40 - T1);
- T0 = (T0 >> T1) | tmp;
+ tmp = T0 << (0x40 - T1);
+ T0 = (T0 >> T1) | tmp;
}
}
@@ -115,10 +115,8 @@
{
target_ulong tmp;
- if (T1) {
- tmp = T0 << (0x40 - (32 + T1));
- T0 = (T0 >> (32 + T1)) | tmp;
- }
+ tmp = T0 << (0x40 - (32 + T1));
+ T0 = (T0 >> (32 + T1)) | tmp;
}
void do_dsllv (void)
@@ -142,10 +140,10 @@
T0 &= 0x3F;
if (T0) {
- tmp = T1 << (0x40 - T0);
- T0 = (T1 >> T0) | tmp;
+ tmp = T1 << (0x40 - T0);
+ T0 = (T1 >> T0) | tmp;
} else
- T0 = T1;
+ T0 = T1;
}
void do_dclo (void)
@@ -626,12 +624,10 @@
/* Complex FPU operations which may need stack space. */
-#define FLOAT_SIGN32 (1 << 31)
-#define FLOAT_SIGN64 (1ULL << 63)
-#define FLOAT_ONE32 (0x3f8 << 20)
-#define FLOAT_ONE64 (0x3ffULL << 52)
-#define FLOAT_TWO32 (1 << 30)
-#define FLOAT_TWO64 (1ULL << 62)
+#define FLOAT_ONE32 make_float32(0x3f8 << 20)
+#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
+#define FLOAT_TWO32 make_float32(1 << 30)
+#define FLOAT_TWO64 make_float64(1ULL << 62)
#define FLOAT_QNAN32 0x7fbfffff
#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
#define FLOAT_SNAN32 0x7fffffff
@@ -1054,7 +1050,7 @@
FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
update_fcr31(); \
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
- FDT2 = FLOAT_QNAN64; \
+ DT2 = FLOAT_QNAN64; \
} \
FLOAT_OP(name, s) \
{ \
@@ -1062,7 +1058,7 @@
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
update_fcr31(); \
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
- FST2 = FLOAT_QNAN32; \
+ WT2 = FLOAT_QNAN32; \
} \
FLOAT_OP(name, ps) \
{ \
@@ -1071,8 +1067,8 @@
FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
update_fcr31(); \
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
- FST2 = FLOAT_QNAN32; \
- FSTH2 = FLOAT_QNAN32; \
+ WT2 = FLOAT_QNAN32; \
+ WTH2 = FLOAT_QNAN32; \
} \
}
FLOAT_BINOP(add)
@@ -1086,14 +1082,14 @@
{
set_float_exception_flags(0, &env->fpu->fp_status);
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
- FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
+ FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
update_fcr31();
}
FLOAT_OP(recip2, s)
{
set_float_exception_flags(0, &env->fpu->fp_status);
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
- FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+ FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
update_fcr31();
}
FLOAT_OP(recip2, ps)
@@ -1101,8 +1097,8 @@
set_float_exception_flags(0, &env->fpu->fp_status);
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
- FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
- FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+ FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
+ FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
update_fcr31();
}
@@ -1111,7 +1107,7 @@
set_float_exception_flags(0, &env->fpu->fp_status);
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
- FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
+ FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
update_fcr31();
}
FLOAT_OP(rsqrt2, s)
@@ -1119,7 +1115,7 @@
set_float_exception_flags(0, &env->fpu->fp_status);
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
- FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+ FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
update_fcr31();
}
FLOAT_OP(rsqrt2, ps)
@@ -1129,8 +1125,8 @@
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
- FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
- FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+ FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
+ FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
update_fcr31();
}
@@ -1164,8 +1160,8 @@
void do_cmpabs_d_ ## op (long cc) \
{ \
int c; \
- FDT0 &= ~FLOAT_SIGN64; \
- FDT1 &= ~FLOAT_SIGN64; \
+ FDT0 = float64_chs(FDT0); \
+ FDT1 = float64_chs(FDT1); \
c = cond; \
update_fcr31(); \
if (c) \
@@ -1222,8 +1218,8 @@
void do_cmpabs_s_ ## op (long cc) \
{ \
int c; \
- FST0 &= ~FLOAT_SIGN32; \
- FST1 &= ~FLOAT_SIGN32; \
+ FST0 = float32_abs(FST0); \
+ FST1 = float32_abs(FST1); \
c = cond; \
update_fcr31(); \
if (c) \
@@ -1285,10 +1281,10 @@
void do_cmpabs_ps_ ## op (long cc) \
{ \
int cl, ch; \
- FST0 &= ~FLOAT_SIGN32; \
- FSTH0 &= ~FLOAT_SIGN32; \
- FST1 &= ~FLOAT_SIGN32; \
- FSTH1 &= ~FLOAT_SIGN32; \
+ FST0 = float32_abs(FST0); \
+ FSTH0 = float32_abs(FSTH0); \
+ FST1 = float32_abs(FST1); \
+ FSTH1 = float32_abs(FSTH1); \
cl = condl; \
ch = condh; \
update_fcr31(); \
Modified: trunk/src/host/qemu-neo1973/target-mips/translate.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-mips/translate.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-mips/translate.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1897,43 +1897,49 @@
goto fail;
gen_op_ext(lsb, msb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DEXTM:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb, msb + 1 + 32);
+ gen_op_dext(lsb, msb + 1 + 32);
break;
case OPC_DEXTU:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb + 32, msb + 1);
+ gen_op_dext(lsb + 32, msb + 1);
break;
case OPC_DEXT:
- gen_op_ext(lsb, msb + 1);
+ if (lsb + msb > 63)
+ goto fail;
+ gen_op_dext(lsb, msb + 1);
break;
+#endif
case OPC_INS:
if (lsb > msb)
goto fail;
GEN_LOAD_REG_TN(T0, rt);
gen_op_ins(lsb, msb - lsb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DINSM:
if (lsb > msb)
goto fail;
GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1 + 32);
+ gen_op_dins(lsb, msb - lsb + 1 + 32);
break;
case OPC_DINSU:
if (lsb > msb)
goto fail;
GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb + 32, msb - lsb + 1);
+ gen_op_dins(lsb + 32, msb - lsb + 1);
break;
case OPC_DINS:
if (lsb > msb)
goto fail;
GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1);
+ gen_op_dins(lsb, msb - lsb + 1);
break;
+#endif
default:
fail:
MIPS_INVAL("bitops");
@@ -6156,6 +6162,7 @@
break;
}
GEN_STORE_TN_REG(rd, T0);
+ break;
#endif
default: /* Invalid */
MIPS_INVAL("special3");
Modified: trunk/src/host/qemu-neo1973/target-mips/translate_init.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-mips/translate_init.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-mips/translate_init.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -129,6 +129,23 @@
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
},
{
+ .name = "4KEm",
+ .CP0_PRid = 0x00019100,
+ /* Config1 implemented, MIPS32R2, fixed mapping MMU,
+ no virtual icache, uncached coherency. */
+ .CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) |
+ (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ },
+ {
.name = "24Kc",
.CP0_PRid = 0x00019300,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
@@ -141,7 +158,7 @@
.CCRes = 2,
/* No DSP implemented. */
.CP0_Status_rw_bitmask = 0x1278FF1F,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
},
{
.name = "24Kf",
@@ -158,7 +175,7 @@
.CP0_Status_rw_bitmask = 0x3678FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
},
{
.name = "34Kf",
@@ -279,7 +296,7 @@
/* A generic CPU providing MIPS64 Release 2 features.
FIXME: Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R2-generic",
- .CP0_PRid = 0x00000000,
+ .CP0_PRid = 0x00010000,
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
Modified: trunk/src/host/qemu-neo1973/target-ppc/cpu.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/cpu.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/cpu.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,6 +23,8 @@
#include "config.h"
#include <inttypes.h>
+//#define PPC_EMULATE_32BITS_HYPV
+
#if defined (TARGET_PPC64)
/* PowerPC 64 definitions */
typedef uint64_t ppc_gpr_t;
@@ -89,35 +91,42 @@
/*****************************************************************************/
/* MMU model */
-enum {
- POWERPC_MMU_UNKNOWN = 0,
+typedef enum powerpc_mmu_t powerpc_mmu_t;
+enum powerpc_mmu_t {
+ POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
- POWERPC_MMU_32B,
+ POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
- POWERPC_MMU_SOFT_6xx,
+ POWERPC_MMU_SOFT_6xx = 0x00000002,
/* PowerPC 74xx MMU with software TLB */
- POWERPC_MMU_SOFT_74xx,
+ POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
- POWERPC_MMU_SOFT_4xx,
+ POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC 4xx MMU with software TLB and zones protections */
- POWERPC_MMU_SOFT_4xx_Z,
- /* PowerPC 4xx MMU in real mode only */
- POWERPC_MMU_REAL_4xx,
+ POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
+ /* PowerPC MMU in real mode only */
+ POWERPC_MMU_REAL = 0x00000006,
+ /* Freescale MPC8xx MMU model */
+ POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
- POWERPC_MMU_BOOKE,
+ POWERPC_MMU_BOOKE = 0x00000008,
/* BookE FSL MMU model */
- POWERPC_MMU_BOOKE_FSL,
+ POWERPC_MMU_BOOKE_FSL = 0x00000009,
/* PowerPC 601 MMU model (specific BATs format) */
- POWERPC_MMU_601,
+ POWERPC_MMU_601 = 0x0000000A,
#if defined(TARGET_PPC64)
+#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
- POWERPC_MMU_64B,
+ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
+ /* 620 variant (no segment exceptions) */
+ POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
#endif /* defined(TARGET_PPC64) */
};
/*****************************************************************************/
/* Exception model */
-enum {
+typedef enum powerpc_excp_t powerpc_excp_t;
+enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
@@ -167,8 +176,8 @@
POWERPC_EXCP_DECR = 10, /* Decrementer exception */
POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
- POWERPC_EXCP_DTLB = 13, /* Data TLB error */
- POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */
+ POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
+ POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
/* Vectors 16 to 31 are reserved */
POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
@@ -180,20 +189,14 @@
/* Vectors 38 to 63 are reserved */
/* Exceptions defined in the PowerPC server specification */
POWERPC_EXCP_RESET = 64, /* System reset exception */
-#if defined(TARGET_PPC64) /* PowerPC 64 */
POWERPC_EXCP_DSEG = 65, /* Data segment exception */
POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
-#endif /* defined(TARGET_PPC64) */
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
-#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_TRACE = 68, /* Trace exception */
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
-#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
/* 40x specific exceptions */
POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
@@ -203,21 +206,27 @@
/* 602 specific exceptions */
POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
/* 602/603 specific exceptions */
- POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */
+ POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
/* Exceptions available on most PowerPC */
POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
- POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */
- POWERPC_EXCP_SMI = 83, /* System management interrupt */
- POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */
+ POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
+ POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
+ POWERPC_EXCP_SMI = 84, /* System management interrupt */
+ POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
/* 7xx/74xx specific exceptions */
- POWERPC_EXCP_THERM = 85, /* Thermal interrupt */
+ POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
/* 74xx specific exceptions */
- POWERPC_EXCP_VPUA = 86, /* Vector assist exception */
+ POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
/* 970FX specific exceptions */
- POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */
- POWERPC_EXCP_MAINT = 88, /* Maintenance exception */
+ POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
+ POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
+ /* Freescale embeded cores specific exceptions */
+ POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
+ POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
+ POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
+ POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
/* EOL */
POWERPC_EXCP_NB = 96,
/* Qemu exceptions: used internally during code translation */
@@ -269,7 +278,8 @@
/*****************************************************************************/
/* Input pins model */
-enum {
+typedef enum powerpc_input_t powerpc_input_t;
+enum powerpc_input_t {
PPC_FLAGS_INPUT_UNKNOWN = 0,
/* PowerPC 6xx bus */
PPC_FLAGS_INPUT_6xx,
@@ -281,6 +291,8 @@
PPC_FLAGS_INPUT_970,
/* PowerPC 401 bus */
PPC_FLAGS_INPUT_401,
+ /* Freescale RCPU bus */
+ PPC_FLAGS_INPUT_RCPU,
};
#define PPC_INPUT(env) (env->bus_model)
@@ -305,11 +317,9 @@
#if !defined(CONFIG_USER_ONLY)
void (*oea_read)(void *opaque, int spr_num);
void (*oea_write)(void *opaque, int spr_num);
-#if defined(TARGET_PPC64H)
void (*hea_read)(void *opaque, int spr_num);
void (*hea_write)(void *opaque, int spr_num);
#endif
-#endif
const unsigned char *name;
};
@@ -348,9 +358,10 @@
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
-#define MSR_HV 60 /* hypervisor state hflags */
+#define MSR_SHV 60 /* hypervisor state hflags */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */
+#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
#define MSR_VR 25 /* altivec available x hflags */
#define MSR_SPE 25 /* SPE enable for BookE x hflags */
@@ -384,9 +395,10 @@
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
-#define msr_hv ((env->msr >> MSR_HV) & 1)
+#define msr_shv ((env->msr >> MSR_SHV) & 1)
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_icm ((env->msr >> MSR_ICM) & 1)
+#define msr_thv ((env->msr >> MSR_THV) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1)
#define msr_spe ((env->msr >> MSR_SE) & 1)
@@ -417,25 +429,42 @@
#define msr_pmm ((env->msr >> MSR_PMM) & 1)
#define msr_ri ((env->msr >> MSR_RI) & 1)
#define msr_le ((env->msr >> MSR_LE) & 1)
+/* Hypervisor bit is more specific */
+#if defined(TARGET_PPC64)
+#define MSR_HVB (1ULL << MSR_SHV)
+#define msr_hv msr_shv
+#else
+#if defined(PPC_EMULATE_32BITS_HYPV)
+#define MSR_HVB (1ULL << MSR_THV)
+#define msr_hv msr_thv
+#else
+#define MSR_HVB (0ULL)
+#define msr_hv (0)
+#endif
+#endif
enum {
- POWERPC_FLAG_NONE = 0x00000000,
+ POWERPC_FLAG_NONE = 0x00000000,
/* Flag for MSR bit 25 signification (VRE/SPE) */
- POWERPC_FLAG_SPE = 0x00000001,
- POWERPC_FLAG_VRE = 0x00000002,
+ POWERPC_FLAG_SPE = 0x00000001,
+ POWERPC_FLAG_VRE = 0x00000002,
/* Flag for MSR bit 17 signification (TGPR/CE) */
- POWERPC_FLAG_TGPR = 0x00000004,
- POWERPC_FLAG_CE = 0x00000008,
+ POWERPC_FLAG_TGPR = 0x00000004,
+ POWERPC_FLAG_CE = 0x00000008,
/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
- POWERPC_FLAG_SE = 0x00000010,
- POWERPC_FLAG_DWE = 0x00000020,
- POWERPC_FLAG_UBLE = 0x00000040,
+ POWERPC_FLAG_SE = 0x00000010,
+ POWERPC_FLAG_DWE = 0x00000020,
+ POWERPC_FLAG_UBLE = 0x00000040,
/* Flag for MSR bit 9 signification (BE/DE) */
- POWERPC_FLAG_BE = 0x00000080,
- POWERPC_FLAG_DE = 0x00000100,
- /* Flag for MSR but 2 signification (PX/PMM) */
- POWERPC_FLAG_PX = 0x00000200,
- POWERPC_FLAG_PMM = 0x00000400,
+ POWERPC_FLAG_BE = 0x00000080,
+ POWERPC_FLAG_DE = 0x00000100,
+ /* Flag for MSR bit 2 signification (PX/PMM) */
+ POWERPC_FLAG_PX = 0x00000200,
+ POWERPC_FLAG_PMM = 0x00000400,
+ /* Flag for special features */
+ /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
+ POWERPC_FLAG_RTC_CLK = 0x00010000,
+ POWERPC_FLAG_BUS_CLK = 0x00020000,
};
/*****************************************************************************/
@@ -510,21 +539,17 @@
/*****************************************************************************/
/* The whole PowerPC CPU context */
-#if defined(TARGET_PPC64H)
#define NB_MMU_MODES 3
-#else
-#define NB_MMU_MODES 2
-#endif
struct CPUPPCState {
/* First are the most commonly used resources
* during translated code execution
*/
-#if TARGET_GPR_BITS > HOST_LONG_BITS
+#if (HOST_LONG_BITS == 32)
/* temporary fixed-point registers
- * used to emulate 64 bits target on 32 bits hosts
+ * used to emulate 64 bits registers on 32 bits hosts
*/
- ppc_gpr_t t0, t1, t2;
+ uint64_t t0, t1, t2;
#endif
ppc_avr_t avr0, avr1, avr2;
@@ -621,10 +646,9 @@
/* Those resources are used during exception processing */
/* CPU model definition */
target_ulong msr_mask;
- uint8_t mmu_model;
- uint8_t excp_model;
- uint8_t bus_model;
- uint8_t pad;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
int bfd_mach;
uint32_t flags;
@@ -742,12 +766,10 @@
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
-#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
-#endif
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
@@ -783,9 +805,7 @@
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
-#if defined(TARGET_PPC64H)
#define MMU_MODE2_SUFFIX _hypv
-#endif
#define MMU_USER_IDX 0
static inline int cpu_mmu_index (CPUState *env)
{
@@ -808,394 +828,454 @@
#define xer_bc env->xer[0]
/* SPR definitions */
-#define SPR_MQ (0x000)
-#define SPR_XER (0x001)
-#define SPR_601_VRTCU (0x004)
-#define SPR_601_VRTCL (0x005)
-#define SPR_601_UDECR (0x006)
-#define SPR_LR (0x008)
-#define SPR_CTR (0x009)
-#define SPR_DSISR (0x012)
-#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
-#define SPR_601_RTCU (0x014)
-#define SPR_601_RTCL (0x015)
-#define SPR_DECR (0x016)
-#define SPR_SDR1 (0x019)
-#define SPR_SRR0 (0x01A)
-#define SPR_SRR1 (0x01B)
-#define SPR_AMR (0x01D)
-#define SPR_BOOKE_PID (0x030)
-#define SPR_BOOKE_DECAR (0x036)
-#define SPR_BOOKE_CSRR0 (0x03A)
-#define SPR_BOOKE_CSRR1 (0x03B)
-#define SPR_BOOKE_DEAR (0x03D)
-#define SPR_BOOKE_ESR (0x03E)
-#define SPR_BOOKE_IVPR (0x03F)
-#define SPR_8xx_EIE (0x050)
-#define SPR_8xx_EID (0x051)
-#define SPR_8xx_NRE (0x052)
-#define SPR_CTRL (0x088)
-#define SPR_58x_CMPA (0x090)
-#define SPR_58x_CMPB (0x091)
-#define SPR_58x_CMPC (0x092)
-#define SPR_58x_CMPD (0x093)
-#define SPR_58x_ICR (0x094)
-#define SPR_58x_DER (0x094)
-#define SPR_58x_COUNTA (0x096)
-#define SPR_58x_COUNTB (0x097)
-#define SPR_UCTRL (0x098)
-#define SPR_58x_CMPE (0x098)
-#define SPR_58x_CMPF (0x099)
-#define SPR_58x_CMPG (0x09A)
-#define SPR_58x_CMPH (0x09B)
-#define SPR_58x_LCTRL1 (0x09C)
-#define SPR_58x_LCTRL2 (0x09D)
-#define SPR_58x_ICTRL (0x09E)
-#define SPR_58x_BAR (0x09F)
-#define SPR_VRSAVE (0x100)
-#define SPR_USPRG0 (0x100)
-#define SPR_USPRG1 (0x101)
-#define SPR_USPRG2 (0x102)
-#define SPR_USPRG3 (0x103)
-#define SPR_USPRG4 (0x104)
-#define SPR_USPRG5 (0x105)
-#define SPR_USPRG6 (0x106)
-#define SPR_USPRG7 (0x107)
-#define SPR_VTBL (0x10C)
-#define SPR_VTBU (0x10D)
-#define SPR_SPRG0 (0x110)
-#define SPR_SPRG1 (0x111)
-#define SPR_SPRG2 (0x112)
-#define SPR_SPRG3 (0x113)
-#define SPR_SPRG4 (0x114)
-#define SPR_SCOMC (0x114)
-#define SPR_SPRG5 (0x115)
-#define SPR_SCOMD (0x115)
-#define SPR_SPRG6 (0x116)
-#define SPR_SPRG7 (0x117)
-#define SPR_ASR (0x118)
-#define SPR_EAR (0x11A)
-#define SPR_TBL (0x11C)
-#define SPR_TBU (0x11D)
-#define SPR_TBU40 (0x11E)
-#define SPR_SVR (0x11E)
-#define SPR_BOOKE_PIR (0x11E)
-#define SPR_PVR (0x11F)
-#define SPR_HSPRG0 (0x130)
-#define SPR_BOOKE_DBSR (0x130)
-#define SPR_HSPRG1 (0x131)
-#define SPR_HDSISR (0x132)
-#define SPR_HDAR (0x133)
-#define SPR_BOOKE_DBCR0 (0x134)
-#define SPR_IBCR (0x135)
-#define SPR_PURR (0x135)
-#define SPR_BOOKE_DBCR1 (0x135)
-#define SPR_DBCR (0x136)
-#define SPR_HDEC (0x136)
-#define SPR_BOOKE_DBCR2 (0x136)
-#define SPR_HIOR (0x137)
-#define SPR_MBAR (0x137)
-#define SPR_RMOR (0x138)
-#define SPR_BOOKE_IAC1 (0x138)
-#define SPR_HRMOR (0x139)
-#define SPR_BOOKE_IAC2 (0x139)
-#define SPR_HSRR0 (0x13A)
-#define SPR_BOOKE_IAC3 (0x13A)
-#define SPR_HSRR1 (0x13B)
-#define SPR_BOOKE_IAC4 (0x13B)
-#define SPR_LPCR (0x13C)
-#define SPR_BOOKE_DAC1 (0x13C)
-#define SPR_LPIDR (0x13D)
-#define SPR_DABR2 (0x13D)
-#define SPR_BOOKE_DAC2 (0x13D)
-#define SPR_BOOKE_DVC1 (0x13E)
-#define SPR_BOOKE_DVC2 (0x13F)
-#define SPR_BOOKE_TSR (0x150)
-#define SPR_BOOKE_TCR (0x154)
-#define SPR_BOOKE_IVOR0 (0x190)
-#define SPR_BOOKE_IVOR1 (0x191)
-#define SPR_BOOKE_IVOR2 (0x192)
-#define SPR_BOOKE_IVOR3 (0x193)
-#define SPR_BOOKE_IVOR4 (0x194)
-#define SPR_BOOKE_IVOR5 (0x195)
-#define SPR_BOOKE_IVOR6 (0x196)
-#define SPR_BOOKE_IVOR7 (0x197)
-#define SPR_BOOKE_IVOR8 (0x198)
-#define SPR_BOOKE_IVOR9 (0x199)
-#define SPR_BOOKE_IVOR10 (0x19A)
-#define SPR_BOOKE_IVOR11 (0x19B)
-#define SPR_BOOKE_IVOR12 (0x19C)
-#define SPR_BOOKE_IVOR13 (0x19D)
-#define SPR_BOOKE_IVOR14 (0x19E)
-#define SPR_BOOKE_IVOR15 (0x19F)
-#define SPR_BOOKE_SPEFSCR (0x200)
-#define SPR_E500_BBEAR (0x201)
-#define SPR_E500_BBTAR (0x202)
-#define SPR_ATBL (0x20E)
-#define SPR_ATBU (0x20F)
-#define SPR_IBAT0U (0x210)
-#define SPR_BOOKE_IVOR32 (0x210)
-#define SPR_IBAT0L (0x211)
-#define SPR_BOOKE_IVOR33 (0x211)
-#define SPR_IBAT1U (0x212)
-#define SPR_BOOKE_IVOR34 (0x212)
-#define SPR_IBAT1L (0x213)
-#define SPR_BOOKE_IVOR35 (0x213)
-#define SPR_IBAT2U (0x214)
-#define SPR_BOOKE_IVOR36 (0x214)
-#define SPR_IBAT2L (0x215)
-#define SPR_E500_L1CFG0 (0x215)
-#define SPR_BOOKE_IVOR37 (0x215)
-#define SPR_IBAT3U (0x216)
-#define SPR_E500_L1CFG1 (0x216)
-#define SPR_IBAT3L (0x217)
-#define SPR_DBAT0U (0x218)
-#define SPR_DBAT0L (0x219)
-#define SPR_DBAT1U (0x21A)
-#define SPR_DBAT1L (0x21B)
-#define SPR_DBAT2U (0x21C)
-#define SPR_DBAT2L (0x21D)
-#define SPR_DBAT3U (0x21E)
-#define SPR_DBAT3L (0x21F)
-#define SPR_IBAT4U (0x230)
-#define SPR_IBAT4L (0x231)
-#define SPR_IBAT5U (0x232)
-#define SPR_IBAT5L (0x233)
-#define SPR_IBAT6U (0x234)
-#define SPR_IBAT6L (0x235)
-#define SPR_IBAT7U (0x236)
-#define SPR_IBAT7L (0x237)
-#define SPR_DBAT4U (0x238)
-#define SPR_DBAT4L (0x239)
-#define SPR_DBAT5U (0x23A)
-#define SPR_BOOKE_MCSRR0 (0x23A)
-#define SPR_DBAT5L (0x23B)
-#define SPR_BOOKE_MCSRR1 (0x23B)
-#define SPR_DBAT6U (0x23C)
-#define SPR_BOOKE_MCSR (0x23C)
-#define SPR_DBAT6L (0x23D)
-#define SPR_E500_MCAR (0x23D)
-#define SPR_DBAT7U (0x23E)
-#define SPR_BOOKE_DSRR0 (0x23E)
-#define SPR_DBAT7L (0x23F)
-#define SPR_BOOKE_DSRR1 (0x23F)
-#define SPR_BOOKE_SPRG8 (0x25C)
-#define SPR_BOOKE_SPRG9 (0x25D)
-#define SPR_BOOKE_MAS0 (0x270)
-#define SPR_BOOKE_MAS1 (0x271)
-#define SPR_BOOKE_MAS2 (0x272)
-#define SPR_BOOKE_MAS3 (0x273)
-#define SPR_BOOKE_MAS4 (0x274)
-#define SPR_BOOKE_MAS6 (0x276)
-#define SPR_BOOKE_PID1 (0x279)
-#define SPR_BOOKE_PID2 (0x27A)
-#define SPR_BOOKE_TLB0CFG (0x2B0)
-#define SPR_BOOKE_TLB1CFG (0x2B1)
-#define SPR_BOOKE_TLB2CFG (0x2B2)
-#define SPR_BOOKE_TLB3CFG (0x2B3)
-#define SPR_BOOKE_EPR (0x2BE)
-#define SPR_PERF0 (0x300)
-#define SPR_PERF1 (0x301)
-#define SPR_PERF2 (0x302)
-#define SPR_PERF3 (0x303)
-#define SPR_PERF4 (0x304)
-#define SPR_PERF5 (0x305)
-#define SPR_PERF6 (0x306)
-#define SPR_PERF7 (0x307)
-#define SPR_PERF8 (0x308)
-#define SPR_PERF9 (0x309)
-#define SPR_PERFA (0x30A)
-#define SPR_PERFB (0x30B)
-#define SPR_PERFC (0x30C)
-#define SPR_PERFD (0x30D)
-#define SPR_PERFE (0x30E)
-#define SPR_PERFF (0x30F)
-#define SPR_UPERF0 (0x310)
-#define SPR_UPERF1 (0x311)
-#define SPR_UPERF2 (0x312)
-#define SPR_UPERF3 (0x313)
-#define SPR_UPERF4 (0x314)
-#define SPR_UPERF5 (0x315)
-#define SPR_UPERF6 (0x316)
-#define SPR_UPERF7 (0x317)
-#define SPR_UPERF8 (0x318)
-#define SPR_UPERF9 (0x319)
-#define SPR_UPERFA (0x31A)
-#define SPR_UPERFB (0x31B)
-#define SPR_UPERFC (0x31C)
-#define SPR_UPERFD (0x31D)
-#define SPR_UPERFE (0x31E)
-#define SPR_UPERFF (0x31F)
-#define SPR_440_INV0 (0x370)
-#define SPR_440_INV1 (0x371)
-#define SPR_440_INV2 (0x372)
-#define SPR_440_INV3 (0x373)
-#define SPR_440_ITV0 (0x374)
-#define SPR_440_ITV1 (0x375)
-#define SPR_440_ITV2 (0x376)
-#define SPR_440_ITV3 (0x377)
-#define SPR_440_CCR1 (0x378)
-#define SPR_DCRIPR (0x37B)
-#define SPR_PPR (0x380)
-#define SPR_440_DNV0 (0x390)
-#define SPR_440_DNV1 (0x391)
-#define SPR_440_DNV2 (0x392)
-#define SPR_440_DNV3 (0x393)
-#define SPR_440_DTV0 (0x394)
-#define SPR_440_DTV1 (0x395)
-#define SPR_440_DTV2 (0x396)
-#define SPR_440_DTV3 (0x397)
-#define SPR_440_DVLIM (0x398)
-#define SPR_440_IVLIM (0x399)
-#define SPR_440_RSTCFG (0x39B)
-#define SPR_BOOKE_DCDBTRL (0x39C)
-#define SPR_BOOKE_DCDBTRH (0x39D)
-#define SPR_BOOKE_ICDBTRL (0x39E)
-#define SPR_BOOKE_ICDBTRH (0x39F)
-#define SPR_UMMCR2 (0x3A0)
-#define SPR_UPMC5 (0x3A1)
-#define SPR_UPMC6 (0x3A2)
-#define SPR_UBAMR (0x3A7)
-#define SPR_UMMCR0 (0x3A8)
-#define SPR_UPMC1 (0x3A9)
-#define SPR_UPMC2 (0x3AA)
-#define SPR_USIAR (0x3AB)
-#define SPR_UMMCR1 (0x3AC)
-#define SPR_UPMC3 (0x3AD)
-#define SPR_UPMC4 (0x3AE)
-#define SPR_USDA (0x3AF)
-#define SPR_40x_ZPR (0x3B0)
-#define SPR_BOOKE_MAS7 (0x3B0)
-#define SPR_620_PMR0 (0x3B0)
-#define SPR_MMCR2 (0x3B0)
-#define SPR_PMC5 (0x3B1)
-#define SPR_40x_PID (0x3B1)
-#define SPR_620_PMR1 (0x3B1)
-#define SPR_PMC6 (0x3B2)
-#define SPR_440_MMUCR (0x3B2)
-#define SPR_620_PMR2 (0x3B2)
-#define SPR_4xx_CCR0 (0x3B3)
-#define SPR_BOOKE_EPLC (0x3B3)
-#define SPR_620_PMR3 (0x3B3)
-#define SPR_405_IAC3 (0x3B4)
-#define SPR_BOOKE_EPSC (0x3B4)
-#define SPR_620_PMR4 (0x3B4)
-#define SPR_405_IAC4 (0x3B5)
-#define SPR_620_PMR5 (0x3B5)
-#define SPR_405_DVC1 (0x3B6)
-#define SPR_620_PMR6 (0x3B6)
-#define SPR_405_DVC2 (0x3B7)
-#define SPR_620_PMR7 (0x3B7)
-#define SPR_BAMR (0x3B7)
-#define SPR_MMCR0 (0x3B8)
-#define SPR_620_PMR8 (0x3B8)
-#define SPR_PMC1 (0x3B9)
-#define SPR_40x_SGR (0x3B9)
-#define SPR_620_PMR9 (0x3B9)
-#define SPR_PMC2 (0x3BA)
-#define SPR_40x_DCWR (0x3BA)
-#define SPR_620_PMRA (0x3BA)
-#define SPR_SIAR (0x3BB)
-#define SPR_405_SLER (0x3BB)
-#define SPR_620_PMRB (0x3BB)
-#define SPR_MMCR1 (0x3BC)
-#define SPR_405_SU0R (0x3BC)
-#define SPR_620_PMRC (0x3BC)
-#define SPR_401_SKR (0x3BC)
-#define SPR_PMC3 (0x3BD)
-#define SPR_405_DBCR1 (0x3BD)
-#define SPR_620_PMRD (0x3BD)
-#define SPR_PMC4 (0x3BE)
-#define SPR_620_PMRE (0x3BE)
-#define SPR_SDA (0x3BF)
-#define SPR_620_PMRF (0x3BF)
-#define SPR_403_VTBL (0x3CC)
-#define SPR_403_VTBU (0x3CD)
-#define SPR_DMISS (0x3D0)
-#define SPR_DCMP (0x3D1)
-#define SPR_HASH1 (0x3D2)
-#define SPR_HASH2 (0x3D3)
-#define SPR_BOOKE_ICDBDR (0x3D3)
-#define SPR_TLBMISS (0x3D4)
-#define SPR_IMISS (0x3D4)
-#define SPR_40x_ESR (0x3D4)
-#define SPR_PTEHI (0x3D5)
-#define SPR_ICMP (0x3D5)
-#define SPR_40x_DEAR (0x3D5)
-#define SPR_PTELO (0x3D6)
-#define SPR_RPA (0x3D6)
-#define SPR_40x_EVPR (0x3D6)
-#define SPR_L3PM (0x3D7)
-#define SPR_403_CDBCR (0x3D7)
-#define SPR_L3OHCR (0x3D8)
-#define SPR_TCR (0x3D8)
-#define SPR_40x_TSR (0x3D8)
-#define SPR_IBR (0x3DA)
-#define SPR_40x_TCR (0x3DA)
-#define SPR_ESASRR (0x3DB)
-#define SPR_40x_PIT (0x3DB)
-#define SPR_403_TBL (0x3DC)
-#define SPR_403_TBU (0x3DD)
-#define SPR_SEBR (0x3DE)
-#define SPR_40x_SRR2 (0x3DE)
-#define SPR_SER (0x3DF)
-#define SPR_40x_SRR3 (0x3DF)
-#define SPR_L3ITCR0 (0x3E8)
-#define SPR_L3ITCR1 (0x3E9)
-#define SPR_L3ITCR2 (0x3EA)
-#define SPR_L3ITCR3 (0x3EB)
-#define SPR_HID0 (0x3F0)
-#define SPR_40x_DBSR (0x3F0)
-#define SPR_HID1 (0x3F1)
-#define SPR_IABR (0x3F2)
-#define SPR_40x_DBCR0 (0x3F2)
-#define SPR_601_HID2 (0x3F2)
-#define SPR_E500_L1CSR0 (0x3F2)
-#define SPR_ICTRL (0x3F3)
-#define SPR_HID2 (0x3F3)
-#define SPR_E500_L1CSR1 (0x3F3)
-#define SPR_440_DBDR (0x3F3)
-#define SPR_LDSTDB (0x3F4)
-#define SPR_40x_IAC1 (0x3F4)
-#define SPR_MMUCSR0 (0x3F4)
-#define SPR_DABR (0x3F5)
+#define SPR_MQ (0x000)
+#define SPR_XER (0x001)
+#define SPR_601_VRTCU (0x004)
+#define SPR_601_VRTCL (0x005)
+#define SPR_601_UDECR (0x006)
+#define SPR_LR (0x008)
+#define SPR_CTR (0x009)
+#define SPR_DSISR (0x012)
+#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
+#define SPR_601_RTCU (0x014)
+#define SPR_601_RTCL (0x015)
+#define SPR_DECR (0x016)
+#define SPR_SDR1 (0x019)
+#define SPR_SRR0 (0x01A)
+#define SPR_SRR1 (0x01B)
+#define SPR_AMR (0x01D)
+#define SPR_BOOKE_PID (0x030)
+#define SPR_BOOKE_DECAR (0x036)
+#define SPR_BOOKE_CSRR0 (0x03A)
+#define SPR_BOOKE_CSRR1 (0x03B)
+#define SPR_BOOKE_DEAR (0x03D)
+#define SPR_BOOKE_ESR (0x03E)
+#define SPR_BOOKE_IVPR (0x03F)
+#define SPR_MPC_EIE (0x050)
+#define SPR_MPC_EID (0x051)
+#define SPR_MPC_NRI (0x052)
+#define SPR_CTRL (0x088)
+#define SPR_MPC_CMPA (0x090)
+#define SPR_MPC_CMPB (0x091)
+#define SPR_MPC_CMPC (0x092)
+#define SPR_MPC_CMPD (0x093)
+#define SPR_MPC_ECR (0x094)
+#define SPR_MPC_DER (0x095)
+#define SPR_MPC_COUNTA (0x096)
+#define SPR_MPC_COUNTB (0x097)
+#define SPR_UCTRL (0x098)
+#define SPR_MPC_CMPE (0x098)
+#define SPR_MPC_CMPF (0x099)
+#define SPR_MPC_CMPG (0x09A)
+#define SPR_MPC_CMPH (0x09B)
+#define SPR_MPC_LCTRL1 (0x09C)
+#define SPR_MPC_LCTRL2 (0x09D)
+#define SPR_MPC_ICTRL (0x09E)
+#define SPR_MPC_BAR (0x09F)
+#define SPR_VRSAVE (0x100)
+#define SPR_USPRG0 (0x100)
+#define SPR_USPRG1 (0x101)
+#define SPR_USPRG2 (0x102)
+#define SPR_USPRG3 (0x103)
+#define SPR_USPRG4 (0x104)
+#define SPR_USPRG5 (0x105)
+#define SPR_USPRG6 (0x106)
+#define SPR_USPRG7 (0x107)
+#define SPR_VTBL (0x10C)
+#define SPR_VTBU (0x10D)
+#define SPR_SPRG0 (0x110)
+#define SPR_SPRG1 (0x111)
+#define SPR_SPRG2 (0x112)
+#define SPR_SPRG3 (0x113)
+#define SPR_SPRG4 (0x114)
+#define SPR_SCOMC (0x114)
+#define SPR_SPRG5 (0x115)
+#define SPR_SCOMD (0x115)
+#define SPR_SPRG6 (0x116)
+#define SPR_SPRG7 (0x117)
+#define SPR_ASR (0x118)
+#define SPR_EAR (0x11A)
+#define SPR_TBL (0x11C)
+#define SPR_TBU (0x11D)
+#define SPR_TBU40 (0x11E)
+#define SPR_SVR (0x11E)
+#define SPR_BOOKE_PIR (0x11E)
+#define SPR_PVR (0x11F)
+#define SPR_HSPRG0 (0x130)
+#define SPR_BOOKE_DBSR (0x130)
+#define SPR_HSPRG1 (0x131)
+#define SPR_HDSISR (0x132)
+#define SPR_HDAR (0x133)
+#define SPR_BOOKE_DBCR0 (0x134)
+#define SPR_IBCR (0x135)
+#define SPR_PURR (0x135)
+#define SPR_BOOKE_DBCR1 (0x135)
+#define SPR_DBCR (0x136)
+#define SPR_HDEC (0x136)
+#define SPR_BOOKE_DBCR2 (0x136)
+#define SPR_HIOR (0x137)
+#define SPR_MBAR (0x137)
+#define SPR_RMOR (0x138)
+#define SPR_BOOKE_IAC1 (0x138)
+#define SPR_HRMOR (0x139)
+#define SPR_BOOKE_IAC2 (0x139)
+#define SPR_HSRR0 (0x13A)
+#define SPR_BOOKE_IAC3 (0x13A)
+#define SPR_HSRR1 (0x13B)
+#define SPR_BOOKE_IAC4 (0x13B)
+#define SPR_LPCR (0x13C)
+#define SPR_BOOKE_DAC1 (0x13C)
+#define SPR_LPIDR (0x13D)
+#define SPR_DABR2 (0x13D)
+#define SPR_BOOKE_DAC2 (0x13D)
+#define SPR_BOOKE_DVC1 (0x13E)
+#define SPR_BOOKE_DVC2 (0x13F)
+#define SPR_BOOKE_TSR (0x150)
+#define SPR_BOOKE_TCR (0x154)
+#define SPR_BOOKE_IVOR0 (0x190)
+#define SPR_BOOKE_IVOR1 (0x191)
+#define SPR_BOOKE_IVOR2 (0x192)
+#define SPR_BOOKE_IVOR3 (0x193)
+#define SPR_BOOKE_IVOR4 (0x194)
+#define SPR_BOOKE_IVOR5 (0x195)
+#define SPR_BOOKE_IVOR6 (0x196)
+#define SPR_BOOKE_IVOR7 (0x197)
+#define SPR_BOOKE_IVOR8 (0x198)
+#define SPR_BOOKE_IVOR9 (0x199)
+#define SPR_BOOKE_IVOR10 (0x19A)
+#define SPR_BOOKE_IVOR11 (0x19B)
+#define SPR_BOOKE_IVOR12 (0x19C)
+#define SPR_BOOKE_IVOR13 (0x19D)
+#define SPR_BOOKE_IVOR14 (0x19E)
+#define SPR_BOOKE_IVOR15 (0x19F)
+#define SPR_BOOKE_SPEFSCR (0x200)
+#define SPR_Exxx_BBEAR (0x201)
+#define SPR_Exxx_BBTAR (0x202)
+#define SPR_Exxx_L1CFG0 (0x203)
+#define SPR_Exxx_NPIDR (0x205)
+#define SPR_ATBL (0x20E)
+#define SPR_ATBU (0x20F)
+#define SPR_IBAT0U (0x210)
+#define SPR_BOOKE_IVOR32 (0x210)
+#define SPR_RCPU_MI_GRA (0x210)
+#define SPR_IBAT0L (0x211)
+#define SPR_BOOKE_IVOR33 (0x211)
+#define SPR_IBAT1U (0x212)
+#define SPR_BOOKE_IVOR34 (0x212)
+#define SPR_IBAT1L (0x213)
+#define SPR_BOOKE_IVOR35 (0x213)
+#define SPR_IBAT2U (0x214)
+#define SPR_BOOKE_IVOR36 (0x214)
+#define SPR_IBAT2L (0x215)
+#define SPR_BOOKE_IVOR37 (0x215)
+#define SPR_IBAT3U (0x216)
+#define SPR_IBAT3L (0x217)
+#define SPR_DBAT0U (0x218)
+#define SPR_RCPU_L2U_GRA (0x218)
+#define SPR_DBAT0L (0x219)
+#define SPR_DBAT1U (0x21A)
+#define SPR_DBAT1L (0x21B)
+#define SPR_DBAT2U (0x21C)
+#define SPR_DBAT2L (0x21D)
+#define SPR_DBAT3U (0x21E)
+#define SPR_DBAT3L (0x21F)
+#define SPR_IBAT4U (0x230)
+#define SPR_RPCU_BBCMCR (0x230)
+#define SPR_MPC_IC_CST (0x230)
+#define SPR_Exxx_CTXCR (0x230)
+#define SPR_IBAT4L (0x231)
+#define SPR_MPC_IC_ADR (0x231)
+#define SPR_Exxx_DBCR3 (0x231)
+#define SPR_IBAT5U (0x232)
+#define SPR_MPC_IC_DAT (0x232)
+#define SPR_Exxx_DBCNT (0x232)
+#define SPR_IBAT5L (0x233)
+#define SPR_IBAT6U (0x234)
+#define SPR_IBAT6L (0x235)
+#define SPR_IBAT7U (0x236)
+#define SPR_IBAT7L (0x237)
+#define SPR_DBAT4U (0x238)
+#define SPR_RCPU_L2U_MCR (0x238)
+#define SPR_MPC_DC_CST (0x238)
+#define SPR_Exxx_ALTCTXCR (0x238)
+#define SPR_DBAT4L (0x239)
+#define SPR_MPC_DC_ADR (0x239)
+#define SPR_DBAT5U (0x23A)
+#define SPR_BOOKE_MCSRR0 (0x23A)
+#define SPR_MPC_DC_DAT (0x23A)
+#define SPR_DBAT5L (0x23B)
+#define SPR_BOOKE_MCSRR1 (0x23B)
+#define SPR_DBAT6U (0x23C)
+#define SPR_BOOKE_MCSR (0x23C)
+#define SPR_DBAT6L (0x23D)
+#define SPR_Exxx_MCAR (0x23D)
+#define SPR_DBAT7U (0x23E)
+#define SPR_BOOKE_DSRR0 (0x23E)
+#define SPR_DBAT7L (0x23F)
+#define SPR_BOOKE_DSRR1 (0x23F)
+#define SPR_BOOKE_SPRG8 (0x25C)
+#define SPR_BOOKE_SPRG9 (0x25D)
+#define SPR_BOOKE_MAS0 (0x270)
+#define SPR_BOOKE_MAS1 (0x271)
+#define SPR_BOOKE_MAS2 (0x272)
+#define SPR_BOOKE_MAS3 (0x273)
+#define SPR_BOOKE_MAS4 (0x274)
+#define SPR_BOOKE_MAS5 (0x275)
+#define SPR_BOOKE_MAS6 (0x276)
+#define SPR_BOOKE_PID1 (0x279)
+#define SPR_BOOKE_PID2 (0x27A)
+#define SPR_MPC_DPDR (0x280)
+#define SPR_MPC_IMMR (0x288)
+#define SPR_BOOKE_TLB0CFG (0x2B0)
+#define SPR_BOOKE_TLB1CFG (0x2B1)
+#define SPR_BOOKE_TLB2CFG (0x2B2)
+#define SPR_BOOKE_TLB3CFG (0x2B3)
+#define SPR_BOOKE_EPR (0x2BE)
+#define SPR_PERF0 (0x300)
+#define SPR_RCPU_MI_RBA0 (0x300)
+#define SPR_MPC_MI_CTR (0x300)
+#define SPR_PERF1 (0x301)
+#define SPR_RCPU_MI_RBA1 (0x301)
+#define SPR_PERF2 (0x302)
+#define SPR_RCPU_MI_RBA2 (0x302)
+#define SPR_MPC_MI_AP (0x302)
+#define SPR_PERF3 (0x303)
+#define SPR_620_PMC1R (0x303)
+#define SPR_RCPU_MI_RBA3 (0x303)
+#define SPR_MPC_MI_EPN (0x303)
+#define SPR_PERF4 (0x304)
+#define SPR_620_PMC2R (0x304)
+#define SPR_PERF5 (0x305)
+#define SPR_MPC_MI_TWC (0x305)
+#define SPR_PERF6 (0x306)
+#define SPR_MPC_MI_RPN (0x306)
+#define SPR_PERF7 (0x307)
+#define SPR_PERF8 (0x308)
+#define SPR_RCPU_L2U_RBA0 (0x308)
+#define SPR_MPC_MD_CTR (0x308)
+#define SPR_PERF9 (0x309)
+#define SPR_RCPU_L2U_RBA1 (0x309)
+#define SPR_MPC_MD_CASID (0x309)
+#define SPR_PERFA (0x30A)
+#define SPR_RCPU_L2U_RBA2 (0x30A)
+#define SPR_MPC_MD_AP (0x30A)
+#define SPR_PERFB (0x30B)
+#define SPR_620_MMCR0R (0x30B)
+#define SPR_RCPU_L2U_RBA3 (0x30B)
+#define SPR_MPC_MD_EPN (0x30B)
+#define SPR_PERFC (0x30C)
+#define SPR_MPC_MD_TWB (0x30C)
+#define SPR_PERFD (0x30D)
+#define SPR_MPC_MD_TWC (0x30D)
+#define SPR_PERFE (0x30E)
+#define SPR_MPC_MD_RPN (0x30E)
+#define SPR_PERFF (0x30F)
+#define SPR_MPC_MD_TW (0x30F)
+#define SPR_UPERF0 (0x310)
+#define SPR_UPERF1 (0x311)
+#define SPR_UPERF2 (0x312)
+#define SPR_UPERF3 (0x313)
+#define SPR_620_PMC1W (0x313)
+#define SPR_UPERF4 (0x314)
+#define SPR_620_PMC2W (0x314)
+#define SPR_UPERF5 (0x315)
+#define SPR_UPERF6 (0x316)
+#define SPR_UPERF7 (0x317)
+#define SPR_UPERF8 (0x318)
+#define SPR_UPERF9 (0x319)
+#define SPR_UPERFA (0x31A)
+#define SPR_UPERFB (0x31B)
+#define SPR_620_MMCR0W (0x31B)
+#define SPR_UPERFC (0x31C)
+#define SPR_UPERFD (0x31D)
+#define SPR_UPERFE (0x31E)
+#define SPR_UPERFF (0x31F)
+#define SPR_RCPU_MI_RA0 (0x320)
+#define SPR_MPC_MI_DBCAM (0x320)
+#define SPR_RCPU_MI_RA1 (0x321)
+#define SPR_MPC_MI_DBRAM0 (0x321)
+#define SPR_RCPU_MI_RA2 (0x322)
+#define SPR_MPC_MI_DBRAM1 (0x322)
+#define SPR_RCPU_MI_RA3 (0x323)
+#define SPR_RCPU_L2U_RA0 (0x328)
+#define SPR_MPC_MD_DBCAM (0x328)
+#define SPR_RCPU_L2U_RA1 (0x329)
+#define SPR_MPC_MD_DBRAM0 (0x329)
+#define SPR_RCPU_L2U_RA2 (0x32A)
+#define SPR_MPC_MD_DBRAM1 (0x32A)
+#define SPR_RCPU_L2U_RA3 (0x32B)
+#define SPR_440_INV0 (0x370)
+#define SPR_440_INV1 (0x371)
+#define SPR_440_INV2 (0x372)
+#define SPR_440_INV3 (0x373)
+#define SPR_440_ITV0 (0x374)
+#define SPR_440_ITV1 (0x375)
+#define SPR_440_ITV2 (0x376)
+#define SPR_440_ITV3 (0x377)
+#define SPR_440_CCR1 (0x378)
+#define SPR_DCRIPR (0x37B)
+#define SPR_PPR (0x380)
+#define SPR_440_DNV0 (0x390)
+#define SPR_440_DNV1 (0x391)
+#define SPR_440_DNV2 (0x392)
+#define SPR_440_DNV3 (0x393)
+#define SPR_440_DTV0 (0x394)
+#define SPR_440_DTV1 (0x395)
+#define SPR_440_DTV2 (0x396)
+#define SPR_440_DTV3 (0x397)
+#define SPR_440_DVLIM (0x398)
+#define SPR_440_IVLIM (0x399)
+#define SPR_440_RSTCFG (0x39B)
+#define SPR_BOOKE_DCDBTRL (0x39C)
+#define SPR_BOOKE_DCDBTRH (0x39D)
+#define SPR_BOOKE_ICDBTRL (0x39E)
+#define SPR_BOOKE_ICDBTRH (0x39F)
+#define SPR_UMMCR2 (0x3A0)
+#define SPR_UPMC5 (0x3A1)
+#define SPR_UPMC6 (0x3A2)
+#define SPR_UBAMR (0x3A7)
+#define SPR_UMMCR0 (0x3A8)
+#define SPR_UPMC1 (0x3A9)
+#define SPR_UPMC2 (0x3AA)
+#define SPR_USIAR (0x3AB)
+#define SPR_UMMCR1 (0x3AC)
+#define SPR_UPMC3 (0x3AD)
+#define SPR_UPMC4 (0x3AE)
+#define SPR_USDA (0x3AF)
+#define SPR_40x_ZPR (0x3B0)
+#define SPR_BOOKE_MAS7 (0x3B0)
+#define SPR_620_PMR0 (0x3B0)
+#define SPR_MMCR2 (0x3B0)
+#define SPR_PMC5 (0x3B1)
+#define SPR_40x_PID (0x3B1)
+#define SPR_620_PMR1 (0x3B1)
+#define SPR_PMC6 (0x3B2)
+#define SPR_440_MMUCR (0x3B2)
+#define SPR_620_PMR2 (0x3B2)
+#define SPR_4xx_CCR0 (0x3B3)
+#define SPR_BOOKE_EPLC (0x3B3)
+#define SPR_620_PMR3 (0x3B3)
+#define SPR_405_IAC3 (0x3B4)
+#define SPR_BOOKE_EPSC (0x3B4)
+#define SPR_620_PMR4 (0x3B4)
+#define SPR_405_IAC4 (0x3B5)
+#define SPR_620_PMR5 (0x3B5)
+#define SPR_405_DVC1 (0x3B6)
+#define SPR_620_PMR6 (0x3B6)
+#define SPR_405_DVC2 (0x3B7)
+#define SPR_620_PMR7 (0x3B7)
+#define SPR_BAMR (0x3B7)
+#define SPR_MMCR0 (0x3B8)
+#define SPR_620_PMR8 (0x3B8)
+#define SPR_PMC1 (0x3B9)
+#define SPR_40x_SGR (0x3B9)
+#define SPR_620_PMR9 (0x3B9)
+#define SPR_PMC2 (0x3BA)
+#define SPR_40x_DCWR (0x3BA)
+#define SPR_620_PMRA (0x3BA)
+#define SPR_SIAR (0x3BB)
+#define SPR_405_SLER (0x3BB)
+#define SPR_620_PMRB (0x3BB)
+#define SPR_MMCR1 (0x3BC)
+#define SPR_405_SU0R (0x3BC)
+#define SPR_620_PMRC (0x3BC)
+#define SPR_401_SKR (0x3BC)
+#define SPR_PMC3 (0x3BD)
+#define SPR_405_DBCR1 (0x3BD)
+#define SPR_620_PMRD (0x3BD)
+#define SPR_PMC4 (0x3BE)
+#define SPR_620_PMRE (0x3BE)
+#define SPR_SDA (0x3BF)
+#define SPR_620_PMRF (0x3BF)
+#define SPR_403_VTBL (0x3CC)
+#define SPR_403_VTBU (0x3CD)
+#define SPR_DMISS (0x3D0)
+#define SPR_DCMP (0x3D1)
+#define SPR_HASH1 (0x3D2)
+#define SPR_HASH2 (0x3D3)
+#define SPR_BOOKE_ICDBDR (0x3D3)
+#define SPR_TLBMISS (0x3D4)
+#define SPR_IMISS (0x3D4)
+#define SPR_40x_ESR (0x3D4)
+#define SPR_PTEHI (0x3D5)
+#define SPR_ICMP (0x3D5)
+#define SPR_40x_DEAR (0x3D5)
+#define SPR_PTELO (0x3D6)
+#define SPR_RPA (0x3D6)
+#define SPR_40x_EVPR (0x3D6)
+#define SPR_L3PM (0x3D7)
+#define SPR_403_CDBCR (0x3D7)
+#define SPR_L3OHCR (0x3D8)
+#define SPR_TCR (0x3D8)
+#define SPR_40x_TSR (0x3D8)
+#define SPR_IBR (0x3DA)
+#define SPR_40x_TCR (0x3DA)
+#define SPR_ESASRR (0x3DB)
+#define SPR_40x_PIT (0x3DB)
+#define SPR_403_TBL (0x3DC)
+#define SPR_403_TBU (0x3DD)
+#define SPR_SEBR (0x3DE)
+#define SPR_40x_SRR2 (0x3DE)
+#define SPR_SER (0x3DF)
+#define SPR_40x_SRR3 (0x3DF)
+#define SPR_L3ITCR0 (0x3E8)
+#define SPR_L3ITCR1 (0x3E9)
+#define SPR_L3ITCR2 (0x3EA)
+#define SPR_L3ITCR3 (0x3EB)
+#define SPR_HID0 (0x3F0)
+#define SPR_40x_DBSR (0x3F0)
+#define SPR_HID1 (0x3F1)
+#define SPR_IABR (0x3F2)
+#define SPR_40x_DBCR0 (0x3F2)
+#define SPR_601_HID2 (0x3F2)
+#define SPR_Exxx_L1CSR0 (0x3F2)
+#define SPR_ICTRL (0x3F3)
+#define SPR_HID2 (0x3F3)
+#define SPR_Exxx_L1CSR1 (0x3F3)
+#define SPR_440_DBDR (0x3F3)
+#define SPR_LDSTDB (0x3F4)
+#define SPR_40x_IAC1 (0x3F4)
+#define SPR_MMUCSR0 (0x3F4)
+#define SPR_DABR (0x3F5)
#define DABR_MASK (~(target_ulong)0x7)
-#define SPR_E500_BUCSR (0x3F5)
-#define SPR_40x_IAC2 (0x3F5)
-#define SPR_601_HID5 (0x3F5)
-#define SPR_40x_DAC1 (0x3F6)
-#define SPR_MSSCR0 (0x3F6)
-#define SPR_970_HID5 (0x3F6)
-#define SPR_MSSSR0 (0x3F7)
-#define SPR_DABRX (0x3F7)
-#define SPR_40x_DAC2 (0x3F7)
-#define SPR_MMUCFG (0x3F7)
-#define SPR_LDSTCR (0x3F8)
-#define SPR_L2PMCR (0x3F8)
-#define SPR_750_HID2 (0x3F8)
-#define SPR_620_HID8 (0x3F8)
-#define SPR_L2CR (0x3F9)
-#define SPR_620_HID9 (0x3F9)
-#define SPR_L3CR (0x3FA)
-#define SPR_IABR2 (0x3FA)
-#define SPR_40x_DCCR (0x3FA)
-#define SPR_ICTC (0x3FB)
-#define SPR_40x_ICCR (0x3FB)
-#define SPR_THRM1 (0x3FC)
-#define SPR_403_PBL1 (0x3FC)
-#define SPR_SP (0x3FD)
-#define SPR_THRM2 (0x3FD)
-#define SPR_403_PBU1 (0x3FD)
-#define SPR_604_HID13 (0x3FD)
-#define SPR_LT (0x3FE)
-#define SPR_THRM3 (0x3FE)
-#define SPR_FPECR (0x3FE)
-#define SPR_403_PBL2 (0x3FE)
-#define SPR_PIR (0x3FF)
-#define SPR_403_PBU2 (0x3FF)
-#define SPR_601_HID15 (0x3FF)
-#define SPR_604_HID15 (0x3FF)
-#define SPR_E500_SVR (0x3FF)
+#define SPR_Exxx_BUCSR (0x3F5)
+#define SPR_40x_IAC2 (0x3F5)
+#define SPR_601_HID5 (0x3F5)
+#define SPR_40x_DAC1 (0x3F6)
+#define SPR_MSSCR0 (0x3F6)
+#define SPR_970_HID5 (0x3F6)
+#define SPR_MSSSR0 (0x3F7)
+#define SPR_DABRX (0x3F7)
+#define SPR_40x_DAC2 (0x3F7)
+#define SPR_MMUCFG (0x3F7)
+#define SPR_LDSTCR (0x3F8)
+#define SPR_L2PMCR (0x3F8)
+#define SPR_750_HID2 (0x3F8)
+#define SPR_620_BUSCSR (0x3F8)
+#define SPR_Exxx_L1FINV0 (0x3F8)
+#define SPR_L2CR (0x3F9)
+#define SPR_620_L2CR (0x3F9)
+#define SPR_L3CR (0x3FA)
+#define SPR_IABR2 (0x3FA)
+#define SPR_40x_DCCR (0x3FA)
+#define SPR_620_L2SR (0x3FA)
+#define SPR_ICTC (0x3FB)
+#define SPR_40x_ICCR (0x3FB)
+#define SPR_THRM1 (0x3FC)
+#define SPR_403_PBL1 (0x3FC)
+#define SPR_SP (0x3FD)
+#define SPR_THRM2 (0x3FD)
+#define SPR_403_PBU1 (0x3FD)
+#define SPR_604_HID13 (0x3FD)
+#define SPR_LT (0x3FE)
+#define SPR_THRM3 (0x3FE)
+#define SPR_RCPU_FPECR (0x3FE)
+#define SPR_403_PBL2 (0x3FE)
+#define SPR_PIR (0x3FF)
+#define SPR_403_PBU2 (0x3FF)
+#define SPR_601_HID15 (0x3FF)
+#define SPR_604_HID15 (0x3FF)
+#define SPR_E500_SVR (0x3FF)
/*****************************************************************************/
/* Memory access type :
@@ -1255,6 +1335,22 @@
PPC40x_INPUT_NB,
};
+enum {
+ /* RCPU input pins */
+ PPCRCPU_INPUT_PORESET = 0,
+ PPCRCPU_INPUT_HRESET = 1,
+ PPCRCPU_INPUT_SRESET = 2,
+ PPCRCPU_INPUT_IRQ0 = 3,
+ PPCRCPU_INPUT_IRQ1 = 4,
+ PPCRCPU_INPUT_IRQ2 = 5,
+ PPCRCPU_INPUT_IRQ3 = 6,
+ PPCRCPU_INPUT_IRQ4 = 7,
+ PPCRCPU_INPUT_IRQ5 = 8,
+ PPCRCPU_INPUT_IRQ6 = 9,
+ PPCRCPU_INPUT_IRQ7 = 10,
+ PPCRCPU_INPUT_NB,
+};
+
#if defined(TARGET_PPC64)
enum {
/* PowerPC 970 input pins */
@@ -1265,6 +1361,7 @@
PPC970_INPUT_MCP = 4,
PPC970_INPUT_INT = 5,
PPC970_INPUT_THINT = 6,
+ PPC970_INPUT_NB,
};
#endif
Modified: trunk/src/host/qemu-neo1973/target-ppc/exec.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/exec.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/exec.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -42,8 +42,8 @@
register unsigned long T1 asm(AREG2);
register unsigned long T2 asm(AREG3);
#endif
-/* We may, sometime, need 64 bits registers on 32 bits target */
-#if TARGET_GPR_BITS > HOST_LONG_BITS
+/* We may, sometime, need 64 bits registers on 32 bits targets */
+#if (HOST_LONG_BITS == 32)
/* no registers can be used */
#define T0_64 (env->t0)
#define T1_64 (env->t1)
Modified: trunk/src/host/qemu-neo1973/target-ppc/helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -706,7 +706,7 @@
int h, int rw, int type)
{
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B)
+ if (env->mmu_model & POWERPC_MMU_64)
return find_pte64(ctx, h, rw, type);
#endif
@@ -916,7 +916,7 @@
pr = msr_pr;
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
+ if (env->mmu_model & POWERPC_MMU_64) {
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "Check SLBs\n");
@@ -973,7 +973,7 @@
sdr = env->sdr1;
pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
+ if (env->mmu_model & POWERPC_MMU_64) {
htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
/* XXX: this is false for 1 TB segments */
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
@@ -1002,7 +1002,7 @@
#endif
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
+ if (env->mmu_model & POWERPC_MMU_64) {
/* Only 5 bits of the page index are used in the AVPN */
ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
} else
@@ -1357,11 +1357,12 @@
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_REAL_4xx:
+ case POWERPC_MMU_REAL:
case POWERPC_MMU_BOOKE:
ctx->prot |= PAGE_WRITE;
break;
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
/* Real address are 60 bits long */
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
@@ -1392,6 +1393,10 @@
}
}
break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
cpu_abort(env, "BookE FSL MMU model not implemented\n");
@@ -1426,6 +1431,7 @@
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
/* Try to find a BAT */
@@ -1445,12 +1451,16 @@
ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
cpu_abort(env, "BookE FSL MMU model not implemented\n");
return -1;
- case POWERPC_MMU_REAL_4xx:
- cpu_abort(env, "PowerPC 401 does not do any translation\n");
+ case POWERPC_MMU_REAL:
+ cpu_abort(env, "PowerPC in real mode do not do any translation\n");
return -1;
default:
cpu_abort(env, "Unknown or invalid MMU model\n");
@@ -1530,6 +1540,7 @@
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
env->exception_index = POWERPC_EXCP_ISI;
@@ -1537,15 +1548,19 @@
break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE MMU model is not implemented\n");
return -1;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE FSL MMU model is not implemented\n");
return -1;
- case POWERPC_MMU_REAL_4xx:
- cpu_abort(env, "PowerPC 401 should never raise any MMU "
- "exceptions\n");
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
+ case POWERPC_MMU_REAL:
+ cpu_abort(env, "PowerPC in real mode should never raise "
+ "any MMU exceptions\n");
return -1;
default:
cpu_abort(env, "Unknown or invalid MMU model\n");
@@ -1571,8 +1586,14 @@
#if defined(TARGET_PPC64)
case -5:
/* No match in segment table */
- env->exception_index = POWERPC_EXCP_ISEG;
- env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_620) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ /* XXX: this might be incorrect */
+ env->error_code = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_ISEG;
+ env->error_code = 0;
+ }
break;
#endif
}
@@ -1622,6 +1643,7 @@
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
env->exception_index = POWERPC_EXCP_DSI;
@@ -1632,17 +1654,21 @@
else
env->spr[SPR_DSISR] = 0x40000000;
break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE MMU model is not implemented\n");
return -1;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE FSL MMU model is not implemented\n");
return -1;
- case POWERPC_MMU_REAL_4xx:
- cpu_abort(env, "PowerPC 401 should never raise any MMU "
- "exceptions\n");
+ case POWERPC_MMU_REAL:
+ cpu_abort(env, "PowerPC in real mode should never raise "
+ "any MMU exceptions\n");
return -1;
default:
cpu_abort(env, "Unknown or invalid MMU model\n");
@@ -1700,9 +1726,20 @@
#if defined(TARGET_PPC64)
case -5:
/* No match in segment table */
- env->exception_index = POWERPC_EXCP_DSEG;
- env->error_code = 0;
- env->spr[SPR_DAR] = address;
+ if (env->mmu_model == POWERPC_MMU_620) {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = address;
+ /* XXX: this might be incorrect */
+ if (rw == 1)
+ env->spr[SPR_DSISR] = 0x42000000;
+ else
+ env->spr[SPR_DSISR] = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSEG;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = address;
+ }
break;
#endif
}
@@ -1921,20 +1958,25 @@
case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_all(env);
break;
- case POWERPC_MMU_REAL_4xx:
+ case POWERPC_MMU_REAL:
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE MMU model is not implemented\n");
break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif /* defined(TARGET_PPC64) */
tlb_flush(env, 1);
@@ -1961,16 +2003,20 @@
case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
break;
- case POWERPC_MMU_REAL_4xx:
+ case POWERPC_MMU_REAL:
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
+ cpu_abort(env, "BookE FSL MMU model is not implemented\n");
break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
@@ -1997,6 +2043,7 @@
tlb_flush_page(env, addr | (0xF << 28));
break;
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
@@ -2100,7 +2147,7 @@
/* GDBstub can read and write MSR... */
void ppc_store_msr (CPUPPCState *env, target_ulong value)
{
- hreg_store_msr(env, value);
+ hreg_store_msr(env, value, 0);
}
/*****************************************************************************/
@@ -2134,12 +2181,17 @@
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
-#if defined(TARGET_PPC64H)
int lpes0, lpes1, lev;
- lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
- lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
-#endif
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
+ lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
+ } else {
+ /* Those values ensure we won't enter the hypervisor mode */
+ lpes0 = 0;
+ lpes1 = 1;
+ }
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
@@ -2190,9 +2242,10 @@
}
new_msr &= ~((target_ulong)1 << MSR_RI);
new_msr &= ~((target_ulong)1 << MSR_ME);
-#if defined(TARGET_PPC64H)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
/* XXX: should also have something loaded in DAR / DSISR */
switch (excp_model) {
case POWERPC_EXCP_40x:
@@ -2217,10 +2270,8 @@
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
#if defined (DEBUG_EXCEPTIONS)
@@ -2230,25 +2281,19 @@
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
msr |= env->error_code;
goto store_next;
case POWERPC_EXCP_EXTERNAL: /* External input */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes0 == 1)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
/* XXX: this is false */
/* Get rS/rD and rA from faulting opcode */
env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
@@ -2267,10 +2312,8 @@
return;
}
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00100000;
if (msr_fe0 == msr_fe1)
goto store_next;
@@ -2284,26 +2327,20 @@
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00080000;
break;
case POWERPC_EXCP_PRIV:
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00040000;
break;
case POWERPC_EXCP_TRAP:
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00020000;
break;
default:
@@ -2315,10 +2352,8 @@
goto store_current;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_current;
case POWERPC_EXCP_SYSCALL: /* System call exception */
/* NOTE: this is a temporary hack to support graphics OSI
@@ -2336,21 +2371,17 @@
dump_syscall(env);
}
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
lev = env->error_code;
if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
new_msr &= ~((target_ulong)1 << MSR_RI);
goto store_current;
case POWERPC_EXCP_DECR: /* Decrementer exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
/* FIT on 4xx */
@@ -2434,68 +2465,55 @@
goto store_next;
case POWERPC_EXCP_RESET: /* System reset exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
goto store_next;
-#if defined(TARGET_PPC64)
case POWERPC_EXCP_DSEG: /* Data segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
-#endif /* defined(TARGET_PPC64) */
-#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)1 << MSR_HV;
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
-#endif
case POWERPC_EXCP_TRACE: /* Trace exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
-#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)1 << MSR_HV;
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)1 << MSR_HV;
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)1 << MSR_HV;
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)1 << MSR_HV;
+ new_msr |= (target_ulong)MSR_HVB;
goto store_next;
-#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
#if defined (DEBUG_EXCEPTIONS)
@@ -2519,10 +2537,8 @@
goto store_next;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
- if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ if (lpes1 == 0) /* XXX: check this */
+ new_msr |= (target_ulong)MSR_HVB;
switch (excp_model) {
case POWERPC_EXCP_602:
case POWERPC_EXCP_603:
@@ -2540,10 +2556,8 @@
break;
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
- if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ if (lpes1 == 0) /* XXX: check this */
+ new_msr |= (target_ulong)MSR_HVB;
switch (excp_model) {
case POWERPC_EXCP_602:
case POWERPC_EXCP_603:
@@ -2561,10 +2575,8 @@
break;
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
- if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ if (lpes1 == 0) /* XXX: check this */
+ new_msr |= (target_ulong)MSR_HVB;
switch (excp_model) {
case POWERPC_EXCP_602:
case POWERPC_EXCP_603:
@@ -2648,6 +2660,10 @@
cpu_abort(env, "Floating point assist exception "
"is not implemented yet !\n");
goto store_next;
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ /* XXX: TODO */
+ cpu_abort(env, "DABR exception is not implemented yet !\n");
+ goto store_next;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
/* XXX: TODO */
cpu_abort(env, "IABR exception is not implemented yet !\n");
@@ -2663,10 +2679,8 @@
goto store_next;
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
if (lpes1 == 0)
- new_msr |= (target_ulong)1 << MSR_HV;
-#endif
+ new_msr |= (target_ulong)MSR_HVB;
/* XXX: TODO */
cpu_abort(env,
"Performance counter exception is not implemented yet !\n");
@@ -2685,6 +2699,16 @@
cpu_abort(env,
"970 maintenance exception is not implemented yet !\n");
goto store_next;
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ /* XXX: TODO */
+ cpu_abort(env, "Maskable external exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ /* XXX: TODO */
+ cpu_abort(env, "Non maskable external exception "
+ "is not implemented yet !\n");
+ goto store_next;
default:
excp_invalid:
cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -2753,8 +2777,7 @@
/* XXX: we don't use hreg_store_msr here as already have treated
* any special case that could occur. Just store MSR and update hflags
*/
- env->msr = new_msr;
- env->hflags_nmsr = 0x00000000;
+ env->msr = new_msr & env->msr_mask;
hreg_compute_hflags(env);
env->nip = vector;
/* Reset exception state */
@@ -2769,9 +2792,7 @@
void ppc_hw_interrupt (CPUPPCState *env)
{
-#if defined(TARGET_PPC64H)
int hdice;
-#endif
#if 0
if (loglevel & CPU_LOG_INT) {
@@ -2800,8 +2821,12 @@
return;
}
#endif
-#if defined(TARGET_PPC64H)
- hdice = env->spr[SPR_LPCR] & 1;
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ hdice = env->spr[SPR_LPCR] & 1;
+ } else {
+ hdice = 0;
+ }
if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
/* Hypervisor decrementer exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
@@ -2810,7 +2835,6 @@
return;
}
}
-#endif
if (msr_ce != 0) {
/* External critical interrupt */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
@@ -2919,9 +2943,10 @@
env = opaque;
msr = (target_ulong)0;
-#if defined(TARGET_PPC64)
- msr |= (target_ulong)0 << MSR_HV; /* Should be 1... */
-#endif
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ msr |= (target_ulong)MSR_HVB;
+ }
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
msr |= (target_ulong)1 << MSR_EP;
@@ -2935,7 +2960,7 @@
msr |= (target_ulong)1 << MSR_PR;
#else
env->nip = env->hreset_vector | env->excp_prefix;
- if (env->mmu_model != POWERPC_MMU_REAL_4xx)
+ if (env->mmu_model != POWERPC_MMU_REAL)
ppc_tlb_invalidate_all(env);
#endif
env->msr = msr;
Modified: trunk/src/host/qemu-neo1973/target-ppc/helper_regs.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/helper_regs.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/helper_regs.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -60,13 +60,12 @@
static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
{
-#if defined (TARGET_PPC64H)
/* Precompute MMU index */
- if (msr_pr == 0 && msr_hv != 0)
+ if (msr_pr == 0 && msr_hv != 0) {
env->mmu_idx = 2;
- else
-#endif
+ } else {
env->mmu_idx = 1 - msr_pr;
+ }
}
static always_inline void hreg_compute_hflags (CPUPPCState *env)
@@ -77,25 +76,26 @@
hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
(1 << MSR_LE);
-#if defined (TARGET_PPC64)
- hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF);
-#if defined (TARGET_PPC64H)
- hflags_mask |= 1ULL << MSR_HV;
-#endif
-#endif
+ hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
/* Merge with hflags coming from other registers */
env->hflags |= env->hflags_nmsr;
}
-static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value)
+static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value,
+ int alter_hv)
{
int excp;
excp = 0;
value &= env->msr_mask;
#if !defined (CONFIG_USER_ONLY)
+ if (!alter_hv) {
+ /* mtmsr cannot alter the hypervisor state */
+ value &= ~MSR_HVB;
+ value |= env->msr & MSR_HVB;
+ }
if (((value >> MSR_IR) & 1) != msr_ir ||
((value >> MSR_DR) & 1) != msr_dr) {
/* Flush all tlb when changing translation mode */
Modified: trunk/src/host/qemu-neo1973/target-ppc/op.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/op.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/op.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1987,12 +1987,10 @@
#define MEMSUFFIX _kernel
#include "op_helper.h"
#include "op_mem.h"
-#if defined(TARGET_PPC64H)
#define MEMSUFFIX _hypv
#include "op_helper.h"
#include "op_mem.h"
#endif
-#endif
/* Special op to check and maybe clear reservation */
void OPPROTO op_check_reservation (void)
@@ -2031,9 +2029,7 @@
do_rfid();
RETURN();
}
-#endif
-#if defined(TARGET_PPC64H)
void OPPROTO op_hrfid (void)
{
do_hrfid();
Modified: trunk/src/host/qemu-neo1973/target-ppc/op_helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/op_helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/op_helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -33,12 +33,10 @@
#define MEMSUFFIX _kernel
#include "op_helper.h"
#include "op_helper_mem.h"
-#if defined(TARGET_PPC64H)
#define MEMSUFFIX _hypv
#include "op_helper.h"
#include "op_helper_mem.h"
#endif
-#endif
//#define DEBUG_OP
//#define DEBUG_EXCEPTIONS
@@ -1427,7 +1425,7 @@
void do_store_msr (void)
{
- T0 = hreg_store_msr(env, T0);
+ T0 = hreg_store_msr(env, T0, 0);
if (T0 != 0) {
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
do_raise_exception(T0);
@@ -1453,7 +1451,7 @@
#endif
/* XXX: beware: this is false if VLE is supported */
env->nip = nip & ~((target_ulong)0x00000003);
- hreg_store_msr(env, msr);
+ hreg_store_msr(env, msr, 1);
#if defined (DEBUG_OP)
cpu_dump_rfi(env->nip, env->msr);
#endif
@@ -1475,8 +1473,7 @@
__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
~((target_ulong)0xFFFF0000), 0);
}
-#endif
-#if defined(TARGET_PPC64H)
+
void do_hrfid (void)
{
__do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
Modified: trunk/src/host/qemu-neo1973/target-ppc/op_helper.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/op_helper.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/op_helper.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -146,8 +146,6 @@
void do_rfi (void);
#if defined(TARGET_PPC64)
void do_rfid (void);
-#endif
-#if defined(TARGET_PPC64H)
void do_hrfid (void);
#endif
void do_load_6xx_tlb (int is_code);
Modified: trunk/src/host/qemu-neo1973/target-ppc/op_mem.h
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/op_mem.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/op_mem.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -414,7 +414,7 @@
#define WORD0 1
#define WORD1 0
#endif
-static always_inline void glue(stfiwx, MEMSUFFIX) (target_ulong EA, double d)
+static always_inline void glue(stfiw, MEMSUFFIX) (target_ulong EA, double d)
{
union {
double d;
@@ -430,11 +430,11 @@
PPC_STF_OP(fd, stfq);
PPC_STF_OP(fs, stfs);
-PPC_STF_OP(fiwx, stfiwx);
+PPC_STF_OP(fiw, stfiw);
#if defined(TARGET_PPC64)
PPC_STF_OP_64(fd, stfq);
PPC_STF_OP_64(fs, stfs);
-PPC_STF_OP_64(fiwx, stfiwx);
+PPC_STF_OP_64(fiw, stfiw);
#endif
static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
@@ -471,7 +471,7 @@
glue(stfl, MEMSUFFIX)(EA, u.f);
}
-static always_inline void glue(stfiwxr, MEMSUFFIX) (target_ulong EA, double d)
+static always_inline void glue(stfiwr, MEMSUFFIX) (target_ulong EA, double d)
{
union {
double d;
@@ -489,11 +489,11 @@
PPC_STF_OP(fd_le, stfqr);
PPC_STF_OP(fs_le, stfsr);
-PPC_STF_OP(fiwx_le, stfiwxr);
+PPC_STF_OP(fiw_le, stfiwr);
#if defined(TARGET_PPC64)
PPC_STF_OP_64(fd_le, stfqr);
PPC_STF_OP_64(fs_le, stfsr);
-PPC_STF_OP_64(fiwx_le, stfiwxr);
+PPC_STF_OP_64(fiw_le, stfiwr);
#endif
/*** Floating-point load ***/
Modified: trunk/src/host/qemu-neo1973/target-ppc/translate.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/translate.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/translate.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -426,111 +426,137 @@
/*****************************************************************************/
/* PowerPC Instructions types definitions */
enum {
- PPC_NONE = 0x0000000000000000ULL,
+ PPC_NONE = 0x0000000000000000ULL,
/* PowerPC base instructions set */
- PPC_INSNS_BASE = 0x0000000000000001ULL,
- /* integer operations instructions */
+ PPC_INSNS_BASE = 0x0000000000000001ULL,
+ /* integer operations instructions */
#define PPC_INTEGER PPC_INSNS_BASE
- /* flow control instructions */
+ /* flow control instructions */
#define PPC_FLOW PPC_INSNS_BASE
- /* virtual memory instructions */
+ /* virtual memory instructions */
#define PPC_MEM PPC_INSNS_BASE
- /* ld/st with reservation instructions */
+ /* ld/st with reservation instructions */
#define PPC_RES PPC_INSNS_BASE
- /* cache control instructions */
-#define PPC_CACHE PPC_INSNS_BASE
- /* spr/msr access instructions */
+ /* spr/msr access instructions */
#define PPC_MISC PPC_INSNS_BASE
- /* Optional floating point instructions */
- PPC_FLOAT = 0x0000000000000002ULL,
- PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
- PPC_FLOAT_FRES = 0x0000000000000008ULL,
- PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
- PPC_FLOAT_FSEL = 0x0000000000000020ULL,
- PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
- /* external control instructions */
- PPC_EXTERN = 0x0000000000000080ULL,
- /* segment register access instructions */
- PPC_SEGMENT = 0x0000000000000100ULL,
- /* Optional cache control instruction */
- PPC_CACHE_DCBA = 0x0000000000000200ULL,
+ /* Deprecated instruction sets */
+ /* Original POWER instruction set */
+ PPC_POWER = 0x0000000000000002ULL,
+ /* POWER2 instruction set extension */
+ PPC_POWER2 = 0x0000000000000004ULL,
+ /* Power RTC support */
+ PPC_POWER_RTC = 0x0000000000000008ULL,
+ /* Power-to-PowerPC bridge (601) */
+ PPC_POWER_BR = 0x0000000000000010ULL,
+ /* 64 bits PowerPC instruction set */
+ PPC_64B = 0x0000000000000020ULL,
+ /* New 64 bits extensions (PowerPC 2.0x) */
+ PPC_64BX = 0x0000000000000040ULL,
+ /* 64 bits hypervisor extensions */
+ PPC_64H = 0x0000000000000080ULL,
+ /* New wait instruction (PowerPC 2.0x) */
+ PPC_WAIT = 0x0000000000000100ULL,
+ /* Time base mftb instruction */
+ PPC_MFTB = 0x0000000000000200ULL,
+
+ /* Fixed-point unit extensions */
+ /* PowerPC 602 specific */
+ PPC_602_SPEC = 0x0000000000000400ULL,
+ /* isel instruction */
+ PPC_ISEL = 0x0000000000000800ULL,
+ /* popcntb instruction */
+ PPC_POPCNTB = 0x0000000000001000ULL,
+ /* string load / store */
+ PPC_STRING = 0x0000000000002000ULL,
+
+ /* Floating-point unit extensions */
+ /* Optional floating point instructions */
+ PPC_FLOAT = 0x0000000000010000ULL,
+ /* New floating-point extensions (PowerPC 2.0x) */
+ PPC_FLOAT_EXT = 0x0000000000020000ULL,
+ PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
+ PPC_FLOAT_FRES = 0x0000000000080000ULL,
+ PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
+ PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
+ PPC_FLOAT_FSEL = 0x0000000000400000ULL,
+ PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
+
+ /* Vector/SIMD extensions */
+ /* Altivec support */
+ PPC_ALTIVEC = 0x0000000001000000ULL,
+ /* PowerPC 2.03 SPE extension */
+ PPC_SPE = 0x0000000002000000ULL,
+ /* PowerPC 2.03 SPE floating-point extension */
+ PPC_SPEFPU = 0x0000000004000000ULL,
+
/* Optional memory control instructions */
- PPC_MEM_TLBIA = 0x0000000000000400ULL,
- PPC_MEM_TLBIE = 0x0000000000000800ULL,
- PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
- /* eieio & sync */
- PPC_MEM_SYNC = 0x0000000000002000ULL,
- /* PowerPC 6xx TLB management instructions */
- PPC_6xx_TLB = 0x0000000000004000ULL,
- /* Altivec support */
- PPC_ALTIVEC = 0x0000000000008000ULL,
- /* Time base mftb instruction */
- PPC_MFTB = 0x0000000000010000ULL,
+ PPC_MEM_TLBIA = 0x0000000010000000ULL,
+ PPC_MEM_TLBIE = 0x0000000020000000ULL,
+ PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
+ /* sync instruction */
+ PPC_MEM_SYNC = 0x0000000080000000ULL,
+ /* eieio instruction */
+ PPC_MEM_EIEIO = 0x0000000100000000ULL,
+
+ /* Cache control instructions */
+ PPC_CACHE = 0x0000000200000000ULL,
+ /* icbi instruction */
+ PPC_CACHE_ICBI = 0x0000000400000000ULL,
+ /* dcbz instruction with fixed cache line size */
+ PPC_CACHE_DCBZ = 0x0000000800000000ULL,
+ /* dcbz instruction with tunable cache line size */
+ PPC_CACHE_DCBZT = 0x0000001000000000ULL,
+ /* dcba instruction */
+ PPC_CACHE_DCBA = 0x0000002000000000ULL,
+ /* Freescale cache locking instructions */
+ PPC_CACHE_LOCK = 0x0000004000000000ULL,
+
+ /* MMU related extensions */
+ /* external control instructions */
+ PPC_EXTERN = 0x0000010000000000ULL,
+ /* segment register access instructions */
+ PPC_SEGMENT = 0x0000020000000000ULL,
+ /* PowerPC 6xx TLB management instructions */
+ PPC_6xx_TLB = 0x0000040000000000ULL,
+ /* PowerPC 74xx TLB management instructions */
+ PPC_74xx_TLB = 0x0000080000000000ULL,
+ /* PowerPC 40x TLB management instructions */
+ PPC_40x_TLB = 0x0000100000000000ULL,
+ /* segment register access instructions for PowerPC 64 "bridge" */
+ PPC_SEGMENT_64B = 0x0000200000000000ULL,
+ /* SLB management */
+ PPC_SLBI = 0x0000400000000000ULL,
+
/* Embedded PowerPC dedicated instructions */
- PPC_EMB_COMMON = 0x0000000000020000ULL,
+ PPC_WRTEE = 0x0001000000000000ULL,
/* PowerPC 40x exception model */
- PPC_40x_EXCP = 0x0000000000040000ULL,
- /* PowerPC 40x TLB management instructions */
- PPC_40x_TLB = 0x0000000000080000ULL,
+ PPC_40x_EXCP = 0x0002000000000000ULL,
/* PowerPC 405 Mac instructions */
- PPC_405_MAC = 0x0000000000100000ULL,
+ PPC_405_MAC = 0x0004000000000000ULL,
/* PowerPC 440 specific instructions */
- PPC_440_SPEC = 0x0000000000200000ULL,
- /* Power-to-PowerPC bridge (601) */
- PPC_POWER_BR = 0x0000000000400000ULL,
- /* PowerPC 602 specific */
- PPC_602_SPEC = 0x0000000000800000ULL,
- /* Deprecated instructions */
- /* Original POWER instruction set */
- PPC_POWER = 0x0000000001000000ULL,
- /* POWER2 instruction set extension */
- PPC_POWER2 = 0x0000000002000000ULL,
- /* Power RTC support */
- PPC_POWER_RTC = 0x0000000004000000ULL,
- /* 64 bits PowerPC instruction set */
- PPC_64B = 0x0000000008000000ULL,
- /* 64 bits hypervisor extensions */
- PPC_64H = 0x0000000010000000ULL,
- /* segment register access instructions for PowerPC 64 "bridge" */
- PPC_SEGMENT_64B = 0x0000000020000000ULL,
+ PPC_440_SPEC = 0x0008000000000000ULL,
/* BookE (embedded) PowerPC specification */
- PPC_BOOKE = 0x0000000040000000ULL,
- /* eieio */
- PPC_MEM_EIEIO = 0x0000000080000000ULL,
- /* e500 vector instructions */
- PPC_E500_VECTOR = 0x0000000100000000ULL,
+ PPC_BOOKE = 0x0010000000000000ULL,
+ /* mfapidi instruction */
+ PPC_MFAPIDI = 0x0020000000000000ULL,
+ /* tlbiva instruction */
+ PPC_TLBIVA = 0x0040000000000000ULL,
+ /* tlbivax instruction */
+ PPC_TLBIVAX = 0x0080000000000000ULL,
/* PowerPC 4xx dedicated instructions */
- PPC_4xx_COMMON = 0x0000000200000000ULL,
- /* PowerPC 2.03 specification extensions */
- PPC_203 = 0x0000000400000000ULL,
- /* PowerPC 2.03 SPE extension */
- PPC_SPE = 0x0000000800000000ULL,
- /* PowerPC 2.03 SPE floating-point extension */
- PPC_SPEFPU = 0x0000001000000000ULL,
- /* SLB management */
- PPC_SLBI = 0x0000002000000000ULL,
+ PPC_4xx_COMMON = 0x0100000000000000ULL,
/* PowerPC 40x ibct instructions */
- PPC_40x_ICBT = 0x0000004000000000ULL,
- /* PowerPC 74xx TLB management instructions */
- PPC_74xx_TLB = 0x0000008000000000ULL,
- /* More BookE (embedded) instructions... */
- PPC_BOOKE_EXT = 0x0000010000000000ULL,
+ PPC_40x_ICBT = 0x0200000000000000ULL,
/* rfmci is not implemented in all BookE PowerPC */
- PPC_RFMCI = 0x0000020000000000ULL,
+ PPC_RFMCI = 0x0400000000000000ULL,
+ /* rfdi instruction */
+ PPC_RFDI = 0x0800000000000000ULL,
+ /* DCR accesses */
+ PPC_DCR = 0x1000000000000000ULL,
+ /* DCR extended accesse */
+ PPC_DCRX = 0x2000000000000000ULL,
/* user-mode DCR access, implemented in PowerPC 460 */
- PPC_DCRUX = 0x0000040000000000ULL,
- /* New floating-point extensions (PowerPC 2.0x) */
- PPC_FLOAT_EXT = 0x0000080000000000ULL,
- /* New wait instruction (PowerPC 2.0x) */
- PPC_WAIT = 0x0000100000000000ULL,
- /* New 64 bits extensions (PowerPC 2.0x) */
- PPC_64BX = 0x0000200000000000ULL,
- /* dcbz instruction with fixed cache line size */
- PPC_CACHE_DCBZ = 0x0000400000000000ULL,
- /* dcbz instruction with tunable cache line size */
- PPC_CACHE_DCBZT = 0x0000800000000000ULL,
- /* frsqrtes extension */
- PPC_FLOAT_FRSQRTES = 0x0001000000000000ULL,
+ PPC_DCRUX = 0x4000000000000000ULL,
};
/*****************************************************************************/
@@ -1107,7 +1133,7 @@
}
/* isel (PowerPC 2.03 specification) */
-GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
+GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_ISEL)
{
uint32_t bi = rC(ctx->opcode);
uint32_t mask;
@@ -1238,7 +1264,6 @@
gen_op_store_pri(6);
}
break;
-#if defined(TARGET_PPC64H)
case 7:
if (ctx->supervisor > 1) {
/* Set process priority to very high */
@@ -1246,7 +1271,6 @@
}
break;
#endif
-#endif
default:
/* nop */
break;
@@ -1332,7 +1356,7 @@
}
/* popcntb : PowerPC 2.03 specification */
-GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
+GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
{
gen_op_load_gpr_T0(rS(ctx->opcode));
#if defined(TARGET_PPC64)
@@ -1594,17 +1618,15 @@
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
{
uint64_t mask;
- uint32_t sh, mb;
+ uint32_t sh, mb, me;
sh = SH(ctx->opcode) | (shn << 5);
mb = MB(ctx->opcode) | (mbn << 5);
+ me = 63 - sh;
if (likely(sh == 0)) {
if (likely(mb == 0)) {
gen_op_load_gpr_T0(rS(ctx->opcode));
goto do_store;
- } else if (likely(mb == 63)) {
- gen_op_load_gpr_T0(rA(ctx->opcode));
- goto do_store;
}
gen_op_load_gpr_T0(rS(ctx->opcode));
gen_op_load_gpr_T1(rA(ctx->opcode));
@@ -1614,7 +1636,7 @@
gen_op_load_gpr_T1(rA(ctx->opcode));
gen_op_rotli64_T0(sh);
do_mask:
- mask = MASK(mb, 63 - sh);
+ mask = MASK(mb, me);
gen_andi_T0_64(ctx, mask);
gen_andi_T1_64(ctx, ~mask);
gen_op_or();
@@ -1805,7 +1827,7 @@
gen_op_frsqrte();
gen_op_frsp();
}
-GEN_FLOAT_BS(rsqrtes, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES);
+GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
/* fsel */
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
@@ -2093,136 +2115,64 @@
#endif
}
-/*** Integer load ***/
-#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
+#if defined(TARGET_PPC64)
+#define _GEN_MEM_FUNCS(name, mode) \
+ &gen_op_##name##_##mode, \
+ &gen_op_##name##_le_##mode, \
+ &gen_op_##name##_64_##mode, \
+ &gen_op_##name##_le_64_##mode
+#else
+#define _GEN_MEM_FUNCS(name, mode) \
+ &gen_op_##name##_##mode, \
+ &gen_op_##name##_le_##mode
+#endif
#if defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
-/* User mode only - 64 bits */
-#define OP_LD_TABLE(width) \
-static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_raw, \
- &gen_op_l##width##_le_raw, \
- &gen_op_l##width##_64_raw, \
- &gen_op_l##width##_le_64_raw, \
-};
-#define OP_ST_TABLE(width) \
-static GenOpFunc *gen_op_st##width[] = { \
- &gen_op_st##width##_raw, \
- &gen_op_st##width##_le_raw, \
- &gen_op_st##width##_64_raw, \
- &gen_op_st##width##_le_64_raw, \
-};
-/* Byte access routine are endian safe */
-#define gen_op_stb_le_64_raw gen_op_stb_64_raw
-#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
+#define NB_MEM_FUNCS 4
#else
-/* User mode only - 32 bits */
-#define OP_LD_TABLE(width) \
-static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_raw, \
- &gen_op_l##width##_le_raw, \
-};
-#define OP_ST_TABLE(width) \
-static GenOpFunc *gen_op_st##width[] = { \
- &gen_op_st##width##_raw, \
- &gen_op_st##width##_le_raw, \
-};
+#define NB_MEM_FUNCS 2
#endif
-/* Byte access routine are endian safe */
-#define gen_op_stb_le_raw gen_op_stb_raw
-#define gen_op_lbz_le_raw gen_op_lbz_raw
+#define GEN_MEM_FUNCS(name) \
+ _GEN_MEM_FUNCS(name, raw)
#else
#if defined(TARGET_PPC64)
-#if defined(TARGET_PPC64H)
-/* Full system - 64 bits with hypervisor mode */
-#define OP_LD_TABLE(width) \
-static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_user, \
- &gen_op_l##width##_le_user, \
- &gen_op_l##width##_64_user, \
- &gen_op_l##width##_le_64_user, \
- &gen_op_l##width##_kernel, \
- &gen_op_l##width##_le_kernel, \
- &gen_op_l##width##_64_kernel, \
- &gen_op_l##width##_le_64_kernel, \
- &gen_op_l##width##_hypv, \
- &gen_op_l##width##_le_hypv, \
- &gen_op_l##width##_64_hypv, \
- &gen_op_l##width##_le_64_hypv, \
-};
-#define OP_ST_TABLE(width) \
-static GenOpFunc *gen_op_st##width[] = { \
- &gen_op_st##width##_user, \
- &gen_op_st##width##_le_user, \
- &gen_op_st##width##_64_user, \
- &gen_op_st##width##_le_64_user, \
- &gen_op_st##width##_kernel, \
- &gen_op_st##width##_le_kernel, \
- &gen_op_st##width##_64_kernel, \
- &gen_op_st##width##_le_64_kernel, \
- &gen_op_st##width##_hypv, \
- &gen_op_st##width##_le_hypv, \
- &gen_op_st##width##_64_hypv, \
- &gen_op_st##width##_le_64_hypv, \
-};
-/* Byte access routine are endian safe */
-#define gen_op_stb_le_hypv gen_op_stb_64_hypv
-#define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
-#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
-#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
+#define NB_MEM_FUNCS 12
#else
-/* Full system - 64 bits */
-#define OP_LD_TABLE(width) \
-static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_user, \
- &gen_op_l##width##_le_user, \
- &gen_op_l##width##_64_user, \
- &gen_op_l##width##_le_64_user, \
- &gen_op_l##width##_kernel, \
- &gen_op_l##width##_le_kernel, \
- &gen_op_l##width##_64_kernel, \
- &gen_op_l##width##_le_64_kernel, \
-};
-#define OP_ST_TABLE(width) \
-static GenOpFunc *gen_op_st##width[] = { \
- &gen_op_st##width##_user, \
- &gen_op_st##width##_le_user, \
- &gen_op_st##width##_64_user, \
- &gen_op_st##width##_le_64_user, \
- &gen_op_st##width##_kernel, \
- &gen_op_st##width##_le_kernel, \
- &gen_op_st##width##_64_kernel, \
- &gen_op_st##width##_le_64_kernel, \
-};
+#define NB_MEM_FUNCS 6
#endif
+#define GEN_MEM_FUNCS(name) \
+ _GEN_MEM_FUNCS(name, user), \
+ _GEN_MEM_FUNCS(name, kernel), \
+ _GEN_MEM_FUNCS(name, hypv)
+#endif
+
+/*** Integer load ***/
+#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
/* Byte access routine are endian safe */
-#define gen_op_stb_le_64_user gen_op_stb_64_user
+#define gen_op_lbz_le_raw gen_op_lbz_raw
+#define gen_op_lbz_le_user gen_op_lbz_user
+#define gen_op_lbz_le_kernel gen_op_lbz_kernel
+#define gen_op_lbz_le_hypv gen_op_lbz_hypv
+#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
#define gen_op_lbz_le_64_user gen_op_lbz_64_user
-#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
-#else
-/* Full system - 32 bits */
+#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
+#define gen_op_stb_le_raw gen_op_stb_raw
+#define gen_op_stb_le_user gen_op_stb_user
+#define gen_op_stb_le_kernel gen_op_stb_kernel
+#define gen_op_stb_le_hypv gen_op_stb_hypv
+#define gen_op_stb_le_64_raw gen_op_stb_64_raw
+#define gen_op_stb_le_64_user gen_op_stb_64_user
+#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
+#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
#define OP_LD_TABLE(width) \
-static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_user, \
- &gen_op_l##width##_le_user, \
- &gen_op_l##width##_kernel, \
- &gen_op_l##width##_le_kernel, \
+static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(l##width), \
};
#define OP_ST_TABLE(width) \
-static GenOpFunc *gen_op_st##width[] = { \
- &gen_op_st##width##_user, \
- &gen_op_st##width##_le_user, \
- &gen_op_st##width##_kernel, \
- &gen_op_st##width##_le_kernel, \
+static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(st##width), \
};
-#endif
-/* Byte access routine are endian safe */
-#define gen_op_stb_le_user gen_op_stb_user
-#define gen_op_lbz_le_user gen_op_lbz_user
-#define gen_op_stb_le_kernel gen_op_stb_kernel
-#define gen_op_lbz_le_kernel gen_op_lbz_kernel
-#endif
#define GEN_LD(width, opc, type) \
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
@@ -2477,75 +2427,12 @@
/*** Integer load and store multiple ***/
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc1 *gen_op_lmw[] = {
- &gen_op_lmw_raw,
- &gen_op_lmw_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_lmw_64_raw,
- &gen_op_lmw_le_64_raw,
-#endif
+static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(lmw),
};
-static GenOpFunc1 *gen_op_stmw[] = {
- &gen_op_stmw_raw,
- &gen_op_stmw_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_stmw_64_raw,
- &gen_op_stmw_le_64_raw,
-#endif
+static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(stmw),
};
-#else
-#if defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-static GenOpFunc1 *gen_op_lmw[] = {
- &gen_op_lmw_user,
- &gen_op_lmw_le_user,
- &gen_op_lmw_64_user,
- &gen_op_lmw_le_64_user,
- &gen_op_lmw_kernel,
- &gen_op_lmw_le_kernel,
- &gen_op_lmw_64_kernel,
- &gen_op_lmw_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_lmw_hypv,
- &gen_op_lmw_le_hypv,
- &gen_op_lmw_64_hypv,
- &gen_op_lmw_le_64_hypv,
-#endif
-};
-static GenOpFunc1 *gen_op_stmw[] = {
- &gen_op_stmw_user,
- &gen_op_stmw_le_user,
- &gen_op_stmw_64_user,
- &gen_op_stmw_le_64_user,
- &gen_op_stmw_kernel,
- &gen_op_stmw_le_kernel,
- &gen_op_stmw_64_kernel,
- &gen_op_stmw_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_stmw_hypv,
- &gen_op_stmw_le_hypv,
- &gen_op_stmw_64_hypv,
- &gen_op_stmw_le_64_hypv,
-#endif
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc1 *gen_op_lmw[] = {
- &gen_op_lmw_user,
- &gen_op_lmw_le_user,
- &gen_op_lmw_kernel,
- &gen_op_lmw_le_kernel,
-};
-static GenOpFunc1 *gen_op_stmw[] = {
- &gen_op_stmw_user,
- &gen_op_stmw_le_user,
- &gen_op_stmw_kernel,
- &gen_op_stmw_le_kernel,
-};
-#endif
-#endif
/* lmw */
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
@@ -2568,105 +2455,15 @@
/*** Integer load and store strings ***/
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc1 *gen_op_lswi[] = {
- &gen_op_lswi_raw,
- &gen_op_lswi_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_lswi_64_raw,
- &gen_op_lswi_le_64_raw,
-#endif
+static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(lswi),
};
-static GenOpFunc3 *gen_op_lswx[] = {
- &gen_op_lswx_raw,
- &gen_op_lswx_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_lswx_64_raw,
- &gen_op_lswx_le_64_raw,
-#endif
+static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(lswx),
};
-static GenOpFunc1 *gen_op_stsw[] = {
- &gen_op_stsw_raw,
- &gen_op_stsw_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_stsw_64_raw,
- &gen_op_stsw_le_64_raw,
-#endif
+static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(stsw),
};
-#else
-#if defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-static GenOpFunc1 *gen_op_lswi[] = {
- &gen_op_lswi_user,
- &gen_op_lswi_le_user,
- &gen_op_lswi_64_user,
- &gen_op_lswi_le_64_user,
- &gen_op_lswi_kernel,
- &gen_op_lswi_le_kernel,
- &gen_op_lswi_64_kernel,
- &gen_op_lswi_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_lswi_hypv,
- &gen_op_lswi_le_hypv,
- &gen_op_lswi_64_hypv,
- &gen_op_lswi_le_64_hypv,
-#endif
-};
-static GenOpFunc3 *gen_op_lswx[] = {
- &gen_op_lswx_user,
- &gen_op_lswx_le_user,
- &gen_op_lswx_64_user,
- &gen_op_lswx_le_64_user,
- &gen_op_lswx_kernel,
- &gen_op_lswx_le_kernel,
- &gen_op_lswx_64_kernel,
- &gen_op_lswx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_lswx_hypv,
- &gen_op_lswx_le_hypv,
- &gen_op_lswx_64_hypv,
- &gen_op_lswx_le_64_hypv,
-#endif
-};
-static GenOpFunc1 *gen_op_stsw[] = {
- &gen_op_stsw_user,
- &gen_op_stsw_le_user,
- &gen_op_stsw_64_user,
- &gen_op_stsw_le_64_user,
- &gen_op_stsw_kernel,
- &gen_op_stsw_le_kernel,
- &gen_op_stsw_64_kernel,
- &gen_op_stsw_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_stsw_hypv,
- &gen_op_stsw_le_hypv,
- &gen_op_stsw_64_hypv,
- &gen_op_stsw_le_64_hypv,
-#endif
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc1 *gen_op_lswi[] = {
- &gen_op_lswi_user,
- &gen_op_lswi_le_user,
- &gen_op_lswi_kernel,
- &gen_op_lswi_le_kernel,
-};
-static GenOpFunc3 *gen_op_lswx[] = {
- &gen_op_lswx_user,
- &gen_op_lswx_le_user,
- &gen_op_lswx_kernel,
- &gen_op_lswx_le_kernel,
-};
-static GenOpFunc1 *gen_op_stsw[] = {
- &gen_op_stsw_user,
- &gen_op_stsw_le_user,
- &gen_op_stsw_kernel,
- &gen_op_stsw_le_kernel,
-};
-#endif
-#endif
/* lswi */
/* PowerPC32 specification says we must generate an exception if
@@ -2674,7 +2471,7 @@
* In an other hand, IBM says this is valid, but rA won't be loaded.
* For now, I'll follow the spec...
*/
-GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
+GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
{
int nb = NB(ctx->opcode);
int start = rD(ctx->opcode);
@@ -2699,7 +2496,7 @@
}
/* lswx */
-GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
+GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
{
int ra = rA(ctx->opcode);
int rb = rB(ctx->opcode);
@@ -2715,7 +2512,7 @@
}
/* stswi */
-GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
+GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
{
int nb = NB(ctx->opcode);
@@ -2729,7 +2526,7 @@
}
/* stswx */
-GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
+GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
@@ -2752,75 +2549,12 @@
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc *gen_op_lwarx[] = {
- &gen_op_lwarx_raw,
- &gen_op_lwarx_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_lwarx_64_raw,
- &gen_op_lwarx_le_64_raw,
-#endif
+static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(lwarx),
};
-static GenOpFunc *gen_op_stwcx[] = {
- &gen_op_stwcx_raw,
- &gen_op_stwcx_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_stwcx_64_raw,
- &gen_op_stwcx_le_64_raw,
-#endif
+static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(stwcx),
};
-#else
-#if defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-static GenOpFunc *gen_op_lwarx[] = {
- &gen_op_lwarx_user,
- &gen_op_lwarx_le_user,
- &gen_op_lwarx_64_user,
- &gen_op_lwarx_le_64_user,
- &gen_op_lwarx_kernel,
- &gen_op_lwarx_le_kernel,
- &gen_op_lwarx_64_kernel,
- &gen_op_lwarx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_lwarx_hypv,
- &gen_op_lwarx_le_hypv,
- &gen_op_lwarx_64_hypv,
- &gen_op_lwarx_le_64_hypv,
-#endif
-};
-static GenOpFunc *gen_op_stwcx[] = {
- &gen_op_stwcx_user,
- &gen_op_stwcx_le_user,
- &gen_op_stwcx_64_user,
- &gen_op_stwcx_le_64_user,
- &gen_op_stwcx_kernel,
- &gen_op_stwcx_le_kernel,
- &gen_op_stwcx_64_kernel,
- &gen_op_stwcx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_stwcx_hypv,
- &gen_op_stwcx_le_hypv,
- &gen_op_stwcx_64_hypv,
- &gen_op_stwcx_le_64_hypv,
-#endif
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc *gen_op_lwarx[] = {
- &gen_op_lwarx_user,
- &gen_op_lwarx_le_user,
- &gen_op_lwarx_kernel,
- &gen_op_lwarx_le_kernel,
-};
-static GenOpFunc *gen_op_stwcx[] = {
- &gen_op_stwcx_user,
- &gen_op_stwcx_le_user,
- &gen_op_stwcx_kernel,
- &gen_op_stwcx_le_kernel,
-};
-#endif
-#endif
/* lwarx */
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
@@ -2845,55 +2579,12 @@
#if defined(TARGET_PPC64)
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc *gen_op_ldarx[] = {
- &gen_op_ldarx_raw,
- &gen_op_ldarx_le_raw,
- &gen_op_ldarx_64_raw,
- &gen_op_ldarx_le_64_raw,
+static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(ldarx),
};
-static GenOpFunc *gen_op_stdcx[] = {
- &gen_op_stdcx_raw,
- &gen_op_stdcx_le_raw,
- &gen_op_stdcx_64_raw,
- &gen_op_stdcx_le_64_raw,
+static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(stdcx),
};
-#else
-/* Full system */
-static GenOpFunc *gen_op_ldarx[] = {
- &gen_op_ldarx_user,
- &gen_op_ldarx_le_user,
- &gen_op_ldarx_64_user,
- &gen_op_ldarx_le_64_user,
- &gen_op_ldarx_kernel,
- &gen_op_ldarx_le_kernel,
- &gen_op_ldarx_64_kernel,
- &gen_op_ldarx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_ldarx_hypv,
- &gen_op_ldarx_le_hypv,
- &gen_op_ldarx_64_hypv,
- &gen_op_ldarx_le_64_hypv,
-#endif
-};
-static GenOpFunc *gen_op_stdcx[] = {
- &gen_op_stdcx_user,
- &gen_op_stdcx_le_user,
- &gen_op_stdcx_64_user,
- &gen_op_stdcx_le_64_user,
- &gen_op_stdcx_kernel,
- &gen_op_stdcx_le_kernel,
- &gen_op_stdcx_64_kernel,
- &gen_op_stdcx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_stdcx_hypv,
- &gen_op_stdcx_le_hypv,
- &gen_op_stdcx_64_hypv,
- &gen_op_stdcx_le_64_hypv,
-#endif
-};
-#endif
/* ldarx */
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
@@ -3073,8 +2764,8 @@
/* Optional: */
/* stfiwx */
-OP_ST_TABLE(fiwx);
-GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
+OP_ST_TABLE(fiw);
+GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
/*** Branch ***/
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
@@ -3396,10 +3087,8 @@
GEN_SYNC(ctx);
#endif
}
-#endif
-#if defined(TARGET_PPC64H)
-GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
+GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVOPC(ctx);
@@ -3532,12 +3221,9 @@
uint32_t sprn = SPR(ctx->opcode);
#if !defined(CONFIG_USER_ONLY)
-#if defined(TARGET_PPC64H)
if (ctx->supervisor == 2)
read_cb = ctx->spr_cb[sprn].hea_read;
- else
-#endif
- if (ctx->supervisor)
+ else if (ctx->supervisor)
read_cb = ctx->spr_cb[sprn].oea_read;
else
#endif
@@ -3672,12 +3358,9 @@
uint32_t sprn = SPR(ctx->opcode);
#if !defined(CONFIG_USER_ONLY)
-#if defined(TARGET_PPC64H)
if (ctx->supervisor == 2)
write_cb = ctx->spr_cb[sprn].hea_write;
- else
-#endif
- if (ctx->supervisor)
+ else if (ctx->supervisor)
write_cb = ctx->spr_cb[sprn].oea_write;
else
#endif
@@ -3763,141 +3446,56 @@
/* dcbz */
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc *gen_op_dcbz[4][4] = {
+static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
+ /* 32 bytes cache line size */
{
- &gen_op_dcbz_l32_raw,
- &gen_op_dcbz_l32_raw,
-#if defined(TARGET_PPC64)
- &gen_op_dcbz_l32_64_raw,
- &gen_op_dcbz_l32_64_raw,
-#endif
+#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
+#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
+#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
+#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
+#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
+#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
+#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
+#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
+ GEN_MEM_FUNCS(dcbz_l32),
},
+ /* 64 bytes cache line size */
{
- &gen_op_dcbz_l64_raw,
- &gen_op_dcbz_l64_raw,
-#if defined(TARGET_PPC64)
- &gen_op_dcbz_l64_64_raw,
- &gen_op_dcbz_l64_64_raw,
-#endif
+#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
+#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
+#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
+#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
+#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
+#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
+#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
+#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
+ GEN_MEM_FUNCS(dcbz_l64),
},
+ /* 128 bytes cache line size */
{
- &gen_op_dcbz_l128_raw,
- &gen_op_dcbz_l128_raw,
-#if defined(TARGET_PPC64)
- &gen_op_dcbz_l128_64_raw,
- &gen_op_dcbz_l128_64_raw,
-#endif
+#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
+#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
+#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
+#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
+#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
+#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
+#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
+#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
+ GEN_MEM_FUNCS(dcbz_l128),
},
+ /* tunable cache line size */
{
- &gen_op_dcbz_raw,
- &gen_op_dcbz_raw,
-#if defined(TARGET_PPC64)
- &gen_op_dcbz_64_raw,
- &gen_op_dcbz_64_raw,
-#endif
+#define gen_op_dcbz_le_raw gen_op_dcbz_raw
+#define gen_op_dcbz_le_user gen_op_dcbz_user
+#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
+#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
+#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
+#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
+#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
+#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
+ GEN_MEM_FUNCS(dcbz),
},
};
-#else
-#if defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-static GenOpFunc *gen_op_dcbz[4][12] = {
- {
- &gen_op_dcbz_l32_user,
- &gen_op_dcbz_l32_user,
- &gen_op_dcbz_l32_64_user,
- &gen_op_dcbz_l32_64_user,
- &gen_op_dcbz_l32_kernel,
- &gen_op_dcbz_l32_kernel,
- &gen_op_dcbz_l32_64_kernel,
- &gen_op_dcbz_l32_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_dcbz_l32_hypv,
- &gen_op_dcbz_l32_hypv,
- &gen_op_dcbz_l32_64_hypv,
- &gen_op_dcbz_l32_64_hypv,
-#endif
- },
- {
- &gen_op_dcbz_l64_user,
- &gen_op_dcbz_l64_user,
- &gen_op_dcbz_l64_64_user,
- &gen_op_dcbz_l64_64_user,
- &gen_op_dcbz_l64_kernel,
- &gen_op_dcbz_l64_kernel,
- &gen_op_dcbz_l64_64_kernel,
- &gen_op_dcbz_l64_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_dcbz_l64_hypv,
- &gen_op_dcbz_l64_hypv,
- &gen_op_dcbz_l64_64_hypv,
- &gen_op_dcbz_l64_64_hypv,
-#endif
- },
- {
- &gen_op_dcbz_l128_user,
- &gen_op_dcbz_l128_user,
- &gen_op_dcbz_l128_64_user,
- &gen_op_dcbz_l128_64_user,
- &gen_op_dcbz_l128_kernel,
- &gen_op_dcbz_l128_kernel,
- &gen_op_dcbz_l128_64_kernel,
- &gen_op_dcbz_l128_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_dcbz_l128_hypv,
- &gen_op_dcbz_l128_hypv,
- &gen_op_dcbz_l128_64_hypv,
- &gen_op_dcbz_l128_64_hypv,
-#endif
- },
- {
- &gen_op_dcbz_user,
- &gen_op_dcbz_user,
- &gen_op_dcbz_64_user,
- &gen_op_dcbz_64_user,
- &gen_op_dcbz_kernel,
- &gen_op_dcbz_kernel,
- &gen_op_dcbz_64_kernel,
- &gen_op_dcbz_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_dcbz_hypv,
- &gen_op_dcbz_hypv,
- &gen_op_dcbz_64_hypv,
- &gen_op_dcbz_64_hypv,
-#endif
- },
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc *gen_op_dcbz[4][4] = {
- {
- &gen_op_dcbz_l32_user,
- &gen_op_dcbz_l32_user,
- &gen_op_dcbz_l32_kernel,
- &gen_op_dcbz_l32_kernel,
- },
- {
- &gen_op_dcbz_l64_user,
- &gen_op_dcbz_l64_user,
- &gen_op_dcbz_l64_kernel,
- &gen_op_dcbz_l64_kernel,
- },
- {
- &gen_op_dcbz_l128_user,
- &gen_op_dcbz_l128_user,
- &gen_op_dcbz_l128_kernel,
- &gen_op_dcbz_l128_kernel,
- },
- {
- &gen_op_dcbz_user,
- &gen_op_dcbz_user,
- &gen_op_dcbz_kernel,
- &gen_op_dcbz_kernel,
- },
-};
-#endif
-#endif
static always_inline void handler_dcbz (DisasContext *ctx,
int dcache_line_size)
@@ -3940,47 +3538,19 @@
/* icbi */
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc *gen_op_icbi[] = {
- &gen_op_icbi_raw,
- &gen_op_icbi_raw,
-#if defined(TARGET_PPC64)
- &gen_op_icbi_64_raw,
- &gen_op_icbi_64_raw,
-#endif
+#define gen_op_icbi_le_raw gen_op_icbi_raw
+#define gen_op_icbi_le_user gen_op_icbi_user
+#define gen_op_icbi_le_kernel gen_op_icbi_kernel
+#define gen_op_icbi_le_hypv gen_op_icbi_hypv
+#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
+#define gen_op_icbi_le_64_user gen_op_icbi_64_user
+#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
+#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
+static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(icbi),
};
-#else
-/* Full system - 64 bits mode */
-#if defined(TARGET_PPC64)
-static GenOpFunc *gen_op_icbi[] = {
- &gen_op_icbi_user,
- &gen_op_icbi_user,
- &gen_op_icbi_64_user,
- &gen_op_icbi_64_user,
- &gen_op_icbi_kernel,
- &gen_op_icbi_kernel,
- &gen_op_icbi_64_kernel,
- &gen_op_icbi_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_icbi_hypv,
- &gen_op_icbi_hypv,
- &gen_op_icbi_64_hypv,
- &gen_op_icbi_64_hypv,
-#endif
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc *gen_op_icbi[] = {
- &gen_op_icbi_user,
- &gen_op_icbi_user,
- &gen_op_icbi_kernel,
- &gen_op_icbi_kernel,
-};
-#endif
-#endif
-GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
+GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
@@ -4229,75 +3799,12 @@
/* Optional: */
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-/* User-mode only */
-static GenOpFunc *gen_op_eciwx[] = {
- &gen_op_eciwx_raw,
- &gen_op_eciwx_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_eciwx_64_raw,
- &gen_op_eciwx_le_64_raw,
-#endif
+static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(eciwx),
};
-static GenOpFunc *gen_op_ecowx[] = {
- &gen_op_ecowx_raw,
- &gen_op_ecowx_le_raw,
-#if defined(TARGET_PPC64)
- &gen_op_ecowx_64_raw,
- &gen_op_ecowx_le_64_raw,
-#endif
+static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(ecowx),
};
-#else
-#if defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-static GenOpFunc *gen_op_eciwx[] = {
- &gen_op_eciwx_user,
- &gen_op_eciwx_le_user,
- &gen_op_eciwx_64_user,
- &gen_op_eciwx_le_64_user,
- &gen_op_eciwx_kernel,
- &gen_op_eciwx_le_kernel,
- &gen_op_eciwx_64_kernel,
- &gen_op_eciwx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_eciwx_hypv,
- &gen_op_eciwx_le_hypv,
- &gen_op_eciwx_64_hypv,
- &gen_op_eciwx_le_64_hypv,
-#endif
-};
-static GenOpFunc *gen_op_ecowx[] = {
- &gen_op_ecowx_user,
- &gen_op_ecowx_le_user,
- &gen_op_ecowx_64_user,
- &gen_op_ecowx_le_64_user,
- &gen_op_ecowx_kernel,
- &gen_op_ecowx_le_kernel,
- &gen_op_ecowx_64_kernel,
- &gen_op_ecowx_le_64_kernel,
-#if defined(TARGET_PPC64H)
- &gen_op_ecowx_hypv,
- &gen_op_ecowx_le_hypv,
- &gen_op_ecowx_64_hypv,
- &gen_op_ecowx_le_64_hypv,
-#endif
-};
-#else
-/* Full system - 32 bits mode */
-static GenOpFunc *gen_op_eciwx[] = {
- &gen_op_eciwx_user,
- &gen_op_eciwx_le_user,
- &gen_op_eciwx_kernel,
- &gen_op_eciwx_le_kernel,
-};
-static GenOpFunc *gen_op_ecowx[] = {
- &gen_op_ecowx_user,
- &gen_op_ecowx_le_user,
- &gen_op_ecowx_kernel,
- &gen_op_ecowx_le_kernel,
-};
-#endif
-#endif
/* eciwx */
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
@@ -4422,22 +3929,26 @@
gen_op_store_T0_gpr(rD(ctx->opcode));
}
-/* As lscbx load from memory byte after byte, it's always endian safe */
+/* As lscbx load from memory byte after byte, it's always endian safe.
+ * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
+ */
#define op_POWER_lscbx(start, ra, rb) \
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
-#if defined(CONFIG_USER_ONLY)
-static GenOpFunc3 *gen_op_POWER_lscbx[] = {
- &gen_op_POWER_lscbx_raw,
- &gen_op_POWER_lscbx_raw,
+#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
+#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
+#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
+#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
+#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
+#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
+#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
+#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
+#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
+#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
+#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
+#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
+static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(POWER_lscbx),
};
-#else
-static GenOpFunc3 *gen_op_POWER_lscbx[] = {
- &gen_op_POWER_lscbx_user,
- &gen_op_POWER_lscbx_user,
- &gen_op_POWER_lscbx_kernel,
- &gen_op_POWER_lscbx_kernel,
-};
-#endif
/* lscbx - lscbx. */
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
@@ -4891,31 +4402,31 @@
/* POWER2 specific instructions */
/* Quad manipulation (load/store two floats at a time) */
+/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-static GenOpFunc *gen_op_POWER2_lfq[] = {
- &gen_op_POWER2_lfq_le_raw,
- &gen_op_POWER2_lfq_raw,
+#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
+#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
+#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
+#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
+#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
+#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
+#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
+#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
+#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
+#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
+#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
+#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
+#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
+#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
+#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
+#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
+static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(POWER2_lfq),
};
-static GenOpFunc *gen_op_POWER2_stfq[] = {
- &gen_op_POWER2_stfq_le_raw,
- &gen_op_POWER2_stfq_raw,
+static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
+ GEN_MEM_FUNCS(POWER2_stfq),
};
-#else
-static GenOpFunc *gen_op_POWER2_lfq[] = {
- &gen_op_POWER2_lfq_le_user,
- &gen_op_POWER2_lfq_user,
- &gen_op_POWER2_lfq_le_kernel,
- &gen_op_POWER2_lfq_kernel,
-};
-static GenOpFunc *gen_op_POWER2_stfq[] = {
- &gen_op_POWER2_stfq_le_user,
- &gen_op_POWER2_stfq_user,
- &gen_op_POWER2_stfq_le_kernel,
- &gen_op_POWER2_stfq_kernel,
-};
-#endif
/* lfq */
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
@@ -5023,14 +4534,14 @@
/* BookE specific instructions */
/* XXX: not implemented on 440 ? */
-GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
+GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
{
/* XXX: TODO */
GEN_EXCP_INVAL(ctx);
}
/* XXX: not implemented on 440 ? */
-GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
+GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVOPC(ctx);
@@ -5226,7 +4737,7 @@
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
/* mfdcr */
-GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
+GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVREG(ctx);
@@ -5244,7 +4755,7 @@
}
/* mtdcr */
-GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
+GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVREG(ctx);
@@ -5263,7 +4774,7 @@
/* mfdcrx */
/* XXX: not implemented on 440 ? */
-GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
+GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVREG(ctx);
@@ -5281,7 +4792,7 @@
/* mtdcrx */
/* XXX: not implemented on 440 ? */
-GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
+GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVREG(ctx);
@@ -5415,7 +4926,7 @@
/* BookE specific */
/* XXX: not implemented on 440 ? */
-GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
+GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVOPC(ctx);
@@ -5591,7 +5102,7 @@
}
/* wrtee */
-GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
+GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVOPC(ctx);
@@ -5610,7 +5121,7 @@
}
/* wrteei */
-GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
+GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
{
#if defined(CONFIG_USER_ONLY)
GEN_EXCP_PRIVOPC(ctx);
@@ -5677,111 +5188,14 @@
#endif
#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-#if defined(TARGET_PPC64)
-/* User-mode only - 64 bits mode */
#define OP_VR_LD_TABLE(name) \
-static GenOpFunc *gen_op_vr_l##name[] = { \
- &gen_op_vr_l##name##_raw, \
- &gen_op_vr_l##name##_le_raw, \
- &gen_op_vr_l##name##_64_raw, \
- &gen_op_vr_l##name##_le_64_raw, \
+static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(vr_l##name), \
};
#define OP_VR_ST_TABLE(name) \
-static GenOpFunc *gen_op_vr_st##name[] = { \
- &gen_op_vr_st##name##_raw, \
- &gen_op_vr_st##name##_le_raw, \
- &gen_op_vr_st##name##_64_raw, \
- &gen_op_vr_st##name##_le_64_raw, \
+static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(vr_st##name), \
};
-#else /* defined(TARGET_PPC64) */
-/* User-mode only - 32 bits mode */
-#define OP_VR_LD_TABLE(name) \
-static GenOpFunc *gen_op_vr_l##name[] = { \
- &gen_op_vr_l##name##_raw, \
- &gen_op_vr_l##name##_le_raw, \
-};
-#define OP_VR_ST_TABLE(name) \
-static GenOpFunc *gen_op_vr_st##name[] = { \
- &gen_op_vr_st##name##_raw, \
- &gen_op_vr_st##name##_le_raw, \
-};
-#endif /* defined(TARGET_PPC64) */
-#else /* defined(CONFIG_USER_ONLY) */
-#if defined(TARGET_PPC64H)
-/* Full system with hypervisor mode */
-#define OP_VR_LD_TABLE(name) \
-static GenOpFunc *gen_op_vr_l##name[] = { \
- &gen_op_vr_l##name##_user, \
- &gen_op_vr_l##name##_le_user, \
- &gen_op_vr_l##name##_64_user, \
- &gen_op_vr_l##name##_le_64_user, \
- &gen_op_vr_l##name##_kernel, \
- &gen_op_vr_l##name##_le_kernel, \
- &gen_op_vr_l##name##_64_kernel, \
- &gen_op_vr_l##name##_le_64_kernel, \
- &gen_op_vr_l##name##_hypv, \
- &gen_op_vr_l##name##_le_hypv, \
- &gen_op_vr_l##name##_64_hypv, \
- &gen_op_vr_l##name##_le_64_hypv, \
-};
-#define OP_VR_ST_TABLE(name) \
-static GenOpFunc *gen_op_vr_st##name[] = { \
- &gen_op_vr_st##name##_user, \
- &gen_op_vr_st##name##_le_user, \
- &gen_op_vr_st##name##_64_user, \
- &gen_op_vr_st##name##_le_64_user, \
- &gen_op_vr_st##name##_kernel, \
- &gen_op_vr_st##name##_le_kernel, \
- &gen_op_vr_st##name##_64_kernel, \
- &gen_op_vr_st##name##_le_64_kernel, \
- &gen_op_vr_st##name##_hypv, \
- &gen_op_vr_st##name##_le_hypv, \
- &gen_op_vr_st##name##_64_hypv, \
- &gen_op_vr_st##name##_le_64_hypv, \
-};
-#elif defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-#define OP_VR_LD_TABLE(name) \
-static GenOpFunc *gen_op_vr_l##name[] = { \
- &gen_op_vr_l##name##_user, \
- &gen_op_vr_l##name##_le_user, \
- &gen_op_vr_l##name##_64_user, \
- &gen_op_vr_l##name##_le_64_user, \
- &gen_op_vr_l##name##_kernel, \
- &gen_op_vr_l##name##_le_kernel, \
- &gen_op_vr_l##name##_64_kernel, \
- &gen_op_vr_l##name##_le_64_kernel, \
-};
-#define OP_VR_ST_TABLE(name) \
-static GenOpFunc *gen_op_vr_st##name[] = { \
- &gen_op_vr_st##name##_user, \
- &gen_op_vr_st##name##_le_user, \
- &gen_op_vr_st##name##_64_user, \
- &gen_op_vr_st##name##_le_64_user, \
- &gen_op_vr_st##name##_kernel, \
- &gen_op_vr_st##name##_le_kernel, \
- &gen_op_vr_st##name##_64_kernel, \
- &gen_op_vr_st##name##_le_64_kernel, \
-};
-#else /* defined(TARGET_PPC64) */
-/* Full system - 32 bits mode */
-#define OP_VR_LD_TABLE(name) \
-static GenOpFunc *gen_op_vr_l##name[] = { \
- &gen_op_vr_l##name##_user, \
- &gen_op_vr_l##name##_le_user, \
- &gen_op_vr_l##name##_kernel, \
- &gen_op_vr_l##name##_le_kernel, \
-};
-#define OP_VR_ST_TABLE(name) \
-static GenOpFunc *gen_op_vr_st##name[] = { \
- &gen_op_vr_st##name##_user, \
- &gen_op_vr_st##name##_le_user, \
- &gen_op_vr_st##name##_kernel, \
- &gen_op_vr_st##name##_le_kernel, \
-};
-#endif /* defined(TARGET_PPC64) */
-#endif /* defined(CONFIG_USER_ONLY) */
#define GEN_VR_LDX(name, opc2, opc3) \
GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
@@ -5820,7 +5234,6 @@
GEN_VR_STX(vxl, 0x07, 0x0F);
/*** SPE extension ***/
-
/* Register moves */
#if !defined(TARGET_PPC64)
@@ -5883,111 +5296,14 @@
}
#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
-#if defined(CONFIG_USER_ONLY)
-#if defined(TARGET_PPC64)
-/* User-mode only - 64 bits mode */
#define OP_SPE_LD_TABLE(name) \
-static GenOpFunc *gen_op_spe_l##name[] = { \
- &gen_op_spe_l##name##_raw, \
- &gen_op_spe_l##name##_le_raw, \
- &gen_op_spe_l##name##_64_raw, \
- &gen_op_spe_l##name##_le_64_raw, \
+static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(spe_l##name), \
};
#define OP_SPE_ST_TABLE(name) \
-static GenOpFunc *gen_op_spe_st##name[] = { \
- &gen_op_spe_st##name##_raw, \
- &gen_op_spe_st##name##_le_raw, \
- &gen_op_spe_st##name##_64_raw, \
- &gen_op_spe_st##name##_le_64_raw, \
+static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
+ GEN_MEM_FUNCS(spe_st##name), \
};
-#else /* defined(TARGET_PPC64) */
-/* User-mode only - 32 bits mode */
-#define OP_SPE_LD_TABLE(name) \
-static GenOpFunc *gen_op_spe_l##name[] = { \
- &gen_op_spe_l##name##_raw, \
- &gen_op_spe_l##name##_le_raw, \
-};
-#define OP_SPE_ST_TABLE(name) \
-static GenOpFunc *gen_op_spe_st##name[] = { \
- &gen_op_spe_st##name##_raw, \
- &gen_op_spe_st##name##_le_raw, \
-};
-#endif /* defined(TARGET_PPC64) */
-#else /* defined(CONFIG_USER_ONLY) */
-#if defined(TARGET_PPC64H)
-/* Full system with hypervisor mode */
-#define OP_SPE_LD_TABLE(name) \
-static GenOpFunc *gen_op_spe_l##name[] = { \
- &gen_op_spe_l##name##_user, \
- &gen_op_spe_l##name##_le_user, \
- &gen_op_spe_l##name##_64_user, \
- &gen_op_spe_l##name##_le_64_user, \
- &gen_op_spe_l##name##_kernel, \
- &gen_op_spe_l##name##_le_kernel, \
- &gen_op_spe_l##name##_64_kernel, \
- &gen_op_spe_l##name##_le_64_kernel, \
- &gen_op_spe_l##name##_hypv, \
- &gen_op_spe_l##name##_le_hypv, \
- &gen_op_spe_l##name##_64_hypv, \
- &gen_op_spe_l##name##_le_64_hypv, \
-};
-#define OP_SPE_ST_TABLE(name) \
-static GenOpFunc *gen_op_spe_st##name[] = { \
- &gen_op_spe_st##name##_user, \
- &gen_op_spe_st##name##_le_user, \
- &gen_op_spe_st##name##_64_user, \
- &gen_op_spe_st##name##_le_64_user, \
- &gen_op_spe_st##name##_kernel, \
- &gen_op_spe_st##name##_le_kernel, \
- &gen_op_spe_st##name##_64_kernel, \
- &gen_op_spe_st##name##_le_64_kernel, \
- &gen_op_spe_st##name##_hypv, \
- &gen_op_spe_st##name##_le_hypv, \
- &gen_op_spe_st##name##_64_hypv, \
- &gen_op_spe_st##name##_le_64_hypv, \
-};
-#elif defined(TARGET_PPC64)
-/* Full system - 64 bits mode */
-#define OP_SPE_LD_TABLE(name) \
-static GenOpFunc *gen_op_spe_l##name[] = { \
- &gen_op_spe_l##name##_user, \
- &gen_op_spe_l##name##_le_user, \
- &gen_op_spe_l##name##_64_user, \
- &gen_op_spe_l##name##_le_64_user, \
- &gen_op_spe_l##name##_kernel, \
- &gen_op_spe_l##name##_le_kernel, \
- &gen_op_spe_l##name##_64_kernel, \
- &gen_op_spe_l##name##_le_64_kernel, \
-};
-#define OP_SPE_ST_TABLE(name) \
-static GenOpFunc *gen_op_spe_st##name[] = { \
- &gen_op_spe_st##name##_user, \
- &gen_op_spe_st##name##_le_user, \
- &gen_op_spe_st##name##_64_user, \
- &gen_op_spe_st##name##_le_64_user, \
- &gen_op_spe_st##name##_kernel, \
- &gen_op_spe_st##name##_le_kernel, \
- &gen_op_spe_st##name##_64_kernel, \
- &gen_op_spe_st##name##_le_64_kernel, \
-};
-#else /* defined(TARGET_PPC64) */
-/* Full system - 32 bits mode */
-#define OP_SPE_LD_TABLE(name) \
-static GenOpFunc *gen_op_spe_l##name[] = { \
- &gen_op_spe_l##name##_user, \
- &gen_op_spe_l##name##_le_user, \
- &gen_op_spe_l##name##_kernel, \
- &gen_op_spe_l##name##_le_kernel, \
-};
-#define OP_SPE_ST_TABLE(name) \
-static GenOpFunc *gen_op_spe_st##name[] = { \
- &gen_op_spe_st##name##_user, \
- &gen_op_spe_st##name##_le_user, \
- &gen_op_spe_st##name##_kernel, \
- &gen_op_spe_st##name##_le_kernel, \
-};
-#endif /* defined(TARGET_PPC64) */
-#endif /* defined(CONFIG_USER_ONLY) */
#define GEN_SPE_LD(name, sh) \
static always_inline void gen_evl##name (DisasContext *ctx) \
@@ -6248,45 +5564,38 @@
/* In that case, we already have 64 bits load & stores
* so, spe_ldd is equivalent to ld and spe_std is equivalent to std
*/
-#if defined(CONFIG_USER_ONLY)
-#define gen_op_spe_ldd_raw gen_op_ld_raw
-#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
-#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
-#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
-#define gen_op_spe_stdd_raw gen_op_ld_raw
-#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
-#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
-#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
-#else /* defined(CONFIG_USER_ONLY) */
-#if defined(TARGET_PPC64H)
-#define gen_op_spe_ldd_hypv gen_op_ld_hypv
-#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
-#define gen_op_spe_ldd_le_hypv gen_op_ld_hypv
-#define gen_op_spe_ldd_le_64_hypv gen_op_ld_64_hypv
-#endif
-#define gen_op_spe_ldd_kernel gen_op_ld_kernel
-#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
-#define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
-#define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
-#define gen_op_spe_ldd_user gen_op_ld_user
-#define gen_op_spe_ldd_64_user gen_op_ld_64_user
-#define gen_op_spe_ldd_le_user gen_op_ld_le_user
-#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
-#if defined(TARGET_PPC64H)
-#define gen_op_spe_stdd_hypv gen_op_std_hypv
-#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
-#define gen_op_spe_stdd_le_hypv gen_op_std_hypv
-#define gen_op_spe_stdd_le_64_hypv gen_op_std_64_hypv
-#endif
-#define gen_op_spe_stdd_kernel gen_op_std_kernel
-#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
-#define gen_op_spe_stdd_le_kernel gen_op_std_kernel
-#define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
-#define gen_op_spe_stdd_user gen_op_std_user
-#define gen_op_spe_stdd_64_user gen_op_std_64_user
-#define gen_op_spe_stdd_le_user gen_op_std_le_user
-#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
-#endif /* defined(CONFIG_USER_ONLY) */
+#define gen_op_spe_ldd_raw gen_op_ld_raw
+#define gen_op_spe_ldd_user gen_op_ld_user
+#define gen_op_spe_ldd_kernel gen_op_ld_kernel
+#define gen_op_spe_ldd_hypv gen_op_ld_hypv
+#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
+#define gen_op_spe_ldd_64_user gen_op_ld_64_user
+#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
+#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
+#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
+#define gen_op_spe_ldd_le_user gen_op_ld_le_user
+#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
+#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
+#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
+#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
+#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
+#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
+#define gen_op_spe_stdd_raw gen_op_std_raw
+#define gen_op_spe_stdd_user gen_op_std_user
+#define gen_op_spe_stdd_kernel gen_op_std_kernel
+#define gen_op_spe_stdd_hypv gen_op_std_hypv
+#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
+#define gen_op_spe_stdd_64_user gen_op_std_64_user
+#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
+#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
+#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
+#define gen_op_spe_stdd_le_user gen_op_std_le_user
+#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
+#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
+#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
+#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
+#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
+#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
#endif /* defined(TARGET_PPC64) */
GEN_SPEOP_LDST(dd, 3);
GEN_SPEOP_LDST(dw, 3);
@@ -6298,28 +5607,23 @@
#if defined(TARGET_PPC64)
/* In that case, spe_stwwo is equivalent to stw */
-#if defined(CONFIG_USER_ONLY)
-#define gen_op_spe_stwwo_raw gen_op_stw_raw
-#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
-#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
-#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
-#else
-#define gen_op_spe_stwwo_user gen_op_stw_user
-#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
-#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
-#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
-#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
-#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
-#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
+#define gen_op_spe_stwwo_raw gen_op_stw_raw
+#define gen_op_spe_stwwo_user gen_op_stw_user
+#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
+#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
+#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
+#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
+#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
+#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
+#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
+#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
+#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
+#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
+#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
+#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
-#if defined(TARGET_PPC64H)
-#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
-#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
-#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
-#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
+#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
#endif
-#endif
-#endif
#define _GEN_OP_SPE_STWWE(suffix) \
static always_inline void gen_op_spe_stwwe_##suffix (void) \
{ \
@@ -6354,11 +5658,9 @@
#if defined(CONFIG_USER_ONLY)
GEN_OP_SPE_STWWE(raw);
#else /* defined(CONFIG_USER_ONLY) */
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_STWWE(hypv);
-#endif
-GEN_OP_SPE_STWWE(kernel);
GEN_OP_SPE_STWWE(user);
+GEN_OP_SPE_STWWE(kernel);
+GEN_OP_SPE_STWWE(hypv);
#endif /* defined(CONFIG_USER_ONLY) */
GEN_SPEOP_ST(wwe, 2);
GEN_SPEOP_ST(wwo, 2);
@@ -6408,109 +5710,69 @@
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
#endif
#else
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHE(hypv);
-#endif
-GEN_OP_SPE_LHE(kernel);
GEN_OP_SPE_LHE(user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
-#endif
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
+GEN_OP_SPE_LHE(kernel);
+GEN_OP_SPE_LHE(hypv);
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHE(le_hypv);
-#endif
-GEN_OP_SPE_LHE(le_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
GEN_OP_SPE_LHE(le_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
+GEN_OP_SPE_LHE(le_kernel);
+GEN_OP_SPE_LHE(le_hypv);
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
-#endif
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHX(hypv);
-#endif
-GEN_OP_SPE_LHX(kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
GEN_OP_SPE_LHX(user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
-#endif
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
+GEN_OP_SPE_LHX(kernel);
+GEN_OP_SPE_LHX(hypv);
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHX(le_hypv);
-#endif
-GEN_OP_SPE_LHX(le_kernel);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
GEN_OP_SPE_LHX(le_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
+GEN_OP_SPE_LHX(le_kernel);
+GEN_OP_SPE_LHX(le_hypv);
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
#if defined(TARGET_PPC64)
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHE(64_hypv);
-#endif
-GEN_OP_SPE_LHE(64_kernel);
GEN_OP_SPE_LHE(64_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
+GEN_OP_SPE_LHE(64_kernel);
+GEN_OP_SPE_LHE(64_hypv);
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHE(le_64_hypv);
-#endif
-GEN_OP_SPE_LHE(le_64_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
GEN_OP_SPE_LHE(le_64_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
+GEN_OP_SPE_LHE(le_64_kernel);
+GEN_OP_SPE_LHE(le_64_hypv);
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
+GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHX(64_hypv);
-#endif
-GEN_OP_SPE_LHX(64_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
+GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
GEN_OP_SPE_LHX(64_user);
-#if defined(TARGET_PPC64H)
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
-#endif
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
+GEN_OP_SPE_LHX(64_kernel);
+GEN_OP_SPE_LHX(64_hypv);
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
-#if defined(TARGET_PPC64H)
-GEN_OP_SPE_LHX(le_64_hypv);
-#endif
-GEN_OP_SPE_LHX(le_64_kernel);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
GEN_OP_SPE_LHX(le_64_user);
-#if defined(TARGET_PPC64H)
+GEN_OP_SPE_LHX(le_64_kernel);
+GEN_OP_SPE_LHX(le_64_hypv);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
+GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
#endif
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
-GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
#endif
-#endif
GEN_SPEOP_LD(hhesplat, 1);
GEN_SPEOP_LD(hhousplat, 1);
GEN_SPEOP_LD(hhossplat, 1);
@@ -6695,7 +5957,7 @@
GEN_SPEOP_COMP(efststeq);
/* Opcodes definitions */
-GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
+GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
Modified: trunk/src/host/qemu-neo1973/target-ppc/translate_init.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-ppc/translate_init.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-ppc/translate_init.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -28,21 +28,24 @@
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
-//#define PPC_DEBUG_IRQ
+//#define PPC_DUMP_SPR_ACCESSES
+#if defined(CONFIG_USER_ONLY)
+#define TODO_USER_ONLY 1
+#endif
struct ppc_def_t {
const unsigned char *name;
uint32_t pvr;
+ uint32_t svr;
uint64_t insns_flags;
uint64_t msr_mask;
- uint8_t mmu_model;
- uint8_t excp_model;
- uint8_t bus_model;
- uint8_t pad;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
void (*init_proc)(CPUPPCState *env);
- int (*check_pow)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
};
/* For user-mode emulation, we don't emulate any IRQ controller */
@@ -278,13 +281,11 @@
/* 64 bits PowerPC specific SPRs */
/* ASR */
#if defined(TARGET_PPC64)
-__attribute__ (( unused ))
static void spr_read_asr (void *opaque, int sprn)
{
gen_op_load_asr();
}
-__attribute__ (( unused ))
static void spr_write_asr (void *opaque, int sprn)
{
gen_op_store_asr();
@@ -921,11 +922,6 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -936,16 +932,6 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
@@ -984,13 +970,6 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* System version register */
- /* SVR */
- /* XXX : TODO: initialize it to an appropriate value */
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
/* Exception processing */
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -1278,14 +1257,68 @@
#endif
}
+static void gen_spr_usprgh (CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
/* PowerPC BookE SPR */
-static void gen_spr_BookE (CPUPPCState *env)
+static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
{
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
+ const unsigned char *ivor_names[64] = {
+ "IVOR0", "IVOR1", "IVOR2", "IVOR3",
+ "IVOR4", "IVOR5", "IVOR6", "IVOR7",
+ "IVOR8", "IVOR9", "IVOR10", "IVOR11",
+ "IVOR12", "IVOR13", "IVOR14", "IVOR15",
+ "IVOR16", "IVOR17", "IVOR18", "IVOR19",
+ "IVOR20", "IVOR21", "IVOR22", "IVOR23",
+ "IVOR24", "IVOR25", "IVOR26", "IVOR27",
+ "IVOR28", "IVOR29", "IVOR30", "IVOR31",
+ "IVOR32", "IVOR33", "IVOR34", "IVOR35",
+ "IVOR36", "IVOR37", "IVOR38", "IVOR39",
+ "IVOR40", "IVOR41", "IVOR42", "IVOR43",
+ "IVOR44", "IVOR45", "IVOR46", "IVOR47",
+ "IVOR48", "IVOR49", "IVOR50", "IVOR51",
+ "IVOR52", "IVOR53", "IVOR54", "IVOR55",
+ "IVOR56", "IVOR57", "IVOR58", "IVOR59",
+ "IVOR60", "IVOR61", "IVOR62", "IVOR63",
+ };
+#define SPR_BOOKE_IVORxx (-1)
+ int ivor_sprn[64] = {
+ SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
+ SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
+ SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
+ SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
+ SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ };
+ int i;
+
/* Interrupt processing */
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -1295,16 +1328,6 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
-#if 0
- spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
/* Debug */
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
@@ -1317,16 +1340,6 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1337,16 +1350,6 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1379,96 +1382,18 @@
&spr_read_generic, &spr_write_excp_prefix,
0x00000000);
/* Exception vectors */
- spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
-#if 0
- spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
-#endif
+ for (i = 0; i < 64; i++) {
+ if (ivor_mask & (1ULL << i)) {
+ if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
+ fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
+ exit(1);
+ }
+ spr_register(env, ivor_sprn[i], ivor_names[i],
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_excp_vector,
+ 0x00000000);
+ }
+ }
spr_register(env, SPR_BOOKE_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1499,76 +1424,43 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG5, "SPRG5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG6, "SPRG6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG7, "SPRG7",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
}
/* FSL storage control registers */
-static void gen_spr_BookE_FSL (CPUPPCState *env)
+static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
{
#if !defined(CONFIG_USER_ONLY)
+ const unsigned char *mas_names[8] = {
+ "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
+ };
+ int mas_sprn[8] = {
+ SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
+ SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
+ };
+ int i;
+
/* TLB assist registers */
/* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS0, "MAS0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS1, "MAS2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS2, "MAS3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS3, "MAS4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS4, "MAS5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS6, "MAS6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MAS7, "MAS7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ for (i = 0; i < 8; i++) {
+ if (mas_mask & (1 << i)) {
+ spr_register(env, mas_sprn[i], mas_names[i],
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ }
+ }
if (env->nb_pids > 1) {
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID1, "PID1",
@@ -1916,34 +1808,19 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG5, "SPRG5",
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG6, "SPRG6",
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
spr_register(env, SPR_SPRG7, "SPRG7",
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
+ gen_spr_usprgh(env);
}
/* SPR shared between PowerPC 401 & 403 implementations */
@@ -2114,7 +1991,71 @@
/* SPR specific to PowerPC 620 */
static void gen_spr_620 (CPUPPCState *env)
{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ spr_register(env, SPR_ASR, "ASR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_asr, &spr_write_asr,
+ 0x00000000);
+ /* Breakpoints */
/* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SDA, "SDA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_PMC1R, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_PMC1W, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_PMC2R, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_PMC2W, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_MMCR0R, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_MMCR0W, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if 0 // XXX: check this
+ /* XXX : not implemented */
spr_register(env, SPR_620_PMR0, "PMR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2194,19 +2135,381 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+#endif
/* XXX : not implemented */
- spr_register(env, SPR_620_HID8, "HID8",
+ spr_register(env, SPR_620_BUSCSR, "BUSCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_620_HID9, "HID9",
+ spr_register(env, SPR_620_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_L2SR, "L2SR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
#endif /* defined (TARGET_PPC64) */
+static void gen_spr_5xx_8xx (CPUPPCState *env)
+{
+ /* Exception processing */
+ spr_register(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_EIE, "EIE",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_EID, "EID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_NRI, "NRI",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPA, "CMPA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPB, "CMPB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPC, "CMPC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPD, "CMPD",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_ECR, "ECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DER, "DER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_COUNTA, "COUNTA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_COUNTB, "COUNTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPE, "CMPE",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPF, "CMPF",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPG, "CMPG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPH, "CMPH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_BAR, "BAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DPDR, "DPDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IMMR, "IMMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_5xx (CPUPPCState *env)
+{
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_FPECR, "FPECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_8xx (CPUPPCState *env)
+{
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_CST, "IC_CST",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_CST, "DC_CST",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_AP, "MI_AP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_AP, "MD_AP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TW, "MD_TW",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
// XXX: TODO
/*
* AMR => SPR 29 (Power 2.04)
@@ -2288,6 +2591,121 @@
#endif
}
+static void init_excp_MPC5xx (CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
+ env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
+ env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
+ env->excp_prefix = 0x00000000UL;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_MPC8xx (CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
+ env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
+ env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
+ env->excp_prefix = 0x00000000UL;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_G2 (CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_prefix = 0x00000000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_e200 (CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
+ env->excp_prefix = 0x00000000UL;
+ env->ivor_mask = 0x0000FFF7UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
static void init_excp_BookE (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -2339,6 +2757,7 @@
static void init_excp_602 (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
+ /* XXX: exception prefix has a special behavior on 602 */
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
@@ -2350,7 +2769,6 @@
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
@@ -2389,32 +2807,6 @@
#endif
}
-static void init_excp_G2 (CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0x00000000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
static void init_excp_604 (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -2445,9 +2837,7 @@
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
@@ -2455,7 +2845,6 @@
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
@@ -2609,9 +2998,7 @@
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
-#endif
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
@@ -2650,19 +3037,20 @@
/*****************************************************************************/
/* PowerPC implementations definitions */
-/* PowerPC 40x instruction set */
-#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
-
/* PowerPC 401 */
-#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_WRTEE | PPC_DCR | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
-#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
+#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
+#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_401 check_pow_nocheck
static void init_proc_401 (CPUPPCState *env)
@@ -2678,17 +3066,20 @@
}
/* PowerPC 401x2 */
-#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | PPC_MFTB | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
+#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_401x2 check_pow_nocheck
static void init_proc_401x2 (CPUPPCState *env)
@@ -2711,17 +3102,20 @@
}
/* PowerPC 401x3 */
-#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | PPC_MFTB | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
+#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_401x3 check_pow_nocheck
__attribute__ (( unused ))
@@ -2740,17 +3134,20 @@
}
/* IOP480 */
-#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
+#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_IOP480 check_pow_nocheck
static void init_proc_IOP480 (CPUPPCState *env)
@@ -2773,15 +3170,19 @@
}
/* PowerPC 403 */
-#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_403 (0x000000000007D00DULL)
-#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
+#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
+#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_403 check_pow_nocheck
static void init_proc_403 (CPUPPCState *env)
@@ -2802,16 +3203,20 @@
}
/* PowerPC 403 GCX */
-#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
+#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
-#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
+#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_403GCX check_pow_nocheck
static void init_proc_403GCX (CPUPPCState *env)
@@ -2846,18 +3251,20 @@
}
/* PowerPC 405 */
-#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
+#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
- PPC_405_MAC)
+ PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
#define POWERPC_MSRM_405 (0x000000000006E630ULL)
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_405 check_pow_nocheck
static void init_proc_405 (CPUPPCState *env)
@@ -2891,26 +3298,56 @@
}
/* PowerPC 440 EP */
-#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC | PPC_RFMCI)
+ PPC_440_SPEC)
#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_440EP check_pow_nocheck
+__attribute__ (( unused ))
static void init_proc_440EP (CPUPPCState *env)
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
/* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2941,25 +3378,55 @@
}
/* PowerPC 440 GP */
-#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
- PPC_405_MAC | PPC_440_SPEC)
+#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_440GP check_pow_nocheck
+__attribute__ (( unused ))
static void init_proc_440GP (CPUPPCState *env)
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -2973,8 +3440,11 @@
}
/* PowerPC 440x4 */
-#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
@@ -2983,7 +3453,7 @@
#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_440x4 check_pow_nocheck
__attribute__ (( unused ))
@@ -2991,8 +3461,34 @@
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -3006,26 +3502,56 @@
}
/* PowerPC 440x5 */
-#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC | PPC_RFMCI)
+ PPC_440_SPEC)
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_440x5 check_pow_nocheck
+__attribute__ (( unused ))
static void init_proc_440x5 (CPUPPCState *env)
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
/* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3056,17 +3582,21 @@
}
/* PowerPC 460 (guessed) */
-#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
- PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
+#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_DCRX | PPC_DCRUX | \
+ PPC_WRTEE | PPC_MFAPIDI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_460 check_pow_nocheck
__attribute__ (( unused ))
@@ -3074,9 +3604,35 @@
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
/* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3112,20 +3668,24 @@
}
/* PowerPC 460F (guessed) */
-#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
+#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \
- PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
- PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
+ PPC_DCR | PPC_DCRX | PPC_DCRUX | \
+ PPC_WRTEE | PPC_MFAPIDI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE)
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_460F check_pow_nocheck
__attribute__ (( unused ))
@@ -3133,9 +3693,35 @@
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
/* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3170,44 +3756,352 @@
/* XXX: TODO: allocate internal IRQ controller */
}
-/* Generic BookE PowerPC */
-#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
- PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | \
- PPC_FLOAT | PPC_FLOAT_FSQRT | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
- PPC_BOOKE)
-#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
-#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
-#define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
-#define check_pow_BookE check_pow_nocheck
+/* Freescale 5xx cores (aka RCPU) */
+#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_MEM_EIEIO | PPC_MEM_SYNC | \
+ PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
+ PPC_MFTB)
+#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
+#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
+#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
+#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
+#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
+#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_MPC5xx check_pow_none
__attribute__ (( unused ))
-static void init_proc_BookE (CPUPPCState *env)
+static void init_proc_MPC5xx (CPUPPCState *env)
{
- init_excp_BookE(env);
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_5xx_8xx(env);
+ gen_spr_5xx(env);
+ init_excp_MPC5xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
}
+/* Freescale 8xx cores (aka PowerQUICC) */
+#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_MEM_EIEIO | PPC_MEM_SYNC | \
+ PPC_CACHE_ICBI | PPC_MFTB)
+#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
+#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
+#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
+#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
+#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
+#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_MPC8xx check_pow_none
+
+__attribute__ (( unused ))
+static void init_proc_MPC8xx (CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_5xx_8xx(env);
+ gen_spr_8xx(env);
+ init_excp_MPC8xx(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+}
+
+/* Freescale 82xx cores (aka PowerQUICC-II) */
+/* PowerPC G2 */
+#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
+#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
+//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
+#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
+#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
+#define check_pow_G2 check_pow_hid0
+
+static void init_proc_G2 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_G2_755(env);
+ gen_spr_G2(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Hardware implementation register */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_G2(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC G2LE */
+#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
+#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
+#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
+#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
+#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
+#define check_pow_G2LE check_pow_hid0
+
+static void init_proc_G2LE (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_G2_755(env);
+ gen_spr_G2(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Hardware implementation register */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_G2(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
/* e200 core */
+/* XXX: unimplemented instructions:
+ * dcblc
+ * dcbtlst
+ * dcbtstls
+ * icblc
+ * icbtls
+ * tlbivax
+ * all SPE multiply-accumulate instructions
+ */
+#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
+ PPC_SPE | PPC_SPEFPU | \
+ PPC_WRTEE | PPC_RFDI | \
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
+ PPC_BOOKE)
+#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
+#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
+#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
+#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
+#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
+#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_e200 check_pow_hid0
+__attribute__ (( unused ))
+static void init_proc_e200 (CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000070000FFFFULL);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_spr_BookE_FSL(env, 0x0000005D);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+#endif
+ init_excp_e200(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+}
+
/* e300 core */
+#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
+#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
+#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
+#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
+#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
+#define check_pow_e300 check_pow_hid0
+__attribute__ (( unused ))
+static void init_proc_e300 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_603(env);
+ /* Time base */
+ gen_tbl(env);
+ /* hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_603(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
/* e500 core */
-#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
- PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | \
- PPC_BOOKE | PPC_E500_VECTOR)
-#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
-#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
+#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
+ PPC_SPE | PPC_SPEFPU | \
+ PPC_WRTEE | PPC_RFDI | \
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
+ PPC_BOOKE)
+#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
+#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
+#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
+#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
+#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_e500 check_pow_hid0
__attribute__ (( unused ))
@@ -3215,32 +4109,107 @@
{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env);
+ gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
- gen_spr_BookE_FSL(env);
#if !defined(CONFIG_USER_ONLY)
+ env->nb_pids = 3;
+#endif
+ gen_spr_BookE_FSL(env, 0x0000005F);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_MCAR, "MCAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_MCSR, "MCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
#endif
- init_excp_BookE(env);
+ init_excp_e200(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* XXX: TODO: allocate internal IRQ controller */
}
-/* e600 core */
-
/* Non-embedded PowerPC */
-/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
-#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
- PPC_MEM_EIEIO | PPC_MEM_TLBIE)
-/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
-#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
- PPC_SEGMENT)
/* POWER : same as 601, without mfmsr, mfsr */
#if defined(TODO)
@@ -3250,14 +4219,18 @@
#endif /* TODO */
/* PowerPC 601 */
-#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
- PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
+#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
+ PPC_FLOAT | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
+#define POWERPC_MSRR_601 (0x0000000000001040ULL)
//#define POWERPC_MMU_601 (POWERPC_MMU_601)
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
-#define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
+#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
#define check_pow_601 check_pow_none
static void init_proc_601 (CPUPPCState *env)
@@ -3285,37 +4258,59 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_601_HID15, "HID15",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 2;
- env->id_tlbs = 0;
-#endif
init_excp_601(env);
- env->dcache_line_size = 64;
+ /* XXX: beware that dcache line size is 64
+ * but dcbz uses 32 bytes "sectors"
+ * XXX: this breaks clcs instruction !
+ */
+ env->dcache_line_size = 32;
env->icache_line_size = 64;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
+/* PowerPC 601v */
+#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
+ PPC_FLOAT | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
+#define POWERPC_MSRR_601v (0x0000000000001040ULL)
+#define POWERPC_MMU_601v (POWERPC_MMU_601)
+#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
+#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
+#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
+#define check_pow_601v check_pow_none
+
+static void init_proc_601v (CPUPPCState *env)
+{
+ init_proc_601(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_601_HID15, "HID15",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* PowerPC 602 */
-#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
+#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_602_SPEC)
-#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
+#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
+/* XXX: 602 MMU is quite specific. Should add a special case */
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE)
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
#define check_pow_602 check_pow_hid0
static void init_proc_602 (CPUPPCState *env)
@@ -3346,14 +4341,20 @@
}
/* PowerPC 603 */
-#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE)
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
#define check_pow_603 check_pow_hid0
static void init_proc_603 (CPUPPCState *env)
@@ -3384,14 +4385,20 @@
}
/* PowerPC 603e */
-#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE)
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
#define check_pow_603E check_pow_hid0
static void init_proc_603E (CPUPPCState *env)
@@ -3426,111 +4433,80 @@
ppc6xx_irq_init(env);
}
-/* PowerPC G2 */
-#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
-#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
-#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
-#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
-#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE)
-#define check_pow_G2 check_pow_hid0
+/* PowerPC 604 */
+#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
+#define POWERPC_MMU_604 (POWERPC_MMU_32B)
+//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
+#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
+#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_604 check_pow_nocheck
-static void init_proc_G2 (CPUPPCState *env)
+static void init_proc_604 (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
+ gen_spr_604(env);
/* Time base */
gen_tbl(env);
- /* Hardware implementation register */
+ /* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
+ init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
-/* PowerPC G2LE */
-#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
-#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
-#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
-#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
-#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
-#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE)
-#define check_pow_G2LE check_pow_hid0
+/* PowerPC 604E */
+#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
+#define POWERPC_MMU_604E (POWERPC_MMU_32B)
+#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
+#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
+#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_604E check_pow_nocheck
-static void init_proc_G2LE (CPUPPCState *env)
+static void init_proc_604E (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation register */
+ gen_spr_604(env);
/* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
+ spr_register(env, SPR_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
+ spr_register(env, SPR_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
+ spr_register(env, SPR_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env);
-}
-
-/* PowerPC 604 */
-#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
-#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
-#define POWERPC_MMU_604 (POWERPC_MMU_32B)
-//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
-#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
-#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM)
-#define check_pow_604 check_pow_nocheck
-
-static void init_proc_604 (CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_604(env);
/* Time base */
gen_tbl(env);
/* Hardware implementation registers */
@@ -3554,14 +4530,21 @@
}
/* PowerPC 740/750 (aka G3) */
-#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
+#define POWERPC_INSNS_7x0 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM)
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#define check_pow_7x0 check_pow_hid0
static void init_proc_7x0 (CPUPPCState *env)
@@ -3593,14 +4576,21 @@
}
/* PowerPC 750FX/GX */
-#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
+#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM)
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#define check_pow_750fx check_pow_hid0
static void init_proc_750fx (CPUPPCState *env)
@@ -3639,14 +4629,21 @@
}
/* PowerPC 745/755 */
-#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
+#define POWERPC_INSNS_7x5 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM)
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#define check_pow_7x5 check_pow_hid0
static void init_proc_7x5 (CPUPPCState *env)
@@ -3698,8 +4695,16 @@
}
/* PowerPC 7400 (aka G4) */
-#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
@@ -3707,7 +4712,8 @@
#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7400 check_pow_hid0
static void init_proc_7400 (CPUPPCState *env)
@@ -3730,8 +4736,16 @@
}
/* PowerPC 7410 (aka G4) */
-#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
@@ -3739,7 +4753,8 @@
#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7410 check_pow_hid0
static void init_proc_7410 (CPUPPCState *env)
@@ -3774,8 +4789,16 @@
}
/* PowerPC 7440 (aka G4) */
-#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
@@ -3783,7 +4806,8 @@
#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7440 check_pow_hid0
__attribute__ (( unused ))
@@ -3845,8 +4869,16 @@
}
/* PowerPC 7450 (aka G4) */
-#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
@@ -3854,7 +4886,8 @@
#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7450 check_pow_hid0
__attribute__ (( unused ))
@@ -3918,8 +4951,16 @@
}
/* PowerPC 7445 (aka G4) */
-#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
@@ -3927,7 +4968,8 @@
#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7445 check_pow_hid0
__attribute__ (( unused ))
@@ -4023,8 +5065,16 @@
}
/* PowerPC 7455 (aka G4) */
-#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
@@ -4032,7 +5082,8 @@
#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#define check_pow_7455 check_pow_hid0
__attribute__ (( unused ))
@@ -4130,12 +5181,14 @@
}
#if defined (TARGET_PPC64)
-#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
/* PowerPC 970 */
-#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
@@ -4144,7 +5197,8 @@
#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
#define POWERPC_BFDM_970 (bfd_mach_ppc64)
#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
#if defined(CONFIG_USER_ONLY)
#define POWERPC970_HID5_INIT 0x00000080
@@ -4215,7 +5269,13 @@
}
/* PowerPC 970FX (aka G5) */
-#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
@@ -4224,7 +5284,8 @@
#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
static int check_pow_970FX (CPUPPCState *env)
{
@@ -4289,7 +5350,13 @@
}
/* PowerPC 970 GX */
-#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
@@ -4298,7 +5365,8 @@
#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
static int check_pow_970GX (CPUPPCState *env)
{
@@ -4363,7 +5431,13 @@
}
/* PowerPC 970 MP */
-#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
@@ -4372,7 +5446,8 @@
#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
static int check_pow_970MP (CPUPPCState *env)
{
@@ -4437,14 +5512,22 @@
}
/* PowerPC 620 */
-#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_64B | PPC_SLBI)
-#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
-#define POWERPC_MMU_620 (POWERPC_MMU_64B)
+#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
+//#define POWERPC_MMU_620 (POWERPC_MMU_620)
#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_620 (bfd_mach_ppc64)
-#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
+#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#define check_pow_620 check_pow_nocheck /* Check this */
__attribute__ (( unused ))
@@ -4462,7 +5545,6 @@
0x00000000);
/* Memory management */
gen_low_BATs(env);
- gen_high_BATs(env);
init_excp_620(env);
env->dcache_line_size = 64;
env->icache_line_size = 64;
@@ -4525,735 +5607,850 @@
enum {
/* PowerPC 401 family */
/* Generic PowerPC 401 */
-#define CPU_POWERPC_401 CPU_POWERPC_401G2
+#define CPU_POWERPC_401 CPU_POWERPC_401G2
/* PowerPC 401 cores */
- CPU_POWERPC_401A1 = 0x00210000,
- CPU_POWERPC_401B2 = 0x00220000,
+ CPU_POWERPC_401A1 = 0x00210000,
+ CPU_POWERPC_401B2 = 0x00220000,
#if 0
- CPU_POWERPC_401B3 = xxx,
+ CPU_POWERPC_401B3 = xxx,
#endif
- CPU_POWERPC_401C2 = 0x00230000,
- CPU_POWERPC_401D2 = 0x00240000,
- CPU_POWERPC_401E2 = 0x00250000,
- CPU_POWERPC_401F2 = 0x00260000,
- CPU_POWERPC_401G2 = 0x00270000,
+ CPU_POWERPC_401C2 = 0x00230000,
+ CPU_POWERPC_401D2 = 0x00240000,
+ CPU_POWERPC_401E2 = 0x00250000,
+ CPU_POWERPC_401F2 = 0x00260000,
+ CPU_POWERPC_401G2 = 0x00270000,
/* PowerPC 401 microcontrolers */
#if 0
- CPU_POWERPC_401GF = xxx,
+ CPU_POWERPC_401GF = xxx,
#endif
-#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
+#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
/* IBM Processor for Network Resources */
- CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
+ CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
#if 0
- CPU_POWERPC_XIPCHIP = xxx,
+ CPU_POWERPC_XIPCHIP = xxx,
#endif
/* PowerPC 403 family */
/* Generic PowerPC 403 */
-#define CPU_POWERPC_403 CPU_POWERPC_403GC
+#define CPU_POWERPC_403 CPU_POWERPC_403GC
/* PowerPC 403 microcontrollers */
- CPU_POWERPC_403GA = 0x00200011,
- CPU_POWERPC_403GB = 0x00200100,
- CPU_POWERPC_403GC = 0x00200200,
- CPU_POWERPC_403GCX = 0x00201400,
+ CPU_POWERPC_403GA = 0x00200011,
+ CPU_POWERPC_403GB = 0x00200100,
+ CPU_POWERPC_403GC = 0x00200200,
+ CPU_POWERPC_403GCX = 0x00201400,
#if 0
- CPU_POWERPC_403GP = xxx,
+ CPU_POWERPC_403GP = xxx,
#endif
/* PowerPC 405 family */
/* Generic PowerPC 405 */
-#define CPU_POWERPC_405 CPU_POWERPC_405D4
+#define CPU_POWERPC_405 CPU_POWERPC_405D4
/* PowerPC 405 cores */
#if 0
- CPU_POWERPC_405A3 = xxx,
+ CPU_POWERPC_405A3 = xxx,
#endif
#if 0
- CPU_POWERPC_405A4 = xxx,
+ CPU_POWERPC_405A4 = xxx,
#endif
#if 0
- CPU_POWERPC_405B3 = xxx,
+ CPU_POWERPC_405B3 = xxx,
#endif
#if 0
- CPU_POWERPC_405B4 = xxx,
+ CPU_POWERPC_405B4 = xxx,
#endif
#if 0
- CPU_POWERPC_405C3 = xxx,
+ CPU_POWERPC_405C3 = xxx,
#endif
#if 0
- CPU_POWERPC_405C4 = xxx,
+ CPU_POWERPC_405C4 = xxx,
#endif
- CPU_POWERPC_405D2 = 0x20010000,
+ CPU_POWERPC_405D2 = 0x20010000,
#if 0
- CPU_POWERPC_405D3 = xxx,
+ CPU_POWERPC_405D3 = xxx,
#endif
- CPU_POWERPC_405D4 = 0x41810000,
+ CPU_POWERPC_405D4 = 0x41810000,
#if 0
- CPU_POWERPC_405D5 = xxx,
+ CPU_POWERPC_405D5 = xxx,
#endif
#if 0
- CPU_POWERPC_405E4 = xxx,
+ CPU_POWERPC_405E4 = xxx,
#endif
#if 0
- CPU_POWERPC_405F4 = xxx,
+ CPU_POWERPC_405F4 = xxx,
#endif
#if 0
- CPU_POWERPC_405F5 = xxx,
+ CPU_POWERPC_405F5 = xxx,
#endif
#if 0
- CPU_POWERPC_405F6 = xxx,
+ CPU_POWERPC_405F6 = xxx,
#endif
/* PowerPC 405 microcontrolers */
/* XXX: missing 0x200108a0 */
-#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
- CPU_POWERPC_405CRa = 0x40110041,
- CPU_POWERPC_405CRb = 0x401100C5,
- CPU_POWERPC_405CRc = 0x40110145,
- CPU_POWERPC_405EP = 0x51210950,
+#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
+ CPU_POWERPC_405CRa = 0x40110041,
+ CPU_POWERPC_405CRb = 0x401100C5,
+ CPU_POWERPC_405CRc = 0x40110145,
+ CPU_POWERPC_405EP = 0x51210950,
#if 0
- CPU_POWERPC_405EXr = xxx,
+ CPU_POWERPC_405EXr = xxx,
#endif
- CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
+ CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
#if 0
- CPU_POWERPC_405FX = xxx,
+ CPU_POWERPC_405FX = xxx,
#endif
-#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
- CPU_POWERPC_405GPa = 0x40110000,
- CPU_POWERPC_405GPb = 0x40110040,
- CPU_POWERPC_405GPc = 0x40110082,
- CPU_POWERPC_405GPd = 0x401100C4,
-#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
- CPU_POWERPC_405GPR = 0x50910951,
+#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
+ CPU_POWERPC_405GPa = 0x40110000,
+ CPU_POWERPC_405GPb = 0x40110040,
+ CPU_POWERPC_405GPc = 0x40110082,
+ CPU_POWERPC_405GPd = 0x401100C4,
+#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
+ CPU_POWERPC_405GPR = 0x50910951,
#if 0
- CPU_POWERPC_405H = xxx,
+ CPU_POWERPC_405H = xxx,
#endif
#if 0
- CPU_POWERPC_405L = xxx,
+ CPU_POWERPC_405L = xxx,
#endif
- CPU_POWERPC_405LP = 0x41F10000,
+ CPU_POWERPC_405LP = 0x41F10000,
#if 0
- CPU_POWERPC_405PM = xxx,
+ CPU_POWERPC_405PM = xxx,
#endif
#if 0
- CPU_POWERPC_405PS = xxx,
+ CPU_POWERPC_405PS = xxx,
#endif
#if 0
- CPU_POWERPC_405S = xxx,
+ CPU_POWERPC_405S = xxx,
#endif
/* IBM network processors */
- CPU_POWERPC_NPE405H = 0x414100C0,
- CPU_POWERPC_NPE405H2 = 0x41410140,
- CPU_POWERPC_NPE405L = 0x416100C0,
- CPU_POWERPC_NPE4GS3 = 0x40B10000,
+ CPU_POWERPC_NPE405H = 0x414100C0,
+ CPU_POWERPC_NPE405H2 = 0x41410140,
+ CPU_POWERPC_NPE405L = 0x416100C0,
+ CPU_POWERPC_NPE4GS3 = 0x40B10000,
#if 0
- CPU_POWERPC_NPCxx1 = xxx,
+ CPU_POWERPC_NPCxx1 = xxx,
#endif
#if 0
- CPU_POWERPC_NPR161 = xxx,
+ CPU_POWERPC_NPR161 = xxx,
#endif
#if 0
- CPU_POWERPC_LC77700 = xxx,
+ CPU_POWERPC_LC77700 = xxx,
#endif
/* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
#if 0
- CPU_POWERPC_STB01000 = xxx,
+ CPU_POWERPC_STB01000 = xxx,
#endif
#if 0
- CPU_POWERPC_STB01010 = xxx,
+ CPU_POWERPC_STB01010 = xxx,
#endif
#if 0
- CPU_POWERPC_STB0210 = xxx, /* 401B3 */
+ CPU_POWERPC_STB0210 = xxx, /* 401B3 */
#endif
- CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
+ CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
#if 0
- CPU_POWERPC_STB043 = xxx,
+ CPU_POWERPC_STB043 = xxx,
#endif
#if 0
- CPU_POWERPC_STB045 = xxx,
+ CPU_POWERPC_STB045 = xxx,
#endif
- CPU_POWERPC_STB04 = 0x41810000,
- CPU_POWERPC_STB25 = 0x51510950,
+ CPU_POWERPC_STB04 = 0x41810000,
+ CPU_POWERPC_STB25 = 0x51510950,
#if 0
- CPU_POWERPC_STB130 = xxx,
+ CPU_POWERPC_STB130 = xxx,
#endif
/* Xilinx cores */
- CPU_POWERPC_X2VP4 = 0x20010820,
-#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
- CPU_POWERPC_X2VP20 = 0x20010860,
-#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
+ CPU_POWERPC_X2VP4 = 0x20010820,
+#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
+ CPU_POWERPC_X2VP20 = 0x20010860,
+#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
#if 0
- CPU_POWERPC_ZL10310 = xxx,
+ CPU_POWERPC_ZL10310 = xxx,
#endif
#if 0
- CPU_POWERPC_ZL10311 = xxx,
+ CPU_POWERPC_ZL10311 = xxx,
#endif
#if 0
- CPU_POWERPC_ZL10320 = xxx,
+ CPU_POWERPC_ZL10320 = xxx,
#endif
#if 0
- CPU_POWERPC_ZL10321 = xxx,
+ CPU_POWERPC_ZL10321 = xxx,
#endif
/* PowerPC 440 family */
/* Generic PowerPC 440 */
-#define CPU_POWERPC_440 CPU_POWERPC_440GXf
+#define CPU_POWERPC_440 CPU_POWERPC_440GXf
/* PowerPC 440 cores */
#if 0
- CPU_POWERPC_440A4 = xxx,
+ CPU_POWERPC_440A4 = xxx,
#endif
#if 0
- CPU_POWERPC_440A5 = xxx,
+ CPU_POWERPC_440A5 = xxx,
#endif
#if 0
- CPU_POWERPC_440B4 = xxx,
+ CPU_POWERPC_440B4 = xxx,
#endif
#if 0
- CPU_POWERPC_440F5 = xxx,
+ CPU_POWERPC_440F5 = xxx,
#endif
#if 0
- CPU_POWERPC_440G5 = xxx,
+ CPU_POWERPC_440G5 = xxx,
#endif
#if 0
- CPU_POWERPC_440H4 = xxx,
+ CPU_POWERPC_440H4 = xxx,
#endif
#if 0
- CPU_POWERPC_440H6 = xxx,
+ CPU_POWERPC_440H6 = xxx,
#endif
/* PowerPC 440 microcontrolers */
-#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
- CPU_POWERPC_440EPa = 0x42221850,
- CPU_POWERPC_440EPb = 0x422218D3,
-#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
- CPU_POWERPC_440GPb = 0x40120440,
- CPU_POWERPC_440GPc = 0x40120481,
-#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
-#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
- CPU_POWERPC_440GRX = 0x200008D0,
-#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
-#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
- CPU_POWERPC_440GXa = 0x51B21850,
- CPU_POWERPC_440GXb = 0x51B21851,
- CPU_POWERPC_440GXc = 0x51B21892,
- CPU_POWERPC_440GXf = 0x51B21894,
+#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
+ CPU_POWERPC_440EPa = 0x42221850,
+ CPU_POWERPC_440EPb = 0x422218D3,
+#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
+ CPU_POWERPC_440GPb = 0x40120440,
+ CPU_POWERPC_440GPc = 0x40120481,
+#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
+#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
+ CPU_POWERPC_440GRX = 0x200008D0,
+#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
+#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
+ CPU_POWERPC_440GXa = 0x51B21850,
+ CPU_POWERPC_440GXb = 0x51B21851,
+ CPU_POWERPC_440GXc = 0x51B21892,
+ CPU_POWERPC_440GXf = 0x51B21894,
#if 0
- CPU_POWERPC_440S = xxx,
+ CPU_POWERPC_440S = xxx,
#endif
- CPU_POWERPC_440SP = 0x53221850,
- CPU_POWERPC_440SP2 = 0x53221891,
- CPU_POWERPC_440SPE = 0x53421890,
+ CPU_POWERPC_440SP = 0x53221850,
+ CPU_POWERPC_440SP2 = 0x53221891,
+ CPU_POWERPC_440SPE = 0x53421890,
/* PowerPC 460 family */
#if 0
/* Generic PowerPC 464 */
-#define CPU_POWERPC_464 CPU_POWERPC_464H90
+#define CPU_POWERPC_464 CPU_POWERPC_464H90
#endif
/* PowerPC 464 microcontrolers */
#if 0
- CPU_POWERPC_464H90 = xxx,
+ CPU_POWERPC_464H90 = xxx,
#endif
#if 0
- CPU_POWERPC_464H90FP = xxx,
+ CPU_POWERPC_464H90FP = xxx,
#endif
/* Freescale embedded PowerPC cores */
/* PowerPC MPC 5xx cores (aka RCPU) */
- CPU_POWERPC_5xx = 0x00020020,
-#define CPU_POWERPC_509 CPU_POWERPC_5xx
-#define CPU_POWERPC_533 CPU_POWERPC_5xx
-#define CPU_POWERPC_534 CPU_POWERPC_5xx
-#define CPU_POWERPC_555 CPU_POWERPC_5xx
-#define CPU_POWERPC_556 CPU_POWERPC_5xx
-#define CPU_POWERPC_560 CPU_POWERPC_5xx
-#define CPU_POWERPC_561 CPU_POWERPC_5xx
-#define CPU_POWERPC_562 CPU_POWERPC_5xx
-#define CPU_POWERPC_563 CPU_POWERPC_5xx
-#define CPU_POWERPC_564 CPU_POWERPC_5xx
-#define CPU_POWERPC_565 CPU_POWERPC_5xx
-#define CPU_POWERPC_566 CPU_POWERPC_5xx
+ CPU_POWERPC_MPC5xx = 0x00020020,
+#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
+#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
/* PowerPC MPC 8xx cores (aka PowerQUICC) */
- CPU_POWERPC_8xx = 0x00500000,
-#define CPU_POWERPC_821 CPU_POWERPC_8xx
-#define CPU_POWERPC_823 CPU_POWERPC_8xx
-#define CPU_POWERPC_850 CPU_POWERPC_8xx
-#define CPU_POWERPC_852T CPU_POWERPC_8xx
-#define CPU_POWERPC_855T CPU_POWERPC_8xx
-#define CPU_POWERPC_859 CPU_POWERPC_8xx
-#define CPU_POWERPC_860 CPU_POWERPC_8xx
-#define CPU_POWERPC_862 CPU_POWERPC_8xx
-#define CPU_POWERPC_866 CPU_POWERPC_8xx
-#define CPU_POWERPC_857 CPU_POWERPC_8xx
-#define CPU_POWERPC_870 CPU_POWERPC_8xx
-#define CPU_POWERPC_875 CPU_POWERPC_8xx
-#define CPU_POWERPC_880 CPU_POWERPC_8xx
-#define CPU_POWERPC_885 CPU_POWERPC_8xx
+ CPU_POWERPC_MPC8xx = 0x00500000,
+#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
+#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
/* G2 cores (aka PowerQUICC-II) */
- CPU_POWERPC_G2 = 0x00810011,
- CPU_POWERPC_G2H4 = 0x80811010,
- CPU_POWERPC_G2gp = 0x80821010,
- CPU_POWERPC_G2ls = 0x90810010,
- CPU_POWERPC_MPC603 = 0x00810100,
-#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
- CPU_POWERPC_G2_HIP3 = 0x00810101,
-#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
- CPU_POWERPC_G2_HIP4 = 0x80811014,
-#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
+ CPU_POWERPC_G2 = 0x00810011,
+ CPU_POWERPC_G2H4 = 0x80811010,
+ CPU_POWERPC_G2gp = 0x80821010,
+ CPU_POWERPC_G2ls = 0x90810010,
+ CPU_POWERPC_MPC603 = 0x00810100,
+ CPU_POWERPC_G2_HIP3 = 0x00810101,
+ CPU_POWERPC_G2_HIP4 = 0x80811014,
/* G2_LE core (aka PowerQUICC-II) */
- CPU_POWERPC_G2LE = 0x80820010,
- CPU_POWERPC_G2LEgp = 0x80822010,
- CPU_POWERPC_G2LEls = 0xA0822010,
- CPU_POWERPC_G2LEgp1 = 0x80822011,
+ CPU_POWERPC_G2LE = 0x80820010,
+ CPU_POWERPC_G2LEgp = 0x80822010,
+ CPU_POWERPC_G2LEls = 0xA0822010,
+ CPU_POWERPC_G2LEgp1 = 0x80822011,
+ CPU_POWERPC_G2LEgp3 = 0x80822013,
+ /* MPC52xx microcontrollers */
/* XXX: MPC 5121 ? */
-#define CPU_POWERPC_MPC5200 CPU_POWERPC_G2LEgp1
- CPU_POWERPC_G2LEgp3 = 0x80822013,
-#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
+#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
+#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
+#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
+ /* MPC82xx microcontrollers */
+#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
+#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
+#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
+#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
+#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
+#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
+#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
+#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
+#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
+#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
+#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
+#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
/* e200 family */
-#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
+ /* e200 cores */
+#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
#if 0
- CPU_POWERPC_e200z0 = xxx,
-#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
+ CPU_POWERPC_e200z0 = xxx,
#endif
#if 0
- CPU_POWERPC_e200z1 = xxx,
-#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
+ CPU_POWERPC_e200z1 = xxx,
#endif
#if 0 /* ? */
- CPU_POWERPC_e200z3 = 0x81120000,
-#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
-#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
+ CPU_POWERPC_e200z3 = 0x81120000,
#endif
- CPU_POWERPC_e200z5 = 0x81000000,
- CPU_POWERPC_e200z6 = 0x81120000,
-#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
+ CPU_POWERPC_e200z5 = 0x81000000,
+ CPU_POWERPC_e200z6 = 0x81120000,
+ /* MPC55xx microcontrollers */
+#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
+#if 0
+#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
+#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
+#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
+#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
+#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
+#endif
+#if 0
+#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
+#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
+#endif
+#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
/* e300 family */
-#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
- CPU_POWERPC_e300c1 = 0x00830000,
-#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
- CPU_POWERPC_e300c2 = 0x00840000,
-#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
- CPU_POWERPC_e300c3 = 0x00850000,
-#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
- CPU_POWERPC_e300c4 = 0x00860000,
-#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
+ /* e300 cores */
+#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
+ CPU_POWERPC_e300c1 = 0x00830010,
+ CPU_POWERPC_e300c2 = 0x00840010,
+ CPU_POWERPC_e300c3 = 0x00850010,
+ CPU_POWERPC_e300c4 = 0x00860010,
+ /* MPC83xx microcontrollers */
+#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
/* e500 family */
-#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
- CPU_POWERPC_e500_v10 = 0x80200010,
-#define CPU_POWERPC_MPC8540_v1 CPU_POWERPC_e500_v10
- CPU_POWERPC_e500_v20 = 0x80200020,
-#define CPU_POWERPC_MPC8540_v2 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8541 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8541E CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8555 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8555E CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8560 CPU_POWERPC_e500_v20
- CPU_POWERPC_e500v2_v10 = 0x80210010,
-#define CPU_POWERPC_MPC8543 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8543E CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8545 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8545E CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8547E CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8548 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8548E CPU_POWERPC_e500v2_v10
- CPU_POWERPC_e500v2_v20 = 0x80210020,
- CPU_POWERPC_e500v2_v21 = 0x80210021,
-#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
- CPU_POWERPC_e500v2_v22 = 0x80210022,
-#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
- CPU_POWERPC_e500v2_v30 = 0x80210030,
-#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
+ /* e500 cores */
+#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
+ CPU_POWERPC_e500_v10 = 0x80200010,
+ CPU_POWERPC_e500_v20 = 0x80200020,
+ CPU_POWERPC_e500v2_v10 = 0x80210010,
+ CPU_POWERPC_e500v2_v11 = 0x80210011,
+ CPU_POWERPC_e500v2_v20 = 0x80210020,
+ CPU_POWERPC_e500v2_v21 = 0x80210021,
+ CPU_POWERPC_e500v2_v22 = 0x80210022,
+ CPU_POWERPC_e500v2_v30 = 0x80210030,
+ /* MPC85xx microcontrollers */
+#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
+#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
+#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
+#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
+#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
+#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
+#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
+#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
+#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
+#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
+#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
+#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
+#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
+#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
+#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
+#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
+#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
+#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
+#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
+#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
/* e600 family */
- CPU_POWERPC_e600 = 0x80040010,
-#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
-#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
-#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
+ /* e600 cores */
+ CPU_POWERPC_e600 = 0x80040010,
+ /* MPC86xx microcontrollers */
+#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
+#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
+#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
/* PowerPC 6xx cores */
-#define CPU_POWERPC_601 CPU_POWERPC_601_v2
- CPU_POWERPC_601_v0 = 0x00010001,
- CPU_POWERPC_601_v1 = 0x00010001,
- CPU_POWERPC_601_v2 = 0x00010002,
- CPU_POWERPC_602 = 0x00050100,
- CPU_POWERPC_603 = 0x00030100,
-#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
- CPU_POWERPC_603E_v11 = 0x00060101,
- CPU_POWERPC_603E_v12 = 0x00060102,
- CPU_POWERPC_603E_v13 = 0x00060103,
- CPU_POWERPC_603E_v14 = 0x00060104,
- CPU_POWERPC_603E_v22 = 0x00060202,
- CPU_POWERPC_603E_v3 = 0x00060300,
- CPU_POWERPC_603E_v4 = 0x00060400,
- CPU_POWERPC_603E_v41 = 0x00060401,
- CPU_POWERPC_603E7t = 0x00071201,
- CPU_POWERPC_603E7v = 0x00070100,
- CPU_POWERPC_603E7v1 = 0x00070101,
- CPU_POWERPC_603E7v2 = 0x00070201,
- CPU_POWERPC_603E7 = 0x00070200,
- CPU_POWERPC_603P = 0x00070000,
-#define CPU_POWERPC_603R CPU_POWERPC_603E7t
+#define CPU_POWERPC_601 CPU_POWERPC_601_v2
+ CPU_POWERPC_601_v0 = 0x00010001,
+ CPU_POWERPC_601_v1 = 0x00010001,
+ CPU_POWERPC_601_v2 = 0x00010002,
+ CPU_POWERPC_602 = 0x00050100,
+ CPU_POWERPC_603 = 0x00030100,
+#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
+ CPU_POWERPC_603E_v11 = 0x00060101,
+ CPU_POWERPC_603E_v12 = 0x00060102,
+ CPU_POWERPC_603E_v13 = 0x00060103,
+ CPU_POWERPC_603E_v14 = 0x00060104,
+ CPU_POWERPC_603E_v22 = 0x00060202,
+ CPU_POWERPC_603E_v3 = 0x00060300,
+ CPU_POWERPC_603E_v4 = 0x00060400,
+ CPU_POWERPC_603E_v41 = 0x00060401,
+ CPU_POWERPC_603E7t = 0x00071201,
+ CPU_POWERPC_603E7v = 0x00070100,
+ CPU_POWERPC_603E7v1 = 0x00070101,
+ CPU_POWERPC_603E7v2 = 0x00070201,
+ CPU_POWERPC_603E7 = 0x00070200,
+ CPU_POWERPC_603P = 0x00070000,
+#define CPU_POWERPC_603R CPU_POWERPC_603E7t
/* XXX: missing 0x00040303 (604) */
- CPU_POWERPC_604 = 0x00040103,
-#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
+ CPU_POWERPC_604 = 0x00040103,
+#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
/* XXX: missing 0x00091203 */
/* XXX: missing 0x00092110 */
/* XXX: missing 0x00092120 */
- CPU_POWERPC_604E_v10 = 0x00090100,
- CPU_POWERPC_604E_v22 = 0x00090202,
- CPU_POWERPC_604E_v24 = 0x00090204,
+ CPU_POWERPC_604E_v10 = 0x00090100,
+ CPU_POWERPC_604E_v22 = 0x00090202,
+ CPU_POWERPC_604E_v24 = 0x00090204,
/* XXX: missing 0x000a0100 */
/* XXX: missing 0x00093102 */
- CPU_POWERPC_604R = 0x000a0101,
+ CPU_POWERPC_604R = 0x000a0101,
#if 0
- CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
+ CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
#endif
/* PowerPC 740/750 cores (aka G3) */
/* XXX: missing 0x00084202 */
-#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
- CPU_POWERPC_7x0_v20 = 0x00080200,
- CPU_POWERPC_7x0_v21 = 0x00080201,
- CPU_POWERPC_7x0_v22 = 0x00080202,
- CPU_POWERPC_7x0_v30 = 0x00080300,
- CPU_POWERPC_7x0_v31 = 0x00080301,
- CPU_POWERPC_740E = 0x00080100,
- CPU_POWERPC_7x0P = 0x10080000,
+#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
+ CPU_POWERPC_7x0_v20 = 0x00080200,
+ CPU_POWERPC_7x0_v21 = 0x00080201,
+ CPU_POWERPC_7x0_v22 = 0x00080202,
+ CPU_POWERPC_7x0_v30 = 0x00080300,
+ CPU_POWERPC_7x0_v31 = 0x00080301,
+ CPU_POWERPC_740E = 0x00080100,
+ CPU_POWERPC_7x0P = 0x10080000,
/* XXX: missing 0x00087010 (CL ?) */
- CPU_POWERPC_750CL = 0x00087200,
-#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
- CPU_POWERPC_750CX_v21 = 0x00082201,
- CPU_POWERPC_750CX_v22 = 0x00082202,
-#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
- CPU_POWERPC_750CXE_v21 = 0x00082211,
- CPU_POWERPC_750CXE_v22 = 0x00082212,
- CPU_POWERPC_750CXE_v23 = 0x00082213,
- CPU_POWERPC_750CXE_v24 = 0x00082214,
- CPU_POWERPC_750CXE_v24b = 0x00083214,
- CPU_POWERPC_750CXE_v31 = 0x00083211,
- CPU_POWERPC_750CXE_v31b = 0x00083311,
- CPU_POWERPC_750CXR = 0x00083410,
- CPU_POWERPC_750E = 0x00080200,
- CPU_POWERPC_750FL = 0x700A0203,
-#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
- CPU_POWERPC_750FX_v10 = 0x70000100,
- CPU_POWERPC_750FX_v20 = 0x70000200,
- CPU_POWERPC_750FX_v21 = 0x70000201,
- CPU_POWERPC_750FX_v22 = 0x70000202,
- CPU_POWERPC_750FX_v23 = 0x70000203,
- CPU_POWERPC_750GL = 0x70020102,
-#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
- CPU_POWERPC_750GX_v10 = 0x70020100,
- CPU_POWERPC_750GX_v11 = 0x70020101,
- CPU_POWERPC_750GX_v12 = 0x70020102,
-#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
- CPU_POWERPC_750L_v22 = 0x00088202,
- CPU_POWERPC_750L_v30 = 0x00088300,
- CPU_POWERPC_750L_v32 = 0x00088302,
+ CPU_POWERPC_750CL = 0x00087200,
+#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
+ CPU_POWERPC_750CX_v21 = 0x00082201,
+ CPU_POWERPC_750CX_v22 = 0x00082202,
+#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
+ CPU_POWERPC_750CXE_v21 = 0x00082211,
+ CPU_POWERPC_750CXE_v22 = 0x00082212,
+ CPU_POWERPC_750CXE_v23 = 0x00082213,
+ CPU_POWERPC_750CXE_v24 = 0x00082214,
+ CPU_POWERPC_750CXE_v24b = 0x00083214,
+ CPU_POWERPC_750CXE_v31 = 0x00083211,
+ CPU_POWERPC_750CXE_v31b = 0x00083311,
+ CPU_POWERPC_750CXR = 0x00083410,
+ CPU_POWERPC_750E = 0x00080200,
+ CPU_POWERPC_750FL = 0x700A0203,
+#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
+ CPU_POWERPC_750FX_v10 = 0x70000100,
+ CPU_POWERPC_750FX_v20 = 0x70000200,
+ CPU_POWERPC_750FX_v21 = 0x70000201,
+ CPU_POWERPC_750FX_v22 = 0x70000202,
+ CPU_POWERPC_750FX_v23 = 0x70000203,
+ CPU_POWERPC_750GL = 0x70020102,
+#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
+ CPU_POWERPC_750GX_v10 = 0x70020100,
+ CPU_POWERPC_750GX_v11 = 0x70020101,
+ CPU_POWERPC_750GX_v12 = 0x70020102,
+#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
+ CPU_POWERPC_750L_v22 = 0x00088202,
+ CPU_POWERPC_750L_v30 = 0x00088300,
+ CPU_POWERPC_750L_v32 = 0x00088302,
/* PowerPC 745/755 cores */
-#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
- CPU_POWERPC_7x5_v10 = 0x00083100,
- CPU_POWERPC_7x5_v11 = 0x00083101,
- CPU_POWERPC_7x5_v20 = 0x00083200,
- CPU_POWERPC_7x5_v21 = 0x00083201,
- CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
- CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
- CPU_POWERPC_7x5_v24 = 0x00083204,
- CPU_POWERPC_7x5_v25 = 0x00083205,
- CPU_POWERPC_7x5_v26 = 0x00083206,
- CPU_POWERPC_7x5_v27 = 0x00083207,
- CPU_POWERPC_7x5_v28 = 0x00083208,
+#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
+ CPU_POWERPC_7x5_v10 = 0x00083100,
+ CPU_POWERPC_7x5_v11 = 0x00083101,
+ CPU_POWERPC_7x5_v20 = 0x00083200,
+ CPU_POWERPC_7x5_v21 = 0x00083201,
+ CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
+ CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
+ CPU_POWERPC_7x5_v24 = 0x00083204,
+ CPU_POWERPC_7x5_v25 = 0x00083205,
+ CPU_POWERPC_7x5_v26 = 0x00083206,
+ CPU_POWERPC_7x5_v27 = 0x00083207,
+ CPU_POWERPC_7x5_v28 = 0x00083208,
#if 0
- CPU_POWERPC_7x5P = xxx,
+ CPU_POWERPC_7x5P = xxx,
#endif
/* PowerPC 74xx cores (aka G4) */
/* XXX: missing 0x000C1101 */
-#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
- CPU_POWERPC_7400_v10 = 0x000C0100,
- CPU_POWERPC_7400_v11 = 0x000C0101,
- CPU_POWERPC_7400_v20 = 0x000C0200,
- CPU_POWERPC_7400_v22 = 0x000C0202,
- CPU_POWERPC_7400_v26 = 0x000C0206,
- CPU_POWERPC_7400_v27 = 0x000C0207,
- CPU_POWERPC_7400_v28 = 0x000C0208,
- CPU_POWERPC_7400_v29 = 0x000C0209,
-#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
- CPU_POWERPC_7410_v10 = 0x800C1100,
- CPU_POWERPC_7410_v11 = 0x800C1101,
- CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
- CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
- CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
-#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
- CPU_POWERPC_7448_v10 = 0x80040100,
- CPU_POWERPC_7448_v11 = 0x80040101,
- CPU_POWERPC_7448_v20 = 0x80040200,
- CPU_POWERPC_7448_v21 = 0x80040201,
-#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
- CPU_POWERPC_7450_v10 = 0x80000100,
- CPU_POWERPC_7450_v11 = 0x80000101,
- CPU_POWERPC_7450_v12 = 0x80000102,
- CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
- CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
- CPU_POWERPC_74x1 = 0x80000203,
- CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
-#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
- CPU_POWERPC_74x5_v10 = 0x80010100,
+#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
+ CPU_POWERPC_7400_v10 = 0x000C0100,
+ CPU_POWERPC_7400_v11 = 0x000C0101,
+ CPU_POWERPC_7400_v20 = 0x000C0200,
+ CPU_POWERPC_7400_v22 = 0x000C0202,
+ CPU_POWERPC_7400_v26 = 0x000C0206,
+ CPU_POWERPC_7400_v27 = 0x000C0207,
+ CPU_POWERPC_7400_v28 = 0x000C0208,
+ CPU_POWERPC_7400_v29 = 0x000C0209,
+#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
+ CPU_POWERPC_7410_v10 = 0x800C1100,
+ CPU_POWERPC_7410_v11 = 0x800C1101,
+ CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
+ CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
+ CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
+#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
+ CPU_POWERPC_7448_v10 = 0x80040100,
+ CPU_POWERPC_7448_v11 = 0x80040101,
+ CPU_POWERPC_7448_v20 = 0x80040200,
+ CPU_POWERPC_7448_v21 = 0x80040201,
+#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
+ CPU_POWERPC_7450_v10 = 0x80000100,
+ CPU_POWERPC_7450_v11 = 0x80000101,
+ CPU_POWERPC_7450_v12 = 0x80000102,
+ CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
+ CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
+ CPU_POWERPC_74x1 = 0x80000203,
+ CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
+#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
+ CPU_POWERPC_74x5_v10 = 0x80010100,
/* XXX: missing 0x80010200 */
- CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
- CPU_POWERPC_74x5_v32 = 0x80010302,
- CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
- CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
-#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
- /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
- /* XXX: missing 0x80030102 */
- /* XXX: missing 0x80020101 */
- CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
- CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
- CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
+ CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
+ CPU_POWERPC_74x5_v32 = 0x80010302,
+ CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
+ CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
+#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
+ CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
+ CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
+#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
+ CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
+ CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
/* 64 bits PowerPC */
#if defined(TARGET_PPC64)
- CPU_POWERPC_620 = 0x00140000,
- CPU_POWERPC_630 = 0x00400000,
- CPU_POWERPC_631 = 0x00410104,
- CPU_POWERPC_POWER4 = 0x00350000,
- CPU_POWERPC_POWER4P = 0x00380000,
+ CPU_POWERPC_620 = 0x00140000,
+ CPU_POWERPC_630 = 0x00400000,
+ CPU_POWERPC_631 = 0x00410104,
+ CPU_POWERPC_POWER4 = 0x00350000,
+ CPU_POWERPC_POWER4P = 0x00380000,
/* XXX: missing 0x003A0201 */
- CPU_POWERPC_POWER5 = 0x003A0203,
-#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
- CPU_POWERPC_POWER5P = 0x003B0000,
-#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
- CPU_POWERPC_POWER6 = 0x003E0000,
- CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
- CPU_POWERPC_POWER6A = 0x0F000002,
- CPU_POWERPC_970 = 0x00390202,
-#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
- CPU_POWERPC_970FX_v10 = 0x00391100,
- CPU_POWERPC_970FX_v20 = 0x003C0200,
- CPU_POWERPC_970FX_v21 = 0x003C0201,
- CPU_POWERPC_970FX_v30 = 0x003C0300,
- CPU_POWERPC_970FX_v31 = 0x003C0301,
- CPU_POWERPC_970GX = 0x00450000,
-#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
- CPU_POWERPC_970MP_v10 = 0x00440100,
- CPU_POWERPC_970MP_v11 = 0x00440101,
-#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
- CPU_POWERPC_CELL_v10 = 0x00700100,
- CPU_POWERPC_CELL_v20 = 0x00700400,
- CPU_POWERPC_CELL_v30 = 0x00700500,
- CPU_POWERPC_CELL_v31 = 0x00700501,
-#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
- CPU_POWERPC_RS64 = 0x00330000,
- CPU_POWERPC_RS64II = 0x00340000,
- CPU_POWERPC_RS64III = 0x00360000,
- CPU_POWERPC_RS64IV = 0x00370000,
+ CPU_POWERPC_POWER5 = 0x003A0203,
+#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
+ CPU_POWERPC_POWER5P = 0x003B0000,
+#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
+ CPU_POWERPC_POWER6 = 0x003E0000,
+ CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
+ CPU_POWERPC_POWER6A = 0x0F000002,
+ CPU_POWERPC_970 = 0x00390202,
+#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
+ CPU_POWERPC_970FX_v10 = 0x00391100,
+ CPU_POWERPC_970FX_v20 = 0x003C0200,
+ CPU_POWERPC_970FX_v21 = 0x003C0201,
+ CPU_POWERPC_970FX_v30 = 0x003C0300,
+ CPU_POWERPC_970FX_v31 = 0x003C0301,
+ CPU_POWERPC_970GX = 0x00450000,
+#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
+ CPU_POWERPC_970MP_v10 = 0x00440100,
+ CPU_POWERPC_970MP_v11 = 0x00440101,
+#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
+ CPU_POWERPC_CELL_v10 = 0x00700100,
+ CPU_POWERPC_CELL_v20 = 0x00700400,
+ CPU_POWERPC_CELL_v30 = 0x00700500,
+ CPU_POWERPC_CELL_v31 = 0x00700501,
+#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
+ CPU_POWERPC_RS64 = 0x00330000,
+ CPU_POWERPC_RS64II = 0x00340000,
+ CPU_POWERPC_RS64III = 0x00360000,
+ CPU_POWERPC_RS64IV = 0x00370000,
#endif /* defined(TARGET_PPC64) */
/* Original POWER */
/* XXX: should be POWER (RIOS), RSC3308, RSC4608,
* POWER2 (RIOS2) & RSC2 (P2SC) here
*/
#if 0
- CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
+ CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
#endif
#if 0
- CPU_POWER2 = xxx, /* 0x40000 ? */
+ CPU_POWER2 = xxx, /* 0x40000 ? */
#endif
/* PA Semi core */
- CPU_POWERPC_PA6T = 0x00900000,
+ CPU_POWERPC_PA6T = 0x00900000,
};
/* System version register (used on MPC 8xxx) */
enum {
- PPC_SVR_5200_v10 = 0x80110010,
- PPC_SVR_5200_v11 = 0x80110011,
- PPC_SVR_5200_v12 = 0x80110012,
- PPC_SVR_5200B_v20 = 0x80110020,
- PPC_SVR_5200B_v21 = 0x80110021,
+ POWERPC_SVR_NONE = 0x00000000,
+#define POWERPC_SVR_52xx POWERPC_SVR_5200
+#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
+ POWERPC_SVR_5200_v10 = 0x80110010,
+ POWERPC_SVR_5200_v11 = 0x80110011,
+ POWERPC_SVR_5200_v12 = 0x80110012,
+#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
+ POWERPC_SVR_5200B_v20 = 0x80110020,
+ POWERPC_SVR_5200B_v21 = 0x80110021,
+#define POWERPC_SVR_55xx POWERPC_SVR_5567
#if 0
- PPC_SVR_5533 = xxx,
+ POWERPC_SVR_5533 = xxx,
#endif
#if 0
- PPC_SVR_5534 = xxx,
+ POWERPC_SVR_5534 = xxx,
#endif
#if 0
- PPC_SVR_5553 = xxx,
+ POWERPC_SVR_5553 = xxx,
#endif
#if 0
- PPC_SVR_5554 = xxx,
+ POWERPC_SVR_5554 = xxx,
#endif
#if 0
- PPC_SVR_5561 = xxx,
+ POWERPC_SVR_5561 = xxx,
#endif
#if 0
- PPC_SVR_5565 = xxx,
+ POWERPC_SVR_5565 = xxx,
#endif
#if 0
- PPC_SVR_5566 = xxx,
+ POWERPC_SVR_5566 = xxx,
#endif
#if 0
- PPC_SVR_5567 = xxx,
+ POWERPC_SVR_5567 = xxx,
#endif
#if 0
- PPC_SVR_8313 = xxx,
+ POWERPC_SVR_8313 = xxx,
#endif
#if 0
- PPC_SVR_8313E = xxx,
+ POWERPC_SVR_8313E = xxx,
#endif
#if 0
- PPC_SVR_8314 = xxx,
+ POWERPC_SVR_8314 = xxx,
#endif
#if 0
- PPC_SVR_8314E = xxx,
+ POWERPC_SVR_8314E = xxx,
#endif
#if 0
- PPC_SVR_8315 = xxx,
+ POWERPC_SVR_8315 = xxx,
#endif
#if 0
- PPC_SVR_8315E = xxx,
+ POWERPC_SVR_8315E = xxx,
#endif
#if 0
- PPC_SVR_8321 = xxx,
+ POWERPC_SVR_8321 = xxx,
#endif
#if 0
- PPC_SVR_8321E = xxx,
+ POWERPC_SVR_8321E = xxx,
#endif
#if 0
- PPC_SVR_8323 = xxx,
+ POWERPC_SVR_8323 = xxx,
#endif
#if 0
- PPC_SVR_8323E = xxx,
+ POWERPC_SVR_8323E = xxx,
#endif
- PPC_SVR_8343A = 0x80570030,
- PPC_SVR_8343EA = 0x80560030,
- PPC_SVR_8347AP = 0x80550030, /* PBGA package */
- PPC_SVR_8347AT = 0x80530030, /* TBGA package */
- PPC_SVR_8347EAP = 0x80540030, /* PBGA package */
- PPC_SVR_8347EAT = 0x80520030, /* TBGA package */
- PPC_SVR_8349 = 0x80510010,
- PPC_SVR_8349A = 0x80510030,
- PPC_SVR_8349E = 0x80500010,
- PPC_SVR_8349EA = 0x80500030,
+ POWERPC_SVR_8343A = 0x80570030,
+ POWERPC_SVR_8343EA = 0x80560030,
+#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
+ POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
+ POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
+#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
+ POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
+ POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
+ POWERPC_SVR_8349 = 0x80510010,
+ POWERPC_SVR_8349A = 0x80510030,
+ POWERPC_SVR_8349E = 0x80500010,
+ POWERPC_SVR_8349EA = 0x80500030,
#if 0
- PPC_SVR_8358E = xxx,
+ POWERPC_SVR_8358E = xxx,
#endif
#if 0
- PPC_SVR_8360E = xxx,
+ POWERPC_SVR_8360E = xxx,
#endif
- PPC_SVR_8377 = 0x80C70010,
- PPC_SVR_8377E = 0x80C60010,
- PPC_SVR_8378 = 0x80C50010,
- PPC_SVR_8378E = 0x80C40010,
- PPC_SVR_8379 = 0x80C30010,
- PPC_SVR_8379E = 0x80C00010,
- PPC_SVR_8533_v10 = 0x80340010,
- PPC_SVR_8533_v11 = 0x80340011,
- PPC_SVR_8533E_v10 = 0x803C0010,
- PPC_SVR_8533E_v11 = 0x803C0011,
- PPC_SVR_8540_v10 = 0x80300010,
- PPC_SVR_8540_v20 = 0x80300020,
- PPC_SVR_8540_v21 = 0x80300021,
- PPC_SVR_8541_v10 = 0x80720010,
- PPC_SVR_8541_v11 = 0x80720011,
- PPC_SVR_8541E_v10 = 0x807A0010,
- PPC_SVR_8541E_v11 = 0x807A0011,
- PPC_SVR_8543_v10 = 0x80320010,
- PPC_SVR_8543_v11 = 0x80320011,
- PPC_SVR_8543_v20 = 0x80320020,
- PPC_SVR_8543_v21 = 0x80320021,
- PPC_SVR_8543E_v10 = 0x803A0010,
- PPC_SVR_8543E_v11 = 0x803A0011,
- PPC_SVR_8543E_v20 = 0x803A0020,
- PPC_SVR_8543E_v21 = 0x803A0021,
- PPC_SVR_8544_v10 = 0x80340110,
- PPC_SVR_8544_v11 = 0x80340111,
- PPC_SVR_8544E_v10 = 0x803C0110,
- PPC_SVR_8544E_v11 = 0x803C0111,
- PPC_SVR_8545_v20 = 0x80310220,
- PPC_SVR_8545_v21 = 0x80310221,
- PPC_SVR_8545E_v20 = 0x80390220,
- PPC_SVR_8545E_v21 = 0x80390221,
- PPC_SVR_8547E_v20 = 0x80390120,
- PPC_SVR_8547E_v21 = 0x80390121,
- PPC_SCR_8548_v10 = 0x80310010,
- PPC_SCR_8548_v11 = 0x80310011,
- PPC_SCR_8548_v20 = 0x80310020,
- PPC_SCR_8548_v21 = 0x80310021,
- PPC_SVR_8548E_v10 = 0x80390010,
- PPC_SVR_8548E_v11 = 0x80390011,
- PPC_SVR_8548E_v20 = 0x80390020,
- PPC_SVR_8548E_v21 = 0x80390021,
- PPC_SVR_8555_v10 = 0x80710010,
- PPC_SVR_8555_v11 = 0x80710011,
- PPC_SVR_8555E_v10 = 0x80790010,
- PPC_SVR_8555E_v11 = 0x80790011,
- PPC_SVR_8560_v10 = 0x80700010,
- PPC_SVR_8560_v20 = 0x80700020,
- PPC_SVR_8560_v21 = 0x80700021,
- PPC_SVR_8567 = 0x80750111,
- PPC_SVR_8567E = 0x807D0111,
- PPC_SVR_8568 = 0x80750011,
- PPC_SVR_8568E = 0x807D0011,
- PPC_SVR_8572 = 0x80E00010,
- PPC_SVR_8572E = 0x80E80010,
+#define POWERPC_SVR_E500 0x40000000
+ POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
+ POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
+ POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
+ POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
+ POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
+ POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
+ POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
+ POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
+ POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
+ POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
+ POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
+ POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
+ POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
+ POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
+ POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
+ POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
+ POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
+ POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
+#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
+ POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
#if 0
- PPC_SVR_8610 = xxx,
+ POWERPC_SVR_8610 = xxx,
#endif
- PPC_SVR_8641 = 0x80900021,
- PPC_SVR_8641D = 0x80900121,
+ POWERPC_SVR_8641 = 0x80900021,
+ POWERPC_SVR_8641D = 0x80900121,
};
/*****************************************************************************/
/* PowerPC CPU definitions */
-#define POWERPC_DEF(_name, _pvr, _type) \
+#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
{ \
.name = _name, \
.pvr = _pvr, \
+ .svr = _svr, \
.insns_flags = glue(POWERPC_INSNS_,_type), \
.msr_mask = glue(POWERPC_MSRM_,_type), \
.mmu_model = glue(POWERPC_MMU_,_type), \
@@ -5264,862 +6461,1575 @@
.init_proc = &glue(init_proc_,_type), \
.check_pow = &glue(check_pow_,_type), \
}
+#define POWERPC_DEF(_name, _pvr, _type) \
+POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
static const ppc_def_t ppc_defs[] = {
/* Embedded PowerPC */
/* PowerPC 401 family */
/* Generic PowerPC 401 */
- POWERPC_DEF("401", CPU_POWERPC_401, 401),
+ POWERPC_DEF("401", CPU_POWERPC_401, 401),
/* PowerPC 401 cores */
/* PowerPC 401A1 */
- POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
+ POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
/* PowerPC 401B2 */
- POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
+ POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
#if defined (TODO)
/* PowerPC 401B3 */
- POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
+ POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
#endif
/* PowerPC 401C2 */
- POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
+ POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
/* PowerPC 401D2 */
- POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
+ POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
/* PowerPC 401E2 */
- POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
+ POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
/* PowerPC 401F2 */
- POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
+ POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
/* PowerPC 401G2 */
/* XXX: to be checked */
- POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
+ POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
/* PowerPC 401 microcontrolers */
#if defined (TODO)
/* PowerPC 401GF */
- POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
+ POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
#endif
/* IOP480 (401 microcontroler) */
- POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
+ POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
/* IBM Processor for Network Resources */
- POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
+ POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
#if defined (TODO)
- POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
+ POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
#endif
/* PowerPC 403 family */
/* Generic PowerPC 403 */
- POWERPC_DEF("403", CPU_POWERPC_403, 403),
+ POWERPC_DEF("403", CPU_POWERPC_403, 403),
/* PowerPC 403 microcontrolers */
/* PowerPC 403 GA */
- POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
+ POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
/* PowerPC 403 GB */
- POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
+ POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
/* PowerPC 403 GC */
- POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
+ POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
/* PowerPC 403 GCX */
- POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
+ POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
#if defined (TODO)
/* PowerPC 403 GP */
- POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
+ POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
#endif
/* PowerPC 405 family */
/* Generic PowerPC 405 */
- POWERPC_DEF("405", CPU_POWERPC_405, 405),
+ POWERPC_DEF("405", CPU_POWERPC_405, 405),
/* PowerPC 405 cores */
#if defined (TODO)
/* PowerPC 405 A3 */
- POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
+ POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
#endif
#if defined (TODO)
/* PowerPC 405 A4 */
- POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
+ POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
#endif
#if defined (TODO)
/* PowerPC 405 B3 */
- POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
+ POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
#endif
#if defined (TODO)
/* PowerPC 405 B4 */
- POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
+ POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
#endif
#if defined (TODO)
/* PowerPC 405 C3 */
- POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
+ POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
#endif
#if defined (TODO)
/* PowerPC 405 C4 */
- POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
+ POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
#endif
/* PowerPC 405 D2 */
- POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
+ POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
#if defined (TODO)
/* PowerPC 405 D3 */
- POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
+ POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
#endif
/* PowerPC 405 D4 */
- POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
+ POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
#if defined (TODO)
/* PowerPC 405 D5 */
- POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
+ POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
#endif
#if defined (TODO)
/* PowerPC 405 E4 */
- POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
+ POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
#endif
#if defined (TODO)
/* PowerPC 405 F4 */
- POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
+ POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
#endif
#if defined (TODO)
/* PowerPC 405 F5 */
- POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
+ POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
#endif
#if defined (TODO)
/* PowerPC 405 F6 */
- POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
+ POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
#endif
/* PowerPC 405 microcontrolers */
/* PowerPC 405 CR */
- POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
+ POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
/* PowerPC 405 CRa */
- POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
+ POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
/* PowerPC 405 CRb */
- POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
+ POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
/* PowerPC 405 CRc */
- POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
+ POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
/* PowerPC 405 EP */
- POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
+ POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
#if defined(TODO)
/* PowerPC 405 EXr */
- POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
+ POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
#endif
/* PowerPC 405 EZ */
- POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
+ POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
#if defined(TODO)
/* PowerPC 405 FX */
- POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
+ POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
#endif
/* PowerPC 405 GP */
- POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
+ POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
/* PowerPC 405 GPa */
- POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
+ POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
/* PowerPC 405 GPb */
- POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
+ POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
/* PowerPC 405 GPc */
- POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
+ POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
/* PowerPC 405 GPd */
- POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
+ POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
/* PowerPC 405 GPe */
- POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
+ POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
/* PowerPC 405 GPR */
- POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
+ POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
#if defined(TODO)
/* PowerPC 405 H */
- POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
+ POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
#endif
#if defined(TODO)
/* PowerPC 405 L */
- POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
+ POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
#endif
/* PowerPC 405 LP */
- POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
+ POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
#if defined(TODO)
/* PowerPC 405 PM */
- POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
+ POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
#endif
#if defined(TODO)
/* PowerPC 405 PS */
- POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
+ POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
#endif
#if defined(TODO)
/* PowerPC 405 S */
- POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
+ POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
#endif
/* Npe405 H */
- POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
+ POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
/* Npe405 H2 */
- POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
+ POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
/* Npe405 L */
- POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
+ POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
/* Npe4GS3 */
- POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
+ POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
#if defined (TODO)
- POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
+ POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
#endif
#if defined (TODO)
- POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
+ POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
#endif
#if defined (TODO)
/* PowerPC LC77700 (Sanyo) */
- POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
+ POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
#endif
/* PowerPC 401/403/405 based set-top-box microcontrolers */
#if defined (TODO)
/* STB010000 */
- POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
+ POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
#endif
#if defined (TODO)
/* STB01010 */
- POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
+ POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
#endif
#if defined (TODO)
/* STB0210 */
- POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
+ POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
#endif
/* STB03xx */
- POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
+ POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
#if defined (TODO)
/* STB043x */
- POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
+ POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
#endif
#if defined (TODO)
/* STB045x */
- POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
+ POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
#endif
/* STB04xx */
- POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
+ POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
/* STB25xx */
- POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
+ POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
#if defined (TODO)
/* STB130 */
- POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
+ POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
#endif
/* Xilinx PowerPC 405 cores */
- POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
- POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
- POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
- POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
+ POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
+ POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
+ POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
+ POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
#if defined (TODO)
/* Zarlink ZL10310 */
- POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
+ POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
#endif
#if defined (TODO)
/* Zarlink ZL10311 */
- POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
+ POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
#endif
#if defined (TODO)
/* Zarlink ZL10320 */
- POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
+ POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
#endif
#if defined (TODO)
/* Zarlink ZL10321 */
- POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
+ POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
#endif
/* PowerPC 440 family */
+#if defined(TODO_USER_ONLY)
/* Generic PowerPC 440 */
- POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
+ POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
+#endif
/* PowerPC 440 cores */
#if defined (TODO)
/* PowerPC 440 A4 */
- POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
+ POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
#endif
#if defined (TODO)
/* PowerPC 440 A5 */
- POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
+ POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
#endif
#if defined (TODO)
/* PowerPC 440 B4 */
- POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
+ POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
#endif
#if defined (TODO)
/* PowerPC 440 G4 */
- POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
+ POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
#endif
#if defined (TODO)
/* PowerPC 440 F5 */
- POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
+ POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
#endif
#if defined (TODO)
/* PowerPC 440 G5 */
- POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
+ POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
#endif
#if defined (TODO)
/* PowerPC 440H4 */
- POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
+ POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
#endif
#if defined (TODO)
/* PowerPC 440H6 */
- POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
+ POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
#endif
/* PowerPC 440 microcontrolers */
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 EP */
- POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
+ POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 EPa */
- POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
+ POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 EPb */
- POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
+ POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 EPX */
- POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
+ POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GP */
- POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
+ POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GPb */
- POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
+ POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GPc */
- POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
+ POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GR */
- POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
+ POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GRa */
- POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
+ POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GRX */
- POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
+ POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GX */
- POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
+ POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXa */
- POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
+ POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXb */
- POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
+ POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXc */
- POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
+ POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXf */
- POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
+ POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
+#endif
#if defined(TODO)
/* PowerPC 440 S */
- POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
+ POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 SP */
- POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
+ POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 SP2 */
- POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
+ POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
+#endif
+#if defined(TODO_USER_ONLY)
/* PowerPC 440 SPE */
- POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
+ POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
+#endif
/* PowerPC 460 family */
#if defined (TODO)
/* Generic PowerPC 464 */
- POWERPC_DEF("464", CPU_POWERPC_464, 460),
+ POWERPC_DEF("464", CPU_POWERPC_464, 460),
#endif
/* PowerPC 464 microcontrolers */
#if defined (TODO)
/* PowerPC 464H90 */
- POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
+ POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
#endif
#if defined (TODO)
/* PowerPC 464H90F */
- POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
+ POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
#endif
/* Freescale embedded PowerPC cores */
+ /* MPC5xx family (aka RCPU) */
+#if defined(TODO_USER_ONLY)
+ /* Generic MPC5xx core */
+ POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* Codename for MPC5xx core */
+ POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
+#endif
+ /* MPC5xx microcontrollers */
+#if defined(TODO_USER_ONLY)
+ /* MGT560 */
+ POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC509 */
+ POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC533 */
+ POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC534 */
+ POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC555 */
+ POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC556 */
+ POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC560 */
+ POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC561 */
+ POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC562 */
+ POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC563 */
+ POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC564 */
+ POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC565 */
+ POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC566 */
+ POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
+#endif
+ /* MPC8xx family (aka PowerQUICC) */
+#if defined(TODO_USER_ONLY)
+ /* Generic MPC8xx core */
+ POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* Codename for MPC8xx core */
+ POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
+#endif
+ /* MPC8xx microcontrollers */
+#if defined(TODO_USER_ONLY)
+ /* MGT823 */
+ POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC821 */
+ POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC823 */
+ POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC850 */
+ POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC852T */
+ POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC855T */
+ POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC857 */
+ POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC859 */
+ POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC860 */
+ POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC862 */
+ POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC866 */
+ POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC870 */
+ POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC875 */
+ POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC880 */
+ POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
+#endif
+#if defined(TODO_USER_ONLY)
+ /* MPC885 */
+ POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
+#endif
+ /* MPC82xx family (aka PowerQUICC-II) */
+ /* Generic MPC52xx core */
+ POWERPC_DEF_SVR("MPC52xx",
+ CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
+ /* Generic MPC82xx core */
+ POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
+ /* Codename for MPC82xx */
+ POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
+ /* PowerPC G2 core */
+ POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
+ /* PowerPC G2 H4 core */
+ POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
+ /* PowerPC G2 GP core */
+ POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
+ /* PowerPC G2 LS core */
+ POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
+ /* PowerPC G2 HiP3 core */
+ POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
+ /* PowerPC G2 HiP4 core */
+ POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
+ /* PowerPC MPC603 core */
+ POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
+ /* PowerPC G2le core (same as G2 plus little-endian mode support) */
+ POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
+ /* PowerPC G2LE GP core */
+ POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
+ /* PowerPC G2LE LS core */
+ POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
+ /* PowerPC G2LE GP1 core */
+ POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
+ /* PowerPC G2LE GP3 core */
+ POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
+ /* PowerPC MPC603 microcontrollers */
+ /* MPC8240 */
+ POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
+ /* PowerPC G2 microcontrollers */
+#if defined(TODO)
+ /* MPC5121 */
+ POWERPC_DEF_SVR("MPC5121",
+ CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
+#endif
+ /* MPC5200 */
+ POWERPC_DEF_SVR("MPC5200",
+ CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
+ /* MPC5200 v1.0 */
+ POWERPC_DEF_SVR("MPC5200_v10",
+ CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
+ /* MPC5200 v1.1 */
+ POWERPC_DEF_SVR("MPC5200_v11",
+ CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
+ /* MPC5200 v1.2 */
+ POWERPC_DEF_SVR("MPC5200_v12",
+ CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
+ /* MPC5200B */
+ POWERPC_DEF_SVR("MPC5200B",
+ CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
+ /* MPC5200B v2.0 */
+ POWERPC_DEF_SVR("MPC5200B_v20",
+ CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
+ /* MPC5200B v2.1 */
+ POWERPC_DEF_SVR("MPC5200B_v21",
+ CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
+ /* MPC8241 */
+ POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
+ /* MPC8245 */
+ POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
+ /* MPC8247 */
+ POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
+ /* MPC8248 */
+ POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
+ /* MPC8250 */
+ POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
+ /* MPC8250 HiP3 */
+ POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
+ /* MPC8250 HiP4 */
+ POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
+ /* MPC8255 */
+ POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
+ /* MPC8255 HiP3 */
+ POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
+ /* MPC8255 HiP4 */
+ POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
+ /* MPC8260 */
+ POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
+ /* MPC8260 HiP3 */
+ POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
+ /* MPC8260 HiP4 */
+ POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
+ /* MPC8264 */
+ POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
+ /* MPC8264 HiP3 */
+ POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
+ /* MPC8264 HiP4 */
+ POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
+ /* MPC8265 */
+ POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
+ /* MPC8265 HiP3 */
+ POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
+ /* MPC8265 HiP4 */
+ POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
+ /* MPC8266 */
+ POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
+ /* MPC8266 HiP3 */
+ POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
+ /* MPC8266 HiP4 */
+ POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
+ /* MPC8270 */
+ POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
+ /* MPC8271 */
+ POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
+ /* MPC8272 */
+ POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
+ /* MPC8275 */
+ POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
+ /* MPC8280 */
+ POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
/* e200 family */
+ /* Generic PowerPC e200 core */
+ POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
+ /* Generic MPC55xx core */
#if defined (TODO)
- /* Generic PowerPC e200 core */
- POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
+ POWERPC_DEF_SVR("MPC55xx",
+ CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
#endif
#if defined (TODO)
- /* PowerPC e200z5 core */
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
+ /* PowerPC e200z0 core */
+ POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
#endif
#if defined (TODO)
+ /* PowerPC e200z1 core */
+ POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
+#endif
+#if defined (TODO)
+ /* PowerPC e200z3 core */
+ POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
+#endif
+ /* PowerPC e200z5 core */
+ POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
/* PowerPC e200z6 core */
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
+ POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
+ /* PowerPC e200 microcontrollers */
+#if defined (TODO)
+ /* MPC5514E */
+ POWERPC_DEF_SVR("MPC5514E",
+ CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
#endif
- /* e300 family */
#if defined (TODO)
- /* Generic PowerPC e300 core */
- POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
+ /* MPC5514E v0 */
+ POWERPC_DEF_SVR("MPC5514E_v0",
+ CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
#endif
#if defined (TODO)
- /* PowerPC e300c1 core */
- POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
+ /* MPC5514E v1 */
+ POWERPC_DEF_SVR("MPC5514E_v1",
+ CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
#endif
#if defined (TODO)
- /* PowerPC e300c2 core */
- POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
+ /* MPC5514G */
+ POWERPC_DEF_SVR("MPC5514G",
+ CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
#endif
#if defined (TODO)
+ /* MPC5514G v0 */
+ POWERPC_DEF_SVR("MPC5514G_v0",
+ CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
+#endif
+#if defined (TODO)
+ /* MPC5514G v1 */
+ POWERPC_DEF_SVR("MPC5514G_v1",
+ CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
+#endif
+#if defined (TODO)
+ /* MPC5515S */
+ POWERPC_DEF_SVR("MPC5515S",
+ CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516E */
+ POWERPC_DEF_SVR("MPC5516E",
+ CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516E v0 */
+ POWERPC_DEF_SVR("MPC5516E_v0",
+ CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516E v1 */
+ POWERPC_DEF_SVR("MPC5516E_v1",
+ CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516G */
+ POWERPC_DEF_SVR("MPC5516G",
+ CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516G v0 */
+ POWERPC_DEF_SVR("MPC5516G_v0",
+ CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516G v1 */
+ POWERPC_DEF_SVR("MPC5516G_v1",
+ CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
+#endif
+#if defined (TODO)
+ /* MPC5516S */
+ POWERPC_DEF_SVR("MPC5516S",
+ CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
+#endif
+#if defined (TODO)
+ /* MPC5533 */
+ POWERPC_DEF_SVR("MPC5533",
+ CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
+#endif
+#if defined (TODO)
+ /* MPC5534 */
+ POWERPC_DEF_SVR("MPC5534",
+ CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
+#endif
+#if defined (TODO)
+ /* MPC5553 */
+ POWERPC_DEF_SVR("MPC5553",
+ CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
+#endif
+#if defined (TODO)
+ /* MPC5554 */
+ POWERPC_DEF_SVR("MPC5554",
+ CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
+#endif
+#if defined (TODO)
+ /* MPC5561 */
+ POWERPC_DEF_SVR("MPC5561",
+ CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
+#endif
+#if defined (TODO)
+ /* MPC5565 */
+ POWERPC_DEF_SVR("MPC5565",
+ CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
+#endif
+#if defined (TODO)
+ /* MPC5566 */
+ POWERPC_DEF_SVR("MPC5566",
+ CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
+#endif
+#if defined (TODO)
+ /* MPC5567 */
+ POWERPC_DEF_SVR("MPC5567",
+ CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
+#endif
+ /* e300 family */
+ /* Generic PowerPC e300 core */
+ POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
+ /* PowerPC e300c1 core */
+ POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
+ /* PowerPC e300c2 core */
+ POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
/* PowerPC e300c3 core */
- POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
+ POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
+ /* PowerPC e300c4 core */
+ POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
+ /* PowerPC e300 microcontrollers */
+#if defined (TODO)
+ /* MPC8313 */
+ POWERPC_DEF_SVR("MPC8313",
+ CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
#endif
- /* e500 family */
#if defined (TODO)
- /* PowerPC e500 core */
- POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
+ /* MPC8313E */
+ POWERPC_DEF_SVR("MPC8313E",
+ CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
#endif
#if defined (TODO)
- /* PowerPC e500 v1.1 core */
- POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, e500),
+ /* MPC8314 */
+ POWERPC_DEF_SVR("MPC8314",
+ CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
#endif
#if defined (TODO)
- /* PowerPC e500 v1.2 core */
- POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, e500),
+ /* MPC8314E */
+ POWERPC_DEF_SVR("MPC8314E",
+ CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
#endif
#if defined (TODO)
- /* PowerPC e500 v2.1 core */
- POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, e500),
+ /* MPC8315 */
+ POWERPC_DEF_SVR("MPC8315",
+ CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
#endif
#if defined (TODO)
- /* PowerPC e500 v2.2 core */
- POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, e500),
+ /* MPC8315E */
+ POWERPC_DEF_SVR("MPC8315E",
+ CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
#endif
- /* e600 family */
#if defined (TODO)
- /* PowerPC e600 core */
- POWERPC_DEF("e600", CPU_POWERPC_e600, e600),
+ /* MPC8321 */
+ POWERPC_DEF_SVR("MPC8321",
+ CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
#endif
- /* PowerPC MPC 5xx cores */
#if defined (TODO)
- /* PowerPC MPC 5xx */
- POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 5xx),
+ /* MPC8321E */
+ POWERPC_DEF_SVR("MPC8321E",
+ CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
#endif
- /* PowerPC MPC 8xx cores */
#if defined (TODO)
- /* PowerPC MPC 8xx */
- POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 8xx),
+ /* MPC8323 */
+ POWERPC_DEF_SVR("MPC8323",
+ CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
#endif
- /* PowerPC MPC 8xxx cores */
#if defined (TODO)
- /* PowerPC MPC 82xx HIP3 */
- POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 82xx),
+ /* MPC8323E */
+ POWERPC_DEF_SVR("MPC8323E",
+ CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
#endif
+ /* MPC8343A */
+ POWERPC_DEF_SVR("MPC8343A",
+ CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
+ /* MPC8343EA */
+ POWERPC_DEF_SVR("MPC8343EA",
+ CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
+ /* MPC8347A */
+ POWERPC_DEF_SVR("MPC8347A",
+ CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
+ /* MPC8347AT */
+ POWERPC_DEF_SVR("MPC8347AT",
+ CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
+ /* MPC8347AP */
+ POWERPC_DEF_SVR("MPC8347AP",
+ CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
+ /* MPC8347EA */
+ POWERPC_DEF_SVR("MPC8347EA",
+ CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
+ /* MPC8347EAT */
+ POWERPC_DEF_SVR("MPC8347EAT",
+ CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
+ /* MPC8343EAP */
+ POWERPC_DEF_SVR("MPC8347EAP",
+ CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
+ /* MPC8349 */
+ POWERPC_DEF_SVR("MPC8349",
+ CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
+ /* MPC8349A */
+ POWERPC_DEF_SVR("MPC8349A",
+ CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
+ /* MPC8349E */
+ POWERPC_DEF_SVR("MPC8349E",
+ CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
+ /* MPC8349EA */
+ POWERPC_DEF_SVR("MPC8349EA",
+ CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
#if defined (TODO)
- /* PowerPC MPC 82xx HIP4 */
- POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 82xx),
+ /* MPC8358E */
+ POWERPC_DEF_SVR("MPC8358E",
+ CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
#endif
#if defined (TODO)
- /* PowerPC MPC 827x */
- POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 827x),
+ /* MPC8360E */
+ POWERPC_DEF_SVR("MPC8360E",
+ CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
#endif
-
+ /* MPC8377 */
+ POWERPC_DEF_SVR("MPC8377",
+ CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
+ /* MPC8377E */
+ POWERPC_DEF_SVR("MPC8377E",
+ CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
+ /* MPC8378 */
+ POWERPC_DEF_SVR("MPC8378",
+ CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
+ /* MPC8378E */
+ POWERPC_DEF_SVR("MPC8378E",
+ CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
+ /* MPC8379 */
+ POWERPC_DEF_SVR("MPC8379",
+ CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
+ /* MPC8379E */
+ POWERPC_DEF_SVR("MPC8379E",
+ CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
+ /* e500 family */
+ /* PowerPC e500 core */
+ POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
+ /* PowerPC e500 v1.0 core */
+ POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
+ /* PowerPC e500 v2.0 core */
+ POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
+ /* PowerPC e500v2 core */
+ POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
+ /* PowerPC e500v2 v1.0 core */
+ POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
+ /* PowerPC e500v2 v2.0 core */
+ POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
+ /* PowerPC e500v2 v2.1 core */
+ POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
+ /* PowerPC e500v2 v2.2 core */
+ POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
+ /* PowerPC e500v2 v3.0 core */
+ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
+ /* PowerPC e500 microcontrollers */
+ /* MPC8533 */
+ POWERPC_DEF_SVR("MPC8533",
+ CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
+ /* MPC8533 v1.0 */
+ POWERPC_DEF_SVR("MPC8533_v10",
+ CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
+ /* MPC8533 v1.1 */
+ POWERPC_DEF_SVR("MPC8533_v11",
+ CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
+ /* MPC8533E */
+ POWERPC_DEF_SVR("MPC8533E",
+ CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
+ /* MPC8533E v1.0 */
+ POWERPC_DEF_SVR("MPC8533E_v10",
+ CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
+ POWERPC_DEF_SVR("MPC8533E_v11",
+ CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
+ /* MPC8540 */
+ POWERPC_DEF_SVR("MPC8540",
+ CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
+ /* MPC8540 v1.0 */
+ POWERPC_DEF_SVR("MPC8540_v10",
+ CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
+ /* MPC8540 v2.0 */
+ POWERPC_DEF_SVR("MPC8540_v20",
+ CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
+ /* MPC8540 v2.1 */
+ POWERPC_DEF_SVR("MPC8540_v21",
+ CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
+ /* MPC8541 */
+ POWERPC_DEF_SVR("MPC8541",
+ CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
+ /* MPC8541 v1.0 */
+ POWERPC_DEF_SVR("MPC8541_v10",
+ CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
+ /* MPC8541 v1.1 */
+ POWERPC_DEF_SVR("MPC8541_v11",
+ CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
+ /* MPC8541E */
+ POWERPC_DEF_SVR("MPC8541E",
+ CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
+ /* MPC8541E v1.0 */
+ POWERPC_DEF_SVR("MPC8541E_v10",
+ CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
+ /* MPC8541E v1.1 */
+ POWERPC_DEF_SVR("MPC8541E_v11",
+ CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
+ /* MPC8543 */
+ POWERPC_DEF_SVR("MPC8543",
+ CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
+ /* MPC8543 v1.0 */
+ POWERPC_DEF_SVR("MPC8543_v10",
+ CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
+ /* MPC8543 v1.1 */
+ POWERPC_DEF_SVR("MPC8543_v11",
+ CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
+ /* MPC8543 v2.0 */
+ POWERPC_DEF_SVR("MPC8543_v20",
+ CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
+ /* MPC8543 v2.1 */
+ POWERPC_DEF_SVR("MPC8543_v21",
+ CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
+ /* MPC8543E */
+ POWERPC_DEF_SVR("MPC8543E",
+ CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
+ /* MPC8543E v1.0 */
+ POWERPC_DEF_SVR("MPC8543E_v10",
+ CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
+ /* MPC8543E v1.1 */
+ POWERPC_DEF_SVR("MPC8543E_v11",
+ CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
+ /* MPC8543E v2.0 */
+ POWERPC_DEF_SVR("MPC8543E_v20",
+ CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
+ /* MPC8543E v2.1 */
+ POWERPC_DEF_SVR("MPC8543E_v21",
+ CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
+ /* MPC8544 */
+ POWERPC_DEF_SVR("MPC8544",
+ CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
+ /* MPC8544 v1.0 */
+ POWERPC_DEF_SVR("MPC8544_v10",
+ CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
+ /* MPC8544 v1.1 */
+ POWERPC_DEF_SVR("MPC8544_v11",
+ CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
+ /* MPC8544E */
+ POWERPC_DEF_SVR("MPC8544E",
+ CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
+ /* MPC8544E v1.0 */
+ POWERPC_DEF_SVR("MPC8544E_v10",
+ CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
+ /* MPC8544E v1.1 */
+ POWERPC_DEF_SVR("MPC8544E_v11",
+ CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
+ /* MPC8545 */
+ POWERPC_DEF_SVR("MPC8545",
+ CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
+ /* MPC8545 v2.0 */
+ POWERPC_DEF_SVR("MPC8545_v20",
+ CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
+ /* MPC8545 v2.1 */
+ POWERPC_DEF_SVR("MPC8545_v21",
+ CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
+ /* MPC8545E */
+ POWERPC_DEF_SVR("MPC8545E",
+ CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
+ /* MPC8545E v2.0 */
+ POWERPC_DEF_SVR("MPC8545E_v20",
+ CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
+ /* MPC8545E v2.1 */
+ POWERPC_DEF_SVR("MPC8545E_v21",
+ CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
+ /* MPC8547E */
+ POWERPC_DEF_SVR("MPC8547E",
+ CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
+ /* MPC8547E v2.0 */
+ POWERPC_DEF_SVR("MPC8547E_v20",
+ CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
+ /* MPC8547E v2.1 */
+ POWERPC_DEF_SVR("MPC8547E_v21",
+ CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
+ /* MPC8548 */
+ POWERPC_DEF_SVR("MPC8548",
+ CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
+ /* MPC8548 v1.0 */
+ POWERPC_DEF_SVR("MPC8548_v10",
+ CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
+ /* MPC8548 v1.1 */
+ POWERPC_DEF_SVR("MPC8548_v11",
+ CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
+ /* MPC8548 v2.0 */
+ POWERPC_DEF_SVR("MPC8548_v20",
+ CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
+ /* MPC8548 v2.1 */
+ POWERPC_DEF_SVR("MPC8548_v21",
+ CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
+ /* MPC8548E */
+ POWERPC_DEF_SVR("MPC8548E",
+ CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
+ /* MPC8548E v1.0 */
+ POWERPC_DEF_SVR("MPC8548E_v10",
+ CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
+ /* MPC8548E v1.1 */
+ POWERPC_DEF_SVR("MPC8548E_v11",
+ CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
+ /* MPC8548E v2.0 */
+ POWERPC_DEF_SVR("MPC8548E_v20",
+ CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
+ /* MPC8548E v2.1 */
+ POWERPC_DEF_SVR("MPC8548E_v21",
+ CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
+ /* MPC8555 */
+ POWERPC_DEF_SVR("MPC8555",
+ CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
+ /* MPC8555 v1.0 */
+ POWERPC_DEF_SVR("MPC8555_v10",
+ CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
+ /* MPC8555 v1.1 */
+ POWERPC_DEF_SVR("MPC8555_v11",
+ CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
+ /* MPC8555E */
+ POWERPC_DEF_SVR("MPC8555E",
+ CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
+ /* MPC8555E v1.0 */
+ POWERPC_DEF_SVR("MPC8555E_v10",
+ CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
+ /* MPC8555E v1.1 */
+ POWERPC_DEF_SVR("MPC8555E_v11",
+ CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
+ /* MPC8560 */
+ POWERPC_DEF_SVR("MPC8560",
+ CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
+ /* MPC8560 v1.0 */
+ POWERPC_DEF_SVR("MPC8560_v10",
+ CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
+ /* MPC8560 v2.0 */
+ POWERPC_DEF_SVR("MPC8560_v20",
+ CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
+ /* MPC8560 v2.1 */
+ POWERPC_DEF_SVR("MPC8560_v21",
+ CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
+ /* MPC8567 */
+ POWERPC_DEF_SVR("MPC8567",
+ CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
+ /* MPC8567E */
+ POWERPC_DEF_SVR("MPC8567E",
+ CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
+ /* MPC8568 */
+ POWERPC_DEF_SVR("MPC8568",
+ CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
+ /* MPC8568E */
+ POWERPC_DEF_SVR("MPC8568E",
+ CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
+ /* MPC8572 */
+ POWERPC_DEF_SVR("MPC8572",
+ CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
+ /* MPC8572E */
+ POWERPC_DEF_SVR("MPC8572E",
+ CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
+ /* e600 family */
+ /* PowerPC e600 core */
+ POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
+ /* PowerPC e600 microcontrollers */
+#if defined (TODO)
+ /* MPC8610 */
+ POWERPC_DEF_SVR("MPC8610",
+ CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
+#endif
+ /* MPC8641 */
+ POWERPC_DEF_SVR("MPC8641",
+ CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
+ /* MPC8641D */
+ POWERPC_DEF_SVR("MPC8641D",
+ CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
/* PowerPC 601 */
- POWERPC_DEF("601", CPU_POWERPC_601, 601),
+ POWERPC_DEF("601", CPU_POWERPC_601, 601),
/* PowerPC 601v0 */
- POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
+ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
/* PowerPC 601v1 */
- POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
+ POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
+ /* PowerPC 601v */
+ POWERPC_DEF("601v", CPU_POWERPC_601, 601v),
/* PowerPC 601v2 */
- POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
+ POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
/* PowerPC 602 */
- POWERPC_DEF("602", CPU_POWERPC_602, 602),
+ POWERPC_DEF("602", CPU_POWERPC_602, 602),
/* PowerPC 603 */
- POWERPC_DEF("603", CPU_POWERPC_603, 603),
+ POWERPC_DEF("603", CPU_POWERPC_603, 603),
/* Code name for PowerPC 603 */
- POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
- /* PowerPC 603e */
- POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
+ POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
+ /* PowerPC 603e (aka PID6) */
+ POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
/* Code name for PowerPC 603e */
- POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
+ POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
/* PowerPC 603e v1.1 */
- POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 603E),
+ POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
/* PowerPC 603e v1.2 */
- POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 603E),
+ POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
/* PowerPC 603e v1.3 */
- POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 603E),
+ POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
/* PowerPC 603e v1.4 */
- POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 603E),
+ POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
/* PowerPC 603e v2.2 */
- POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 603E),
+ POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
/* PowerPC 603e v3 */
- POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 603E),
+ POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
/* PowerPC 603e v4 */
- POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 603E),
+ POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
/* PowerPC 603e v4.1 */
- POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 603E),
- /* PowerPC 603e */
- POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
+ POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
+ /* PowerPC 603e (aka PID7) */
+ POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
/* PowerPC 603e7t */
- POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
+ POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
/* PowerPC 603e7v */
- POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
+ POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
/* Code name for PowerPC 603ev */
- POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
+ POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
/* PowerPC 603e7v1 */
- POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
+ POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
/* PowerPC 603e7v2 */
- POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
- /* PowerPC 603p */
- /* to be checked */
- POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
- /* PowerPC 603r */
- POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
+ POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
+ /* PowerPC 603p (aka PID7v) */
+ POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
+ /* PowerPC 603r (aka PID7t) */
+ POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
/* Code name for PowerPC 603r */
- POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
- /* PowerPC G2 core */
- POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
- /* PowerPC G2 H4 */
- POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
- /* PowerPC G2 GP */
- POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
- /* PowerPC G2 LS */
- POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
- /* PowerPC G2LE */
- /* Same as G2, with little-endian mode support */
- POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
- /* PowerPC G2LE GP */
- POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
- /* PowerPC G2LE LS */
- POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
+ POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
/* PowerPC 604 */
- POWERPC_DEF("604", CPU_POWERPC_604, 604),
- /* PowerPC 604e */
- /* XXX: code names "Sirocco" "Mach 5" */
- POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
+ POWERPC_DEF("604", CPU_POWERPC_604, 604),
+ /* PowerPC 604e (aka PID9) */
+ POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
+ /* Code name for PowerPC 604e */
+ POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
/* PowerPC 604e v1.0 */
- POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 604),
+ POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
/* PowerPC 604e v2.2 */
- POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 604),
+ POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
/* PowerPC 604e v2.4 */
- POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 604),
- /* PowerPC 604r */
- POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
+ POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
+ /* PowerPC 604r (aka PIDA) */
+ POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
+ /* Code name for PowerPC 604r */
+ POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
#if defined(TODO)
/* PowerPC 604ev */
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
+ POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
#endif
/* PowerPC 7xx family */
/* Generic PowerPC 740 (G3) */
- POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
+ POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
+ /* Code name for PowerPC 740 */
+ POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
/* Generic PowerPC 750 (G3) */
- POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
- /* Code name for generic PowerPC 740/750 (G3) */
- POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
- /* XXX: 750 codename "Typhoon" */
+ POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
+ /* Code name for PowerPC 750 */
+ POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 7x0),
/* PowerPC 740/750 is also known as G3 */
- POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
+ POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
/* PowerPC 740 v2.0 (G3) */
- POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 7x0),
+ POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
/* PowerPC 750 v2.0 (G3) */
- POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 7x0),
+ POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
/* PowerPC 740 v2.1 (G3) */
- POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 7x0),
+ POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
/* PowerPC 750 v2.1 (G3) */
- POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 7x0),
+ POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
/* PowerPC 740 v2.2 (G3) */
- POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 7x0),
+ POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
/* PowerPC 750 v2.2 (G3) */
- POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 7x0),
+ POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
/* PowerPC 740 v3.0 (G3) */
- POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 7x0),
+ POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
/* PowerPC 750 v3.0 (G3) */
- POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 7x0),
+ POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
/* PowerPC 740 v3.1 (G3) */
- POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 7x0),
+ POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
/* PowerPC 750 v3.1 (G3) */
- POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 7x0),
+ POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
/* PowerPC 740E (G3) */
- POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
+ POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
/* PowerPC 740P (G3) */
- POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
/* PowerPC 750P (G3) */
- POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
/* Code name for PowerPC 740P/750P (G3) */
- POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
/* PowerPC 750CL (G3 embedded) */
- POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
+ POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
/* PowerPC 750CX (G3 embedded) */
- POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
+ POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
/* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 7x0),
+ POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
/* PowerPC 750CX v2.2 (G3 embedded) */
- POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 7x0),
+ POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
/* PowerPC 750CXe (G3 embedded) */
- POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
+ POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
/* PowerPC 750CXe v2.1 (G3 embedded) */
- POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 7x0),
+ POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 7x0),
/* PowerPC 750CXe v2.2 (G3 embedded) */
- POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 7x0),
+ POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 7x0),
/* PowerPC 750CXe v2.3 (G3 embedded) */
- POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 7x0),
+ POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 7x0),
/* PowerPC 750CXe v2.4 (G3 embedded) */
- POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 7x0),
+ POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 7x0),
/* PowerPC 750CXe v2.4b (G3 embedded) */
- POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 7x0),
+ POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 7x0),
/* PowerPC 750CXe v3.1 (G3 embedded) */
- POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 7x0),
+ POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 7x0),
/* PowerPC 750CXe v3.1b (G3 embedded) */
- POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
+ POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
/* PowerPC 750CXr (G3 embedded) */
- POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
+ POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
/* PowerPC 750E (G3) */
- POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
+ POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
/* PowerPC 750FL (G3 embedded) */
- POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
+ POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
/* PowerPC 750FX (G3 embedded) */
- POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
+ POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
/* PowerPC 750FX v1.0 (G3 embedded) */
- POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 750fx),
+ POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
/* PowerPC 750FX v2.0 (G3 embedded) */
- POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 750fx),
+ POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
/* PowerPC 750FX v2.1 (G3 embedded) */
- POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 750fx),
+ POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
/* PowerPC 750FX v2.2 (G3 embedded) */
- POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 750fx),
+ POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
/* PowerPC 750FX v2.3 (G3 embedded) */
- POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 750fx),
+ POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
/* PowerPC 750GL (G3 embedded) */
- POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
+ POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
/* PowerPC 750GX (G3 embedded) */
- POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
+ POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
/* PowerPC 750GX v1.0 (G3 embedded) */
- POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 750fx),
+ POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
/* PowerPC 750GX v1.1 (G3 embedded) */
- POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 750fx),
+ POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
/* PowerPC 750GX v1.2 (G3 embedded) */
- POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 750fx),
+ POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
/* PowerPC 750L (G3 embedded) */
- POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
+ POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
/* Code name for PowerPC 750L (G3 embedded) */
- POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
+ POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
/* PowerPC 750L v2.2 (G3 embedded) */
- POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 7x0),
+ POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
/* PowerPC 750L v3.0 (G3 embedded) */
- POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 7x0),
+ POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
/* PowerPC 750L v3.2 (G3 embedded) */
- POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 7x0),
+ POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
/* Generic PowerPC 745 */
- POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
/* Generic PowerPC 755 */
- POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
/* Code name for PowerPC 745/755 */
- POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
/* PowerPC 745 v1.0 */
- POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 7x5),
+ POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
/* PowerPC 755 v1.0 */
- POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 7x5),
+ POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
/* PowerPC 745 v1.1 */
- POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 7x5),
+ POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
/* PowerPC 755 v1.1 */
- POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 7x5),
+ POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
/* PowerPC 745 v2.0 */
- POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 7x5),
+ POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
/* PowerPC 755 v2.0 */
- POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 7x5),
+ POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
/* PowerPC 745 v2.1 */
- POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 7x5),
+ POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
/* PowerPC 755 v2.1 */
- POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 7x5),
+ POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
/* PowerPC 745 v2.2 */
- POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 7x5),
+ POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
/* PowerPC 755 v2.2 */
- POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 7x5),
+ POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
/* PowerPC 745 v2.3 */
- POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 7x5),
+ POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
/* PowerPC 755 v2.3 */
- POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 7x5),
+ POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
/* PowerPC 745 v2.4 */
- POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 7x5),
+ POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
/* PowerPC 755 v2.4 */
- POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 7x5),
+ POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
/* PowerPC 745 v2.5 */
- POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 7x5),
+ POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
/* PowerPC 755 v2.5 */
- POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 7x5),
+ POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
/* PowerPC 745 v2.6 */
- POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 7x5),
+ POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
/* PowerPC 755 v2.6 */
- POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 7x5),
+ POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
/* PowerPC 745 v2.7 */
- POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 7x5),
+ POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
/* PowerPC 755 v2.7 */
- POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 7x5),
+ POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
/* PowerPC 745 v2.8 */
- POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 7x5),
+ POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
/* PowerPC 755 v2.8 */
- POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 7x5),
+ POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
#if defined (TODO)
/* PowerPC 745P (G3) */
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
+ POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
/* PowerPC 755P (G3) */
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
+ POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
#endif
/* PowerPC 74xx family */
/* PowerPC 7400 (G4) */
- POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
/* Code name for PowerPC 7400 */
- POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
/* PowerPC 74xx is also well known as G4 */
- POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
/* PowerPC 7400 v1.0 (G4) */
- POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 7400),
+ POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
/* PowerPC 7400 v1.1 (G4) */
- POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 7400),
+ POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
/* PowerPC 7400 v2.0 (G4) */
- POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 7400),
+ POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
/* PowerPC 7400 v2.2 (G4) */
- POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 7400),
+ POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
/* PowerPC 7400 v2.6 (G4) */
- POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 7400),
+ POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
/* PowerPC 7400 v2.7 (G4) */
- POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 7400),
+ POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
/* PowerPC 7400 v2.8 (G4) */
- POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 7400),
+ POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
/* PowerPC 7400 v2.9 (G4) */
- POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 7400),
+ POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
/* PowerPC 7410 (G4) */
- POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
+ POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
/* Code name for PowerPC 7410 */
- POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
+ POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
/* PowerPC 7410 v1.0 (G4) */
- POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 7410),
+ POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
/* PowerPC 7410 v1.1 (G4) */
- POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 7410),
+ POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
/* PowerPC 7410 v1.2 (G4) */
- POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 7410),
+ POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
/* PowerPC 7410 v1.3 (G4) */
- POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 7410),
+ POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
/* PowerPC 7410 v1.4 (G4) */
- POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 7410),
+ POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
/* PowerPC 7448 (G4) */
- POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
+ POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
/* PowerPC 7448 v1.0 (G4) */
- POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 7400),
+ POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
/* PowerPC 7448 v1.1 (G4) */
- POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 7400),
+ POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
/* PowerPC 7448 v2.0 (G4) */
- POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 7400),
+ POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
/* PowerPC 7448 v2.1 (G4) */
- POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 7400),
+ POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
/* PowerPC 7450 (G4) */
- POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
+ POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
/* Code name for PowerPC 7450 */
- POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
+ POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
/* PowerPC 7450 v1.0 (G4) */
- POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 7450),
+ POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
/* PowerPC 7450 v1.1 (G4) */
- POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 7450),
+ POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
/* PowerPC 7450 v1.2 (G4) */
- POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 7450),
+ POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
/* PowerPC 7450 v2.0 (G4) */
- POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 7450),
+ POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
/* PowerPC 7450 v2.1 (G4) */
- POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 7450),
+ POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
/* PowerPC 7441 (G4) */
- POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
+ POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
/* PowerPC 7451 (G4) */
- POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
+ POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
/* PowerPC 7441g (G4) */
- POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
+ POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
/* PowerPC 7451g (G4) */
- POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
+ POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
/* PowerPC 7445 (G4) */
- POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
+ POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
/* PowerPC 7455 (G4) */
- POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
+ POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
/* Code name for PowerPC 7445/7455 */
- POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
+ POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
/* PowerPC 7445 v1.0 (G4) */
- POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 7445),
+ POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
/* PowerPC 7455 v1.0 (G4) */
- POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 7455),
+ POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
/* PowerPC 7445 v2.1 (G4) */
- POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 7445),
+ POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
/* PowerPC 7455 v2.1 (G4) */
- POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 7455),
+ POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
/* PowerPC 7445 v3.2 (G4) */
- POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 7445),
+ POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
/* PowerPC 7455 v3.2 (G4) */
- POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 7455),
+ POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
/* PowerPC 7445 v3.3 (G4) */
- POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 7445),
+ POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
/* PowerPC 7455 v3.3 (G4) */
- POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 7455),
+ POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
/* PowerPC 7445 v3.4 (G4) */
- POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 7445),
+ POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
/* PowerPC 7455 v3.4 (G4) */
- POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 7455),
+ POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
/* PowerPC 7447 (G4) */
- POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
+ POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
/* PowerPC 7457 (G4) */
- POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
+ POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
/* Code name for PowerPC 7447/7457 */
- POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
+ POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
/* PowerPC 7447 v1.0 (G4) */
- POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 7445),
+ POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
/* PowerPC 7457 v1.0 (G4) */
- POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 7455),
- /* Code name for PowerPC 7447A/7457A */
- POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
+ POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
/* PowerPC 7447 v1.1 (G4) */
- POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 7445),
+ POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
/* PowerPC 7457 v1.1 (G4) */
- POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 7455),
+ POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
/* PowerPC 7447 v1.2 (G4) */
- POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 7445),
+ POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
/* PowerPC 7457 v1.2 (G4) */
- POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 7455),
+ POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
+ /* PowerPC 7447A (G4) */
+ POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
+ /* PowerPC 7457A (G4) */
+ POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
+ /* PowerPC 7447A v1.0 (G4) */
+ POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
+ /* PowerPC 7457A v1.0 (G4) */
+ POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
+ /* Code name for PowerPC 7447A/7457A */
+ POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
+ /* PowerPC 7447A v1.1 (G4) */
+ POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
+ /* PowerPC 7457A v1.1 (G4) */
+ POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
+ /* PowerPC 7447A v1.2 (G4) */
+ POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
+ /* PowerPC 7457A v1.2 (G4) */
+ POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
/* PowerPC 620 */
- /* XXX: code name "Trident" */
- POWERPC_DEF("620", CPU_POWERPC_620, 620),
+ POWERPC_DEF("620", CPU_POWERPC_620, 620),
+ /* Code name for PowerPC 620 */
+ POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
#if defined (TODO)
/* PowerPC 630 (POWER3) */
- /* XXX: code names: "Boxer" "Dino" */
- POWERPC_DEF("630", CPU_POWERPC_630, 630),
- POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
+ POWERPC_DEF("630", CPU_POWERPC_630, 630),
+ POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
+ /* Code names for POWER3 */
+ POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
+ POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
#endif
#if defined (TODO)
/* PowerPC 631 (Power 3+) */
- POWERPC_DEF("631", CPU_POWERPC_631, 631),
- POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
+ POWERPC_DEF("631", CPU_POWERPC_631, 631),
+ POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
#endif
#if defined (TODO)
/* POWER4 */
- POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
+ POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
#endif
#if defined (TODO)
/* POWER4p */
- POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
+ POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
#endif
#if defined (TODO)
/* POWER5 */
- POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
+ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
/* POWER5GR */
- POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
+ POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
#endif
#if defined (TODO)
/* POWER5+ */
- POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
+ POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
/* POWER5GS */
- POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
+ POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
#endif
#if defined (TODO)
/* POWER6 */
- POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
+ POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
/* POWER6 running in POWER5 mode */
- POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
+ POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
/* POWER6A */
- POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
+ POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
#endif
/* PowerPC 970 */
- POWERPC_DEF("970", CPU_POWERPC_970, 970),
+ POWERPC_DEF("970", CPU_POWERPC_970, 970),
/* PowerPC 970FX (G5) */
- POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
+ POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
/* PowerPC 970FX v1.0 (G5) */
- POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 970FX),
+ POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
/* PowerPC 970FX v2.0 (G5) */
- POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 970FX),
+ POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
/* PowerPC 970FX v2.1 (G5) */
- POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 970FX),
+ POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
/* PowerPC 970FX v3.0 (G5) */
- POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 970FX),
+ POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
/* PowerPC 970FX v3.1 (G5) */
- POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 970FX),
+ POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
/* PowerPC 970GX (G5) */
- POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
+ POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
/* PowerPC 970MP */
- POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
+ POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
/* PowerPC 970MP v1.0 */
- POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 970MP),
+ POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
/* PowerPC 970MP v1.1 */
- POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 970MP),
+ POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
#if defined (TODO)
/* PowerPC Cell */
- POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
+ POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
#endif
#if defined (TODO)
/* PowerPC Cell v1.0 */
- POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 970),
+ POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
#endif
#if defined (TODO)
/* PowerPC Cell v2.0 */
- POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 970),
+ POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
#endif
#if defined (TODO)
/* PowerPC Cell v3.0 */
- POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 970),
+ POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
#endif
#if defined (TODO)
/* PowerPC Cell v3.1 */
- POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 970),
+ POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
#endif
#if defined (TODO)
/* PowerPC Cell v3.2 */
- POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 970),
+ POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
#endif
#if defined (TODO)
/* RS64 (Apache/A35) */
@@ -6127,59 +8037,57 @@
* and the PowerPC 64 one.
*/
/* What about A10 & A30 ? */
- POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
- POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
- POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
+ POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
+ POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
+ POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
#endif
#if defined (TODO)
/* RS64-II (NorthStar/A50) */
- POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
- POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
- POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
+ POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
+ POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
+ POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
#endif
#if defined (TODO)
/* RS64-III (Pulsar) */
- POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
- POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
+ POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
+ POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
#endif
#if defined (TODO)
/* RS64-IV (IceStar/IStar/SStar) */
- POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
+ POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
+ POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
+ POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
+ POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
#if defined (TODO)
/* Original POWER */
- POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
#endif
#if defined (TODO)
/* POWER2 */
- POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
- POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
- POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
+ POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
+ POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
+ POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
#endif
/* PA semi cores */
#if defined (TODO)
/* PA PA6T */
- POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
+ POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
#endif
/* Generic PowerPCs */
#if defined (TARGET_PPC64)
-#if defined (TODO)
- POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
+ POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
#endif
-#endif
- POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
- POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
+ POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
+ POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
/* Fallback */
- POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
+ POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
};
/*****************************************************************************/
@@ -6207,6 +8115,20 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
def->pvr);
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (def->svr != POWERPC_SVR_NONE) {
+ if (def->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ def->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ def->svr);
+ }
+ }
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*def->init_proc)(env);
/* MSR bits & flags consistency checks */
@@ -6290,6 +8212,11 @@
"Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
exit(1);
}
+ if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
+ fprintf(stderr, "PowerPC flags inconsistency\n"
+ "Should define the time-base and decrementer clock source\n");
+ exit(1);
+ }
/* Allocate TLBs buffer when needed */
#if !defined(CONFIG_USER_ONLY)
if (env->nb_tlb != 0) {
@@ -6413,6 +8340,10 @@
if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
printf("*** ERROR: opcode %02x already assigned in main "
"opcode table\n", idx);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ppc_opcodes[idx]->oname, handler->oname);
+#endif
return -1;
}
@@ -6433,6 +8364,10 @@
if (!is_indirect_opcode(table[idx1])) {
printf("*** ERROR: idx %02x already assigned to a direct "
"opcode\n", idx1);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ind_table(table[idx1])[idx2]->oname, handler->oname);
+#endif
return -1;
}
}
@@ -6440,6 +8375,10 @@
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
printf("*** ERROR: opcode %02x already assigned in "
"opcode table %02x\n", idx2, idx1);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ind_table(table[idx1])[idx2]->oname, handler->oname);
+#endif
return -1;
}
@@ -6562,6 +8501,7 @@
static void dump_ppc_insns (CPUPPCState *env)
{
opc_handler_t **table, *handler;
+ const unsigned char *p, *q;
uint8_t opc1, opc2, opc3;
printf("Instructions set:\n");
@@ -6582,9 +8522,35 @@
for (opc3 = 0; opc3 < 0x20; opc3++) {
handler = table[opc3];
if (handler->handler != &gen_invalid) {
- printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
- opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
- handler->oname);
+ /* Special hack to properly dump SPE insns */
+ p = strchr(handler->oname, '_');
+ if (p == NULL) {
+ printf("INSN: %02x %02x %02x (%02d %04d) : "
+ "%s\n",
+ opc1, opc2, opc3, opc1,
+ (opc3 << 5) | opc2,
+ handler->oname);
+ } else {
+ q = "speundef";
+ if ((p - handler->oname) != strlen(q) ||
+ memcmp(handler->oname, q, strlen(q)) != 0) {
+ /* First instruction */
+ printf("INSN: %02x %02x %02x (%02d %04d) : "
+ "%.*s\n",
+ opc1, opc2 << 1, opc3, opc1,
+ (opc3 << 6) | (opc2 << 1),
+ (int)(p - handler->oname),
+ handler->oname);
+ }
+ if (strcmp(p + 1, q) != 0) {
+ /* Second instruction */
+ printf("INSN: %02x %02x %02x (%02d %04d) : "
+ "%s\n",
+ opc1, (opc2 << 1) | 1, opc3, opc1,
+ (opc3 << 6) | (opc2 << 1) | 1,
+ p + 1);
+ }
+ }
}
}
} else {
@@ -6636,19 +8602,28 @@
mmu_model = "PowerPC 4xx with software driven TLBs "
"and zones protections";
break;
- case POWERPC_MMU_REAL_4xx:
- mmu_model = "PowerPC 4xx real mode only";
+ case POWERPC_MMU_REAL:
+ mmu_model = "PowerPC real mode only";
break;
+ case POWERPC_MMU_MPC8xx:
+ mmu_model = "PowerPC MPC8xx";
+ break;
case POWERPC_MMU_BOOKE:
mmu_model = "PowerPC BookE";
break;
case POWERPC_MMU_BOOKE_FSL:
mmu_model = "PowerPC BookE FSL";
break;
+ case POWERPC_MMU_601:
+ mmu_model = "PowerPC 601";
+ break;
#if defined (TARGET_PPC64)
case POWERPC_MMU_64B:
mmu_model = "PowerPC 64";
break;
+ case POWERPC_MMU_620:
+ mmu_model = "PowerPC 620";
+ break;
#endif
default:
mmu_model = "Unknown or invalid";
@@ -6710,6 +8685,9 @@
case PPC_FLAGS_INPUT_401:
bus_model = "PowerPC 401/403";
break;
+ case PPC_FLAGS_INPUT_RCPU:
+ bus_model = "RCPU / MPC8xx";
+ break;
#if defined (TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
bus_model = "PowerPC 970";
@@ -6758,6 +8736,8 @@
printf(" performance monitor mark\n");
if (env->flags == POWERPC_FLAG_NONE)
printf(" none\n");
+ printf(" Time-base/decrementer clock source: %s\n",
+ env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
}
dump_ppc_insns(env);
dump_ppc_sprs(env);
@@ -6790,7 +8770,7 @@
match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
/* We check '>=' instead of '>' because the PPC_defs table
* is ordered by increasing revision.
- * Then, we will match the higher revision compatible
+ * Then, we will match the higher revision compatible
* with the requested PVR
*/
if (match >= best_match) {
Modified: trunk/src/host/qemu-neo1973/target-sparc/helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-sparc/helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-sparc/helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -604,3 +604,34 @@
dst[6] = src[6];
dst[7] = src[7];
}
+
+#ifdef TARGET_SPARC64
+#if !defined(CONFIG_USER_ONLY)
+#include "qemu-common.h"
+#include "hw/irq.h"
+#include "qemu-timer.h"
+#endif
+
+void do_tick_set_count(void *opaque, uint64_t count)
+{
+#if !defined(CONFIG_USER_ONLY)
+ ptimer_set_count(opaque, -count);
+#endif
+}
+
+uint64_t do_tick_get_count(void *opaque)
+{
+#if !defined(CONFIG_USER_ONLY)
+ return -ptimer_get_count(opaque);
+#else
+ return 0;
+#endif
+}
+
+void do_tick_set_limit(void *opaque, uint64_t limit)
+{
+#if !defined(CONFIG_USER_ONLY)
+ ptimer_set_limit(opaque, -limit, 0);
+#endif
+}
+#endif
Modified: trunk/src/host/qemu-neo1973/target-sparc/op_helper.c
===================================================================
--- trunk/src/host/qemu-neo1973/target-sparc/op_helper.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/target-sparc/op_helper.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -207,6 +207,14 @@
else
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
break;
+ case 0x01c00c00: /* Module reset register */
+ if (size == 8) {
+ ret = env->mxccregs[5] >> 32;
+ T0 = env->mxccregs[5];
+ // should we do something here?
+ } else
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ break;
case 0x01c00f00: /* MBus port address register */
if (size == 8) {
ret = env->mxccregs[7];
@@ -263,7 +271,7 @@
case 8:
tmp = ldq_code(T0 & ~7);
ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ T0 = tmp;
break;
}
break;
@@ -282,7 +290,7 @@
case 8:
tmp = ldq_user(T0 & ~7);
ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ T0 = tmp;
break;
}
break;
@@ -301,7 +309,7 @@
case 8:
tmp = ldq_kernel(T0 & ~7);
ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ T0 = tmp;
break;
}
break;
@@ -325,7 +333,7 @@
case 8:
tmp = ldq_phys(T0 & ~7);
ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ T0 = tmp;
break;
}
break;
@@ -349,7 +357,7 @@
tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
| ((target_phys_addr_t)(asi & 0xf) << 32));
ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ T0 = tmp;
break;
}
break;
@@ -438,13 +446,11 @@
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
break;
case 0x01c00e00: /* MXCC error register */
+ // writing a 1 bit clears the error
if (size == 8)
- env->mxccregs[6] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
else
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
- if (env->mxccregs[6] == 0xffffffffffffffffULL) {
- // this is probably a reset
- }
break;
case 0x01c00f00: /* MBus port address register */
if (size == 8)
@@ -1798,27 +1804,3 @@
}
#endif
-#ifdef TARGET_SPARC64
-void do_tick_set_count(void *opaque, uint64_t count)
-{
-#if !defined(CONFIG_USER_ONLY)
- ptimer_set_count(opaque, -count);
-#endif
-}
-
-uint64_t do_tick_get_count(void *opaque)
-{
-#if !defined(CONFIG_USER_ONLY)
- return -ptimer_get_count(opaque);
-#else
- return 0;
-#endif
-}
-
-void do_tick_set_limit(void *opaque, uint64_t limit)
-{
-#if !defined(CONFIG_USER_ONLY)
- ptimer_set_limit(opaque, -limit, 0);
-#endif
-}
-#endif
Modified: trunk/src/host/qemu-neo1973/tests/Makefile
===================================================================
--- trunk/src/host/qemu-neo1973/tests/Makefile 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/tests/Makefile 2007-11-19 18:54:17 UTC (rev 3443)
@@ -92,13 +92,6 @@
hello-mipsel: hello-mips.c
mipsel-linux-gnu-gcc -nostdlib -static -mno-abicalls -fno-PIC -mabi=32 -Wall -Wextra -g -O2 -o $@ $<
-# XXX: find a way to compile easily a test for each arch
-test2:
- @for arch in i386 arm armeb sparc ppc mips mipsel; do \
- ../$${arch}-linux-user/qemu-$${arch} $${arch}/ls -l linux-test.c ; \
- done
-
-
# testsuite for the CRIS port.
test-cris:
$(MAKE) -C cris check
Modified: trunk/src/host/qemu-neo1973/thunk.c
===================================================================
--- trunk/src/host/qemu-neo1973/thunk.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/thunk.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -31,6 +31,8 @@
/* XXX: make it dynamic */
StructEntry struct_entries[MAX_STRUCTS];
+static const argtype *thunk_type_next_ptr(const argtype *type_ptr);
+
static inline const argtype *thunk_type_next(const argtype *type_ptr)
{
int type;
@@ -47,9 +49,9 @@
case TYPE_PTRVOID:
return type_ptr;
case TYPE_PTR:
- return thunk_type_next(type_ptr);
+ return thunk_type_next_ptr(type_ptr);
case TYPE_ARRAY:
- return thunk_type_next(type_ptr + 1);
+ return thunk_type_next_ptr(type_ptr + 1);
case TYPE_STRUCT:
return type_ptr + 1;
default:
@@ -57,6 +59,11 @@
}
}
+static const argtype *thunk_type_next_ptr(const argtype *type_ptr)
+{
+ return thunk_type_next(type_ptr);
+}
+
void thunk_register_struct(int id, const char *name, const argtype *types)
{
const argtype *type_ptr;
@@ -267,3 +274,15 @@
}
return(x86_mask);
}
+
+#ifndef NO_THUNK_TYPE_SIZE
+int thunk_type_size_array(const argtype *type_ptr, int is_host)
+{
+ return thunk_type_size(type_ptr, is_host);
+}
+
+int thunk_type_align_array(const argtype *type_ptr, int is_host)
+{
+ return thunk_type_align(type_ptr, is_host);
+}
+#endif /* ndef NO_THUNK_TYPE_SIZE */
Modified: trunk/src/host/qemu-neo1973/thunk.h
===================================================================
--- trunk/src/host/qemu-neo1973/thunk.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/thunk.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -75,6 +75,9 @@
extern StructEntry struct_entries[];
+int thunk_type_size_array(const argtype *type_ptr, int is_host);
+int thunk_type_align_array(const argtype *type_ptr, int is_host);
+
static inline int thunk_type_size(const argtype *type_ptr, int is_host)
{
int type, size;
@@ -103,7 +106,7 @@
break;
case TYPE_ARRAY:
size = type_ptr[1];
- return size * thunk_type_size(type_ptr + 2, is_host);
+ return size * thunk_type_size_array(type_ptr + 2, is_host);
case TYPE_STRUCT:
se = struct_entries + type_ptr[1];
return se->size[is_host];
@@ -139,7 +142,7 @@
}
break;
case TYPE_ARRAY:
- return thunk_type_align(type_ptr + 2, is_host);
+ return thunk_type_align_array(type_ptr + 2, is_host);
case TYPE_STRUCT:
se = struct_entries + type_ptr[1];
return se->align[is_host];
Modified: trunk/src/host/qemu-neo1973/translate-all.c
===================================================================
--- trunk/src/host/qemu-neo1973/translate-all.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/translate-all.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -264,7 +264,8 @@
#else
#define CASE3(op)\
case INDEX_op_ ## op ## _user:\
- case INDEX_op_ ## op ## _kernel
+ case INDEX_op_ ## op ## _kernel:\
+ case INDEX_op_ ## op ## _hypv
#endif
CASE3(stfd):
Modified: trunk/src/host/qemu-neo1973/translate-op.c
===================================================================
--- trunk/src/host/qemu-neo1973/translate-op.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/translate-op.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -24,6 +24,7 @@
#include <inttypes.h>
#include "config.h"
+#include "osdep.h"
enum {
#define DEF(s, n, copy_size) INDEX_op_ ## s,
@@ -33,5 +34,8 @@
};
#include "dyngen.h"
+extern int dyngen_code(uint8_t *gen_code_buf,
+ uint16_t *label_offsets, uint16_t *jmp_offsets,
+ const uint16_t *opc_buf, const uint32_t *opparam_buf, const long *gen_labels);
#include "op.h"
Modified: trunk/src/host/qemu-neo1973/usb-linux-gadget.c
===================================================================
--- trunk/src/host/qemu-neo1973/usb-linux-gadget.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/usb-linux-gadget.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -34,7 +34,10 @@
# include <signal.h>
/* Must be after usb_ch9.h */
-# include "vl.h"
+# include "qemu-common.h"
+# include "qemu-char.h"
+# include "sysemu.h"
+# include "hw/usb.h"
# define USBGADGETFS_PATH "/dev/gadget"
@@ -811,7 +814,7 @@
}
#else
-# include "vl.h"
+# include "hw/usb.h"
int usb_gadget_init(void)
{
Modified: trunk/src/host/qemu-neo1973/usb-linux.c
===================================================================
--- trunk/src/host/qemu-neo1973/usb-linux.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/usb-linux.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "hw/usb.h"
+#include "console.h"
#if defined(__linux__)
#include <dirent.h>
@@ -905,10 +907,10 @@
return p->class_name;
}
-void usb_info_device(int bus_num, int addr, int class_id,
- int vendor_id, int product_id,
- const char *product_name,
- int speed)
+static void usb_info_device(int bus_num, int addr, int class_id,
+ int vendor_id, int product_id,
+ const char *product_name,
+ int speed)
{
const char *class_str, *speed_str;
Modified: trunk/src/host/qemu-neo1973/vl.c
===================================================================
--- trunk/src/host/qemu-neo1973/vl.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/vl.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,22 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw/hw.h"
+#include "hw/boards.h"
+#include "hw/usb.h"
+#include "hw/pcmcia.h"
+#include "hw/pc.h"
+#include "hw/fdc.h"
+#include "hw/audiodev.h"
+#include "hw/isa.h"
+#include "net.h"
+#include "console.h"
+#include "sysemu.h"
+#include "gdbstub.h"
+#include "qemu-timer.h"
+#include "qemu-char.h"
+#include "block.h"
+#include "audio/audio.h"
#include <unistd.h>
#include <fcntl.h>
@@ -229,7 +244,7 @@
target_phys_addr_t isa_mem_base = 0;
PicState2 *isa_pic;
-uint32_t default_ioport_readb(void *opaque, uint32_t address)
+static uint32_t default_ioport_readb(void *opaque, uint32_t address)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused inb: port=0x%04x\n", address);
@@ -237,7 +252,7 @@
return 0xff;
}
-void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
+static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused outb: port=0x%04x data=0x%02x\n", address, data);
@@ -245,7 +260,7 @@
}
/* default is to make two byte accesses */
-uint32_t default_ioport_readw(void *opaque, uint32_t address)
+static uint32_t default_ioport_readw(void *opaque, uint32_t address)
{
uint32_t data;
data = ioport_read_table[0][address](ioport_opaque[address], address);
@@ -254,14 +269,14 @@
return data;
}
-void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
+static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
{
ioport_write_table[0][address](ioport_opaque[address], address, data & 0xff);
address = (address + 1) & (MAX_IOPORTS - 1);
ioport_write_table[0][address](ioport_opaque[address], address, (data >> 8) & 0xff);
}
-uint32_t default_ioport_readl(void *opaque, uint32_t address)
+static uint32_t default_ioport_readl(void *opaque, uint32_t address)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused inl: port=0x%04x\n", address);
@@ -269,14 +284,14 @@
return 0xffffffff;
}
-void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
+static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused outl: port=0x%04x data=0x%02x\n", address, data);
#endif
}
-void init_ioports(void)
+static void init_ioports(void)
{
int i;
@@ -948,7 +963,7 @@
static QEMUTimer *active_timers[2];
-QEMUClock *qemu_new_clock(int type)
+static QEMUClock *qemu_new_clock(int type)
{
QEMUClock *clock;
clock = qemu_mallocz(sizeof(QEMUClock));
@@ -1526,7 +1541,7 @@
alarm_timer = t;
}
-void quit_timers(void)
+static void quit_timers(void)
{
alarm_timer->stop(alarm_timer);
alarm_timer = NULL;
@@ -1819,7 +1834,7 @@
d->mux_cnt++;
}
-CharDriverState *qemu_chr_open_mux(CharDriverState *drv)
+static CharDriverState *qemu_chr_open_mux(CharDriverState *drv)
{
CharDriverState *chr;
MuxDriver *d;
@@ -3372,7 +3387,8 @@
/***********************************************************/
/* network device redirectors */
-void hex_dump(FILE *f, const uint8_t *buf, int size)
+__attribute__ (( unused ))
+static void hex_dump(FILE *f, const uint8_t *buf, int size)
{
int len, i, j, c;
@@ -3720,7 +3736,7 @@
}
/* automatic user mode samba server configuration */
-void net_slirp_smb(const char *exported_dir)
+static void net_slirp_smb(const char *exported_dir)
{
char smb_conf[1024];
char smb_cmdline[1024];
@@ -5340,7 +5356,7 @@
return NULL;
}
-QEMUFile *qemu_fopen_bdrv(BlockDriverState *bs, int64_t offset, int is_writable)
+static QEMUFile *qemu_fopen_bdrv(BlockDriverState *bs, int64_t offset, int is_writable)
{
QEMUFile *f;
@@ -5574,7 +5590,7 @@
#define QEMU_VM_FILE_MAGIC 0x5145564d
#define QEMU_VM_FILE_VERSION 0x00000002
-int qemu_savevm_state(QEMUFile *f)
+static int qemu_savevm_state(QEMUFile *f)
{
SaveStateEntry *se;
int len, ret;
@@ -5597,7 +5613,6 @@
/* record size: filled later */
len_pos = qemu_ftell(f);
qemu_put_be32(f, 0);
-
se->save_state(f, se->opaque);
/* fill record size */
@@ -5628,7 +5643,7 @@
return NULL;
}
-int qemu_loadvm_state(QEMUFile *f)
+static int qemu_loadvm_state(QEMUFile *f)
{
SaveStateEntry *se;
int len, ret, instance_id, record_len, version_id;
@@ -6857,7 +6872,7 @@
return 0;
}
-QEMUMachine *find_machine(const char *name)
+static QEMUMachine *find_machine(const char *name)
{
QEMUMachine *m;
@@ -6871,7 +6886,7 @@
/***********************************************************/
/* main execution loop */
-void gui_update(void *opaque)
+static void gui_update(void *opaque)
{
DisplayState *ds = opaque;
ds->dpy_refresh(ds);
@@ -7155,7 +7170,7 @@
static CPUState *cur_cpu;
-int main_loop(void)
+static int main_loop(void)
{
int ret, timeout;
#ifdef CONFIG_PROFILER
@@ -7619,7 +7634,7 @@
}
/* XXX: currently we cannot use simultaneously different CPUs */
-void register_machines(void)
+static void register_machines(void)
{
#if defined(TARGET_I386)
qemu_register_machine(&pc_machine);
@@ -7656,6 +7671,7 @@
qemu_register_machine(&palmte_machine);
qemu_register_machine(&lm3s811evb_machine);
qemu_register_machine(&lm3s6965evb_machine);
+ qemu_register_machine(&connex_machine);
#elif defined(TARGET_SH4)
qemu_register_machine(&shix_machine);
qemu_register_machine(&r2d_machine);
@@ -8490,20 +8506,21 @@
kqemu_allowed = 0;
#endif
linux_boot = (kernel_filename != NULL);
- net_boot = (boot_devices_bitmap >> ('n' - 'a')) && 0xF;
-
+ net_boot = (boot_devices_bitmap >> ('n' - 'a')) & 0xF;
+
/* XXX: this should not be: some embedded targets just have flash */
if (!linux_boot && net_boot == 0 &&
- hd_filename[0] == '\0' &&
- (cdrom_index >= 0 && hd_filename[cdrom_index] == '\0') &&
- fd_filename[0] == '\0')
+ hd_filename[0] == NULL &&
+ (cdrom_index >= 0 && hd_filename[cdrom_index] == NULL) &&
+ fd_filename[0] == NULL &&
+ pflash_filename[0] == NULL)
help(1);
/* boot to floppy or the default cd if no hard disk defined yet */
if (!boot_devices[0]) {
- if (hd_filename[0] != '\0')
+ if (hd_filename[0] != NULL)
boot_devices = "c";
- else if (fd_filename[0] != '\0')
+ else if (fd_filename[0] != NULL)
boot_devices = "a";
else
boot_devices = "d";
@@ -8694,6 +8711,8 @@
sdl_display_init(ds, full_screen, no_frame);
#elif defined(CONFIG_COCOA)
cocoa_display_init(ds, full_screen);
+#else
+ dumb_display_init(ds);
#endif
}
@@ -8749,8 +8768,7 @@
local_piconet = qemu_mallocz(sizeof(struct bt_piconet_s));
- machine->init(ram_size, vga_ram_size, boot_devices,
- ds, fd_filename, snapshot,
+ machine->init(ram_size, vga_ram_size, boot_devices, ds,
kernel_filename, kernel_cmdline, initrd_filename, cpu_model);
/* init USB devices */
Deleted: trunk/src/host/qemu-neo1973/vl.h
===================================================================
--- trunk/src/host/qemu-neo1973/vl.h 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/vl.h 2007-11-19 18:54:17 UTC (rev 3443)
@@ -1,1572 +0,0 @@
-/*
- * QEMU System Emulator header
- *
- * Copyright (c) 2003 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#ifndef VL_H
-#define VL_H
-
-#include "qemu-common.h"
-
-/* FIXME: Remove this. */
-#include "block.h"
-
-#ifndef glue
-#define xglue(x, y) x ## y
-#define glue(x, y) xglue(x, y)
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-#endif
-
-#ifndef likely
-#if __GNUC__ < 3
-#define __builtin_expect(x, n) (x)
-#endif
-
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#endif
-
-#ifndef MIN
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-#ifndef MAX
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-#endif
-
-#ifndef always_inline
-#if (__GNUC__ < 3) || defined(__APPLE__)
-#define always_inline inline
-#else
-#define always_inline __attribute__ (( always_inline )) inline
-#endif
-#endif
-
-#include "audio/audio.h"
-
-/* vl.c */
-uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
-
-void hw_error(const char *fmt, ...);
-
-extern const char *bios_dir;
-extern const char *bios_name;
-
-extern int vm_running;
-extern const char *qemu_name;
-
-typedef struct vm_change_state_entry VMChangeStateEntry;
-typedef void VMChangeStateHandler(void *opaque, int running);
-typedef void VMStopHandler(void *opaque, int reason);
-
-VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
- void *opaque);
-void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
-
-int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
-void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
-
-void vm_start(void);
-void vm_stop(int reason);
-
-typedef void QEMUResetHandler(void *opaque);
-
-void qemu_register_reset(QEMUResetHandler *func, void *opaque);
-void qemu_system_reset_request(void);
-void qemu_system_shutdown_request(void);
-void qemu_system_powerdown_request(void);
-#if !defined(TARGET_SPARC)
-// Please implement a power failure function to signal the OS
-#define qemu_system_powerdown() do{}while(0)
-#else
-void qemu_system_powerdown(void);
-#endif
-
-void main_loop_wait(int timeout);
-
-extern int ram_size;
-extern int bios_size;
-extern int rtc_utc;
-extern int rtc_start_date;
-extern int cirrus_vga_enabled;
-extern int vmsvga_enabled;
-extern int graphic_width;
-extern int graphic_height;
-extern int graphic_depth;
-extern const char *keyboard_layout;
-extern int kqemu_allowed;
-extern int win2k_install_hack;
-extern int alt_grab;
-extern int usb_enabled;
-extern int smp_cpus;
-extern int cursor_hide;
-extern int graphic_rotate;
-extern int no_quit;
-extern int semihosting_enabled;
-extern int autostart;
-extern int old_param;
-extern const char *bootp_filename;
-
-#define MAX_OPTION_ROMS 16
-extern const char *option_rom[MAX_OPTION_ROMS];
-extern int nb_option_roms;
-
-#ifdef TARGET_SPARC
-#define MAX_PROM_ENVS 128
-extern const char *prom_envs[MAX_PROM_ENVS];
-extern unsigned int nb_prom_envs;
-#endif
-
-/* XXX: make it dynamic */
-#define MAX_BIOS_SIZE (4 * 1024 * 1024)
-#if defined (TARGET_PPC)
-#define BIOS_SIZE (1024 * 1024)
-#elif defined (TARGET_SPARC64)
-#define BIOS_SIZE ((512 + 32) * 1024)
-#elif defined(TARGET_MIPS)
-#define BIOS_SIZE (4 * 1024 * 1024)
-#endif
-
-/* keyboard/mouse support */
-
-#define MOUSE_EVENT_LBUTTON 0x01
-#define MOUSE_EVENT_RBUTTON 0x02
-#define MOUSE_EVENT_MBUTTON 0x04
-
-typedef void QEMUPutKBDEvent(void *opaque, int keycode);
-typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
-
-typedef struct QEMUPutMouseEntry {
- QEMUPutMouseEvent *qemu_put_mouse_event;
- void *qemu_put_mouse_event_opaque;
- int qemu_put_mouse_event_absolute;
- char *qemu_put_mouse_event_name;
-
- /* used internally by qemu for handling mice */
- struct QEMUPutMouseEntry *next;
-} QEMUPutMouseEntry;
-
-void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
-QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
- void *opaque, int absolute,
- const char *name);
-void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
-
-void kbd_put_keycode(int keycode);
-void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
-int kbd_mouse_is_absolute(void);
-
-void do_info_mice(void);
-void do_mouse_set(int index);
-
-/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
- constants) */
-#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
-#define QEMU_KEY_BACKSPACE 0x007f
-#define QEMU_KEY_UP QEMU_KEY_ESC1('A')
-#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
-#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
-#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
-#define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
-#define QEMU_KEY_END QEMU_KEY_ESC1(4)
-#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
-#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
-#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
-
-#define QEMU_KEY_CTRL_UP 0xe400
-#define QEMU_KEY_CTRL_DOWN 0xe401
-#define QEMU_KEY_CTRL_LEFT 0xe402
-#define QEMU_KEY_CTRL_RIGHT 0xe403
-#define QEMU_KEY_CTRL_HOME 0xe404
-#define QEMU_KEY_CTRL_END 0xe405
-#define QEMU_KEY_CTRL_PAGEUP 0xe406
-#define QEMU_KEY_CTRL_PAGEDOWN 0xe407
-
-void kbd_put_keysym(int keysym);
-
-/* async I/O support */
-
-typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
-typedef int IOCanRWHandler(void *opaque);
-typedef void IOHandler(void *opaque);
-
-int qemu_set_fd_handler2(int fd,
- IOCanRWHandler *fd_read_poll,
- IOHandler *fd_read,
- IOHandler *fd_write,
- void *opaque);
-int qemu_set_fd_handler(int fd,
- IOHandler *fd_read,
- IOHandler *fd_write,
- void *opaque);
-
-/* Polling handling */
-
-/* return TRUE if no sleep should be done afterwards */
-typedef int PollingFunc(void *opaque);
-
-int qemu_add_polling_cb(PollingFunc *func, void *opaque);
-void qemu_del_polling_cb(PollingFunc *func, void *opaque);
-
-#ifdef _WIN32
-/* Wait objects handling */
-typedef void WaitObjectFunc(void *opaque);
-
-int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
-void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
-#endif
-
-/* character device */
-
-#define CHR_EVENT_BREAK 0 /* serial break char */
-#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
-#define CHR_EVENT_RESET 2 /* new connection established */
-
-
-#define CHR_IOCTL_SERIAL_SET_PARAMS 1
-typedef struct {
- int speed;
- int parity;
- int data_bits;
- int stop_bits;
-} QEMUSerialSetParams;
-
-#define CHR_IOCTL_SERIAL_SET_BREAK 2
-
-#define CHR_IOCTL_PP_READ_DATA 3
-#define CHR_IOCTL_PP_WRITE_DATA 4
-#define CHR_IOCTL_PP_READ_CONTROL 5
-#define CHR_IOCTL_PP_WRITE_CONTROL 6
-#define CHR_IOCTL_PP_READ_STATUS 7
-#define CHR_IOCTL_PP_EPP_READ_ADDR 8
-#define CHR_IOCTL_PP_EPP_READ 9
-#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
-#define CHR_IOCTL_PP_EPP_WRITE 11
-
-#define CHR_IOCTL_MODEM_HANDSHAKE 12
-
-typedef void IOEventHandler(void *opaque, int event);
-
-typedef struct CharDriverState {
- int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
- void (*chr_update_read_handler)(struct CharDriverState *s);
- int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
- IOEventHandler *chr_event;
- IOCanRWHandler *chr_can_read;
- IOReadHandler *chr_read;
- void *handler_opaque;
- void (*chr_send_event)(struct CharDriverState *chr, int event);
- void (*chr_close)(struct CharDriverState *chr);
- void *opaque;
- int focus;
- QEMUBH *bh;
-} CharDriverState;
-
-CharDriverState *qemu_chr_open(const char *filename);
-void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
-int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
-void qemu_chr_send_event(CharDriverState *s, int event);
-void qemu_chr_add_handlers(CharDriverState *s,
- IOCanRWHandler *fd_can_read,
- IOReadHandler *fd_read,
- IOEventHandler *fd_event,
- void *opaque);
-int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
-void qemu_chr_reset(CharDriverState *s);
-int qemu_chr_can_read(CharDriverState *s);
-void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
-
-/* consoles */
-
-typedef struct DisplayState DisplayState;
-typedef struct TextConsole TextConsole;
-
-struct DisplayState {
- uint8_t *data;
- int linesize;
- int depth;
- int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
- int width;
- int height;
- void *opaque;
- struct QEMUTimer *gui_timer;
-
- void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
- void (*dpy_resize)(struct DisplayState *s, int w, int h);
- void (*dpy_refresh)(struct DisplayState *s);
- void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
- int dst_x, int dst_y, int w, int h);
- void (*dpy_fill)(struct DisplayState *s, int x, int y,
- int w, int h, uint32_t c);
- void (*mouse_set)(int x, int y, int on);
- void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
- uint8_t *image, uint8_t *mask);
-};
-
-static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
-{
- s->dpy_update(s, x, y, w, h);
-}
-
-static inline void dpy_resize(DisplayState *s, int w, int h)
-{
- s->dpy_resize(s, w, h);
-}
-
-typedef void (*vga_hw_update_ptr)(void *);
-typedef void (*vga_hw_invalidate_ptr)(void *);
-typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
-
-TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
- vga_hw_invalidate_ptr invalidate,
- vga_hw_screen_dump_ptr screen_dump,
- void *opaque);
-void vga_hw_update(void);
-void vga_hw_invalidate(void);
-void vga_hw_screen_dump(const char *filename);
-
-int is_graphic_console(void);
-CharDriverState *text_console_init(DisplayState *ds, const char *p);
-void console_select(unsigned int index);
-void console_color_init(DisplayState *ds);
-
-/* serial ports */
-
-#define MAX_SERIAL_PORTS 4
-
-extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
-
-/* parallel ports */
-
-#define MAX_PARALLEL_PORTS 3
-
-extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
-
-struct ParallelIOArg {
- void *buffer;
- int count;
-};
-
-/* VLANs support */
-
-typedef struct VLANClientState VLANClientState;
-
-struct VLANClientState {
- IOReadHandler *fd_read;
- /* Packets may still be sent if this returns zero. It's used to
- rate-limit the slirp code. */
- IOCanRWHandler *fd_can_read;
- void *opaque;
- struct VLANClientState *next;
- struct VLANState *vlan;
- char info_str[256];
-};
-
-typedef struct VLANState {
- int id;
- VLANClientState *first_client;
- struct VLANState *next;
- unsigned int nb_guest_devs, nb_host_devs;
-} VLANState;
-
-VLANState *qemu_find_vlan(int id);
-VLANClientState *qemu_new_vlan_client(VLANState *vlan,
- IOReadHandler *fd_read,
- IOCanRWHandler *fd_can_read,
- void *opaque);
-int qemu_can_send_packet(VLANClientState *vc);
-void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
-void qemu_handler_true(void *opaque);
-
-void do_info_network(void);
-
-/* TAP win32 */
-int tap_win32_init(VLANState *vlan, const char *ifname);
-
-/* NIC info */
-
-#define MAX_NICS 8
-
-typedef struct NICInfo {
- uint8_t macaddr[6];
- const char *model;
- VLANState *vlan;
-} NICInfo;
-
-extern int nb_nics;
-extern NICInfo nd_table[MAX_NICS];
-
-/* SLIRP */
-void do_info_slirp(void);
-
-/* timers */
-
-typedef struct QEMUClock QEMUClock;
-typedef struct QEMUTimer QEMUTimer;
-typedef void QEMUTimerCB(void *opaque);
-
-/* The real time clock should be used only for stuff which does not
- change the virtual machine state, as it is run even if the virtual
- machine is stopped. The real time clock has a frequency of 1000
- Hz. */
-extern QEMUClock *rt_clock;
-
-/* The virtual clock is only run during the emulation. It is stopped
- when the virtual machine is stopped. Virtual timers use a high
- precision clock, usually cpu cycles (use ticks_per_sec). */
-extern QEMUClock *vm_clock;
-
-int64_t qemu_get_clock(QEMUClock *clock);
-
-QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
-void qemu_free_timer(QEMUTimer *ts);
-void qemu_del_timer(QEMUTimer *ts);
-void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
-int qemu_timer_pending(QEMUTimer *ts);
-
-extern int64_t ticks_per_sec;
-
-int64_t cpu_get_ticks(void);
-void cpu_enable_ticks(void);
-void cpu_disable_ticks(void);
-
-/* VM Load/Save */
-
-typedef struct QEMUFile QEMUFile;
-
-QEMUFile *qemu_fopen(const char *filename, const char *mode);
-void qemu_fflush(QEMUFile *f);
-void qemu_fclose(QEMUFile *f);
-void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
-void qemu_put_byte(QEMUFile *f, int v);
-void qemu_put_be16(QEMUFile *f, unsigned int v);
-void qemu_put_be32(QEMUFile *f, unsigned int v);
-void qemu_put_be64(QEMUFile *f, uint64_t v);
-int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
-int qemu_get_byte(QEMUFile *f);
-unsigned int qemu_get_be16(QEMUFile *f);
-unsigned int qemu_get_be32(QEMUFile *f);
-uint64_t qemu_get_be64(QEMUFile *f);
-
-static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
-{
- qemu_put_be64(f, *pv);
-}
-
-static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
-{
- qemu_put_be32(f, *pv);
-}
-
-static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
-{
- qemu_put_be16(f, *pv);
-}
-
-static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
-{
- qemu_put_byte(f, *pv);
-}
-
-static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
-{
- *pv = qemu_get_be64(f);
-}
-
-static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
-{
- *pv = qemu_get_be32(f);
-}
-
-static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
-{
- *pv = qemu_get_be16(f);
-}
-
-static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
-{
- *pv = qemu_get_byte(f);
-}
-
-#if TARGET_LONG_BITS == 64
-#define qemu_put_betl qemu_put_be64
-#define qemu_get_betl qemu_get_be64
-#define qemu_put_betls qemu_put_be64s
-#define qemu_get_betls qemu_get_be64s
-#else
-#define qemu_put_betl qemu_put_be32
-#define qemu_get_betl qemu_get_be32
-#define qemu_put_betls qemu_put_be32s
-#define qemu_get_betls qemu_get_be32s
-#endif
-
-int64_t qemu_ftell(QEMUFile *f);
-int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
-
-typedef void SaveStateHandler(QEMUFile *f, void *opaque);
-typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
-
-int register_savevm(const char *idstr,
- int instance_id,
- int version_id,
- SaveStateHandler *save_state,
- LoadStateHandler *load_state,
- void *opaque);
-void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
-void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
-
-void cpu_save(QEMUFile *f, void *opaque);
-int cpu_load(QEMUFile *f, void *opaque, int version_id);
-
-void do_savevm(const char *name);
-void do_loadvm(const char *name);
-void do_delvm(const char *name);
-void do_info_snapshots(void);
-
-/* monitor.c */
-void monitor_init(CharDriverState *hd, int show_banner);
-void term_puts(const char *str);
-void term_vprintf(const char *fmt, va_list ap);
-void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
-void term_print_filename(const char *filename);
-void term_flush(void);
-void term_print_help(void);
-void monitor_readline(const char *prompt, int is_password,
- char *buf, int buf_size);
-
-/* readline.c */
-typedef void ReadLineFunc(void *opaque, const char *str);
-
-extern int completion_index;
-void add_completion(const char *str);
-void readline_handle_byte(int ch);
-void readline_find_completion(const char *cmdline);
-const char *readline_get_history(unsigned int index);
-void readline_start(const char *prompt, int is_password,
- ReadLineFunc *readline_func, void *opaque);
-void readline_history_save(void);
-void readline_history_restore(void);
-
-void kqemu_record_dump(void);
-
-/* sdl.c */
-void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
-
-/* cocoa.m */
-void cocoa_display_init(DisplayState *ds, int full_screen);
-
-/* vnc.c */
-void vnc_display_init(DisplayState *ds);
-void vnc_display_close(DisplayState *ds);
-int vnc_display_open(DisplayState *ds, const char *display);
-int vnc_display_password(DisplayState *ds, const char *password);
-void do_info_vnc(void);
-
-/* x_keymap.c */
-extern uint8_t _translate_keycode(const int key);
-
-#ifdef NEED_CPU_H
-
-typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
- const char *boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model);
-
-typedef struct QEMUMachine {
- const char *name;
- const char *desc;
- QEMUMachineInitFunc *init;
- struct QEMUMachine *next;
-} QEMUMachine;
-
-int qemu_register_machine(QEMUMachine *m);
-
-typedef void SetIRQFunc(void *opaque, int irq_num, int level);
-
-#include "hw/irq.h"
-
-/* ISA bus */
-
-extern target_phys_addr_t isa_mem_base;
-
-typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
-typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
-
-int register_ioport_read(int start, int length, int size,
- IOPortReadFunc *func, void *opaque);
-int register_ioport_write(int start, int length, int size,
- IOPortWriteFunc *func, void *opaque);
-void isa_unassign_ioport(int start, int length);
-
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
-
-/* PCI bus */
-
-extern target_phys_addr_t pci_mem_base;
-
-typedef struct PCIBus PCIBus;
-typedef struct PCIDevice PCIDevice;
-
-typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
- uint32_t address, uint32_t data, int len);
-typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
- uint32_t address, int len);
-typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type);
-
-#define PCI_ADDRESS_SPACE_MEM 0x00
-#define PCI_ADDRESS_SPACE_IO 0x01
-#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
-
-typedef struct PCIIORegion {
- uint32_t addr; /* current PCI mapping address. -1 means not mapped */
- uint32_t size;
- uint8_t type;
- PCIMapIORegionFunc *map_func;
-} PCIIORegion;
-
-#define PCI_ROM_SLOT 6
-#define PCI_NUM_REGIONS 7
-
-#define PCI_DEVICES_MAX 64
-
-#define PCI_VENDOR_ID 0x00 /* 16 bits */
-#define PCI_DEVICE_ID 0x02 /* 16 bits */
-#define PCI_COMMAND 0x04 /* 16 bits */
-#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
-#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
-#define PCI_CLASS_DEVICE 0x0a /* Device class */
-#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
-#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
-#define PCI_MIN_GNT 0x3e /* 8 bits */
-#define PCI_MAX_LAT 0x3f /* 8 bits */
-
-struct PCIDevice {
- /* PCI config space */
- uint8_t config[256];
-
- /* the following fields are read only */
- PCIBus *bus;
- int devfn;
- char name[64];
- PCIIORegion io_regions[PCI_NUM_REGIONS];
-
- /* do not access the following fields */
- PCIConfigReadFunc *config_read;
- PCIConfigWriteFunc *config_write;
- /* ??? This is a PC-specific hack, and should be removed. */
- int irq_index;
-
- /* IRQ objects for the INTA-INTD pins. */
- qemu_irq *irq;
-
- /* Current IRQ levels. Used internally by the generic PCI code. */
- int irq_state[4];
-};
-
-PCIDevice *pci_register_device(PCIBus *bus, const char *name,
- int instance_size, int devfn,
- PCIConfigReadFunc *config_read,
- PCIConfigWriteFunc *config_write);
-
-void pci_register_io_region(PCIDevice *pci_dev, int region_num,
- uint32_t size, int type,
- PCIMapIORegionFunc *map_func);
-
-uint32_t pci_default_read_config(PCIDevice *d,
- uint32_t address, int len);
-void pci_default_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len);
-void pci_device_save(PCIDevice *s, QEMUFile *f);
-int pci_device_load(PCIDevice *s, QEMUFile *f);
-
-typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
-typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
-PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq);
-
-void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
-void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
-uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
-int pci_bus_num(PCIBus *s);
-void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
-
-void pci_info(void);
-PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
- pci_map_irq_fn map_irq, const char *name);
-
-/* prep_pci.c */
-PCIBus *pci_prep_init(qemu_irq *pic);
-
-/* apb_pci.c */
-PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
- qemu_irq *pic);
-
-PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
-
-/* piix_pci.c */
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
-void i440fx_set_smm(PCIDevice *d, int val);
-int piix3_init(PCIBus *bus, int devfn);
-void i440fx_init_memory_mappings(PCIDevice *d);
-
-int piix4_init(PCIBus *bus, int devfn);
-
-/* openpic.c */
-/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
-enum {
- OPENPIC_OUTPUT_INT = 0, /* IRQ */
- OPENPIC_OUTPUT_CINT, /* critical IRQ */
- OPENPIC_OUTPUT_MCK, /* Machine check event */
- OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
- OPENPIC_OUTPUT_RESET, /* Core reset event */
- OPENPIC_OUTPUT_NB,
-};
-qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out);
-
-/* gt64xxx.c */
-PCIBus *pci_gt64120_init(qemu_irq *pic);
-
-#ifdef HAS_AUDIO
-struct soundhw {
- const char *name;
- const char *descr;
- int enabled;
- int isa;
- union {
- int (*init_isa) (AudioState *s, qemu_irq *pic);
- int (*init_pci) (PCIBus *bus, AudioState *s);
- } init;
-};
-
-extern struct soundhw soundhw[];
-#endif
-
-/* vga.c */
-
-#ifndef TARGET_SPARC
-#define VGA_RAM_SIZE (8192 * 1024)
-#else
-#define VGA_RAM_SIZE (9 * 1024 * 1024)
-#endif
-
-int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size);
-int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size,
- unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size,
- target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
- int it_shift);
-
-/* cirrus_vga.c */
-void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size);
-void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size);
-
-/* vmware_vga.c */
-void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size);
-
-/* ide.c */
-#define MAX_DISKS 4
-
-extern BlockDriverState *bs_table[MAX_DISKS + 1];
-extern BlockDriverState *sd_bdrv;
-extern BlockDriverState *mtd_bdrv;
-
-void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
- BlockDriverState *hd0, BlockDriverState *hd1);
-void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
- int secondary_ide_enabled);
-void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic);
-void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic);
-
-/* cdrom.c */
-int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
-int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
-
-/* ds1225y.c */
-typedef struct ds1225y_t ds1225y_t;
-ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
-
-/* es1370.c */
-int es1370_init (PCIBus *bus, AudioState *s);
-
-/* sb16.c */
-int SB16_init (AudioState *s, qemu_irq *pic);
-
-/* adlib.c */
-int Adlib_init (AudioState *s, qemu_irq *pic);
-
-/* gus.c */
-int GUS_init (AudioState *s, qemu_irq *pic);
-
-/* dma.c */
-typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
-int DMA_get_channel_mode (int nchan);
-int DMA_read_memory (int nchan, void *buf, int pos, int size);
-int DMA_write_memory (int nchan, void *buf, int pos, int size);
-void DMA_hold_DREQ (int nchan);
-void DMA_release_DREQ (int nchan);
-void DMA_schedule(int nchan);
-void DMA_run (void);
-void DMA_init (int high_page_enable);
-void DMA_register_channel (int nchan,
- DMA_transfer_handler transfer_handler,
- void *opaque);
-/* fdc.c */
-#define MAX_FD 2
-extern BlockDriverState *fd_table[MAX_FD];
-
-typedef struct fdctrl_t fdctrl_t;
-
-fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
- target_phys_addr_t io_base,
- BlockDriverState **fds);
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
- BlockDriverState **fds);
-int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
-
-/* eepro100.c */
-
-void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
-void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
-void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
-
-/* ne2000.c */
-
-void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
-void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
-
-/* rtl8139.c */
-
-void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
-
-/* pcnet.c */
-
-void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
-void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
- qemu_irq irq, qemu_irq *reset);
-
-/* mipsnet.c */
-void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
-
-/* vmmouse.c */
-void *vmmouse_init(void *m);
-
-/* vmport.c */
-#ifdef TARGET_I386
-void vmport_init(CPUState *env);
-void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
-#endif
-
-/* pckbd.c */
-
-void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, int it_shift);
-
-/* mc146818rtc.c */
-
-typedef struct RTCState RTCState;
-
-RTCState *rtc_init(int base, qemu_irq irq);
-RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
-void rtc_set_memory(RTCState *s, int addr, int val);
-void rtc_set_date(RTCState *s, const struct tm *tm);
-
-/* serial.c */
-
-typedef struct SerialState SerialState;
-SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
-SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
- qemu_irq irq, CharDriverState *chr,
- int ioregister);
-uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
-void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
-uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
-void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
-uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
-void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
-
-/* parallel.c */
-
-typedef struct ParallelState ParallelState;
-ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
-ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
-
-/* i8259.c */
-
-typedef struct PicState2 PicState2;
-extern PicState2 *isa_pic;
-void pic_set_irq(int irq, int level);
-void pic_set_irq_new(void *opaque, int irq, int level);
-qemu_irq *i8259_init(qemu_irq parent_irq);
-void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
- void *alt_irq_opaque);
-int pic_read_irq(PicState2 *s);
-void pic_update_irq(PicState2 *s);
-uint32_t pic_intack_read(PicState2 *s);
-void pic_info(void);
-void irq_info(void);
-
-/* APIC */
-typedef struct IOAPICState IOAPICState;
-
-int apic_init(CPUState *env);
-int apic_accept_pic_intr(CPUState *env);
-int apic_get_interrupt(CPUState *env);
-IOAPICState *ioapic_init(void);
-void ioapic_set_irq(void *opaque, int vector, int level);
-
-/* i8254.c */
-
-#define PIT_FREQ 1193182
-
-typedef struct PITState PITState;
-
-PITState *pit_init(int base, qemu_irq irq);
-void pit_set_gate(PITState *pit, int channel, int val);
-int pit_get_gate(PITState *pit, int channel);
-int pit_get_initial_count(PITState *pit, int channel);
-int pit_get_mode(PITState *pit, int channel);
-int pit_get_out(PITState *pit, int channel, int64_t current_time);
-
-/* jazz_led.c */
-extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
-
-/* pcspk.c */
-void pcspk_init(PITState *);
-int pcspk_audio_init(AudioState *, qemu_irq *pic);
-
-/* GPIO */
-typedef void (*gpio_handler_t)(int line, int level, void *opaque);
-
-#include "hw/i2c.h"
-
-#include "hw/smbus.h"
-
-/* Bluetooth */
-#include "hw/bt.h"
-extern struct bt_piconet_s *local_piconet;
-
-/* acpi.c */
-extern int acpi_enabled;
-i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
-void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
-void acpi_bios_init(void);
-
-/* Axis ETRAX. */
-extern QEMUMachine bareetraxfs_machine;
-
-/* pc.c */
-extern QEMUMachine pc_machine;
-extern QEMUMachine isapc_machine;
-extern int fd_bootchk;
-
-void ioport_set_a20(int enable);
-int ioport_get_a20(void);
-
-/* ppc.c */
-extern QEMUMachine prep_machine;
-extern QEMUMachine core99_machine;
-extern QEMUMachine heathrow_machine;
-extern QEMUMachine ref405ep_machine;
-extern QEMUMachine taihu_machine;
-
-/* mips_r4k.c */
-extern QEMUMachine mips_machine;
-
-/* mips_malta.c */
-extern QEMUMachine mips_malta_machine;
-
-/* mips_pica61.c */
-extern QEMUMachine mips_pica61_machine;
-
-/* mips_mipssim.c */
-extern QEMUMachine mips_mipssim_machine;
-
-/* mips_int.c */
-extern void cpu_mips_irq_init_cpu(CPUState *env);
-
-/* mips_timer.c */
-extern void cpu_mips_clock_init(CPUState *);
-extern void cpu_mips_irqctrl_init (void);
-
-/* shix.c */
-extern QEMUMachine shix_machine;
-
-/* r2d.c */
-extern QEMUMachine r2d_machine;
-
-#ifdef TARGET_PPC
-/* PowerPC hardware exceptions management helpers */
-typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
-typedef struct clk_setup_t clk_setup_t;
-struct clk_setup_t {
- clk_setup_cb cb;
- void *opaque;
-};
-static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
-{
- if (clk->cb != NULL)
- (*clk->cb)(clk->opaque, freq);
-}
-
-clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
-/* Embedded PowerPC DCR management */
-typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
-typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
-int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
- int (*dcr_write_error)(int dcrn));
-int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
- dcr_read_cb drc_read, dcr_write_cb dcr_write);
-clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
-/* Embedded PowerPC reset */
-void ppc40x_core_reset (CPUState *env);
-void ppc40x_chip_reset (CPUState *env);
-void ppc40x_system_reset (CPUState *env);
-void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
-
-extern CPUWriteMemoryFunc *PPC_io_write[];
-extern CPUReadMemoryFunc *PPC_io_read[];
-void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
-#endif
-
-/* sun4m.c */
-extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
-
-/* iommu.c */
-void *iommu_init(target_phys_addr_t addr);
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
- uint8_t *buf, int len, int is_write);
-static inline void sparc_iommu_memory_read(void *opaque,
- target_phys_addr_t addr,
- uint8_t *buf, int len)
-{
- sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
-}
-
-static inline void sparc_iommu_memory_write(void *opaque,
- target_phys_addr_t addr,
- uint8_t *buf, int len)
-{
- sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
-}
-
-/* tcx.c */
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
- unsigned long vram_offset, int vram_size, int width, int height,
- int depth);
-
-/* slavio_intctl.c */
-void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
- const uint32_t *intbit_to_level,
- qemu_irq **irq, qemu_irq **cpu_irq,
- qemu_irq **parent_irq, unsigned int cputimer);
-void slavio_pic_info(void *opaque);
-void slavio_irq_info(void *opaque);
-
-/* loader.c */
-int get_image_size(const char *filename);
-int load_image(const char *filename, uint8_t *addr);
-int load_elf(const char *filename, int64_t virt_to_phys_addend,
- uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
-int load_aout(const char *filename, uint8_t *addr);
-int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
-
-/* slavio_timer.c */
-void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
- qemu_irq *cpu_irqs);
-
-/* slavio_serial.c */
-SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
- CharDriverState *chr1, CharDriverState *chr2);
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
-
-/* slavio_misc.c */
-void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
- qemu_irq irq);
-void slavio_set_power_fail(void *opaque, int power_failing);
-
-/* esp.c */
-void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
-void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
- void *dma_opaque, qemu_irq irq, qemu_irq *reset);
-
-/* sparc32_dma.c */
-void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
- void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
- uint8_t *buf, int len, int do_bswap);
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
- uint8_t *buf, int len, int do_bswap);
-void espdma_memory_read(void *opaque, uint8_t *buf, int len);
-void espdma_memory_write(void *opaque, uint8_t *buf, int len);
-
-/* cs4231.c */
-void cs_init(target_phys_addr_t base, int irq, void *intctl);
-
-/* sun4u.c */
-extern QEMUMachine sun4u_machine;
-
-/* NVRAM helpers */
-typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
-typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
-typedef struct nvram_t {
- void *opaque;
- nvram_read_t read_fn;
- nvram_write_t write_fn;
-} nvram_t;
-
-#include "hw/m48t59.h"
-
-void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
-uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
-void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
-uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
-void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
-uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
-void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
- const unsigned char *str, uint32_t max);
-int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
-void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
- uint32_t start, uint32_t count);
-int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
- const unsigned char *arch,
- uint32_t RAM_size, int boot_device,
- uint32_t kernel_image, uint32_t kernel_size,
- const char *cmdline,
- uint32_t initrd_image, uint32_t initrd_size,
- uint32_t NVRAM_image,
- int width, int height, int depth);
-
-/* adb.c */
-
-#define MAX_ADB_DEVICES 16
-
-#define ADB_MAX_OUT_LEN 16
-
-typedef struct ADBDevice ADBDevice;
-
-/* buf = NULL means polling */
-typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
- const uint8_t *buf, int len);
-typedef int ADBDeviceReset(ADBDevice *d);
-
-struct ADBDevice {
- struct ADBBusState *bus;
- int devaddr;
- int handler;
- ADBDeviceRequest *devreq;
- ADBDeviceReset *devreset;
- void *opaque;
-};
-
-typedef struct ADBBusState {
- ADBDevice devices[MAX_ADB_DEVICES];
- int nb_devices;
- int poll_index;
-} ADBBusState;
-
-int adb_request(ADBBusState *s, uint8_t *buf_out,
- const uint8_t *buf, int len);
-int adb_poll(ADBBusState *s, uint8_t *buf_out);
-
-ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
- ADBDeviceRequest *devreq,
- ADBDeviceReset *devreset,
- void *opaque);
-void adb_kbd_init(ADBBusState *bus);
-void adb_mouse_init(ADBBusState *bus);
-
-extern ADBBusState adb_bus;
-
-#include "hw/usb.h"
-
-/* usb ports of the VM */
-
-#define USB_INDEX_HOST -1
-void qemu_register_usb_port(USBPort *port, void *opaque, int index,
- usb_attachfn attach);
-void qemu_register_usb_gadget(USBDevice *device);
-
-#define VM_USB_HUB_SIZE 8
-
-void do_usb_add(const char *devname);
-void do_usb_del(const char *devname);
-void usb_info(void);
-void usb_slave_info(void);
-int usb_device_attach(USBDevice *dev);
-
-/* scsi-disk.c */
-enum scsi_reason {
- SCSI_REASON_DONE, /* Command complete. */
- SCSI_REASON_DATA /* Transfer complete, more data required. */
-};
-
-typedef struct SCSIDevice SCSIDevice;
-typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
- uint32_t arg);
-
-SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
- int tcq,
- scsi_completionfn completion,
- void *opaque);
-void scsi_disk_destroy(SCSIDevice *s);
-
-int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
-/* SCSI data transfers are asynchrnonous. However, unlike the block IO
- layer the completion routine may be called directly by
- scsi_{read,write}_data. */
-void scsi_read_data(SCSIDevice *s, uint32_t tag);
-int scsi_write_data(SCSIDevice *s, uint32_t tag);
-void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
-uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
-
-/* lsi53c895a.c */
-void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
-void *lsi_scsi_init(PCIBus *bus, int devfn);
-
-/* integratorcp.c */
-extern QEMUMachine integratorcp_machine;
-
-/* versatilepb.c */
-extern QEMUMachine versatilepb_machine;
-extern QEMUMachine versatileab_machine;
-
-/* realview.c */
-extern QEMUMachine realview_machine;
-
-/* spitz.c */
-extern QEMUMachine akitapda_machine;
-extern QEMUMachine spitzpda_machine;
-extern QEMUMachine borzoipda_machine;
-extern QEMUMachine terrierpda_machine;
-
-/* neo1973.c */
-extern QEMUMachine neo1973_machine;
-
-/* palm.c */
-extern QEMUMachine palmte_machine;
-
-/* armv7m.c */
-qemu_irq *armv7m_init(int flash_size, int sram_size,
- const char *kernel_filename, const char *cpu_model);
-
-/* stellaris.c */
-extern QEMUMachine lm3s811evb_machine;
-extern QEMUMachine lm3s6965evb_machine;
-
-/* ps2.c */
-void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
-void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
-void ps2_write_mouse(void *, int val);
-void ps2_write_keyboard(void *, int val);
-uint32_t ps2_read_data(void *);
-void ps2_queue(void *, int b);
-void ps2_keyboard_set_translation(void *opaque, int mode);
-void ps2_mouse_fake_event(void *opaque);
-
-/* smc91c111.c */
-void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
-
-/* pl031.c */
-void pl031_init(uint32_t base, qemu_irq irq);
-
-/* pl110.c */
-void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
-
-/* pl011.c */
-enum pl011_type {
- PL011_ARM,
- PL011_LUMINARY
-};
-
-void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr,
- enum pl011_type type);
-
-/* pl022.c */
-void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int),
- void *opaque);
-
-/* pl050.c */
-void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
-
-/* pl061.c */
-qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
-
-/* pl080.c */
-void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
-
-/* pl181.c */
-void pl181_init(uint32_t base, BlockDriverState *bd,
- qemu_irq irq0, qemu_irq irq1);
-
-/* pl190.c */
-qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
-
-/* arm-timer.c */
-void sp804_init(uint32_t base, qemu_irq irq);
-void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
-
-/* arm_sysctl.c */
-void arm_sysctl_init(uint32_t base, uint32_t sys_id);
-
-/* realview_gic.c */
-qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
-
-/* mpcore.c */
-extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
-
-/* arm_boot.c */
-
-void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
- const char *kernel_cmdline, const char *initrd_filename,
- int board_id, target_phys_addr_t loader_start);
-
-/* armv7m_nvic.c */
-qemu_irq *armv7m_nvic_init(CPUState *env);
-
-/* ssd0303.c */
-void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address);
-
-/* ssd0323.c */
-int ssd0323_xfer_ssi(void *opaque, int data);
-void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
-
-/* sh7750.c */
-struct SH7750State;
-
-struct SH7750State *sh7750_init(CPUState * cpu);
-
-typedef struct {
- /* The callback will be triggered if any of the designated lines change */
- uint16_t portamask_trigger;
- uint16_t portbmask_trigger;
- /* Return 0 if no action was taken */
- int (*port_change_cb) (uint16_t porta, uint16_t portb,
- uint16_t * periph_pdtra,
- uint16_t * periph_portdira,
- uint16_t * periph_pdtrb,
- uint16_t * periph_portdirb);
-} sh7750_io_device;
-
-int sh7750_register_io_device(struct SH7750State *s,
- sh7750_io_device * device);
-/* sh_timer.c */
-#define TMU012_FEAT_TOCR (1 << 0)
-#define TMU012_FEAT_3CHAN (1 << 1)
-#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(uint32_t base, int feat, uint32_t freq);
-
-/* sh_serial.c */
-#define SH_SERIAL_FEAT_SCIF (1 << 0)
-void sh_serial_init (target_phys_addr_t base, int feat,
- uint32_t freq, CharDriverState *chr);
-
-/* tc58128.c */
-int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
-
-/* NOR flash devices */
-#define MAX_PFLASH 4
-extern BlockDriverState *pflash_table[MAX_PFLASH];
-typedef struct pflash_t pflash_t;
-
-pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
- BlockDriverState *bs,
- uint32_t sector_len, int nb_blocs, int width,
- uint16_t id0, uint16_t id1,
- uint16_t id2, uint16_t id3);
-
-/* nand.c */
-struct nand_flash_s;
-struct nand_flash_s *nand_init(int manf_id, int chip_id);
-void nand_done(struct nand_flash_s *s);
-void nand_setpins(struct nand_flash_s *s,
- int cle, int ale, int ce, int wp, int gnd);
-void nand_getpins(struct nand_flash_s *s, int *rb);
-void nand_setio(struct nand_flash_s *s, uint8_t value);
-uint8_t nand_getio(struct nand_flash_s *s);
-
-#define NAND_MFR_TOSHIBA 0x98
-#define NAND_MFR_SAMSUNG 0xec
-#define NAND_MFR_FUJITSU 0x04
-#define NAND_MFR_NATIONAL 0x8f
-#define NAND_MFR_RENESAS 0x07
-#define NAND_MFR_STMICRO 0x20
-#define NAND_MFR_HYNIX 0xad
-#define NAND_MFR_MICRON 0x2c
-
-/* ecc.c */
-struct ecc_state_s {
- uint8_t cp; /* Column parity */
- uint16_t lp[2]; /* Line parity */
- uint16_t count;
-};
-
-uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
-void ecc_reset(struct ecc_state_s *s);
-void ecc_put(QEMUFile *f, struct ecc_state_s *s);
-void ecc_get(QEMUFile *f, struct ecc_state_s *s);
-
-/* ads7846.c */
-struct ads7846_state_s;
-uint32_t ads7846_read(void *opaque);
-void ads7846_write(void *opaque, uint32_t value);
-struct ads7846_state_s *ads7846_init(qemu_irq penirq);
-
-/* max111x.c */
-struct max111x_s;
-uint32_t max111x_read(void *opaque);
-void max111x_write(void *opaque, uint32_t value);
-struct max111x_s *max1110_init(qemu_irq cb);
-struct max111x_s *max1111_init(qemu_irq cb);
-void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
-
-/* jbt6k74.c */
-uint8_t jbt6k74_txrx(void *opaque, uint8_t value);
-uint8_t jbt6k74_btxrx(void *opaque, uint8_t value);
-void *jbt6k74_init();
-
-/* modem.c */
-CharDriverState *modem_init();
-void modem_enable(CharDriverState *chr, int enable);
-extern struct modem_ops_s {
- void *opaque;
- void (*ring)(void *opaque);
-} modem_ops;
-
-/* gps.c */
-CharDriverState *gps_antaris_serial_init();
-void gps_enable(CharDriverState *chr, int enable);
-
-/* PCMCIA/Cardbus */
-
-struct pcmcia_socket_s {
- qemu_irq irq;
- int attached;
- const char *slot_string;
- const char *card_string;
-};
-
-void pcmcia_socket_register(struct pcmcia_socket_s *socket);
-void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
-void pcmcia_info(void);
-
-struct pcmcia_card_s {
- void *state;
- struct pcmcia_socket_s *slot;
- int (*attach)(void *state);
- int (*detach)(void *state);
- const uint8_t *cis;
- int cis_len;
-
- /* Only valid if attached */
- uint8_t (*attr_read)(void *state, uint32_t address);
- void (*attr_write)(void *state, uint32_t address, uint8_t value);
- uint16_t (*common_read)(void *state, uint32_t address);
- void (*common_write)(void *state, uint32_t address, uint16_t value);
- uint16_t (*io_read)(void *state, uint32_t address);
- void (*io_write)(void *state, uint32_t address, uint16_t value);
-};
-
-#define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
-#define CISTPL_NO_LINK 0x14 /* No Link Tuple */
-#define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
-#define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
-#define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
-#define CISTPL_CONFIG 0x1a /* Configuration Tuple */
-#define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
-#define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
-#define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
-#define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
-#define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
-#define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
-#define CISTPL_FUNCID 0x21 /* Function ID Tuple */
-#define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
-#define CISTPL_END 0xff /* Tuple End */
-#define CISTPL_ENDMARK 0xff
-
-/* dscm1xxxx.c */
-struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
-
-/* ptimer.c */
-typedef struct ptimer_state ptimer_state;
-typedef void (*ptimer_cb)(void *opaque);
-
-ptimer_state *ptimer_init(QEMUBH *bh);
-void ptimer_set_period(ptimer_state *s, int64_t period);
-void ptimer_set_freq(ptimer_state *s, uint32_t freq);
-void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
-uint64_t ptimer_get_count(ptimer_state *s);
-void ptimer_set_count(ptimer_state *s, uint64_t count);
-void ptimer_run(ptimer_state *s, int oneshot);
-void ptimer_stop(ptimer_state *s);
-void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
-void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
-
-#include "hw/pxa.h"
-
-#include "hw/s3c.h"
-
-#include "hw/omap.h"
-
-/* tsc210x.c */
-struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
-struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
-
-/* mcf_uart.c */
-uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
-void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
-void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
-void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
- CharDriverState *chr);
-
-/* mcf_intc.c */
-qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
-
-/* mcf_fec.c */
-void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
-
-/* mcf5206.c */
-qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
-
-/* an5206.c */
-extern QEMUMachine an5206_machine;
-
-/* mcf5208.c */
-extern QEMUMachine mcf5208evb_machine;
-
-/* dummy_m68k.c */
-extern QEMUMachine dummy_m68k_machine;
-
-#include "gdbstub.h"
-
-#endif /* defined(NEED_CPU_H) */
-#endif /* VL_H */
Modified: trunk/src/host/qemu-neo1973/vnc.c
===================================================================
--- trunk/src/host/qemu-neo1973/vnc.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/vnc.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -23,8 +23,11 @@
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
+#include "sysemu.h"
#include "qemu_socket.h"
+#include "qemu-timer.h"
#define VNC_REFRESH_INTERVAL (1000 / 30)
@@ -809,9 +812,9 @@
}
#if CONFIG_VNC_TLS
-ssize_t vnc_tls_push(gnutls_transport_ptr_t transport,
- const void *data,
- size_t len) {
+static ssize_t vnc_tls_push(gnutls_transport_ptr_t transport,
+ const void *data,
+ size_t len) {
struct VncState *vs = (struct VncState *)transport;
int ret;
@@ -826,9 +829,9 @@
}
-ssize_t vnc_tls_pull(gnutls_transport_ptr_t transport,
- void *data,
- size_t len) {
+static ssize_t vnc_tls_pull(gnutls_transport_ptr_t transport,
+ void *data,
+ size_t len) {
struct VncState *vs = (struct VncState *)transport;
int ret;
Modified: trunk/src/host/qemu-neo1973/x_keymap.c
===================================================================
--- trunk/src/host/qemu-neo1973/x_keymap.c 2007-11-19 17:26:24 UTC (rev 3442)
+++ trunk/src/host/qemu-neo1973/x_keymap.c 2007-11-19 18:54:17 UTC (rev 3443)
@@ -21,7 +21,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "qemu-common.h"
+#include "console.h"
+
static const uint8_t x_keycode_to_pc_keycode[115] = {
0xc7, /* 97 Home */
0xc8, /* 98 Up */
More information about the commitlog
mailing list
