r3162 - trunk/src/target/u-boot/patches
laforge at sita.openmoko.org
laforge at sita.openmoko.org
Sun Oct 14 19:52:41 CEST 2007
Author: laforge
Date: 2007-10-14 19:52:31 +0200 (Sun, 14 Oct 2007)
New Revision: 3162
Modified:
trunk/src/target/u-boot/patches/uboot-s3c2410-nand.patch
trunk/src/target/u-boot/patches/uboot-s3c2440.patch
trunk/src/target/u-boot/patches/uboot-s3c2442.patch
trunk/src/target/u-boot/patches/uboot-s3c2443.patch
Log:
re-sync our start.S changes with mainline u-boot
Modified: trunk/src/target/u-boot/patches/uboot-s3c2410-nand.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2410-nand.patch 2007-10-14 13:10:33 UTC (rev 3161)
+++ trunk/src/target/u-boot/patches/uboot-s3c2410-nand.patch 2007-10-14 17:52:31 UTC (rev 3162)
@@ -368,18 +368,18 @@
#include <config.h>
#include <version.h>
+#include <s3c2410.h>
- #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- #include <led.h>
- #endif
-@@ -246,6 +251,7 @@
- #endif /* CONFIG_BOOTBINFUNC */
- #else
+ #include <status_led.h>
+
+ /*
+@@ -181,6 +186,7 @@
+ #ifdef CONFIG_AT91RM9200
+
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+#ifndef CONFIG_S3C2410_NAND_BOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
-@@ -262,6 +268,93 @@
+@@ -197,6 +203,93 @@
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
Modified: trunk/src/target/u-boot/patches/uboot-s3c2440.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2440.patch 2007-10-14 13:10:33 UTC (rev 3161)
+++ trunk/src/target/u-boot/patches/uboot-s3c2440.patch 2007-10-14 17:52:31 UTC (rev 3162)
@@ -756,22 +756,29 @@
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
+#endif
- #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- #include <led.h>
+ #include <status_led.h>
+
+ /*
+@@ -154,20 +158,38 @@
+ bne copyex
#endif
-@@ -207,14 +211,32 @@
- # define pWTCON 0x15300000
- # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
- # define CLKDIVN 0x14800014 /* clock divisor register */
--#elif defined(CONFIG_S3C2410)
-+#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440)
- # define pWTCON 0x53000000
- # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
- # define INTSUBMSK 0x4A00001C
- # define CLKDIVN 0x4C000014 /* clock divisor register */
- #endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ /* turn off the watchdog */
+
+ # if defined(CONFIG_S3C2400)
+ # define pWTCON 0x15300000
+ # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+ # define CLKDIVN 0x14800014 /* clock divisor register */
+-#else
++#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ # define pWTCON 0x53000000
+ # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+ # define INTSUBMSK 0x4A00001C
+ # define CLKDIVN 0x4C000014 /* clock divisor register */
+ # endif
+
+#if defined(CONFIG_S3C2410)
+# define INTSUBMSK_val 0x7ff
+# define MPLLCON_val ((0x90 << 12) + (0x7 << 4) + 0x0) /* 202 MHz */
@@ -790,11 +797,10 @@
+# define CAMDIVN 0x4C000018
+#endif
+
-+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
-@@ -225,24 +247,34 @@
+@@ -178,24 +200,34 @@
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
@@ -836,7 +842,7 @@
str r1, [r0]
/* Page 7-19, seven nops between UPLL and MPLL */
-@@ -254,12 +286,12 @@
+@@ -207,12 +239,12 @@
nop
nop
@@ -851,7 +857,7 @@
str r1, [r0]
#if 1
-@@ -287,7 +319,7 @@
+@@ -240,7 +272,7 @@
str r1, [r0, #0x28]
#endif
@@ -860,7 +866,7 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifndef CONFIG_LL_INIT_NAND_ONLY
-@@ -364,7 +396,7 @@
+@@ -299,7 +331,7 @@
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
bl cpu_init_crit
#endif
@@ -869,7 +875,7 @@
/* ensure some refresh has happened */
ldr r1, =0xfffff
1: subs r1, r1, #1
-@@ -375,11 +407,12 @@
+@@ -310,11 +342,12 @@
ldr r0, [ r1 ]
tst r0, #0x02 /* is this resume from power down */
ldrne pc, [r1, #4] /* gstatus3 */
@@ -883,7 +889,7 @@
@ reset NAND
mov r1, #S3C2410_NAND_BASE
ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0
-@@ -399,6 +432,17 @@
+@@ -334,6 +367,17 @@
ldr r2, [r1, #oNFCONF]
orr r2, r2, #0x800 @ disable chip
str r2, [r1, #oNFCONF]
@@ -901,7 +907,7 @@
#if 0
@ get ready to call C functions (for nand_read())
-@@ -467,7 +511,7 @@
+@@ -402,7 +446,7 @@
#endif /* CONFIG_S3C2410_NAND_BOOT */
done_relocate:
Modified: trunk/src/target/u-boot/patches/uboot-s3c2442.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2442.patch 2007-10-14 13:10:33 UTC (rev 3161)
+++ trunk/src/target/u-boot/patches/uboot-s3c2442.patch 2007-10-14 17:52:31 UTC (rev 3162)
@@ -391,40 +391,44 @@
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
#include <s3c2440.h>
#endif
- #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-@@ -211,7 +211,7 @@
- # define pWTCON 0x15300000
- # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
- # define CLKDIVN 0x14800014 /* clock divisor register */
--#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440)
-+#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) || defined(CONFIG_S3C2442)
- # define pWTCON 0x53000000
- # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
- # define INTSUBMSK 0x4A00001C
-@@ -234,9 +234,21 @@
+ #include <status_led.h>
+@@ -158,14 +158,15 @@
+ bne copyex
#endif
+
+-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFOG_S3C2442)
+ /* turn off the watchdog */
+
+ # if defined(CONFIG_S3C2400)
+ # define pWTCON 0x15300000
+ # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+ # define CLKDIVN 0x14800014 /* clock divisor register */
+-#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ # define pWTCON 0x53000000
+ # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+ # define INTSUBMSK 0x4A00001C
+@@ -188,6 +189,17 @@
+ #endif
# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
# define CAMDIVN 0x4C000018
+#elif defined(CONFIG_S3C2442)
-+# define INTSUBMSK_val 0xffff
++# define INTSUBMSK_val 0xffff
+# if (CONFIG_SYS_CLK_FREQ == 12000000)
-+# define MPLLCON_val ((142 << 12) + (7 << 4) + 1)
++# define MPLLCON_val ((142 << 12) + (7 << 4) + 1)
+# define UPLLCON_val (( 88 << 12) + (8 << 4) + 2)
+# elif (CONFIG_SYS_CLK_FREQ == 16934400)
+# define MPLLCON_val ((181 << 12) + (14<< 4) + 1)
+# define UPLLCON_val (( 26 << 12) + (4 << 4) + 1)
+# endif
-+# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
-+# define CAMDIVN 0x4C000018
++# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
++# define CAMDIVN 0x4C000018
#endif
--#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
-+ defined(CONFIG_S3C2442)
ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-@@ -247,13 +259,13 @@
+@@ -200,13 +212,13 @@
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
@@ -440,7 +444,7 @@
/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
ldr r0, =CAMDIVN
mov r1, #0
-@@ -319,7 +331,7 @@
+@@ -272,7 +284,7 @@
str r1, [r0, #0x28]
#endif
@@ -449,7 +453,7 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifndef CONFIG_LL_INIT_NAND_ONLY
-@@ -396,7 +408,7 @@
+@@ -331,7 +343,7 @@
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
bl cpu_init_crit
#endif
@@ -458,7 +462,7 @@
/* ensure some refresh has happened */
ldr r1, =0xfffff
1: subs r1, r1, #1
-@@ -407,7 +419,7 @@
+@@ -342,7 +354,7 @@
ldr r0, [ r1 ]
tst r0, #0x02 /* is this resume from power down */
ldrne pc, [r1, #4] /* gstatus3 */
@@ -467,7 +471,7 @@
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/* mov r10, lr */
-@@ -432,7 +444,7 @@
+@@ -367,7 +379,7 @@
ldr r2, [r1, #oNFCONF]
orr r2, r2, #0x800 @ disable chip
str r2, [r1, #oNFCONF]
@@ -476,7 +480,7 @@
mov r1, #S3C2440_NAND_BASE
ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7
ldr r3, [r1, #oNFCONF]
-@@ -511,7 +523,8 @@
+@@ -446,7 +458,8 @@
#endif /* CONFIG_S3C2410_NAND_BOOT */
done_relocate:
Modified: trunk/src/target/u-boot/patches/uboot-s3c2443.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-10-14 13:10:33 UTC (rev 3161)
+++ trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-10-14 17:52:31 UTC (rev 3162)
@@ -9,26 +9,30 @@
+#elif defined(CONFIG_S3C2443)
+#include <s3c2443.h>
#endif
- #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- #include <led.h>
-@@ -245,10 +247,15 @@
+ #include <status_led.h>
+
+@@ -159,7 +161,7 @@
+ #endif
+
+ #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+- defined(CONFOG_S3C2442)
++ defined(CONFOG_S3C2442) || defined(CONFIG_S3C2443)
+ /* turn off the watchdog */
+
+ # if defined(CONFIG_S3C2400)
+@@ -200,6 +202,11 @@
# endif
- # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
- # define CAMDIVN 0x4C000018
+ # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
+ # define CAMDIVN 0x4C000018
+#elif defined(CONFIG_S3C2443)
-+# define INTSUBMSK_val 0x1fffffff
++# define INTSUBMSK_val 0x1fffffff
+# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */
+# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */
+# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
#endif
- #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
-- defined(CONFIG_S3C2442)
-+ defined(CONFIG_S3C2442) || defined(CONFIG_S3c2443)
ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-@@ -259,7 +266,8 @@
+@@ -212,7 +219,8 @@
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
@@ -38,7 +42,7 @@
ldr r1, =INTSUBMSK_val
ldr r0, =INTSUBMSK
str r1, [r0]
-@@ -278,6 +286,43 @@
+@@ -231,6 +239,43 @@
mcr p15, 0, r1, c1, c0, 0
@@ -82,7 +86,7 @@
#define LOCKTIME 0x4c000000
#define UPLLCON 0x4c000008
-@@ -305,6 +350,7 @@
+@@ -258,6 +303,7 @@
ldr r0, =CLKDIVN
mov r1, #CLKDIVN_val
str r1, [r0]
@@ -90,7 +94,7 @@
#if 1
/* enable uart */
-@@ -331,7 +377,8 @@
+@@ -284,7 +330,8 @@
str r1, [r0, #0x28]
#endif
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