r3216 - trunk/src/target/u-boot/patches

[laforge at sita.openmoko.org]

Author: laforge
Date: 2007-10-18 08:35:38 +0200 (Thu, 18 Oct 2007)
New Revision: 3216

Modified:
   trunk/src/target/u-boot/patches/uboot-s3c2442.patch
Log:
Add S3C2442B54 (500Mhz) core clock support to cmd_s3c24xx


Modified: trunk/src/target/u-boot/patches/uboot-s3c2442.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2442.patch	2007-10-18 06:06:17 UTC (rev 3215)
+++ trunk/src/target/u-boot/patches/uboot-s3c2442.patch	2007-10-18 06:35:38 UTC (rev 3216)
@@ -20,7 +20,7 @@
  #define CLKDIVN_1_4_8	0x05
  #define CLKDIVN_1_3_6	0x07
  #endif
-@@ -142,6 +142,49 @@
+@@ -142,6 +142,67 @@
  #error "clock frequencies != 12MHz / 16.9344MHz not supported"
  #endif
  };
@@ -43,11 +43,20 @@
 +		.camdivn = 0,
 +	},
 +	{
++		/* Make sure you are running at 1.4VDDiarm if you use this mode*/
 +		.mhz = 400,
 +		.mpllcon = ((42 << 12) + (1 << 4) + 0),
 +		.clkdivn = CLKDIVN_1_4_8,
 +		.camdivn = 0,
 +	},
++	{
++		/* This is MSP54 specific, as per openmoko calculations */
++		/* Make sure you are running at 1.7VDDiarm if you use this mode*/
++		.mhz = 500,
++		.mpllcon = ((96 << 12) + (3 << 4) + 0),
++		.clkdivn = CLKDIVN_1_4_8,
++		.camdivn = 0,
++	},
 +#elif (CONFIG_SYS_CLK_FREQ == 16934400)
 +static const u_int32_t upllcon = ((26 << 12) + (4 << 4) + 1);
 +static const struct s3c24x0_pll_speed pll_configs[] = {
@@ -58,11 +67,20 @@
 +		.camdivn = 0,
 +	},
 +	{
++		/* Make sure you are running at 1.4VDDiarm if you use this mode*/
 +		.mhz = 400,
 +		.mpllcon = ((63 << 12) + (4 << 4) + 0),
 +		.clkdivn = CLKDIVN_1_4_8,
 +		.camdivn = 0,
 +	},
++	{
++		/* This is MSP54 specific, as per data sheet. */
++		/* Make sure you are running at 1.7VDDiarm if you use this mode*/
++		.mhz = 500,
++		.mpllcon = ((110 << 12) + (2 << 4) + 1),
++		.clkdivn = CLKDIVN_1_4_8,
++		.camdivn = 0,
++	},
 +#else
 +#error "clock frequencies != 12MHz / 16.9344MHz not supported"
 +#endif
@@ -392,7 +410,7 @@
  #include <s3c2440.h>
  #endif
  #include <status_led.h>
-@@ -158,14 +158,15 @@
+@@ -163,14 +163,15 @@
  	bne	copyex
  #endif
  
@@ -410,7 +428,7 @@
  #  define pWTCON		0x53000000
  #  define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
  #  define INTSUBMSK	0x4A00001C
-@@ -188,6 +189,17 @@
+@@ -193,6 +194,17 @@
  #endif
  # define CLKDIVN_val	7 /* FCLK:HCLK:PCLK = 1:3:6 */
  # define CAMDIVN	0x4C000018
@@ -428,7 +446,7 @@
  #endif
  
  	ldr     r0, =pWTCON
-@@ -200,13 +212,13 @@
+@@ -205,13 +217,13 @@
  	mov	r1, #0xffffffff
  	ldr	r0, =INTMSK
  	str	r1, [r0]
@@ -444,7 +462,7 @@
  	/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
  	ldr	r0, =CAMDIVN
  	mov	r1, #0
-@@ -272,7 +284,7 @@
+@@ -277,7 +289,7 @@
  	str	r1, [r0, #0x28]
  #endif
  
@@ -453,7 +471,7 @@
  
  #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  #ifndef CONFIG_LL_INIT_NAND_ONLY
-@@ -280,7 +292,7 @@
+@@ -285,7 +297,7 @@
  #endif
  
  #if defined(CONFIG_AT91RM9200) || defined(CONFIG_S3C2410) || \
@@ -462,7 +480,7 @@
  
  #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  	adr	r0, _start		/* r0 <- current position of code   */
-@@ -332,7 +344,7 @@
+@@ -337,7 +349,7 @@
  #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
  	bl	cpu_init_crit
  #endif
@@ -471,7 +489,7 @@
  	/* ensure some refresh has happened */
  	ldr	r1, =0xfffff
  1:	subs	r1, r1, #1
-@@ -343,7 +355,7 @@
+@@ -348,7 +360,7 @@
  	ldr	r0, [ r1 ]
  	tst	r0, #0x02		/* is this resume from power down */
  	ldrne	pc, [r1, #4]		/* gstatus3 */
@@ -480,7 +498,7 @@
  #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  
  	/* mov	r10, lr */
-@@ -368,7 +380,7 @@
+@@ -373,7 +385,7 @@
  	ldr	r2, [r1, #oNFCONF]
  	orr	r2, r2, #0x800		@ disable chip
  	str	r2, [r1, #oNFCONF]
@@ -489,7 +507,7 @@
  	mov	r1, #S3C2440_NAND_BASE
  	ldr	r2, =0xfff0		@ initial value tacls=3,rph0=7,rph1=7
  	ldr	r3, [r1, #oNFCONF]
-@@ -447,7 +459,8 @@
+@@ -452,7 +464,8 @@
  #endif /* CONFIG_S3C2410_NAND_BOOT */
  done_relocate: