r3237 - trunk/src/target/kernel/patches

[laforge at sita.openmoko.org]

Author: laforge
Date: 2007-10-22 10:56:29 +0200 (Mon, 22 Oct 2007)
New Revision: 3237

Modified:
   trunk/src/target/kernel/patches/gta01-jbt6k74.patch
Log:
emove double register settings. Not listed in the data-sheet and it works fine
without them. Looks like a copy-and-paste error. (Stefan Schmidt)


Modified: trunk/src/target/kernel/patches/gta01-jbt6k74.patch
===================================================================
--- trunk/src/target/kernel/patches/gta01-jbt6k74.patch	2007-10-22 08:55:35 UTC (rev 3236)
+++ trunk/src/target/kernel/patches/gta01-jbt6k74.patch	2007-10-22 08:56:29 UTC (rev 3237)
@@ -29,7 +29,7 @@
 ===================================================================
 --- /dev/null
 +++ linux-2.6.22.5-moko/drivers/spi/jbt6k74.c
-@@ -0,0 +1,653 @@
+@@ -0,0 +1,645 @@
 +/* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
 + *
 + * Copyright (C) 2006-2007 by OpenMoko, Inc.
@@ -213,7 +213,6 @@
 +	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
 +	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
 +	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
-+	rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
 +	rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
 +	rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
 +	rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
@@ -234,14 +233,12 @@
 +	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
 +	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
 +	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
-+	rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 +
 +	if (!qvga) {
 +		DEBUGP("entering VGA mode\n");
 +		rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
 +		rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
 +		rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
-+		rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
 +
 +		rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
 +		rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
@@ -264,11 +261,6 @@
 +		rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
 +	}
 +
-+#if 0
-+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
-+	rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
-+#endif
-+
 +	return rc;
 +}
 +