org.openembedded.dev: d935cd87c7c9021470bafc4d24b4faafe4d6c58b

oe at monotone.openmoko.org oe at monotone.openmoko.org
Fri May 2 21:06:13 CEST 2008


revision:            d935cd87c7c9021470bafc4d24b4faafe4d6c58b
date:                2008-05-01T12:53:25
author:              likewise at openembedded.org
branch:              org.openembedded.dev
changelog:
u-boot-1.1.4: Added additional patches from Atmel AT32STK1000 BSP 2.0.0 CD, mostly LCD/splash support.

 u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch   |  112 +
 u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch              |  117 +
 u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch                |   11 
 u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch                      |   16 
 u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch         |  252 ++
 u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch           |  124 +
 u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch            |  163 +
 u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch                         |   98 
 u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch                   |  120 +
 u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch               |   90 
 u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch                          |  101 
 u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch |  670 ++++++
 u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch                         |  755 +++++++
 u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch        |   61 
 u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch                          | 1026 ++++++++++
 u-boot_1.1.4.bb                                                              |   48 


manifest:
format_version "1"

new_manifest [db7364932039bbd546471f3f70e64932d4fa63b2]

old_revision [ab470e95662adb7ab2cc12e234b243e2281bde06]

add_dir "packages/u-boot/u-boot-1.1.4/at32stk1000"

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch"
 content [264148f2ada6a081fe0b2e071b0edc80d5bb26d3]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch"
 content [aacb40f62692f7f12d2594259831635533ea5254]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch"
 content [0dc5903c7cb85cbda2a744d9ded9a86258089d87]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch"
 content [758d34baadad1b76b6ed1ef398709646af1defbf]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch"
 content [0905f155e05eba575a0685462783708b8098af55]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch"
 content [174d54cdd69afafd05d72a0fd0c8751d0976a599]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch"
 content [c9bf5bf83f39696ee9f981ed85f847334f28c2b1]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch"
 content [a1ebfc54a394239909ae56d84e754d7ec80bbac3]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch"
 content [0687dbba73b78ddd353f834a58a26b02ce8f8ef8]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch"
 content [80f5abd078487b50df179cad3b3d1a0f382b56ae]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch"
 content [70b1b5f471490abbf21b2c173a9863794616545c]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch"
 content [055ca79e80417f03df63174afb7a707a2e98e5a6]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch"
 content [87dc7c19ee654a3223802b457bb82c44ff3c515e]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch"
 content [f9cdf2cc1db97cbdcfbb811df1067fb7baec5542]

add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch"
 content [aaf3a5bcf5a60041e4da853c72c9417adca86a12]

patch "packages/u-boot/u-boot_1.1.4.bb"
 from [d038552bd2f9296f6e46ab33c2c4ebb364477fec]
   to [f33798683ca5789d2b3c96f26805a5f148b78370]
-------------- next part --------------
#
#
# add_dir "packages/u-boot/u-boot-1.1.4/at32stk1000"
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch"
#  content [264148f2ada6a081fe0b2e071b0edc80d5bb26d3]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch"
#  content [aacb40f62692f7f12d2594259831635533ea5254]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch"
#  content [0dc5903c7cb85cbda2a744d9ded9a86258089d87]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch"
#  content [758d34baadad1b76b6ed1ef398709646af1defbf]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch"
#  content [0905f155e05eba575a0685462783708b8098af55]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch"
#  content [174d54cdd69afafd05d72a0fd0c8751d0976a599]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch"
#  content [c9bf5bf83f39696ee9f981ed85f847334f28c2b1]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch"
#  content [a1ebfc54a394239909ae56d84e754d7ec80bbac3]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch"
#  content [0687dbba73b78ddd353f834a58a26b02ce8f8ef8]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch"
#  content [80f5abd078487b50df179cad3b3d1a0f382b56ae]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch"
#  content [70b1b5f471490abbf21b2c173a9863794616545c]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch"
#  content [055ca79e80417f03df63174afb7a707a2e98e5a6]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch"
#  content [87dc7c19ee654a3223802b457bb82c44ff3c515e]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch"
#  content [f9cdf2cc1db97cbdcfbb811df1067fb7baec5542]
# 
# add_file "packages/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch"
#  content [aaf3a5bcf5a60041e4da853c72c9417adca86a12]
# 
# patch "packages/u-boot/u-boot_1.1.4.bb"
#  from [d038552bd2f9296f6e46ab33c2c4ebb364477fec]
#    to [f33798683ca5789d2b3c96f26805a5f148b78370]
#
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch	264148f2ada6a081fe0b2e071b0edc80d5bb26d3
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch	264148f2ada6a081fe0b2e071b0edc80d5bb26d3
@@ -0,0 +1,112 @@
+diff -uprN u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c u-boot/cpu/at32ap7xxx/ap7000/devices.c
+--- u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/cpu/at32ap7xxx/ap7000/devices.c	2006-12-22 14:51:26.000000000 +0100
+@@ -223,6 +223,46 @@ static const struct resource macb1_resou
+ 	},
+ };
+ #endif
++#if defined(CFG_SPI0)
++static const struct resource spi0_resource[] = {
++	{
++		.type	= RESOURCE_CLOCK,
++		.u	= {
++			.clock	= { CLOCK_APBA, 0 },
++		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio	= { 6, DEVICE_PIOA, GPIO_FUNC_A, 0 },
++		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio	= { 1, DEVICE_PIOA, GPIO_FUNC_B, 20 },
++		},
++	},
++};
++#endif
++#if defined(CFG_SPI1)
++static const struct resource spi1_resource[] = {
++	{
++		.type	= RESOURCE_CLOCK,
++		.u	= {
++			.clock	= { CLOCK_APBA, 1 },
++		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio	= { 6, DEVICE_PIOB, GPIO_FUNC_B, 0 },
++		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio	= { 1, DEVICE_PIOA, GPIO_FUNC_A, 27 },
++		},
++	},
++};
++#endif
+ #if defined(CFG_LCDC)
+ static const struct resource lcdc_resource[] = {
+ 	{
+@@ -230,6 +270,16 @@ static const struct resource lcdc_resour
+ 		.u	= {
+ 			.clock	= { CLOCK_AHB, 7 },
+ 		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio = { 13, DEVICE_PIOC, GPIO_FUNC_A, 19 },
++		},
++	}, {
++		.type	= RESOURCE_GPIO,
++		.u	= {
++			.gpio = { 18, DEVICE_PIOD, GPIO_FUNC_A, 0 },
++		},
+ 	},
+ };
+ #endif
+@@ -390,6 +440,20 @@ const struct device chip_device[] = {
+ 		.resource	= macb0_resource,
+ 	},
+ #endif
++#if defined(CFG_SPI0)
++	[DEVICE_SPI0] = {
++		.regs		= (void *)SPI0_BASE,
++		.nr_resources	= ARRAY_SIZE(spi0_resource),
++		.resource	= spi0_resource,
++	},
++#endif
++#if defined(CFG_SPI1)
++	[DEVICE_SPI1] = {
++		.regs		= (void *)SPI1_BASE,
++		.nr_resources	= ARRAY_SIZE(spi1_resource),
++		.resource	= spi1_resource,
++	},
++#endif
+ #if defined(CFG_MACB1)
+ 	[DEVICE_MACB1] = {
+ 		.regs		= (void *)MACB1_BASE,
+@@ -399,6 +463,7 @@ const struct device chip_device[] = {
+ #endif
+ #if defined(CFG_LCDC)
+ 	[DEVICE_LCDC] = {
++		.regs		= (void *)LCDC_BASE,
+ 		.nr_resources	= ARRAY_SIZE(lcdc_resource),
+ 		.resource	= lcdc_resource,
+ 	},
+diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/platform.h u-boot/include/asm-avr32/arch-ap7000/platform.h
+--- u-boot-orig/include/asm-avr32/arch-ap7000/platform.h	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/arch-ap7000/platform.h	2006-12-22 14:20:39.000000000 +0100
+@@ -66,6 +66,12 @@ enum device_id {
+ #if defined(CFG_MACB1)
+ 	DEVICE_MACB1,
+ #endif
++#if defined(CFG_SPI0)
++	DEVICE_SPI0,
++#endif
++#if defined(CFG_SPI1)
++	DEVICE_SPI1,
++#endif
+ #if defined(CFG_LCDC)
+ 	DEVICE_LCDC,
+ #endif
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch	aacb40f62692f7f12d2594259831635533ea5254
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch	aacb40f62692f7f12d2594259831635533ea5254
@@ -0,0 +1,117 @@
+Index: u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c
+===================================================================
+--- u-boot-1.1.4.orig/cpu/at32ap7xxx/hsdramc.c	2007-01-11 15:28:40.000000000 +0100
++++ u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c	2007-01-11 15:29:36.000000000 +0100
+@@ -133,6 +133,7 @@
+ 	printf("SDRAM: %u MB at address 0x%08lx\n",
+ 	       sdram_size >> 20, info->phys_addr);
+ 
++#ifdef CONFIG_SDRAM_TEST
+ 	printf("Testing SDRAM...");
+ 	for (i = 0; i < sdram_size / 4; i++)
+ 		sdram[i] = i;
+@@ -148,6 +149,7 @@
+ 	}
+ 
+ 	puts("OK\n");
++#endif
+ 
+ 	return sdram_size;
+ }
+Index: u-boot-1.1.4/include/configs/atngw.h
+===================================================================
+--- u-boot-1.1.4.orig/include/configs/atngw.h	2007-01-11 15:28:40.000000000 +0100
++++ u-boot-1.1.4/include/configs/atngw.h	2007-01-30 16:41:23.000000000 +0100
+@@ -31,6 +31,10 @@
+ 
+ #define CONFIG_NGW_EXT_FLASH		1
+ 
++/* Handy macros for making strings */
++#define xstringify(x) #x
++#define stringify(x) xstringify(x)
++
+ /*
+  * Timer clock frequency. We're using the CPU-internal COUNT register
+  * for this, so this is equivalent to the CPU core clock frequency
+@@ -80,9 +84,9 @@
+ 
+ #define CONFIG_BAUDRATE			115200
+ #define CONFIG_BOOTARGS							\
+-	"console=ttyS0 root=/dev/mmcblk0p1"
++	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
+ #define CONFIG_BOOTCOMMAND						\
+-	"mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000"
++	"fsload 0x90250000 /uImage; bootm 0x90250000"
+ 
+ #define CONFIG_BOOTDELAY		2
+ #define CONFIG_AUTOBOOT			1
+@@ -105,8 +109,8 @@
+  * generated and assigned to the environment variables "ethaddr" and
+  * "eth1addr".
+  */
+-#define CONFIG_ETHADDR			"6a:87:71:14:cd:cb"
+-#define CONFIG_ETH1ADDR			"ca:f8:15:e6:3e:e6"
++#define CONFIG_ETHADDR			"42:b2:13:36:50:94"
++#define CONFIG_ETH1ADDR			"4e:29:49:7e:5c:b9"
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+ #define CONFIG_NET_MULTI		1
+ 
+@@ -183,6 +187,7 @@
+ 
+ #define CFG_SDRAM_BASE			0x10000000
+ #define CFG_SDRAM_16BIT			1
++#define CONFIG_SDRAM_TEST		1
+ 
+ #define CFG_ENV_IS_IN_FLASH		1
+ #define CFG_ENV_SIZE			65536
+@@ -202,7 +207,7 @@
+ #define CFG_DMA_ALLOC_END		(CFG_MALLOC_START)
+ #define CFG_DMA_ALLOC_START		(CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+ /* Allow 2MB for the kernel run-time image */
+-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
++#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00250000)
+ #define CFG_BOOTPARAMS_LEN		(16 * 1024)
+ 
+ /* Other configuration settings that shouldn't have to change all that often */
+Index: u-boot-1.1.4/include/configs/atstk1002.h
+===================================================================
+--- u-boot-1.1.4.orig/include/configs/atstk1002.h	2007-01-11 15:29:36.000000000 +0100
++++ u-boot-1.1.4/include/configs/atstk1002.h	2007-01-30 16:41:25.000000000 +0100
+@@ -98,7 +98,7 @@
+ #define CFG_CONSOLE_UART_DEV		DEVICE_USART1
+ 
+ /* Define to force consol on serial */
+-/* #define CFG_CONSOLE_ALLWAYS_UART	1 */
++#define CFG_CONSOLE_ALLWAYS_UART	1
+ #ifdef CFG_CONSOLE_ALLWAYS_UART
+ #define CFG_CONSOLE_IS_IN_ENV		1
+ #define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+@@ -123,7 +123,7 @@
+ #endif
+ 
+ #define CONFIG_BOOTCOMMAND						\
+-	"mmcinit; ext2load mmc 0:1 /uImage; bootm"
++	"mmcinit; ext2load mmc 0:1 0x90250000 /uImage; bootm 0x90250000"
+ #define CONFIG_BOOTDELAY		2
+ #define CONFIG_AUTOBOOT			1
+ 
+@@ -145,8 +145,8 @@
+  * generated and assigned to the environment variables "ethaddr" and
+  * "eth1addr".
+  */
+-#define CONFIG_ETHADDR			"6a:87:71:14:cd:cb"
+-#define CONFIG_ETH1ADDR			"ca:f8:15:e6:3e:e6"
++#define CONFIG_ETHADDR			"42:b2:13:36:50:94"
++#define CONFIG_ETH1ADDR			"4e:29:49:7e:5c:b9"
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+ #define CONFIG_NET_MULTI		1
+ 
+@@ -233,6 +233,8 @@
+ #define CFG_INTRAM_SIZE			0x8000
+ 
+ #define CFG_SDRAM_BASE			0x10000000
++/* Will do SDRAM test if defined */
++#define CONFIG_SDRAM_TEST		1
+ 
+ #define CFG_ENV_IS_IN_FLASH		1
+ #define CFG_ENV_SIZE			65536
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch	0dc5903c7cb85cbda2a744d9ded9a86258089d87
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch	0dc5903c7cb85cbda2a744d9ded9a86258089d87
@@ -0,0 +1,11 @@
+diff -uprN u-boot-orig/include/asm-avr32/global_data.h u-boot/include/asm-avr32/global_data.h
+--- u-boot-orig/include/asm-avr32/global_data.h	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/global_data.h	2006-12-19 11:08:14.000000000 +0100
+@@ -44,6 +44,7 @@ typedef	struct	global_data {
+ 	unsigned long	env_addr;	/* Address of env struct */
+ 	unsigned long	env_valid;	/* Checksum of env valid? */
+ 	unsigned long	cpu_hz;		/* TODO: remove */
++	unsigned long	fb_base;	/* Address to framebuffer */
+ 	void		**jt;
+ } gd_t;
+ 
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch	758d34baadad1b76b6ed1ef398709646af1defbf
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch	758d34baadad1b76b6ed1ef398709646af1defbf
@@ -0,0 +1,16 @@
+diff -uprN u-boot-orig/include/asm-avr32/initcalls.h u-boot/include/asm-avr32/initcalls.h
+--- u-boot-orig/include/asm-avr32/initcalls.h	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/initcalls.h	2007-01-05 13:29:16.000000000 +0100
+@@ -30,6 +30,12 @@ extern void board_init_memories(void);
+ extern void board_init_pio(void);
+ extern void board_init_info(void);
+ 
++#if CONFIG_SPI
++extern void board_init_spi(void);
++#else
++static inline void board_init_spi(void) { }
++#endif
++
+ #if (CONFIG_COMMANDS & CFG_CMD_NET)
+ extern void net_init(void);
+ #else
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch	0905f155e05eba575a0685462783708b8098af55
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch	0905f155e05eba575a0685462783708b8098af55
@@ -0,0 +1,252 @@
+diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/sm.h u-boot/include/asm-avr32/arch-ap7000/sm.h
+--- u-boot-orig/include/asm-avr32/arch-ap7000/sm.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/asm-avr32/arch-ap7000/sm.h	2006-12-21 16:28:04.000000000 +0100
+@@ -0,0 +1,248 @@
++/*
++ * Register definitions for SM
++ *
++ * System Manager
++ */
++#ifndef __ASM_AVR32_SM_H__
++#define __ASM_AVR32_SM_H__
++
++/* SM register offsets */
++#define SM_PM_MCCTRL                            0x0000
++#define SM_PM_CKSEL                             0x0004
++#define SM_PM_CPU_MASK                          0x0008
++#define SM_PM_AHB_MASK                          0x000c
++#define SM_PM_APBA_MASK                         0x0010
++#define SM_PM_APBB_MASK                         0x0014
++#define SM_PM_PLL0                              0x0020
++#define SM_PM_PLL1                              0x0024
++#define SM_PM_VCTRL                             0x0030
++#define SM_PM_VMREF                             0x0034
++#define SM_PM_VMV                               0x0038
++#define SM_PM_IER                               0x0040
++#define SM_PM_IDR                               0x0044
++#define SM_PM_IMR                               0x0048
++#define SM_PM_ISR                               0x004c
++#define SM_PM_ICR                               0x0050
++#define SM_PM_GCCTRL                            0x0060
++#define SM_PM_GCCTRL0                           0x0060
++#define SM_PM_GCCTRL1                           0x0064
++#define SM_PM_GCCTRL2                           0x0068
++#define SM_PM_GCCTRL3                           0x006c
++#define SM_PM_GCCTRL4                           0x0070
++#define SM_PM_GCCTRL5                           0x0074
++#define SM_PM_GCCTRL6                           0x0078
++#define SM_PM_GCCTRL7                           0x007c
++#define SM_RTC_CTRL                             0x0080
++#define SM_RTC_VAL                              0x0084
++#define SM_RTC_TOP                              0x0088
++#define SM_RTC_IER                              0x0090
++#define SM_RTC_IDR                              0x0094
++#define SM_RTC_IMR                              0x0098
++#define SM_RTC_ISR                              0x009c
++#define SM_RTC_ICR                              0x00a0
++#define SM_WDT_CTRL                             0x00b0
++#define SM_WDT_CLR                              0x00b4
++#define SM_WDT_EXT                              0x00b8
++#define SM_RC_RCAUSE                            0x00c0
++#define SM_EIM_IER                              0x0100
++#define SM_EIM_IDR                              0x0104
++#define SM_EIM_IMR                              0x0108
++#define SM_EIM_ISR                              0x010c
++#define SM_EIM_ICR                              0x0110
++#define SM_EIM_MODE                             0x0114
++#define SM_EIM_EDGE                             0x0118
++#define SM_EIM_LEVEL                            0x011c
++#define SM_EIM_TEST                             0x0120
++#define SM_EIM_NMIC                             0x0124
++
++/* Bitfields in PM_MCCTRL */
++
++/* Bitfields in PM_CKSEL */
++#define SM_CPUSEL_OFFSET                        0
++#define SM_CPUSEL_SIZE                          3
++#define SM_CPUDIV_OFFSET                        7
++#define SM_CPUDIV_SIZE                          1
++#define SM_AHBSEL_OFFSET                        8
++#define SM_AHBSEL_SIZE                          3
++#define SM_AHBDIV_OFFSET                        15
++#define SM_AHBDIV_SIZE                          1
++#define SM_APBASEL_OFFSET                       16
++#define SM_APBASEL_SIZE                         3
++#define SM_APBADIV_OFFSET                       23
++#define SM_APBADIV_SIZE                         1
++#define SM_APBBSEL_OFFSET                       24
++#define SM_APBBSEL_SIZE                         3
++#define SM_APBBDIV_OFFSET                       31
++#define SM_APBBDIV_SIZE                         1
++
++/* Bitfields in PM_CPU_MASK */
++
++/* Bitfields in PM_AHB_MASK */
++
++/* Bitfields in PM_APBA_MASK */
++
++/* Bitfields in PM_APBB_MASK */
++
++/* Bitfields in PM_PLL0 */
++#define SM_PLLEN_OFFSET                         0
++#define SM_PLLEN_SIZE                           1
++#define SM_PLLOSC_OFFSET                        1
++#define SM_PLLOSC_SIZE                          1
++#define SM_PLLOPT_OFFSET                        2
++#define SM_PLLOPT_SIZE                          3
++#define SM_PLLDIV_OFFSET                        8
++#define SM_PLLDIV_SIZE                          8
++#define SM_PLLMUL_OFFSET                        16
++#define SM_PLLMUL_SIZE                          8
++#define SM_PLLCOUNT_OFFSET                      24
++#define SM_PLLCOUNT_SIZE                        6
++#define SM_PLLTEST_OFFSET                       31
++#define SM_PLLTEST_SIZE                         1
++
++/* Bitfields in PM_PLL1 */
++
++/* Bitfields in PM_VCTRL */
++#define SM_VAUTO_OFFSET                         0
++#define SM_VAUTO_SIZE                           1
++#define SM_PM_VCTRL_VAL_OFFSET                  8
++#define SM_PM_VCTRL_VAL_SIZE                    7
++
++/* Bitfields in PM_VMREF */
++#define SM_REFSEL_OFFSET                        0
++#define SM_REFSEL_SIZE                          4
++
++/* Bitfields in PM_VMV */
++#define SM_PM_VMV_VAL_OFFSET                    0
++#define SM_PM_VMV_VAL_SIZE                      8
++
++/* Bitfields in PM_IER */
++
++/* Bitfields in PM_IDR */
++
++/* Bitfields in PM_IMR */
++
++/* Bitfields in PM_ISR */
++
++/* Bitfields in PM_ICR */
++#define SM_LOCK0_OFFSET                         0
++#define SM_LOCK0_SIZE                           1
++#define SM_LOCK1_OFFSET                         1
++#define SM_LOCK1_SIZE                           1
++#define SM_WAKE_OFFSET                          2
++#define SM_WAKE_SIZE                            1
++#define SM_VOK_OFFSET                           3
++#define SM_VOK_SIZE                             1
++#define SM_VMRDY_OFFSET                         4
++#define SM_VMRDY_SIZE                           1
++#define SM_CKRDY_OFFSET                         5
++#define SM_CKRDY_SIZE                           1
++
++/* Bitfields in PM_GCCTRL */
++#define SM_OSCSEL_OFFSET                        0
++#define SM_OSCSEL_SIZE                          1
++#define SM_PLLSEL_OFFSET                        1
++#define SM_PLLSEL_SIZE                          1
++#define SM_CEN_OFFSET                           2
++#define SM_CEN_SIZE                             1
++#define SM_CPC_OFFSET                           3
++#define SM_CPC_SIZE                             1
++#define SM_DIVEN_OFFSET                         4
++#define SM_DIVEN_SIZE                           1
++#define SM_DIV_OFFSET                           8
++#define SM_DIV_SIZE                             8
++
++/* Bitfields in RTC_CTRL */
++#define SM_PCLR_OFFSET                          1
++#define SM_PCLR_SIZE                            1
++#define SM_TOPEN_OFFSET                         2
++#define SM_TOPEN_SIZE                           1
++#define SM_CLKEN_OFFSET                         3
++#define SM_CLKEN_SIZE                           1
++#define SM_PSEL_OFFSET                          8
++#define SM_PSEL_SIZE                            16
++
++/* Bitfields in RTC_VAL */
++#define SM_RTC_VAL_VAL_OFFSET                   0
++#define SM_RTC_VAL_VAL_SIZE                     31
++
++/* Bitfields in RTC_TOP */
++#define SM_RTC_TOP_VAL_OFFSET                   0
++#define SM_RTC_TOP_VAL_SIZE                     32
++
++/* Bitfields in RTC_IER */
++
++/* Bitfields in RTC_IDR */
++
++/* Bitfields in RTC_IMR */
++
++/* Bitfields in RTC_ISR */
++
++/* Bitfields in RTC_ICR */
++#define SM_TOPI_OFFSET                          0
++#define SM_TOPI_SIZE                            1
++
++/* Bitfields in WDT_CTRL */
++#define SM_KEY_OFFSET                           24
++#define SM_KEY_SIZE                             8
++
++/* Bitfields in WDT_CLR */
++
++/* Bitfields in WDT_EXT */
++
++/* Bitfields in RC_RCAUSE */
++#define SM_POR_OFFSET                           0
++#define SM_POR_SIZE                             1
++#define SM_BOD_OFFSET                           1
++#define SM_BOD_SIZE                             1
++#define SM_EXT_OFFSET                           2
++#define SM_EXT_SIZE                             1
++#define SM_WDT_OFFSET                           3
++#define SM_WDT_SIZE                             1
++#define SM_NTAE_OFFSET                          4
++#define SM_NTAE_SIZE                            1
++#define SM_SERP_OFFSET                          5
++#define SM_SERP_SIZE                            1
++
++/* Bitfields in EIM_IER */
++
++/* Bitfields in EIM_IDR */
++
++/* Bitfields in EIM_IMR */
++
++/* Bitfields in EIM_ISR */
++
++/* Bitfields in EIM_ICR */
++
++/* Bitfields in EIM_MODE */
++
++/* Bitfields in EIM_EDGE */
++#define SM_INT0_OFFSET                          0
++#define SM_INT0_SIZE                            1
++#define SM_INT1_OFFSET                          1
++#define SM_INT1_SIZE                            1
++#define SM_INT2_OFFSET                          2
++#define SM_INT2_SIZE                            1
++#define SM_INT3_OFFSET                          3
++#define SM_INT3_SIZE                            1
++
++/* Bitfields in EIM_LEVEL */
++
++/* Bitfields in EIM_TEST */
++#define SM_TESTEN_OFFSET                        31
++#define SM_TESTEN_SIZE                          1
++
++/* Bitfields in EIM_NMIC */
++#define SM_EN_OFFSET                            0
++#define SM_EN_SIZE                              1
++
++/* Bit manipulation macros */
++#define SM_BIT(name)                            (1 << SM_##name##_OFFSET)
++#define SM_BF(name,value)                       (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
++#define SM_BFEXT(name,value)                    (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
++#define SM_BFINS(name,value,old)                (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
++
++/* Register access macros */
++#define sm_readl(port,reg)                      readl((port)->regs + SM_##reg)
++#define sm_writel(port,reg,value)               writel((value), (port)->regs + SM_##reg)
++
++#endif /* __ASM_AVR32_SM_H__ */
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch	174d54cdd69afafd05d72a0fd0c8751d0976a599
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch	174d54cdd69afafd05d72a0fd0c8751d0976a599
@@ -0,0 +1,124 @@
+Index: u-boot-orig/include/configs/atstk1002.h
+===================================================================
+--- u-boot-orig.orig/include/configs/atstk1002.h	2007-01-05 15:58:53.000000000 +0100
++++ u-boot-orig/include/configs/atstk1002.h	2007-01-05 16:04:50.000000000 +0100
+@@ -32,6 +32,10 @@
+ 
+ #define CONFIG_ATSTK1000_EXT_FLASH	1
+ 
++/* Handy macros for making strings */
++#define xstringify(x) #x
++#define stringify(x) xstringify(x)
++
+ /*
+  * Timer clock frequency. We're using the CPU-internal COUNT register
+  * for this, so this is equivalent to the CPU core clock frequency
+@@ -68,10 +72,39 @@
+ #define CFG_USART1			1
+ #define CFG_MMCI			1
+ #define CFG_MACB0			1
+-#define CFG_MACB1			1
++/* #define CFG_MACB1			1 */
++
++/* Enable SPI support */
++#define CONFIG_SPI			1
++#define CONFIG_ATMEL_SPI		1
++#define CFG_SPI0			1
++
++/* Enable LCD support */
++#define CFG_DMAC			1
++#define CFG_LCDC			1
++#define CONFIG_LCD			1
++#define CONFIG_ATMEL_LCDC		1
++#define CONFIG_DISPLAY_LTV350QV		1
++
++/* Setup LCD */
++#define LCD_BPP				LCD_COLOR24
++/* CFG_SDRAM_BASE + 0x00500000 */
++#define CFG_LCD_BASE			0x10500000
++#define CFG_WHITE_ON_BLACK		1
++#define CONFIG_VIDEO_BMP_GZIP		1
++#define CFG_VIDEO_LOGO_MAX_SIZE		262144 /* > 320 * 240 * 3 */
++/* #define CONFIG_SPLASH_SCREEN		1 */
+ 
+ #define CFG_CONSOLE_UART_DEV		DEVICE_USART1
+ 
++/* Define to force consol on serial */
++/* #define CFG_CONSOLE_ALLWAYS_UART	1 */
++#ifdef CFG_CONSOLE_ALLWAYS_UART
++#define CFG_CONSOLE_IS_IN_ENV		1
++#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
++#define CFG_CONSOLE_ENV_OVERWRITE	1
++#endif
++
+ /* User serviceable stuff */
+ #define CONFIG_CMDLINE_TAG		1
+ #define CONFIG_SETUP_MEMORY_TAGS	1
+@@ -80,11 +113,17 @@
+ #define CONFIG_STACKSIZE		(2048)
+ 
+ #define CONFIG_BAUDRATE			115200
++
++#ifdef CFG_LCD_BASE
+ #define CONFIG_BOOTARGS							\
+-	"console=ttyUS0 root=/dev/mmcblk0p1 fbmem=600k"
+-#define CONFIG_BOOTCOMMAND						\
+-	"mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000"
++	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k@" stringify(CFG_LCD_BASE)
++#else
++#define CONFIG_BOOTARGS							\
++	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k"
++#endif
+ 
++#define CONFIG_BOOTCOMMAND						\
++	"mmcinit; ext2load mmc 0:1 /uImage; bootm"
+ #define CONFIG_BOOTDELAY		2
+ #define CONFIG_AUTOBOOT			1
+ 
+@@ -144,7 +183,7 @@
+ 					 /* | CFG_CMD_DIAG */		\
+ 					 /* | CFG_CMD_HWFLOW */		\
+ 					 /* | CFG_CMD_SAVES */		\
+-					 /* | CFG_CMD_SPI */		\
++					 | CFG_CMD_SPI			\
+ 					 /* | CFG_CMD_PING */		\
+ 					 | CFG_CMD_MMC			\
+ 					 /* | CFG_CMD_FAT */		\
+@@ -152,6 +191,7 @@
+ 					 /* | CFG_CMD_ITEST */		\
+ 					 | CFG_CMD_EXT2			\
+ 					 | CFG_CMD_JFFS2		\
++					 | CFG_CMD_BMP			\
+ 		)
+ 
+ #include <cmd_confdefs.h>
+@@ -201,7 +241,7 @@
+ #define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+ 
+ #ifdef CONFIG_ATSTK1000
+-# define CFG_MALLOC_LEN			(256*1024)
++# define CFG_MALLOC_LEN			(512*1024)
+ # define CFG_MALLOC_END							\
+ 	({								\
+ 		DECLARE_GLOBAL_DATA_PTR;				\
+@@ -213,7 +253,7 @@
+ # define CFG_DMA_ALLOC_END		(CFG_MALLOC_START)
+ # define CFG_DMA_ALLOC_START		(CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+ /* Allow 2MB for the kernel run-time image */
+-# define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
++# define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00250000)
+ # define CFG_BOOTPARAMS_LEN		(16 * 1024)
+ #else
+ # define CFG_MALLOC_LEN			(8*1024)
+Index: u-boot-orig/board/atstk1000/atstk1000.c
+===================================================================
+--- u-boot-orig.orig/board/atstk1000/atstk1000.c	2007-01-05 16:02:33.000000000 +0100
++++ u-boot-orig/board/atstk1000/atstk1000.c	2007-01-05 16:04:00.000000000 +0100
+@@ -52,3 +52,7 @@
+ 	gd->bd->bi_phy_id[0] = 0x10;
+ 	gd->bd->bi_phy_id[1] = 0x11;
+ }
++
++#ifdef CFG_CONSOLE_ALLWAYS_UART
++int overwrite_console(void) { return 1; }
++#endif
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch	c9bf5bf83f39696ee9f981ed85f847334f28c2b1
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch	c9bf5bf83f39696ee9f981ed85f847334f28c2b1
@@ -0,0 +1,163 @@
+diff -uprN u-boot-orig/board/atstk1000/ltv350qv.c u-boot/board/atstk1000/ltv350qv.c
+--- u-boot-orig/board/atstk1000/ltv350qv.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/board/atstk1000/ltv350qv.c	2007-01-02 15:17:32.000000000 +0100
+@@ -0,0 +1,147 @@
++/*
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#ifdef CONFIG_LCD
++#ifndef CONFIG_SPI
++#error No SPI controller for LCD setup, enable CFG_SPI
++#endif
++
++#include <spi.h>
++
++#ifdef CONFIG_ATMEL_SPI
++#include <atmel_spi.h>
++#endif
++
++static int ltv350qv_write_reg(u8 reg, u16 val)
++{
++	int ret;
++	u8 buffer[3];
++
++	buffer[0] = 0x74;
++	buffer[1] = 0x00;
++	buffer[2] = reg & 0x7f;
++
++	ret = spi_write(&buffer[0], 1, &buffer[1], 2);
++	if (ret != 3) {
++		printf("spi_write returned %d\n", ret);
++		return -1;
++	}
++
++	buffer[0] = 0x76;
++	buffer[1] = val >> 8;
++	buffer[2] = val;
++
++	ret = spi_write(&buffer[0], 1, &buffer[1], 2);
++	if (ret != 3) {
++		printf("spi_write returned %d\n", ret);
++		return -1;
++	}
++
++	return 0;
++}
++
++#define write_reg(reg, val)				\
++	do {						\
++		ret = ltv350qv_write_reg(reg, val);	\
++		if (ret)				\
++			goto out;			\
++	} while (0)
++
++void ltv350qv_power_on(void)
++{
++	int ret;
++
++#ifdef CONFIG_ATMEL_SPI
++	spi_select_chip(1);
++#endif
++
++	debug ("ltv350qv: do power on sequence\n");
++
++	/* write startup procedure */
++	write_reg(9, 0x0000);
++	udelay(15000);
++	write_reg(9, 0x4000);
++	write_reg(10, 0x2000);
++	write_reg(9, 0x4055);
++	udelay(55000);
++	write_reg(1, 0x409d);
++	write_reg(2, 0x0204);
++	write_reg(3, 0x0100);
++	write_reg(4, 0x3000);
++	write_reg(5, 0x4003);
++	write_reg(6, 0x000a);
++	write_reg(7, 0x0021);
++	write_reg(8, 0x0c00);
++	write_reg(10, 0x0103);
++	write_reg(11, 0x0301);
++	write_reg(12, 0x1f0f);
++	write_reg(13, 0x1f0f);
++	write_reg(14, 0x0707);
++	write_reg(15, 0x0307);
++	write_reg(16, 0x0707);
++	write_reg(17, 0x0000);
++	write_reg(18, 0x0004);
++	write_reg(19, 0x0000);
++
++	udelay(20000);
++	write_reg(9, 0x4a55);
++	write_reg(5, 0x5003);
++
++	debug ("ltv350qv: power on sequence done\n");
++out:
++	return;
++}
++
++void ltv350qv_power_off(void)
++{
++	int ret;
++
++#ifdef CONFIG_ATMEL_SPI
++	spi_select_chip(1);
++#endif
++
++	debug ("ltv350qv: do power off sequence\n");
++	/* GON -> 0, POC -> 0 */
++	write_reg(9, 0x4055);
++	/* DSC -> 0 */
++	write_reg(5, 0x4003);
++	/* VCOMG -> 0 */
++	write_reg(10, 0x2103);
++
++	udelay(1000000);
++
++	/* AP[2:0] -> 000 */
++	write_reg(9, 0x4050);
++
++	debug ("ltv350qv: power off sequence done\n");
++out:
++	return;
++}
++
++void ltv350qv_init(void)
++{
++	debug ("ltv350qv: initializing LTV350QV panel\n");
++	ltv350qv_power_on();
++}
++
++#endif
+diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile
+--- u-boot-orig/board/atstk1000/Makefile	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/board/atstk1000/Makefile	2007-01-01 16:23:12.000000000 +0100
+@@ -30,7 +30,7 @@ endif
+ 
+ LIB		:= lib$(BOARD).a
+ 
+-SRC		:= $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c
++SRC		:= $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ltv350qv.c
+ SRC		+= spi.c
+ OBJS		:= $(addsuffix .o,$(basename $(SRC)))
+ 
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch	a1ebfc54a394239909ae56d84e754d7ec80bbac3
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch	a1ebfc54a394239909ae56d84e754d7ec80bbac3
@@ -0,0 +1,98 @@
+diff -uprN u-boot-orig/board/atstk1000/spi.c u-boot/board/atstk1000/spi.c
+--- u-boot-orig/board/atstk1000/spi.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/board/atstk1000/spi.c	2007-01-03 08:46:36.000000000 +0100
+@@ -0,0 +1,83 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#include <spi.h>
++#include <asm/io.h>
++#include <atmel_spi.h>
++
++extern void ltv350qv_init(void);
++
++static struct spi_options_t cs0 = {
++	.reg		= 0,
++	.baudrate	= 200000,
++	.bits		= 8,
++	.spck_delay	= 0,
++	.trans_delay	= 0,
++	.stay_act	= 1,
++	.spi_mode	= 3,
++};
++static struct spi_options_t cs1 = {
++	.reg		= 1,
++	.baudrate	= 1500000,
++	.bits		= 8,
++	.spck_delay	= 0,
++	.trans_delay	= 0,
++	.stay_act	= 1,
++	.spi_mode	= 3,
++};
++
++void spi_chipsel_dac(int cs)
++{
++	if (cs) spi_select_chip(0);
++	else spi_unselect_chip(0);
++}
++
++void spi_chipsel_lcd(int cs)
++{
++	if (cs) spi_select_chip(1);
++	else spi_unselect_chip(1);
++}
++
++spi_chipsel_type spi_chipsel[] = {
++	spi_chipsel_dac,
++	spi_chipsel_lcd,
++};
++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
++
++void board_init_spi(void)
++{
++	int ret;
++
++	spi_init();
++
++	ret = spi_setup_chip_reg(&cs0, 45000000); /* TODO: get APBA speed */
++	if (ret)
++		return;
++	ret = spi_setup_chip_reg(&cs1, 45000000); /* TODO: get APBA speed */
++	if (ret)
++		return;
++
++	spi_enable();
++
++	ltv350qv_init();
++}
+diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile
+--- u-boot-orig/board/atstk1000/Makefile	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/board/atstk1000/Makefile	2007-01-01 16:23:12.000000000 +0100
+@@ -31,6 +31,7 @@ endif
+ LIB		:= lib$(BOARD).a
+ 
+ SRC		:= $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c
++SRC		+= spi.c
+ OBJS		:= $(addsuffix .o,$(basename $(SRC)))
+ 
+ .PHONY: all
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch	0687dbba73b78ddd353f834a58a26b02ce8f8ef8
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch	0687dbba73b78ddd353f834a58a26b02ce8f8ef8
@@ -0,0 +1,120 @@
+Index: u-boot-orig/board/atmel/ngw/flash.c
+===================================================================
+--- u-boot-orig.orig/board/atmel/ngw/flash.c	2007-01-03 11:31:44.000000000 +0100
++++ u-boot-orig/board/atmel/ngw/flash.c	2007-01-03 11:33:13.000000000 +0100
+@@ -161,7 +161,7 @@
+ {
+ 	unsigned long flags;
+ 	uint16_t *base, *p, *s, *end;
+-	uint16_t word, status;
++	uint16_t word, status,status1;
+ 	int ret = ERR_OK;
+ 
+ 	if (addr < info->start[0]
+@@ -196,20 +196,36 @@
+ 		sync_write_buffer();
+ 
+ 		/* Wait for completion */
+-		do {
++        status1 = readw(p);
++        do {
+ 			/* TODO: Timeout */
+-			status = readw(p);
+-		} while ((status != word) && !(status & 0x28));
+-
++            status = status1;
++            status1=readw(p);
++        } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled
++                 !(status1 & 0x28) // status is "working"
++                );
++
++        // We'll need to check once again for toggle bit because the toggle bit
++        // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9)
++        status1=readw(p);
++        status=readw(p);
++        if ((status ^ status1) & 0x40)
++        {
++			printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n",
++			       p, status,word);
++            ret = ERR_PROG_ERROR;
++            writew(0xf0, base);
++            readw(base);
++            break;
++        }
++        // we can now verify status==word if we want to.
++
++        // is this Product ID Exit command really required??
++        // --If configuration is 00 (the default) the device is allready in read mode,
++        // and the instruction is not required!
+ 		writew(0xf0, base);
+ 		readw(base);
+ 
+-		if (status != word) {
+-			printf("Flash write error at address 0x%p: 0x%02x\n",
+-			       p, status);
+-			ret = ERR_PROG_ERROR;
+-			break;
+-		}
+ 	}
+ 
+ 	local_irq_restore(flags);
+Index: u-boot-orig/board/atstk1000/flash.c
+===================================================================
+--- u-boot-orig.orig/board/atstk1000/flash.c	2007-01-03 11:31:44.000000000 +0100
++++ u-boot-orig/board/atstk1000/flash.c	2007-01-03 11:33:13.000000000 +0100
+@@ -160,7 +160,7 @@
+ {
+ 	unsigned long flags;
+ 	uint16_t *base, *p, *s, *end;
+-	uint16_t word, status;
++	uint16_t word, status,status1;
+ 	int ret = ERR_OK;
+ 
+ 	if (addr < info->start[0]
+@@ -195,20 +195,36 @@
+ 		sync_write_buffer();
+ 
+ 		/* Wait for completion */
+-		do {
++        status1 = readw(p);
++        do {
+ 			/* TODO: Timeout */
+-			status = readw(p);
+-		} while ((status != word) && !(status & 0x28));
+-
++            status = status1;
++            status1=readw(p);
++        } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled
++                 !(status1 & 0x28) // status is "working"
++                );
++
++        // We'll need to check once again for toggle bit because the toggle bit
++        // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9)
++        status1=readw(p);
++        status=readw(p);
++        if ((status ^ status1) & 0x40)
++        {
++			printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n",
++			       p, status,word);
++            ret = ERR_PROG_ERROR;
++            writew(0xf0, base);
++            readw(base);
++            break;
++        }
++        // we can now verify status==word if we want to.
++
++        // is this Product ID Exit command really required??
++        // --If configuration is 00 (the default) the device is allready in read mode,
++        // and the instruction is not required!
+ 		writew(0xf0, base);
+ 		readw(base);
+ 
+-		if (status != word) {
+-			printf("Flash write error at address 0x%p: 0x%02x\n",
+-			       p, status);
+-			ret = ERR_PROG_ERROR;
+-			break;
+-		}
+ 	}
+ 
+ 	local_irq_restore(flags);
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch	80f5abd078487b50df179cad3b3d1a0f382b56ae
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch	80f5abd078487b50df179cad3b3d1a0f382b56ae
@@ -0,0 +1,90 @@
+Index: u-boot-orig/common/cmd_bmp.c
+===================================================================
+--- u-boot-orig.orig/common/cmd_bmp.c	2007-01-05 14:50:55.000000000 +0100
++++ u-boot-orig/common/cmd_bmp.c	2007-01-05 15:59:21.000000000 +0100
+@@ -176,13 +176,83 @@
+  */
+ static int bmp_display(ulong addr, int x, int y)
+ {
++	int ret;
++#ifdef CONFIG_VIDEO_BMP_GZIP
++	bmp_image_t *bmp = (bmp_image_t *)addr;
++	unsigned char *dst = NULL;
++	ulong len;
++
++	if (!((bmp->header.signature[0]=='B') &&
++	      (bmp->header.signature[1]=='M'))) {
++
++		/*
++		 * Decompress bmp image
++		 */
++		len = CFG_VIDEO_LOGO_MAX_SIZE;
++		dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
++		if (dst == NULL) {
++			printf("Error: malloc in gunzip failed!\n");
++			return(1);
++		}
++		if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
++			free(dst);
++			printf("There is no valid bmp file at the given address\n");
++			return(1);
++		}
++		if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
++			printf("Image could be truncated "
++					"(increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
++		}
++
++		/*
++		 * Set addr to decompressed image
++		 */
++		bmp = (bmp_image_t *)dst;
++
++		/*
++		 * Check for bmp mark 'BM'
++		 */
++		if (!((bmp->header.signature[0] == 'B') &&
++		      (bmp->header.signature[1] == 'M'))) {
++			printf("There is no valid bmp file at the given address\n");
++			free(dst);
++			return(1);
++		}
++	}
++
++	if (dst) {
++		addr = (ulong)dst;
++	}
++#endif /* CONFIG_VIDEO_BMP_GZIP */
++
+ #if defined(CONFIG_LCD)
+ 	extern int lcd_display_bitmap (ulong, int, int);
+ 
+-	return (lcd_display_bitmap (addr, x, y));
++	ret = lcd_display_bitmap (addr, x, y);
++	if (ret) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		free(dst);
++#endif
++		return ret;
++	}
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		free(dst);
++#endif
++	return 0;
++
+ #elif defined(CONFIG_VIDEO)
+ 	extern int video_display_bitmap (ulong, int, int);
+-	return (video_display_bitmap (addr, x, y));
++	ret = video_display_bitmap (addr, x, y);
++	if (ret) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		free(dst);
++#endif
++		return ret;
++	}
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		free(dst);
++#endif
++	return 0;
+ #else
+ # error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
+ #endif
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch	70b1b5f471490abbf21b2c173a9863794616545c
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch	70b1b5f471490abbf21b2c173a9863794616545c
@@ -0,0 +1,101 @@
+---
+ cpu/at32ap7xxx/mmc.c |   58 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+Index: u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c
+===================================================================
+--- u-boot-1.1.4-avr32.orig/cpu/at32ap7xxx/mmc.c	2007-01-30 14:53:33.000000000 +0100
++++ u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c	2007-01-30 15:45:37.000000000 +0100
+@@ -67,6 +67,7 @@ struct mmci {
+ 	unsigned int rca;
+ 	block_dev_desc_t blkdev;
+ 	const struct device *dev;
++	int card_is_sd;
+ };
+ 
+ struct mmci mmci = {
+@@ -391,6 +392,8 @@ static int sd_init_card(struct mmci *mmc
+ 	mmc->rca = resp[0] >> 16;
+ 	if (verbose)
+ 		printf("SD Card detected (RCA %u)\n", mmc->rca);
++	mmc->card_is_sd = 1;
++
+ 	return 0;
+ }
+ 
+@@ -425,6 +428,57 @@ static int mmc_init_card(struct mmci *mm
+ 	return ret;
+ }
+ 
++static void mci_set_data_timeout(struct mmci *mmc, struct mmc_csd *csd)
++{
++	static const unsigned int dtomul_to_shift[] = {
++		0, 4, 7, 8, 10, 12, 16, 20,
++	};
++	static const unsigned int taac_exp[] = {
++		1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
++	};
++	static const unsigned int taac_mant[] = {
++		0,  10, 12, 13, 15, 60, 25, 30,
++		35, 40, 45, 50, 55, 60, 70, 80,
++	};
++	unsigned int timeout_ns, timeout_clks;
++	unsigned int e, m;
++	unsigned int dtocyc, dtomul;
++	u32 dtor;
++
++	e = csd->taac & 0x07;
++	m = (csd->taac >> 3) & 0x0f;
++
++	timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
++	timeout_clks = csd->nsac * 100;
++
++	timeout_clks += (((timeout_ns + 9) / 10)
++			 * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000;
++	if (!mmc->card_is_sd)
++		timeout_clks *= 10;
++	else
++		timeout_clks *= 100;
++
++	dtocyc = timeout_clks;
++	dtomul = 0;
++	while (dtocyc > 15 && dtomul < 8) {
++		dtomul++;
++		dtocyc = timeout_clks >> dtomul_to_shift[dtomul];
++	}
++
++	if (dtomul >= 8) {
++		dtomul = 7;
++		dtocyc = 15;
++		puts("Warning: Using maximum data timeout\n");
++	}
++
++	dtor = (MMCI_MKBF(MCI_DTOR_DTOMUL, dtomul)
++		| MMCI_MKBF(MCI_DTOR_DTOCYC, dtocyc));
++	mmci_writel(&mmci, MCI_DTOR, dtor);
++
++	printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
++	       dtocyc << dtomul_to_shift[dtomul], dtor);
++}
++
+ int mmc_init(int verbose)
+ {
+ 	struct mmc_cid cid;
+@@ -443,6 +497,8 @@ int mmc_init(int verbose)
+ 	mmci_writel(&mmci, MCI_IDR, ~0UL);
+ 	mci_set_mode(CFG_MMC_CLK_OD, CFG_MMC_BLKLEN);
+ 
++	mmci.card_is_sd = 0;
++
+ 	ret = sd_init_card(&mmci, &cid, verbose);
+ 	if (ret) {
+ 		mmci.rca = MMC_DEFAULT_RCA;
+@@ -458,6 +514,8 @@ int mmc_init(int verbose)
+ 	if (verbose)
+ 		mmc_dump_csd(&csd);
+ 
++	mci_set_data_timeout(&mmci, &csd);
++
+ 	/* Initialize the blockdev structure */
+ 	sprintf(mmci.blkdev.vendor,
+ 		 "Man %02x%04x Snr %08x",
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch	055ca79e80417f03df63174afb7a707a2e98e5a6
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch	055ca79e80417f03df63174afb7a707a2e98e5a6
@@ -0,0 +1,670 @@
+Index: u-boot-1.1.4/common/lcd.c
+===================================================================
+--- u-boot-1.1.4.orig/common/lcd.c	2007-01-11 15:25:03.000000000 +0100
++++ u-boot-1.1.4/common/lcd.c	2007-01-11 15:28:54.000000000 +0100
+@@ -34,6 +34,7 @@
+ #include <command.h>
+ #include <version.h>
+ #include <stdarg.h>
++#include <malloc.h>
+ #include <linux/types.h>
+ #include <devices.h>
+ #if defined(CONFIG_POST)
+@@ -81,6 +82,9 @@
+ extern void lcd_enable (void);
+ static void *lcd_logo (void);
+ 
++#ifdef CONFIG_VIDEO_BMP_GZIP
++extern int gunzip(void *, int, unsigned char *, unsigned long *);
++#endif
+ 
+ #if LCD_BPP == LCD_COLOR8
+ extern void lcd_setcolreg (ushort regno,
+@@ -112,9 +116,12 @@
+ #if 1
+ 	/* Copy up rows ignoring the first one */
+ 	memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+-
+ 	/* Clear the last one */
+ 	memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
++#ifdef CONFIG_AVR32
++	/* flush cache */
++	dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE);
++#endif
+ #else
+ 	/*
+ 	 * Poor attempt to optimize speed by moving "long"s.
+@@ -228,10 +235,23 @@
+ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
+ {
+ 	uchar *dest;
+-	ushort off, row;
++	ushort off, row, bpp, bytespp;
++#ifdef CONFIG_AVR32
++	uchar *dest_start;
++#endif
+ 
+-	dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8);
+-	off  = x * (1 << LCD_BPP) % 8;
++#if (LCD_BPP > LCD_COLOR32)
++	bpp = LCD_BPP;
++#else
++	bpp = 1<<LCD_BPP;
++#endif
++	bytespp = (bpp + 7) / 8;
++
++	dest = (uchar *)(lcd_base + y * lcd_line_length + x * bytespp);
++	off  = x * bytespp * 8 % 8;
++#ifdef CONFIG_AVR32
++	dest_start = dest;
++#endif
+ 
+ 	for (row=0;  row < VIDEO_FONT_HEIGHT;  ++row, dest += lcd_line_length)  {
+ 		uchar *s = str;
+@@ -261,7 +281,17 @@
+ 				bits <<= 1;
+ 			}
+ #elif LCD_BPP == LCD_COLOR16
+-			for (c=0; c<16; ++c) {
++			for (c=0; c<8; ++c) {
++				*d++ = (bits & 0x80) ?
++						lcd_color_fg : lcd_color_bg;
++				bits <<= 1;
++			}
++#elif LCD_BPP == LCD_COLOR24
++			for (c=0; c<8; ++c) {
++				*d++ = (bits & 0x80) ?
++						lcd_color_fg : lcd_color_bg;
++				*d++ = (bits & 0x80) ?
++						lcd_color_fg : lcd_color_bg;
+ 				*d++ = (bits & 0x80) ?
+ 						lcd_color_fg : lcd_color_bg;
+ 				bits <<= 1;
+@@ -271,6 +301,10 @@
+ #if LCD_BPP == LCD_MONOCHROME
+ 		*d  = rest | (*d & ((1 << (8-off)) - 1));
+ #endif
++#ifdef CONFIG_AVR32
++		/* flush cache */
++		dcache_clean_range(dest_start, (int)(d - dest_start));
++#endif
+ 	}
+ }
+ 
+@@ -346,7 +380,11 @@
+ 
+ 	lcd_base = (void *)(gd->fb_base);
+ 
+-	lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
++	if (panel_info.vl_bpix > LCD_COLOR32)
++		lcd_line_length = (panel_info.vl_col * panel_info.vl_bpix) / 8;
++	else
++		lcd_line_length = (panel_info.vl_col
++				* NBITS (panel_info.vl_bpix)) / 8;
+ 
+ 	lcd_init (lcd_base);		/* LCD initialization */
+ 
+@@ -407,6 +445,11 @@
+ 	console_col = 0;
+ 	console_row = 0;
+ 
++#ifdef CONFIG_AVR32
++	/* flush cache */
++	dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE);
++#endif
++
+ 	return (0);
+ }
+ 
+@@ -453,10 +496,17 @@
+ ulong lcd_setmem (ulong addr)
+ {
+ 	ulong size;
+-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
++	int bpp;
++	int line_length;
++	if (panel_info.vl_bpix > LCD_COLOR32)
++		bpp = panel_info.vl_bpix;
++	else
++		bpp = NBITS (panel_info.vl_bpix);
++
++	line_length = (panel_info.vl_col * bpp) / 8;
+ 
+ 	debug ("LCD panel info: %d x %d, %d bit/pix\n",
+-		panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) );
++		panel_info.vl_col, panel_info.vl_row, bpp);
+ 
+ 	size = line_length * panel_info.vl_row;
+ 
+@@ -475,14 +525,22 @@
+ 
+ static void lcd_setfgcolor (int color)
+ {
++#if LCD_BPP <= LCD_COLOR8
+ 	lcd_color_fg = color & 0x0F;
++#else
++	lcd_color_fg = color;
++#endif
+ }
+ 
+ /*----------------------------------------------------------------------*/
+ 
+ static void lcd_setbgcolor (int color)
+ {
++#if LCD_BPP <= LCD_COLOR8
+ 	lcd_color_bg = color & 0x0F;
++#else
++	lcd_color_bg = color;
++#endif
+ }
+ 
+ /*----------------------------------------------------------------------*/
+@@ -509,7 +567,11 @@
+ #ifdef CONFIG_LCD_LOGO
+ void bitmap_plot (int x, int y)
+ {
++#if !defined(CONFIG_ATMEL_LCDC)
+ 	ushort *cmap;
++#else
++	ulong *cmap;
++#endif
+ 	ushort i, j;
+ 	uchar *bmap;
+ 	uchar *fb;
+@@ -519,6 +581,8 @@
+ #elif defined(CONFIG_MPC823)
+ 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ 	volatile cpm8xx_t *cp = &(immr->im_cpm);
++#elif defined(CONFIG_ATMEL_LCDC)
++	struct lcdc_info *cinfo = panel_info.lcdc;
+ #endif
+ 
+ 	debug ("Logo: width %d  height %d  colors %d  cmap %d\n",
+@@ -534,6 +598,8 @@
+ 		cmap = (ushort *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ 		cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
++#elif defined(CONFIG_ATMEL_LCDC)
++		cmap = (ulong *)(cinfo->palette) + BMP_LOGO_OFFSET;
+ #endif
+ 
+ 		WATCHDOG_RESET();
+@@ -541,10 +607,19 @@
+ 		/* Set color map */
+ 		for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
+ 			ushort colreg = bmp_logo_palette[i];
++#if defined(CONFIG_ATMEL_LCDC)
++			/* convert to match palette registers */
++			uchar red   = (colreg >> 8) & 0x0f;
++			uchar green = (colreg >> 4) & 0x0f;
++			uchar blue  = (colreg >> 0) & 0x0f;
++			colreg  = (blue  << 11);
++			colreg |= (green << 6);
++			colreg |= (red   << 1);
++#endif
+ #ifdef  CFG_INVERT_COLORS
+-			*cmap++ = 0xffff - colreg;
++			*(cmap++) = 0xffff - colreg;
+ #else
+-			*cmap++ = colreg;
++			*(cmap++) = colreg;
+ #endif
+ 		}
+ 
+@@ -579,14 +654,16 @@
+  */
+ int lcd_display_bitmap(ulong bmp_image, int x, int y)
+ {
++#if !defined(CONFIG_ATMEL_LCDC)
+ 	ushort *cmap;
++#endif
+ 	ushort i, j;
+ 	uchar *fb;
+ 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+ 	uchar *bmap;
+ 	ushort padded_line;
+ 	unsigned long width, height;
+-	unsigned colors,bpix;
++	unsigned colors,bpix,bpp,bytespp;
+ 	unsigned long compression;
+ #if defined(CONFIG_PXA250)
+ 	struct pxafb_info *fbi = &panel_info.pxa;
+@@ -597,82 +674,126 @@
+ 
+ 	if (!((bmp->header.signature[0]=='B') &&
+ 		(bmp->header.signature[1]=='M'))) {
+-		printf ("Error: no valid bmp image at %lx\n", bmp_image);
++		printf ("[LCD] No valid BMP image at 0x%08lx\n", bmp_image);
+ 		return 1;
+-}
++	}
+ 
+ 	width = le32_to_cpu (bmp->header.width);
+ 	height = le32_to_cpu (bmp->header.height);
++	bpp = le16_to_cpu (bmp->header.bit_count);
+ 	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+ 	compression = le32_to_cpu (bmp->header.compression);
++	bytespp = (panel_info.vl_bpix + 7) / 8;
+ 
+-	bpix = NBITS(panel_info.vl_bpix);
++	if (panel_info.vl_bpix > LCD_COLOR32)
++		bpix = panel_info.vl_bpix;
++	else
++		bpix = NBITS(panel_info.vl_bpix);
+ 
+-	if ((bpix != 1) && (bpix != 8)) {
++	if ((bpix != 1) && (bpix != 8) && (bpix != 24)) {
+ 		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
+ 			bpix);
+ 		return 1;
+ 	}
+ 
+-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
++	if (bpix != bpp) {
+ 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+-			bpix,
+-			le16_to_cpu(bmp->header.bit_count));
++			bpix, bpp);
+ 		return 1;
+ 	}
+ 
+-	debug ("Display-bmp: %d x %d  with %d colors\n",
+-		(int)width, (int)height, (int)colors);
++	debug ("Display-bmp: %d x %d with %d colors (%d bpp)\n",
++		(int)width, (int)height, (int)colors, (int)bpp);
+ 
+-	if (bpix==8) {
++	if (bpix == 8) {
+ #if defined(CONFIG_PXA250)
+ 		cmap = (ushort *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
++#elif defined(CONFIG_ATMEL_LCDC)
++		/* no need to have a palette link, we use lcd_setcolreg */
+ #else
+ # error "Don't know location of color map"
+ #endif
+ 
+ 		/* Set color map */
+ 		for (i=0; i<colors; ++i) {
++#if LCP_BPP <= LCD_COLOR8 /* palette only for 8 bpp and less */
+ 			bmp_color_table_entry_t cte = bmp->color_table[i];
++#endif
++#if !defined(CONFIG_ATMEL_LCDC)
+ 			ushort colreg =
+ 				( ((cte.red)   << 8) & 0xf800) |
+ 				( ((cte.green) << 3) & 0x07e0) |
+ 				( ((cte.blue)  >> 3) & 0x001f) ;
+ #ifdef CFG_INVERT_COLORS
+-			*cmap = 0xffff - colreg;
+-#else
+-			*cmap = colreg;
++			colreg = 0xffff - colreg;
+ #endif
+ #if defined(CONFIG_PXA250)
+-			cmap++;
++			cmap[i] = colreg;
+ #elif defined(CONFIG_MPC823)
+-			cmap--;
++			cmap[colors-i] = colreg;
++#endif
++#else /* CONFIG_ATMEL_LCDC */
++#if LCD_BPP <= LCD_COLOR8
++			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
++#endif
+ #endif
+ 		}
+ 	}
+ 
+-	padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+-	if ((x + width)>panel_info.vl_col)
++	padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3;
++	if ((x + width) > panel_info.vl_col)
+ 		width = panel_info.vl_col - x;
+-	if ((y + height)>panel_info.vl_row)
++	if ((y + height) > panel_info.vl_row)
+ 		height = panel_info.vl_row - y;
+ 
+ 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
+-	fb   = (uchar *) (lcd_base +
+-		(y + height - 1) * lcd_line_length + x);
+-	for (i = 0; i < height; ++i) {
+-		WATCHDOG_RESET();
+-		for (j = 0; j < width ; j++)
++	fb   = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x);
++
++	switch (bpp) {
++	case 24:
++		for (i = 0; i < height; ++i) {
++			WATCHDOG_RESET();
++			for (j = 0; j < width; j++) {
+ #if defined(CONFIG_PXA250)
+-			*(fb++)=*(bmap++);
++#error 24 bpp support not added for PXA250
++#elif defined(CONFIG_ATMEL_LCDC)
++				fb[0] = bmap[0];
++				fb[1] = bmap[1];
++				fb[2] = bmap[2];
++				fb += 3;
++				bmap += 3;
+ #elif defined(CONFIG_MPC823)
+-			*(fb++)=255-*(bmap++);
++#error 24 bpp support not added for MPC823
+ #endif
+-		bmap += (width - padded_line);
+-		fb   -= (width + lcd_line_length);
+-	}
++			}
++			bmap += (width * bytespp - padded_line);
++			fb   -= (width * bytespp + lcd_line_length);
++		}
++		break;
++	case 1: /* pass through */
++	case 8:
++		for (i = 0; i < height; ++i) {
++			WATCHDOG_RESET();
++			for (j = 0; j < width; j++) {
++#if defined(CONFIG_PXA250)
++				*(fb++)=*(bmap++);
++#elif defined(CONFIG_ATMEL_LCDC)
++				*(fb++)=*(bmap++);
++#elif defined(CONFIG_MPC823)
++				*(fb++)=255-*(bmap++);
++#endif
++			}
++			bmap += (width * bytespp - padded_line);
++			fb   -= (width * bytespp + lcd_line_length);
++		}
++		break;
++	default:
++		break;
++	};
++
++	/* TODO: flush fb */
+ 
+ 	return (0);
+ }
+@@ -694,12 +815,68 @@
+ 	static int do_splash = 1;
+ 
+ 	if (do_splash && (s = getenv("splashimage")) != NULL) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		bmp_image_t *bmp;
++		unsigned char *dst = NULL;
++		ulong len;
++#endif
+ 		addr = simple_strtoul(s, NULL, 16);
+ 		do_splash = 0;
+ 
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		bmp = (bmp_image_t *)addr;
++
++		if (!((bmp->header.signature[0]=='B') &&
++		      (bmp->header.signature[1]=='M'))) {
++			len = CFG_VIDEO_LOGO_MAX_SIZE;
++			dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
++			if (dst == NULL) {
++				printf("[LCD] Malloc for gunzip failed!\n");
++				return ((void *)lcd_base);
++			}
++			if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
++						(uchar *)addr, &len) != 0) {
++				free(dst);
++				printf("[LCD] No valid BMP image at 0x%08lx\n",
++						addr);
++				return ((void *)lcd_base);
++			}
++			if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
++				printf("[LCD] Image could be truncated (increase "
++						"CFG_VIDEO_LOGO_MAX_SIZE)!\n");
++			}
++
++			/*
++			 * Set addr to decompressed image
++			 */
++			bmp = (bmp_image_t *)dst;
++
++			/*
++			 * Check for bmp mark 'BM'
++			 */
++			if (!((bmp->header.signature[0] == 'B') &&
++			      (bmp->header.signature[1] == 'M'))) {
++				printf("[LCD] No valid BMP image at 0x%08lx\n",
++						addr);
++				free(dst);
++				return ((void *)lcd_base);
++			}
++
++			addr = (ulong)dst;
++		}
++#endif
+ 		if (lcd_display_bitmap (addr, 0, 0) == 0) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++			if (dst)
++				free(dst);
++#endif
+ 			return ((void *)lcd_base);
+ 		}
++
++#ifdef CONFIG_VIDEO_BMP_GZIP
++		if (dst)
++			free(dst);
++#endif
+ 	}
+ #endif /* CONFIG_SPLASH_SCREEN */
+ 
+Index: u-boot-1.1.4/include/lcd.h
+===================================================================
+--- u-boot-1.1.4.orig/include/lcd.h	2007-01-11 15:25:03.000000000 +0100
++++ u-boot-1.1.4/include/lcd.h	2007-01-11 15:25:38.000000000 +0100
+@@ -148,7 +148,159 @@
+ 
+ extern vidinfo_t panel_info;
+ 
+-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
++#elif defined CONFIG_ATMEL_LCDC
++struct lcdc_bitfield {
++	u32 offset;	/* beginning of bitfield */
++	u32 length;	/* length of bitfield */
++	u32 msb_right;	/* != 0 : Most significant bit is right */
++};
++
++struct lcdc_var_screeninfo {
++	u32 xres;			/* visible resolution		*/
++	u32 yres;
++	u32 xres_virtual;		/* virtual resolution		*/
++	u32 yres_virtual;
++	u32 xoffset;			/* offset from virtual to visible */
++	u32 yoffset;			/* resolution			*/
++
++	u32 bits_per_pixel;		/* guess what			*/
++	u32 grayscale;			/* != 0 Graylevels instead of colors */
++
++	struct lcdc_bitfield red;	/* bitfield in fb mem if true color, */
++	struct lcdc_bitfield green;	/* else only length is significant */
++	struct lcdc_bitfield blue;
++	struct lcdc_bitfield transp;	/* transparency			*/
++
++	u32 nonstd;			/* != 0 Non standard pixel format */
++
++	u32 activate;			/* see FB_ACTIVATE_*		*/
++
++	u32 height;			/* height of picture in mm    */
++	u32 width;			/* width of picture in mm     */
++
++	u32 accel_flags;		/* (OBSOLETE) see fb_info.flags */
++
++	/* Timing: All values in pixclocks, except pixclock (of course) */
++	u32 pixclock;			/* pixel clock in ps (pico seconds) */
++	u32 left_margin;		/* time from sync to picture	*/
++	u32 right_margin;		/* time from picture to sync	*/
++	u32 upper_margin;		/* time from sync to picture	*/
++	u32 lower_margin;
++	u32 hsync_len;		/* length of horizontal sync	*/
++	u32 vsync_len;		/* length of vertical sync	*/
++	u32 sync;			/* see FB_SYNC_*		*/
++	u32 vmode;			/* see FB_VMODE_*		*/
++	u32 rotate;			/* angle we rotate counter clockwise */
++	u32 reserved[5];		/* Reserved for future compatibility */
++};
++
++/*
++ * Atmel LCDC DMA descriptor
++ */
++struct lcdc_dma_descriptor {
++	u_long	fdadr;		/* Frame descriptor address register */
++	u_long	fsadr;		/* Frame source address register */
++	u_long	fidr;		/* Frame ID register */
++	u_long	ldcmd;		/* Command register */
++};
++
++/*
++ * Atmel LCDC info
++ */
++struct lcdc_info {
++	u_long	reg_lccr3;
++	u_long	reg_lccr2;
++	u_long	reg_lccr1;
++	u_long	reg_lccr0;
++	u_long	fdadr0;
++	u_long	fdadr1;
++
++	void	*regs;
++
++	u_long	guard_time;
++	u_long	xres;
++	u_long	yres;
++	u_long	xres_virtual;
++	u_long	yres_virtual;
++	u_long	bits_per_pixel;
++	u_long	smem_start;
++	u_long	line_length;
++	u_long	visual;
++
++	u_long	pixclock;
++	u_long	left_margin;
++	u_long	right_margin;
++	u_long	upper_margin;
++	u_long	lower_margin;
++	u_long	hsync_len;
++	u_long	vsync_len;
++	u_long	sync;
++	u_long	yoffset;
++	u_long	xoffset;
++
++	struct  lcdc_var_screeninfo var;
++
++	/* DMA descriptors */
++	struct	lcdc_dma_descriptor	*dmadesc_fblow;
++	struct	lcdc_dma_descriptor	*dmadesc_fbhigh;
++	struct	lcdc_dma_descriptor	*dmadesc_palette;
++
++	u_long	screen;		/* physical address of frame buffer */
++	u_long	palette;	/* physical address of palette memory */
++	u_int	palette_size;
++
++	/* Device resource */
++	const struct device *dev;
++};
++
++/*
++ * LCD controller stucture for AVR32 CPU
++ */
++typedef struct vidinfo {
++	ushort	vl_col;		/* Number of columns (i.e. 640) */
++	ushort	vl_row;		/* Number of rows (i.e. 480) */
++	ushort	vl_width;	/* Width of display area in millimeters */
++	ushort	vl_height;	/* Height of display area in millimeters */
++
++	/* LCD configuration register */
++	u_char	vl_clkp;	/* Clock polarity */
++	u_char	vl_oep;		/* Output Enable polarity */
++	u_char	vl_hsp;		/* Horizontal Sync polarity */
++	u_char	vl_vsp;		/* Vertical Sync polarity */
++	u_char	vl_dp;		/* Data polarity */
++	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
++	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
++	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
++	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
++	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
++
++	/* Horizontal control register. Timing from data sheet */
++	ushort	vl_hpw;		/* Horz sync pulse width */
++	u_char	vl_blw;		/* Wait before of line */
++	u_char	vl_elw;		/* Wait end of line */
++
++	/* Vertical control register. */
++	u_char	vl_vpw;		/* Vertical sync pulse width */
++	u_char	vl_bfw;		/* Wait before of frame */
++	u_char	vl_efw;		/* Wait end of frame */
++
++	/* Atmel LCDC controller params */
++	struct	lcdc_info *lcdc;
++	u_long	pixclock;
++	u_long	left_margin;
++	u_long	right_margin;
++	u_long	upper_margin;
++	u_long	lower_margin;
++	u_long	hsync_len;
++	u_long	vsync_len;
++	u_long	sync;
++	u_long	yoffset;
++	u_long	xoffset;
++} vidinfo_t;
++
++extern vidinfo_t panel_info;
++
++#endif /* CONFIG_MPC823 or CONFIG_PXA250 or CONFIG_ATMEL_LCDC */
+ 
+ /* Video functions */
+ 
+@@ -184,6 +336,16 @@
+ #define LCD_COLOR4	2
+ #define LCD_COLOR8	3
+ #define LCD_COLOR16	4
++#define LCD_COLOR32	5
++#define LCD_COLOR15	15
++#define LCD_COLOR24	24
++
++#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
++#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
++#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
++#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
++#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
++#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+ 
+ /*----------------------------------------------------------------------*/
+ #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
+@@ -235,7 +397,7 @@
+ # define CONSOLE_COLOR_GREY	14
+ # define CONSOLE_COLOR_WHITE	15	/* Must remain last / highest	*/
+ 
+-#else
++#elif LCD_BPP == LCD_COLOR16
+ 
+ /*
+  * 16bpp color definitions
+@@ -243,6 +405,14 @@
+ # define CONSOLE_COLOR_BLACK	0x0000
+ # define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/
+ 
++#else
++
++/*
++ * 24bpp color definitions
++ */
++# define CONSOLE_COLOR_BLACK	0x000000
++# define CONSOLE_COLOR_WHITE	0xffffff /* Must remain last / highest */
++
+ #endif /* color definitions */
+ 
+ /************************************************************************/
+@@ -274,6 +444,8 @@
+ 				 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
+ #elif LCD_BPP == LCD_COLOR8
+ # define COLOR_MASK(c)		(c)
++#elif LCD_BPP == LCD_COLOR24
++# define COLOR_MASK(c)		(c)
+ #else
+ # error Unsupported LCD BPP.
+ #endif
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch	87dc7c19ee654a3223802b457bb82c44ff3c515e
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch	87dc7c19ee654a3223802b457bb82c44ff3c515e
@@ -0,0 +1,755 @@
+diff -uprN u-boot-orig/include/atmel_lcdc.h u-boot/include/atmel_lcdc.h
+--- u-boot-orig/include/atmel_lcdc.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/atmel_lcdc.h	2006-12-21 16:26:10.000000000 +0100
+@@ -0,0 +1,269 @@
++/*
++ * Register definitions for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ATMEL_LCDC_H__
++#define __ATMEL_LCDC_H__
++
++#define LCDC_CONTRAST_CTR                       0x00000840
++# define LCDC_CONTRAST_CTR_ENA_OFFSET           3
++# define LCDC_CONTRAST_CTR_ENA_SIZE             1
++# define LCDC_CONTRAST_CTR_POL_OFFSET           2
++# define LCDC_CONTRAST_CTR_POL_SIZE             1
++# define LCDC_CONTRAST_CTR_PS_OFFSET            0
++# define LCDC_CONTRAST_CTR_PS_SIZE              2
++#define LCDC_CONTRAST_VAL                       0x00000844
++# define LCDC_CONTRAST_VAL_CVAL_OFFSET          0
++# define LCDC_CONTRAST_VAL_CVAL_SIZE            8
++#define LCDC_DMABADDR1                          0x00000000
++# define LCDC_DMABADDR1_BADDR_U_OFFSET          0
++# define LCDC_DMABADDR1_BADDR_U_SIZE            32
++#define LCDC_DMABADDR2                          0x00000004
++# define LCDC_DMABADDR2_BADDR_L_OFFSET          0
++# define LCDC_DMABADDR2_BADDR_L_SIZE            32
++#define LCDC_DMACON                             0x0000001C
++# define LCDC_DMACON_DMABUSY_OFFSET             2
++# define LCDC_DMACON_DMABUSY_SIZE               1
++# define LCDC_DMACON_DMAEN_OFFSET               0
++# define LCDC_DMACON_DMAEN_SIZE                 1
++# define LCDC_DMACON_DMARST_OFFSET              1
++# define LCDC_DMACON_DMARST_SIZE                1
++# define LCDC_DMACON_DMAUPDT_OFFSET             3
++# define LCDC_DMACON_DMAUPDT_SIZE               1
++# define LCDC_DMACON_DMA2DEN_OFFSET             4
++# define LCDC_DMACON_DMA2DEN_SIZE               1
++#define LCDC_DMAFRMADD1                         0x00000010
++# define LCDC_DMAFRMADD1_FRMADD_U_OFFSET        0
++# define LCDC_DMAFRMADD1_FRMADD_U_SIZE          32
++#define LCDC_DMAFRMADD2                         0x00000014
++# define LCDC_DMAFRMADD2_FRMADD_L_OFFSET        0
++# define LCDC_DMAFRMADD2_FRMADD_L_SIZE          32
++#define LCDC_DMAFRMCFG                          0x00000018
++# define LCDC_DMAFRMCFG_BRSTLEN_OFFSET          24
++# define LCDC_DMAFRMCFG_BRSTLEN_SIZE            7
++# define LCDC_DMAFRMCFG_FRMSIZE_OFFSET          0
++# define LCDC_DMAFRMCFG_FRMSIZE_SIZE            23
++#define LCDC_DMAFRMPT1                          0x00000008
++# define LCDC_DMAFRMPT1_FRMPT_U_OFFSET          0
++# define LCDC_DMAFRMPT1_FRMPT_U_SIZE            23
++#define LCDC_DMAFRMPT2                          0x0000000C
++# define LCDC_DMAFRMPT2_FRMPT_L_OFFSET          0
++# define LCDC_DMAFRMPT2_FRMPT_L_SIZE            23
++#define LCDC_DMA2DCFG                           0x00000020
++# define LCDC_DMA2DCFG_ADDRINC_OFFSET           0
++# define LCDC_DMA2DCFG_ADDRINC_SIZE             16
++# define LCDC_DMA2DCFG_PIXELOFF_OFFSET          24
++# define LCDC_DMA2DCFG_PIXELOFF_SIZE            5
++#define LCDC_DP1_2                              0x0000081C
++# define LCDC_DP1_2_DP1_2_OFFSET                0
++# define LCDC_DP1_2_DP1_2_SIZE                  8
++#define LCDC_DP2_3                              0x00000828
++# define LCDC_DP2_3_DP2_3_OFFSET                0
++# define LCDC_DP2_3_DP2_3_SIZE                  12
++#define LCDC_DP3_4                              0x00000830
++# define LCDC_DP3_4_DP3_4_OFFSET                0
++# define LCDC_DP3_4_DP3_4_SIZE                  16
++#define LCDC_DP3_5                              0x00000824
++# define LCDC_DP3_5_DP3_5_OFFSET                0
++# define LCDC_DP3_5_DP3_5_SIZE                  20
++#define LCDC_DP4_5                              0x00000834
++# define LCDC_DP4_5_DP4_5_OFFSET                0
++# define LCDC_DP4_5_DP4_5_SIZE                  20
++#define LCDC_DP4_7                              0x00000820
++# define LCDC_DP4_7_DP4_7_OFFSET                0
++# define LCDC_DP4_7_DP4_7_SIZE                  28
++#define LCDC_DP5_7                              0x0000082C
++# define LCDC_DP5_7_DP5_7_OFFSET                0
++# define LCDC_DP5_7_DP5_7_SIZE                  28
++#define LCDC_DP6_7                              0x00000838
++# define LCDC_DP6_7_DP6_7_OFFSET                0
++# define LCDC_DP6_7_DP6_7_SIZE                  28
++#define LCDC_LCDCON1                            0x00000800
++# define LCDC_LCDCON1_BYPASS_OFFSET             0
++# define LCDC_LCDCON1_BYPASS_SIZE               1
++# define LCDC_LCDCON1_CLKVAL_OFFSET             12
++# define LCDC_LCDCON1_CLKVAL_SIZE               9
++# define LCDC_LCDCON1_LINECNT_OFFSET            21
++# define LCDC_LCDCON1_LINECNT_SIZE              11
++#define LCDC_LCDCON2                            0x00000804
++# define LCDC_LCDCON2_CLKMOD_OFFSET             15
++# define LCDC_LCDCON2_CLKMOD_SIZE               1
++# define LCDC_LCDCON2_DISTYPE_OFFSET            0
++# define LCDC_LCDCON2_DISTYPE_SIZE              2
++# define LCDC_LCDCON2_IFWIDTH_OFFSET            3
++# define LCDC_LCDCON2_IFWIDTH_SIZE              2
++# define LCDC_LCDCON2_INVCLK_OFFSET             11
++# define LCDC_LCDCON2_INVCLK_SIZE               1
++# define LCDC_LCDCON2_INVDVAL_OFFSET            12
++# define LCDC_LCDCON2_INVDVAL_SIZE              1
++# define LCDC_LCDCON2_INVFRAME_OFFSET           9
++# define LCDC_LCDCON2_INVFRAME_SIZE             1
++# define LCDC_LCDCON2_INVLINE_OFFSET            10
++# define LCDC_LCDCON2_INVLINE_SIZE              1
++# define LCDC_LCDCON2_INVVD_OFFSET              8
++# define LCDC_LCDCON2_INVVD_SIZE                1
++# define LCDC_LCDCON2_MEMOR_OFFSET              30
++# define LCDC_LCDCON2_MEMOR_SIZE                2
++# define LCDC_LCDCON2_PIXELSIZE_OFFSET          5
++# define LCDC_LCDCON2_PIXELSIZE_SIZE            3
++# define LCDC_LCDCON2_SCANMOD_OFFSET            2
++# define LCDC_LCDCON2_SCANMOD_SIZE              1
++#define LCDC_LCDFIFO                            0x00000814
++# define LCDC_LCDFIFO_FIFOTH_OFFSET             0
++# define LCDC_LCDFIFO_FIFOTH_SIZE               16
++#define LCDC_LCDFRMCFG                          0x00000810
++# define LCDC_LCDFRMCFG_LINESIZE_OFFSET         21
++# define LCDC_LCDFRMCFG_LINESIZE_SIZE           11
++# define LCDC_LCDFRMCFG_LINEVAL_OFFSET          0
++# define LCDC_LCDFRMCFG_LINEVAL_SIZE            11
++#define LCDC_LCDMVAL                            0x00000818
++# define LCDC_LCDMVAL_MMODE_OFFSET              31
++# define LCDC_LCDMVAL_MMODE_SIZE                1
++# define LCDC_LCDMVAL_MVAL_OFFSET               0
++# define LCDC_LCDMVAL_MVAL_SIZE                 8
++#define LCDC_LCDTIM1                            0x00000808
++# define LCDC_LCDTIM1_VBP_OFFSET                8
++# define LCDC_LCDTIM1_VBP_SIZE                  8
++# define LCDC_LCDTIM1_VFP_OFFSET                0
++# define LCDC_LCDTIM1_VFP_SIZE                  8
++# define LCDC_LCDTIM1_VHDLY_OFFSET              24
++# define LCDC_LCDTIM1_VHDLY_SIZE                4
++# define LCDC_LCDTIM1_VPW_OFFSET                16
++# define LCDC_LCDTIM1_VPW_SIZE                  6
++#define LCDC_LCDTIM2                            0x0000080C
++# define LCDC_LCDTIM2_HBP_OFFSET                0
++# define LCDC_LCDTIM2_HBP_SIZE                  8
++# define LCDC_LCDTIM2_HFP_OFFSET                21
++# define LCDC_LCDTIM2_HFP_SIZE                  11
++# define LCDC_LCDTIM2_HPW_OFFSET                8
++# define LCDC_LCDTIM2_HPW_SIZE                  6
++#define LCDC_LCD_GPR                            0x0000085C
++# define LCDC_LCD_GPR_GPRB0_OFFSET              0
++# define LCDC_LCD_GPR_GPRB0_SIZE                1
++# define LCDC_LCD_GPR_GPRB1_OFFSET              1
++# define LCDC_LCD_GPR_GPRB1_SIZE                1
++# define LCDC_LCD_GPR_GPRB2_OFFSET              2
++# define LCDC_LCD_GPR_GPRB2_SIZE                1
++# define LCDC_LCD_GPR_GPRB3_OFFSET              3
++# define LCDC_LCD_GPR_GPRB3_SIZE                1
++# define LCDC_LCD_GPR_GPRB4_OFFSET              4
++# define LCDC_LCD_GPR_GPRB4_SIZE                1
++# define LCDC_LCD_GPR_GPRB5_OFFSET              5
++# define LCDC_LCD_GPR_GPRB5_SIZE                1
++# define LCDC_LCD_GPR_GPRB6_OFFSET              6
++# define LCDC_LCD_GPR_GPRB6_SIZE                1
++# define LCDC_LCD_GPR_GPRB7_OFFSET              7
++# define LCDC_LCD_GPR_GPRB7_SIZE                1
++#define LCDC_LCD_ICR                            0x00000858
++# define LCDC_LCD_ICR_EOFIC_OFFSET              2
++# define LCDC_LCD_ICR_EOFIC_SIZE                1
++# define LCDC_LCD_ICR_LNIC_OFFSET               0
++# define LCDC_LCD_ICR_LNIC_SIZE                 1
++# define LCDC_LCD_ICR_LSTLNIC_OFFSET            1
++# define LCDC_LCD_ICR_LSTLNIC_SIZE              1
++# define LCDC_LCD_ICR_MERIC_OFFSET              6
++# define LCDC_LCD_ICR_MERIC_SIZE                1
++# define LCDC_LCD_ICR_OWRIC_OFFSET              5
++# define LCDC_LCD_ICR_OWRIC_SIZE                1
++# define LCDC_LCD_ICR_UFLWIC_OFFSET             4
++# define LCDC_LCD_ICR_UFLWIC_SIZE               1
++#define LCDC_LCD_IDR                            0x0000084C
++# define LCDC_LCD_IDR_EOFID_OFFSET              2
++# define LCDC_LCD_IDR_EOFID_SIZE                1
++# define LCDC_LCD_IDR_LNID_OFFSET               0
++# define LCDC_LCD_IDR_LNID_SIZE                 1
++# define LCDC_LCD_IDR_LSTLNID_OFFSET            1
++# define LCDC_LCD_IDR_LSTLNID_SIZE              1
++# define LCDC_LCD_IDR_MERID_OFFSET              6
++# define LCDC_LCD_IDR_MERID_SIZE                1
++# define LCDC_LCD_IDR_OWRID_OFFSET              5
++# define LCDC_LCD_IDR_OWRID_SIZE                1
++# define LCDC_LCD_IDR_UFLWID_OFFSET             4
++# define LCDC_LCD_IDR_UFLWID_SIZE               1
++#define LCDC_LCD_IER                            0x00000848
++# define LCDC_LCD_IER_EOFIE_OFFSET              2
++# define LCDC_LCD_IER_EOFIE_SIZE                1
++# define LCDC_LCD_IER_LNIE_OFFSET               0
++# define LCDC_LCD_IER_LNIE_SIZE                 1
++# define LCDC_LCD_IER_LSTLNIE_OFFSET            1
++# define LCDC_LCD_IER_LSTLNIE_SIZE              1
++# define LCDC_LCD_IER_MERIE_OFFSET              6
++# define LCDC_LCD_IER_MERIE_SIZE                1
++# define LCDC_LCD_IER_OWRIE_OFFSET              5
++# define LCDC_LCD_IER_OWRIE_SIZE                1
++# define LCDC_LCD_IER_UFLWIE_OFFSET             4
++# define LCDC_LCD_IER_UFLWIE_SIZE               1
++#define LCDC_LCD_IMR                            0x00000850
++# define LCDC_LCD_IMR_EOFIM_OFFSET              2
++# define LCDC_LCD_IMR_EOFIM_SIZE                1
++# define LCDC_LCD_IMR_LNIM_OFFSET               0
++# define LCDC_LCD_IMR_LNIM_SIZE                 1
++# define LCDC_LCD_IMR_LSTLNIM_OFFSET            1
++# define LCDC_LCD_IMR_LSTLNIM_SIZE              1
++# define LCDC_LCD_IMR_MERIM_OFFSET              6
++# define LCDC_LCD_IMR_MERIM_SIZE                1
++# define LCDC_LCD_IMR_OWRIM_OFFSET              5
++# define LCDC_LCD_IMR_OWRIM_SIZE                1
++# define LCDC_LCD_IMR_UFLWIM_OFFSET             4
++# define LCDC_LCD_IMR_UFLWIM_SIZE               1
++#define LCDC_LCD_IRR                            0x00000864
++# define LCDC_LCD_IRR_EOFIR_OFFSET              2
++# define LCDC_LCD_IRR_EOFIR_SIZE                1
++# define LCDC_LCD_IRR_LNIR_OFFSET               0
++# define LCDC_LCD_IRR_LNIR_SIZE                 1
++# define LCDC_LCD_IRR_LSTLNIR_OFFSET            1
++# define LCDC_LCD_IRR_LSTLNIR_SIZE              1
++# define LCDC_LCD_IRR_MERIR_OFFSET              6
++# define LCDC_LCD_IRR_MERIR_SIZE                1
++# define LCDC_LCD_IRR_OWRIR_OFFSET              5
++# define LCDC_LCD_IRR_OWRIR_SIZE                1
++# define LCDC_LCD_IRR_UFLWIR_OFFSET             4
++# define LCDC_LCD_IRR_UFLWIR_SIZE               1
++#define LCDC_LCD_ISR                            0x00000854
++# define LCDC_LCD_ISR_EOFIS_OFFSET              2
++# define LCDC_LCD_ISR_EOFIS_SIZE                1
++# define LCDC_LCD_ISR_LNIS_OFFSET               0
++# define LCDC_LCD_ISR_LNIS_SIZE                 1
++# define LCDC_LCD_ISR_LSTLNIS_OFFSET            1
++# define LCDC_LCD_ISR_LSTLNIS_SIZE              1
++# define LCDC_LCD_ISR_MERIS_OFFSET              6
++# define LCDC_LCD_ISR_MERIS_SIZE                1
++# define LCDC_LCD_ISR_OWRIS_OFFSET              5
++# define LCDC_LCD_ISR_OWRIS_SIZE                1
++# define LCDC_LCD_ISR_UFLWIS_OFFSET             4
++# define LCDC_LCD_ISR_UFLWIS_SIZE               1
++#define LCDC_LCD_ITR                            0x00000860
++# define LCDC_LCD_ITR_EOFIT_OFFSET              2
++# define LCDC_LCD_ITR_EOFIT_SIZE                1
++# define LCDC_LCD_ITR_LNIT_OFFSET               0
++# define LCDC_LCD_ITR_LNIT_SIZE                 1
++# define LCDC_LCD_ITR_LSTLNIT_OFFSET            1
++# define LCDC_LCD_ITR_LSTLNIT_SIZE              1
++# define LCDC_LCD_ITR_MERIT_OFFSET              6
++# define LCDC_LCD_ITR_MERIT_SIZE                1
++# define LCDC_LCD_ITR_OWRIT_OFFSET              5
++# define LCDC_LCD_ITR_OWRIT_SIZE                1
++# define LCDC_LCD_ITR_UFLWIT_OFFSET             4
++# define LCDC_LCD_ITR_UFLWIT_SIZE               1
++#define LCDC_PWRCON                             0x0000083C
++# define LCDC_PWRCON_GUARD_TIME_OFFSET          1
++# define LCDC_PWRCON_GUARD_TIME_SIZE            7
++# define LCDC_PWRCON_LCD_BUSY_OFFSET            31
++# define LCDC_PWRCON_LCD_BUSY_SIZE              1
++# define LCDC_PWRCON_LCD_PWR_OFFSET             0
++# define LCDC_PWRCON_LCD_PWR_SIZE               1
++
++#define LCDC_BIT(name)                          (1 << LCDC_##name##_OFFSET)
++#define LCDC_MKBF(name,value)                   (((value) & ((1 << LCDC_##name##_SIZE) - 1)) << LCDC_##name##_OFFSET)
++#define LCDC_GETBF(name,value)                  (((value) >> LCDC_##name##_OFFSET) & ((1 << LCDC_##name##_SIZE) - 1))
++#define LCDC_INSBF(name,value,old)              (((old) & ~(((1 << LCDC_##name##_SIZE) - 1) << LCDC_##name##_OFFSET)) | LCDC_MKBF(name, value))
++
++#define lcdc_readl(port,reg)		readl((port)->regs + LCDC_##reg)
++#define lcdc_writel(port,reg,value)	writel((value), (port)->regs + LCDC_##reg)
++
++#endif /* __ASM_AVR32_PERIPH_LCDC_H__ */
+diff -uprN u-boot-orig/drivers/atmel_lcdc.c u-boot/drivers/atmel_lcdc.c
+--- u-boot-orig/drivers/atmel_lcdc.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/drivers/atmel_lcdc.c	2007-01-05 12:29:24.000000000 +0100
+@@ -0,0 +1,465 @@
++/*
++ * Framebuffer Driver for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <common.h>
++
++#if defined(CONFIG_ATMEL_LCDC)
++
++#ifndef LCD_BPP
++# define LCD_BPP	LCD_COLOR24
++#endif
++
++#include <lcd.h>
++#include <malloc.h>
++#include <video_fb.h>
++
++#include <atmel_lcdc.h>
++
++#include <asm/io.h>
++#include <asm/arch/sm.h>
++#include <asm/arch/platform.h>
++
++/* Sync defines */
++#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
++#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
++#define FB_SYNC_EXT		4	/* external sync		*/
++#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
++#define FB_SYNC_BROADCAST	16	/* broadcast video timings      */
++/* vtotal = 144d/288n/576i => PAL  */
++/* vtotal = 121d/242n/484i => NTSC */
++#define FB_SYNC_ON_GREEN	32	/* sync on green */
++#define FB_SYNC_PCLK_RISING	64	/* pixel data sampled on rising pclk */
++
++/* More or less configurable parameters */
++#define LCDC_FIFO_SIZE		512
++#define LCDC_DMA_BURST_LEN	8
++
++/* TODO: These should be autogenerated from part description file */
++#define LCDC_DISTYPE_STN_MONO	0
++#define LCDC_DISTYPE_STN_COLOR	1
++#define LCDC_DISTYPE_TFT	2
++#define LCDC_LUT		0xc00
++
++#ifdef CONFIG_DISPLAY_LTV350QV
++/* 320x240x24 @ 75 Hz */
++vidinfo_t panel_info = {
++		vl_col:		320,		/* Number of columns */
++		vl_row:		240,		/* Number of rows */
++		vl_width:	320,		/* Width in mm */
++		vl_height:	240,		/* Height in mm */
++		vl_clkp:	CFG_HIGH,	/* Clock polarity */
++		vl_oep:		CFG_HIGH,	/* Output enable polarity */
++		vl_hsp:		CFG_HIGH,	/* Horizontal sync polarity */
++		vl_vsp:		CFG_HIGH,	/* Vertical sync polarity */
++		vl_dp:		CFG_HIGH,	/* Data polarity */
++		vl_bpix:	LCD_BPP,	/* Bits per pixel */
++		vl_lbw:		1,		/* LCD bus width */
++		vl_splt:	0,		/* Split display? 0=single, 1=dual */
++		vl_clor:	1,		/* Color? 0 = mono, 1 = color */
++		vl_tft:		1,		/* TFT? 0 = passive, 1 = TFT */
++		vl_hpw:		16,		/* Horizontal sync pulse width */
++		vl_blw:		17,		/* Wait before of line */
++		vl_elw:		33,		/* Wait end of line */
++		vl_vpw:		1,		/* Vertical sync pulse width */
++		vl_bfw:		10,		/* Wait before of frame */
++		vl_efw:		10,		/* Wait end of frame */
++
++		pixclock:	145111,
++		left_margin:	17,
++		right_margin:	33,
++		upper_margin:	10,
++		lower_margin:	10,
++		hsync_len:	16,
++		vsync_len:	1,
++		sync:		FB_SYNC_PCLK_RISING,
++		yoffset:	0,
++		xoffset:	0,
++};
++#else
++#error A display must be defined for the LCD controller
++#endif
++
++void lcd_ctrl_init	(void *lcdbase);
++void lcd_enable	(void);
++
++int lcd_line_length;
++int lcd_color_fg;
++int lcd_color_bg;
++
++void *lcd_base;			/* Start of framebuffer memory	*/
++void *lcd_console_address;	/* Start of console buffer	*/
++
++short console_col;
++short console_row;
++
++static int lcdc_init_mem(void *lcdbase);
++void lcdc_init(void *lcdbase);
++
++static inline u_int chan_to_field(u_int chan, const struct lcdc_bitfield *bf)
++{
++	chan &= 0xffff;
++	chan >>= 16 - bf->length;
++	return chan << bf->offset;
++}
++
++/*
++ * ************************************************************************* *
++ *                        Das U-Boot LCD functions                           *
++ * ************************************************************************* *
++ */
++void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
++{
++	struct lcdc_info *cinfo = panel_info.lcdc;
++	u_int *palette = (u_int *)cinfo->palette;
++	u_int val;
++
++	if (cinfo->var.grayscale)
++		red = green = blue = (19595 * red + 38470 * green
++				+ 7471 * blue) >> 16;
++
++	switch (cinfo->visual) {
++	case FB_VISUAL_TRUECOLOR:
++		if (regno < 16) {
++			/* TODO: I do not get why we need a palette here
++			palette = cinfo->pseudo_palette;
++			*/
++
++			val  = chan_to_field(red, &cinfo->var.red);
++			val |= chan_to_field(green, &cinfo->var.green);
++			val |= chan_to_field(blue, &cinfo->var.blue);
++
++			palette[regno] = val;
++		}
++		break;
++
++	case FB_VISUAL_PSEUDOCOLOR:
++		if (regno < 256) {
++			val =  ((blue  << 7) & 0x7c00);
++			val |= ((green << 2) & 0x03e0);
++			val |= ((red   >> 3) & 0x001f);
++
++			/*
++			 * TODO: intensity bit. Maybe something like
++			 *   ~(red[10] ^ green[10] ^ blue[10]) & 1
++			 */
++			palette[regno] = val;
++		}
++		break;
++	}
++}
++
++void lcd_ctrl_init (void *lcdbase)
++{
++	lcdc_init_mem(lcdbase);
++	lcdc_init(lcdbase);
++}
++
++
++
++void lcd_enable (void)
++{
++	return;
++}
++
++ulong calc_fbsize (void)
++{
++	ulong size;
++	int line_length;
++	if (panel_info.vl_bpix > LCD_COLOR32)
++		line_length = panel_info.vl_col * panel_info.vl_bpix / 8;
++	else
++		line_length = panel_info.vl_col * NBITS(panel_info.vl_bpix) / 8;
++
++	size = line_length * panel_info.vl_row;
++	size += PAGE_SIZE;
++
++	return size;
++}
++
++/* ************************************************************************* *
++ *                    Architecture specific functions                        *
++ * ************************************************************************* *
++ */
++static int lcdc_init_mem(void *lcdbase)
++{
++	struct lcdc_info *cinfo;
++	const struct device *dev;
++
++	cinfo = malloc(sizeof(struct lcdc_info));
++	if (!cinfo) {
++		printf("lcdc: could not allocate RAM for lcdc_info\n");
++		return -1;
++	}
++
++	dev = get_device(DEVICE_LCDC);
++	if (!dev)
++		printf("lcdc: could not get LCDC\n");
++
++	cinfo->dev = dev;
++	cinfo->regs = dev->regs;
++
++	cinfo->screen = (u_long)lcdbase;
++	cinfo->palette_size = NBITS(panel_info.vl_bpix) == 8 ? 256 : 16;
++	/* palette is stored in LCD controller IO memory */
++	cinfo->palette = (u_long)cinfo->regs + LCDC_LUT;
++
++	panel_info.lcdc = cinfo;
++
++	return 0;
++}
++
++static void lcdc_update_dma()
++{
++	unsigned long dma_addr;
++	unsigned long pixeloff;
++	unsigned long dma2dcfg;
++	struct lcdc_info *cinfo = panel_info.lcdc;
++
++	dma_addr = (cinfo->smem_start + cinfo->yoffset * cinfo->line_length
++			+ cinfo->xoffset * cinfo->bits_per_pixel / 8);
++
++	dma_addr &= ~3UL;
++	pixeloff = LCDC_MKBF(DMA2DCFG_PIXELOFF, cinfo->xoffset * cinfo->bits_per_pixel);
++
++	/* Set framebuffer DMA base address and pixel offset */
++	lcdc_writel(cinfo, DMABADDR1, dma_addr);
++	dma2dcfg = lcdc_readl(cinfo, DMA2DCFG);
++	dma2dcfg = LCDC_INSBF(DMA2DCFG_PIXELOFF, pixeloff, dma2dcfg);
++	lcdc_writel(cinfo, DMA2DCFG, dma2dcfg);
++
++	/* Update configuration */
++	lcdc_writel(cinfo, DMACON, (lcdc_readl(cinfo, DMACON)
++				| LCDC_BIT(DMACON_DMAUPDT)));
++}
++
++static int lcdc_set_var(struct lcdc_info *info)
++{
++	info->var.red.msb_right = info->var.green.msb_right
++		= info->var.blue.msb_right = 0;
++	info->var.transp.offset = info->var.transp.length = 0;
++
++	switch (info->bits_per_pixel) {
++	case 2:
++	case 4:
++	case 8:
++		info->var.red.offset = info->var.green.offset
++			= info->var.blue.offset = 0;
++		info->var.red.length = info->var.green.length
++			= info->var.blue.length = info->var.bits_per_pixel;
++		break;
++	case 15:
++	case 16:
++		/*
++		 * Bit 16 is the "intensity" bit, I think. Not sure
++		 * what we're going to use that for...
++		 */
++		info->var.red.offset = 0;
++		info->var.green.offset = 5;
++		info->var.blue.offset = 10;
++		info->var.red.length = 5;
++		info->var.green.length = 5;
++		info->var.blue.length = 5;
++		break;
++	case 32:
++		info->var.transp.offset = 24;
++		info->var.transp.length = 8;
++		/* fall through */
++	case 24:
++		info->var.red.offset = 16;
++		info->var.green.offset = 8;
++		info->var.blue.offset = 0;
++		info->var.red.length = info->var.green.length
++			= info->var.blue.length = 8;
++		break;
++	default:
++		printf("lcdc: color depth %d not supported\n",
++		       info->var.bits_per_pixel);
++		return -1;
++	}
++
++	info->var.xoffset = info->var.yoffset = 0;
++	info->var.red.msb_right = info->var.green.msb_right
++		= info->var.blue.msb_right = info->var.transp.msb_right = 0;
++
++	return 0;
++}
++
++void lcdc_init(void *lcdbase)
++{
++	unsigned int value;
++	const struct device *sm;
++	struct lcdc_info *cinfo = panel_info.lcdc;
++
++	sm = get_device(DEVICE_SM);
++	if (!sm)
++		printf("lcdc: could not get SM\n");
++
++	cinfo->xres = panel_info.vl_col;
++	cinfo->yres = panel_info.vl_row;
++	cinfo->xres_virtual = panel_info.vl_col;
++	cinfo->yres_virtual = panel_info.vl_row;
++	if (panel_info.vl_bpix > LCD_COLOR32) {
++		cinfo->bits_per_pixel = panel_info.vl_bpix;
++	} else {
++		cinfo->bits_per_pixel = (1<<panel_info.vl_bpix);
++	}
++	/* INFO: if you see weird offset errors when displaying data
++	 * increase the guard_time */
++	cinfo->guard_time = 2;
++
++	cinfo->pixclock = panel_info.pixclock;
++
++	cinfo->left_margin = panel_info.left_margin;
++	cinfo->right_margin = panel_info.right_margin;
++	cinfo->upper_margin = panel_info.upper_margin;
++	cinfo->lower_margin = panel_info.lower_margin;
++
++	cinfo->hsync_len = panel_info.hsync_len;
++	cinfo->vsync_len = panel_info.vsync_len;
++
++	cinfo->sync = panel_info.sync;
++
++	cinfo->smem_start = (u_long)lcdbase;
++	cinfo->yoffset = panel_info.yoffset;
++	cinfo->xoffset = panel_info.xoffset;
++	cinfo->line_length = cinfo->xres;
++
++	panel_info.lcdc = cinfo;
++
++	if (cinfo->bits_per_pixel <= 8) {
++		cinfo->visual = FB_VISUAL_PSEUDOCOLOR;
++	} else {
++		cinfo->visual = FB_VISUAL_TRUECOLOR;
++	}
++
++	/* setup var information */
++	if (lcdc_set_var(cinfo) != 0) {
++		printf("lcdc: could not set var information\n");
++		return;
++	}
++
++	sm_writel(sm, PM_GCCTRL7, SM_BIT(PLLSEL)|SM_BIT(CEN));
++
++	debug("lcdc: resolution: %ux%u %dbpp (%ux%u virtual)\n",
++			cinfo->xres, cinfo->yres, cinfo->bits_per_pixel,
++			cinfo->xres_virtual, cinfo->yres_virtual);
++
++	/* Turn off the LCD controller and the DMA controller */
++	lcdc_writel(cinfo, PWRCON,
++			LCDC_MKBF(PWRCON_GUARD_TIME, cinfo->guard_time));
++	lcdc_writel(cinfo, DMACON, 0);
++
++	cinfo->line_length = (cinfo->xres_virtual
++			* (cinfo->bits_per_pixel / 8));
++
++	/* Re-initialize the DMA engine... */
++	lcdc_update_dma();
++
++	/* ...set frame size and burst length = 8 words (?) */
++	value = LCDC_MKBF(DMAFRMCFG_FRMSIZE,
++			(cinfo->yres * cinfo->line_length + 3) / 4);
++	value |= LCDC_MKBF(DMAFRMCFG_BRSTLEN, (LCDC_DMA_BURST_LEN - 1));
++	lcdc_writel(cinfo, DMAFRMCFG, value);
++
++	/* ...set 2D configuration (necessary for xres_virtual != xres) */
++	value = LCDC_MKBF(DMA2DCFG_ADDRINC,
++			cinfo->xres_virtual - cinfo->xres);
++	lcdc_writel(cinfo, DMA2DCFG, value);
++
++	/* ...wait for DMA engine to become idle... */
++	while (lcdc_readl(cinfo, DMACON) & LCDC_BIT(DMACON_DMABUSY));
++
++	/* ...and enable it with updated configuration */
++	lcdc_writel(cinfo, DMACON, (LCDC_BIT(DMACON_DMAEN)
++				| LCDC_BIT(DMACON_DMAUPDT)
++				| LCDC_BIT(DMACON_DMA2DEN)));
++
++	/* Now, the LCD core... */
++
++	/* Set pixel clock. */
++	value = 140000000 / 100000 * cinfo->pixclock;
++	value /= 10000000;
++	value = (value + 1) / 2;
++	if (value == 0) {
++		lcdc_writel(cinfo, LCDCON1, LCDC_BIT(LCDCON1_BYPASS));
++	} else {
++		lcdc_writel(cinfo, LCDCON1, LCDC_MKBF(LCDCON1_CLKVAL, value - 1));
++	}
++
++	/* Initialize control register 2 */
++	value = (LCDC_BIT(LCDCON2_CLKMOD)
++			| LCDC_MKBF(LCDCON2_DISTYPE, LCDC_DISTYPE_TFT));
++	if (!(cinfo->sync & FB_SYNC_HOR_HIGH_ACT))
++		value |= LCDC_BIT(LCDCON2_INVLINE);
++	if (!(cinfo->sync & FB_SYNC_VERT_HIGH_ACT))
++		value |= LCDC_BIT(LCDCON2_INVFRAME);
++	if (cinfo->sync & FB_SYNC_PCLK_RISING)
++		value |= LCDC_BIT(LCDCON2_INVCLK);
++
++	switch (cinfo->bits_per_pixel) {
++		case 1:	value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 0); break;
++		case 2: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 1); break;
++		case 4: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 2); break;
++		case 8: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 3); break;
++		case 15: /* fall through */
++		case 16: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 4); break;
++		case 24: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 5); break;
++		case 32: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 6); break;
++		default:
++			 printf("lcdc: %d bits per pixel not supported\n",
++					 cinfo->bits_per_pixel);
++			 return;
++			 break;
++	}
++	lcdc_writel(cinfo, LCDCON2, value);
++
++	/* Vertical timing */
++	value = LCDC_MKBF(LCDTIM1_VPW, cinfo->vsync_len - 1);
++	value |= LCDC_MKBF(LCDTIM1_VBP, cinfo->upper_margin);
++	value |= LCDC_MKBF(LCDTIM1_VFP, cinfo->lower_margin);
++	lcdc_writel(cinfo, LCDTIM1, value);
++
++	/* Horizontal timing */
++	value = LCDC_MKBF(LCDTIM2_HFP, cinfo->right_margin - 1);
++	value |= LCDC_MKBF(LCDTIM2_HPW, cinfo->hsync_len - 1);
++	value |= LCDC_MKBF(LCDTIM2_HBP, cinfo->left_margin - 1);
++	lcdc_writel(cinfo, LCDTIM2, value);
++
++	/* Display size */
++	value = LCDC_MKBF(LCDFRMCFG_LINESIZE, cinfo->xres - 1);
++	value |= LCDC_MKBF(LCDFRMCFG_LINEVAL, cinfo->yres - 1);
++	lcdc_writel(cinfo, LCDFRMCFG, value);
++
++	/* FIFO Threshold: Use formula from data sheet */
++	value = LCDC_FIFO_SIZE - (2 * LCDC_DMA_BURST_LEN + 3);
++	lcdc_writel(cinfo, LCDFIFO, value);
++
++	/* Toggle LCD_MODE every frame */
++	lcdc_writel(cinfo, LCDMVAL, 0);
++
++	/* Disable all interrupts */
++	lcdc_writel(cinfo, LCD_IDR, ~0UL);
++
++	/* Wait for the LCDC core to become idle and enable it */
++	while (lcdc_readl(cinfo, PWRCON) & LCDC_BIT(PWRCON_LCD_BUSY));
++
++	lcdc_writel(cinfo, PWRCON,
++			LCDC_MKBF(PWRCON_GUARD_TIME, cinfo->guard_time)
++			| LCDC_BIT(PWRCON_LCD_PWR));
++
++	debug("lcdc: controller at 0x%08x, framebuffer at 0x%08x\n",
++			cinfo->regs, cinfo->smem_start);
++
++	/* clear 320 x 240 x 24bpp area in framebuffer */
++	memset((void *)cinfo->smem_start, 0, cinfo->xres * cinfo->yres * 3);
++
++	return;
++}
++#endif
+diff -uprN u-boot-orig/drivers/Makefile u-boot/drivers/Makefile
+--- u-boot-orig/drivers/Makefile	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/drivers/Makefile	2007-01-01 16:10:49.000000000 +0100
+@@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk
+ 
+ LIB	= libdrivers.a
+ 
+-OBJS	= 3c589.o 5701rls.o ali512x.o atmel_usart.o \
++OBJS	= 3c589.o 5701rls.o ali512x.o \
++	  atmel_usart.o atmel_lcdc.o \
+ 	  bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
+ 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
+ 	  e1000.o eepro100.o \
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch	f9cdf2cc1db97cbdcfbb811df1067fb7baec5542
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch	f9cdf2cc1db97cbdcfbb811df1067fb7baec5542
@@ -0,0 +1,61 @@
+diff -uprN u-boot-orig/lib_avr32/board.c u-boot/lib_avr32/board.c
+--- u-boot-orig/lib_avr32/board.c	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/lib_avr32/board.c	2007-01-05 13:29:34.000000000 +0100
+@@ -28,6 +28,7 @@
+ 
+ #include <asm/initcalls.h>
+ #include <asm/sections.h>
++#include <asm/page.h>
+ 
+ #ifndef CONFIG_IDENT_STRING
+ #define CONFIG_IDENT_STRING ""
+@@ -128,6 +129,10 @@ void start_u_boot (void)
+ {
+ 	DECLARE_GLOBAL_DATA_PTR;
+ 	gd_t gd_data;
++#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
++	unsigned long size;
++	unsigned long addr;
++#endif
+ 
+ 	/* Initialize the global data pointer */
+ 	memset(&gd_data, 0, sizeof(gd_data));
+@@ -172,9 +177,38 @@ void start_u_boot (void)
+ 	if (!gd->bd->bi_boot_params)
+ 		puts("WARNING: Cannot allocate space for boot parameters\n");
+ 
++#if CONFIG_SPI
++	board_init_spi();
++#endif
++
++#ifdef CONFIG_VFD
++	/*
++	 * reserve memory for VFD display (always full pages)
++	 */
++	/* bss_end is defined in the board-specific linker script */
++	addr = CFG_LCD_BASE;
++	size = vfd_setmem(addr);
++	gd->fb_base = addr;
++#endif /* CONFIG_VFD */
++
++#ifdef CONFIG_LCD
++	/*
++	 * reserve memory for LCD display (always full pages)
++	 */
++	/* bss_end is defined in the board-specific linker script */
++	addr = CFG_LCD_BASE;
++	size = lcd_setmem(addr);
++	gd->fb_base = addr;
++#endif /* CONFIG_LCD */
++
+ 	/* initialize environment */
+ 	env_relocate();
+ 
++#ifdef CONFIG_VFD
++	/* must do this after the framebuffer is allocated */
++	drv_vfd_init();
++#endif /* CONFIG_VFD */
++
+ 	devices_init();
+ 	jumptable_init();
+ 	console_init_r();
============================================================
--- packages/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch	aaf3a5bcf5a60041e4da853c72c9417adca86a12
+++ packages/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch	aaf3a5bcf5a60041e4da853c72c9417adca86a12
@@ -0,0 +1,1026 @@
+diff -uprN u-boot-orig/include/atmel_spi.h u-boot/include/atmel_spi.h
+--- u-boot-orig/include/atmel_spi.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/atmel_spi.h	2007-01-01 18:45:27.000000000 +0100
+@@ -0,0 +1,676 @@
++#ifndef __SPI_H_
++#define __SPI_H_
++
++/*! \brief Timeout for spi read and write blocking functions */
++#define SPI_TIMEOUT		10000
++/*! \brief Enable PDC functions for SPI */
++#define SPI_ENABLE_PDC
++
++#define SPI_10_BPT                                   0x00000002
++#define SPI_11_BPT                                   0x00000003
++#define SPI_12_BPT                                   0x00000004
++#define SPI_13_BPT                                   0x00000005
++#define SPI_14_BPT                                   0x00000006
++#define SPI_15_BPT                                   0x00000007
++#define SPI_16_BPT                                   0x00000008
++#define SPI_8_BPT                                    0x00000000
++#define SPI_9_BPT                                    0x00000001
++#define SPI_BITS                                              4
++#define SPI_BITS_10_BPT                              0x00000002
++#define SPI_BITS_11_BPT                              0x00000003
++#define SPI_BITS_12_BPT                              0x00000004
++#define SPI_BITS_13_BPT                              0x00000005
++#define SPI_BITS_14_BPT                              0x00000006
++#define SPI_BITS_15_BPT                              0x00000007
++#define SPI_BITS_16_BPT                              0x00000008
++#define SPI_BITS_8_BPT                               0x00000000
++#define SPI_BITS_9_BPT                               0x00000001
++#define SPI_BITS_MASK                                0x000000f0
++#define SPI_BITS_OFFSET                                       4
++#define SPI_BITS_SIZE                                         4
++#define SPI_CPOL                                              0
++#define SPI_CPOL_MASK                                0x00000001
++#define SPI_CPOL_OFFSET                                       0
++#define SPI_CPOL_SIZE                                         1
++#define SPI_CR                                       0x00000000
++#define SPI_CR_LASTXFER                                      24
++#define SPI_CR_LASTXFER_MASK                         0x01000000
++#define SPI_CR_LASTXFER_OFFSET                               24
++#define SPI_CR_LASTXFER_SIZE                                  1
++#define SPI_CR_SPIDIS                                         1
++#define SPI_CR_SPIDIS_MASK                           0x00000002
++#define SPI_CR_SPIDIS_OFFSET                                  1
++#define SPI_CR_SPIDIS_SIZE                                    1
++#define SPI_CR_SPIEN                                          0
++#define SPI_CR_SPIEN_MASK                            0x00000001
++#define SPI_CR_SPIEN_OFFSET                                   0
++#define SPI_CR_SPIEN_SIZE                                     1
++#define SPI_CR_SWRST                                          7
++#define SPI_CR_SWRST_MASK                            0x00000080
++#define SPI_CR_SWRST_OFFSET                                   7
++#define SPI_CR_SWRST_SIZE                                     1
++#define SPI_CSAAT                                             3
++#define SPI_CSAAT_MASK                               0x00000008
++#define SPI_CSAAT_OFFSET                                      3
++#define SPI_CSAAT_SIZE                                        1
++#define SPI_CSR0                                     0x00000030
++#define SPI_CSR0_BITS                                         4
++#define SPI_CSR0_BITS_10_BPT                         0x00000002
++#define SPI_CSR0_BITS_11_BPT                         0x00000003
++#define SPI_CSR0_BITS_12_BPT                         0x00000004
++#define SPI_CSR0_BITS_13_BPT                         0x00000005
++#define SPI_CSR0_BITS_14_BPT                         0x00000006
++#define SPI_CSR0_BITS_15_BPT                         0x00000007
++#define SPI_CSR0_BITS_16_BPT                         0x00000008
++#define SPI_CSR0_BITS_8_BPT                          0x00000000
++#define SPI_CSR0_BITS_9_BPT                          0x00000001
++#define SPI_CSR0_BITS_MASK                           0x000000f0
++#define SPI_CSR0_BITS_OFFSET                                  4
++#define SPI_CSR0_BITS_SIZE                                    4
++#define SPI_CSR0_CPOL                                         0
++#define SPI_CSR0_CPOL_MASK                           0x00000001
++#define SPI_CSR0_CPOL_OFFSET                                  0
++#define SPI_CSR0_CPOL_SIZE                                    1
++#define SPI_CSR0_CSAAT                                        3
++#define SPI_CSR0_CSAAT_MASK                          0x00000008
++#define SPI_CSR0_CSAAT_OFFSET                                 3
++#define SPI_CSR0_CSAAT_SIZE                                   1
++#define SPI_CSR0_DLYBCT                                      24
++#define SPI_CSR0_DLYBCT_MASK                         0xff000000
++#define SPI_CSR0_DLYBCT_OFFSET                               24
++#define SPI_CSR0_DLYBCT_SIZE                                  8
++#define SPI_CSR0_DLYBS                                       16
++#define SPI_CSR0_DLYBS_MASK                          0x00ff0000
++#define SPI_CSR0_DLYBS_OFFSET                                16
++#define SPI_CSR0_DLYBS_SIZE                                   8
++#define SPI_CSR0_NCPHA                                        1
++#define SPI_CSR0_NCPHA_MASK                          0x00000002
++#define SPI_CSR0_NCPHA_OFFSET                                 1
++#define SPI_CSR0_NCPHA_SIZE                                   1
++#define SPI_CSR0_SCBR                                         8
++#define SPI_CSR0_SCBR_MASK                           0x0000ff00
++#define SPI_CSR0_SCBR_OFFSET                                  8
++#define SPI_CSR0_SCBR_SIZE                                    8
++#define SPI_CSR1                                     0x00000034
++#define SPI_CSR1_BITS                                         4
++#define SPI_CSR1_BITS_10_BPT                         0x00000002
++#define SPI_CSR1_BITS_11_BPT                         0x00000003
++#define SPI_CSR1_BITS_12_BPT                         0x00000004
++#define SPI_CSR1_BITS_13_BPT                         0x00000005
++#define SPI_CSR1_BITS_14_BPT                         0x00000006
++#define SPI_CSR1_BITS_15_BPT                         0x00000007
++#define SPI_CSR1_BITS_16_BPT                         0x00000008
++#define SPI_CSR1_BITS_8_BPT                          0x00000000
++#define SPI_CSR1_BITS_9_BPT                          0x00000001
++#define SPI_CSR1_BITS_MASK                           0x000000f0
++#define SPI_CSR1_BITS_OFFSET                                  4
++#define SPI_CSR1_BITS_SIZE                                    4
++#define SPI_CSR1_CPOL                                         0
++#define SPI_CSR1_CPOL_MASK                           0x00000001
++#define SPI_CSR1_CPOL_OFFSET                                  0
++#define SPI_CSR1_CPOL_SIZE                                    1
++#define SPI_CSR1_CSAAT                                        3
++#define SPI_CSR1_CSAAT_MASK                          0x00000008
++#define SPI_CSR1_CSAAT_OFFSET                                 3
++#define SPI_CSR1_CSAAT_SIZE                                   1
++#define SPI_CSR1_DLYBCT                                      24
++#define SPI_CSR1_DLYBCT_MASK                         0xff000000
++#define SPI_CSR1_DLYBCT_OFFSET                               24
++#define SPI_CSR1_DLYBCT_SIZE                                  8
++#define SPI_CSR1_DLYBS                                       16
++#define SPI_CSR1_DLYBS_MASK                          0x00ff0000
++#define SPI_CSR1_DLYBS_OFFSET                                16
++#define SPI_CSR1_DLYBS_SIZE                                   8
++#define SPI_CSR1_NCPHA                                        1
++#define SPI_CSR1_NCPHA_MASK                          0x00000002
++#define SPI_CSR1_NCPHA_OFFSET                                 1
++#define SPI_CSR1_NCPHA_SIZE                                   1
++#define SPI_CSR1_SCBR                                         8
++#define SPI_CSR1_SCBR_MASK                           0x0000ff00
++#define SPI_CSR1_SCBR_OFFSET                                  8
++#define SPI_CSR1_SCBR_SIZE                                    8
++#define SPI_CSR2                                     0x00000038
++#define SPI_CSR2_BITS                                         4
++#define SPI_CSR2_BITS_10_BPT                         0x00000002
++#define SPI_CSR2_BITS_11_BPT                         0x00000003
++#define SPI_CSR2_BITS_12_BPT                         0x00000004
++#define SPI_CSR2_BITS_13_BPT                         0x00000005
++#define SPI_CSR2_BITS_14_BPT                         0x00000006
++#define SPI_CSR2_BITS_15_BPT                         0x00000007
++#define SPI_CSR2_BITS_16_BPT                         0x00000008
++#define SPI_CSR2_BITS_8_BPT                          0x00000000
++#define SPI_CSR2_BITS_9_BPT                          0x00000001
++#define SPI_CSR2_BITS_MASK                           0x000000f0
++#define SPI_CSR2_BITS_OFFSET                                  4
++#define SPI_CSR2_BITS_SIZE                                    4
++#define SPI_CSR2_CPOL                                         0
++#define SPI_CSR2_CPOL_MASK                           0x00000001
++#define SPI_CSR2_CPOL_OFFSET                                  0
++#define SPI_CSR2_CPOL_SIZE                                    1
++#define SPI_CSR2_CSAAT                                        3
++#define SPI_CSR2_CSAAT_MASK                          0x00000008
++#define SPI_CSR2_CSAAT_OFFSET                                 3
++#define SPI_CSR2_CSAAT_SIZE                                   1
++#define SPI_CSR2_DLYBCT                                      24
++#define SPI_CSR2_DLYBCT_MASK                         0xff000000
++#define SPI_CSR2_DLYBCT_OFFSET                               24
++#define SPI_CSR2_DLYBCT_SIZE                                  8
++#define SPI_CSR2_DLYBS                                       16
++#define SPI_CSR2_DLYBS_MASK                          0x00ff0000
++#define SPI_CSR2_DLYBS_OFFSET                                16
++#define SPI_CSR2_DLYBS_SIZE                                   8
++#define SPI_CSR2_NCPHA                                        1
++#define SPI_CSR2_NCPHA_MASK                          0x00000002
++#define SPI_CSR2_NCPHA_OFFSET                                 1
++#define SPI_CSR2_NCPHA_SIZE                                   1
++#define SPI_CSR2_SCBR                                         8
++#define SPI_CSR2_SCBR_MASK                           0x0000ff00
++#define SPI_CSR2_SCBR_OFFSET                                  8
++#define SPI_CSR2_SCBR_SIZE                                    8
++#define SPI_CSR3                                     0x0000003c
++#define SPI_CSR3_BITS                                         4
++#define SPI_CSR3_BITS_10_BPT                         0x00000002
++#define SPI_CSR3_BITS_11_BPT                         0x00000003
++#define SPI_CSR3_BITS_12_BPT                         0x00000004
++#define SPI_CSR3_BITS_13_BPT                         0x00000005
++#define SPI_CSR3_BITS_14_BPT                         0x00000006
++#define SPI_CSR3_BITS_15_BPT                         0x00000007
++#define SPI_CSR3_BITS_16_BPT                         0x00000008
++#define SPI_CSR3_BITS_8_BPT                          0x00000000
++#define SPI_CSR3_BITS_9_BPT                          0x00000001
++#define SPI_CSR3_BITS_MASK                           0x000000f0
++#define SPI_CSR3_BITS_OFFSET                                  4
++#define SPI_CSR3_BITS_SIZE                                    4
++#define SPI_CSR3_CPOL                                         0
++#define SPI_CSR3_CPOL_MASK                           0x00000001
++#define SPI_CSR3_CPOL_OFFSET                                  0
++#define SPI_CSR3_CPOL_SIZE                                    1
++#define SPI_CSR3_CSAAT                                        3
++#define SPI_CSR3_CSAAT_MASK                          0x00000008
++#define SPI_CSR3_CSAAT_OFFSET                                 3
++#define SPI_CSR3_CSAAT_SIZE                                   1
++#define SPI_CSR3_DLYBCT                                      24
++#define SPI_CSR3_DLYBCT_MASK                         0xff000000
++#define SPI_CSR3_DLYBCT_OFFSET                               24
++#define SPI_CSR3_DLYBCT_SIZE                                  8
++#define SPI_CSR3_DLYBS                                       16
++#define SPI_CSR3_DLYBS_MASK                          0x00ff0000
++#define SPI_CSR3_DLYBS_OFFSET                                16
++#define SPI_CSR3_DLYBS_SIZE                                   8
++#define SPI_CSR3_NCPHA                                        1
++#define SPI_CSR3_NCPHA_MASK                          0x00000002
++#define SPI_CSR3_NCPHA_OFFSET                                 1
++#define SPI_CSR3_NCPHA_SIZE                                   1
++#define SPI_CSR3_SCBR                                         8
++#define SPI_CSR3_SCBR_MASK                           0x0000ff00
++#define SPI_CSR3_SCBR_OFFSET                                  8
++#define SPI_CSR3_SCBR_SIZE                                    8
++#define SPI_DLYBCS                                           24
++#define SPI_DLYBCS_MASK                              0xff000000
++#define SPI_DLYBCS_OFFSET                                    24
++#define SPI_DLYBCS_SIZE                                       8
++#define SPI_DLYBCT                                           24
++#define SPI_DLYBCT_MASK                              0xff000000
++#define SPI_DLYBCT_OFFSET                                    24
++#define SPI_DLYBCT_SIZE                                       8
++#define SPI_DLYBS                                            16
++#define SPI_DLYBS_MASK                               0x00ff0000
++#define SPI_DLYBS_OFFSET                                     16
++#define SPI_DLYBS_SIZE                                        8
++#define SPI_ENDRX                                             4
++#define SPI_ENDRX_MASK                               0x00000010
++#define SPI_ENDRX_OFFSET                                      4
++#define SPI_ENDRX_SIZE                                        1
++#define SPI_ENDTX                                             5
++#define SPI_ENDTX_MASK                               0x00000020
++#define SPI_ENDTX_OFFSET                                      5
++#define SPI_ENDTX_SIZE                                        1
++#define SPI_FDIV                                              3
++#define SPI_FDIV_MASK                                0x00000008
++#define SPI_FDIV_OFFSET                                       3
++#define SPI_FDIV_SIZE                                         1
++#define SPI_IDR                                      0x00000018
++#define SPI_IDR_ENDRX                                         4
++#define SPI_IDR_ENDRX_MASK                           0x00000010
++#define SPI_IDR_ENDRX_OFFSET                                  4
++#define SPI_IDR_ENDRX_SIZE                                    1
++#define SPI_IDR_ENDTX                                         5
++#define SPI_IDR_ENDTX_MASK                           0x00000020
++#define SPI_IDR_ENDTX_OFFSET                                  5
++#define SPI_IDR_ENDTX_SIZE                                    1
++#define SPI_IDR_MODF                                          2
++#define SPI_IDR_MODF_MASK                            0x00000004
++#define SPI_IDR_MODF_OFFSET                                   2
++#define SPI_IDR_MODF_SIZE                                     1
++#define SPI_IDR_NSSR                                          8
++#define SPI_IDR_NSSR_MASK                            0x00000100
++#define SPI_IDR_NSSR_OFFSET                                   8
++#define SPI_IDR_NSSR_SIZE                                     1
++#define SPI_IDR_OVRES                                         3
++#define SPI_IDR_OVRES_MASK                           0x00000008
++#define SPI_IDR_OVRES_OFFSET                                  3
++#define SPI_IDR_OVRES_SIZE                                    1
++#define SPI_IDR_RDRF                                          0
++#define SPI_IDR_RDRF_MASK                            0x00000001
++#define SPI_IDR_RDRF_OFFSET                                   0
++#define SPI_IDR_RDRF_SIZE                                     1
++#define SPI_IDR_RXBUFF                                        6
++#define SPI_IDR_RXBUFF_MASK                          0x00000040
++#define SPI_IDR_RXBUFF_OFFSET                                 6
++#define SPI_IDR_RXBUFF_SIZE                                   1
++#define SPI_IDR_TDRE                                          1
++#define SPI_IDR_TDRE_MASK                            0x00000002
++#define SPI_IDR_TDRE_OFFSET                                   1
++#define SPI_IDR_TDRE_SIZE                                     1
++#define SPI_IDR_TXBUFE                                        7
++#define SPI_IDR_TXBUFE_MASK                          0x00000080
++#define SPI_IDR_TXBUFE_OFFSET                                 7
++#define SPI_IDR_TXBUFE_SIZE                                   1
++#define SPI_IDR_TXEMPTY                                       9
++#define SPI_IDR_TXEMPTY_MASK                         0x00000200
++#define SPI_IDR_TXEMPTY_OFFSET                                9
++#define SPI_IDR_TXEMPTY_SIZE                                  1
++#define SPI_IER                                      0x00000014
++#define SPI_IER_ENDRX                                         4
++#define SPI_IER_ENDRX_MASK                           0x00000010
++#define SPI_IER_ENDRX_OFFSET                                  4
++#define SPI_IER_ENDRX_SIZE                                    1
++#define SPI_IER_ENDTX                                         5
++#define SPI_IER_ENDTX_MASK                           0x00000020
++#define SPI_IER_ENDTX_OFFSET                                  5
++#define SPI_IER_ENDTX_SIZE                                    1
++#define SPI_IER_MODF                                          2
++#define SPI_IER_MODF_MASK                            0x00000004
++#define SPI_IER_MODF_OFFSET                                   2
++#define SPI_IER_MODF_SIZE                                     1
++#define SPI_IER_NSSR                                          8
++#define SPI_IER_NSSR_MASK                            0x00000100
++#define SPI_IER_NSSR_OFFSET                                   8
++#define SPI_IER_NSSR_SIZE                                     1
++#define SPI_IER_OVRES                                         3
++#define SPI_IER_OVRES_MASK                           0x00000008
++#define SPI_IER_OVRES_OFFSET                                  3
++#define SPI_IER_OVRES_SIZE                                    1
++#define SPI_IER_RDRF                                          0
++#define SPI_IER_RDRF_MASK                            0x00000001
++#define SPI_IER_RDRF_OFFSET                                   0
++#define SPI_IER_RDRF_SIZE                                     1
++#define SPI_IER_RXBUFF                                        6
++#define SPI_IER_RXBUFF_MASK                          0x00000040
++#define SPI_IER_RXBUFF_OFFSET                                 6
++#define SPI_IER_RXBUFF_SIZE                                   1
++#define SPI_IER_TDRE                                          1
++#define SPI_IER_TDRE_MASK                            0x00000002
++#define SPI_IER_TDRE_OFFSET                                   1
++#define SPI_IER_TDRE_SIZE                                     1
++#define SPI_IER_TXBUFE                                        7
++#define SPI_IER_TXBUFE_MASK                          0x00000080
++#define SPI_IER_TXBUFE_OFFSET                                 7
++#define SPI_IER_TXBUFE_SIZE                                   1
++#define SPI_IER_TXEMPTY                                       9
++#define SPI_IER_TXEMPTY_MASK                         0x00000200
++#define SPI_IER_TXEMPTY_OFFSET                                9
++#define SPI_IER_TXEMPTY_SIZE                                  1
++#define SPI_IMR                                      0x0000001c
++#define SPI_IMR_ENDRX                                         4
++#define SPI_IMR_ENDRX_MASK                           0x00000010
++#define SPI_IMR_ENDRX_OFFSET                                  4
++#define SPI_IMR_ENDRX_SIZE                                    1
++#define SPI_IMR_ENDTX                                         5
++#define SPI_IMR_ENDTX_MASK                           0x00000020
++#define SPI_IMR_ENDTX_OFFSET                                  5
++#define SPI_IMR_ENDTX_SIZE                                    1
++#define SPI_IMR_MODF                                          2
++#define SPI_IMR_MODF_MASK                            0x00000004
++#define SPI_IMR_MODF_OFFSET                                   2
++#define SPI_IMR_MODF_SIZE                                     1
++#define SPI_IMR_NSSR                                          8
++#define SPI_IMR_NSSR_MASK                            0x00000100
++#define SPI_IMR_NSSR_OFFSET                                   8
++#define SPI_IMR_NSSR_SIZE                                     1
++#define SPI_IMR_OVRES                                         3
++#define SPI_IMR_OVRES_MASK                           0x00000008
++#define SPI_IMR_OVRES_OFFSET                                  3
++#define SPI_IMR_OVRES_SIZE                                    1
++#define SPI_IMR_RDRF                                          0
++#define SPI_IMR_RDRF_MASK                            0x00000001
++#define SPI_IMR_RDRF_OFFSET                                   0
++#define SPI_IMR_RDRF_SIZE                                     1
++#define SPI_IMR_RXBUFF                                        6
++#define SPI_IMR_RXBUFF_MASK                          0x00000040
++#define SPI_IMR_RXBUFF_OFFSET                                 6
++#define SPI_IMR_RXBUFF_SIZE                                   1
++#define SPI_IMR_TDRE                                          1
++#define SPI_IMR_TDRE_MASK                            0x00000002
++#define SPI_IMR_TDRE_OFFSET                                   1
++#define SPI_IMR_TDRE_SIZE                                     1
++#define SPI_IMR_TXBUFE                                        7
++#define SPI_IMR_TXBUFE_MASK                          0x00000080
++#define SPI_IMR_TXBUFE_OFFSET                                 7
++#define SPI_IMR_TXBUFE_SIZE                                   1
++#define SPI_IMR_TXEMPTY                                       9
++#define SPI_IMR_TXEMPTY_MASK                         0x00000200
++#define SPI_IMR_TXEMPTY_OFFSET                                9
++#define SPI_IMR_TXEMPTY_SIZE                                  1
++#define SPI_LASTXFER                                         24
++#define SPI_LASTXFER_MASK                            0x01000000
++#define SPI_LASTXFER_OFFSET                                  24
++#define SPI_LASTXFER_SIZE                                     1
++#define SPI_LLB                                               7
++#define SPI_LLB_MASK                                 0x00000080
++#define SPI_LLB_OFFSET                                        7
++#define SPI_LLB_SIZE                                          1
++#define SPI_MODF                                              2
++#define SPI_MODFDIS                                           4
++#define SPI_MODFDIS_MASK                             0x00000010
++#define SPI_MODFDIS_OFFSET                                    4
++#define SPI_MODFDIS_SIZE                                      1
++#define SPI_MODF_MASK                                0x00000004
++#define SPI_MODF_OFFSET                                       2
++#define SPI_MODF_SIZE                                         1
++#define SPI_MR                                       0x00000004
++#define SPI_MR_DLYBCS                                        24
++#define SPI_MR_DLYBCS_MASK                           0xff000000
++#define SPI_MR_DLYBCS_OFFSET                                 24
++#define SPI_MR_DLYBCS_SIZE                                    8
++#define SPI_MR_FDIV                                           3
++#define SPI_MR_FDIV_MASK                             0x00000008
++#define SPI_MR_FDIV_OFFSET                                    3
++#define SPI_MR_FDIV_SIZE                                      1
++#define SPI_MR_LLB                                            7
++#define SPI_MR_LLB_MASK                              0x00000080
++#define SPI_MR_LLB_OFFSET                                     7
++#define SPI_MR_LLB_SIZE                                       1
++#define SPI_MR_MODFDIS                                        4
++#define SPI_MR_MODFDIS_MASK                          0x00000010
++#define SPI_MR_MODFDIS_OFFSET                                 4
++#define SPI_MR_MODFDIS_SIZE                                   1
++#define SPI_MR_MSTR                                           0
++#define SPI_MR_MSTR_MASK                             0x00000001
++#define SPI_MR_MSTR_OFFSET                                    0
++#define SPI_MR_MSTR_SIZE                                      1
++#define SPI_MR_PCS                                           16
++#define SPI_MR_PCSDEC                                         2
++#define SPI_MR_PCSDEC_MASK                           0x00000004
++#define SPI_MR_PCSDEC_OFFSET                                  2
++#define SPI_MR_PCSDEC_SIZE                                    1
++#define SPI_MR_PCS_MASK                              0x000f0000
++#define SPI_MR_PCS_OFFSET                                    16
++#define SPI_MR_PCS_SIZE                                       4
++#define SPI_MR_PS                                             1
++#define SPI_MR_PS_MASK                               0x00000002
++#define SPI_MR_PS_OFFSET                                      1
++#define SPI_MR_PS_SIZE                                        1
++#define SPI_MSTR                                              0
++#define SPI_MSTR_MASK                                0x00000001
++#define SPI_MSTR_OFFSET                                       0
++#define SPI_MSTR_SIZE                                         1
++#define SPI_NCPHA                                             1
++#define SPI_NCPHA_MASK                               0x00000002
++#define SPI_NCPHA_OFFSET                                      1
++#define SPI_NCPHA_SIZE                                        1
++#define SPI_NSSR                                              8
++#define SPI_NSSR_MASK                                0x00000100
++#define SPI_NSSR_OFFSET                                       8
++#define SPI_NSSR_SIZE                                         1
++#define SPI_OVRES                                             3
++#define SPI_OVRES_MASK                               0x00000008
++#define SPI_OVRES_OFFSET                                      3
++#define SPI_OVRES_SIZE                                        1
++#define SPI_PCS                                              16
++#define SPI_PCSDEC                                            2
++#define SPI_PCSDEC_MASK                              0x00000004
++#define SPI_PCSDEC_OFFSET                                     2
++#define SPI_PCSDEC_SIZE                                       1
++#define SPI_PCS_MASK                                 0x000f0000
++#define SPI_PCS_OFFSET                                       16
++#define SPI_PCS_SIZE                                          4
++#define SPI_PS                                                1
++#define SPI_PS_MASK                                  0x00000002
++#define SPI_PS_OFFSET                                         1
++#define SPI_PS_SIZE                                           1
++#define SPI_PTCR                                     0x00000120
++#define SPI_PTCR_RXTDIS                                       1
++#define SPI_PTCR_RXTDIS_MASK                         0x00000002
++#define SPI_PTCR_RXTDIS_OFFSET                                1
++#define SPI_PTCR_RXTDIS_SIZE                                  1
++#define SPI_PTCR_RXTEN                                        0
++#define SPI_PTCR_RXTEN_MASK                          0x00000001
++#define SPI_PTCR_RXTEN_OFFSET                                 0
++#define SPI_PTCR_RXTEN_SIZE                                   1
++#define SPI_PTCR_TXTDIS                                       9
++#define SPI_PTCR_TXTDIS_MASK                         0x00000200
++#define SPI_PTCR_TXTDIS_OFFSET                                9
++#define SPI_PTCR_TXTDIS_SIZE                                  1
++#define SPI_PTCR_TXTEN                                        8
++#define SPI_PTCR_TXTEN_MASK                          0x00000100
++#define SPI_PTCR_TXTEN_OFFSET                                 8
++#define SPI_PTCR_TXTEN_SIZE                                   1
++#define SPI_PTSR                                     0x00000124
++#define SPI_PTSR_RXTEN                                        0
++#define SPI_PTSR_RXTEN_MASK                          0x00000001
++#define SPI_PTSR_RXTEN_OFFSET                                 0
++#define SPI_PTSR_RXTEN_SIZE                                   1
++#define SPI_PTSR_TXTEN                                        8
++#define SPI_PTSR_TXTEN_MASK                          0x00000100
++#define SPI_PTSR_TXTEN_OFFSET                                 8
++#define SPI_PTSR_TXTEN_SIZE                                   1
++#define SPI_RCR                                      0x00000104
++#define SPI_RCR_RXCTR                                         0
++#define SPI_RCR_RXCTR_MASK                           0x0000ffff
++#define SPI_RCR_RXCTR_OFFSET                                  0
++#define SPI_RCR_RXCTR_SIZE                                   16
++#define SPI_RD                                                0
++#define SPI_RDR                                      0x00000008
++#define SPI_RDRF                                              0
++#define SPI_RDRF_MASK                                0x00000001
++#define SPI_RDRF_OFFSET                                       0
++#define SPI_RDRF_SIZE                                         1
++#define SPI_RDR_PCS                                          16
++#define SPI_RDR_PCS_MASK                             0x000f0000
++#define SPI_RDR_PCS_OFFSET                                   16
++#define SPI_RDR_PCS_SIZE                                      4
++#define SPI_RDR_RD                                            0
++#define SPI_RDR_RD_MASK                              0x0000ffff
++#define SPI_RDR_RD_OFFSET                                     0
++#define SPI_RDR_RD_SIZE                                      16
++#define SPI_RD_MASK                                  0x0000ffff
++#define SPI_RD_OFFSET                                         0
++#define SPI_RD_SIZE                                          16
++#define SPI_RNCR                                     0x00000114
++#define SPI_RNCR_RXNCR                                        0
++#define SPI_RNCR_RXNCR_MASK                          0x0000ffff
++#define SPI_RNCR_RXNCR_OFFSET                                 0
++#define SPI_RNCR_RXNCR_SIZE                                  16
++#define SPI_RNPR                                     0x00000110
++#define SPI_RPR                                      0x00000100
++#define SPI_RXBUFF                                            6
++#define SPI_RXBUFF_MASK                              0x00000040
++#define SPI_RXBUFF_OFFSET                                     6
++#define SPI_RXBUFF_SIZE                                       1
++#define SPI_RXCTR                                             0
++#define SPI_RXCTR_MASK                               0x0000ffff
++#define SPI_RXCTR_OFFSET                                      0
++#define SPI_RXCTR_SIZE                                       16
++#define SPI_RXNCR                                             0
++#define SPI_RXNCR_MASK                               0x0000ffff
++#define SPI_RXNCR_OFFSET                                      0
++#define SPI_RXNCR_SIZE                                       16
++#define SPI_RXTDIS                                            1
++#define SPI_RXTDIS_MASK                              0x00000002
++#define SPI_RXTDIS_OFFSET                                     1
++#define SPI_RXTDIS_SIZE                                       1
++#define SPI_RXTEN                                             0
++#define SPI_RXTEN_MASK                               0x00000001
++#define SPI_RXTEN_OFFSET                                      0
++#define SPI_RXTEN_SIZE                                        1
++#define SPI_SCBR                                              8
++#define SPI_SCBR_MASK                                0x0000ff00
++#define SPI_SCBR_OFFSET                                       8
++#define SPI_SCBR_SIZE                                         8
++#define SPI_SPIDIS                                            1
++#define SPI_SPIDIS_MASK                              0x00000002
++#define SPI_SPIDIS_OFFSET                                     1
++#define SPI_SPIDIS_SIZE                                       1
++#define SPI_SPIEN                                             0
++#define SPI_SPIENS                                           16
++#define SPI_SPIENS_MASK                              0x00010000
++#define SPI_SPIENS_OFFSET                                    16
++#define SPI_SPIENS_SIZE                                       1
++#define SPI_SPIEN_MASK                               0x00000001
++#define SPI_SPIEN_OFFSET                                      0
++#define SPI_SPIEN_SIZE                                        1
++#define SPI_SR                                       0x00000010
++#define SPI_SR_ENDRX                                          4
++#define SPI_SR_ENDRX_MASK                            0x00000010
++#define SPI_SR_ENDRX_OFFSET                                   4
++#define SPI_SR_ENDRX_SIZE                                     1
++#define SPI_SR_ENDTX                                          5
++#define SPI_SR_ENDTX_MASK                            0x00000020
++#define SPI_SR_ENDTX_OFFSET                                   5
++#define SPI_SR_ENDTX_SIZE                                     1
++#define SPI_SR_MODF                                           2
++#define SPI_SR_MODF_MASK                             0x00000004
++#define SPI_SR_MODF_OFFSET                                    2
++#define SPI_SR_MODF_SIZE                                      1
++#define SPI_SR_NSSR                                           8
++#define SPI_SR_NSSR_MASK                             0x00000100
++#define SPI_SR_NSSR_OFFSET                                    8
++#define SPI_SR_NSSR_SIZE                                      1
++#define SPI_SR_OVRES                                          3
++#define SPI_SR_OVRES_MASK                            0x00000008
++#define SPI_SR_OVRES_OFFSET                                   3
++#define SPI_SR_OVRES_SIZE                                     1
++#define SPI_SR_RDRF                                           0
++#define SPI_SR_RDRF_MASK                             0x00000001
++#define SPI_SR_RDRF_OFFSET                                    0
++#define SPI_SR_RDRF_SIZE                                      1
++#define SPI_SR_RXBUFF                                         6
++#define SPI_SR_RXBUFF_MASK                           0x00000040
++#define SPI_SR_RXBUFF_OFFSET                                  6
++#define SPI_SR_RXBUFF_SIZE                                    1
++#define SPI_SR_SPIENS                                        16
++#define SPI_SR_SPIENS_MASK                           0x00010000
++#define SPI_SR_SPIENS_OFFSET                                 16
++#define SPI_SR_SPIENS_SIZE                                    1
++#define SPI_SR_TDRE                                           1
++#define SPI_SR_TDRE_MASK                             0x00000002
++#define SPI_SR_TDRE_OFFSET                                    1
++#define SPI_SR_TDRE_SIZE                                      1
++#define SPI_SR_TXBUFE                                         7
++#define SPI_SR_TXBUFE_MASK                           0x00000080
++#define SPI_SR_TXBUFE_OFFSET                                  7
++#define SPI_SR_TXBUFE_SIZE                                    1
++#define SPI_SR_TXEMPTY                                        9
++#define SPI_SR_TXEMPTY_MASK                          0x00000200
++#define SPI_SR_TXEMPTY_OFFSET                                 9
++#define SPI_SR_TXEMPTY_SIZE                                   1
++#define SPI_SWRST                                             7
++#define SPI_SWRST_MASK                               0x00000080
++#define SPI_SWRST_OFFSET                                      7
++#define SPI_SWRST_SIZE                                        1
++#define SPI_TCR                                      0x0000010c
++#define SPI_TCR_TXCTR                                         0
++#define SPI_TCR_TXCTR_MASK                           0x0000ffff
++#define SPI_TCR_TXCTR_OFFSET                                  0
++#define SPI_TCR_TXCTR_SIZE                                   16
++#define SPI_TD                                                0
++#define SPI_TDR                                      0x0000000c
++#define SPI_TDRE                                              1
++#define SPI_TDRE_MASK                                0x00000002
++#define SPI_TDRE_OFFSET                                       1
++#define SPI_TDRE_SIZE                                         1
++#define SPI_TDR_LASTXFER                                     24
++#define SPI_TDR_LASTXFER_MASK                        0x01000000
++#define SPI_TDR_LASTXFER_OFFSET                              24
++#define SPI_TDR_LASTXFER_SIZE                                 1
++#define SPI_TDR_PCS                                          16
++#define SPI_TDR_PCS_MASK                             0x000f0000
++#define SPI_TDR_PCS_OFFSET                                   16
++#define SPI_TDR_PCS_SIZE                                      4
++#define SPI_TDR_TD                                            0
++#define SPI_TDR_TD_MASK                              0x0000ffff
++#define SPI_TDR_TD_OFFSET                                     0
++#define SPI_TDR_TD_SIZE                                      16
++#define SPI_TD_MASK                                  0x0000ffff
++#define SPI_TD_OFFSET                                         0
++#define SPI_TD_SIZE                                          16
++#define SPI_TNCR                                     0x0000011c
++#define SPI_TNCR_TXNCR                                        0
++#define SPI_TNCR_TXNCR_MASK                          0x0000ffff
++#define SPI_TNCR_TXNCR_OFFSET                                 0
++#define SPI_TNCR_TXNCR_SIZE                                  16
++#define SPI_TNPR                                     0x00000118
++#define SPI_TPR                                      0x00000108
++#define SPI_TXBUFE                                            7
++#define SPI_TXBUFE_MASK                              0x00000080
++#define SPI_TXBUFE_OFFSET                                     7
++#define SPI_TXBUFE_SIZE                                       1
++#define SPI_TXCTR                                             0
++#define SPI_TXCTR_MASK                               0x0000ffff
++#define SPI_TXCTR_OFFSET                                      0
++#define SPI_TXCTR_SIZE                                       16
++#define SPI_TXEMPTY                                           9
++#define SPI_TXEMPTY_MASK                             0x00000200
++#define SPI_TXEMPTY_OFFSET                                    9
++#define SPI_TXEMPTY_SIZE                                      1
++#define SPI_TXNCR                                             0
++#define SPI_TXNCR_MASK                               0x0000ffff
++#define SPI_TXNCR_OFFSET                                      0
++#define SPI_TXNCR_SIZE                                       16
++#define SPI_TXTDIS                                            9
++#define SPI_TXTDIS_MASK                              0x00000200
++#define SPI_TXTDIS_OFFSET                                     9
++#define SPI_TXTDIS_SIZE                                       1
++#define SPI_TXTEN                                             8
++#define SPI_TXTEN_MASK                               0x00000100
++#define SPI_TXTEN_OFFSET                                      8
++#define SPI_TXTEN_SIZE                                        1
++
++enum {
++	SPI_ERROR = -1,
++	SPI_OK = 0,
++	SPI_ERROR_TIMEOUT = 1,
++	SPI_ERROR_ARGUMENT,
++	SPI_ERROR_OVERRUN,
++	SPI_ERROR_MODE_FAULT,
++	SPI_ERROR_OVERRUN_AND_MODE_FAULT
++};
++
++struct spi_options_t {
++	unsigned char reg;
++	unsigned int baudrate;
++	unsigned char bits;
++	unsigned char spck_delay;
++	unsigned char trans_delay;
++	unsigned char stay_act;
++	unsigned char spi_mode;
++};
++
++struct spi_info {
++	void			*regs;
++};
++
++int spi_select_chip(unsigned char chip);
++
++int spi_unselect_chip(unsigned char chip);
++
++int spi_setup_chip_reg(struct spi_options_t *options, unsigned int cpuHz);
++
++void spi_enable(void);
++
++void spi_disable(void);
++
++int spi_write(uchar *addr, int alen, uchar *buffer, int len);
++
++int spi_read(uchar *addr, int alen, uchar *buffer, int len);
++
++#define SPI_BIT(name)                          (1 << SPI_##name##_OFFSET)
++#define SPI_MKBF(name,value)                   (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
++#define SPI_GETBF(name,value)                  (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
++#define SPI_INSBF(name,value,old)              (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) | SPI_MKBF(name, value))
++
++#define spi_readl(port,reg)		readl((port)->regs + SPI_##reg)
++#define spi_writel(port,reg,value)	writel((value), (port)->regs + SPI_##reg)
++
++#endif /* #ifndef __SPI_H_ */
+diff -uprN u-boot-orig/drivers/atmel_spi.c u-boot/drivers/atmel_spi.c
+--- u-boot-orig/drivers/atmel_spi.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot/drivers/atmel_spi.c	2007-01-03 10:01:26.000000000 +0100
+@@ -0,0 +1,330 @@
++/*
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#ifdef CONFIG_ATMEL_SPI
++
++#include <part.h>
++#include <malloc.h>
++#include <spi.h>
++#include <atmel_spi.h>
++
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/byteorder.h>
++
++#include <asm/arch/memory-map.h>
++#include <asm/arch/platform.h>
++
++
++struct spi_info *spi;
++
++void spi_reset(struct spi_info *spi);
++
++int get_baud_div(struct spi_options_t * options, int busHz);
++
++int spi_selection_mode(unsigned char variable_ps,
++		unsigned char pcs_decode,
++		unsigned char delay);
++
++void spi_reset(struct spi_info *spi)
++{
++	spi_writel(spi, CR, SPI_BIT(CR_SWRST));
++}
++
++void spi_init()
++{
++	const struct device *dev;
++
++#ifdef CFG_SPI0
++	dev = get_device(DEVICE_SPI0);
++#elif CFG_SPI1
++	dev = get_device(DEVICE_SPI1);
++#else
++#error No SPI device available
++#endif
++	if (!dev)
++		return;
++
++	spi = malloc(sizeof(struct spi_info));
++	if (!spi)
++		return;
++
++	spi->regs = dev->regs;
++
++	/* Reset */
++	spi_reset(spi);
++
++	/* Master Mode */
++	spi_writel(spi, MR, SPI_BIT(MR_MSTR)
++			|SPI_MR_PCS_MASK
++			|(0<<SPI_MR_FDIV_OFFSET)
++			|(0<<SPI_MR_MODFDIS_OFFSET));
++
++	/* Selection mode:
++	 * no variable peripheral select
++	 * no peripheral chip select decode
++	 * 0 delay cycles after a chip select
++	 */
++	if (!spi_selection_mode(0, 0, 0))
++		return;
++
++	debug("spi: controller at 0x%08x\n", spi->regs);
++}
++
++int spi_selection_mode(unsigned char variable_ps,
++		unsigned char pcs_decode,
++		unsigned char delay)
++{
++	if (variable_ps > 1 || pcs_decode > 1) {
++		return SPI_ERROR_ARGUMENT;
++	}
++
++	/* Unset bitfields */
++	spi_writel(spi, MR, spi_readl(spi, MR) &
++			~(SPI_MR_PS_MASK|SPI_MR_PCSDEC_MASK
++				|SPI_MR_DLYBCS_MASK));
++	/* Set selction bits */
++	spi_writel(spi, MR, spi_readl(spi, MR)
++			|SPI_MKBF(MR_PS, variable_ps)
++			|SPI_MKBF(MR_PCSDEC, pcs_decode)
++			|SPI_MKBF(MR_DLYBCS, delay));
++
++	return SPI_OK;
++}
++
++int spi_select_chip(unsigned char chip)
++{
++	/* Assert all lines; no peripheral is selected */
++	spi_writel(spi, MR_PCS, spi_readl(spi, MR)|SPI_MR_PCS_MASK);
++
++	if (spi_readl(spi, MR) & SPI_MR_PCSDEC_MASK) {
++		ulong status;
++
++		/* The signal is decoded; allow up to 15 chips */
++		if (chip > 14) {
++			return SPI_ERROR_ARGUMENT;
++		}
++
++		status = spi_readl(spi, MR);
++		status &= ~SPI_MR_PCS_MASK;
++		status |= SPI_MKBF(MR_PCS, chip);
++		spi_writel(spi, MR, status);
++	} else {
++		if (chip > 3) {
++			return SPI_ERROR_ARGUMENT;
++		}
++
++		spi_writel(spi, MR, spi_readl(spi, MR) &
++				~(1<<(SPI_MR_PCS_OFFSET + chip)));
++	}
++
++	debug("spi: chip select %d activated\n", chip);
++
++	return SPI_OK;
++}
++
++int spi_unselect_chip(unsigned char chip)
++{
++	/* Assert all lines; no peripheral is selected */
++	spi_writel(spi, MR, spi_readl(spi, MR)|SPI_MR_PCS_MASK);
++
++	/* Last transfer, so deassert the current NPCS if CSAAT is set */
++	spi_writel(spi, CR, spi_readl(spi, MR)|SPI_CR_LASTXFER_MASK);
++
++	debug("spi: chip select %d deactivated\n", chip);
++
++	return SPI_OK;
++}
++
++int spi_setup_chip_reg(struct spi_options_t *options,
++		unsigned int busHz)
++{
++	int baudDiv = -1;
++	unsigned long csr = 0;
++
++	if (options->bits > 16 || options->bits < 8 || options->stay_act > 1) {
++		return SPI_ERROR_ARGUMENT;
++	}
++
++	baudDiv = get_baud_div(options, busHz);
++
++	if (baudDiv < 0) {
++		return -baudDiv;
++	}
++
++	/* Will use CSR0 offsets; these are the same for CSR0 - CSR3 */
++	csr = ((options->bits - 8)<<SPI_CSR0_BITS_OFFSET)|
++		(baudDiv<<SPI_CSR0_SCBR_OFFSET)|
++		(options->spck_delay<<SPI_CSR0_DLYBS_OFFSET)|
++		(options->trans_delay<<SPI_CSR0_DLYBCT_OFFSET)|
++		(options->stay_act<<SPI_CSR0_CSAAT_OFFSET);
++
++	switch (options->spi_mode) {
++		case 0:
++			csr |= (1<<SPI_CSR0_NCPHA_OFFSET); /* pass through */
++		case 1:
++			break;
++		case 2:
++			csr |= (1<<SPI_CSR0_NCPHA_OFFSET); /* pass through */
++		case 3:
++			csr |= (1<<SPI_CSR0_CPOL_OFFSET);
++			break;
++		default: /* Not in legal range */
++			return SPI_ERROR_ARGUMENT;
++	}
++
++	switch (options->reg) {
++		case 0:
++			spi_writel(spi, CSR0, csr);
++			break;
++		case 1:
++			spi_writel(spi, CSR1, csr);
++			break;
++		case 2:
++			spi_writel(spi, CSR2, csr);
++			break;
++		case 3:
++			spi_writel(spi, CSR3, csr);
++			break;
++		default:
++			return SPI_ERROR_ARGUMENT;
++	}
++
++	debug("spi: chip select %d registered\n", options->reg);
++
++	return SPI_OK;
++}
++
++void spi_enable()
++{
++	spi_writel(spi, CR, SPI_BIT(CR_SPIEN));
++}
++
++void spi_disable()
++{
++	spi_writel(spi, CR, SPI_BIT(CR_SPIDIS));
++}
++
++int spi_write(uchar *addr, int alen, uchar *buffer, int len)
++{
++	int sent = 0;
++	uchar *addr_p = addr;
++	uchar *buffer_p = buffer;
++	unsigned int timeout = SPI_TIMEOUT;
++
++	if ((alen + len) <= 0)
++		return -SPI_ERROR_ARGUMENT;
++
++	do {
++		while (!(spi_readl(spi, SR) & SPI_BIT(SR_TXEMPTY)) && --timeout);
++		if (!timeout)
++			return -SPI_ERROR_TIMEOUT;
++		if (len > 0 || alen > 1)
++			spi_writel(spi, TDR, *addr_p++ & 0x0000FFFF);
++		else
++			spi_writel(spi, TDR, (*addr_p++ & 0x0000FFFF)
++					| SPI_BIT(TDR_LASTXFER));
++		sent++;
++	} while (--alen > 0);
++
++	timeout = SPI_TIMEOUT;
++
++	do {
++		while (!(spi_readl(spi, SR) & SPI_BIT(SR_TXEMPTY)) && --timeout);
++		if (!timeout)
++			return -SPI_ERROR_TIMEOUT;
++		if (len > 1)
++			spi_writel(spi, TDR, *buffer_p++ & 0x0000FFFF);
++		else
++			spi_writel(spi, TDR, (*buffer_p++ & 0x0000FFFF)
++					| SPI_BIT(TDR_LASTXFER));
++		sent++;
++	} while (--len > 0);
++
++	return sent;
++}
++
++int spi_read(uchar *addr, int alen, uchar *buffer, int len)
++{
++	int received = 0;
++	uchar *addr_p = addr;
++	uchar *buffer_p = buffer;
++	unsigned int timeout = SPI_TIMEOUT;
++
++	if ((alen + len) <= 0)
++		return SPI_ERROR_ARGUMENT;
++
++	do {
++		while (!(spi_readl(spi, SR) & SPI_BIT(SR_RDRF)) && --timeout);
++		if (!timeout)
++			return -SPI_ERROR_TIMEOUT;
++		*addr_p++ = spi_readl(spi, RDR) & 0x000000FF;
++		--alen;
++		received++;
++	} while (alen > 0);
++
++	timeout = SPI_TIMEOUT;
++
++	do {
++		while (!(spi_readl(spi, SR) & SPI_BIT(SR_RDRF)) && --timeout);
++		if (!timeout)
++			return -SPI_ERROR_TIMEOUT;
++		*buffer_p++ = spi_readl(spi, RDR) & 0x000000FF;
++		--len;
++		received++;
++	} while (len > 0);
++
++	return received;
++}
++
++int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
++{
++	int len = 0;
++	uchar *dout_p = dout;
++	uchar *din_p = din;
++
++	while (--bitlen) {
++		if (spi_write(dout_p++, 1, 0, 0) != 1)
++			break;
++		if (spi_read(din_p++, 1, 0, 0) != 1)
++			break;
++		len++;
++	}
++
++	return len;
++}
++
++int get_baud_div(struct spi_options_t *options, int busHz) {
++	int baudDiv = 0;
++
++	baudDiv = busHz / options->baudrate;
++
++	if (baudDiv > (SPI_CSR0_SCBR_MASK<<SPI_CSR0_SCBR_OFFSET)
++			|| baudDiv <= 0) {
++		return -SPI_ERROR_ARGUMENT;
++	}
++
++	return baudDiv;
++}
++
++#endif /* CONFIG_ATMEL_SPI */
+diff -uprN u-boot-orig/drivers/Makefile u-boot/drivers/Makefile
+--- u-boot-orig/drivers/Makefile	2007-01-01 19:26:46.000000000 +0100
++++ u-boot/drivers/Makefile	2007-01-01 16:10:49.000000000 +0100
+@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
+ LIB	= libdrivers.a
+ 
+ OBJS	= 3c589.o 5701rls.o ali512x.o \
+-	  atmel_usart.o atmel_lcdc.o \
++	  atmel_usart.o atmel_lcdc.o atmel_spi.o \
+ 	  bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
+ 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
+ 	  e1000.o eepro100.o \
============================================================
--- packages/u-boot/u-boot_1.1.4.bb	d038552bd2f9296f6e46ab33c2c4ebb364477fec
+++ packages/u-boot/u-boot_1.1.4.bb	f33798683ca5789d2b3c96f26805a5f148b78370
@@ -1,24 +1,27 @@ require u-boot.inc
 require u-boot.inc
 
+PR = "r1"
+
 DEFAULT_PREFERENCE = "-1"
 
 SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \
           file://u-boot-make381-fix.patch;patch=1"
 
 SRC_URI_append_gumstix = "\
-						  file://u-boot-autoscript.patch;patch=1 \
-						  file://u-boot-base.patch;patch=1 \
-						  file://u-boot-crc-warning-not-so-scary.patch;patch=1 \
-						  file://u-boot-flash-protect-fixup.patch;patch=1 \
-						  file://u-boot-fw_printenv.patch;patch=1 \
-						  file://u-boot-install.patch;patch=1 \
-						  file://u-boot-jerase-cmd.patch;patch=1 \
-						  file://u-boot-jffs2-new-nodetypes.patch;patch=1 \
-						  file://u-boot-loadb-safe.patch;patch=1 \
-						  file://u-boot-mmc-init.patch;patch=1 \
-						  file://u-boot-mmcclk-alternate.patch;patch=1 \
-						  file://u-boot-smc91x-multi.patch;patch=1 \
-						  file://u-boot-zzz-osx.patch;patch=1"
+	file://u-boot-autoscript.patch;patch=1 \
+	file://u-boot-base.patch;patch=1 \
+	file://u-boot-crc-warning-not-so-scary.patch;patch=1 \
+	file://u-boot-flash-protect-fixup.patch;patch=1 \
+	file://u-boot-fw_printenv.patch;patch=1 \
+	file://u-boot-install.patch;patch=1 \
+	file://u-boot-jerase-cmd.patch;patch=1 \
+	file://u-boot-jffs2-new-nodetypes.patch;patch=1 \
+	file://u-boot-loadb-safe.patch;patch=1 \
+	file://u-boot-mmc-init.patch;patch=1 \
+	file://u-boot-mmcclk-alternate.patch;patch=1 \
+	file://u-boot-smc91x-multi.patch;patch=1 \
+	file://u-boot-zzz-osx.patch;patch=1"
+
 SRC_URI_append_amsdelta = "\
 	http://the.earth.li/pub/e3/u-boot-amsdelta-20060519.diff;patch=1"
 
@@ -26,9 +29,24 @@ SRC_URI_append_avr32= "\
         file://u-boot-dht-walnut-df2.patch;patch=1"
 
 SRC_URI_append_avr32= "\
-             http://avr32linux.org/twiki/pub/Main/UbootPatches/u-boot-1.1.4-avr1.patch.bz2;patch=1"
+	http://avr32linux.org/twiki/pub/Main/UbootPatches/u-boot-1.1.4-avr1.patch.bz2;patch=1 \
+	file://avr32-boards-fix-flash-read.patch;patch=1 \
+	file://lcdc-driver-for-avr32.patch;patch=1 \
+	file://spi-driver-for-avr32.patch;patch=1 \
+	file://at32ap-add-framebuffer-address.patch;patch=1 \
+	file://at32ap-add-spi-initcalls.patch;patch=1 \
+	file://at32ap-add-system-manager-header-file.patch;patch=1 \
+	file://ap7000-add-spi-device-and-lcdc-base-address.patch;patch=1 \
+	file://libavr32-add-spi-and-lcd-board-support.patch;patch=1 \
+	file://cmd-bmp-add-gzip-compressed-bmp.patch;patch=1 \
+	file://lcd-add-24-bpp-support-and-atmel-lcdc-support.patch;patch=1 \
+	file://atstk1000-spi-support.patch;patch=1 \
+	file://atstk1000-ltv350qv-display-support.patch;patch=1 \
+	file://atstk1000-add-lcd-and-spi-to-config.patch;patch=1 \
+	file://at32ap-add-define-for-sdram-test.patch;patch=1 \
+	file://fix-mmc-data-timeout.patch;patch=1 \
+"
 
-
 EXTRA_OEMAKE_gumstix = "CROSS_COMPILE=${TARGET_PREFIX} GUMSTIX_400MHZ=${GUMSTIX_400MHZ}"
 TARGET_LDFLAGS = ""
 
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