Phase 0 devices just running @100MHz?
philipp.zabel at gmail.com
Fri Mar 9 11:04:49 CET 2007
On 3/9/07, Siarhei Siamashka <siarhei.siamashka at gmail.com> wrote:
> On Friday 09 March 2007 11:07, pHilipp Zabel wrote:
> > On 3/8/07, Nils Faerber <nils.faerber at kernelconcepts.de> wrote:
> > > Pierre Hébert schrieb:
> > > > It doesn't seem so bad : my s3c2440 at 400MHz shows 199bogomips, so at
> > > > 200MHz 100bogomips seems correct (s3c2440 has the same cpu as s3c2410).
> > > > I don't know if the bogomips indication is a value in which we can
> > > > really trust, these little devices are really efficient even at
> > > > 100/200bogomips.
> > >
> > > The bogomips result is a little different depending on the core
> > > architecture. So for the Samsung CPU bogomips ~= 1/2 MHz.
> > > OK, good to know!
> > > A PXA270 I have on my desk has the ~ 1:1 bogomips to MHz mapping...
> > I guess this depends on how many cycles the __delay(loops_per_jiffy) loop
> > ENTRY(__delay)
> > subs r0, r0, 1
> > bhi __delay
> > mov pc,lr
> > takes on the given cpu.
> > On the S3C2440 subs takes 1S and bhi takes 2S+1N cycles.
> > Is information about the PXA27x instruction cycle times available
> > somewhere?
> If you are interested in estimating cpu clock frequency, you can try a simple
> test program I have written some time ago:
Thanks, I'm just interested in understanding the bogomips issue for now.
> A few references related to arm cpu performance.
> Instruction timings and optimization guide for ARM9E:
> Instruction timings and optimization guide for ARM11 (used in OMAP2):
> Instruction timings and optimization guide for Intel XScale:
This is exactly what I was looking for!
On Xscale, b(hi) has a minimum issue latency of 1 cycle if there is no
branch misprediction, same for sub(s) (with a result latency of
So the average __delay loop on Xscale takes 2 cycles opposed to 4 on
the S3C2440, resulting in a factor of 1:2 in the BogoMips values.
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