cpu reclocking to 500Mhz, overclocking to 533Mhz, performance tests and bootloader images

[Benjamin Deering]

Hi,

Thanks for your research into reclocking.  I've tried the 533-CLK2 
version on one of my freerunners and it seems to work well.  I am trying 
to put your changes into my qi build.  You have one patch posted for the 
500-83 uboot which wasn't too difficult to adapt to qi.

Do you have the PLL divider values (not sure if that is the correct 
term) for the other speeds?

Ben



Here is is the diff for the 500mhz version with CLK 2 (be careful, might 
fry your fr, etc)


diff --git a/src/cpu/s3c2442/gta02.c b/src/cpu/s3c2442/gta02.c
index e9bc0a3..aadb495 100644
--- a/src/cpu/s3c2442/gta02.c
+++ b/src/cpu/s3c2442/gta02.c
@@ -35,7 +35,7 @@

  #define GTA02_DEBUG_UART 2
  #define PCF50633_I2C_ADS 0x73
-#define BOOST_TO_400MHZ 1
+#define BOOST_TO_533MHZ 1

  static int battery_condition_reasonable = 0;

@@ -85,12 +85,12 @@ const struct pcf50633_init pcf50633_init[] = {

         { PCF50633_REG_AUTOENA,         0x01 }, /* always on */

-       { PCF50633_REG_DOWN1OUT,        0x1b }, /* 1.3V (0x1b * .025V + 
0.625V) */
+       { PCF50633_REG_DOWN1OUT,        43 }, /* 1.3V (0x1b * .025V + 
0.625V) */
         { PCF50633_REG_DOWN1ENA,        0x02 }, /* enabled if GPIO1 = 
HIGH */
         { PCF50633_REG_HCLDOOUT,        21 },   /* 3.0V (21 * 0.1V + 
0.9V) */
         { PCF50633_REG_HCLDOENA,        0x01 }, /* ON by default*/
-       { PCF50633_REG_DOWN1OUT,        0x1b }, /* 1.3V (0x1b * .025V + 
0.625V) */
+       { PCF50633_REG_DOWN1OUT,        43 }, /* 1.3V (0x1b * .025V + 
0.625V) */
         { PCF50633_REG_DOWN1ENA,        0x02 }, /* enabled if GPIO1 = 
HIGH */

         { PCF50633_REG_INT1M,           0x00 },
@@ -299,10 +299,12 @@ void port_init_gta02(void)
                                     PCF50633_I2C_ADS, 
PCF50633_REG_BVMCTL) & 1);

         if (battery_condition_reasonable) {
-               /* change CPU clocking to 400MHz 1:4:8 */
+               /* change CPU clocking to 533MHz 1:6:12 */

-               /* clock divide 1:4:8 - do it first */
-               *CLKDIVN = 5;
+               /* clock divide 1:6:12 - do it first */
+               *CLKDIVN = 7;
+unsigned int* CAMDIVN  =  (unsigned int*)    0x4C000018;
+               *CAMDIVN |=  (1<<8);
                 /* configure UPLL */
                 *UPLLCON = ((88 << 12) + (4 << 4) + 2);
                 /* Magic delay: Page 7-19, seven nops between UPLL and 
MPLL */
@@ -316,7 +318,7 @@ void port_init_gta02(void)
                         "nop\n"
                 );
                 /* configure MPLL */
-               *MPLLCON = ((42 << 12) + (1 << 4) + 0);
+               *MPLLCON = ((117 << 12) + (1 << 4) + 1);

                 /* get debug UART working at 115kbps */
                 serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 50 /* 
50MHz */);
@@ -666,7 +668,9 @@ const struct board_api board_api_gta02 = {
         .get_ui_keys = get_ui_keys_gta02,
         .get_ui_debug = get_ui_debug_gta02,
         .set_ui_indication = set_ui_indication_gta02,
                                       "console=tty0 "
                                       "console=ttySAC2,115200 "
                                       "init=/sbin/init "
diff --git a/src/cpu/s3c2442/lowlevel_init.S 
b/src/cpu/s3c2442/lowlevel_init.S
index 2a1654c..9ba45a5 100644
--- a/src/cpu/s3c2442/lowlevel_init.S
+++ b/src/cpu/s3c2442/lowlevel_init.S
@@ -105,22 +105,22 @@
  #define B5_PMC                 0x0     /* normal */

  #define B6_MT                          0x3     /* SDRAM */
-#define B6_Trcd                        0x1     /* 3clk */
+#define B6_Trcd                        0x0     /* 23clk */

  #define B6_SCAN                        0x1     /* 9bit */
  #define B7_SCAN                        0x1     /* 9bit */


  #define B7_MT                          0x3     /* SDRAM */
-#define B7_Trcd                        0x1     /* 3clk */
+#define B7_Trcd                        0x0     /* 2clk */

  /* REFRESH parameter */
  #define REFEN                          0x1     /* Refresh enable */
  #define TREFMD                 0x0     /* CBR(CAS before RAS)/Auto 
refresh */
-#define Trp                            0x1     /* 3clk */
-#define Trc                            0x3     /* 7clk */
-#define Tchr                           0x2     /* 3clk */
-//#define REFCNT                       1113    /* period=15.6us, 
HCLK=60Mhz, (2048+1-15.6*60) */
+#define Trp                            0x0     /* 2clk */
+#define Trc                            0x1     /* 5clk */
+#define Tchr                           0x0     /* 3clk */
+//#define REFCNT                       997     /* period=17.5us, 
HCLK=60Mhz, (2048+1-15.6*60) */
  #define REFCNT                 997     /* period=17.5us, HCLK=60Mhz, 
(2048+1-15.6*60) */
  /**************************************/

@@ -129,6 +129,7 @@ lowlevel_init:

         ldr     r0, =SMRDATA
         ldr     r1, =BWSCON     /* Bus Width Status Controller */
+       mov     r2, #0
         add     r2, r0, #13*4
  0:
         ldr     r3, [r0], #4
@@ -158,5 +159,5 @@ SMRDATA:
      .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
      .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
           .word 0xb1
-    .word 0x30
-    .word 0x30
+    .word 0x20
+    .word 0x20