[gta02-core] ECN0001 comments+patch on SPI
Rask Ingemann Lambertsen
ccc94453 at vip.cybercity.dk
Sat Sep 5 17:32:11 CEST 2009
On Fri, Sep 04, 2009 at 09:48:17AM -0300, Werner Almesberger wrote:
> Rask Ingemann Lambertsen wrote:
> > Hardware SPI likely wasn't designed with the dual protocol accelerometers
> > in mind. IIRC there's a comment in arch/arm/mach-s3c2442/mach-gta02.c about
> > the workaround needed to keep the I2C-mode accelerometer from responding.
> Whether the SPI vs. I2C logic could actually misfire on the
> "deselected" accelerometer is something we never fully analyzed.
> SDI/SDA should only change if SPC/SCL is low, so this would prevent
> the I2C transceiver from ever seeing a START condition.
Figure 22-2 of the SC32442B manual shows SPI data changing on SPI clock
> > I suppose reception could be realigned by prepending a dummy bit to the
> > bit stream or by removing the first 7 bits. A D-flipflop or two could do
> > the former I think.
> Ah, interesting idea. If the shift is in the right direction (I think
> it is) and happens all the time (I didn't test this), adding a
> software-generated SPI clock pulse may indeed help.
The direction of shift doesn't matter so much if you send software SPI
clock pulses, just ask the card for e.g. firmware revision and discard bits
until the alignment is right.
> > Do we know if the receive misalignment is triggered by the 12 MHz
> > frequency or by the clock divider to get 12 MHz from 50 MHz PCLK? Since
> > we'll be using 66 MHz PCLK in gta02-core, it would be nice to know.
> All my tests were done on a GTA02. I did't try a different PCLK.
> You're right, depending on what actually causes the problem inside
> the 2442, how you divide the clock may make a difference.
The thing is that the 2442 SPI interface is poorly documented in places.
For example, when the user's manual specifies a 25 MHz maximum baud rate, it
is not clear where that limit comes from (signal quality or clock rate), if
it applies to both master mode and slave mode or if it applies to all the
operating modes (polled, interrupt and DMA). In this particular case we'll
be running in master mode, so the minimum clock divider of two gives 25 MHz
with a 50 MHz PCLK as in GTA02 and 33 MHz with a 66 MHz PCLK as in
gta02-core. Does it mean that gta02-core WLAN SPI is effectively limited to
66 MHz / 3 = 22 MHz rather than 66 MHz / 2 = 33 MHz?
Rask Ingemann Lambertsen
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