[gta02-core] The 1000 faces of 0402 (1005)

[Rene Harder]

Werner Almesberger wrote:
> One item that's been pending for a good while are the footprints for
> standard passive components, i.e., the ubiquitous 0402, 0603, etc.
>
> There is a bewildering variety of pad sizes and keepout areas in
> use in the industry. A few examples:
>
> 0402 (1005), package about 1 x 0.5 mm, terminals 0.2-0.25 mm:
>
> 			Package		Overall size	Outline (keepout)
> 					(pads)
> 	My 0402	[1]	-		1.30  x 0.60	1.55 x 0.85
> 	GTA02 (silk)	-		-		2.0  x 1.1
> 	GTA02 (real)	-		1.4  x 0.5	1.7  x 0.8
> 	AVX [2]		1.0 x 0.55	1.7  x 0.55	-
> 	Panasonic [3]	1.0 x 0.5	1.5  x 0.5 *	-
> 	Vishay [4]	1.0 x 0.5	1.3  x 0.6	-
>
> 0603 (1608), package about 1.6 x 0.8 mm, terminals 0.3 mm:
>
> 			Package		Overall size	Outline (keepout)
> 					(pads)
> 	My 0603 [2]	-		2.0  x 0.9	2.25 x 1.15
> 	KiCad SM0603	-		2.2  x 1.15	2.3  x 1.3
> 	AVX [2]		1.6  x 0.81	2.3  x 0.8	-
> 	Panasonic [3]	1.6  x 0.80	2.1  x 0.8 *	-
> 	Vishay [4]	1.55 x 0.85	2.0  x 0.9	-
>
> [1] http://people.openmoko.org/werner/gta02-core/gta02-core-modules.pdf
> [2] http://www.avx.com/docs/Catalogs/accuf-p.pdf
> [3] http://industrial.panasonic.com/www-data/pdf/AOA0000/AOA0000CE1.pdf
> [4] http://www.vishay.com/doc?20035
>
> *  Panasonic specify pad sizes +/- 0.1 mm. Size shown is average.
>
> There are the following goals here:
>
> 1) make the keepout area large enough that we won't have problems
>    fitting the components
>
> 2) make the pads large enough that also soldering will go well
>
> 3) make the keepout area small enough that it won't routinely get
>    violated because "everyone knows there's a lot of slack."
>    If you look at the GTA02 silkscreen, that's precisely what
>    happened there. Good luck finding the ones that are really too
>    close :-)
>
> I took my parameters from Vishay's reference and just added a 4 mil
> clearance for the keepout area. For 0603, this is also within the
> range of Vishay's parameters. For 0402, Vishay are 0.1 mm shorter
> than anyone else.
>   

I think the keepout area should meet our minimum trace clearance so we
do not get into any trouble during production.

According to Panasonic the land pattern heavily depends on the soldering
technique:
"In case of flow soldering, the land width must be smaller than the Chip
Resistor width to control the solder amount properly.
Generally, the land width should be 0.7 to 0.8 times (W) of the width of
chip resistor. In case of reflow soldering, solder
amount can be adjusted, therefore the land width should be set to 1.0 to
1.3 times chip resistor width (W)."  [3, page 4]


Does anyone know, how Kicad handles the solder stop mask, is it
generating the mask from the solder lands and what's their clearance?