[gta02-core] The 1000 faces of 0402 (1005)

Werner Almesberger werner at openmoko.org
Sat Sep 5 23:39:58 CEST 2009

Rene Harder wrote:
> I think the keepout area should meet our minimum trace clearance so we
> do not get into any trouble during production.

Hmm, this sounds so obvious, but it's also tricky.

- for component to trace conflicts, the keepout distance would equal
  the clearance from the package's edge, plus any placement tolerance.

- for pad to pad conflicts, the sum of the keepout distances from the
  pads would equal the clearance.

- for component to pad conflicts, the sum of the keepout distance from
  component and opposing pad would equal the clearance plus any
  placement tolerance.

- there could also be component to component conflicts. If we also
  want to maintain the clearance between components, the keepout
  distance of each component would be the placement tolerance plus
  half the clearance.

Let's see what this yields. Let p be the distance of the pads's edge
from our origin, r be the distance of the component's edge from the
origin, c the clearance, and t the placement tolerance. Then the
border of the keepout area would be at position k. So we get,
assuming all parts are equal:

(1) k >= r+c+t
(2) k >= p+c/2
(3) k >= (p+r+c+t)/2
(4) k >= r+t+c/2

(4) is weaker than (1), so we can eliminate (4).

Let's assume t = c. We don't know t but we have c = 5 mil (0.127 mm).
Then we can replace c with t end get:

(1) k >= r+2*t
(2) k >= p+t/2
(3) k >= (p+r)/2+t

So (2) is weaker than (3). One equation less.

(1) k >= r+2*t
(3) k >= (p+r)/2+t

Using the package width and t = 0.127 mm, we get:

			r	p	(1)	(3)	My value
Panasonic 0402, width	0.5	0.5	0.75	0.63	0.85
Vishay 0402, width	0.5	0.6	0.75	0.68	=
Panasonic 0402, length	1.0	1.5	1.25	1.38	1.55
Vishay 0402, length	1.0	1.3	1.25	1.28	=
Panasonic 0603, width	0.8	0.8	1.05	0.93	1.15
Vishay 0603, width	0.85	0.9	1.1	1.00	=
Panasonic 0603, length	1.6	2.1	1.85	1.98	2.25
Vishay 0603, length	1.55	2.0	1.8	1.90	=

So this looks good, doesn't it ?

A while ago, I asked whether silk screen should mark a border with
the edge of the line or its center. I think I can answer this myself:
for traces and such, DRC generally keeps us out of trouble. For
placing components, it's better if the center of silk is used, because
one can then just overlay the silk edges of adjacent components.

I've changed stdpass.fpd accordingly. I also increased the overly thin
silk screen lines from 2 mil to 5 mil.

> According to Panasonic the land pattern heavily depends on the soldering
> technique:

Ah, thanks. That explains the +/- 0.1 mm.

> In case of reflow soldering, solder
> amount can be adjusted, therefore the land width should be set to 1.0 to
> 1.3 times chip resistor width (W)."  [3, page 4]

Okay, we have that. 0402: package width about 0.5 mm, pad width 0.6 mm.
For 0603: package width about 0.8 mm, pad width 0.9 mm.

> Does anyone know, how Kicad handles the solder stop mask, is it
> generating the mask from the solder lands and what's their clearance?

The clearance is set in Dimensions/Tracks and Vias/Mask clearance.
The effective solder mask is the solder mark layer of the footprint,
plus the clearance. If the footprint doesn't specify a solder mask,
the land will have no opening in the solder mask !

The usual setting is that all pads have the same shape and side in
their solder mask layer as they have in their copper and solder
paste layer.

- Werner

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