Cesar Eduardo Barros cesarb at cesarb.net
Fri Aug 29 00:56:54 CEST 2008

Joerg Reisenweber escreveu:
> Am Do  28. August 2008 schrieb Joerg Reisenweber:
>> Am Do  28. August 2008 schrieb Werner Almesberger:
>>> Joerg Reisenweber wrote:
>>>> Should we try to set up a ECN demanding future (GTA02) devices to have 
>> this? 
>>>> Andy? Werner? I consider engineering risk very low, as we always may 
> fall 
>>>> back to current scheme.
>>> Sounds good and safe to me as well. One problem is that UCLK/GPH8 is
>>> currently used in GTA03, so we'd have to find a way to free this if
>>> we don't want to regress.
>> one more good reason to do it *now*, as we easily can reorder GPIO for GTA03 
>> in this stage of development.
>> So I guess I'll set up a ECN for GTA02 *and* GTA03.
>> Andy, any comments?
> Ah, and btw: does anybody have a decent set of bookmarks/pointers/quotes to 
> S3C2442 datasheet sections needed to facilitate my duty to validate this ECN? 
> Much appreciated ;-)!

Do not know if this is what you want, but:

- CLKOUT is described on chapter 7 (clock & power management), as is the 
UPLL (together with the the 48MHz frequency). The output selection is at 
CLKSEL on MISCCR on chapter 9 (I/O ports).
- On the input side, the selection is made at the UCON registers, 
described at chapter 11 (UART). The baud rate formula can also be found 
there (UBRDIV registers).
- The pad function selection is as usual, described on chapter 9 (I/O 
ports). Both GPH8 and GPH9/10 default at GPHCON to GPIO input, and at 
GPHDN to pulldown enabled (resulting on two 100K pull downs and two 
inputs on the trace, which should not cause any problem).
- If I'm reading the table on chapter 1 (overview) correctly, on sleep 
GPH8 would become Hi-Z and GPH9/10 would output a low logic level (again 
should not cause any problem). The same table coupled with the next one 
shows the type of both pins.

This is all for GTA02. My email backlog is growing again, so I probably 
missed an email which would tell me which SoC the GTA03 will use.

Of course, what matters is what the datasheet won't tell:

- Chapter 25 (electrical data) seems to assume both in the diagrams and 
in the tables that the pin will be driven from HCLK. How will it behave 
being driven from the USB PLL?
- In the same chapter, what are the timing constraints for UEXTCLK? I'd 
guess it's the same as EXTCLK, but didn't find anything saying that 
explicitly. Will it be compatible with the output from the USB PLL?

Cesar Eduardo Barros
cesarb at cesarb.net
cesar.barros at gmail.com

More information about the hardware mailing list