NOR flash, NAND flash and the steppingstone
wolfgang.draxinger at draxit.de
Mon Sep 8 02:27:23 CEST 2008
last week I finally got my GTA02v6, together with debug board.
Naturally, as a geek, I've to tinker with it :-)
Currently I'm reading the schematics, s3c2442 user manual and the
wiki. Now I think I understood, how things are working together, but
I'd like some affirmation.
The s3c2442 has signals OM[0:1].
If OM[0:1]==00 on system reset the steppingstone is executed and the
first 4k of NAND flash are copied to a special portion of SRAM (the
stepping stone) which is mapped to memory addresses
0x0000_0000...0x0000_0fff. Then executions with %pc = 0x0000_0000.
If OM[0:1]==01 || OM[0:1]==10, then the 4k of steppingstone SRAM are
mapped to 0x4000_0000...0x4000_0fff and it's content left undefined.
Execution starts again from %pc=0x0000_0000, but this time the memory
interface is used to address external memory, organized in 8 banks.
The NOR flash chip is interfaced to the memory bus, and gets chip
selected (CS) by AND-ing GCS0 and GCS3. Well, actually I'm a bit
puzzled here, as some lines have inverted signalling. So the AND gate
could, in the combination with inverted lines GCS0, GCS3 be as well
an OR on the chip select. And only the latter makes sense to me, as,
how I understood it, only one of the GCS lines can be active at a
time. Anyway. GCS0 means, the NOR will be mapped starting from
0x0000_0000 and GCS3 means, nor starts at 0x1800_0000
The external SDRAM chip has been connected to GCS7, i.e. it is memory
bank7 at 0x3800_0000...0x3, also the place where the bootloader and
stuff are housed. In the schematics it is shown, that address lines
are connected by one bit shifted. I wonder if that means
* the memory can be addressed 2 byte aligned only
* the s3c2442 internally also does that shift
Address lines 24 and 25 are used to select memory banks within the
SDRAM chip, independent of the banking done with the GCS signals. I
wonder if this happens with the internal SDRAM, too.
The internal SDRAM in the s3c2442 is internally connected to the
memory bus, but the CS comes from external line. For that, the GCS6
signal is backrouted to CS input of the s3c244s, and so mapping the
internal SDRAM to 0x3000_0000.
Both SDRAMs are 64MiB in size, so they would cover memory ranges
0x3000_0000...0x3400_0000 and 0x3800_0000...0x3c00_0000, leaving some
gap between 0x3400_0000 and 0x3800_0000. This gap must be told to the
Finally, to flash the NOR flash, if I understood everything right, one
would connect the debug board to the GTA02, supply the NOR_WP line
with power (how much volts?), boot with the AUX button hold, so that
the CPU doesn not go into steppingstone mode. Then using JTAG the CPU
gets hold and by writing data using JTAG to addresses 0x0000_0000...
or 0x1800_0000 that data ends up in NOR flash. One could also boot
with steppingstone enabled, i.e. OM[0:1]==00, but then only the
0x1800_0000 mapping would be avaliable to flash the NOR.
Except the steppingstone (internal) NAND flash can be accessed
programmatically only through the NAND flash controller of the
s3c2442, i.e. it is not memory mapped. However normal memory bus data
lines are used for transfer. NAND flash protocol (read a whole block
modify a few bytes, write back block) is handled transparently by the
flash controller, though.
Well, that's about it. Did I get everything right?
Oh, one last question: I expect the NOR flash u-boot has it's very own
environment stored in NOR flash, and as such can't be changed,
without fiddling with the NOR flash write power line?
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