[patch 3/6] mach-gta01: Change CLKVAL in mach-gta01

[Harald Welte]

Hi Stefan.

First of all, thanks for your patch.

[rtp/fluffs: please feel free to skip towards the end of this e-mail]

On Thu, Oct 18, 2007 at 08:10:12PM +0800, Stefan Schmidt wrote:
> CLKVAL 5 works fine for both VGA and QVGA mode of the LCM. Also the samsung
> datasheet states on p. 15-42 that CLKVAL should be 5 for a frame rate of 60-70Hz
> 
> Signed-off-by: Stefan Schmidt <stefan at openmoko.org>
> 
> Index: linux-2.6.22.5/arch/arm/mach-s3c2410/mach-gta01.c
> ===================================================================
> --- linux-2.6.22.5.orig/arch/arm/mach-s3c2410/mach-gta01.c	2007-10-18 15:43:23.000000000 +0800
> +++ linux-2.6.22.5/arch/arm/mach-s3c2410/mach-gta01.c	2007-10-18 15:43:35.000000000 +0800
> @@ -279,7 +279,7 @@
>  	.regs	= {
>  		.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
>  				  S3C2410_LCDCON1_TFT |
> -				  S3C2410_LCDCON1_CLKVAL(0x01),	/* HCLK/4 */
> +				  S3C2410_LCDCON1_CLKVAL(0x05),	/* HCLK/4 */

The formula for the pixel clock VCLK is:

HCLK / (CLKVAL+1)*2

I.e. with CLKVAL = 0x01, we get HCLK/4 which is 133MHz/4 = 33MHz

At 648*520 gross pixels, we get 33000000/(648*520) = 97 Hz
At 326*344 gross pixels, we get 33000000/(326*344) = 294 Hz

This is clearly a quite high refresh frequency.  However, the LCM data
sheet states VCLK should be between 22MHz and 28MHZ. 

So in fact we drive the LCM at too high pixel clock.  CLKVAL=0x02 gives
us 22.17MHz (65Hz refresh rate at VGA).  I believe this is due to the
historical fact of running the CPU at 200MHz (thus HCLK at 100MHz) in
the early days of GTA01 development.

If we change CLKVLA to 0x05, like you proposed, then we get 133MHz/12 =
11.08Mhz

At 648*520 gross pixels, we get 11800000/(648*520) = 35 Hz
At 326*344 gross pixels, we get 11800000/(326*344) = 105 Hz

So this means that 
1) we don't fulfill the minimum LCM pixel clock of 22MHz in VGA
2) we have a refresh rate of 35Hz which is definitely on the low end.

Since QVGA has a minimum LCM pixel clock of 6.5MHz, we should probably
drive it at as little as possible above that speed. (consumes less power
and less memory bandwidth).

This means, CLKVAL should be 9 (resulting in HCLK/20, i.e. 6.65MHz

At 326*344 gross pixels, we get 6500000/(326*344) = 57.9Hz
which is quite reasonable.

So I suggest

a) we switch the default CLKVAL to 0x02.

b) we think of how to switch CLKVAL depending on the framebuffer mode.
   Ideally, this should just work like in the VGA world:  The screen
   specifies it's vsync and hsync ranges - and the driver calculates
   the pixel and other clocks depending on this.  Sooner or later,
   s3c2410_fb will need this anyway, since if you start to use things
   like cpufreq (DVS / SLOW mode) to scale down the core clock rate,
   HCLK will be affected and CLKVAL will have to be re-calculated
   on-the-fly.  rtp / fluffs might have some ideas on this.

   As an interim, QVGA might actually still work with CLKVAL=0x02, even
   if it's suboptimal.

Cheers,

[oh, and btw:  If you change CLKVAL, please also change the comment next
 to it.  HCLK/4 is only true for CLKVAL = 0x01]
-- 
- Harald Welte <laforge at openmoko.org>          	        http://openmoko.org/
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