[PATCH 0/9] Experimental S3C2410A cpufreq driver

Cesar Eduardo Barros cesarb at cesarb.net
Thu Feb 14 00:01:32 CET 2008

Harald Welte escreveu:
>> See s3c2410_get_transition_latency() and  
>> s3c2442_get_transition_latency(). Both try to find out how long will it  
>> take for the PLL lock time to pass (on GTA01 only to tell the cpufreq  
>> core the transition latency, on GTA02 also to know how long to wait  
>> after turning on the PLL before it can be used). However, the formula  
>> used is pure guesswork (I'm guessing it counts cycles from the 12MHz 
>> input).
> I think this is the logical conclusion, since there is no other clock
> during PLL reconfiguration.

Actually, there is another clock: the divided 12MHz clock (on the slower 
slow modes).

Cesar Eduardo Barros
cesarb at cesarb.net
cesar.barros at gmail.com

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