why we set CAMDIVN and CLKDIVN

[xiangfu]

i find :
 set CLKDIVN is to make    FCLK:HCLK:PCLK = 1:3:6

HDIVN [2:1]    00 : HCLK = FCLK/1.
                    01 : HCLK = FCLK/2.
                    10 : HCLK = FCLK/4 when CAMDIVN[9] = 0.
                            HCLK= FCLK/8 when CAMDIVN[9] = 1.
                    11 : HCLK = FCLK/3 when CAMDIVN[8] = 0.
                            HCLK = FCLK/6 when CAMDIVN[8] = 1.
PDIVN  [0]    0: PCLK has the clock same as the HCLK/1.  0
                    1: PCLK has the clock same as the HCLK/2.

----i still don't know why we set CAMDIVN
----i still can't run the C function by add "stack_setup".


xiangfu wrote:
> # define CLKDIVN        0x4C000014    /* clock divisor register */
> # define CLKDIVN_val      7             /* FCLK:HCLK:PCLK = 1:3:6 */
>    /* FCLK:HCLK:PCLK = 1:2:4 */
-- i should delete this line   " /* FCLK:HCLK:PCLK = 1:2:4 */ " : )
>    ldr    r0, =CLKDIVN
>    mov    r1, #CLKDIVN_val
>    str    r1, [r0]
>
>    /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
> # define CAMDIVN        0x4C000018
>    ldr    r0, =CAMDIVN
>    mov    r1, #0
>    str    r1, [r0]
> ----i don't know why we set CAMDIVN and CLKDIVN
>
> ----i still can't run the C function by add "stack_setup".
>
>