[s3c6410 BSP] Funnies and questions
ben at simtec.co.uk
Mon Nov 3 15:58:21 CET 2008
On Mon, Nov 03, 2008 at 02:38:20PM +0000, Andy Green wrote:
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> Somebody in the thread at some point said:
> | That's something your bootloader should really setup, all this code
> | is doing is reading the current settings for where the clocks are
> | sourced from. Either set this in the bootloader, or it should be
> | allowable to set these registers early in the machine specific
> | setup.
> |>  This nearly caused a heart attack when I noticed it yesterday since
> |> it looked like the iROM was using the (NC on GTA03) 27MHz source, but I
> |> verified in bootloader it's EPll.
> | Hmm, iirc the EPLL is selected via the mmc_bus clock, it might be using
> | the HCLK fed into the unit which is another possible clock source?
> CLK_SRC is 0x00002007 early in the bootloader, b19b18 = 00 = MMC0 =
> MOUTepll; 11 there would be 27MHz source. I didn't spot where the
> bootloader MMC stuff changes the clock source to 27MHz, so something is
> fishy somewhere.
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 78938a5..b1082c1 100644
@@ -205,8 +205,8 @@
#define S3C6400_CLKSRC_MMC2_SHIFT (22)
#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
#define S3C6400_CLKSRC_MMC1_SHIFT (20)
-#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
-#define S3C6400_CLKSRC_MMC0_SHIFT (1)
+#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
+#define S3C6400_CLKSRC_MMC0_SHIFT (18)
#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
#define S3C6400_CLKSRC_SPI1_SHIFT (16)
#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
merged into s3c64xx and pushed out.
> - -Andy
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