[PATCH] debug-add-more-glamo-mem-speed-options.patch

[Andy Green]

People on bug

https://docs.openmoko.org/trac/ticket/2217

experiencing problems with default emmory settings on Glamo
reported that changing reg 0x200 <- 0xef0 as in 2.6.24 made
the problem not reproducible any more.

However this changes three bitfields, two are to do with
waitstates before sampling read and write cycles off the
bus, and the last is to do with which PLL provides the clock
to the memory interface unit logic.  The old settings has
all three of these very conservative, 3 waitstates and using
the 50MHz PLL instead of the 90MHz one; the new default
setting has all of these at their fastest of 0 wait states
and the 90MHz PLL.

This patch adds some more granular tests to the same

glamo3362.slow_memory=

parameter to see if we can find some middle ground.  For
example the issue may be the waitstates and not the PLL
source, in which case even users with the bad Glamo
behaviour can have the advantage of the faster PLL / bus
bandwidth.

0  90MHz PLL, no wait states (default)
1  50MHz PLL, 3 wait states
2  50MHz PLL, 2 wait states
3  50MHz PLL, 1 wait state
4  50MHz PLL, no wait states
5  90MHz PLL, 3 wait states
6  90MHz PLL, 2 wait states
7  90MHz PLL, 1 wait state

Signed-off-by: Andy Green <andy at openmoko.com>
---

 drivers/mfd/glamo/glamo-core.c |   30 ++++++++++++++++++++++++++++--
 1 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
index e6253de..28dc1f3 100644
--- a/drivers/mfd/glamo/glamo-core.c
+++ b/drivers/mfd/glamo/glamo-core.c
@@ -812,10 +812,36 @@ int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
 		 */
 
 		case 0x200:
-			if (slow_memory)
+			switch (slow_memory) {
+			/* choice 1 is the most conservative */
+			case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
 				__reg_write(glamo, script[i].reg, 0xef0);
-			else
+				break;
+			case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xea0);
+				break;
+			case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xe50);
+				break;
+			case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xe00);
+				break;
+
+			/* using PLL2 for memory bus increases CPU bandwidth significantly */
+			case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xef3);
+				break;
+			case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xea3);
+				break;
+			case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
+				__reg_write(glamo, script[i].reg, 0xe53);
+				break;
+			/* default of 0 or >7 is fastest */
+			default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
 				__reg_write(glamo, script[i].reg, 0xe03);
+				break;
+			}
 			break;
 
 		default: