trimarchi at gandalf.sssup.it
Wed Feb 4 13:27:22 CET 2009
Andy Green wrote:
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> Somebody in the thread at some point said:
> |> speed 9600 baud; rows 24; columns 80;
> | Ok, this is one problem. The other one is the interrupt latency. The
> | threshold is set on 8 chars
> | so you have ~800us to get chars from the buffer and it is quite a lot.
> What are we talking about there because it's unclear.
> At 9600bps each 10-bit character is about 1ms in transit.
> The threshold for the FIFO at 8 means that normally, the UART does not
> make an RX interrupt to the CPU until it has 8 characters. In the case
> where <8 characters come, it waits for a timeout and then makes the
> interrupt anyway.
Ok I wrong, I'm talking for 115200 but is ~4ms, I missed some :(. The
is on 9600 too?
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