[PATCH] fix s3c64xx_setrate_clksrc

[Werner Almesberger]

Some of the rate selection logic in s3c64xx_setrate_clksrc uses what
appears to be parent clock selection logic. This patch corrects it.

I also added a BUG_ON, since an overly large divider can cause
unrelated clocks to be changed.

Signed-off-by: Werner Almesberger <werner at openmoko.org>

---

Index: cam/arch/arm/plat-s3c64xx/s3c6400-clock.c
===================================================================
--- cam.orig/arch/arm/plat-s3c64xx/s3c6400-clock.c	2009-02-27 16:17:15.000000000 +0800
+++ cam/arch/arm/plat-s3c64xx/s3c6400-clock.c	2009-02-27 16:52:50.000000000 +0800
@@ -239,10 +239,11 @@
 
 	rate = clk_round_rate(clk, rate);
 	div = clk_get_rate(clk->parent) / rate;
+	BUG_ON(div > 16);
 
 	val = __raw_readl(reg);
-	val &= ~sclk->mask;
-	val |= (rate - 1) << sclk->shift;
+	val &= ~(0xf << sclk->shift);
+	val |= (div - 1) << sclk->shift;
 	__raw_writel(val, reg);
 
 	return 0;