r1103 - trunk/src/target/u-boot/patches

laforge at sita.openmoko.org laforge at sita.openmoko.org
Sat Feb 24 15:20:43 CET 2007


Author: laforge
Date: 2007-02-24 15:20:43 +0100 (Sat, 24 Feb 2007)
New Revision: 1103

Modified:
   trunk/src/target/u-boot/patches/series
   trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch
Log:
* we always have to configure UPLLCON when reconfiguring MPLLCON (!)
* re-enable uboot-neo1973-resume.patch


Modified: trunk/src/target/u-boot/patches/series
===================================================================
--- trunk/src/target/u-boot/patches/series	2007-02-24 13:47:14 UTC (rev 1102)
+++ trunk/src/target/u-boot/patches/series	2007-02-24 14:20:43 UTC (rev 1103)
@@ -25,7 +25,7 @@
 #boot-from-ram-reloc.patch
 #boot-from-ram-and-nand.patch
 wakeup-reason-nand-only.patch
-#uboot-neo1973-resume.patch
+uboot-neo1973-resume.patch
 
 uboot-arm920t-gd_in_irq.patch
 

Modified: trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch	2007-02-24 13:47:14 UTC (rev 1102)
+++ trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch	2007-02-24 14:20:43 UTC (rev 1103)
@@ -4,9 +4,9 @@
 
 Index: u-boot/cpu/arm920t/start.S
 ===================================================================
---- u-boot.orig/cpu/arm920t/start.S
-+++ u-boot/cpu/arm920t/start.S
-@@ -158,18 +158,52 @@ reset:
+--- u-boot.orig/cpu/arm920t/start.S	2007-02-24 15:14:00.000000000 +0100
++++ u-boot/cpu/arm920t/start.S	2007-02-24 15:17:47.000000000 +0100
+@@ -156,11 +156,37 @@
  	str	r1, [r0]
  # endif
  
@@ -14,6 +14,7 @@
 +#define LOCKTIME	0x4c000000
 +#define MPLLCON		0x4c000004
 +#define MPLLCFG		((0x90 << 12) + (0x2 << 4) + 0x2)
++#define UPLLCFG		((0x78 << 12) + (0x2 << 4) + 0x3)
 +	ldr	r0, =LOCKTIME
 +	mov	r1, #0xffffff
 +	str	r1, [r0]
@@ -22,6 +23,9 @@
 +	ldr	r1, =MPLLCFG
 +	str	r1, [r0]
 +
++	ldr	r1, =UPLLCFG
++	str	r1, [r0, #4]	/* UPLLCON */
++
  	/* FCLK:HCLK:PCLK = 1:2:4 */
 -	/* default FCLK is 120 MHz ! */
  	ldr	r0, =CLKDIVN
@@ -40,17 +44,18 @@
 +	bpl	1b
  #endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
  
+ 	/*
+@@ -169,7 +195,19 @@
+ 	 */
  #ifndef CONFIG_SKIP_LOWLEVEL_INIT
- #ifndef CONFIG_LL_INIT_NAND_ONLY
  	bl	cpu_init_crit
- #endif
 -#endif
 +#if defined(CONFIG_S3C2410)
 +	/* ensure some refresh has happened */
 +	mov	r1, #4096
 +1:	subs	r1, r1, #1
 +	bpl	1b
-+	
++
 +	/* test for resume */
 +	ldr	r1, =0x560000B4		/* gstatus2 */
 +	ldr	r0, [ r1 ]
@@ -60,5 +65,4 @@
 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  
  #ifndef CONFIG_SKIP_RELOCATE_UBOOT
- 	adr	r0, _start		/* r0 <- current position of code   */
-
+ #ifndef CONFIG_S3C2410_NAND_BOOT





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