r1165 - trunk/src/target/u-boot/patches
laforge at sita.openmoko.org
laforge at sita.openmoko.org
Thu Mar 1 02:45:45 CET 2007
Author: laforge
Date: 2007-03-01 02:45:44 +0100 (Thu, 01 Mar 2007)
New Revision: 1165
Modified:
trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch
Log:
* re-order start.S to make sure resume gets handled in the correct order
* increase timeout waiting for refresh (the current one is very high, but
works reliably. this can receive some tuning
* first init UPLL then MPLL, not the other way around
* introduce 7 nop delay between UPLL and MPLL init
* initialize UART at the very beginning, this makes it easier for resume debugging
Modified: trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch 2007-02-28 15:28:25 UTC (rev 1164)
+++ trunk/src/target/u-boot/patches/uboot-neo1973-resume.patch 2007-03-01 01:45:44 UTC (rev 1165)
@@ -4,34 +4,83 @@
Index: u-boot/cpu/arm920t/start.S
===================================================================
---- u-boot.orig/cpu/arm920t/start.S
-+++ u-boot/cpu/arm920t/start.S
-@@ -156,18 +156,56 @@ reset:
+--- u-boot.orig/cpu/arm920t/start.S 2007-02-28 03:51:24.000000000 +0100
++++ u-boot/cpu/arm920t/start.S 2007-03-01 02:43:47.000000000 +0100
+@@ -158,18 +158,68 @@
str r1, [r0]
# endif
+ /* default FCLK is 202 MHz ! */
+#define LOCKTIME 0x4c000000
-+#define MPLLCON 0x4c000004
-+#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2)
++#define UPLLCON 0x4c000008
++//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2)
++#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0)
+#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3)
+ ldr r0, =LOCKTIME
+ mov r1, #0xffffff
+ str r1, [r0]
+
-+ ldr r0, =MPLLCON
-+ ldr r1, =MPLLCFG
++ ldr r0, =UPLLCON
++ ldr r1, =UPLLCFG
+ str r1, [r0]
+
-+ ldr r1, =UPLLCFG
-+ str r1, [r0, #4] /* UPLLCON */
++ /* Page 7-19, seven nops between UPLL and MPLL */
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
+
++ ldr r1, =MPLLCFG
++ str r1, [r0, #-4] /* MPLLCON */
++
/* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
+
++#if 1
++ /* enable uart */
++ ldr r0, =0x4c00000c /* clkcon */
++ ldr r1, =0x7fff0 /* all clocks on */
++ str r1, [r0]
++
++ /* gpio UART0 init */
++ ldr r0, =0x56000070
++ mov r1, #0xaa
++ str r1, [r0]
++
++ /* init uart */
++ ldr r0, =0x50000000
++ mov r1, #0x03
++ str r1, [r0]
++ ldr r1, =0x245
++ str r1, [r0, #0x04]
++ mov r1, #0x01
++ str r1, [r0, #0x08]
++ mov r1, #0x00
++ str r1, [r0, #0x0c]
++ mov r1, #0x1a
++ str r1, [r0, #0x28]
++#endif
++
+ #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
+
+ #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ #ifndef CONFIG_LL_INIT_NAND_ONLY
+ bl cpu_init_crit
+ #endif
+-#endif
+
+ #ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ adr r0, _start /* r0 <- current position of code */
+@@ -202,9 +252,33 @@
+
+ #ifdef CONFIG_S3C2410_NAND_BOOT
+ nand_load:
+ /* take sdram out of power down */
+ ldr r0, =0x56000080 /* misccr */
+ ldr r1, [ r0 ]
@@ -42,16 +91,13 @@
+ mov r1, #128
+1: subs r1, r1, #1
+ bpl 1b
- #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
-
- #ifndef CONFIG_SKIP_LOWLEVEL_INIT
- #ifndef CONFIG_LL_INIT_NAND_ONLY
++
+ #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
bl cpu_init_crit
#endif
--#endif
+#if defined(CONFIG_S3C2410)
+ /* ensure some refresh has happened */
-+ mov r1, #4096
++ ldr r1, =0xfffff
+1: subs r1, r1, #1
+ bpl 1b
+
@@ -63,5 +109,5 @@
+#endif /* CONFIG_S3C2410 */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
- #ifndef CONFIG_SKIP_RELOCATE_UBOOT
- adr r0, _start /* r0 <- current position of code */
+ /* mov r10, lr */
+
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