r1925 - trunk/src/target/u-boot/patches
laforge at sita.openmoko.org
laforge at sita.openmoko.org
Tue May 8 05:21:38 CEST 2007
Author: laforge
Date: 2007-05-08 05:21:28 +0200 (Tue, 08 May 2007)
New Revision: 1925
Added:
trunk/src/target/u-boot/patches/uboot-gta02.patch
trunk/src/target/u-boot/patches/uboot-s3c2443.patch
trunk/src/target/u-boot/patches/uboot-smdk2443.patch
Modified:
trunk/src/target/u-boot/patches/series
Log:
add unfinished code for
* GTA02v1 support
* S3C2443 support
* SMDK2443 support
Modified: trunk/src/target/u-boot/patches/series
===================================================================
--- trunk/src/target/u-boot/patches/series 2007-05-07 23:11:17 UTC (rev 1924)
+++ trunk/src/target/u-boot/patches/series 2007-05-08 03:21:28 UTC (rev 1925)
@@ -68,3 +68,7 @@
uboot-hxd8.patch
uboot-license.patch
+
+uboot-gta02.patch
+uboot-s3c2443.patch
+uboot-smdk2443.patch
Added: trunk/src/target/u-boot/patches/uboot-gta02.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-gta02.patch 2007-05-07 23:11:17 UTC (rev 1924)
+++ trunk/src/target/u-boot/patches/uboot-gta02.patch 2007-05-08 03:21:28 UTC (rev 1925)
@@ -0,0 +1,1177 @@
+Add support for new GTA02 version of Neo1973
+
+Index: u-boot/Makefile
+===================================================================
+--- u-boot.orig/Makefile
++++ u-boot/Makefile
+@@ -1988,6 +1988,10 @@
+ sbc2410x_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
+
++gta02_config \
++gta02v1_config : unconfig
++ @sh board/neo1973/gta02/split_by_variant.sh $@
++
+ gta01_config \
+ gta01v3_config \
+ gta01bv2_config \
+Index: u-boot/board/neo1973/gta02/Makefile
+===================================================================
+--- /dev/null
++++ u-boot/board/neo1973/gta02/Makefile
+@@ -0,0 +1,64 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := gta02.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o
++SOBJS := ../common/lowlevel_init.o
++
++.PHONY: all
++
++all: $(LIB) lowevel_foo.bin
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS) $(SOBJS)
++
++lowlevel_foo.o: ../common/lowlevel_foo.S
++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
++ -o lowlevel_foo.o ../common/lowlevel_foo.S
++
++lowlevel_foo: lowlevel_foo.o ../common/lowlevel_init.o ../common/lowlevel_foo.lds
++ $(LD) -T ../common/lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
++ ../common/lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
++
++lowevel_foo.bin: lowlevel_foo
++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
++ lowlevel_foo lowlevel_foo.bin
++
++
++clean:
++ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+Index: u-boot/board/neo1973/gta02/gta02.c
+===================================================================
+--- /dev/null
++++ u-boot/board/neo1973/gta02/gta02.c
+@@ -0,0 +1,301 @@
++/*
++ * (C) 2006-2007 by OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * based on existing S3C2410 startup code in u-boot:
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger at sysgo.de>
++ *
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <s3c2440.h>
++#include <i2c.h>
++
++#include "../common/neo1973.h"
++#include "../common/jbt6k74.h"
++
++#include "pcf50633.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/* That many seconds the power key needs to be pressed to power up */
++#define POWER_KEY_SECONDS 2
++
++#define M_MDIV 0x6e /* Fout = 399.65MHz */
++#define M_PDIV 0x3
++#define M_SDIV 0x1
++
++#define U_M_MDIV 0x3c
++#define U_M_PDIV 0x4
++#define U_M_SDIV 0x2
++
++unsigned int neo1973_wakeup_cause;
++extern int nobootdelay;
++
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ /* to reduce PLL lock time, adjust the LOCKTIME register */
++ clk_power->LOCKTIME = 0xFFFFFF;
++
++ /* configure MPLL */
++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (4000);
++
++ /* configure UPLL */
++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (8000);
++
++ /* set up the I/O ports */
++#if defined(CONFIG_ARCH_GTA02_v1)
++ gpio->GPACON = 0x007E1FFF;
++
++ gpio->GPBCON = 0x001555AA;
++ gpio->GPBUP = 0x000007FF;
++
++ gpio->GPCCON = 0x55551155;
++ gpio->GPCUP = 0x0000FFFF;
++
++ gpio->GPDCON = 0x55555555;
++ gpio->GPDUP = 0x0000FFFF;
++
++ gpio->GPECON = 0xAAAAAAAA;
++ gpio->GPEUP = 0x0000FFFF;
++
++ gpio->GPFCON = 0x0000AAAA;
++ gpio->GPFUP = 0x000000FF;
++
++ gpio->GPGCON = 0x013DFDFA;
++ gpio->GPGUP = 0x0000FFFF;
++
++ gpio->GPHCON = 0x0028AAAA;
++ gpio->GPHUP = 0x000007FF;
++
++ gpio->GPJCON = 0x1545541;
++#else
++#error Please define GTA02 version
++#endif
++
++ /* arch number of SMDK2410-Board */
++ gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA02;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0x30000100;
++
++ icache_enable();
++ dcache_enable();
++
++ return 0;
++}
++
++int board_late_init(void)
++{
++ extern unsigned char booted_from_nand;
++ unsigned char tmp;
++ char buf[32];
++ int menu_vote = 0; /* <= 0: no, > 0: yes */
++ int seconds = 0;
++
++ /* Initialize the Power Management Unit with a safe register set */
++ pcf50633_init();
++#if 0
++ /* if there's no other reason, must be regular reset */
++ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET;
++
++ if (!booted_from_nand)
++ goto woken_by_reset;
++
++ /* obtain wake-up reason, save INT1 in environment */
++ tmp = pcf50606_reg_read(PCF50606_REG_INT1);
++ sprintf(buf, "0x%02x", tmp);
++ setenv("pcf50606_int1", buf);
++
++ if (tmp & PCF50606_INT1_ALARM) {
++ /* we've been woken up by RTC alarm, boot */
++ neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM;
++ goto continue_boot;
++ }
++ if (tmp & PCF50606_INT1_EXTONR) {
++ /* we've been woken up by charger insert */
++ neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER;
++ }
++
++ if (tmp & PCF50606_INT1_ONKEYF) {
++ /* we've been woken up by a falling edge of the onkey */
++ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY;
++ }
++
++ if (neo1973_wakeup_cause == NEO1973_WAKEUP_CHARGER) {
++ /* if we still think it was only a charger insert, boot */
++ goto continue_boot;
++ }
++
++woken_by_reset:
++
++ while (neo1973_wakeup_cause == NEO1973_WAKEUP_RESET ||
++ neo1973_on_key_pressed()) {
++ if (neo1973_aux_key_pressed())
++ menu_vote++;
++ else
++ menu_vote--;
++
++ if (neo1973_new_second())
++ seconds++;
++ if (seconds >= POWER_KEY_SECONDS)
++ goto continue_boot;
++ }
++ /* Power off if minimum number of seconds not reached */
++ neo1973_poweroff();
++
++continue_boot:
++#endif
++ jbt6k74_init();
++ jbt6k74_enter_state(JBT_STATE_NORMAL);
++ jbt6k74_display_onoff(1);
++
++ /* issue a short pulse with the vibrator */
++ neo1973_vibrator(1);
++ udelay(50000);
++ neo1973_vibrator(0);
++
++ /* switch on the backlight */
++ neo1973_backlight(1);
++
++#if 0
++ {
++ /* check if sd card is inserted, and power-up if it is */
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++ if (!(gpio->GPFDAT & (1 << 5)))
++ gpio->GPBDAT &= ~(1 << 2);
++ }
++
++ if (menu_vote > 0) {
++ bootmenu();
++ nobootdelay = 1;
++ }
++#endif
++
++ return 0;
++}
++
++int dram_init (void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++u_int32_t get_board_rev(void)
++{
++#if defined(CONFIG_ARCH_GTA02_v1)
++ return 0x00000310;
++#endif
++}
++
++void neo1973_poweroff(void)
++{
++ printf("poweroff\n");
++ udc_disconnect();
++ pcf50633_reg_write(PCF50633_REG_OOCSHDWN, 0x01);
++ /* don't return to caller */
++ while (1) ;
++}
++
++void neo1973_backlight(int on)
++{
++ /* FIXME: PMU based implementation */
++}
++
++/* FIXME: shared */
++void neo1973_vibrator(int on)
++{
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++ if (on)
++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
++ gpio->GPGDAT |= (1 << 11); /* GPG11 */
++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
++ gpio->GPBDAT |= (1 << 10); /* GPB10 */
++#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1)
++ gpio->GPBDAT |= (1 << 3); /* GPB3 */
++#endif
++ else
++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
++ gpio->GPGDAT &= ~(1 << 11); /* GPG11 */
++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
++ gpio->GPBDAT &= ~(1 << 10); /* GPB10 */
++#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1)
++ gpio->GPBDAT &= ~(1 << 3); /* GPB3 */
++#endif
++}
++
++int neo1973_new_second(void)
++{
++ return pcf50633_reg_read(PCF50633_REG_INT1) & PCF50633_INT1_SECOND;
++}
++
++int neo1973_on_key_pressed(void)
++{
++ return !(pcf50606_reg_read(PCF50633_REG_OOCSTAT)
++ & PFC50633_OOCSTAT_ONKEY);
++}
++
++/* FIXME: shared */
++int neo1973_aux_key_pressed(void)
++{
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++ if (gpio->GPFDAT & (1 << 6))
++ return 0;
++ return 1;
++}
++
++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
++ images: 640*480*2*2 = 1228800 < 1245184. */
++
++unsigned int dynpart_size[] = {
++ CFG_UBOOT_SIZE, 0x4000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 };
++char *dynpart_names[] = {
++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
++
++
+Index: u-boot/board/neo1973/gta02/u-boot.lds
+===================================================================
+--- /dev/null
++++ u-boot/board/neo1973/gta02/u-boot.lds
+@@ -0,0 +1,58 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm920t/start.o (.text)
++ cpu/arm920t/s3c24x0/nand_read.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+Index: u-boot/include/configs/neo1973_gta02.h
+===================================================================
+--- /dev/null
++++ u-boot/include/configs/neo1973_gta02.h
+@@ -0,0 +1,274 @@
++/*
++ * (C) Copyright 2007 OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * Configuation settings for the FIC Neo1973 GTA02 Linux GSM phone
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* we want to be able to start u-boot directly from within NAND flash */
++#define CONFIG_LL_INIT_NAND_ONLY
++#define CONFIG_S3C2410_NAND_BOOT 1
++#define CONFIG_S3C2410_NAND_SKIP_BAD 1
++
++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC */
++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */
++
++/* input clock of PLL */
++#define CONFIG_SYS_CLK_FREQ 16934400/* the GTA02 has this input clock */
++
++
++#define USE_920T_MMU 1
++#define CONFIG_USE_IRQ 1
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024)
++ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/*
++ * Hardware drivers
++ */
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL3 1 /* we use SERIAL 1 on GTA01 */
++
++/************************************************************
++ * RTC
++ ************************************************************/
++#define CONFIG_RTC_S3C24X0 1
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++#define CONFIG_COMMANDS (\
++ CFG_CMD_BDI | \
++ CFG_CMD_LOADS | \
++ CFG_CMD_LAODB | \
++ CFG_CMD_IMI | \
++ CFG_CMD_CACHE | \
++ CFG_CMD_MEMORY | \
++ CFG_CMD_ENV | \
++ /* CFG_CMD_IRQ | */ \
++ CFG_CMD_BOOTD | \
++ CFG_CMD_CONSOLE | \
++ CFG_CMD_BMP | \
++ CFG_CMD_ASKENV | \
++ CFG_CMD_RUN | \
++ CFG_CMD_ECHO | \
++ CFG_CMD_I2C | \
++ CFG_CMD_REGINFO | \
++ CFG_CMD_IMMAP | \
++ CFG_CMD_DATE | \
++ CFG_CMD_AUTOSCRIPT | \
++ CFG_CMD_BSP | \
++ CFG_CMD_ELF | \
++ CFG_CMD_MISC | \
++ /* CFG_CMD_USB | */ \
++ CFG_CMD_JFFS2 | \
++ CFG_CMD_DIAG | \
++ /* CFG_CMD_HWFLOW | */ \
++ CFG_CMD_SAVES | \
++ CFG_CMD_NAND | \
++ CFG_CMD_PORTIO | \
++ CFG_CMD_MMC | \
++ CFG_CMD_FAT | \
++ CFG_CMD_EXT2 | \
++ 0)
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTARGS ""
++#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
++
++#define CONFIG_DOS_PARTITION 1
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
++/* what's this ? it's not used anywhere */
++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#if defined(CONFIG_ARCH_GTA02_v1)
++#define CFG_PROMPT "GTA02v1 # " /* Monitor Command Prompt */
++#endif
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 64 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0x33000000 /* default load address */
++
++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
++/* it to wrap 100 times (total 1562500) to get 1 sec. */
++#define CFG_HZ 1562500
++
++/* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++#if 0
++#define CONFIG_USB_OHCI 1
++#endif
++
++#define CONFIG_USB_DEVICE 1
++#define CONFIG_USB_TTY 1
++#define CFG_CONSOLE_IS_IN_ENV 1
++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc"
++#define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION
++#define CONFIG_USBD_DFU 1
++#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
++#define CONFIG_USBD_DFU_INTERFACE 2
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "usbtty=cdc_acm\0" \
++ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8\0" \
++ ""
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++/* No NOR flash in this device */
++#define CFG_NO_FLASH 1
++
++#define CFG_ENV_IS_IN_NAND 1
++#define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */
++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
++#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
++
++#define NAND_MAX_CHIPS 1
++#define CFG_NAND_BASE 0x4e000000
++#define CFG_MAX_NAND_DEVICE 1
++
++#define CONFIG_MMC 1
++#define CFG_MMC_BASE 0xff000000
++
++/* EXT2 driver */
++#define CONFIG_EXT2 1
++
++#define CONFIG_FAT 1
++#define CONFIG_SUPPORT_VFAT
++
++#if 1
++/* JFFS2 driver */
++#define CONFIG_JFFS2_CMDLINE 1
++#define CONFIG_JFFS2_NAND 1
++#define CONFIG_JFFS2_NAND_DEV 0
++//#define CONFIG_JFFS2_NAND_OFF 0x634000
++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
++#endif
++
++/* ATAG configuration */
++#define CONFIG_INITRD_TAG 1
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_CMDLINE_TAG 1
++#define CONFIG_REVISION_TAG 1
++#if 0
++#define CONFIG_SERIAL_TAG 1
++#endif
++
++#define CONFIG_DRIVER_S3C24X0_I2C 1
++#define CONFIG_HARD_I2C 1
++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50633 data sheet */
++#define CFG_I2C_SLAVE 0x7f
++
++/* we have a board_late_init() function */
++#define BOARD_LATE_INIT 1
++
++#if 0
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_S3C2410
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_SPLASH_SCREEN
++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
++#define CONFIG_VIDEO_BMP_GZIP
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++#define CONFIG_UNZIP
++
++#define VIDEO_KBD_INIT_FCT 0
++#define VIDEO_TSTC_FCT serial_tstc
++#define VIDEO_GETC_FCT serial_getc
++
++#define LCD_VIDEO_ADDR 0x33d00000
++#endif
++
++#define CONFIG_S3C2410_NAND_BBT 1
++#define CONFIG_S3C2410_NAND_HWECC 1
++
++#define CONFIG_DRIVER_PCF50633 1
++
++#define MTDIDS_DEFAULT "nand0=neo1973-nand"
++#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),-(jffs2)"
++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "neo1973-nand"
++#define CONFIG_NAND_DYNPART
++
++#endif /* __CONFIG_H */
+Index: u-boot/board/neo1973/gta02/split_by_variant.sh
+===================================================================
+--- /dev/null
++++ u-boot/board/neo1973/gta02/split_by_variant.sh
+@@ -0,0 +1,31 @@
++#!/bin/sh
++# ---------------------------------------------------------
++# Set the core module defines according to Core Module
++# ---------------------------------------------------------
++# ---------------------------------------------------------
++# Set up the GTA01 type define
++# ---------------------------------------------------------
++
++mkdir -p ${obj}include
++if [ "$1" == "" ]
++then
++ echo "$0:: No parameters - using GTA02Bv1 config"
++ echo "#define CONFIG_ARCH_GTA02_v1" > ${obj}include/config.h
++else
++ case "$1" in
++ gta02v1_config)
++ echo "#define CONFIG_ARCH_GTA02_v1" > ${obj}include/config.h
++ ;;
++
++ *)
++ echo "$0:: Unrecognised config - using GTA02v1 config"
++ echo "#define CONFIG_ARCH_GTA02_v1" > ${obj}include/config.h
++ ;;
++
++ esac
++
++fi
++# ---------------------------------------------------------
++# Complete the configuration
++# ---------------------------------------------------------
++$MKCONFIG -a neo1973_gta02 arm arm920t gta02 neo1973 s3c24x0
+Index: u-boot/include/pcf50633.h
+===================================================================
+--- /dev/null
++++ u-boot/include/pcf50633.h
+@@ -0,0 +1,234 @@
++#ifndef _PCF50633_H
++#define _PCF50633_H
++
++/* Philips PCF50633 Power Managemnt Unit (PMU) driver
++ * (C) 2006-2007 by OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ */
++
++enum pfc50633_regs {
++ PCF50633_REG_VERSION = 0x00,
++ PCF50633_REG_VARIANT = 0x01,
++ PCF50633_REG_INT1 = 0x02, /* Interrupt Status */
++ PCF50633_REG_INT2 = 0x03, /* Interrupt Status */
++ PCF50633_REG_INT3 = 0x04, /* Interrupt Status */
++ PCF50633_REG_INT4 = 0x05, /* Interrupt Status */
++ PCF50633_REG_INT5 = 0x06, /* Interrupt Status */
++ PCF50633_REG_INT1M = 0x07, /* Interrupt Mask */
++ PCF50633_REG_INT2M = 0x08, /* Interrupt Mask */
++ PCF50633_REG_INT3M = 0x09, /* Interrupt Mask */
++ PCF50633_REG_INT4M = 0x0a, /* Interrupt Mask */
++ PCF50633_REG_INT5M = 0x0b, /* Interrupt Mask */
++ PCF50633_REG_OOCSHDWN = 0x0c,
++ PCF50633_REG_OOCWAKE = 0x0d,
++ PCF50633_REG_OOCTIM1 = 0x0e,
++ PCF50633_REG_OOCTIM2 = 0x0f,
++ PCF50633_REG_OOCMODE = 0x10,
++ PCF50633_REG_OOCCTL = 0x11,
++ PCF50633_REG_OOCSTAT = 0x12,
++ PCF50633_REG_GPIOCTL = 0x13,
++ PCF50633_REG_GPIO1CFG = 0x14,
++ PCF50633_REG_GPIO2CFG = 0x15,
++ PCF50633_REG_GPIO3CFG = 0x16,
++ PCF50633_REG_GPOCFG = 0x17,
++ PCF50633_REG_BVMCTL = 0x18,
++ PCF50633_REG_SVMCTL = 0x19,
++ PCF50633_REG_AUTOOUT = 0x1a,
++ PCF50633_REG_AUTOENA = 0x1b,
++ PCF50633_REG_AUTOCTL = 0x1c,
++ PCF50633_REG_AUTOMXC = 0x1d,
++ PCF50633_REG_DOWN1OUT = 0x1e,
++ PCF50633_REG_DOWN1ENA = 0x1f,
++ PCF50633_REG_DOWN1CTL = 0x20,
++ PCF50633_REG_DOWN1MXC = 0x21,
++ PCF50633_REG_DOWN2OUT = 0x22,
++ PCF50633_REG_DOWN2ENA = 0x23,
++ PCF50633_REG_DOWN2CTL = 0x24,
++ PCF50633_REG_DOWN2MXC = 0x25,
++ PCF50633_REG_MEMLDOOUT = 0x26,
++ PCF50633_REG_MEMLDOENA = 0x27,
++ PCF50633_REG_LEDOUT = 0x28,
++ PCF50633_REG_LEDENA = 0x29,
++ PCF50633_REG_LEDCTL = 0x2a,
++ PCF50633_REG_LEDDIM = 0x2b,
++ /* reserved */
++ PCF50633_REG_LDO1OUT = 0x2d,
++ PCF50633_REG_LDO1ENA = 0x2e,
++ PCF50633_REG_LDO2OUT = 0x2f,
++ PCF50633_REG_LDO2ENA = 0x30,
++ PCF50633_REG_LDO3OUT = 0x31,
++ PCF50633_REG_LDO3ENA = 0x32,
++ PCF50633_REG_LDO4OUT = 0x33,
++ PCF50633_REG_LDO4ENA = 0x34,
++ PCF50633_REG_LDO5OUT = 0x35,
++ PCF50633_REG_LDO5ENA = 0x36,
++ PCF50633_REG_LDO6OUT = 0x37,
++ PCF50633_REG_LDO6ENA = 0x38,
++ PCF50633_REG_HCDLDOOUT = 0x39,
++ PCF50633_REG_HCDLDOENA = 0x3a,
++ PCF50633_REG_STBYCTL1 = 0x3b,
++ PCF50633_REG_STBYCTL2 = 0x3c,
++ PCF50633_REG_DEBPF1 = 0x3d,
++ PCF50633_REG_DEBPF2 = 0x3e,
++ PCF50633_REG_DEBPF3 = 0x3f,
++ PCF50633_REG_HCLDOOVL = 0x40,
++ PCF50633_REG_DCDCSTAT = 0x41,
++ PCF50633_REG_LDOSTAT = 0x42,
++ PCF50633_REG_MBCC1 = 0x43,
++ PCF50633_REG_MBCC2 = 0x44,
++ PCF50633_REG_MBCC3 = 0x45,
++ PCF50633_REG_MBCC4 = 0x46,
++ PCF50633_REG_MBCC5 = 0x47,
++ PCF50633_REG_MBCC6 = 0x48,
++ PCF50633_REG_MBCC7 = 0x49,
++ PCF50633_REG_MBCC8 = 0x4a,
++ PCF50633_REG_MBCS1 = 0x4b,
++ PCF50633_REG_MBCS2 = 0x4c,
++ PCF50633_REG_MBCS3 = 0x4d,
++ PCF50633_REG_BBCCTL = 0x4e,
++ PCF50633_REG_ALMGAIN = 0x4f,
++ PCF50633_REG_ALMDATA = 0x50,
++ /* reserved */
++ PCF50633_REG_ADCC3 = 0x52,
++ PCF50633_REG_ADCC2 = 0x53,
++ PCF50633_REG_ADCC1 = 0x54,
++ PCF50633_REG_ADCS1 = 0x55,
++ PCF50633_REG_ADCS2 = 0x56,
++ PCF50633_REG_ADCS3 = 0x57,
++ /* reserved */
++ PCF50633_REG_RTCSC = 0x59, /* Second */
++ PCF50633_REG_RTCMN = 0x5a, /* Minute */
++ PCF50633_REG_RTCHR = 0x5b, /* Hour */
++ PCF50633_REG_RTCWD = 0x5c, /* Weekday */
++ PCF50633_REG_RTCDT = 0x5d, /* Day */
++ PCF50633_REG_RTCMT = 0x5e, /* Month */
++ PCF50633_REG_RTCYR = 0x5f, /* Year */
++ PCF50633_REG_RTCSCA = 0x60, /* Alarm Second */
++ PCF50633_REG_RTCMNA = 0x61, /* Alarm Minute */
++ PCF50633_REG_RTCHRA = 0x62, /* Alarm Hour */
++ PCF50633_REG_RTCWDA = 0x63, /* Alarm Weekday */
++ PCF50633_REG_RTCDTA = 0x64, /* Alarm Day */
++ PCF50633_REG_RTCMTA = 0x65, /* Alarm Month */
++ PCF50633_REG_RTCYRA = 0x66, /* Alarm Year */
++
++ PCF50633_REG_MEMBYTE0 = 0x67,
++ PCF50633_REG_MEMBYTE1 = 0x68,
++ PCF50633_REG_MEMBYTE2 = 0x69,
++ PCF50633_REG_MEMBYTE3 = 0x6a,
++ PCF50633_REG_MEMBYTE4 = 0x6b,
++ PCF50633_REG_MEMBYTE5 = 0x6c,
++ PCF50633_REG_MEMBYTE6 = 0x6d,
++ PCF50633_REG_MEMBYTE7 = 0x6e,
++ /* reserved */
++ PCF50633_REG_DCDCPFM = 0x84,
++ __NUM_PCF50633_REGS
++};
++
++enum pcf50633_reg_int1 {
++ PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
++ PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
++ PCF50633_INT1_USBINS = 0x04, /* USB inserted */
++ PCF50633_INT1_USBREM = 0x08, /* USB removed */
++ /* reserved */
++ PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
++ PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
++};
++
++enum pcf50633_reg_int2 {
++ PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
++ PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
++ PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
++ PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
++ PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
++ PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
++ PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
++ PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
++};
++
++enum pcf50633_reg_int3 {
++ PCF50633_INT3_BATFULL = 0x01, /* Battery full */
++ PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
++ PCF50633_INT3_THLIMON = 0x04,
++ PCF50633_INT3_THLIMOFF = 0x08,
++ PCF50633_INT3_USBLIMON = 0x10,
++ PCF50633_INT3_USBLIMOFF = 0x20,
++ PCF50633_INT3_ADCRDY = 0x40, /* ADC conversion finished */
++ PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
++};
++
++enum pcf50633_reg_int4 {
++ PCF50633_INT4_LOWSYS = 0x01,
++ PCF50633_INT4_LOWBAT = 0x02,
++ PCF50633_INT4_HIGHTMP = 0x04,
++ PCF50633_INT4_AUTOPWRFAIL = 0x08,
++ PCF50633_INT4_DWN1PWRFAIL = 0x10,
++ PCF50633_INT4_DWN2PWRFAIL = 0x20,
++ PCF50633_INT4_LEDPWRFAIL = 0x40,
++ PCF50633_INT4_LEDOVP = 0x80,
++};
++
++enum pcf50633_reg_int5 {
++ PCF50633_INT4_LDO1PWRFAIL = 0x01,
++ PCF50633_INT4_LDO2PWRFAIL = 0x02,
++ PCF50633_INT4_LDO3PWRFAIL = 0x04,
++ PCF50633_INT4_LDO4PWRFAIL = 0x08,
++ PCF50633_INT4_LDO5PWRFAIL = 0x10,
++ PCF50633_INT4_LDO6PWRFAIL = 0x20,
++ PCF50633_INT4_HCLDOPWRFAIL = 0x40,
++ PCF50633_INT4_HCLDOOVL = 0x80,
++};
++
++enum pcf50633_reg_oocwake {
++ PCF50633_OOCWAKE_ONKEY = 0x01,
++ PCF50633_OOCWAKE_EXTON1 = 0x02,
++ PCF50633_OOCWAKE_EXTON2 = 0x04,
++ PCF50633_OOCWAKE_EXTON3 = 0x08,
++ PCF50633_OOCWAKE_RTC = 0x10,
++ /* reserved */
++ PCF50633_OOCWAKE_USB = 0x40,
++ PCF50633_OOCWAKE_ADP = 0x80,
++};
++
++enum pcf50633_reg_mbcc1 {
++ PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
++ PCF50633_MBCC1_AUTOSTOP = 0x02,
++ PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
++ PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
++ PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
++ PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
++ PCF50633_MBCC1_WDTIME_1H = 0x00,
++ PCF50633_MBCC1_WDTIME_2H = 0x40,
++ PCF50633_MBCC1_WDTIME_4H = 0x80,
++ PCF50633_MBCC1_WDTIME_6H = 0xc0,
++};
++#define PCF50633_MBCC1_WDTIME_MASK 0xc0
++
++enum pcf50633_reg_mbcc2 {
++ PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
++ PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
++ PCF50633_MBCC2_VBATCOND_3V = 0x02,
++ PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
++ PCF50633_MBCC2_VMAX_4V = 0x00,
++ PCF50633_MBCC2_VMAX_4V20 = 0x28,
++ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
++};
++#define PCF50633_MBCC2_VBATCOND_MASK 0x03
++#define PCF50633_MBCC2_VMAX_MASK 0x3c
++
++
++/* this is to be provided by the board implementation */
++extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
++
++void pcf50633_reg_write(u_int8_t reg, u_int8_t val);
++
++u_int8_t pcf50633_reg_read(u_int8_t reg);
++
++void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val);
++void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits);
++
++void pcf50633_init(void);
++void pcf50633_charge_autofast(int on);
++
++#endif /* _PCF50606_H */
++
+Index: u-boot/drivers/pcf50633.c
+===================================================================
+--- /dev/null
++++ u-boot/drivers/pcf50633.c
+@@ -0,0 +1,81 @@
++#include <common.h>
++
++#ifdef CONFIG_DRIVER_PCF50633
++
++#include <i2c.h>
++#include <pcf50633.h>
++#include <asm/atomic.h>
++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
++
++#define PCF50633_I2C_ADDR 0x73
++
++void __pcf50633_reg_write(u_int8_t reg, u_int8_t val)
++{
++ i2c_write(PCF50633_I2C_ADDR, reg, 1, &val, 1);
++}
++
++u_int8_t __pcf50633_reg_read(u_int8_t reg)
++{
++ u_int8_t tmp;
++ i2c_read(PCF50633_I2C_ADDR, reg, 1, &tmp, 1);
++ return tmp;
++}
++
++void pcf50633_reg_write(u_int8_t reg, u_int8_t val)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++ __pcf50633_reg_write(reg, val);
++ local_irq_restore(flags);
++}
++
++u_int8_t pcf50633_reg_read(u_int8_t reg)
++{
++ unsigned long flags;
++ u_int8_t tmp;
++
++ local_irq_save(flags);
++ tmp = __pcf50633_reg_read(reg);
++ local_irq_restore(flags);
++
++ return tmp;
++}
++
++void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val)
++{
++ unsigned long flags;
++ u_int8_t tmp;
++
++ local_irq_save(flags);
++ tmp = __pcf50633_reg_read(reg);
++ __pcf50633_reg_write(reg, (val & mask) | (tmp & ~mask));
++ local_irq_restore(flags);
++}
++
++void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits)
++{
++ unsigned long flags;
++ u_int8_t tmp;
++
++ local_irq_save(flags);
++ tmp = pcf50633_reg_read(reg);
++ pcf50633_reg_write(reg, (tmp & ~bits));
++ local_irq_restore(flags);
++}
++
++/* initialize PCF50633 register set */
++void pcf50633_init(void)
++{
++ unsigned long flags;
++ int i;
++
++ local_irq_save(flags);
++ for (i = 0; i < ARRAY_SIZE(regs_valid); i++) {
++ __pcf50633_reg_write(regs_valid[i],
++ pcf50633_initial_regs[regs_valid[i]]);
++ }
++ local_irq_restore(flags);
++}
++
++#endif /* CONFIG DRIVER_PCF50633 */
+Index: u-boot/board/neo1973/common/lowlevel_init.S
+===================================================================
+--- u-boot.orig/board/neo1973/common/lowlevel_init.S
++++ u-boot/board/neo1973/common/lowlevel_init.S
+@@ -167,6 +167,18 @@
+ str r1, [r0]
+ #endif
+
++#if defined(CONFIG_ARCH_GTA02_v1)
++ /* enable KEEPACT to make sure PMU keeps us alive */
++ ldr r0, =0x56000000 /* GPJ base */
++ ldr r1, [r0, #0xd0] /* GPJCON */
++ orr r1, r1, #(1 << 6)
++ str r1, [r0, #0xd0]
++
++ ldr r1, [r0, #0xd4] /* GPJDAT */
++ orr r1, r1, #(1 << 3)
++ str r1, [r0, #0xd4]
++#endif
++
+ /* everything is fine now */
+ mov pc, lr
+
+Index: u-boot/board/neo1973/gta02/pcf50633.c
+===================================================================
+--- /dev/null
++++ u-boot/board/neo1973/gta02/pcf50633.c
+@@ -0,0 +1,54 @@
++
++#include <common.h>
++#include <pcf50633.h>
++
++/* initial register set for PCF50633 in Neo1973 GTA02 devices */
++const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS] = {
++ /* gap */
++ [PCF50633_REG_INT1M] = PCF50606_INT1_SECOND,
++ [PCF50633_REG_INT2M] = 0x00,
++ [PCF50633_REG_INT3M] = PCF50606_INT3_TSCPRES,
++ [PCF50633_REG_INT4M] = PCF50606_INT3_TSCPRES,
++ [PCF50633_REG_INT5M] = PCF50606_INT3_TSCPRES,
++
++ [PCF50633_REG_AUTOOUT] = 0x6b, /* 3.300V */
++ [PCF50633_REG_AUTOENA] = 0x01, /* always on */
++ [PCF50633_REG_AUTOCTL] = 0x00, /* automatic up/down operation */
++ [PCF50633_REG_AUTOMXC] = 0x0a, /* 400mA at startup FIXME */
++
++ [PCF50633_REG_DOWN1OUT] = 0x1b, /* 1.3V (0x1b * .025V + 0.625V) */
++ [PCF50633_REG_DOWN1ENA] = 0x02, /* enabled if GPIO1 = HIGH */
++ [PCF50633_REG_DOWN1CTL] = 0x00, /* no DVM */
++ [PCF50633_REG_DOWN1MXC] = 0x22, /* limit to 510mA at startup */
++
++ [PCF50633_REG_DOWN2OUT] = 0x2f, /* 1.8V (0x2f * .025V + 0.625V) */
++ [PCF50633_REG_DOWN2ENA] = 0x02, /* enabled if GPIO1 = HIGH */
++ [PCF50633_REG_DOWN2CTL] = 0x00, /* no DVM */
++ [PCF50633_REG_DOWN2MXC] = 0x22, /* limit to 510mA at startup */
++
++ [PCF50633_REG_MEMLDOOUT] = 0x00,
++ [PCF50633_REG_MEMLDOENA] = 0x00,
++
++ [PCF50633_REG_LEDOUT] = 0x2f, /* full backlight power */
++ [PCF50633_REG_LEDENA] = 0x02, /* enabled if GPIO1 = HIGH */
++ [PCF50633_REG_LEDCTL] = 0x05, /* ovp enabled, ocp 500mA */
++ [PCF50633_REG_LEDDIM] = 0x20, /* dimming curve */
++
++ [PCF50633_REG_LDO1OUT] = 0x04, /* 1.3V (4 * 0.1V + 0.9V) */
++ [PCF50633_REG_LDO1ENA] = 0x01, /* always on */
++
++ [PCF50633_REG_LDO2OUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */
++ [PCF50633_REG_LDO2ENA] = 0x02, /* enabled if GPIO1 = HIGH */
++
++ [PCF50633_REG_LDO3OUT] = 0x15, /* 3.0V (21 * 0.1V + 0.9V) */
++ [PCF50633_REG_LDO3ENA] = 0x02, /* enabled if GPIO1 = HIGH */
++
++ [PCF50633_REG_LDO4ENA] = 0x00,
++ [PCF50633_REG_LDO5ENA] = 0x00,
++ [PCF50633_REG_LDO6ENA] = 0x00,
++
++ [PCF50633_REG_HCLDOOUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */
++ [PCF50633_REG_HCLDOENA] = 0x00, /* off by default*/
++
++ /* FIXME */
++};
Added: trunk/src/target/u-boot/patches/uboot-s3c2443.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-05-07 23:11:17 UTC (rev 1924)
+++ trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-05-08 03:21:28 UTC (rev 1925)
@@ -0,0 +1,256 @@
+Index: u-boot/cpu/arm920t/start.S
+===================================================================
+--- u-boot.orig/cpu/arm920t/start.S
++++ u-boot/cpu/arm920t/start.S
+@@ -35,6 +35,8 @@
+ #include <s3c2410.h>
+ #elif defined(CONFIG_S3C2440)
+ #include <s3c2440.h>
++#elif defined(CONFIG_S3C2443)
++#include <s3c2443.h>
+ #endif
+
+
+@@ -164,9 +166,15 @@
+ # define UPLLCON_val ((0x3c << 12) + (0x4 << 4) + 0x2)
+ # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
+ # define CAMDIVN 0x4C000018
++#elif defined(CONFIG_S3C2443)
++# define INTSUBMSK_val 0x1fffffff
++# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */
++# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */
++# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
+ #endif
+
+-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443)
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+@@ -177,7 +185,7 @@
+ mov r1, #0xffffffff
+ ldr r0, =INTMSK
+ str r1, [r0]
+-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443)
+ ldr r1, =INTSUBMSK_val
+ ldr r0, =INTSUBMSK
+ str r1, [r0]
+@@ -196,6 +204,43 @@
+ mcr p15, 0, r1, c1, c0, 0
+
+
++#if defined(CONFIG_S3C2443)
++#define LOCKCON0 0x4c000000
++#define LOCKCON1 0x4c000004
++#define MPLLCON 0x4c000010
++#define EPLLCON 0x4c000018
++
++ ldr r0, =CLKDIV0
++ ldr r1, =CLKDIV0_val
++ str r1, [r0]
++
++ /* set safe (way too long) locktime for both PLLs */
++ ldr r0, =LOCKCON0
++ mov r1, #0xffffff
++ str r1, [r0]
++ ldr r0, =LOCKCON1
++ str r1, [r0]
++
++ /* configure MPLL */
++ ldr r0, =MPLLCON
++ ldr r1, =MPLLCON_val
++ str r1, [r0]
++
++ /* select MPLL clock out for SYSCLK */
++ ldr r0, =CLKSRC
++ ldr r1, [r0]
++ orr r1, r1, #0x10
++ str r1, [r0]
++
++#if 0
++ /* configure EPLL */
++ ldr r0, =EPLLCON
++ ldr r1, =EPLLCON_val
++ str r1, [r0]
++#endif
++
++
++#else /* i.e. 2440, 2410 and 2440 */
+ #define LOCKTIME 0x4c000000
+ #define UPLLCON 0x4c000008
+
+@@ -223,6 +268,7 @@
+ ldr r0, =CLKDIVN
+ mov r1, #CLKDIVN_val
+ str r1, [r0]
++#endif
+
+ #if 1
+ /* enable uart */
+@@ -249,7 +295,7 @@
+ str r1, [r0, #0x28]
+ #endif
+
+-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
++#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2443 */
+
+ #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ #ifndef CONFIG_LL_INIT_NAND_ONLY
+Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
+@@ -31,7 +31,8 @@
+
+ #include <common.h>
+ #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) || \
++ defined (CONFIG_TRAB)
+
+ #include <arm920t.h>
+ #if defined(CONFIG_S3C2400)
+@@ -40,6 +41,8 @@
+ #include <s3c2410.h>
+ #elif defined(CONFIG_S3C2440)
+ #include <s3c2440.h>
++#elif defined(CONFIG_S3C2443)
++#include <s3c2443.h>
+ #endif
+
+ int timer_load_val = 0;
+@@ -186,6 +189,7 @@
+ #elif defined(CONFIG_SBC2410X) || \
+ defined(CONFIG_SMDK2410) || \
+ defined(CONFIG_SMDK2440) || \
++ defined(CONFIG_SMDK2443) || \
+ defined(CONFIG_VCMA9)
+ tbclk = CFG_HZ;
+ #else
+Index: u-boot/drivers/usbdcore_s3c2410.c
+===================================================================
+--- u-boot.orig/drivers/usbdcore_s3c2410.c
++++ u-boot/drivers/usbdcore_s3c2410.c
+@@ -24,7 +24,8 @@
+
+ #include <config.h>
+
+-#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE)
++#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2443)) && defined(CONFIG_USB_DEVICE)
+
+ #include <common.h>
+
+Index: u-boot/include/s3c2443.h
+===================================================================
+--- /dev/null
++++ u-boot/include/s3c2443.h
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2007 OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __S3C2443_H
++#define __S3C2443_H
++
++#include <s3c24x0.h>
++
++/* CLOCK & POWER MANAGEMENT (see S3C2443 manual chapter 2) */
++typedef struct {
++ S3C24X0_REG32 LOCKCON0;
++ S3C24X0_REG32 LOCKCON1;
++ S3C24X0_REG32 OSCSET;
++ S3C24X0_REG32 res1;
++ S3C24X0_REG32 MPLLCON;
++ S3C24X0_REG32 res2;
++ S3C24X0_REG32 EPLLCON;
++ S3C24X0_REG32 res3;
++ S3C24X0_REG32 CLKSRC;
++ S3C24X0_REG32 CLKDIV0;
++ S3C24X0_REG32 CLKDIV1;
++ S3C24X0_REG32 res4;
++ S3C24X0_REG32 HCLKCON;
++ S3C24X0_REG32 PCLKCON;
++ S3C24X0_REG32 SCLKCON;
++ S3C24X0_REG32 res5;
++ S3C24X0_REG32 PWRMODE;
++ S3C24X0_REG32 SWRST;
++ S3C24X0_REG32 res6[2];
++ S3C24X0_REG32 BUSPRI0;
++ S3C24X0_REG32 res7[3];
++} /*__attribute__((__packed__))*/ S3C2443_CLOCK_POWER;
++
++/* NAND FLASH (see S3C2443 manual chapter 7) */
++typedef struct {
++ S3C24X0_REG32 NFCONF;
++ S3C24X0_REG32 NFCONT;
++ S3C24X0_REG32 NFCMD;
++ S3C24X0_REG32 NFADDR;
++ S3C24X0_REG32 NFDATA;
++ S3C24X0_REG32 NFMECCD0;
++ S3C24X0_REG32 NFMECCD1;
++ S3C24X0_REG32 NFSECCD;
++ S3C24X0_REG32 NFSBLK;
++ S3C24X0_REG32 NFEBLK;
++ S3C24X0_REG32 NFSTAT;
++ S3C24X0_REG32 NFECCERR0;
++ S3C24X0_REG32 NFECCERR1;
++ S3C24X0_REG32 NFMECC0;
++ S3C24X0_REG32 NFMECC1;
++ S3C24X0_REG32 NFSECC;
++ S3C24X0_REG32 NFMLCBITPT;
++} /*__attribute__((__packed__))*/ S3C2443_NAND;
++
++/* STATIC MEMORY (see S3C2443 manual chapter 5) */
++struct s3c2443_sm_bank {
++ S3C24X0_REG32 SMBIDCYR;
++ S3C24X0_REG32 SMBWSTRDR;
++ S3C24X0_REG32 SMBWSTWRR;
++ S3C24X0_REG32 SMBWSTOENR;
++ S3C24X0_REG32 SMBWSTWENR;
++ S3C24X0_REG32 SMBCR;
++ S3C24X0_REG32 SMBSR;
++ S3C24X0_REG32 SMBWSTBRDR;
++};
++
++typedef struct {
++ struct s3c2443_sm_bank bank[5]; /* 0x4f000000..0x4f0000bf */
++ S3C24X0_REG32 res[0x40]; /* 0x4f0000c0..0x4f0000ff */
++ S3C24X0_REG32 SMBONETYPER;
++ S3C24X0_REG32 SMCSR;
++ S3C24X0_REG32 SMCCR;
++} /*__attribute__((__packed__))*/ S3C2443_SMEM;
++
++
++/* MOBILE DRAM (see S3C2443 manual chapter 6) */
++typedef struct {
++ S3C24X0_REG32 BANKCFG;
++ S3C24X0_REG32 BANKCON1;
++ S3C24X0_REG32 BANKCON2;
++ S3C24X0_REG32 BANKCON3;
++ S3C24X0_REG32 REFRESH;
++ S3C24X0_REG32 TIMEOUT;
++} /*__attribute__((__packed__))*/ S3C2443_MDRAM
++
++#endif /* __S3C2443_H */
Added: trunk/src/target/u-boot/patches/uboot-smdk2443.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-smdk2443.patch 2007-05-07 23:11:17 UTC (rev 1924)
+++ trunk/src/target/u-boot/patches/uboot-smdk2443.patch 2007-05-08 03:21:28 UTC (rev 1925)
@@ -0,0 +1,1407 @@
+Index: u-boot/Makefile
+===================================================================
+--- u-boot.orig/Makefile
++++ u-boot/Makefile
+@@ -2014,6 +2014,9 @@
+ smdk2440_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0
+
++smdk2443_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2443 NULL s3c24x0
++
+ SX1_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm925t sx1
+
+Index: u-boot/board/smdk2443/Makefile
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/Makefile
+@@ -0,0 +1,67 @@
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := smdk2443.o flash.o udc.o
++SOBJS := lowlevel_init.o
++
++.PHONY: all
++
++all: $(LIB) lowlevel_foo.bin
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++lowlevel_foo.o: lowlevel_foo.S
++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
++ -o lowlevel_foo.o lowlevel_foo.S
++
++lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds
++ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
++ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
++
++lowlevel_foo.bin: lowlevel_foo
++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
++ lowlevel_foo lowlevel_foo.bin
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot/board/smdk2443/smdk2443.c
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/smdk2443.c
+@@ -0,0 +1,147 @@
++/*
++ * (C) Copyright 2006 OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <s3c2440.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define FCLK_SPEED 1
++
++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
++#define M_MDIV 0xC3
++#define M_PDIV 0x4
++#define M_SDIV 0x1
++#elif FCLK_SPEED==1 /* Fout = 399.65MHz */
++#define M_MDIV 0x6e
++#define M_PDIV 0x3
++#define M_SDIV 0x1
++#endif
++
++#define USB_CLOCK 1
++
++#if USB_CLOCK==0
++#define U_M_MDIV 0xA1
++#define U_M_PDIV 0x3
++#define U_M_SDIV 0x1
++#elif USB_CLOCK==1
++#define U_M_MDIV 0x3c
++#define U_M_PDIV 0x4
++#define U_M_SDIV 0x2
++#endif
++
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ /* to reduce PLL lock time, adjust the LOCKTIME register */
++ clk_power->LOCKTIME = 0xFFFFFF;
++
++ /* configure MPLL */
++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (4000);
++
++ /* configure UPLL */
++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
++
++ /* some delay between MPLL and UPLL */
++ delay (8000);
++
++ /* set up the I/O ports */
++ gpio->GPACON = 0x007FFFFF;
++ gpio->GPBCON = 0x00044555;
++ gpio->GPBUP = 0x000007FF;
++ gpio->GPCCON = 0xAAAAAAAA;
++ gpio->GPCUP = 0x0000FFFF;
++ gpio->GPDCON = 0xAAAAAAAA;
++ gpio->GPDUP = 0x0000FFFF;
++ gpio->GPECON = 0xAAAAAAAA;
++ gpio->GPEUP = 0x0000FFFF;
++ gpio->GPFCON = 0x000055AA;
++ gpio->GPFUP = 0x000000FF;
++ gpio->GPGCON = 0xFD95FFBA;
++ gpio->GPGUP = 0x0000FFFF;
++#ifdef CONFIG_SERIAL3
++ gpio->GPHCON = 0x002AAAAA;
++#else
++ gpio->GPHCON = 0x002AFAAA;
++#endif
++ gpio->GPHUP = 0x000007FF;
++
++#if 0
++ /* USB Device Part */
++ /*GPGCON is reset for USB Device */
++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
++
++ gpio->GPGDAT |= ( 1 << 12) ;
++ gpio->GPGDAT &= ~( 1 << 12) ;
++ udelay(20000);
++ gpio->GPGDAT |= ( 1 << 12) ;
++#endif
++
++ /* arch number of SMDK2440-Board */
++ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0x30000100;
++
++ icache_enable();
++ dcache_enable();
++
++ return 0;
++}
++
++int dram_init (void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
++ images: 640*480*2*2 = 1228800 < 1245184. */
++
++unsigned int dynpart_size[] = {
++ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 };
++
++char *dynpart_names[] = {
++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
++
++
+Index: u-boot/board/smdk2443/u-boot.lds
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/u-boot.lds
+@@ -0,0 +1,58 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm920t/start.o (.text)
++ cpu/arm920t/s3c24x0/nand_read.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+Index: u-boot/include/configs/smdk2443.h
+===================================================================
+--- /dev/null
++++ u-boot/include/configs/smdk2443.h
+@@ -0,0 +1,289 @@
++/*
++ * (C) Copyright 2007 OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * Configuation settings for the SAMSUNG SMDK2443 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#if 0
++/* If we want to start u-boot from usb bootloader in NOR flash */
++#define CONFIG_SKIP_RELOCATE_UBOOT 1
++#define CONFIG_SKIP_LOWLEVEL_INIT 1
++#else
++/* If we want to start u-boot directly from within NAND flash */
++#define CONFIG_LL_INIT_NAND_ONLY
++#define CONFIG_S3C2410_NAND_BOOT 1
++#define CONFIG_S3C2410_NAND_SKIP_BAD 1
++#endif
++
++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
++#define CONFIG_SMDK2443 1 /* on a SAMSUNG SMDK2440 Board */
++
++/* input clock of PLL */
++#define CONFIG_SYS_CLK_FREQ 16934400/* SMDK2440 has 16.9344MHz input clock */
++
++
++#define USE_920T_MMU 1
++#define CONFIG_USE_IRQ 1
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
++#define CS8900_BASE 0x19000300
++#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */
++#define CONFIG_HWFLOW 1
++
++/************************************************************
++ * RTC
++ ************************************************************/
++#define CONFIG_RTC_S3C24X0 1
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++#define CONFIG_COMMANDS \
++ (CONFIG_CMD_DFL | \
++ /*CFG_CMD_BSP | */ \
++ CFG_CMD_CACHE | \
++ CFG_CMD_DATE | \
++ /*CFG_CMD_DHCP | */ \
++ CFG_CMD_DIAG | \
++ CFG_CMD_ELF | \
++ CFG_CMD_EXT2 | \
++ CFG_CMD_FAT | \
++ /*CFG_CMD_HWFLOW | */ \
++ /* CFG_CMD_IDE | */ \
++ /* CFG_CMD_IRQ | */ \
++ CFG_CMD_JFFS2 | \
++ CFG_CMD_MMC | \
++ CFG_CMD_NAND | \
++ CFG_CMD_PING | \
++ CFG_CMD_PORTIO | \
++ CFG_CMD_REGINFO | \
++ CFG_CMD_SAVES | \
++ CFG_CMD_LICENSE | \
++ CFG_CMD_USB)
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8"
++#define CONFIG_ETHADDR 00:0c:20:02:0a:5b
++#define CONFIG_NETMASK 255.255.255.0
++#define CONFIG_IPADDR 192.168.1.100
++#define CONFIG_SERVERIP 192.168.1.21
++#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm"
++
++#define CONFIG_DOS_PARTITION 1
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
++/* what's this ? it's not used anywhere */
++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "SMDK2443 # " /* Monitor Command Prompt */
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 32 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0x32000000 /* default load address */
++
++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
++/* it to wrap 100 times (total 1562500) to get 1 sec. */
++#define CFG_HZ 1562500
++
++/* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (512*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/* IDE/ATA config */
++
++#if 0
++#define CFG_IDE_MAXBUS 1
++#define CFG_IDE_MAXDEVICE 2
++#define CFG_IDE_PREINIT 0
++
++#define CFG_ATA_BASE_ADDR
++#endif
++
++#define CONFIG_USB_OHCI 1
++
++#define CONFIG_USB_DEVICE 1
++#define CONFIG_USB_TTY 1
++#define CFG_CONSOLE_IS_IN_ENV 1
++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
++#define CONFIG_USBD_MANUFACTURER "FiWin"
++#define CONFIG_USBD_PRODUCT_NAME "S3C2443 Bootloader " U_BOOT_VERSION
++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0"
++#define CONFIG_USBD_DFU 1
++#define CONFIG_USBD_DFU_XFER_SIZE 4096
++#define CONFIG_USBD_DFU_INTERFACE 2
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++
++#define CFG_FLASH_BASE PHYS_FLASH_1
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
++#if 0
++#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
++#endif
++
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#ifdef CONFIG_AMD_LV800
++#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
++#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
++#endif
++#ifdef CONFIG_AMD_LV400
++#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
++#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
++#endif
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
++
++#define CFG_ENV_IS_IN_NAND 1
++#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */
++#define CFG_ENV_OFFSET_OOB 1
++#define CFG_PREBOOT_OVERRIDE 1
++
++#define NAND_MAX_CHIPS 1
++#define CFG_NAND_BASE 0x4e000000
++#define CFG_MAX_NAND_DEVICE 1
++
++#define CONFIG_MMC 1
++#define CFG_MMC_BASE 0xff000000
++
++#define CONFIG_EXT2 1
++
++/* FAT driver in u-boot is broken currently */
++#define CONFIG_FAT 1
++#define CONFIG_SUPPORT_VFAT
++
++#if 1
++/* JFFS2 driver */
++#define CONFIG_JFFS2_CMDLINE 1
++#define CONFIG_JFFS2_NAND 1
++#define CONFIG_JFFS2_NAND_DEV 0
++//#define CONFIG_JFFS2_NAND_OFF 0x634000
++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
++#endif
++
++/* ATAG configuration */
++#define CONFIG_INITRD_TAG 1
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_CMDLINE_TAG 1
++#if 0
++#define CONFIG_SERIAL_TAG 1
++#define CONFIG_REVISION_TAG 1
++#endif
++
++
++#if 0
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_S3C2410
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++
++#define VIDEO_KBD_INIT_FCT 0
++#define VIDEO_TSTC_FCT serial_tstc
++#define VIDEO_GETC_FCT serial_getc
++
++#define LCD_VIDEO_ADDR 0x33d00000
++#endif
++
++#define CONFIG_S3C2410_NAND_BBT 1
++//#define CONFIG_S3C2410_NAND_HWECC 1
++
++#define CFG_NAND_YAFFS_WRITE
++#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT
++
++#define MTDIDS_DEFAULT "nand0=smdk2443-nand"
++#define MTPARTS_DEFAULT "smdk2443-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)"
++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2443-nand"
++#define CONFIG_NAND_DYNPART
++
++#endif /* __CONFIG_H */
+Index: u-boot/board/smdk2443/lowlevel_foo.S
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/lowlevel_foo.S
+@@ -0,0 +1,82 @@
++
++_start:
++ b reset
++undefvec:
++ b undefvec
++swivec:
++ b swivec
++pabtvec:
++ b pabtvec
++dabtvec:
++ b dabtvec
++rsvdvec:
++ b rsvdvec
++irqvec:
++ b irqvec
++fiqvec:
++ b fiqvec
++
++reset:
++ /*
++ * set the cpu to SVC32 mode
++ */
++ mrs r0,cpsr
++ bic r0,r0,#0x1f
++ orr r0,r0,#0xd3
++ msr cpsr,r0
++
++/* turn off the watchdog */
++#define pWTCON 0x53000000
++#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
++#define INTSUBMSK 0x4A00001C
++#define CLKDIVN 0x4C000014 /* clock divisor register */
++
++ ldr r0, =pWTCON
++ mov r1, #0x0
++ str r1, [r0]
++
++ mov r1, #0xffffffff
++ ldr r0, =INTMSK
++ str r1, [r0]
++ ldr r1, =0x3ff
++ ldr r0, =INTSUBMSK
++ str r1, [r0]
++
++ /* FCLK:HCLK:PCLK = 1:2:4 */
++ /* default FCLK is 120 MHz ! */
++ ldr r0, =CLKDIVN
++ mov r1, #3
++ str r1, [r0]
++
++ bl cpu_init_crit
++ ldr r0,=TEXT_BASE
++ mov pc, r0
++
++cpu_init_crit:
++ /*
++ * flush v4 I/D caches
++ */
++ mov r0, #0
++ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
++ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
++
++ /*
++ * disable MMU stuff and caches
++ */
++ mrc p15, 0, r0, c1, c0, 0
++ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
++ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
++ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
++ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
++ mcr p15, 0, r0, c1, c0, 0
++
++ /*
++ * before relocating, we have to setup RAM timing
++ * because memory timing is board-dependend, you will
++ * find a lowlevel_init.S in your board directory.
++ */
++ mov ip, lr
++ bl lowlevel_init
++ mov lr, ip
++ mov pc, lr
++
+Index: u-boot/board/smdk2443/lowlevel_init.S
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/lowlevel_init.S
+@@ -0,0 +1,163 @@
++/*
++ * SMDK2443 Memory Setup
++ *
++ * Copyright (C) 2007 by OpenMoko, Inc.
++ * Author: Harald Welte <laforge at openmoko.org>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++
++
++/* some parameters for the board */
++
++/*
++ *
++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
++ *
++ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar at sec.samsung.com>
++ *
++ */
++
++#define BWSCON 0x48000000
++
++/* BWSCON */
++#define DW8 (0x0)
++#define DW16 (0x1)
++#define DW32 (0x2)
++#define WAIT (0x1<<2)
++#define UBLB (0x1<<3)
++
++#define B1_BWSCON (DW32)
++#define B2_BWSCON (DW16)
++#define B3_BWSCON (DW16 + WAIT + UBLB)
++#define B4_BWSCON (DW16)
++#define B5_BWSCON (DW16)
++#define B6_BWSCON (DW32)
++#define B7_BWSCON (DW32)
++
++/* BANK0CON */
++#define B0_Tacs 0x0 /* 0clk */
++#define B0_Tcos 0x0 /* 0clk */
++#define B0_Tacc 0x7 /* 14clk */
++#define B0_Tcoh 0x0 /* 0clk */
++#define B0_Tah 0x0 /* 0clk */
++#define B0_Tacp 0x0
++#define B0_PMC 0x0 /* normal */
++
++/* BANK1CON */
++#define B1_Tacs 0x0 /* 0clk */
++#define B1_Tcos 0x0 /* 0clk */
++#define B1_Tacc 0x7 /* 14clk */
++#define B1_Tcoh 0x0 /* 0clk */
++#define B1_Tah 0x0 /* 0clk */
++#define B1_Tacp 0x0
++#define B1_PMC 0x0
++
++#define B2_Tacs 0x0
++#define B2_Tcos 0x0
++#define B2_Tacc 0x7
++#define B2_Tcoh 0x0
++#define B2_Tah 0x0
++#define B2_Tacp 0x0
++#define B2_PMC 0x0
++
++#define B3_Tacs 0x0 /* 0clk */
++#define B3_Tcos 0x3 /* 4clk */
++#define B3_Tacc 0x7 /* 14clk */
++#define B3_Tcoh 0x1 /* 1clk */
++#define B3_Tah 0x0 /* 0clk */
++#define B3_Tacp 0x3 /* 6clk */
++#define B3_PMC 0x0 /* normal */
++
++#define B4_Tacs 0x0 /* 0clk */
++#define B4_Tcos 0x0 /* 0clk */
++#define B4_Tacc 0x7 /* 14clk */
++#define B4_Tcoh 0x0 /* 0clk */
++#define B4_Tah 0x0 /* 0clk */
++#define B4_Tacp 0x0
++#define B4_PMC 0x0 /* normal */
++
++#define B5_Tacs 0x0 /* 0clk */
++#define B5_Tcos 0x0 /* 0clk */
++#define B5_Tacc 0x7 /* 14clk */
++#define B5_Tcoh 0x0 /* 0clk */
++#define B5_Tah 0x0 /* 0clk */
++#define B5_Tacp 0x0
++#define B5_PMC 0x0 /* normal */
++
++#define B6_MT 0x3 /* SDRAM */
++#define B6_Trcd 0x1
++#define B6_SCAN 0x1 /* 9bit */
++
++#define B7_MT 0x3 /* SDRAM */
++#define B7_Trcd 0x1 /* 3clk */
++#define B7_SCAN 0x1 /* 9bit */
++
++/* REFRESH parameter */
++#define REFEN 0x1 /* Refresh enable */
++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
++#define Trp 0x0 /* 2clk */
++#define Trc 0x3 /* 7clk */
++#define Tchr 0x2 /* 3clk */
++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
++/**************************************/
++
++_TEXT_BASE:
++ .word TEXT_BASE
++
++.globl lowlevel_init
++lowlevel_init:
++ /* memory control configuration */
++ /* make r0 relative the current location so that it */
++ /* reads SMRDATA out of FLASH rather than memory ! */
++ ldr r0, =SMRDATA
++ ldr r1, _TEXT_BASE
++ sub r0, r0, r1
++ ldr r1, =BWSCON /* Bus Width Status Controller */
++ add r2, r0, #13*4
++0:
++ ldr r3, [r0], #4
++ str r3, [r1], #4
++ cmp r2, r0
++ bne 0b
++
++ /* everything is fine now */
++ mov pc, lr
++
++ .ltorg
++/* the literal pools origin */
++
++SMRDATA:
++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
++ .word 0x32
++ .word 0x30
++ .word 0x30
+Index: u-boot/board/smdk2443/config.mk
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/config.mk
+@@ -0,0 +1,25 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++# David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
++#
++# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
++#
++# see http://www.samsung.com/ for more information on SAMSUNG
++#
++
++#
++# SMDK2410 has 1 bank of 64 MB DRAM
++#
++# 3000'0000 to 3400'0000
++#
++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
++# optionally with a ramdisk at 3080'0000
++#
++# we load ourself to 33F8'0000
++#
++# download area is 3300'0000
++#
++
++
++TEXT_BASE = 0x33F80000
+Index: u-boot/board/smdk2443/lowlevel_foo.lds
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/lowlevel_foo.lds
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ lowlevel_foo.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+Index: u-boot/board/smdk2443/flash.c
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/flash.c
+@@ -0,0 +1,433 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Alex Zuepke <azu at sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++
++ulong myflush (void);
++
++
++#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
++#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++
++
++#define CMD_READ_ARRAY 0x000000F0
++#define CMD_UNLOCK1 0x000000AA
++#define CMD_UNLOCK2 0x00000055
++#define CMD_ERASE_SETUP 0x00000080
++#define CMD_ERASE_CONFIRM 0x00000030
++#define CMD_PROGRAM 0x000000A0
++#define CMD_UNLOCK_BYPASS 0x00000020
++
++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
++
++#define BIT_ERASE_DONE 0x00000080
++#define BIT_RDY_MASK 0x00000080
++#define BIT_PROGRAM_ERROR 0x00000020
++#define BIT_TIMEOUT 0x80000000 /* our flag */
++
++#define READY 1
++#define ERR 2
++#define TMO 4
++
++/*-----------------------------------------------------------------------
++ */
++
++ulong flash_init (void)
++{
++ int i, j;
++ ulong size = 0;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
++ ulong flashbase = 0;
++
++ flash_info[i].flash_id =
++#if defined(CONFIG_AMD_LV400)
++ (AMD_MANUFACT & FLASH_VENDMASK) |
++ (AMD_ID_LV400B & FLASH_TYPEMASK);
++#elif defined(CONFIG_AMD_LV800)
++ (AMD_MANUFACT & FLASH_VENDMASK) |
++ (AMD_ID_LV800B & FLASH_TYPEMASK);
++#else
++#error "Unknown flash configured"
++#endif
++ flash_info[i].size = FLASH_BANK_SIZE;
++ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
++ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
++ if (i == 0)
++ flashbase = PHYS_FLASH_1;
++ else
++ panic ("configured too many flash banks!\n");
++ for (j = 0; j < flash_info[i].sector_count; j++) {
++ if (j <= 3) {
++ /* 1st one is 16 KB */
++ if (j == 0) {
++ flash_info[i].start[j] =
++ flashbase + 0;
++ }
++
++ /* 2nd and 3rd are both 8 KB */
++ if ((j == 1) || (j == 2)) {
++ flash_info[i].start[j] =
++ flashbase + 0x4000 + (j -
++ 1) *
++ 0x2000;
++ }
++
++ /* 4th 32 KB */
++ if (j == 3) {
++ flash_info[i].start[j] =
++ flashbase + 0x8000;
++ }
++ } else {
++ flash_info[i].start[j] =
++ flashbase + (j - 3) * MAIN_SECT_SIZE;
++ }
++ }
++ size += flash_info[i].size;
++ }
++
++ flash_protect (FLAG_PROTECT_SET,
++ CFG_FLASH_BASE,
++ CFG_FLASH_BASE + monitor_flash_len - 1,
++ &flash_info[0]);
++
++ flash_protect (FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
++
++ return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t * info)
++{
++ int i;
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case (AMD_MANUFACT & FLASH_VENDMASK):
++ printf ("AMD: ");
++ break;
++ default:
++ printf ("Unknown Vendor ");
++ break;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case (AMD_ID_LV400B & FLASH_TYPEMASK):
++ printf ("1x Amd29LV400BB (4Mbit)\n");
++ break;
++ case (AMD_ID_LV800B & FLASH_TYPEMASK):
++ printf ("1x Amd29LV800BB (8Mbit)\n");
++ break;
++ default:
++ printf ("Unknown Chip Type\n");
++ goto Done;
++ break;
++ }
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; i++) {
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++ printf (" %08lX%s", info->start[i],
++ info->protect[i] ? " (RO)" : " ");
++ }
++ printf ("\n");
++
++ Done:;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t * info, int s_first, int s_last)
++{
++ ushort result;
++ int iflag, cflag, prot, sect;
++ int rc = ERR_OK;
++ int chip;
++
++ /* first look for protection bits */
++
++ if (info->flash_id == FLASH_UNKNOWN)
++ return ERR_UNKNOWN_FLASH_TYPE;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ return ERR_INVAL;
++ }
++
++ if ((info->flash_id & FLASH_VENDMASK) !=
++ (AMD_MANUFACT & FLASH_VENDMASK)) {
++ return ERR_UNKNOWN_FLASH_VENDOR;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++ if (prot)
++ return ERR_PROTECTED;
++
++ /*
++ * Disable interrupts which might cause a timeout
++ * here. Remember that our exception vectors are
++ * at address 0 in the flash, and we don't want a
++ * (ticker) exception to happen while the flash
++ * chip is in programming mode.
++ */
++ cflag = icache_status ();
++ icache_disable ();
++ iflag = disable_interrupts ();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
++ printf ("Erasing sector %2d ... ", sect);
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ if (info->protect[sect] == 0) { /* not protected */
++ vu_short *addr = (vu_short *) (info->start[sect]);
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ *addr = CMD_ERASE_CONFIRM;
++
++ /* wait until flash is ready */
++ chip = 0;
++
++ do {
++ result = *addr;
++
++ /* check timeout */
++ if (get_timer_masked () >
++ CFG_FLASH_ERASE_TOUT) {
++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++ chip = TMO;
++ break;
++ }
++
++ if (!chip
++ && (result & 0xFFFF) & BIT_ERASE_DONE)
++ chip = READY;
++
++ if (!chip
++ && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
++ chip = ERR;
++
++ } while (!chip);
++
++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++
++ if (chip == ERR) {
++ rc = ERR_PROG_ERROR;
++ goto outahere;
++ }
++ if (chip == TMO) {
++ rc = ERR_TIMOUT;
++ goto outahere;
++ }
++
++ printf ("ok.\n");
++ } else { /* it was protected */
++
++ printf ("protected!\n");
++ }
++ }
++
++ if (ctrlc ())
++ printf ("User Interrupt!\n");
++
++ outahere:
++ /* allow flash to settle - wait 10 ms */
++ udelay_masked (10000);
++
++ if (iflag)
++ enable_interrupts ();
++
++ if (cflag)
++ icache_enable ();
++
++ return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash
++ */
++
++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
++{
++ vu_short *addr = (vu_short *) dest;
++ ushort result;
++ int rc = ERR_OK;
++ int cflag, iflag;
++ int chip;
++
++ /*
++ * Check if Flash is (sufficiently) erased
++ */
++ result = *addr;
++ if ((result & data) != data)
++ return ERR_NOT_ERASED;
++
++
++ /*
++ * Disable interrupts which might cause a timeout
++ * here. Remember that our exception vectors are
++ * at address 0 in the flash, and we don't want a
++ * (ticker) exception to happen while the flash
++ * chip is in programming mode.
++ */
++ cflag = icache_status ();
++ icache_disable ();
++ iflag = disable_interrupts ();
++
++ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
++ *addr = CMD_PROGRAM;
++ *addr = data;
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ /* wait until flash is ready */
++ chip = 0;
++ do {
++ result = *addr;
++
++ /* check timeout */
++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++ chip = ERR | TMO;
++ break;
++ }
++ if (!chip && ((result & 0x80) == (data & 0x80)))
++ chip = READY;
++
++ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
++ result = *addr;
++
++ if ((result & 0x80) == (data & 0x80))
++ chip = READY;
++ else
++ chip = ERR;
++ }
++
++ } while (!chip);
++
++ *addr = CMD_READ_ARRAY;
++
++ if (chip == ERR || *addr != data)
++ rc = ERR_PROG_ERROR;
++
++ if (iflag)
++ enable_interrupts ();
++
++ if (cflag)
++ icache_enable ();
++
++ return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash.
++ */
++
++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
++{
++ ulong cp, wp;
++ int l;
++ int i, rc;
++ ushort data;
++
++ wp = (addr & ~1); /* get lower word aligned address */
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++ for (; i < 2 && cnt > 0; ++i) {
++ data = (data >> 8) | (*src++ << 8);
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < 2; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++
++ if ((rc = write_hword (info, wp, data)) != 0) {
++ return (rc);
++ }
++ wp += 2;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ while (cnt >= 2) {
++ data = *((vu_short *) src);
++ if ((rc = write_hword (info, wp, data)) != 0) {
++ return (rc);
++ }
++ src += 2;
++ wp += 2;
++ cnt -= 2;
++ }
++
++ if (cnt == 0) {
++ return ERR_OK;
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
++ data = (data >> 8) | (*src++ << 8);
++ --cnt;
++ }
++ for (; i < 2; ++i, ++cp) {
++ data = (data >> 8) | (*(uchar *) cp << 8);
++ }
++
++ return write_hword (info, wp, data);
++}
+Index: u-boot/board/smdk2443/udc.c
+===================================================================
+--- /dev/null
++++ u-boot/board/smdk2443/udc.c
+@@ -0,0 +1,23 @@
++
++#include <common.h>
++#include <usbdcore.h>
++#include <s3c2440.h>
++
++void udc_ctrl(enum usbd_event event, int param)
++{
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++ switch (event) {
++ case UDC_CTRL_PULLUP_ENABLE:
++ if (param)
++ gpio->GPGDAT |= (1 << 12);
++ else
++ gpio->GPGDAT &= ~(1 << 12);
++ break;
++ case UDC_CTRL_500mA_ENABLE:
++ /* IGNORE */
++ break;
++ default:
++ break;
++ }
++}
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