r3511 - in developers: . sameo sameo/patches sameo/patches/ar6k-atheros
sameo at sita.openmoko.org
sameo at sita.openmoko.org
Mon Nov 26 15:17:10 CET 2007
Author: sameo
Date: 2007-11-26 15:17:02 +0100 (Mon, 26 Nov 2007)
New Revision: 3511
Added:
developers/sameo/
developers/sameo/patches/
developers/sameo/patches/ar6k-atheros/
developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack.patch
developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_ar6000_wlan.patch
developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_functions.patch
developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_shcd.patch
developers/sameo/patches/ar6k-atheros/pnp_fixes_2.6.22.5.patch
developers/sameo/patches/ar6k-atheros/s3c2440_wlan_gpio_cfg.patch
developers/sameo/patches/ar6k-atheros/s3c24xx_hcd_atheros.patch
developers/sameo/patches/ar6k-atheros/series
Log:
ar6k-atheros: Initial commit, against 1.1 target FW.
With this patch series, we should be able to send our first probe
request, although a bogus one. Wireless-tools command work as well.
Added: developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,28469 @@
+---
+ arch/arm/Kconfig | 2
+ drivers/Kconfig | 2
+ drivers/Makefile | 1
+ drivers/sdio/Kconfig | 18
+ drivers/sdio/Makefile | 6
+ drivers/sdio/busdriver/Makefile | 7
+ drivers/sdio/busdriver/_busdriver.h | 462 +++
+ drivers/sdio/busdriver/sdio_bus.c | 2119 ++++++++++++++++
+ drivers/sdio/busdriver/sdio_bus_events.c | 1073 ++++++++
+ drivers/sdio/busdriver/sdio_bus_misc.c | 3184 +++++++++++++++++++++++++
+ drivers/sdio/busdriver/sdio_bus_os.c | 807 ++++++
+ drivers/sdio/busdriver/sdio_function.c | 713 +++++
+ drivers/sdio/hcd/Kconfig | 56
+ drivers/sdio/hcd/Makefile | 8
+ drivers/sdio/hcd/mx21/Makefile | 7
+ drivers/sdio/hcd/mx21/sdio_mx21.c | 1286 ++++++++++
+ drivers/sdio/hcd/mx21/sdio_mx21.h | 210 +
+ drivers/sdio/hcd/mx21/sdio_mx21_linux.h | 105
+ drivers/sdio/hcd/mx21/sdio_mx21_os.c | 435 +++
+ drivers/sdio/hcd/omap/Makefile | 3
+ drivers/sdio/hcd/omap/sdio_hcd.c | 1337 ++++++++++
+ drivers/sdio/hcd/omap/sdio_hcd_linux.h | 165 +
+ drivers/sdio/hcd/omap/sdio_hcd_os_2_6.c | 574 ++++
+ drivers/sdio/hcd/omap/sdio_omap_hcd.h | 372 ++
+ drivers/sdio/hcd/omap_2420/Makefile | 3
+ drivers/sdio/hcd/omap_2420/sdio_hcd.c | 1363 ++++++++++
+ drivers/sdio/hcd/omap_2420/sdio_hcd_linux.h | 147 +
+ drivers/sdio/hcd/omap_2420/sdio_hcd_os.c | 608 ++++
+ drivers/sdio/hcd/omap_2420/sdio_hcd_os_2_6.c | 731 +++++
+ drivers/sdio/hcd/omap_2420/sdio_omap_hcd.h | 370 ++
+ drivers/sdio/hcd/pci_ellen/Makefile | 7
+ drivers/sdio/hcd/pci_ellen/sdio_hcd.c | 1238 +++++++++
+ drivers/sdio/hcd/pci_ellen/sdio_hcd_linux.h | 185 +
+ drivers/sdio/hcd/pci_ellen/sdio_hcd_os.c | 781 ++++++
+ drivers/sdio/hcd/pci_ellen/sdio_pciellen_hcd.h | 253 +
+ drivers/sdio/hcd/pxa255/Makefile | 5
+ drivers/sdio/hcd/pxa255/sdio_hcd.c | 914 +++++++
+ drivers/sdio/hcd/pxa255/sdio_hcd_linux.h | 136 +
+ drivers/sdio/hcd/pxa255/sdio_hcd_os.c | 589 ++++
+ drivers/sdio/hcd/pxa255/sdio_pxa255hcd.h | 227 +
+ drivers/sdio/hcd/pxa270/Makefile | 5
+ drivers/sdio/hcd/pxa270/sdio_hcd.c | 1087 ++++++++
+ drivers/sdio/hcd/pxa270/sdio_hcd_linux.h | 150 +
+ drivers/sdio/hcd/pxa270/sdio_hcd_os.c | 1084 ++++++++
+ drivers/sdio/hcd/pxa270/sdio_pxa270hcd.h | 273 ++
+ drivers/sdio/lib/Makefile | 6
+ drivers/sdio/lib/sdio_lib_c.c | 903 +++++++
+ drivers/sdio/lib/sdio_lib_os.c | 254 +
+ include/linux/sdio/_sdio_defs.h | 632 ++++
+ include/linux/sdio/ctsystem.h | 110
+ include/linux/sdio/ctsystem_linux.h | 955 +++++++
+ include/linux/sdio/mmc_defs.h | 99
+ include/linux/sdio/sdio_busdriver.h | 1431 +++++++++++
+ include/linux/sdio/sdio_hcd_defs.h | 215 +
+ include/linux/sdio/sdio_lib.h | 262 ++
+ include/linux/sdio/sdlist.h | 137 +
+ 56 files changed, 28112 insertions(+)
+
+Index: linux-2.6.22/include/linux/sdio/_sdio_defs.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/_sdio_defs.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,632 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: _sdio_defs.h
++
++ at abstract: SD/SDIO definitions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef ___SDIO_DEFS_H___
++#define ___SDIO_DEFS_H___
++
++#define SD_INIT_BUS_CLOCK 100000 /* initialization clock in hz */
++#define SPI_INIT_BUS_CLOCK 100000 /* initialization clock in hz */
++#define SD_MAX_BUS_CLOCK 25000000 /* max clock speed in hz */
++#define SD_HS_MAX_BUS_CLOCK 50000000 /* SD high speed max clock speed in hz */
++#define SDIO_LOW_SPEED_MAX_BUS_CLOCK 400000 /* max low speed clock in hz */
++#define SDMMC_MIN_INIT_CLOCKS 80 /* minimun number of initialization clocks */
++#define SDIO_EMPC_CURRENT_THRESHOLD 300 /* SDIO 1.10 , EMPC (mA) threshold, we add some overhead */
++
++/* commands */
++#define CMD0 0
++#define CMD1 1
++#define CMD2 2
++#define CMD3 3
++#define CMD4 4
++#define CMD5 5
++#define CMD6 6
++#define CMD7 7
++#define CMD9 9
++#define CMD10 10
++#define CMD12 12
++#define CMD13 13
++#define CMD15 15
++#define CMD16 16
++#define CMD17 17
++#define CMD18 18
++#define CMD24 24
++#define CMD25 25
++#define CMD27 27
++#define CMD28 28
++#define CMD29 29
++#define CMD30 30
++#define CMD32 32
++#define CMD33 33
++#define CMD38 38
++#define CMD42 42
++#define CMD52 52
++#define CMD53 53
++#define CMD55 55
++#define CMD56 56
++#define CMD58 58
++#define CMD59 59
++#define ACMD6 6
++#define ACMD13 13
++#define ACMD22 22
++#define ACMD23 23
++#define ACMD41 41
++#define ACMD42 42
++#define ACMD51 51
++
++#define SD_ACMD6_BUS_WIDTH_1_BIT 0x00
++#define SD_ACMD6_BUS_WIDTH_4_BIT 0x02
++
++#define SD_CMD59_CRC_OFF 0x00000000
++#define SD_CMD59_CRC_ON 0x00000001
++
++/* SD/SPI max response size */
++#define SD_MAX_CMD_RESPONSE_BYTES SD_R2_RESPONSE_BYTES
++
++#define SD_R1_RESPONSE_BYTES 6
++#define SD_R1B_RESPONSE_BYTES SD_R1_RESPONSE_BYTES
++#define SD_R1_GET_CMD(pR) ((pR)[5] & 0xC0))
++#define SD_R1_SET_CMD(pR,cmd) (pR)[5] = (cmd) & 0xC0
++#define SD_R1_GET_CARD_STATUS(pR) (((UINT32)((pR)[1])) | \
++ (((UINT32)((pR)[2])) << 8) | \
++ (((UINT32)((pR)[3])) << 16) | \
++ (((UINT32)((pR)[4])) << 24) )
++#define SD_R1_SET_CMD_STATUS(pR,status) \
++{ \
++ (pR)[1] = (UINT8)(status); \
++ (pR)[2] = (UINT8)((status) >> 8); \
++ (pR)[3] = (UINT8)((status) >> 16); \
++ (pR)[4] = (UINT8)((status) >> 24); \
++}
++
++/* SD R1 card status bit masks */
++#define SD_CS_CMD_OUT_OF_RANGE ((UINT32)(1 << 31))
++#define SD_CS_ADDRESS_ERR (1 << 30)
++#define SD_CS_BLK_LEN_ERR (1 << 29)
++#define SD_CS_ERASE_SEQ_ERR (1 << 28)
++#define SD_CS_ERASE_PARAM_ERR (1 << 27)
++#define SD_CS_WP_ERR (1 << 26)
++#define SD_CS_CARD_LOCKED (1 << 25)
++#define SD_CS_LK_UNLK_FAILED (1 << 24)
++#define SD_CS_PREV_CMD_CRC_ERR (1 << 23)
++#define SD_CS_ILLEGAL_CMD_ERR (1 << 22)
++#define SD_CS_ECC_FAILED (1 << 21)
++#define SD_CS_CARD_INTERNAL_ERR (1 << 20)
++#define SD_CS_GENERAL_ERR (1 << 19)
++#define SD_CS_CSD_OVERWR_ERR (1 << 16)
++#define SD_CS_WP_ERASE_SKIP (1 << 15)
++#define SD_CS_ECC_DISABLED (1 << 14)
++#define SD_CS_ERASE_RESET (1 << 13)
++#define SD_CS_GET_STATE(status) (((status) >> 9) & 0x0f)
++#define SD_CS_SET_STATE(status, state) \
++{ \
++ (status) &= ~(0x0F << 9); \
++ (status) |= (state) << 9 \
++}
++
++#define SD_CS_TRANSFER_ERRORS \
++ ( SD_CS_ADDRESS_ERR | \
++ SD_CS_BLK_LEN_ERR | \
++ SD_CS_ERASE_SEQ_ERR | \
++ SD_CS_ERASE_PARAM_ERR | \
++ SD_CS_WP_ERR | \
++ SD_CS_ECC_FAILED | \
++ SD_CS_CARD_INTERNAL_ERR | \
++ SD_CS_GENERAL_ERR )
++
++#define SD_CS_STATE_IDLE 0
++#define SD_CS_STATE_READY 1
++#define SD_CS_STATE_IDENT 2
++#define SD_CS_STATE_STBY 3
++#define SD_CS_STATE_TRANS 4
++#define SD_CS_STATE_DATA 5
++#define SD_CS_STATE_RCV 6
++#define SD_CS_STATE_PRG 7
++#define SD_CS_STATE_DIS 8
++#define SD_CS_READY_FOR_DATA (1 << 8)
++#define SD_CS_APP_CMD (1 << 5)
++#define SD_CS_AKE_SEQ_ERR (1 << 3)
++
++/* SD R2 response */
++#define SD_R2_RESPONSE_BYTES 17
++#define MAX_CSD_CID_BYTES 16
++#define SD_R2_SET_STUFF_BITS(pR) (pR)[16] = 0x3F
++#define GET_SD_CSD_TRANS_SPEED(pR) (pR)[12]
++#define GET_SD_CID_MANFID(pR) (pR)[15]
++#define GET_SD_CID_PN_1(pR) (pR)[12]
++#define GET_SD_CID_PN_2(pR) (pR)[11]
++#define GET_SD_CID_PN_3(pR) (pR)[10]
++#define GET_SD_CID_PN_4(pR) (pR)[9]
++#define GET_SD_CID_PN_5(pR) (pR)[8]
++#define GET_SD_CID_PN_6(pR) (pR)[7]
++
++#define GET_SD_CID_OEMID(pR) ((((UINT16)(pR)[14]) << 8 )| (UINT16)((pR)[13]))
++#define SDMMC_OCR_VOLTAGE_MASK 0x7FFFFFFF
++/* SD R3 response */
++#define SD_R3_RESPONSE_BYTES 6
++#define SD_R3_GET_OCR(pR) ((((UINT32)((pR)[1])) | \
++ (((UINT32)((pR)[2])) << 8) | \
++ (((UINT32)((pR)[3])) << 16) | \
++ (((UINT32)((pR)[4])) << 24)) & SDMMC_OCR_VOLTAGE_MASK)
++#define SD_R3_IS_CARD_READY(pR) (((pR)[4] & 0x80) == 0x80)
++
++/* OCR bit definitions */
++#define SD_OCR_CARD_PWR_UP_STATUS ((UINT32)(1 << 31))
++#define SD_OCR_3_5_TO_3_6_VDD (1 << 23)
++#define SD_OCR_3_4_TO_3_5_VDD (1 << 22)
++#define SD_OCR_3_3_TO_3_4_VDD (1 << 21)
++#define SD_OCR_3_2_TO_3_3_VDD (1 << 20)
++#define SD_OCR_3_1_TO_3_2_VDD (1 << 19)
++#define SD_OCR_3_0_TO_3_1_VDD (1 << 18)
++#define SD_OCR_2_9_TO_3_0_VDD (1 << 17)
++#define SD_OCR_2_8_TO_2_9_VDD (1 << 16)
++#define SD_OCR_2_7_TO_2_8_VDD (1 << 15)
++#define SD_OCR_2_6_TO_2_7_VDD (1 << 14)
++#define SD_OCR_2_5_TO_2_6_VDD (1 << 13)
++#define SD_OCR_2_4_TO_2_5_VDD (1 << 12)
++#define SD_OCR_2_3_TO_2_4_VDD (1 << 11)
++#define SD_OCR_2_2_TO_2_3_VDD (1 << 10)
++#define SD_OCR_2_1_TO_2_2_VDD (1 << 9)
++#define SD_OCR_2_0_TO_2_1_VDD (1 << 8)
++#define SD_OCR_1_9_TO_2_0_VDD (1 << 7)
++#define SD_OCR_1_8_TO_1_9_VDD (1 << 6)
++#define SD_OCR_1_7_TO_1_8_VDD (1 << 5)
++#define SD_OCR_1_6_TO_1_7_VDD (1 << 4)
++
++/* SD Status data block */
++#define SD_STATUS_DATA_BYTES 64
++#define SDS_GET_DATA_WIDTH(buffer) ((buffer)[0] & 0xC0)
++#define SDS_BUS_1_BIT 0x00
++#define SDS_BUS_4_BIT 0x80
++#define SDS_GET_SECURE_MODE(buffer) ((buffer)[0] & 0x20)
++#define SDS_CARD_SECURE_MODE 0x20
++#define SDS_GET_CARD_TYPE(buffer) ((buffer)[60] & 0x0F)
++#define SDS_SD_CARD_RW 0x00
++#define SDS_SD_CARD_ROM 0x01
++
++/* SD R6 response */
++#define SD_R6_RESPONSE_BYTES 6
++#define SD_R6_GET_RCA(pR) ((UINT16)((pR)[3]) | (((UINT16)((pR)[4])) << 8))
++#define SD_R6_GET_CS(pR) ((UINT16)((pR)[1]) | (((UINT16)((pR)[2])) << 8))
++
++/* SD Configuration Register (SCR) */
++#define SD_SCR_BYTES 8
++#define SCR_REV_1_0 0x00
++#define SCR_SD_SPEC_1_00 0x00
++#define SCR_SD_SPEC_1_10 0x01
++#define SCR_BUS_SUPPORTS_1_BIT 0x01
++#define SCR_BUS_SUPPORTS_4_BIT 0x04
++#define SCR_SD_SECURITY_MASK 0x70
++#define SCR_SD_NO_SECURITY 0x00
++#define SCR_SD_SECURITY_1_0 0x10
++#define SCR_SD_SECURITY_2_0 0x20
++#define SCR_DATA_STATUS_1_AFTER_ERASE 0x80
++
++#define GET_SD_SCR_STRUCT_VER(pB) ((pB)[7] >> 4)
++#define GET_SD_SCR_SDSPEC_VER(pB) ((pB)[7] & 0x0F)
++#define GET_SD_SCR_BUSWIDTHS(pB) ((pB)[6] & 0x0F)
++#define GET_SD_SCR_BUSWIDTHS_FLAGS(pB) (pB)[6]
++#define GET_SD_SCR_SECURITY(pB) (((pB)[6] >> 4) & 0x07)
++#define GET_SD_SCR_DATA_STAT_AFTER_ERASE(pB) (((pB)[6] >> 7) & 0x01)
++
++/* SDIO R4 Response */
++#define SD_SDIO_R4_RESPONSE_BYTES 6
++#define SD_SDIO_R4_GET_OCR(pR) ((UINT32)((pR)[1]) | \
++ (((UINT32)(pR)[2]) << 8) | \
++ (((UINT32)(pR)[3]) << 16))
++#define SD_SDIO_R4_IS_MEMORY_PRESENT(pR) (((pR)[4] & 0x08) == 0x08)
++#define SD_SDIO_R4_GET_IO_FUNC_COUNT(pR) (((pR)[4] >> 4) & 0x07)
++#define SD_SDIO_R4_IS_CARD_READY(pR) (((pR)[4] & 0x80) == 0x80)
++
++/* SDIO R5 response */
++#define SD_SDIO_R5_RESPONSE_BYTES 6
++#define SD_SDIO_R5_READ_DATA_OFFSET 1
++#define SD_R5_GET_READ_DATA(pR) (pR)[SD_SDIO_R5_READ_DATA_OFFSET]
++#define SD_R5_RESP_FLAGS_OFFSET 2
++#define SD_R5_GET_RESP_FLAGS(pR) (pR)[SD_R5_RESP_FLAGS_OFFSET]
++#define SD_R5_SET_CMD(pR,cmd) (pR)[5] = (cmd) & 0xC0
++#define SD_R5_RESP_CMD_ERR (1 << 7) /* for previous cmd */
++#define SD_R5_ILLEGAL_CMD (1 << 6)
++#define SD_R5_GENERAL_ERR (1 << 3)
++#define SD_R5_INVALID_FUNC (1 << 1)
++#define SD_R5_ARG_RANGE_ERR (1 << 0)
++#define SD_R5_CURRENT_CMD_ERRORS (SD_R5_ILLEGAL_CMD | SD_R5_GENERAL_ERR \
++ | SD_R5_INVALID_FUNC | SD_R5_ARG_RANGE_ERR)
++#define SD_R5_ERRORS (SD_R5_CURRENT_CMD_ERRORS)
++
++#define SD_R5_GET_IO_STATE(pR) (((pR)[2] >> 4) & 0x03)
++#define SD_R5_STATE_DIS 0x00
++#define SD_R5_STATE_CMD 0x01
++#define SD_R5_STATE_TRN 0x02
++
++/* SDIO Modified R6 Response */
++#define SD_SDIO_R6_RESPONSE_BYTES 6
++#define SD_SDIO_R6_GET_RCA(pR) ((UINT16)((pR)[3]) | ((UINT16)((pR)[4]) << 8))
++#define SD_SDIO_R6_GET_CSTAT(pR)((UINT16)((pR)[1]) | ((UINT16)((pR)[2]) << 8))
++
++/* SPI mode R1 response */
++#define SPI_R1_RESPONSE_BYTES 1
++#define GET_SPI_R1_RESP_TOKEN(pR) (pR)[0]
++#define SPI_CS_STATE_IDLE 0x01
++#define SPI_CS_ERASE_RESET (1 << 1)
++#define SPI_CS_ILLEGAL_CMD (1 << 2)
++#define SPI_CS_CMD_CRC_ERR (1 << 3)
++#define SPI_CS_ERASE_SEQ_ERR (1 << 4)
++#define SPI_CS_ADDRESS_ERR (1 << 5)
++#define SPI_CS_PARAM_ERR (1 << 6)
++#define SPI_CS_ERR_MASK 0x7c
++
++/* SPI mode R2 response */
++#define SPI_R2_RESPONSE_BYTES 2
++#define GET_SPI_R2_RESP_TOKEN(pR) (pR)[1]
++#define GET_SPI_R2_STATUS_TOKEN(pR) (pR)[0]
++/* the first response byte is defined above */
++/* the second response byte is defined below */
++#define SPI_CS_CARD_IS_LOCKED (1 << 0)
++#define SPI_CS_LOCK_UNLOCK_FAILED (1 << 1)
++#define SPI_CS_ERROR (1 << 2)
++#define SPI_CS_INTERNAL_ERROR (1 << 3)
++#define SPI_CS_ECC_FAILED (1 << 4)
++#define SPI_CS_WP_VIOLATION (1 << 5)
++#define SPI_CS_ERASE_PARAM_ERR (1 << 6)
++#define SPI_CS_OUT_OF_RANGE (1 << 7)
++
++/* SPI mode R3 response */
++#define SPI_R3_RESPONSE_BYTES 5
++#define SPI_R3_GET_OCR(pR) ((((UINT32)((pR)[0])) | \
++ (((UINT32)((pR)[1])) << 8) | \
++ (((UINT32)((pR)[2])) << 16) | \
++ (((UINT32)((pR)[3])) << 24)) & SDMMC_OCR_VOLTAGE_MASK)
++#define SPI_R3_IS_CARD_READY(pR) (((pR)[3] & 0x80) == 0x80)
++#define GET_SPI_R3_RESP_TOKEN(pR) (pR)[4]
++
++/* SPI mode SDIO R4 response */
++#define SPI_SDIO_R4_RESPONSE_BYTES 5
++#define SPI_SDIO_R4_GET_OCR(pR) ((UINT32)((pR)[0]) | \
++ (((UINT32)(pR)[1]) << 8) | \
++ (((UINT32)(pR)[2]) << 16))
++#define SPI_SDIO_R4_IS_MEMORY_PRESENT(pR) (((pR)[3] & 0x08) == 0x08)
++#define SPI_SDIO_R4_GET_IO_FUNC_COUNT(pR) (((pR)[3] >> 4) & 0x07)
++#define SPI_SDIO_R4_IS_CARD_READY(pR) (((pR)[3] & 0x80) == 0x80)
++#define GET_SPI_SDIO_R4_RESP_TOKEN(pR) (pR)[4]
++
++/* SPI Mode SDIO R5 response */
++#define SPI_SDIO_R5_RESPONSE_BYTES 2
++#define GET_SPI_SDIO_R5_RESP_TOKEN(pR) (pR)[1]
++#define GET_SPI_SDIO_R5_RESPONSE_RDATA(pR) (pR)[0]
++#define SPI_R5_IDLE_STATE 0x01
++#define SPI_R5_ILLEGAL_CMD (1 << 2)
++#define SPI_R5_CMD_CRC (1 << 3)
++#define SPI_R5_FUNC_ERR (1 << 4)
++#define SPI_R5_PARAM_ERR (1 << 6)
++
++/* SDIO COMMAND 52 Definitions */
++#define CMD52_READ 0
++#define CMD52_WRITE 1
++#define CMD52_READ_AFTER_WRITE 1
++#define CMD52_NORMAL_WRITE 0
++#define SDIO_SET_CMD52_ARG(arg,rw,func,raw,address,writedata) \
++ (arg) = (((rw) & 1) << 31) | \
++ (((func) & 0x7) << 28) | \
++ (((raw) & 1) << 27) | \
++ (1 << 26) | \
++ (((address) & 0x1FFFF) << 9) | \
++ (1 << 8) | \
++ ((writedata) & 0xFF)
++#define SDIO_SET_CMD52_READ_ARG(arg,func,address) \
++ SDIO_SET_CMD52_ARG(arg,CMD52_READ,(func),0,address,0x00)
++#define SDIO_SET_CMD52_WRITE_ARG(arg,func,address,value) \
++ SDIO_SET_CMD52_ARG(arg,CMD52_WRITE,(func),CMD52_NORMAL_WRITE,address,value)
++
++/* SDIO COMMAND 53 Definitions */
++#define CMD53_READ 0
++#define CMD53_WRITE 1
++#define CMD53_BLOCK_BASIS 1
++#define CMD53_BYTE_BASIS 0
++#define CMD53_FIXED_ADDRESS 0
++#define CMD53_INCR_ADDRESS 1
++#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
++ (arg) = (((rw) & 1) << 31) | \
++ (((func) & 0x7) << 28) | \
++ (((mode) & 1) << 27) | \
++ (((opcode) & 1) << 26) | \
++ (((address) & 0x1FFFF) << 9) | \
++ ((bytes_blocks) & 0x1FF)
++
++#define SDIO_MAX_LENGTH_BYTE_BASIS 512
++#define SDIO_MAX_BLOCKS_BLOCK_BASIS 511
++#define SDIO_MAX_BYTES_PER_BLOCK 2048
++#define SDIO_COMMON_AREA_FUNCTION_NUMBER 0
++#define SDIO_FIRST_FUNCTION_NUMBER 1
++#define SDIO_LAST_FUNCTION_NUMBER 7
++
++#define CMD53_CONVERT_BYTE_BASIS_BLK_LENGTH_PARAM(b) (((b) < SDIO_MAX_LENGTH_BYTE_BASIS) ? (b) : 0)
++#define CMD53_CONVERT_BLOCK_BASIS_BLK_COUNT_PARAM(b) (((b) <= SDIO_MAX_BLOCKS_BLOCK_BASIS) ? (b) : 0)
++
++
++/* SDIO COMMON Registers */
++
++/* revision register */
++#define CCCR_SDIO_REVISION_REG 0x00
++#define CCCR_REV_MASK 0x0F
++#define CCCR_REV_1_0 0x00
++#define CCCR_REV_1_1 0x01
++#define SDIO_REV_MASK 0xF0
++#define SDIO_REV_1_00 0x00
++#define SDIO_REV_1_10 0x10
++#define SDIO_REV_1_20 0x20
++/* SD physical spec revision */
++#define SD_SPEC_REVISION_REG 0x01
++#define SD_REV_MASK 0x0F
++#define SD_REV_1_01 0x00
++#define SD_REV_1_10 0x01
++/* I/O Enable */
++#define SDIO_ENABLE_REG 0x02
++/* I/O Ready */
++#define SDIO_READY_REG 0x03
++/* Interrupt Enable */
++#define SDIO_INT_ENABLE_REG 0x04
++#define SDIO_INT_MASTER_ENABLE 0x01
++#define SDIO_INT_ALL_ENABLE 0xFE
++/* Interrupt Pending */
++#define SDIO_INT_PENDING_REG 0x05
++#define SDIO_INT_PEND_MASK 0xFE
++/* I/O Abort */
++#define SDIO_IO_ABORT_REG 0x06
++#define SDIO_IO_RESET (1 << 3)
++/* Bus Interface */
++#define SDIO_BUS_IF_REG 0x07
++#define CARD_DETECT_DISABLE 0x80
++#define SDIO_BUS_WIDTH_1_BIT 0x00
++#define SDIO_BUS_WIDTH_4_BIT 0x02
++/* Card Capabilities */
++#define SDIO_CARD_CAPS_REG 0x08
++#define SDIO_CAPS_CMD52_WHILE_DATA 0x01 /* card can issue CMD52 while data transfer */
++#define SDIO_CAPS_MULTI_BLOCK 0x02 /* card supports multi-block data transfers */
++#define SDIO_CAPS_READ_WAIT 0x04 /* card supports read-wait protocol */
++#define SDIO_CAPS_SUSPEND_RESUME 0x08 /* card supports I/O function suspend/resume */
++#define SDIO_CAPS_INT_MULTI_BLK 0x10 /* interrupts between multi-block data capable */
++#define SDIO_CAPS_ENB_INT_MULTI_BLK 0x20 /* enable ints between muli-block data */
++#define SDIO_CAPS_LOW_SPEED 0x40 /* low speed card */
++#define SDIO_CAPS_4BIT_LS 0x80 /* 4 bit low speed card */
++/* Common CIS pointer */
++#define SDIO_CMN_CIS_PTR_LOW_REG 0x09
++#define SDIO_CMN_CIS_PTR_MID_REG 0x0a
++#define SDIO_CMN_CIS_PTR_HI_REG 0x0b
++/* Bus suspend */
++#define SDIO_BUS_SUSPEND_REG 0x0c
++#define SDIO_FUNC_SUSPEND_STATUS_MASK 0x01 /* selected function is suspended */
++#define SDIO_SUSPEND_FUNCTION 0x02 /* suspend the current selected function */
++/* Function select (for bus suspension) */
++#define SDIO_FUNCTION_SELECT_REG 0x0d
++#define SDIO_SUSPEND_FUNCTION_0 0x00
++#define SDIO_SUSPEND_MEMORY_FUNC_MASK 0x08
++/* Function Execution */
++#define SDIO_FUNCTION_EXEC_REG 0x0e
++#define SDIO_MEMORY_FUNC_EXEC_MASK 0x01
++/* Function Ready */
++#define SDIO_FUNCTION_READY_REG 0x0f
++#define SDIO_MEMORY_FUNC_BUSY_MASK 0x01
++
++/* power control 1.10 only */
++#define SDIO_POWER_CONTROL_REG 0x12
++#define SDIO_POWER_CONTROL_SMPC 0x01
++#define SDIO_POWER_CONTROL_EMPC 0x02
++
++/* high speed control , 1.20 only */
++#define SDIO_HS_CONTROL_REG 0x13
++#define SDIO_HS_CONTROL_SHS 0x01
++#define SDIO_HS_CONTROL_EHS 0x02
++
++/* Function Base Registers */
++#define xFUNCTION_FBR_OFFSET(funcNo) (0x100*(funcNo))
++/* offset calculation that does not use multiplication */
++static INLINE UINT32 CalculateFBROffset(UCHAR FuncNo) {
++ UCHAR i = FuncNo;
++ UINT32 offset = 0;
++ while (i) {
++ offset += 0x100;
++ i--;
++ }
++ return offset;
++}
++/* Function info */
++#define FBR_FUNC_INFO_REG_OFFSET(fbr) ((fbr) + 0x00)
++#define FUNC_INFO_SUPPORTS_CSA_MASK 0x40
++#define FUNC_INFO_ENABLE_CSA 0x80
++#define FUNC_INFO_DEVICE_CODE_MASK 0x0F
++#define FUNC_INFO_DEVICE_CODE_LAST 0x0F
++#define FBR_FUNC_EXT_DEVICE_CODE_OFFSET(fbr) ((fbr) + 0x01)
++/* Function Power selection */
++#define FBR_FUNC_POWER_SELECT_OFFSET(fbr) ((fbr) + 0x02)
++#define FUNC_POWER_SELECT_SPS 0x01
++#define FUNC_POWER_SELECT_EPS 0x02
++/* Function CIS ptr */
++#define FBR_FUNC_CIS_LOW_OFFSET(fbr) ((fbr) + 0x09)
++#define FBR_FUNC_CIS_MID_OFFSET(fbr) ((fbr) + 0x0a)
++#define FBR_FUNC_CIS_HI_OFFSET(fbr) ((fbr) + 0x0b)
++/* Function CSA ptr */
++#define FBR_FUNC_CSA_LOW_OFFSET(fbr) ((fbr) + 0x0c)
++#define FBR_FUNC_CSA_MID_OFFSET(fbr) ((fbr) + 0x0d)
++#define FBR_FUNC_CSA_HI_OFFSET(fbr) ((fbr) + 0x0e)
++/* Function CSA data window */
++#define FBR_FUNC_CSA_DATA_OFFSET(fbr) ((fbr) + 0x0f)
++/* Function Block Size Control */
++#define FBR_FUNC_BLK_SIZE_LOW_OFFSET(fbr) ((fbr) + 0x10)
++#define FBR_FUNC_BLK_SIZE_HI_OFFSET(fbr) ((fbr) + 0x11)
++#define SDIO_CIS_AREA_BEGIN 0x00001000
++#define SDIO_CIS_AREA_END 0x00017fff
++/* Tuple definitions */
++#define CISTPL_NULL 0x00
++#define CISTPL_CHECKSUM 0x10
++#define CISTPL_VERS_1 0x15
++#define CISTPL_ALTSTR 0x16
++#define CISTPL_MANFID 0x20
++#define CISTPL_FUNCID 0x21
++#define CISTPL_FUNCE 0x22
++#define CISTPL_VENDOR 0x91
++#define CISTPL_END 0xff
++#define CISTPL_LINK_END 0xff
++
++
++/* Manufacturer ID tuple */
++struct SDIO_MANFID_TPL {
++ UINT16 ManufacturerCode; /* jedec code */
++ UINT16 ManufacturerInfo; /* manufacturer specific code */
++}CT_PACK_STRUCT;
++
++/* Function ID Tuple */
++struct SDIO_FUNC_ID_TPL {
++ UINT8 DeviceCode; /* device code */
++ UINT8 InitMask; /* system initialization mask (not used) */
++}CT_PACK_STRUCT;
++
++ /* Extended Function Tuple (Common) */
++struct SDIO_FUNC_EXT_COMMON_TPL {
++ UINT8 Type; /* type */
++ UINT16 Func0_MaxBlockSize; /* max function 0 block transfer size */
++ UINT8 MaxTransSpeed; /* max transfer speed (encoded) */
++#define TRANSFER_UNIT_MULTIPIER_MASK 0x07
++#define TIME_VALUE_MASK 0x78
++#define TIME_VALUE_SHIFT 3
++}CT_PACK_STRUCT;
++
++/* Extended Function Tuple (Per Function) */
++struct SDIO_FUNC_EXT_FUNCTION_TPL {
++ UINT8 Type; /* type */
++#define SDIO_FUNC_INFO_WAKEUP_SUPPORT 0x01
++ UINT8 FunctionInfo; /* function info */
++ UINT8 SDIORev; /* revision */
++ UINT32 CardPSN; /* product serial number */
++ UINT32 CSASize; /* CSA size */
++ UINT8 CSAProperties; /* CSA properties */
++ UINT16 MaxBlockSize; /* max block size for block transfers */
++ UINT32 FunctionOCR; /* optimal function OCR */
++ UINT8 OpMinPwr; /* operational min power */
++ UINT8 OpAvgPwr; /* operational average power */
++ UINT8 OpMaxPwr; /* operation maximum power */
++ UINT8 SbMinPwr; /* standby minimum power */
++ UINT8 SbAvgPwr; /* standby average power */
++ UINT8 SbMaxPwr; /* standby maximum power */
++ UINT16 MinBandWidth; /* minimum bus bandwidth */
++ UINT16 OptBandWidth; /* optimalbus bandwitdh */
++}CT_PACK_STRUCT;
++
++struct SDIO_FUNC_EXT_FUNCTION_TPL_1_1 {
++ struct SDIO_FUNC_EXT_FUNCTION_TPL CommonInfo; /* from 1.0*/
++ UINT16 EnableTimeOut; /* timeout for enable */
++ UINT16 OperPwrMaxPwr;
++ UINT16 OperPwrAvgPwr;
++ UINT16 HiPwrMaxPwr;
++ UINT16 HiPwrAvgPwr;
++ UINT16 LowPwrMaxPwr;
++ UINT16 LowPwrAvgPwr;
++}CT_PACK_STRUCT;
++
++static INLINE SDIO_STATUS ConvertCMD52ResponseToSDIOStatus(UINT8 CMD52ResponseFlags) {
++ if (!(CMD52ResponseFlags & SD_R5_ERRORS)) {
++ return SDIO_STATUS_SUCCESS;
++ }
++ if (CMD52ResponseFlags & SD_R5_ILLEGAL_CMD) {
++ return SDIO_STATUS_DATA_STATE_INVALID;
++ } else if (CMD52ResponseFlags & SD_R5_INVALID_FUNC) {
++ return SDIO_STATUS_INVALID_FUNC;
++ } else if (CMD52ResponseFlags & SD_R5_ARG_RANGE_ERR) {
++ return SDIO_STATUS_FUNC_ARG_ERROR;
++ } else {
++ return SDIO_STATUS_DATA_ERROR_UNKNOWN;
++ }
++}
++
++/* CMD6 mode switch definitions */
++
++#define SD_SWITCH_FUNC_CHECK 0
++#define SD_SWITCH_FUNC_SET ((UINT32)(1 << 31))
++#define SD_FUNC_NO_SELECT_MASK 0x00FFFFFF
++#define SD_SWITCH_GRP_1 0
++#define SD_SWITCH_GRP_2 1
++#define SD_SWITCH_GRP_3 2
++#define SD_SWITCH_GRP_4 3
++#define SD_SWITCH_GRP_5 4
++#define SD_SWITCH_GRP_6 5
++
++#define SD_SWITCH_HIGH_SPEED_GROUP SD_SWITCH_GRP_1
++#define SD_SWITCH_HIGH_SPEED_FUNC_NO 1
++
++#define SD_SWITCH_MAKE_SHIFT(grp) ((grp) * 4)
++
++#define SD_SWITCH_MAKE_GRP_PATTERN(FuncGrp,FuncNo) \
++ ((SD_FUNC_NO_SELECT_MASK & (~(0xF << SD_SWITCH_MAKE_SHIFT(FuncGrp)))) | \
++ (((FuncNo) & 0xF) << SD_SWITCH_MAKE_SHIFT(FuncGrp))) \
++
++#define SD_SWITCH_FUNC_ARG_GROUP_CHECK(FuncGrp,FuncNo) \
++ (SD_SWITCH_FUNC_CHECK | SD_SWITCH_MAKE_GRP_PATTERN(FuncGrp,FuncNo))
++
++#define SD_SWITCH_FUNC_ARG_GROUP_SET(FuncGrp,FuncNo) \
++ (SD_SWITCH_FUNC_SET | SD_SWITCH_MAKE_GRP_PATTERN(FuncGrp,FuncNo))
++
++#define SD_SWITCH_FUNC_STATUS_BLOCK_BYTES 64
++
++#define SD_SWITCH_FUNC_STATUS_GET_GRP_BIT_MASK(pBuffer,FuncGrp) \
++ (USHORT)((pBuffer)[50 + ((FuncGrp)*2)] | ((pBuffer)[51 + ((FuncGrp)*2)] << 8))
++
++#define SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pBuffer) \
++ (USHORT)((pBuffer)[62] | ((pBuffer)[63] << 8))
++
++static INLINE UINT8 SDSwitchGetSwitchResult(PUINT8 pBuffer, UINT8 FuncGrp)
++{
++ switch (FuncGrp) {
++ case 0:
++ return (pBuffer[47] & 0xF);
++ case 1:
++ return (pBuffer[47] >> 4);
++ case 2:
++ return (pBuffer[48] & 0xF);
++ case 3:
++ return (pBuffer[48] >> 4);
++ case 4:
++ return (pBuffer[49] & 0xF);
++ case 5:
++ return (pBuffer[49] >> 4);
++ default:
++ return 0xF;
++ }
++}
++
++#endif
+Index: linux-2.6.22/include/linux/sdio/ctsystem.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/ctsystem.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,110 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: cpsystem.h
++
++ at abstract: common system include file.
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __CPSYSTEM_H___
++#define __CPSYSTEM_H___
++
++/* SDIO stack status defines */
++/* < 0 error, >0 warning, 0 success */
++#define SDIO_IS_WARNING(status) ((status) > 0)
++#define SDIO_IS_ERROR(status) ((status) < 0)
++#define SDIO_SUCCESS(status) ((SDIO_STATUS)(status) >= 0)
++#define SDIO_STATUS_SUCCESS 0
++#define SDIO_STATUS_ERROR -1
++#define SDIO_STATUS_INVALID_PARAMETER -2
++#define SDIO_STATUS_PENDING 3
++#define SDIO_STATUS_DEVICE_NOT_FOUND -4
++#define SDIO_STATUS_DEVICE_ERROR -5
++#define SDIO_STATUS_INTERRUPTED -6
++#define SDIO_STATUS_NO_RESOURCES -7
++#define SDIO_STATUS_CANCELED -8
++#define SDIO_STATUS_BUFFER_TOO_SMALL -9
++#define SDIO_STATUS_NO_MORE_MESSAGES -10
++#define SDIO_STATUS_BUS_RESP_TIMEOUT -20 /* response timed-out */
++#define SDIO_STATUS_BUS_READ_TIMEOUT -21 /* read data timed-out */
++#define SDIO_STATUS_BUS_READ_CRC_ERR -22 /* data CRC failed */
++#define SDIO_STATUS_BUS_WRITE_ERROR -23 /* write failed */
++#define SDIO_STATUS_BUS_RESP_CRC_ERR -24 /* response received with a CRC error */
++#define SDIO_STATUS_INVALID_TUPLE_LENGTH -25 /* tuple length was invalid */
++#define SDIO_STATUS_TUPLE_NOT_FOUND -26 /* tuple could not be found */
++#define SDIO_STATUS_CIS_OUT_OF_RANGE -27 /* CIS is out of range in the tuple scan */
++#define SDIO_STATUS_FUNC_ENABLE_TIMEOUT -28 /* card timed out enabling or disabling */
++#define SDIO_STATUS_DATA_STATE_INVALID -29 /* card is in an invalid state for data */
++#define SDIO_STATUS_DATA_ERROR_UNKNOWN -30 /* card cannot process data transfer */
++#define SDIO_STATUS_INVALID_FUNC -31 /* sdio request is not valid for the function */
++#define SDIO_STATUS_FUNC_ARG_ERROR -32 /* sdio request argument is invalid or out of range */
++#define SDIO_STATUS_INVALID_COMMAND -33 /* SD COMMAND is invalid for the card state */
++#define SDIO_STATUS_SDREQ_QUEUE_FAILED -34 /* request failed to insert into queue */
++#define SDIO_STATUS_BUS_RESP_TIMEOUT_SHIFTABLE -35 /* response timed-out, possibily shiftable to correct */
++#define SDIO_STATUS_UNSUPPORTED -36 /* not supported */
++#define SDIO_STATUS_PROGRAM_TIMEOUT -37 /* memory card programming timeout */
++#define SDIO_STATUS_PROGRAM_STATUS_ERROR -38 /* memory card programming errors */
++
++#include <linux/sdio/ctsystem_linux.h>
++
++/* get structure from contained field */
++#define CONTAINING_STRUCT(address, struct_type, field_name)\
++ ((struct_type *)((ULONG_PTR)(address) - (ULONG_PTR)(&((struct_type *)0)->field_name)))
++
++#define ZERO_OBJECT(obj) memset(&(obj),0,sizeof(obj))
++#define ZERO_POBJECT(pObj) memset((pObj),0,sizeof(*(pObj)))
++
++/* bit field support functions */
++static INLINE void SetBit(PULONG pField, UINT position) {
++ *pField |= 1 << (ULONG)position;
++}
++static INLINE void ClearBit(PULONG pField, UINT position) {
++ *pField &= ~(1 << (ULONG)position);
++}
++static INLINE BOOL IsBitSet(PULONG pField, UINT position) {
++ return (*pField & (1 << (ULONG)position)) ? TRUE : FALSE;
++}
++static INLINE INT FirstClearBit(PULONG pField) {
++ UINT ii;
++ for(ii = 0; ii < sizeof(ULONG)*8; ii++) {
++ if (!IsBitSet(pField, ii)) {
++ return (INT)ii;
++ }
++ }
++ /* no clear bits found */
++ return -1;
++}
++
++#endif /* __CPSYSTEM_H___ */
+Index: linux-2.6.22/include/linux/sdio/ctsystem_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/ctsystem_linux.h 2007-11-08 16:56:34.000000000 +0100
+@@ -0,0 +1,955 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: ctsystem_linux.h
++
++ at abstract: common system include file for Linux.
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __CPSYSTEM_LINUX_H___
++#define __CPSYSTEM_LINUX_H___
++
++/* #define DBG_TIMESTAMP 1 */
++#define SD_TRACK_REQ 1
++
++/* LINUX support */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/spinlock.h>
++#include <linux/version.h>
++#include <linux/interrupt.h>
++#include <linux/pnp.h>
++#include <asm/hardirq.h>
++#include <asm/semaphore.h>
++#include <asm/io.h>
++#include <asm/scatterlist.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++
++
++/* generic types */
++typedef unsigned char UCHAR;
++typedef unsigned char * PUCHAR;
++typedef char TEXT;
++typedef char * PTEXT;
++typedef unsigned short USHORT;
++typedef unsigned short* PUSHORT;
++typedef unsigned int UINT;
++typedef unsigned int* PUINT;
++typedef int INT;
++typedef int* PINT;
++typedef unsigned long ULONG;
++typedef unsigned long* PULONG;
++typedef u8 UINT8;
++typedef u16 UINT16;
++typedef u32 UINT32;
++typedef u8* PUINT8;
++typedef u16* PUINT16;
++typedef u32* PUINT32;
++typedef unsigned char * ULONG_PTR;
++typedef void* PVOID;
++typedef unsigned char BOOL;
++typedef BOOL* PBOOL;
++typedef int SDIO_STATUS;
++typedef int SYSTEM_STATUS;
++typedef unsigned int EVENT_TYPE;
++typedef unsigned int EVENT_ARG;
++typedef unsigned int* PEVENT_TYPE;
++typedef struct semaphore OS_SEMAPHORE;
++typedef struct semaphore* POS_SEMAPHORE;
++typedef struct semaphore OS_SIGNAL; /* OS signals are just semaphores */
++typedef struct semaphore* POS_SIGNAL;
++typedef spinlock_t OS_CRITICALSECTION;
++typedef spinlock_t *POS_CRITICALSECTION;
++typedef int SDPOWER_STATE;
++typedef unsigned long ATOMIC_FLAGS;
++typedef INT THREAD_RETURN;
++typedef dma_addr_t DMA_ADDRESS;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9)
++typedef struct task_struct* PKERNEL_TASK;
++typedef struct device_driver OS_DRIVER;
++typedef struct device_driver* POS_DRIVER;
++typedef struct device OS_DEVICE;
++typedef struct device* POS_DEVICE;
++typedef struct pnp_driver OS_PNPDRIVER;
++typedef struct pnp_driver* POS_PNPDRIVER;
++typedef struct pnp_dev OS_PNPDEVICE;
++typedef struct pnp_dev* POS_PNPDEVICE;
++typedef struct module* POS_MODULE;
++#else
++/* 2.4 */
++typedef int PKERNEL_TASK;
++typedef PVOID OS_DRIVER;
++typedef PVOID* POS_DRIVER;
++typedef PVOID OS_DEVICE;
++typedef PVOID* POS_DEVICE;
++typedef PVOID OS_PNPDRIVER;
++typedef PVOID* POS_PNPDRIVER;
++typedef PVOID OS_PNPDEVICE;
++typedef PVOID* POS_PNPDEVICE;
++typedef struct module* POS_MODULE;
++#define module_param(a,b,c) MODULE_PARM(a, "i")
++#endif
++
++typedef int CT_DEBUG_LEVEL;
++
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++#ifndef FALSE
++#define FALSE 0
++#endif
++#ifndef NULL
++#define NULL ((PVOID)0)
++#endif
++#define SDDMA_DESCRIPTION_FLAG_DMA 0x1 /* DMA enabled */
++#define SDDMA_DESCRIPTION_FLAG_SGDMA 0x2 /* Scatter-Gather DMA enabled */
++typedef struct _SDDMA_DESCRIPTION {
++ UINT16 Flags; /* SDDMA_DESCRIPTION_FLAG_xxx */
++ UINT16 MaxDescriptors; /* number of supported scatter gather entries */
++ UINT32 MaxBytesPerDescriptor; /* maximum bytes in a DMA descriptor entry */
++ u64 Mask; /* dma address mask */
++ UINT32 AddressAlignment; /* dma address alignment mask, least significant bits indicate illegal address bits */
++ UINT32 LengthAlignment; /* dma buffer length alignment mask, least significant bits indicate illegal length bits */
++}SDDMA_DESCRIPTION, *PSDDMA_DESCRIPTION;
++typedef struct scatterlist SDDMA_DESCRIPTOR, *PSDDMA_DESCRIPTOR;
++
++#define INLINE inline
++#define CT_PACK_STRUCT __attribute__ ((packed))
++
++#define CT_DECLARE_MODULE_PARAM_INTEGER(p) module_param(p, int, 0644);
++
++/* debug print macros */
++//#define SDDBG_KERNEL_PRINT_LEVEL KERN_DEBUG
++#define SDDBG_KERNEL_PRINT_LEVEL KERN_ALERT
++
++#define DBG_MASK_NONE 0x0
++#define DBG_MASK_HCD 0x100
++#define DBG_MASK_LIB 0x200
++#define DBG_MASK_BUS 0x400
++
++/* debug output levels, this must be order low number to higher */
++#define SDDBG_ERROR 3
++#define SDDBG_WARN 4
++#define SDDBG_DEBUG 6
++#define SDDBG_TRACE 7
++
++#define DBG_LEVEL_NONE 0
++#define DBG_LEVEL_ERROR SDDBG_ERROR
++#define DBG_LEVEL_WARN SDDBG_WARN
++#define DBG_LEVEL_DEBUG SDDBG_DEBUG
++#define DBG_LEVEL_TRACE SDDBG_TRACE
++
++#define DBG_GET_LEVEL(lvl) ((lvl) & 0xff)
++#define DBG_GET_MASK(lvl) (((lvl) & 0xff00))
++
++#define DBG_SDIO_MASK (DBG_MASK_NONE | DBG_LEVEL_TRACE)
++
++#define DEBUG 1
++
++#ifdef DEBUG
++#define DBG_ASSERT(test) \
++{ \
++ if (!(test)) { \
++ DBG_PRINT(SDDBG_ERROR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \
++ } \
++}
++#define DBG_ASSERT_WITH_MSG(test,s) \
++{ \
++ if (!(test)) { \
++ DBG_PRINT(SDDBG_ERROR, ("Assert:%s File %s, Line: %d \n",(s),__FILE__, __LINE__)); \
++ } \
++}
++
++#define DBG_PRINT(lvl, args)\
++ do {\
++ if (DBG_GET_LEVEL(lvl) <= (DBG_SDIO_MASK & 0xff)) \
++ printk(_DBG_PRINTX_ARG args); \
++ } while(0);
++
++#else /* DEBUG */
++
++#define DBG_PRINT(lvl, str)
++#define DBG_ASSERT(test)
++#define DBG_ASSERT_WITH_MSG(test,s)
++#endif /* DEBUG */
++
++#define _DBG_PRINTX_ARG(arg...) arg /* unroll the parens around the var args*/
++#define DBG_GET_DEBUG_LEVEL() DBG_GET_LEVEL(DBG_SDIO_MASK)
++#define DBG_SET_DEBUG_LEVEL(v)
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Print a string to the debugger or console
++
++ @function name: REL_PRINT
++ @prototype: void REL_PRINT(INT Level, string)
++ @category: Support_Reference
++ @input: Level - debug level for the print
++
++ @output: none
++
++ @return:
++
++ @notes: If Level is less than the current debug level, the print will be
++ issued. This print cannot be conditionally compiled.
++ @see also: DBG_PRINT
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define REL_PRINT(lvl, args)\
++ {if (lvl <= DBG_GET_DEBUG_LEVEL())\
++ printk(_DBG_PRINTX_ARG args);\
++ }
++
++#ifdef DBG_CRIT_SECTION_RECURSE
++ /* this macro thows an exception if the lock is recursively taken
++ * the kernel must be configured with: CONFIG_DEBUG_SPINLOCK=y */
++#define call_spin_lock(pCrit) \
++{ \
++ UINT32 unlocked = 1; \
++ if ((pCrit)->lock) {unlocked = 0;} \
++ spin_lock_bh(pCrit); \
++ if (!unlocked) { \
++ unlocked = 0x01; \
++ unlocked = *((volatile UINT32 *)unlocked); \
++ } \
++}
++
++#define call_spin_lock_irqsave(pCrit,isc) \
++{ \
++ UINT32 unlocked = 1; \
++ if ((pCrit)->lock) {unlocked = 0;} \
++ spin_lock_irqsave(pCrit,isc); \
++ if (!unlocked) { \
++ unlocked = 0x01; \
++ unlocked = *((volatile UINT32 *)unlocked); \
++ } \
++}
++
++#else
++#define call_spin_lock(s) spin_lock_bh(s)
++#define call_spin_lock_irqsave(s,isc) spin_lock_irqsave(s,isc)
++#endif
++
++#define call_spin_unlock(s) spin_unlock_bh((s))
++#define call_spin_unlock_irqrestore(s,isc) spin_unlock_irqrestore(s,isc)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9)
++#define NonSchedulable() (in_atomic() || irqs_disabled())
++#else
++#define NonSchedulable() (irqs_disabled())
++#endif
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Initialize a critical section object.
++
++ @function name: CriticalSectionInit
++ @prototype: SDIO_STATUS CriticalSectionInit(POS_CRITICALSECTION pCrit)
++ @category: Support_Reference
++ @output: pCrit - pointer to critical section to initialize
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: CriticalSectionDelete() must be called to cleanup any resources
++ associated with the critical section.
++
++ @see also: CriticalSectionDelete, CriticalSectionAcquire, CriticalSectionRelease
++ @example: To initialize a critical section:
++ status = CriticalSectionInit(&pDevice->ListLock);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ return status;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS CriticalSectionInit(POS_CRITICALSECTION pCrit) {
++ spin_lock_init(pCrit);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Acquire a critical section lock.
++
++ @function name: CriticalSectionAcquire
++ @prototype: SDIO_STATUS CriticalSectionAcquire(POS_CRITICALSECTION pCrit)
++ @category: Support_Reference
++
++ @input: pCrit - pointer to critical section that was initialized
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: The critical section lock is acquired when this function returns
++ SDIO_STATUS_SUCCESS. Use CriticalSectionRelease() to release
++ the critical section lock.
++
++ @see also: CriticalSectionRelease
++
++ @example: To acquire a critical section lock:
++ status = CriticalSectionAcquire(&pDevice->ListLock);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ return status;
++ }
++ ... access protected data
++ // unlock
++ status = CriticalSectionRelease(&pDevice->ListLock);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ return status;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS CriticalSectionAcquire(POS_CRITICALSECTION pCrit) {
++ call_spin_lock(pCrit);
++ return SDIO_STATUS_SUCCESS;
++}
++
++// macro-tized versions
++#define CriticalSectionAcquire_M(pCrit) \
++ SDIO_STATUS_SUCCESS; call_spin_lock(pCrit)
++#define CriticalSectionRelease_M(pCrit) \
++ SDIO_STATUS_SUCCESS; call_spin_unlock(pCrit)
++
++#define CT_DECLARE_IRQ_SYNC_CONTEXT() unsigned long _ctSyncFlags
++
++#define CriticalSectionAcquireSyncIrq(pCrit) \
++ SDIO_STATUS_SUCCESS; call_spin_lock_irqsave(pCrit,_ctSyncFlags)
++
++#define CriticalSectionReleaseSyncIrq(pCrit) \
++ SDIO_STATUS_SUCCESS; call_spin_unlock_irqrestore(pCrit,_ctSyncFlags)
++
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Release a critical section lock.
++
++ @function name: CriticalSectionRelease
++ @prototype: SDIO_STATUS CriticalSectionRelease(POS_CRITICALSECTION pCrit)
++ @category: Support_Reference
++
++ @input: pCrit - pointer to critical section that was initialized
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: The critical section lock is released when this function returns
++ SDIO_STATUS_SUCCESS.
++
++ @see also: CriticalSectionAcquire
++
++ @example: see CriticalSectionAcquire
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS CriticalSectionRelease(POS_CRITICALSECTION pCrit) {
++ call_spin_unlock(pCrit);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Cleanup a critical section object
++
++ @function name: CriticalSectionDelete
++ @prototype: void CriticalSectionDelete(POS_CRITICALSECTION pCrit)
++ @category: Support_Reference
++
++ @input: pCrit - an initialized critical section object
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes:
++
++ @see also: CriticalSectionInit, CriticalSectionAcquire, CriticalSectionRelease
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void CriticalSectionDelete(POS_CRITICALSECTION pCrit) {
++ return;
++}
++
++/* internal use */
++static inline SDIO_STATUS SignalInitialize(POS_SIGNAL pSignal) {
++ sema_init(pSignal, 0);
++ return SDIO_STATUS_SUCCESS;
++}
++/* internal use */
++static inline void SignalDelete(POS_SIGNAL pSignal) {
++ return;
++}
++/* internal use */
++static inline SDIO_STATUS SignalWaitInterruptible(POS_SIGNAL pSignal) {
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"SignalWaitInterruptible not allowed\n");
++ if (down_interruptible(pSignal) == 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_INTERRUPTED;
++ }
++}
++/* internal use */
++static inline SDIO_STATUS SignalWait(POS_SIGNAL pSignal) {
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"SignalWait not allowed\n");
++ down(pSignal);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/* internal use */
++static inline SDIO_STATUS SignalSet(POS_SIGNAL pSignal) {
++ up(pSignal);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Initialize a semaphore object.
++
++ @function name: SemaphoreInitialize
++ @prototype: SDIO_STATUS SemaphoreInitialize(POS_SEMAPHORE pSem, UINT value)
++ @category: Support_Reference
++
++ @input: value - initial value of the semaphore
++
++ @output: pSem - pointer to a semaphore object to initialize
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: SemaphoreDelete() must be called to cleanup any resources
++ associated with the semaphore
++
++ @see also: SemaphoreDelete, SemaphorePend, SemaphorePendInterruptable
++
++ @example: To initialize a semaphore:
++ status = SemaphoreInitialize(&pDevice->ResourceSem,1);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ return status;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS SemaphoreInitialize(POS_SEMAPHORE pSem, UINT value) {
++ sema_init(pSem, value);
++ return SDIO_STATUS_SUCCESS;
++}
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Cleanup a semaphore object.
++
++ @function name: SemaphoreDelete
++ @prototype: void SemaphoreDelete(POS_SEMAPHORE pSem)
++ @category: Support_Reference
++
++ @input: pSem - pointer to a semaphore object to cleanup
++
++ @return:
++
++ @notes:
++
++ @see also: SemaphoreInitialize
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void SemaphoreDelete(POS_SEMAPHORE pSem) {
++ return;
++}
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Acquire the semaphore or pend if the resource is not available
++
++ @function name: SemaphorePend
++ @prototype: SDIO_STATUS SemaphorePend(POS_SEMAPHORE pSem)
++ @category: Support_Reference
++
++ @input: pSem - pointer to an initialized semaphore object
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: If the semaphore count is zero this function blocks until the count
++ becomes non-zero, otherwise the count is decremented and execution
++ continues. While waiting, the task/thread cannot be interrupted.
++ If the task or thread should be interruptible, use SemaphorePendInterruptible.
++ On some OSes SemaphorePend and SemaphorePendInterruptible behave the same.
++
++ @see also: SemaphorePendInterruptable, SemaphorePost
++ @example: To wait for a resource using a semaphore:
++ status = SemaphorePend(&pDevice->ResourceSem);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ return status;
++ }
++ ... resource acquired
++ SemaphorePost(&pDevice->ResourceSem);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS SemaphorePend(POS_SEMAPHORE pSem) {
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"SemaphorePend not allowed\n");
++ down(pSem);
++ return SDIO_STATUS_SUCCESS;
++}
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Acquire the semaphore or pend if the resource is not available
++
++ @function name: SemaphorePendInterruptable
++ @prototype: SDIO_STATUS SemaphorePendInterruptable(POS_SEMAPHORE pSem)
++ @category: Support_Reference
++
++ @input: pSem - pointer to an initialized semaphore object
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: If the semaphore count is zero this function blocks until the count
++ becomes non-zero, otherwise the count is decremented and execution
++ continues. While waiting, the task/thread can be interrupted.
++ If the task or thread should not be interruptible, use SemaphorePend.
++
++ @see also: SemaphorePend, SemaphorePost
++ @example: To wait for a resource using a semaphore:
++ status = SemaphorePendInterruptable(&pDevice->ResourceSem);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed, could have been interrupted
++ return status;
++ }
++ ... resource acquired
++ SemaphorePost(&pDevice->ResourceSem);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS SemaphorePendInterruptable(POS_SEMAPHORE pSem) {
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"SemaphorePendInterruptable not allowed\n");
++ if (down_interruptible(pSem) == 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_INTERRUPTED;
++ }
++}
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Post a semaphore.
++
++ @function name: SemaphorePost
++ @prototype: SDIO_STATUS SemaphorePost(POS_SEMAPHORE pSem)
++ @category: Support_Reference
++
++ @input: pSem - pointer to an initialized semaphore object
++
++ @return: SDIO_STATUS_SUCCESS on success.
++
++ @notes: This function increments the semaphore count.
++
++ @see also: SemaphorePend, SemaphorePendInterruptable.
++ @example: Posting a semaphore:
++ status = SemaphorePendInterruptable(&pDevice->ResourceSem);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed, could have been interrupted
++ return status;
++ }
++ ... resource acquired
++ // post the semaphore
++ SemaphorePost(&pDevice->ResourceSem);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS SemaphorePost(POS_SEMAPHORE pSem) {
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"SemaphorePost not allowed\n");
++ up(pSem);
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Allocate a block of kernel accessible memory
++
++ @function name: KernelAlloc
++ @prototype: PVOID KernelAlloc(UINT size)
++ @category: Support_Reference
++
++ @input: size - size of memory block to allocate
++
++ @return: pointer to the allocated memory, NULL if allocation failed
++
++ @notes: For operating systems that use paging, the allocated memory is always
++ non-paged memory. Caller should only use KernelFree() to release the
++ block of memory. This call can potentially block and should only be called
++ from a schedulable context. Use KernelAllocIrqSafe() if the allocation
++ must be made from a non-schedulable context.
++
++ @see also: KernelFree, KernelAllocIrqSafe
++ @example: allocating memory:
++ pBlock = KernelAlloc(1024);
++ if (pBlock == NULL) {
++ .. failed, no memory
++ return SDIO_STATUS_INSUFFICIENT_RESOURCES;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline PVOID KernelAlloc(UINT size) {
++ PVOID pMem = kmalloc(size, GFP_KERNEL);
++ if (pMem != NULL) { memset(pMem,0,size); }
++ return pMem;
++}
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Free a block of kernel accessible memory.
++
++ @function name: KernelFree
++ @prototype: void KernelFree(PVOID ptr)
++ @category: Support_Reference
++
++ @input: ptr - pointer to memory allocated with KernelAlloc()
++
++ @return:
++
++ @notes: Caller should only use KernelFree() to release memory that was allocated
++ with KernelAlloc().
++
++ @see also: KernelAlloc
++ @example: KernelFree(pBlock);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void KernelFree(PVOID ptr) {
++ kfree(ptr);
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Allocate a block of kernel accessible memory in an IRQ-safe manner
++
++ @function name: KernelAllocIrqSafe
++ @prototype: PVOID KernelAllocIrqSafe(UINT size)
++ @category: Support_Reference
++
++ @input: size - size of memory block to allocate
++
++ @return: pointer to the allocated memory, NULL if allocation failed
++
++ @notes: This variant of KernelAlloc allows the allocation of small blocks of
++ memory from an ISR or from a context where scheduling has been disabled.
++ The allocations should be small as the memory is typically allocated
++ from a critical heap. The caller should only use KernelFreeIrqSafe()
++ to release the block of memory.
++
++ @see also: KernelAlloc, KernelFreeIrqSafe
++ @example: allocating memory:
++ pBlock = KernelAllocIrqSafe(16);
++ if (pBlock == NULL) {
++ .. failed, no memory
++ return SDIO_STATUS_INSUFFICIENT_RESOURCES;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline PVOID KernelAllocIrqSafe(UINT size) {
++ return kmalloc(size, GFP_ATOMIC);
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Free a block of kernel accessible memory.
++
++ @function name: KernelFreeIrqSafe
++ @prototype: void KernelFreeIrqSafe(PVOID ptr)
++ @category: Support_Reference
++
++ @input: ptr - pointer to memory allocated with KernelAllocIrqSafe()
++
++ @return:
++
++ @notes: Caller should only use KernelFreeIrqSafe() to release memory that was allocated
++ with KernelAllocIrqSafe().
++
++ @see also: KernelAllocIrqSafe
++ @example: KernelFreeIrqSafe(pBlock);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void KernelFreeIrqSafe(PVOID ptr) {
++ kfree(ptr);
++}
++
++/* error status conversions */
++static inline SYSTEM_STATUS SDIOErrorToOSError(SDIO_STATUS status) {
++ switch (status) {
++ case SDIO_STATUS_SUCCESS:
++ return 0;
++ case SDIO_STATUS_INVALID_PARAMETER:
++ return -EINVAL;
++ case SDIO_STATUS_PENDING:
++ return -EAGAIN; /* try again */
++ case SDIO_STATUS_DEVICE_NOT_FOUND:
++ return -ENXIO;
++ case SDIO_STATUS_DEVICE_ERROR:
++ return -EIO;
++ case SDIO_STATUS_INTERRUPTED:
++ return -EINTR;
++ case SDIO_STATUS_NO_RESOURCES:
++ return -ENOMEM;
++ case SDIO_STATUS_ERROR:
++ default:
++ return -EFAULT;
++ }
++}
++static inline SDIO_STATUS OSErrorToSDIOError(SYSTEM_STATUS status) {
++ if (status >=0) {
++ return SDIO_STATUS_SUCCESS;
++ }
++ switch (status) {
++ case -EINVAL:
++ return SDIO_STATUS_INVALID_PARAMETER;
++ case -ENXIO:
++ return SDIO_STATUS_DEVICE_NOT_FOUND;
++ case -EIO:
++ return SDIO_STATUS_DEVICE_ERROR;
++ case -EINTR:
++ return SDIO_STATUS_INTERRUPTED;
++ case -ENOMEM:
++ return SDIO_STATUS_NO_RESOURCES;
++ case -EFAULT:
++ return SDIO_STATUS_ERROR;
++ default:
++ return SDIO_STATUS_ERROR;
++ }
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Sleep or delay the execution context for a number of milliseconds.
++
++ @function name: OSSleep
++ @prototype: SDIO_STATUS OSSleep(INT SleepInterval)
++ @category: Support_Reference
++
++ @input: SleepInterval - time in milliseconds to put the execution context to sleep
++
++ @return: SDIO_STATUS_SUCCESS if sleep succeeded.
++
++ @notes: Caller should be in a context that allows it to sleep or block. The
++ minimum duration of sleep may be greater than 1 MS on some platforms and OSes.
++
++ @see also: OSSleep
++ @example: Using sleep to delay
++ EnableSlotPower(pSlot);
++ // wait for power to settle
++ status = OSSleep(100);
++ if (!SDIO_SUCCESS(status)){
++ // failed..
++ }
++
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline SDIO_STATUS OSSleep(INT SleepInterval) {
++ UINT32 delta;
++
++ DBG_ASSERT_WITH_MSG(!NonSchedulable(),"OSSleep not allowed\n");
++ /* convert timeout to ticks */
++ delta = (SleepInterval * HZ)/1000;
++ if (delta == 0) {
++ delta = 1;
++ }
++ set_current_state(TASK_INTERRUPTIBLE);
++ if (schedule_timeout(delta) != 0) {
++ return SDIO_STATUS_INTERRUPTED;
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: get the OSs device object
++
++ @function name: SD_GET_OS_DEVICE
++ @prototype: POS_DEVICE SD_GET_OS_DEVICE(PSDDEVICE pDevice)
++ @category: Support_Reference
++
++ @input: pDevice - the device on the HCD
++
++ @return: pointer to the OSs device
++
++ @see also:
++ @example: obtain low level device
++ pFunctionContext->GpsDevice.Port.dev = SD_GET_OS_DEVICE(pDevice);
++
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SD_GET_OS_DEVICE(pDevice) &((pDevice)->Device.dev)
++
++
++#ifdef __iomem
++ /* new type checking in 2.6.9 */
++ /* I/O Access macros */
++#define _READ_DWORD_REG(reg) \
++ readl((const volatile void __iomem *)(reg))
++#define _READ_WORD_REG(reg) \
++ readw((const volatile void __iomem *)(reg))
++#define _READ_BYTE_REG(reg) \
++ readb((const volatile void __iomem *)(reg))
++#define _WRITE_DWORD_REG(reg,value) \
++ writel((value),(volatile void __iomem *)(reg))
++#define _WRITE_WORD_REG(reg,value) \
++ writew((value),(volatile void __iomem *)(reg))
++#define _WRITE_BYTE_REG(reg,value) \
++ writeb((value),(volatile void __iomem *)(reg))
++#else
++ /* I/O Access macros */
++#define _READ_DWORD_REG(reg) \
++ readl((reg))
++#define _READ_WORD_REG(reg) \
++ readw((reg))
++#define _READ_BYTE_REG(reg) \
++ readb((reg))
++#define _WRITE_DWORD_REG(reg,value) \
++ writel((value),(reg))
++#define _WRITE_WORD_REG(reg,value) \
++ writew((value),(reg))
++#define _WRITE_BYTE_REG(reg,value) \
++ writeb((value),(reg))
++#endif
++ /* atomic operators */
++static inline ATOMIC_FLAGS AtomicTest_Set(volatile ATOMIC_FLAGS *pValue, INT BitNo) {
++ return test_and_set_bit(BitNo,(ATOMIC_FLAGS *)pValue);
++}
++static inline ATOMIC_FLAGS AtomicTest_Clear(volatile ATOMIC_FLAGS *pValue, INT BitNo) {
++ return test_and_clear_bit(BitNo,(ATOMIC_FLAGS *)pValue);
++}
++
++struct _OSKERNEL_HELPER;
++
++typedef THREAD_RETURN (*PHELPER_FUNCTION)(struct _OSKERNEL_HELPER *);
++
++typedef struct _OSKERNEL_HELPER {
++ PKERNEL_TASK pTask;
++ BOOL ShutDown;
++ OS_SIGNAL WakeSignal;
++ struct completion Completion;
++ PVOID pContext;
++ PHELPER_FUNCTION pHelperFunc;
++}OSKERNEL_HELPER, *POSKERNEL_HELPER;
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Wake the helper thread
++
++ @function name: SD_WAKE_OS_HELPER
++ @prototype: SD_WAKE_OS_HELPER(POSKERNEL_HELPER pOSHelper)
++ @category: Support_Reference
++
++ @input: pOSHelper - the OS helper object
++
++ @return: SDIO_STATUS
++
++ @see also: SDLIB_OSCreateHelper
++
++ @example: Waking up a helper thread
++ status = SD_WAKE_OS_HELPER(&pInstance->OSHelper);
++
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SD_WAKE_OS_HELPER(p) SignalSet(&(p)->WakeSignal)
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Obtains the context for the helper function
++
++ @function name: SD_GET_OS_HELPER_CONTEXT
++ @prototype: SD_GET_OS_HELPER_CONTEXT(POSKERNEL_HELPER pOSHelper)
++ @category: Support_Reference
++
++ @input: pOSHelper - the OS helper object
++
++ @return: helper specific context
++
++ @notes: This macro should only be called by the function associated with
++ the helper object.
++
++ @see also: SDLIB_OSCreateHelper
++
++ @example: Getting the helper specific context
++ PMYCONTEXT pContext = (PMYCONTEXT)SD_GET_OS_HELPER_CONTEXT(pHelper);
++
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SD_GET_OS_HELPER_CONTEXT(p) (p)->pContext
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Check helper function shut down flag.
++
++ @function name: SD_IS_HELPER_SHUTTING_DOWN
++ @prototype: SD_IS_HELPER_SHUTTING_DOWN(POSKERNEL_HELPER pOSHelper)
++ @category: Support_Reference
++
++ @input: pOSHelper - the OS helper object
++
++ @return: TRUE if shutting down, else FALSE
++
++ @notes: This macro should only be called by the function associated with
++ the helper object. The function should call this macro when it
++ unblocks from the call to SD_WAIT_FOR_WAKEUP(). If this function
++ returns TRUE, the function should clean up and exit.
++
++ @see also: SDLIB_OSCreateHelper , SD_WAIT_FOR_WAKEUP
++
++ @example: Checking for shutdown
++ while(1) {
++ status = SD_WAIT_FOR_WAKEUP(pHelper);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ if (SD_IS_HELPER_SHUTTING_DOWN(pHelper)) {
++ ... shutting down
++ break;
++ }
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SD_IS_HELPER_SHUTTING_DOWN(p) (p)->ShutDown
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Suspend and wait for wakeup signal
++
++ @function name: SD_WAIT_FOR_WAKEUP
++ @prototype: SD_WAIT_FOR_WAKEUP(POSKERNEL_HELPER pOSHelper)
++ @category: Support_Reference
++
++ @input: pOSHelper - the OS helper object
++
++ @return: SDIO_STATUS
++
++ @notes: This macro should only be called by the function associated with
++ the helper object. The function should call this function to suspend (block)
++ itself and wait for a wake up signal. The function should always check
++ whether the function should exit by calling SD_IS_HELPER_SHUTTING_DOWN.
++
++ @see also: SDLIB_OSCreateHelper , SD_IS_HELPER_SHUTTING_DOWN
++
++ @example: block on the wake signal
++ while(1) {
++ status = SD_WAIT_FOR_WAKEUP(pHelper);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ if (SD_IS_HELPER_SHUTTING_DOWN(pHelper)) {
++ ... shutting down
++ break;
++ }
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SD_WAIT_FOR_WAKEUP(p) SignalWait(&(p)->WakeSignal);
++
++#define CT_LE16_TO_CPU_ENDIAN(x) __le16_to_cpu(x)
++#define CT_LE32_TO_CPU_ENDIAN(x) __le32_to_cpu(x)
++#define CT_CPU_ENDIAN_TO_LE16(x) __cpu_to_le16(x)
++#define CT_CPU_ENDIAN_TO_LE32(x) __cpu_to_le32(x)
++
++#define CT_CPU_ENDIAN_TO_BE16(x) __cpu_to_be16(x)
++#define CT_CPU_ENDIAN_TO_BE32(x) __cpu_to_be32(x)
++#define CT_BE16_TO_CPU_ENDIAN(x) __be16_to_cpu(x)
++#define CT_BE32_TO_CPU_ENDIAN(x) __be32_to_cpu(x)
++#endif /* __CPSYSTEM_LINUX_H___ */
++
+Index: linux-2.6.22/include/linux/sdio/mmc_defs.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/mmc_defs.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,99 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: mmc_defs.h
++
++ at abstract: MMC definitions not already defined in _sdio_defs.h
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef ___MMC_DEFS_H___
++#define ___MMC_DEFS_H___
++
++#define MMC_MAX_BUS_CLOCK 20000000 /* max clock speed in hz */
++#define MMC_HS_MAX_BUS_CLOCK 52000000 /* MMC PLUS (high speed) max clock rate in hz */
++
++/* R2 (CSD) macros */
++#define GET_MMC_CSD_TRANS_SPEED(pR) (pR)[12]
++#define GET_MMC_SPEC_VERSION(pR) (((pR)[15] >> 2) & 0x0F)
++#define MMC_SPEC_1_0_TO_1_2 0x00
++#define MMC_SPEC_1_4 0x01
++#define MMC_SPEC_2_0_TO_2_2 0x02
++#define MMC_SPEC_3_1 0x03
++#define MMC_SPEC_4_0_TO_4_1 0x04
++
++#define MMC_CMD_SWITCH 6
++#define MMC_CMD8 8
++
++#define MMC_SWITCH_CMD_SET 0
++#define MMC_SWITCH_SET_BITS 1
++#define MMC_SWITCH_CLEAR_BITS 2
++#define MMC_SWITCH_WRITE_BYTE 3
++#define MMC_SWITCH_CMD_SET0 0
++#define MMC_SWITCH_BUILD_ARG(cmdset,access,index,value) \
++ (((cmdset) & 0x07) | (((access) & 0x03) << 24) | (((index) & 0xFF) << 16) | (((value) & 0xFF) << 8))
++
++#define MMC_EXT_CSD_SIZE 512
++
++#define MMC_EXT_S_CMD_SET_OFFSET 504
++#define MMC_EXT_MIN_PERF_W_8_52_OFFSET 210
++#define MMC_EXT_MIN_PERF_R_8_52_OFFSET 209
++#define MMC_EXT_MIN_PERF_W_8_26_4_52_OFFSET 208
++#define MMC_EXT_MIN_PERF_R_8_26_4_52_OFFSET 207
++#define MMC_EXT_MIN_PERF_W_4_26_OFFSET 206
++#define MMC_EXT_MIN_PERF_R_4_56_OFFSET 205
++#define MMC_EXT_PWR_CL_26_360_OFFSET 203
++#define MMC_EXT_PWR_CL_52_360_OFFSET 202
++#define MMC_EXT_PWR_CL_26_195_OFFSET 201
++#define MMC_EXT_PWR_CL_52_195_OFFSET 200
++#define MMC_EXT_GET_PWR_CLASS(reg) ((reg) & 0xF)
++#define MMC_EXT_MAX_PWR_CLASSES 16
++#define MMC_EXT_CARD_TYPE_OFFSET 196
++#define MMC_EXT_CARD_TYPE_HS_52 (1 << 1)
++#define MMC_EXT_CARD_TYPE_HS_26 (1 << 0)
++#define MMC_EXT_CSD_VER_OFFSET 194
++#define MMC_EXT_VER_OFFSET 192
++#define MMC_EXT_VER_1_0 0
++#define MMC_EXT_VER_1_1 1
++#define MMC_EXT_CMD_SET_OFFSET 191
++#define MMC_EXT_CMD_SET_REV_OFFSET 189
++#define MMC_EXT_PWR_CLASS_OFFSET 187
++#define MMC_EXT_HS_TIMING_OFFSET 185
++#define MMC_EXT_HS_TIMING_ENABLE 0x01
++#define MMC_EXT_BUS_WIDTH_OFFSET 183
++#define MMC_EXT_BUS_WIDTH_1_BIT 0x00
++#define MMC_EXT_BUS_WIDTH_4_BIT 0x01
++#define MMC_EXT_BUS_WIDTH_8_BIT 0x02
++
++#endif
+Index: linux-2.6.22/include/linux/sdio/sdio_busdriver.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/sdio_busdriver.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1431 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_busdriver.h
++
++ at abstract: include file for registration of SDIO function drivers
++ and SDIO host controller bus drivers.
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_BUSDRIVER_H___
++#define __SDIO_BUSDRIVER_H___
++
++typedef UINT8 CT_VERSION_CODE;
++#define CT_SDIO_STACK_VERSION_CODE ((CT_VERSION_CODE)0x27) /* version code that must be set in various structures */
++#define CT_SDIO_STACK_VERSION_MAJOR(v) (((v) & 0xF0) >> 4)
++#define CT_SDIO_STACK_VERSION_MINOR(v) (((v) & 0x0F))
++#define SET_SDIO_STACK_VERSION(p) (p)->Version = CT_SDIO_STACK_VERSION_CODE
++#define GET_SDIO_STACK_VERSION(p) (p)->Version
++#define GET_SDIO_STACK_VERSION_MAJOR(p) CT_SDIO_STACK_VERSION_MAJOR(GET_SDIO_STACK_VERSION(p))
++#define GET_SDIO_STACK_VERSION_MINOR(p) CT_SDIO_STACK_VERSION_MINOR(GET_SDIO_STACK_VERSION(p))
++#include "sdlist.h"
++
++/* card flags */
++typedef UINT16 CARD_INFO_FLAGS;
++#define CARD_MMC 0x0001 /* Multi-media card */
++#define CARD_SD 0x0002 /* SD-Memory present */
++#define CARD_SDIO 0x0004 /* SDIO present */
++#define CARD_RAW 0x0008 /* Raw card */
++#define CARD_COMBO (CARD_SD | CARD_SDIO) /* SDIO with SD */
++#define CARD_TYPE_MASK 0x000F /* card type mask */
++#define CARD_SD_WP 0x0010 /* SD WP on */
++#define CARD_PSEUDO 0x0020 /* pseudo card (internal use) */
++#define CARD_HIPWR 0x0040 /* card can use more than 200mA (SDIO 1.1 or greater)*/
++#define GET_CARD_TYPE(flags) ((flags) & CARD_TYPE_MASK)
++
++/* bus mode and clock rate */
++typedef UINT32 SD_BUSCLOCK_RATE; /* clock rate in hz */
++typedef UINT16 SD_BUSMODE_FLAGS;
++#define SDCONFIG_BUS_WIDTH_RESERVED 0x00
++#define SDCONFIG_BUS_WIDTH_SPI 0x01
++#define SDCONFIG_BUS_WIDTH_1_BIT 0x02
++#define SDCONFIG_BUS_WIDTH_4_BIT 0x03
++#define SDCONFIG_BUS_WIDTH_MMC8_BIT 0x04
++#define SDCONFIG_BUS_WIDTH_MASK 0x0F
++#define SDCONFIG_SET_BUS_WIDTH(flags,width) \
++{ \
++ (flags) &= ~SDCONFIG_BUS_WIDTH_MASK; \
++ (flags) |= (width); \
++}
++#define SDCONFIG_GET_BUSWIDTH(flags) ((flags) & SDCONFIG_BUS_WIDTH_MASK)
++#define SDCONFIG_BUS_MODE_SPI_NO_CRC 0x40 /* SPI bus is operating with NO CRC */
++#define SDCONFIG_BUS_MODE_SD_HS 0x80 /* set interface to SD high speed mode */
++#define SDCONFIG_BUS_MODE_MMC_HS 0x20 /* set interface to MMC high speed mode */
++
++typedef UINT16 SD_SLOT_CURRENT; /* slot current in mA */
++
++typedef UINT8 SLOT_VOLTAGE_MASK; /* slot voltage */
++#define SLOT_POWER_3_3V 0x01
++#define SLOT_POWER_3_0V 0x02
++#define SLOT_POWER_2_8V 0x04
++#define SLOT_POWER_2_0V 0x08
++#define SLOT_POWER_1_8V 0x10
++#define SLOT_POWER_1_6V 0x20
++
++#define MAX_CARD_RESPONSE_BYTES 17
++
++/* plug and play information for SD cards */
++typedef struct _SD_PNP_INFO {
++ UINT16 SDIO_ManufacturerCode; /* JEDEC Code */
++ UINT16 SDIO_ManufacturerID; /* manf-specific ID */
++ UINT8 SDIO_FunctionNo; /* function number 1-7 */
++ UINT8 SDIO_FunctionClass; /* function class */
++ UINT8 SDMMC_ManfacturerID; /* card CID's MANF-ID */
++ UINT16 SDMMC_OEMApplicationID; /* card CID's OEMAPP-ID */
++ CARD_INFO_FLAGS CardFlags; /* card flags */
++}SD_PNP_INFO, *PSD_PNP_INFO;
++
++#define IS_LAST_SDPNPINFO_ENTRY(id)\
++ (((id)->SDIO_ManufacturerCode == 0) &&\
++ ((id)->SDIO_ManufacturerID == 0) &&\
++ ((id)->SDIO_FunctionNo == 0) &&\
++ ((id)->SDIO_FunctionClass == 0) &&\
++ ((id)->SDMMC_OEMApplicationID == 0) && \
++ ((id)->CardFlags == 0))
++
++/* card properties */
++typedef struct _CARD_PROPERTIES {
++ UINT8 IOFnCount; /* number of I/O functions */
++ UINT8 SDIORevision; /* SDIO revision */
++#define SDIO_REVISION_1_00 0x00
++#define SDIO_REVISION_1_10 0x01
++#define SDIO_REVISION_1_20 0x02
++ UINT8 SD_MMC_Revision; /* SD or MMC revision */
++#define SD_REVISION_1_01 0x00
++#define SD_REVISION_1_10 0x01
++#define MMC_REVISION_1_0_2_2 0x00
++#define MMC_REVISION_3_1 0x01
++#define MMC_REVISION_4_0 0x02
++ UINT16 SDIO_ManufacturerCode; /* JEDEC Code */
++ UINT16 SDIO_ManufacturerID; /* manf-specific ID */
++ UINT32 CommonCISPtr; /* common CIS ptr */
++ UINT16 RCA; /* relative card address */
++ UINT8 SDIOCaps; /* SDIO card capabilities (refer to SDIO spec for decoding) */
++ UINT8 CardCSD[MAX_CARD_RESPONSE_BYTES]; /* for SD/MMC cards */
++ CARD_INFO_FLAGS Flags; /* card flags */
++ SD_BUSCLOCK_RATE OperBusClock; /* operational bus clock (based on HCD limit)*/
++ SD_BUSMODE_FLAGS BusMode; /* current card bus mode */
++ UINT16 OperBlockLenLimit; /* operational bytes per block length limit*/
++ UINT16 OperBlockCountLimit; /* operational number of blocks per transfer limit */
++ UINT8 CardState; /* card state flags */
++ SLOT_VOLTAGE_MASK CardVoltage; /* card operational voltage */
++#define CARD_STATE_REMOVED 0x01
++}CARD_PROPERTIES, *PCARD_PROPERTIES;
++
++/* SDREQUEST request flags */
++typedef UINT32 SDREQUEST_FLAGS;
++/* write operation */
++#define SDREQ_FLAGS_DATA_WRITE 0x8000
++/* has data (read or write) */
++#define SDREQ_FLAGS_DATA_TRANS 0x4000
++/* command is an atomic APP command, requiring CMD55 to be issued */
++#define SDREQ_FLAGS_APP_CMD 0x2000
++/* transfer should be handled asynchronously */
++#define SDREQ_FLAGS_TRANS_ASYNC 0x1000
++/* host should skip the SPI response filter for this command */
++#define SDREQ_FLAGS_RESP_SKIP_SPI_FILT 0x0800
++/* host should skip the response check for this data transfer */
++#define SDREQ_FLAGS_DATA_SKIP_RESP_CHK 0x0400
++/* flag requesting a CMD12 be automatically issued by host controller */
++#define SDREQ_FLAGS_AUTO_CMD12 0x0200
++/* flag indicating that the data buffer meets HCD's DMA restrictions */
++#define SDREQ_FLAGS_DATA_DMA 0x0010
++/* indicate to host that this is a short and quick transfer, the HCD may optimize
++ * this request to reduce interrupt overhead */
++#define SDREQ_FLAGS_DATA_SHORT_TRANSFER 0x00010000
++/* indicate to the host that this is a raw request */
++#define SDREQ_FLAGS_RAW 0x00020000
++/* auto data transfer status check for MMC and Memory cards */
++#define SDREQ_FLAGS_AUTO_TRANSFER_STATUS 0x00100000
++
++#define SDREQ_FLAGS_UNUSED1 0x00200000
++#define SDREQ_FLAGS_UNUSED2 0x00400000
++#define SDREQ_FLAGS_UNUSED3 0x00800000
++#define SDREQ_FLAGS_UNUSED4 0x01000000
++#define SDREQ_FLAGS_UNUSED5 0x02000000
++
++/* the following flags are internal use only */
++#define SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE 0x0100
++/* flag indicating that response has been converted (internal use) */
++#define SDREQ_FLAGS_RESP_SPI_CONVERTED 0x0040
++/* request was cancelled - internal use only */
++#define SDREQ_FLAGS_CANCELED 0x0020
++/* a barrier operation */
++#define SDREQ_FLAGS_BARRIER 0x00040000
++/* a pseudo bus request */
++#define SDREQ_FLAGS_PSEUDO 0x00080000
++/* queue to the head */
++#define SDREQ_FLAGS_QUEUE_HEAD 0x04000000
++
++#define SDREQ_FLAGS_I_UNUSED1 0x08000000
++#define SDREQ_FLAGS_I_UNUSED2 0x10000000
++#define SDREQ_FLAGS_I_UNUSED3 0x20000000
++#define SDREQ_FLAGS_I_UNUSED4 0x40000000
++#define SDREQ_FLAGS_I_UNUSED5 0x80000000
++
++/* response type mask */
++#define SDREQ_FLAGS_RESP_MASK 0x000F
++#define GET_SDREQ_RESP_TYPE(flags) ((flags) & SDREQ_FLAGS_RESP_MASK)
++#define IS_SDREQ_WRITE_DATA(flags) ((flags) & SDREQ_FLAGS_DATA_WRITE)
++#define IS_SDREQ_DATA_TRANS(flags) ((flags) & SDREQ_FLAGS_DATA_TRANS)
++#define IS_SDREQ_RAW(flags) ((flags) & SDREQ_FLAGS_RAW)
++#define IS_SDREQ_FORCE_DEFERRED_COMPLETE(flags) ((flags) & SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE)
++#define SDREQ_FLAGS_NO_RESP 0x0000
++#define SDREQ_FLAGS_RESP_R1 0x0001
++#define SDREQ_FLAGS_RESP_R1B 0x0002
++#define SDREQ_FLAGS_RESP_R2 0x0003
++#define SDREQ_FLAGS_RESP_R3 0x0004
++#define SDREQ_FLAGS_RESP_MMC_R4 0x0005 /* not supported, for future use */
++#define SDREQ_FLAGS_RESP_MMC_R5 0x0006 /* not supported, for future use */
++#define SDREQ_FLAGS_RESP_R6 0x0007
++#define SDREQ_FLAGS_RESP_SDIO_R4 0x0008
++#define SDREQ_FLAGS_RESP_SDIO_R5 0x0009
++
++struct _SDREQUEST;
++struct _SDFUNCTION;
++
++typedef void (*PSDEQUEST_COMPLETION)(struct _SDREQUEST *);
++
++/* defines SD/MMC and SDIO requests for the RAW-mode API */
++typedef struct _SDREQUEST {
++ SDLIST SDList; /* internal use list*/
++ UINT32 Argument; /* SD/SDIO/MMC 32 bit argument */
++ SDREQUEST_FLAGS Flags; /* request flags */
++ ATOMIC_FLAGS InternalFlags; /* internal use flags */
++ UINT8 Command; /* SD/SDIO/MMC 8 bit command */
++ UINT8 Response[MAX_CARD_RESPONSE_BYTES]; /* buffer for CMD response */
++ UINT16 BlockCount; /* number of blocks to send/rcv */
++ UINT16 BlockLen; /* length of each block */
++ UINT16 DescriptorCount; /* number of DMA descriptor entries in pDataBuffer if DMA */
++ PVOID pDataBuffer; /* starting address of buffer (or ptr to PSDDMA_DESCRIPTOR*/
++ UINT32 DataRemaining; /* number of bytes remaining in the transfer (internal use) */
++ PVOID pHcdContext; /* internal use context */
++ PSDEQUEST_COMPLETION pCompletion; /* function driver completion routine */
++ PVOID pCompleteContext; /* function driver completion context */
++ SDIO_STATUS Status; /* completion status */
++ struct _SDFUNCTION* pFunction; /* function driver that generated request (internal use)*/
++ INT RetryCount; /* number of times to retry on error, non-data cmds only */
++ PVOID pBdRsv1; /* reserved */
++ PVOID pBdRsv2;
++ PVOID pBdRsv3;
++}SDREQUEST, *PSDREQUEST;
++
++ /* a request queue */
++typedef struct _SDREQUESTQUEUE {
++ SDLIST Queue; /* the queue of requests */
++ BOOL Busy; /* busy flag */
++}SDREQUESTQUEUE, *PSDREQUESTQUEUE;
++
++
++typedef UINT16 SDCONFIG_COMMAND;
++/* SDCONFIG request flags */
++/* get operation */
++#define SDCONFIG_FLAGS_DATA_GET 0x8000
++/* put operation */
++#define SDCONFIG_FLAGS_DATA_PUT 0x4000
++/* host controller */
++#define SDCONFIG_FLAGS_HC_CONFIG 0x2000
++/* both */
++#define SDCONFIG_FLAGS_DATA_BOTH (SDCONFIG_FLAGS_DATA_GET | SDCONFIG_FLAGS_DATA_PUT)
++/* no data */
++#define SDCONFIG_FLAGS_DATA_NONE 0x0000
++
++/* SDCONFIG commands */
++#define SDCONFIG_GET_HCD_DEBUG (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_GET | 275)
++#define SDCONFIG_SET_HCD_DEBUG (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_PUT | 276)
++
++/* custom hcd commands */
++#define SDCONFIG_GET_HOST_CUSTOM (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_GET | 300)
++#define SDCONFIG_PUT_HOST_CUSTOM (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_PUT | 301)
++
++/* function commands */
++#define SDCONFIG_FUNC_ENABLE_DISABLE (SDCONFIG_FLAGS_DATA_PUT | 18)
++#define SDCONFIG_FUNC_UNMASK_IRQ (SDCONFIG_FLAGS_DATA_NONE | 21)
++#define SDCONFIG_FUNC_MASK_IRQ (SDCONFIG_FLAGS_DATA_NONE | 22)
++#define SDCONFIG_FUNC_ACK_IRQ (SDCONFIG_FLAGS_DATA_NONE | 23)
++#define SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC (SDCONFIG_FLAGS_DATA_NONE | 24)
++#define SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC (SDCONFIG_FLAGS_DATA_NONE | 25)
++#define SDCONFIG_FUNC_ALLOC_SLOT_CURRENT (SDCONFIG_FLAGS_DATA_PUT | 26)
++#define SDCONFIG_FUNC_FREE_SLOT_CURRENT (SDCONFIG_FLAGS_DATA_NONE | 27)
++#define SDCONFIG_FUNC_CHANGE_BUS_MODE (SDCONFIG_FLAGS_DATA_BOTH | 28)
++#define SDCONFIG_FUNC_CHANGE_BUS_MODE_ASYNC (SDCONFIG_FLAGS_DATA_BOTH | 29)
++#define SDCONFIG_FUNC_NO_IRQ_PEND_CHECK (SDCONFIG_FLAGS_DATA_NONE | 30)
++
++typedef UINT8 FUNC_ENABLE_DISABLE_FLAGS;
++typedef UINT32 FUNC_ENABLE_TIMEOUT;
++
++ /* function enable */
++typedef struct _SDCONFIG_FUNC_ENABLE_DISABLE_DATA {
++#define SDCONFIG_DISABLE_FUNC 0x0000
++#define SDCONFIG_ENABLE_FUNC 0x0001
++ FUNC_ENABLE_DISABLE_FLAGS EnableFlags; /* enable flags*/
++ FUNC_ENABLE_TIMEOUT TimeOut; /* timeout in milliseconds */
++ void (*pOpComplete)(PVOID Context, SDIO_STATUS status); /* reserved */
++ PVOID pOpCompleteContext; /* reserved */
++}SDCONFIG_FUNC_ENABLE_DISABLE_DATA, *PSDCONFIG_FUNC_ENABLE_DISABLE_DATA;
++
++ /* slot current allocation data */
++typedef struct _SDCONFIG_FUNC_SLOT_CURRENT_DATA {
++ SD_SLOT_CURRENT SlotCurrent; /* slot current to request in mA*/
++}SDCONFIG_FUNC_SLOT_CURRENT_DATA, *PSDCONFIG_FUNC_SLOT_CURRENT_DATA;
++
++/* slot bus mode configuration */
++typedef struct _SDCONFIG_BUS_MODE_DATA {
++ SD_BUSCLOCK_RATE ClockRate; /* clock rate in Hz */
++ SD_BUSMODE_FLAGS BusModeFlags; /* bus mode flags */
++ SD_BUSCLOCK_RATE ActualClockRate; /* actual rate in KHz */
++}SDCONFIG_BUS_MODE_DATA, *PSDCONFIG_BUS_MODE_DATA;
++
++/* defines configuration requests for the HCD */
++typedef struct _SDCONFIG {
++ SDCONFIG_COMMAND Cmd; /* configuration command */
++ PVOID pData; /* configuration data */
++ INT DataLength; /* config data length */
++}SDCONFIG, *PSDCONFIG;
++
++#define SET_SDCONFIG_CMD_INFO(pHdr,cmd,pC,len) \
++{ \
++ (pHdr)->Cmd = (cmd); \
++ (pHdr)->pData = (PVOID)(pC); \
++ (pHdr)->DataLength = (len); \
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a pointer to the configuration command data.
++
++ @function name: GET_SDCONFIG_CMD
++ @prototype: UNIT16 GET_SDCONFIG_CMD (PSDCONFIG pCommand)
++ @category: HD_Reference
++
++ @input: pCommand - config command structure.
++
++ @return: command code
++
++ @notes: Implemented as a macro. This macro returns the command code for this
++ configuration request.
++
++ @example: getting the command code:
++ cmd = GET_SDCONFIG_CMD(pConfig);
++ switch (cmd) {
++ case SDCONFIG_GET_WP:
++ .. get write protect switch position
++ break;
++ ...
++ }
++
++ @see also: GET_SDCONFIG_CMD_LEN, GET_SDCONFIG_CMD_DATA
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define GET_SDCONFIG_CMD(pBuffer) ((pBuffer)->Cmd)
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a pointer to the configuration command data.
++
++ @function name: GET_SDCONFIG_CMD_LEN
++ @prototype: INT GET_SDCONFIG_CMD_LEN (PSDCONFIG pCommand)
++ @category: HD_Reference
++
++ @input: pCommand - config command structure.
++
++ @return: length of config command data
++
++ @notes: Implemented as a macro. Host controller drivers can use this macro to extract
++ the number of bytes of command specific data. This can be used to validate the
++ config data buffer size.
++
++ @example: getting the data length:
++ length = GET_SDCONFIG_CMD_LEN(pConfig);
++ if (length < CUSTOM_COMMAND_XXX_SIZE) {
++ ... invalid length
++ }
++
++ @see also: GET_SDCONFIG_CMD, GET_SDCONFIG_CMD_DATA
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define GET_SDCONFIG_CMD_LEN(pBuffer) ((pBuffer)->DataLength)
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a pointer to the configuration command data.
++
++ @function name: GET_SDCONFIG_CMD_DATA
++ @prototype: (casted ptr) GET_SDCONFIG_CMD_DATA (type, PSDCONFIG pCommand)
++ @category: HD_Reference
++
++ @input: type - pointer type to cast the returned pointer to.
++ pCommand - config command structure.
++
++ @return: type-casted pointer to the command's data
++
++ @notes: Implemented as a macro. Host controller drivers can use this macro to extract
++ a pointer to the command specific data in an HCD configuration request.
++
++ @example: getting the pointer:
++ // get interrupt control data
++ pIntControl = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig);
++ if (pIntControl->SlotIRQEnable) {
++ ... enable slot IRQ detection
++ }
++
++ @see also: GET_SDCONFIG_CMD, GET_SDCONFIG_CMD_LEN
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define GET_SDCONFIG_CMD_DATA(type,pBuffer) ((type)((pBuffer)->pData))
++#define IS_SDCONFIG_CMD_GET(pBuffer) ((pBuffer)->Cmd & SDCONFIG_FLAGS_DATA_GET)
++#define IS_SDCONFIG_CMD_PUT(pBuffer) ((pBuffer)->Cmd & SDCONFIG_FLAGS_DATA_PUT)
++
++struct _SDDEVICE;
++struct _SDHCD;
++
++typedef UINT8 SD_FUNCTION_FLAGS;
++#define SDFUNCTION_FLAG_REMOVING 0x01
++
++/* function driver registration structure */
++typedef struct _SDFUNCTION {
++ CT_VERSION_CODE Version; /* version code of the SDIO stack */
++ SDLIST SDList; /* internal use list*/
++ PTEXT pName; /* name of registering driver */
++ UINT MaxDevices; /* maximum number of devices supported by this function */
++ UINT NumDevices; /* number of devices supported by this function */
++ PSD_PNP_INFO pIds; /* null terminated table of supported devices*/
++ BOOL (*pProbe)(struct _SDFUNCTION *pFunction, struct _SDDEVICE *pDevice);/* New device inserted */
++ /* Device removed (NULL if not a hot-plug capable driver) */
++ void (*pRemove)(struct _SDFUNCTION *pFunction, struct _SDDEVICE *pDevice);
++ SDIO_STATUS (*pSuspend)(struct _SDFUNCTION *pFunction, SDPOWER_STATE state); /* Device suspended */
++ SDIO_STATUS (*pResume)(struct _SDFUNCTION *pFunction); /* Device woken up */
++ /* Enable wake event */
++ SDIO_STATUS (*pWake) (struct _SDFUNCTION *pFunction, SDPOWER_STATE state, BOOL enable);
++ PVOID pContext; /* function driver use data */
++ OS_PNPDRIVER Driver; /* driver registration with base system */
++ SDLIST DeviceList; /* the list of devices this driver is using*/
++ OS_SIGNAL CleanupReqSig; /* wait for requests completion on cleanup (internal use) */
++ SD_FUNCTION_FLAGS Flags; /* internal flags (internal use) */
++}SDFUNCTION, *PSDFUNCTION;
++
++typedef UINT8 HCD_EVENT;
++
++ /* device info for SDIO functions */
++typedef struct _SDIO_DEVICE_INFO {
++ UINT32 FunctionCISPtr; /* function's CIS ptr */
++ UINT32 FunctionCSAPtr; /* function's CSA ptr */
++ UINT16 FunctionMaxBlockSize; /* function's reported max block size */
++}SDIO_DEVICE_INFO, *PSDIO_DEVICE_INFO;
++
++ /* device info for SD/MMC card functions */
++typedef struct _SDMMC_INFO{
++ UINT8 Unused; /* reserved */
++}SDMMC_INFO, *PSDMMC_INFO;
++
++ /* union of SDIO function and device info */
++typedef union _SDDEVICE_INFO {
++ SDIO_DEVICE_INFO AsSDIOInfo;
++ SDMMC_INFO AsSDMMCInfo;
++}SDDEVICE_INFO, *PSDDEVICE_INFO;
++
++
++typedef UINT8 SD_DEVICE_FLAGS;
++#define SDDEVICE_FLAG_REMOVING 0x01
++
++/* inserted device description, describes an inserted card */
++typedef struct _SDDEVICE {
++ SDLIST SDList; /* internal use list*/
++ SDLIST FuncListLink; /* internal use list */
++ /* read/write request function */
++ SDIO_STATUS (*pRequest)(struct _SDDEVICE *pDev, PSDREQUEST req);
++ /* get/set configuration */
++ SDIO_STATUS (*pConfigure)(struct _SDDEVICE *pDev, PSDCONFIG config);
++ PSDREQUEST (*AllocRequest)(struct _SDDEVICE *pDev); /* allocate a request */
++ void (*FreeRequest)(struct _SDDEVICE *pDev, PSDREQUEST pReq); /* free the request */
++ void (*pIrqFunction)(PVOID pContext); /* interrupt routine, synchronous calls allowed */
++ void (*pIrqAsyncFunction)(PVOID pContext); /* async IRQ function , asynch only calls */
++ PVOID IrqContext; /* irq context */
++ PVOID IrqAsyncContext; /* irq async context */
++ PSDFUNCTION pFunction; /* function driver supporting this device */
++ struct _SDHCD *pHcd; /* host controller this device is on (internal use) */
++ SDDEVICE_INFO DeviceInfo; /* device info */
++ SD_PNP_INFO pId[1]; /* id of this device */
++ OS_PNPDEVICE Device; /* device registration with base system */
++ SD_SLOT_CURRENT SlotCurrentAlloc; /* allocated slot current for this device/function (internal use) */
++ SD_DEVICE_FLAGS Flags; /* internal use flags */
++ CT_VERSION_CODE Version; /* version code of the bus driver */
++}SDDEVICE, *PSDDEVICE;
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get SDIO Bus Driver Version Major number
++
++ @function name: SDDEVICE_GET_VERSION_MAJOR
++ @prototype: INT SDDEVICE_GET_VERSION_MAJOR(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: integer value for the major version
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_VERSION_MINOR
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_VERSION_MAJOR(pDev) (GET_SDIO_STACK_VERSION_MAJOR(pDev))
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get SDIO Bus Driver Version Minor number
++
++ @function name: SDDEVICE_GET_VERSION_MINOR
++ @prototype: INT SDDEVICE_GET_VERSION_MINOR(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: integer value for the minor version
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_VERSION_MAJOR
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_VERSION_MINOR(pDev) (GET_SDIO_STACK_VERSION_MINOR(pDev))
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Test the SDIO revision for greater than or equal to 1.10
++
++ @function name: SDDEVICE_IS_SDIO_REV_GTEQ_1_10
++ @prototype: BOOL SDDEVICE_IS_SDIO_REV_GTEQ_1_10(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE if the revision is greater than or equal to 1.10
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_IS_SD_REV_GTEQ_1_10
++ @see also: SDDEVICE_IS_MMC_REV_GTEQ_4_0
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_SDIO_REV_GTEQ_1_10(pDev) ((pDev)->pHcd->CardProperties.SDIORevision >= SDIO_REVISION_1_10)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Test the SDIO revision for greater than or equal to 1.20
++
++ @function name: SDDEVICE_IS_SDIO_REV_GTEQ_1_20
++ @prototype: BOOL SDDEVICE_IS_SDIO_REV_GTEQ_1_20(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE if the revision is greater than or equal to 1.20
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_IS_SD_REV_GTEQ_1_10
++ @see also: SDDEVICE_IS_SDIO_REV_GTEQ_1_10
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_SDIO_REV_GTEQ_1_20(pDev) ((pDev)->pHcd->CardProperties.SDIORevision >= SDIO_REVISION_1_20)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Test the SD revision for greater than or equal to 1.10
++
++ @function name: SDDEVICE_IS_SD_REV_GTEQ_1_10
++ @prototype: BOOL SDDEVICE_IS_SD_REV_GTEQ_1_10(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE if the revision is greater than or equal to 1.10
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_IS_SDIO_REV_GTEQ_1_10
++ @see also: SDDEVICE_IS_MMC_REV_GTEQ_4_0
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_SD_REV_GTEQ_1_10(pDev) ((pDev)->pHcd->CardProperties.SD_MMC_Revision >= SD_REVISION_1_10)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Test the MMC revision for greater than or equal to 4.0
++
++ @function name: SDDEVICE_IS_MMC_REV_GTEQ_4_0
++ @prototype: BOOL SDDEVICE_IS_MMC_REV_GTEQ_4_0(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE if the revision is greater than or equal to 4.0
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_IS_SDIO_REV_GTEQ_1_10
++ @see also: SDDEVICE_IS_SD_REV_GTEQ_1_10
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_MMC_REV_GTEQ_4_0(pDev) ((pDev)->pHcd->CardProperties.SD_MMC_Revision >= MMC_REVISION_4_0)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Test for write protect enabled
++
++ @function name: SDDEVICE_IS_CARD_WP_ON
++ @prototype: BOOL SDDEVICE_IS_CARD_WP_ON(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE if device is write protected.
++
++ @notes: Implemented as a macro.
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_CARD_WP_ON(pDev) ((pDev)->pHcd->CardProperties.Flags & CARD_SD_WP)
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the device's manufacturer specific ID
++
++ @function name: SDDEVICE_GET_SDIO_MANFID
++ @prototype: UINT16 SDDEVICE_GET_SDIO_MANFID(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: function number
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_MANFCODE
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_MANFID(pDev) (pDev)->pId[0].SDIO_ManufacturerID
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the device's manufacturer code
++
++ @function name: SDDEVICE_GET_SDIO_MANFCODE
++ @prototype: UINT16 SDDEVICE_GET_SDIO_MANFCODE(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: function number
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_MANFID
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_MANFCODE(pDev) (pDev)->pId[0].SDIO_ManufacturerCode
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the device's function number
++
++ @function name: SDDEVICE_GET_SDIO_FUNCNO
++ @prototype: UINT8 SDDEVICE_GET_SDIO_FUNCNO(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: function number
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_FUNC_CLASS
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_FUNCNO(pDev) (pDev)->pId[0].SDIO_FunctionNo
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the functions's class
++
++ @function name: SDDEVICE_GET_SDIO_FUNC_CLASS
++ @prototype: UINT8 SDDEVICE_GET_SDIO_FUNC_CLASS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: class number
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_FUNCNO
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_FUNC_CLASS(pDev) (pDev)->pId[0].SDIO_FunctionClass
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the functions's Card Information Structure pointer
++
++ @function name: SDDEVICE_GET_SDIO_FUNC_CISPTR
++ @prototype: UINT32 SDDEVICE_GET_SDIO_FUNC_CISPTR(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: CIS offset
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_FUNC_CSAPTR
++ @see also: SDDEVICE_GET_SDIO_COMMON_CISPTR
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_FUNC_CISPTR(pDev)(pDev)->DeviceInfo.AsSDIOInfo.FunctionCISPtr
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the functions's Code Stoarge Area pointer
++
++ @function name: SDDEVICE_GET_SDIO_FUNC_CSAPTR
++ @prototype: UINT32 SDDEVICE_GET_SDIO_FUNC_CSAPTR(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: CSA offset
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_FUNC_CISPTR
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_FUNC_CSAPTR(pDev)(pDev)->DeviceInfo.AsSDIOInfo.FunctionCSAPtr
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the functions's maximum reported block size
++
++ @function name: SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE
++ @prototype: UINT16 SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: block size
++
++ @notes: Implemented as a macro.
++
++ @see also:
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(pDev) (pDev)->DeviceInfo.AsSDIOInfo.FunctionMaxBlockSize
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the common Card Information Structure pointer
++
++ @function name: SDDEVICE_GET_SDIO_COMMON_CISPTR
++ @prototype: UINT32 SDDEVICE_GET_SDIO_COMMON_CISPTR(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: Common CIS Address (in SDIO address space)
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_SDIO_FUNC_CSAPTR
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_COMMON_CISPTR(pDev) (pDev)->pHcd->CardProperties.CommonCISPtr
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the card capabilities
++
++ @function name: SDDEVICE_GET_SDIO_CARD_CAPS
++ @prototype: UINT8 SDDEVICE_GET_SDIO_CARD_CAPS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: 8-bit card capabilities register
++
++ @notes: Implemented as a macro. Refer to SDIO spec for decoding.
++
++ @see also: SDDEVICE_GET_CARD_FLAGS
++ @see also: SDDEVICE_GET_SDIOCARD_CAPS
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIO_CARD_CAPS(pDev) (pDev)->pHcd->CardProperties.SDIOCaps
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the card flags
++
++ @function name: SDDEVICE_GET_CARD_FLAGS
++ @prototype: CARD_INFO_FLAGS SDDEVICE_GET_CARD_FLAGS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: flags
++
++ @notes: Implemented as a macro.
++
++ @example: Get card type:
++ CARD_INFO_FLAGS flags;
++ flags = SDDEVICE_GET_CARD_FLAGS(pDevice);
++ switch(GET_CARD_TYPE(flags)) {
++ case CARD_MMC: // Multi-media card
++ ...
++ case CARD_SD: // SD-Memory present
++ ...
++ case CARD_SDIO: // SDIO card present
++ ...
++ case CARD_COMBO: //SDIO card with SD
++ ...
++ }
++ if (flags & CARD_SD_WP) {
++ ...SD write protect on
++ }
++
++ @see also: SDDEVICE_GET_SDIO_CARD_CAPS
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_CARD_FLAGS(pDev) (pDev)->pHcd->CardProperties.Flags
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the Relative Card Address register
++
++ @function name: SDDEVICE_GET_CARD_RCA
++ @prototype: UINT16 SDDEVICE_GET_CARD_RCA(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: register address
++
++ @notes: Implemented as a macro. Refer to SDIO spec for decoding.
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_CARD_RCA(pDev) (pDev)->pHcd->CardProperties.RCA
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get operational bus clock
++
++ @function name: SDDEVICE_GET_OPER_CLOCK
++ @prototype: SD_BUSCLOCK_RATE SDDEVICE_GET_OPER_CLOCK(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: clock rate
++
++ @notes: Implemented as a macro. Returns the current bus clock rate.
++ This may be lower than reported by the card due to Host Controller,
++ Bus driver, or power management limitations.
++
++ @see also: SDDEVICE_GET_MAX_CLOCK
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_OPER_CLOCK(pDev) (pDev)->pHcd->CardProperties.OperBusClock
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get maximum bus clock
++
++ @function name: SDDEVICE_GET_MAX_CLOCK
++ @prototype: SD_BUSCLOCK_RATE SDDEVICE_GET_MAX_CLOCK(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: clock rate
++
++ @notes: To obtain the current maximum clock rate use SDDEVICE_GET_OPER_CLOCK().
++ This rate my be lower than the host controllers maximum obtained using
++ SDDEVICE_GET_MAX_CLOCK().
++
++ @see also: SDDEVICE_GET_OPER_CLOCK
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_MAX_CLOCK(pDev) (pDev)->pHcd->MaxClockRate
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get operational maximum block length.
++
++ @function name: SDDEVICE_GET_OPER_BLOCK_LEN
++ @prototype: UINT16 SDDEVICE_GET_OPER_BLOCK_LEN(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: block size in bytes
++
++ @notes: Implemented as a macro. Returns the maximum current block length.
++ This may be lower than reported by the card due to Host Controller,
++ Bus driver, or power management limitations.
++
++ @see also: SDDEVICE_GET_MAX_BLOCK_LEN
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_OPER_BLOCK_LEN(pDev) (pDev)->pHcd->CardProperties.OperBlockLenLimit
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get maximum block length.
++
++ @function name: SDDEVICE_GET_MAX_BLOCK_LEN
++ @prototype: UINT16 SDDEVICE_GET_MAX_BLOCK_LEN(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: block size in bytes
++
++ @notes: Implemented as a macro. Use SDDEVICE_GET_OPER_BLOCK_LEN to obtain
++ the current block length.
++
++ @see also: SDDEVICE_GET_OPER_BLOCK_LEN
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_MAX_BLOCK_LEN(pDev) (pDev)->pHcd->MaxBytesPerBlock
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get operational maximum block count.
++
++ @function name: SDDEVICE_GET_OPER_BLOCKS
++ @prototype: UINT16 SDDEVICE_GET_OPER_BLOCKS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: maximum number of blocks per transaction.
++
++ @notes: Implemented as a macro. Returns the maximum current block count.
++ This may be lower than reported by the card due to Host Controller,
++ Bus driver, or power management limitations.
++
++ @see also: SDDEVICE_GET_MAX_BLOCK_LEN
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_OPER_BLOCKS(pDev) (pDev)->pHcd->CardProperties.OperBlockCountLimit
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get maximum block count.
++
++ @function name: SDDEVICE_GET_MAX_BLOCKS
++ @prototype: UINT16 SDDEVICE_GET_MAX_BLOCKS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: maximum number of blocks per transaction.
++
++ @notes: Implemented as a macro. Use SDDEVICE_GET_OPER_BLOCKS to obtain
++ the current block count.
++
++ @see also: SDDEVICE_GET_OPER_BLOCKS
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_MAX_BLOCKS(pDev) (pDev)->pHcd->MaxBlocksPerTrans
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get applied slot voltage
++
++ @function name: SDDEVICE_GET_SLOT_VOLTAGE_MASK
++ @prototype: SLOT_VOLTAGE_MASK SDDEVICE_GET_SLOT_VOLTAGE_MASK(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: slot voltage mask
++
++ @notes: This function returns the applied voltage on the slot. The voltage value is a
++ mask having the following values:
++ SLOT_POWER_3_3V
++ SLOT_POWER_3_0V
++ SLOT_POWER_2_8V
++ SLOT_POWER_2_0V
++ SLOT_POWER_1_8V
++ SLOT_POWER_1_6V
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SLOT_VOLTAGE_MASK(pDev) (pDev)->pHcd->CardProperties.CardVoltage
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the Card Specific Data Register.
++
++ @function name: SDDEVICE_GET_CARDCSD
++ @prototype: PUINT8 SDDEVICE_GET_CARDCSD(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: UINT8 CardCSD[MAX_CARD_RESPONSE_BYTES] array of CSD data.
++
++ @notes: Implemented as a macro.
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_CARDCSD(pDev) (pDev)->pHcd->CardProperties.CardCSD
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the bus mode flags
++
++ @function name: SDDEVICE_GET_BUSMODE_FLAGS
++ @prototype: SD_BUSMODE_FLAGS SDDEVICE_GET_BUSMODE_FLAGS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return:
++
++ @notes: Implemented as a macro. This function returns the raw bus mode flags. This
++ is useful for function drivers that wish to override the bus clock without
++ modifying the current bus mode.
++
++ @see also: SDDEVICE_GET_BUSWIDTH
++ @see also: SDCONFIG_BUS_MODE_CTRL
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_BUSMODE_FLAGS(pDev) (pDev)->pHcd->CardProperties.BusMode
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the bus width.
++
++ @function name: SDDEVICE_GET_BUSWIDTH
++ @prototype: UINT8 SDDEVICE_GET_BUSWIDTH(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: bus width: SDCONFIG_BUS_WIDTH_SPI, SDCONFIG_BUS_WIDTH_1_BIT, SDCONFIG_BUS_WIDTH_4_BIT
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_IS_BUSMODE_SPI
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_BUSWIDTH(pDev) SDCONFIG_GET_BUSWIDTH((pDev)->pHcd->CardProperties.BusMode)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Is bus in SPI mode.
++
++ @function name: SDDEVICE_IS_BUSMODE_SPI
++ @prototype: BOOL SDDEVICE_IS_BUSMODE_SPI(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: TRUE, SPI mode.
++
++ @notes: Implemented as a macro.
++
++ @see also: SDDEVICE_GET_BUSWIDTH
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_IS_BUSMODE_SPI(pDev) (SDDEVICE_GET_BUSWIDTH(pDev) == SDCONFIG_BUS_WIDTH_SPI)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Send a request to a device.
++
++ @function name: SDDEVICE_CALL_REQUEST_FUNC
++ @prototype: SDIO_STATUS SDDEVICE_CALL_REQUEST_FUNC(PSDDEVICE pDevice, PSDREQUEST pRequest)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++ @input: pRequest - the request to be sent
++
++ @output: none
++
++ @return: SDIO_STATUS
++
++ @notes: Sends a request to the specified device. If the request is successfully sent, then
++ the response flags can be checked to detemine the result of the request.
++
++ @example: Example of sending a request to a device:
++ PSDREQUEST pReq = NULL;
++ //allocate a request
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ //initialize the request
++ SDLIB_SetupCMD52Request(FuncNo, Address, Write, *pData, pReq);
++ //send the request to the target
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice,pReq);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ //check the request response (based on the request type)
++ if (SD_R5_GET_RESP_FLAGS(pReq->Response) & SD_R5_ERRORS) {
++ ...
++ }
++ if (!Write) {
++ // store the byte
++ *pData = SD_R5_GET_READ_DATA(pReq->Response);
++ }
++ //free the request
++ SDDeviceFreeRequest(pDevice,pReq);
++ ...
++
++ @see also: SDDeviceAllocRequest
++ @see also: SDDEVICE_CALL_CONFIG_FUNC
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_CALL_REQUEST_FUNC(pDev,pReq) (pDev)->pRequest((pDev),(pReq))
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Send configuration to a device.
++
++ @function name: SDDEVICE_CALL_CONFIG_FUNC
++ @prototype: SDIO_STATUS SDDEVICE_CALL_CONFIG_FUNC(PSDDEVICE pDevice, PSDCONFIG pConfigure)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++ @input: pConfigure - configuration request
++
++ @output: none
++
++ @return: SDIO_STATUS
++
++ @notes: Sends a configuration request to the specified device.
++
++ @example: Example of sending a request to a device:
++ SDCONFIG configHdr;
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
++ fData.TimeOut = 500;
++ SET_SDCONFIG_CMD_INFO(&configHdr, SDCONFIG_FUNC_ENABLE_DISABLE, fData, sizeof(fData));
++ return SDDEVICE_CALL_CONFIG_FUNC(pDevice, &configHdr);
++
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_CALL_CONFIG_FUNC(pDev,pCfg) (pDev)->pConfigure((pDev),(pCfg))
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Allocate a request structure.
++
++ @function name: SDDeviceAllocRequest
++ @prototype: PSDREQUEST SDDeviceAllocRequest(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: request pointer or NULL if not available.
++
++ @notes: This function must not be called in a non-schedulable (interrupts off) context.
++ Allocating memory on some OSes may block.
++
++ @see also: SDDEVICE_CALL_REQUEST_FUNC
++ @see also: SDDeviceFreeRequest
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDeviceAllocRequest(pDev) (pDev)->AllocRequest((pDev))
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Free a request structure.
++
++ @function name: SDDeviceFreeRequest
++ @prototype: void SDDeviceFreeRequest(PSDDEVICE pDevice, PSDREQUEST pRequest)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++ @input: pRequest - request allocated by SDDeviceAllocRequest().
++
++ @output: none
++
++ @return: none
++
++ @notes: This function must not be called in a non-schedulable (interrupts off) context.
++ Freeing memory on some OSes may block.
++
++ @see also: SDDEVICE_CALL_REQUEST_FUNC
++ @see also: SDDeviceAllocRequest
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDeviceFreeRequest(pDev,pReq) (pDev)->FreeRequest((pDev),pReq)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Register an interrupt handler for a device.
++
++ @function name: SDDEVICE_SET_IRQ_HANDLER
++ @prototype: void SDDEVICE_SET_IRQ_HANDLER(PSDDEVICE pDevice,
++ void (*pIrqFunction)(PVOID pContext),
++ PVOID pContext)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++ @input: pIrqFunction - the interrupt function to execute.
++ @input: pContext - context value passed into interrupt routine.
++
++ @output: none
++
++ @return: none
++
++ @notes: The registered routine will be called upon each card interrupt.
++ The interrupt function should acknowledge the interrupt when it is
++ ready to handle more interrupts using:
++ SDLIB_IssueConfig(pDevice, SDCONFIG_FUNC_ACK_IRQ, NULL, 0);
++ The interrupt handler can perform synchronous request calls.
++
++ @see also: SDDEVICE_SET_ASYNC_IRQ_HANDLER
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_SET_IRQ_HANDLER(pDev,pFn,pContext) \
++{ \
++ (pDev)->pIrqFunction = (pFn); \
++ (pDev)->IrqContext = (PVOID)(pContext); \
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Register an asynchronous interrupt handler for a device.
++
++ @function name: SDDEVICE_SET_ASYNC_IRQ_HANDLER
++ @prototype: void SDDEVICE_SET_ASYNC_IRQ_HANDLER(PSDDEVICE pDevice,
++ void (*pIrqAsyncFunction)(PVOID pContext),
++ PVOID pContext)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++ @input: pIrqAsyncFunction - the interrupt function to execute.
++ @input: pContext - context value passed into interrupt routine.
++
++ @output: none
++
++ @return: none
++
++ @notes: The registered routine will be called upon each card interrupt.
++ The interrupt function should acknowledge the interrupt when it is
++ ready to handle more interrupts using:
++ SDLIB_IssueConfig(pDevice, SDCONFIG_FUNC_ACK_IRQ, NULL, 0);
++ The interrupt handler can not perform any synchronous request calls.
++ Using this call provides a faster interrupt dispatch, but limits all
++ requests to asynchronous mode.
++
++ @see also: SDDEVICE_SET_IRQ_HANDLER
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_SET_ASYNC_IRQ_HANDLER(pDev,pFn,pContext) \
++{ \
++ (pDev)->pIrqAsyncFunction = (pFn); \
++ (pDev)->IrqAsyncContext = (PVOID)(pContext); \
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the SDIO capabilities rgeister.
++
++ @function name: SDDEVICE_GET_SDIOCARD_CAPS
++ @prototype: UINT8 SDDEVICE_GET_SDIOCARD_CAPS(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: SD capabilities
++
++ @notes: See SD specification for decoding of these capabilities.
++
++ @see also: SDDEVICE_GET_SDIO_CARD_CAPS
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SDIOCARD_CAPS(pDev) (pDev)->pHcd->CardProperties.SDIOCaps
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get HCD driver name
++
++ @function name: SDDEVICE_GET_HCDNAME
++ @prototype: PTEXT SDDEVICE_GET_HCDNAME(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the target device for this request
++
++ @output: none
++
++ @return: pointer to a string containing the name of the underlying HCD
++
++ @notes: Implemented as a macro.
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_HCDNAME(pDev) (pDev)->pHcd->pName
++
++
++#define SDDEVICE_CALL_IRQ_HANDLER(pDev) (pDev)->pIrqFunction((pDev)->IrqContext)
++#define SDDEVICE_CALL_IRQ_ASYNC_HANDLER(pDev) (pDev)->pIrqAsyncFunction((pDev)->IrqAsyncContext)
++
++
++#define SDDEVICE_SET_SDIO_FUNCNO(pDev,Num) (pDev)->pId[0].SDIO_FunctionNo = (Num)
++#define SDDEVICE_IS_CARD_REMOVED(pDev) ((pDev)->pHcd->CardProperties.CardState & \
++ CARD_STATE_REMOVED)
++
++
++typedef enum _SDHCD_IRQ_PROC_STATE {
++ SDHCD_IDLE = 0,
++ SDHCD_IRQ_PENDING = 1,
++ SDHCD_IRQ_HELPER = 2
++}SDHCD_IRQ_PROC_STATE, *PSDHCD_IRQ_PROC_STATE;
++
++/* host controller bus driver registration structure */
++typedef struct _SDHCD {
++ CT_VERSION_CODE Version; /* version code of the SDIO stack */
++ SDLIST SDList; /* internal use list*/
++ PTEXT pName; /* name of registering host/slot driver */
++ UINT32 Attributes; /* attributes of host controller */
++ UINT16 MaxBytesPerBlock; /* max bytes per block */
++ UINT16 MaxBlocksPerTrans; /* max blocks per transaction */
++ SD_SLOT_CURRENT MaxSlotCurrent; /* max current per slot in milli-amps */
++ UINT8 SlotNumber; /* sequential slot number for this HCD, set by bus driver */
++ SD_BUSCLOCK_RATE MaxClockRate; /* max clock rate in hz */
++ SLOT_VOLTAGE_MASK SlotVoltageCaps; /* slot voltage capabilities */
++ SLOT_VOLTAGE_MASK SlotVoltagePreferred; /* preferred slot voltage */
++ PVOID pContext; /* host controller driver use data */
++ SDIO_STATUS (*pRequest)(struct _SDHCD *pHcd);
++ /* get/set configuration */
++ SDIO_STATUS (*pConfigure)(struct _SDHCD *pHcd, PSDCONFIG pConfig);
++ /* everything below this line is for bus driver use */
++ OS_SEMAPHORE ConfigureOpsSem; /* semaphore to make specific configure ops atomic, internal use */
++ OS_CRITICALSECTION HcdCritSection; /* critical section to protect hcd data structures (internal use) */
++ SDREQUESTQUEUE RequestQueue; /* request queue, internal use */
++ PSDREQUEST pCurrentRequest; /* current request we are working on */
++ CARD_PROPERTIES CardProperties; /* properties for the currently inserted card*/
++ OSKERNEL_HELPER SDIOIrqHelper; /* synch IRQ helper, internal use */
++ SDDEVICE *pPseudoDev; /* pseudo device used for initialization (internal use) */
++ UINT8 PendingHelperIrqs; /* IRQ helper pending IRQs */
++ UINT8 PendingIrqAcks; /* pending IRQ acks from function drivers */
++ UINT8 IrqsEnabled; /* current irq enabled mask */
++ SDHCD_IRQ_PROC_STATE IrqProcState; /* irq processing state */
++ POS_DEVICE pDevice; /* device registration with base system */
++ SD_SLOT_CURRENT SlotCurrentAllocated; /* slot current allocated (internal use ) */
++ ATOMIC_FLAGS HcdFlags; /* HCD Flags */
++#define HCD_REQUEST_CALL_BIT 0
++#define HCD_IRQ_NO_PEND_CHECK 1 /* HCD flag to bypass interrupt pending register
++ check, typically done on single function cards */
++ SDREQUESTQUEUE CompletedRequestQueue; /* completed request queue, internal use */
++ PSDDMA_DESCRIPTION pDmaDescription; /* description of HCD's DMA capabilities */
++ POS_MODULE pModule; /* OS-specific module information */
++ INT Recursion; /* recursion level */
++ PVOID Reserved1;
++ PVOID Reserved2;
++}SDHCD, *PSDHCD;
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a pointer to the HCD's DMA description
++
++ @function name: SDGET_DMA_DESCRIPTION
++ @prototype: PSDDMA_DESCRIPTION SDGET_DMA_DESCRIPTION(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - device structure
++
++ @return: PSDDMA_DESCRIPTION or NULL if no DMA support
++
++ @notes: Implemented as a macro.
++
++ @example: getting the current request:
++ PSDDMA_DESCRIPTION pDmaDescrp = SDGET_DMA_DESCRIPTION(pDevice);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDGET_DMA_DESCRIPTION(pDevice) (pDevice)->pHcd->pDmaDescription
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the logical slot number the device is assigned to.
++
++ @function name: SDDEVICE_GET_SLOT_NUMBER
++ @prototype: UINT8 SDDEVICE_GET_SLOT_NUMBER(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - device structure
++
++ @return: unsigned number representing the slot number
++
++ @notes: Implemented as a macro. This value is unique for each physical slot in the system
++ and assigned by the bus driver. Devices on a multi-function card will share the same
++ slot number.
++
++ @example: getting the slot number:
++ UINT8 thisSlot = SDDEVICE_GET_SLOT_NUMBER(pDevice);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDDEVICE_GET_SLOT_NUMBER(pDevice) (pDevice)->pHcd->SlotNumber
++
++/* for function use */
++SDIO_STATUS SDIO_RegisterFunction(PSDFUNCTION pFunction);
++SDIO_STATUS SDIO_UnregisterFunction(PSDFUNCTION pFunction);
++
++#include "sdio_hcd_defs.h"
++#endif /* __SDIO_BUSDRIVER_H___ */
+Index: linux-2.6.22/drivers/Kconfig
+===================================================================
+--- linux-2.6.22.orig/drivers/Kconfig 2007-11-08 15:42:31.000000000 +0100
++++ linux-2.6.22/drivers/Kconfig 2007-11-08 15:47:58.000000000 +0100
+@@ -68,6 +68,8 @@
+
+ source "drivers/usb/Kconfig"
+
++source "drivers/sdio/Kconfig"
++
+ source "drivers/mmc/Kconfig"
+
+ source "drivers/leds/Kconfig"
+Index: linux-2.6.22/drivers/sdio/Kconfig
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/Kconfig 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,18 @@
++#
++# SDIO driver and host controller support
++#
++
++menu "SDIO support"
++
++config SDIO
++ tristate "SDIO support"
++ default m
++ ---help---
++ good luck.
++
++source "drivers/sdio/hcd/Kconfig"
++
++source "drivers/sdio/function/Kconfig"
++
++endmenu
++
+Index: linux-2.6.22/drivers/sdio/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/Makefile 2007-11-08 17:28:12.000000000 +0100
+@@ -0,0 +1,6 @@
++#Makefile for SDIO stack
++obj-$(CONFIG_SDIO) += lib/
++obj-$(CONFIG_SDIO) += busdriver/
++obj-$(CONFIG_SDIO) += hcd/
++obj-$(CONFIG_SDIO) += function/
++
+Index: linux-2.6.22/drivers/sdio/lib/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/lib/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,6 @@
++#
++# SDIO stack library Makefile
++#
++obj-$(CONFIG_SDIO) += sdio_lib.o
++sdio_lib-objs := sdio_lib_c.o sdio_lib_os.o
++
+Index: linux-2.6.22/drivers/sdio/lib/sdio_lib_c.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/lib/sdio_lib_c.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,903 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_lib_c.c
++
++ at abstract: OS independent SDIO library functions
++ at category abstract: Support_Reference Support Functions.
++
++ at notes: Support functions for device I/O
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDLIB_
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++
++#define _Cmd52WriteByteCommon(pDev, Address, pValue) \
++ _SDLIB_IssueCMD52((pDev),0,(Address),(pValue),1,TRUE)
++#define _Cmd52ReadByteCommon(pDev, Address, pValue) \
++ _SDLIB_IssueCMD52((pDev),0,(Address),pValue,1,FALSE)
++#define _Cmd52ReadMultipleCommon(pDev, Address, pBuf,length) \
++ _SDLIB_IssueCMD52((pDev),0,(Address),(pBuf),(length),FALSE)
++
++/* inline version */
++static INLINE void _iSDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest) {
++ if (Write) {
++ SDIO_SET_CMD52_ARG(pRequest->Argument,CMD52_WRITE,
++ FuncNo,
++ CMD52_NORMAL_WRITE,Address,WriteData);
++ } else {
++ SDIO_SET_CMD52_ARG(pRequest->Argument,CMD52_READ,FuncNo,0,Address,0x00);
++ }
++
++ pRequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5;
++ pRequest->Command = CMD52;
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Setup cmd52 requests
++
++ @function name: SDLIB_SetupCMD52Request
++ @prototype: void SDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest)
++ @category: PD_Reference
++
++ @input: FunctionNo - function number.
++ @input: Address - I/O address, 17-bit register address.
++ @input: Write - TRUE if a write operation, FALSE for reads.
++ @input: WriteData - write data, byte to write if write operation.
++
++ @output: pRequest - request is updated with cmd52 parameters
++
++ @return: none
++
++ @notes: This function does not perform any I/O. For register reads, the completion
++ routine can use the SD_R5_GET_READ_DATA() macro to extract the register value.
++ The routine should also extract the response flags using the SD_R5_GET_RESP_FLAGS()
++ macro and check the flags with the SD_R5_ERRORS mask.
++
++ @example: Getting the register value from the completion routine:
++ flags = SD_R5_GET_RESP_FLAGS(pRequest->Response);
++ if (flags & SD_R5_ERRORS) {
++ ... errors
++ } else {
++ registerValue = SD_R5_GET_READ_DATA(pRequest->Response);
++ }
++
++ @see also: SDLIB_IssueCMD52
++ @see also: SDDEVICE_CALL_REQUEST_FUNC
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void _SDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest)
++{
++ _iSDLIB_SetupCMD52Request(FuncNo,Address,Write,WriteData,pRequest);
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Issue a CMD52 to read or write a register
++
++ @function name: SDLIB_IssueCMD52
++ @prototype: SDIO_STATUS SDLIB_IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUINT8 pData,
++ INT ByteCount,
++ BOOL Write)
++ @category: PD_Reference
++ @input: pDevice - the device that is the target of the command.
++ @input: FunctionNo - function number of the target.
++ @input: Address - 17-bit register address.
++ @input: ByteCount - number of bytes to read or write,
++ @input: Write - TRUE if a write operation, FALSE for reads.
++ @input: pData - data buffer for writes.
++
++ @output: pData - data buffer for writes.
++
++ @return: SDIO Status
++
++ @notes: This function will allocate a request and issue multiple byte reads or writes
++ to satisfy the ByteCount requested. This function is fully synchronous and will block
++ the caller.
++
++ @see also: SDLIB_SetupCMD52Request
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDLIB_IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUINT8 pData,
++ INT ByteCount,
++ BOOL Write)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ PSDREQUEST pReq = NULL;
++
++ pReq = SDDeviceAllocRequest(pDevice);
++
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ while (ByteCount) {
++ _iSDLIB_SetupCMD52Request(FuncNo,Address,Write,*pData,pReq);
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice,pReq);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ status = ConvertCMD52ResponseToSDIOStatus(SD_R5_GET_RESP_FLAGS(pReq->Response));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Library: CMD52 resp error: 0x%X \n",
++ SD_R5_GET_RESP_FLAGS(pReq->Response)));
++ break;
++ }
++ if (!Write) {
++ /* store the byte */
++ *pData = SD_R5_GET_READ_DATA(pReq->Response);
++ }
++ pData++;
++ Address++;
++ ByteCount--;
++ }
++
++ SDDeviceFreeRequest(pDevice,pReq);
++ return status;
++}
++
++
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Find a device's tuple.
++
++ @function name: SDLIB_FindTuple
++ @prototype: SDIO_STATUS SDLIB_FindTuple(PSDDEVICE pDevice,
++ UINT8 Tuple,
++ UINT32 *pTupleScanAddress,
++ PUINT8 pBuffer,
++ UINT8 *pLength)
++
++ @category: PD_Reference
++ @input: pDevice - the device that is the target of the command.
++ @input: Tuple - 8-bit ID of tuple to find
++ @input: pTupleScanAddress - On entry pTupleScanAddress is the adddress to start scanning
++ @input: pLength - length of pBuffer
++
++ @output: pBuffer - storage for tuple
++ @output: pTupleScanAddress - address of the next tuple
++ @output: pLength - length of tuple read
++
++ @return: status
++
++ @notes: It is possible to have the same tuple ID multiple times with different lengths. This function
++ blocks and is fully synchronous.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDLIB_FindTuple(PSDDEVICE pDevice,
++ UINT8 Tuple,
++ UINT32 *pTupleScanAddress,
++ PUINT8 pBuffer,
++ UINT8 *pLength)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 scanStart = *pTupleScanAddress;
++ UINT8 tupleCode;
++ UINT8 tupleLink;
++
++ /* sanity check */
++ if (scanStart < SDIO_CIS_AREA_BEGIN) {
++ return SDIO_STATUS_CIS_OUT_OF_RANGE;
++ }
++
++ while (TRUE) {
++ /* check for end */
++ if (scanStart > SDIO_CIS_AREA_END) {
++ status = SDIO_STATUS_TUPLE_NOT_FOUND;
++ break;
++ }
++ /* get the code */
++ status = _Cmd52ReadByteCommon(pDevice, scanStart, &tupleCode);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ if (CISTPL_END == tupleCode) {
++ /* found the end */
++ status = SDIO_STATUS_TUPLE_NOT_FOUND;
++ break;
++ }
++ /* bump past tuple code */
++ scanStart++;
++ /* get the tuple link value */
++ status = _Cmd52ReadByteCommon(pDevice, scanStart, &tupleLink);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* bump past tuple link*/
++ scanStart++;
++ /* check tuple we just found */
++ if (tupleCode == Tuple) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Library: Tuple:0x%2.2X Found at Address:0x%X, TupleLink:0x%X \n",
++ Tuple, (scanStart - 2), tupleLink));
++ if (tupleLink != CISTPL_LINK_END) {
++ /* return the next scan address to the caller */
++ *pTupleScanAddress = scanStart + tupleLink;
++ } else {
++ /* the tuple link is an end marker */
++ *pTupleScanAddress = 0xFFFFFFFF;
++ }
++ /* go get the tuple */
++ status = _Cmd52ReadMultipleCommon(pDevice, scanStart,pBuffer,min(*pLength,tupleLink));
++ if (SDIO_SUCCESS(status)) {
++ /* set the actual return length */
++ *pLength = min(*pLength,tupleLink);
++ }
++ /* break out of loop */
++ break;
++ }
++ /*increment past this entire tuple */
++ scanStart += tupleLink;
++ }
++
++ return status;
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Issue an SDIO configuration command.
++
++ @function name: SDLIB_IssueConfig
++ @prototype: SDIO_STATUS _SDLIB_IssueConfig(PSDDEVICE pDevice,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length)
++
++ @category: PD_Reference
++ @input: pDevice - the device that is the target of the command.
++ @input: Command - command to send, see example.
++ @input: pData - command's data
++ @input: Length length of pData
++
++ @output: pData - updated on commands that return data.
++
++ @return: SDIO Status
++
++ @example: Command and data pairs:
++ Type Data
++ SDCONFIG_GET_WP SDCONFIG_WP_VALUE
++ SDCONFIG_SEND_INIT_CLOCKS none
++ SDCONFIG_SDIO_INT_CTRL SDCONFIG_SDIO_INT_CTRL_DATA
++ SDCONFIG_SDIO_REARM_INT none
++ SDCONFIG_BUS_MODE_CTRL SDCONFIG_BUS_MODE_DATA
++ SDCONFIG_POWER_CTRL SDCONFIG_POWER_CTRL_DATA
++
++ @notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDLIB_IssueConfig(PSDDEVICE pDevice,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length)
++{
++ SDCONFIG configHdr;
++ SET_SDCONFIG_CMD_INFO(&configHdr,Command,pData,Length);
++ return SDDEVICE_CALL_CONFIG_FUNC(pDevice,&configHdr);
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Set function block size
++
++ @function name: SDLIB_SetFunctionBlockSize
++ @prototype: SDIO_STATUS SDLIB_SetFunctionBlockSize(PSDDEVICE pDevice,
++ UINT16 BlockSize)
++
++ @category: PD_Reference
++ @input: pDevice - the device that is the target of the command.
++ @input: BlockSize - block size to set in function
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: Issues CMD52 to set the block size. This function is fully synchronous and may
++ block.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDLIB_SetFunctionBlockSize(PSDDEVICE pDevice,
++ UINT16 BlockSize)
++{
++ UINT8 data[2];
++
++ /* endian safe */
++ data[0] = (UINT8)BlockSize;
++ data[1] = (UINT8)(BlockSize >> 8);
++ /* write the function blk size control register */
++ return _SDLIB_IssueCMD52(pDevice,
++ 0, /* function 0 register space */
++ FBR_FUNC_BLK_SIZE_LOW_OFFSET(CalculateFBROffset(
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice))),
++ data,
++ 2,
++ TRUE);
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Print a buffer to the debug output
++
++ @function name: SDLIB_PrintBuffer
++ @prototype: void SDLIB_PrintBuffer(PUCHAR pBuffer, INT Length, PTEXT pDescription)
++ @category: Support_Reference
++
++ @input: pBuffer - Hex buffer to be printed.
++ @input: Length - length of pBuffer.
++ @input: pDescription - String title to be printed above the dump.
++
++ @output: none
++
++ @return: none
++
++ @notes: Prints the buffer by converting to ASCII and using REL_PRINT() with 16
++ bytes per line.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void _SDLIB_PrintBuffer(PUCHAR pBuffer, INT Length, PTEXT pDescription)
++{
++ TEXT line[49];
++ TEXT address[5];
++ TEXT ascii[17];
++ TEXT temp[5];
++ INT i;
++ UCHAR num;
++ USHORT offset = 0;
++
++ REL_PRINT(0,
++ ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n"));
++ if (pDescription != NULL) {
++ REL_PRINT(0, ("Description: %s \n\n",pDescription));
++ } else {
++ REL_PRINT(0, ("Description: NONE \n\n"));
++ }
++ REL_PRINT(0,
++ ("Offset Data ASCII \n"));
++ REL_PRINT(0,
++ ("--------------------------------------------------------------------------\n"));
++
++ while (Length) {
++ line[0] = (TEXT)0;
++ ascii[0] = (TEXT)0;
++ address[0] = (TEXT)0;
++ sprintf(address,"%4.4X",offset);
++ for (i = 0; i < 16; i++) {
++ if (Length != 0) {
++ num = *pBuffer;
++ sprintf(temp,"%2.2X ",num);
++ strcat(line,temp);
++ if ((num >= 0x20) && (num <= 0x7E)) {
++ sprintf(temp,"%c",*pBuffer);
++ } else {
++ sprintf(temp,"%c",0x2e);
++ }
++ strcat(ascii,temp);
++ pBuffer++;
++ Length--;
++ } else {
++ /* pad partial line with spaces */
++ strcat(line," ");
++ strcat(ascii," ");
++ }
++ }
++ REL_PRINT(0,("%s %s %s\n", address, line, ascii));
++ offset += 16;
++ }
++ REL_PRINT(0,
++ ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n"));
++
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get default operational current
++
++ @function name: SDLIB_GetDefaultOpCurrent
++ @prototype: SDIO_STATUS SDLIB_GetDefaultOpCurrent(PSDDEVICE pDevice, SD_SLOT_CURRENT *pOpCurrent)
++ @category: PD_Reference
++
++ @input: pDevice - the device that is the target of the command.
++
++ @output: pOpCurrent - operational current in mA.
++
++ @return: SDIO_STATUS
++
++ @notes: This routine reads the function's CISTPL_FUNCE tuple for the default operational
++ current. For SDIO 1.0 devices this value is read from the 8-bit TPLFE_OP_MAX_PWR
++ field. For SDIO 1.1 devices, the HP MAX power field is used only if the device is
++ operating in HIPWR mode. Otherwise the 8-bit TPLFE_OP_MAX_PWR field is used.
++ Some systems may restrict high power/current mode and force cards to operate in a
++ legacy (< 200mA) mode. This function is fully synchronous and will block the caller.
++
++ @example: Getting the default operational current for this function:
++ // get default operational current
++ status = SDLIB_GetDefaultOpCurrent(pDevice, &slotCurrent);
++ if (!SDIO_SUCCESS(status)) {
++ .. failed
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDLIB_GetDefaultOpCurrent(PSDDEVICE pDevice, SD_SLOT_CURRENT *pOpCurrent)
++{
++ UINT32 nextTpl;
++ UINT8 tplLength;
++ struct SDIO_FUNC_EXT_FUNCTION_TPL_1_1 funcTuple;
++ SDIO_STATUS status;
++
++ /* get the FUNCE tuple */
++ nextTpl = SDDEVICE_GET_SDIO_FUNC_CISPTR(pDevice);
++ tplLength = sizeof(funcTuple);
++ /* go get the function Extension tuple */
++ status = _SDLIB_FindTuple(pDevice,
++ CISTPL_FUNCE,
++ &nextTpl,
++ (PUINT8)&funcTuple,
++ &tplLength);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDLIB_GetDefaultOpCurrent: Failed to get FuncE Tuple: %d \n", status));
++ return status;
++ }
++ /* use the operational power (8-bit) value of current in mA as default*/
++ *pOpCurrent = funcTuple.CommonInfo.OpMaxPwr;
++ if ((tplLength >= sizeof(funcTuple)) && (SDDEVICE_IS_SDIO_REV_GTEQ_1_10(pDevice))) {
++ /* we have a 1.1 tuple */
++ /* check for HIPWR mode */
++ if (SDDEVICE_GET_CARD_FLAGS(pDevice) & CARD_HIPWR) {
++ /* use the maximum operational power (16 bit ) from the tuple */
++ *pOpCurrent = CT_LE16_TO_CPU_ENDIAN(funcTuple.HiPwrMaxPwr);
++ }
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++static INLINE void FreeMessageBlock(PSDMESSAGE_QUEUE pQueue, PSDMESSAGE_BLOCK pMsg) {
++ SDListInsertHead(&pQueue->FreeMessageList, &pMsg->SDList);
++}
++static INLINE void QueueMessageBlock(PSDMESSAGE_QUEUE pQueue, PSDMESSAGE_BLOCK pMsg) {
++ SDListInsertTail(&pQueue->MessageList, &pMsg->SDList);
++}
++static INLINE void QueueMessageToHead(PSDMESSAGE_QUEUE pQueue, PSDMESSAGE_BLOCK pMsg) {
++ SDListInsertHead(&pQueue->MessageList, &pMsg->SDList);
++}
++
++static INLINE PSDMESSAGE_BLOCK GetFreeMessageBlock(PSDMESSAGE_QUEUE pQueue) {
++ PSDLIST pItem = SDListRemoveItemFromHead(&pQueue->FreeMessageList);
++ if (pItem != NULL) {
++ return CONTAINING_STRUCT(pItem, SDMESSAGE_BLOCK , SDList);
++ }
++ return NULL;
++}
++static INLINE PSDMESSAGE_BLOCK GetQueuedMessage(PSDMESSAGE_QUEUE pQueue) {
++ PSDLIST pItem = SDListRemoveItemFromHead(&pQueue->MessageList);
++ if (pItem != NULL) {
++ return CONTAINING_STRUCT(pItem, SDMESSAGE_BLOCK , SDList);
++ }
++ return NULL;
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Create a message queue
++
++ @function name: SDLIB_CreateMessageQueue
++ @prototype: PSDMESSAGE_QUEUE SDLIB_CreateMessageQueue(INT MaxMessages, INT MaxMessageLength)
++ @category: Support_Reference
++
++ @input: MaxMessages - Maximum number of messages this queue supports
++ @input: MaxMessageLength - Maximum size of each message
++
++ @return: Message queue object, NULL on failure
++
++ @notes: This function creates a simple first-in-first-out message queue. The caller must determine
++ the maximum number of messages the queue supports and the size of each message. This
++ function will pre-allocate memory for each message. A producer of data posts a message
++ using SDLIB_PostMessage with a user defined data structure. A consumer of this data
++ can retrieve the message (in FIFO order) using SDLIB_GetMessage. A message queue does not
++ provide a signaling mechanism for notifying a consumer of data. Notifying a consumer is
++ user defined.
++
++ @see also: SDLIB_DeleteMessageQueue, SDLIB_GetMessage, SDLIB_PostMessage.
++
++ @example: Creating a message queue:
++ typedef struct _MyMessage {
++ UINT8 Code;
++ PVOID pDataBuffer;
++ } MyMessage;
++ // create message queue, 16 messages max.
++ pMsgQueue = SDLIB_CreateMessageQueue(16,sizeof(MyMessage));
++ if (NULL == pMsgQueue) {
++ .. failed
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++PSDMESSAGE_QUEUE _CreateMessageQueue(INT MaxMessages, INT MaxMessageLength)
++{
++ PSDMESSAGE_QUEUE pQueue = NULL;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ INT ii;
++ PSDMESSAGE_BLOCK pMsg;
++
++ do {
++ pQueue = (PSDMESSAGE_QUEUE)KernelAlloc(sizeof(SDMESSAGE_QUEUE));
++
++ if (NULL == pQueue) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ SDLIST_INIT(&pQueue->MessageList);
++ SDLIST_INIT(&pQueue->FreeMessageList);
++ pQueue->MaxMessageLength = MaxMessageLength;
++ status = CriticalSectionInit(&pQueue->MessageCritSection);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* allocate message blocks */
++ for (ii = 0; ii < MaxMessages; ii++) {
++ pMsg = (PSDMESSAGE_BLOCK)KernelAlloc(sizeof(SDMESSAGE_BLOCK) + MaxMessageLength -1);
++ if (NULL == pMsg) {
++ break;
++ }
++ FreeMessageBlock(pQueue, pMsg);
++ }
++
++ if (0 == ii) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ if (pQueue != NULL) {
++ _DeleteMessageQueue(pQueue);
++ pQueue = NULL;
++ }
++ }
++ return pQueue;
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Delete a message queue
++
++ @function name: SDLIB_DeleteMessageQueue
++ @prototype: void SDLIB_DeleteMessageQueue(PSDMESSAGE_QUEUE pQueue)
++ @category: Support_Reference
++
++ @input: pQueue - message queue to delete
++
++ @notes: This function flushes the message queue and frees all memory allocated for
++ messages.
++
++ @see also: SDLIB_CreateMessageQueue
++
++ @example: Deleting a message queue:
++ if (pMsgQueue != NULL) {
++ SDLIB_DeleteMessageQueue(pMsgQueue);
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void _DeleteMessageQueue(PSDMESSAGE_QUEUE pQueue)
++{
++ PSDMESSAGE_BLOCK pMsg;
++ SDIO_STATUS status;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ status = CriticalSectionAcquireSyncIrq(&pQueue->MessageCritSection);
++
++ /* cleanup free list */
++ while (1) {
++ pMsg = GetFreeMessageBlock(pQueue);
++ if (pMsg != NULL) {
++ KernelFree(pMsg);
++ } else {
++ break;
++ }
++ }
++ /* cleanup any in the queue */
++ while (1) {
++ pMsg = GetQueuedMessage(pQueue);
++ if (pMsg != NULL) {
++ KernelFree(pMsg);
++ } else {
++ break;
++ }
++ }
++
++ status = CriticalSectionReleaseSyncIrq(&pQueue->MessageCritSection);
++ CriticalSectionDelete(&pQueue->MessageCritSection);
++ KernelFree(pQueue);
++
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Post a message queue
++
++ @function name: SDLIB_PostMessage
++ @prototype: SDIO_STATUS SDLIB_PostMessage(PSDMESSAGE_QUEUE pQueue, PVOID pMessage, INT MessageLength)
++ @category: Support_Reference
++
++ @input: pQueue - message queue to post to
++ @input: pMessage - message to post
++ @input: MessageLength - length of message (for validation)
++
++ @return: SDIO_STATUS
++
++ @notes: The message queue uses an internal list of user defined message structures. When
++ posting a message the message is copied into an allocated structure and queued. The memory
++ pointed to by pMessage does not need to be allocated and can reside on the stack.
++ The length of the message to post can be smaller that the maximum message size. This allows
++ for variable length messages up to the maximum message size. This
++ function returns SDIO_STATUS_NO_RESOURCES, if the message queue is full. This
++ function returns SDIO_STATUS_BUFFER_TOO_SMALL, if the message size exceeds the maximum
++ size of a message. Posting and getting messsages from a message queue is safe in any
++ driver context.
++
++ @see also: SDLIB_CreateMessageQueue , SDLIB_GetMessage
++
++ @example: Posting a message
++ MyMessage message;
++ // set up message
++ message.code = MESSAGE_DATA_READY;
++ message.pData = pInstance->pDataBuffers[currentIndex];
++ // post message
++ status = SDLIB_PostMessage(pInstance->pReadQueue,&message,sizeof(message));
++ if (!SDIO_SUCCESS(status)) {
++ // failed
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _PostMessage(PSDMESSAGE_QUEUE pQueue, PVOID pMessage, INT MessageLength)
++{
++ SDIO_STATUS status2;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDMESSAGE_BLOCK pMsg;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ if (MessageLength > pQueue->MaxMessageLength) {
++ return SDIO_STATUS_BUFFER_TOO_SMALL;
++ }
++
++ status = CriticalSectionAcquireSyncIrq(&pQueue->MessageCritSection);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ do {
++ /* get a message block */
++ pMsg = GetFreeMessageBlock(pQueue);
++ if (NULL == pMsg) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ /* copy the message */
++ memcpy(pMsg->MessageStart,pMessage,MessageLength);
++ /* set the length of the message */
++ pMsg->MessageLength = MessageLength;
++ /* queue the message to the list */
++ QueueMessageBlock(pQueue,pMsg);
++ } while (FALSE);
++
++ status2 = CriticalSectionReleaseSyncIrq(&pQueue->MessageCritSection);
++ return status;
++}
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a message from a message queue
++
++ @function name: SDLIB_GetMessage
++ @prototype: SDIO_STATUS SDLIB_GetMessage(PSDMESSAGE_QUEUE pQueue, PVOID pData, INT *pBufferLength)
++ @category: Support_Reference
++
++ @input: pQueue - message queue to retreive a message from
++ @input: pBufferLength - on entry, the length of the data buffer
++ @output: pData - buffer to hold the message
++ @output: pBufferLength - on return, contains the number of bytes copied
++
++ @return: SDIO_STATUS
++
++ @notes: The message queue uses an internal list of user defined message structures. The message is
++ dequeued (FIFO order) and copied to the callers buffer. The internal allocation for the message
++ is returned back to the message queue. This function returns SDIO_STATUS_NO_MORE_MESSAGES
++ if the message queue is empty. If the length of the buffer is smaller than the length of
++ the message at the head of the queue,this function returns SDIO_STATUS_BUFFER_TOO_SMALL and
++ returns the required length in pBufferLength.
++
++ @see also: SDLIB_CreateMessageQueue , SDLIB_PostMessage
++
++ @example: Getting a message
++ MyMessage message;
++ INT length;
++ // set length
++ length = sizeof(message);
++ // post message
++ status = SDLIB_GetMessage(pInstance->pReadQueue,&message,&length);
++ if (!SDIO_SUCCESS(status)) {
++ // failed
++ }
++
++ @example: Checking queue for a message and getting the size of the message
++ INT length;
++ // use zero length to get the size of the message
++ length = 0;
++ status = SDLIB_GetMessage(pInstance->pReadQueue,NULL,&length);
++ if (status == SDIO_STATUS_NO_MORE_MESSAGES) {
++ // no messages in queue
++ } else if (status == SDIO_STATUS_BUFFER_TOO_SMALL) {
++ // message exists in queue and length of message is returned
++ messageSizeInQueue = length;
++ } else {
++ // some other failure
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _GetMessage(PSDMESSAGE_QUEUE pQueue, PVOID pData, INT *pBufferLength)
++{
++ SDIO_STATUS status2;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDMESSAGE_BLOCK pMsg;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ status = CriticalSectionAcquireSyncIrq(&pQueue->MessageCritSection);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ do {
++ pMsg = GetQueuedMessage(pQueue);
++ if (NULL == pMsg) {
++ status = SDIO_STATUS_NO_MORE_MESSAGES;
++ break;
++ }
++ if (*pBufferLength < pMsg->MessageLength) {
++ /* caller buffer is too small */
++ *pBufferLength = pMsg->MessageLength;
++ /* stick it back to the front */
++ QueueMessageToHead(pQueue, pMsg);
++ status = SDIO_STATUS_BUFFER_TOO_SMALL;
++ break;
++ }
++ /* copy the message to the callers buffer */
++ memcpy(pData,pMsg->MessageStart,pMsg->MessageLength);
++ /* return actual length */
++ *pBufferLength = pMsg->MessageLength;
++ /* return this message block back to the free list */
++ FreeMessageBlock(pQueue, pMsg);
++
++ } while (FALSE);
++
++ status2 = CriticalSectionReleaseSyncIrq(&pQueue->MessageCritSection);
++
++ return status;
++}
++
++/* the following documents the OS helper APIs */
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Create an OS-specific helper task/thread
++
++ @function name: SDLIB_OSCreateHelper
++ @prototype: SDIO_STATUS SDLIB_OSCreateHelper(POSKERNEL_HELPER pHelper,
++ PHELPER_FUNCTION pFunction,
++ PVOID pContext)
++ @category: Support_Reference
++
++ @input: pHelper - caller allocated helper object
++ @input: pFunction - helper function
++ @input: pContext - helper context
++
++ @return: SDIO_STATUS
++
++ @notes: This function creates a helper task/thread that runs in a new execution context. The newly
++ created task/thread invokes the helper function. The thread/task exits when the helper
++ function returns. The helper function has the prototype of:
++ THREAD_RETURN HelperFunction(POSKERNEL_HELPER pHelper)
++ The helper function usually implements a while loop and suspends execution using
++ SD_WAIT_FOR_WAKEUP(). On exit the helper function can return an OS-specific THREAD_RETURN
++ code (usually zero). The helper function executes in a fully schedule-able context and
++ can block on semaphores and sleep.
++
++ @see also: SDLIB_OSDeleteHelper , SD_WAIT_FOR_WAKEUP
++
++ @example: A thread helper function:
++ THREAD_RETURN HelperFunction(POSKERNEL_HELPER pHelper)
++ {
++ SDIO_STATUS status;
++ PMYCONTEXT pContext = (PMYCONTEXT)SD_GET_OS_HELPER_CONTEXT(pHelper);
++ // wait for wake up
++ while(1) {
++ status = SD_WAIT_FOR_WAKEUP(pHelper);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ if (SD_IS_HELPER_SHUTTING_DOWN(pHelper)) {
++ //... shutting down
++ break;
++ }
++ // handle wakeup...
++ }
++ return 0;
++ }
++
++ @example: Creating a helper:
++ status = SDLIB_OSCreateHelper(&pInstance->OSHelper,HelperFunction,pInstance);
++ if (!SDIO_SUCCESS(status)) {
++ // failed
++ }
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/**++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Delete an OS helper task/thread
++
++ @function name: SDLIB_OSDeleteHelper
++ @prototype: void SDLIB_OSDeleteHelper(POSKERNEL_HELPER pHelper)
++ @category: Support_Reference
++
++ @input: pHelper - caller allocated helper object
++
++ @notes: This function wakes the helper and waits(blocks) until the helper exits. The caller can
++ only pass an OS helper structure that was initialized sucessfully by
++ SDLIB_OSCreateHelper. The caller must be in a schedulable context.
++
++ @see also: SDLIB_OSCreateHelper
++
++ @example: Deleting a helper:
++ if (pInstance->HelperCreated) {
++ // clean up the helper if we successfully created it
++ SDLIB_OSDeleteHelper(&pInstance->OSHelper);
++ }
++
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++
+Index: linux-2.6.22/drivers/sdio/lib/sdio_lib_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/lib/sdio_lib_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,254 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_function_os.c
++
++ at abstract: Linux implementation module for SDIO library
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++#define DBG_DECLARE 17;
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/module.h>
++#include <linux/init.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/kthread.h>
++#endif
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++
++#define DESCRIPTION "SDIO Kernel Library"
++#define AUTHOR "Atheros Communications, Inc."
++
++/* debug print parameter */
++
++//CT_DECLARE_MODULE_PARAM_INTEGER(sdio_lib_debug_level);
++//MODULE_PARM_DESC(sdio_lib_debug_level, "debuglevel 0-7, controls debug prints");
++
++
++/* proxies */
++SDIO_STATUS SDLIB_IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUINT8 pData,
++ INT ByteCount,
++ BOOL Write)
++{
++ return _SDLIB_IssueCMD52(pDevice,FuncNo,Address,pData,ByteCount,Write);
++}
++
++SDIO_STATUS SDLIB_FindTuple(PSDDEVICE pDevice,
++ UINT8 Tuple,
++ UINT32 *pTupleScanAddress,
++ PUINT8 pBuffer,
++ UINT8 *pLength)
++{
++ return _SDLIB_FindTuple(pDevice,Tuple,pTupleScanAddress,pBuffer,pLength);
++}
++
++SDIO_STATUS SDLIB_IssueConfig(PSDDEVICE pDevice,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length)
++{
++ return _SDLIB_IssueConfig(pDevice,Command,pData,Length);
++}
++
++void SDLIB_PrintBuffer(PUCHAR pBuffer,INT Length,PTEXT pDescription)
++{
++ _SDLIB_PrintBuffer(pBuffer,Length,pDescription);
++}
++
++SDIO_STATUS SDLIB_SetFunctionBlockSize(PSDDEVICE pDevice,
++ UINT16 BlockSize)
++{
++ return _SDLIB_SetFunctionBlockSize(pDevice,BlockSize);
++}
++
++void SDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest)
++{
++ _SDLIB_SetupCMD52Request(FuncNo,Address,Write,WriteData,pRequest);
++}
++
++SDIO_STATUS SDLIB_GetDefaultOpCurrent(PSDDEVICE pDevice, SD_SLOT_CURRENT *pOpCurrent)
++{
++ return _SDLIB_GetDefaultOpCurrent(pDevice,pOpCurrent);
++}
++
++/* helper function launcher */
++INT HelperLaunch(PVOID pContext)
++{
++ INT exit;
++ /* call function */
++ exit = ((POSKERNEL_HELPER)pContext)->pHelperFunc((POSKERNEL_HELPER)pContext);
++ complete_and_exit(&((POSKERNEL_HELPER)pContext)->Completion, exit);
++ return exit;
++}
++
++/*
++ * OSCreateHelper - create a worker kernel thread
++*/
++SDIO_STATUS SDLIB_OSCreateHelper(POSKERNEL_HELPER pHelper,
++ PHELPER_FUNCTION pFunction,
++ PVOID pContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ memset(pHelper,0,sizeof(OSKERNEL_HELPER));
++
++ do {
++ pHelper->pContext = pContext;
++ pHelper->pHelperFunc = pFunction;
++ status = SignalInitialize(&pHelper->WakeSignal);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ init_completion(&pHelper->Completion);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ pHelper->pTask = kthread_create(HelperLaunch,
++ (PVOID)pHelper,
++ "SDIO Helper");
++ if (NULL == pHelper->pTask) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ wake_up_process(pHelper->pTask);
++#else
++ /* 2.4 */
++ pHelper->pTask = kernel_thread(HelperLaunch,
++ (PVOID)pHelper,
++ (CLONE_FS | CLONE_FILES | SIGCHLD));
++ if (pHelper->pTask < 0) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - OSCreateHelper, failed to create thread\n"));
++ }
++#endif
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ SDLIB_OSDeleteHelper(pHelper);
++ }
++ return status;
++}
++
++/*
++ * OSDeleteHelper - delete thread created with OSCreateHelper
++*/
++void SDLIB_OSDeleteHelper(POSKERNEL_HELPER pHelper)
++{
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ if (pHelper->pTask != NULL) {
++#else
++ /* 2.4 */
++ if (pHelper->pTask >= 0) {
++#endif
++ pHelper->ShutDown = TRUE;
++ SignalSet(&pHelper->WakeSignal);
++ /* wait for thread to exit */
++ wait_for_completion(&pHelper->Completion);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ pHelper->pTask = NULL;
++#else
++ /* 2.4 */
++ pHelper->pTask = 0;
++#endif
++ }
++
++ SignalDelete(&pHelper->WakeSignal);
++}
++
++/*
++ * module init
++*/
++static int __init sdio_lib_init(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO Library load\n"));
++ return 0;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_lib_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO Library unload\n"));
++}
++
++PSDMESSAGE_QUEUE SDLIB_CreateMessageQueue(INT MaxMessages, INT MaxMessageLength)
++{
++ return _CreateMessageQueue(MaxMessages,MaxMessageLength);
++
++}
++void SDLIB_DeleteMessageQueue(PSDMESSAGE_QUEUE pQueue)
++{
++ _DeleteMessageQueue(pQueue);
++}
++
++SDIO_STATUS SDLIB_PostMessage(PSDMESSAGE_QUEUE pQueue, PVOID pMessage, INT MessageLength)
++{
++ return _PostMessage(pQueue,pMessage,MessageLength);
++}
++
++SDIO_STATUS SDLIB_GetMessage(PSDMESSAGE_QUEUE pQueue, PVOID pData, INT *pBufferLength)
++{
++ return _GetMessage(pQueue,pData,pBufferLength);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++module_init(sdio_lib_init);
++module_exit(sdio_lib_cleanup);
++EXPORT_SYMBOL(SDLIB_IssueCMD52);
++EXPORT_SYMBOL(SDLIB_FindTuple);
++EXPORT_SYMBOL(SDLIB_IssueConfig);
++EXPORT_SYMBOL(SDLIB_PrintBuffer);
++EXPORT_SYMBOL(SDLIB_SetFunctionBlockSize);
++EXPORT_SYMBOL(SDLIB_SetupCMD52Request);
++EXPORT_SYMBOL(SDLIB_GetDefaultOpCurrent);
++EXPORT_SYMBOL(SDLIB_OSCreateHelper);
++EXPORT_SYMBOL(SDLIB_OSDeleteHelper);
++EXPORT_SYMBOL(SDLIB_CreateMessageQueue);
++EXPORT_SYMBOL(SDLIB_DeleteMessageQueue);
++EXPORT_SYMBOL(SDLIB_PostMessage);
++EXPORT_SYMBOL(SDLIB_GetMessage);
+Index: linux-2.6.22/drivers/sdio/busdriver/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,7 @@
++#
++# SDIO stack bus drivers
++#
++obj-$(CONFIG_SDIO) += sdio_busdriver.o
++sdio_busdriver-objs := sdio_bus.o sdio_function.o sdio_bus_misc.o sdio_bus_events.o sdio_bus_os.o
++
++
+Index: linux-2.6.22/drivers/sdio/busdriver/_busdriver.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/_busdriver.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,462 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: _busdriver.h
++
++ at abstract: internal include file for busdriver
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef ___BUSDRIVER_H___
++#define ___BUSDRIVER_H___
++#include <linux/sdio/sdio_lib.h>
++
++#define SDIODBG_FUNC_IRQ (SDDBG_TRACE + 1)
++#define SDIODBG_REQUESTS (SDDBG_TRACE + 2)
++#define SDIODBG_CD_TIMER (SDDBG_TRACE + 3)
++#define SDIODBG_HCD_EVENTS (SDDBG_TRACE + 4)
++
++#define SDIOBUS_CD_TIMER_ID 0
++
++#define SDBUS_MAX_RETRY 3
++
++/* Notes on list linkages:
++ * list heads are held in BDCONTEXT
++ * HcdList - SDHCD
++ * one per registered host controller
++ * Next - links of all HCDs
++ * DeviceList SDDEVICE
++ * one per inserted device
++ * Next - links of all devices
++ * DeviceListNext - links of all devices on a function
++ * pFunction - ptr to Function supportting this device
++ * pHcd - ptr to HCD with supporting this device
++ * FunctionList SDFUNCTION
++ * one per register function driver
++ * Next - links of all functions
++ * DeviceList - list of devices being support by this function
++ * uses DeviceListNext in SDDEVICE to link
++ *
++ *
++*/
++
++#define SDMMC_DEFAULT_CMD_RETRIES 1
++#define SDMMC_DEFAULT_CARD_READY_RETRIES 200
++#define OCR_READY_CHECK_DELAY_MS 10
++#define SDMMC_POWER_SETTLE_DELAY 400 /* in milliseconds */
++#define SDBUS_DEFAULT_REQ_LIST_SIZE 16
++#define SDBUS_DEFAULT_REQ_SIG_SIZE 8
++#define CARD_DETECT_PAUSE 100
++#define SDBUS_DEFAULT_CD_POLLING_INTERVAL 1000 /* in milliseconds */
++#define MAX_CARD_DETECT_MSGS 16
++#define SDMMC_DEFAULT_BYTES_PER_BLOCK 2048
++#define SDMMC_DEFAULT_BLOCKS_PER_TRANS 512
++#define SDMMC_CMD13_POLLING_MULTIPLIER 1000 /* per block multiplier */
++#define MAX_HCD_REQ_RECURSION 5
++#define MAX_HCD_RECURSION_RUNAWAY 100
++
++ /* internal signalling item */
++typedef struct _SIGNAL_ITEM{
++ SDLIST SDList; /* list link*/
++ OS_SIGNAL Signal; /* signal */
++}SIGNAL_ITEM, *PSIGNAL_ITEM;
++
++typedef struct _HCD_EVENT_MESSAGE {
++ HCD_EVENT Event; /* the event */
++ PSDHCD pHcd; /* hcd that generated the event */
++}HCD_EVENT_MESSAGE, *PHCD_EVENT_MESSAGE;
++
++/* internal data for bus driver */
++typedef struct _BDCONTEXT {
++
++ /* list of SD requests and signalling semaphores and a semaphore to protect it */
++ SDLIST RequestList;
++ SDLIST SignalList;
++ OS_CRITICALSECTION RequestListCritSection;
++ /* list of host controller bus drivers, sempahore to protect it */
++ SDLIST HcdList;
++ OS_SEMAPHORE HcdListSem;
++ /* list of inserted devices, semaphore to protect it */
++ SDLIST DeviceList;
++ OS_SEMAPHORE DeviceListSem;
++ /* list of function drivers, semaphore to protect it */
++ SDLIST FunctionList;
++ OS_SEMAPHORE FunctionListSem;
++ INT RequestListSize; /* default request list */
++ INT SignalSemListSize; /* default signalling semaphore size */
++ INT CurrentRequestAllocations; /*current count of allocated requests */
++ INT CurrentSignalAllocations; /* current count of signal allocations */
++ INT MaxRequestAllocations; /* max number of allocated requests to keep around*/
++ INT MaxSignalAllocations; /* max number of signal allocations to keep around*/
++ INT RequestRetries; /* cmd retries */
++ INT CardReadyPollingRetry; /* card ready polling retry count */
++ INT PowerSettleDelay; /* power settle delay */
++ INT CMD13PollingMultiplier; /* CMD13 (GET STATUS) multiplier */
++ SD_BUSCLOCK_RATE DefaultOperClock; /* default operation clock */
++ SD_BUSMODE_FLAGS DefaultBusMode; /* default bus mode */
++ UINT16 DefaultOperBlockLen; /* default operational block length per block */
++ UINT16 DefaultOperBlockCount; /* default operational block count per transaction */
++ UINT32 CDPollingInterval; /* card insert/removal polling interval */
++ UINT8 InitMask; /* bus driver init mask */
++#define BD_TIMER_INIT 0x01
++#define HELPER_INIT 0x02
++#define RESOURCE_INIT 0x04
++ BOOL CDTimerQueued; /* card detect timer queued */
++ OSKERNEL_HELPER CardDetectHelper; /* card detect helper */
++ PSDMESSAGE_QUEUE pCardDetectMsgQueue; /* card detect message queue */
++ ULONG HcdInUseField; /* bit field of in use HCD numbers*/
++ UINT32 ConfigFlags; /* bus driver configuration flags */
++#define BD_CONFIG_SDREQ_FORCE_ALL_ASYNC 0x00000001
++ INT MaxHcdRecursion; /* max HCD recurion level */
++}BDCONTEXT, *PBDCONTEXT;
++
++#define BD_DEFAULT_CONFIG_FLAGS 0x00000000
++#define IsQueueBusy(pRequestQueue) (pRequestQueue)->Busy
++#define MarkQueueBusy(pRequestQueue) (pRequestQueue)->Busy = TRUE
++#define MarkQueueNotBusy(pRequestQueue) (pRequestQueue)->Busy = FALSE
++
++#define CLEAR_INTERNAL_REQ_FLAGS(pReq) (pReq)->Flags &= ~(UINT)((SDREQ_FLAGS_RESP_SPI_CONVERTED | \
++ SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE))
++
++/* macros to insert request into the queue */
++#define QueueRequest(pReqQ,pReq) SDListInsertTail(&(pReqQ)->Queue,&(pReq)->SDList)
++#define QueueRequestToFront(pReqQ,pReq) SDListInsertHead(&(pReqQ)->Queue,&(pReq)->SDList)
++
++/* macros to remove an item from the head of the queue */
++static INLINE PSDREQUEST DequeueRequest(PSDREQUESTQUEUE pRequestQueue) {
++ PSDLIST pItem;
++ pItem = SDListRemoveItemFromHead(&pRequestQueue->Queue);
++ if (pItem != NULL) {
++ return CONTAINING_STRUCT(pItem, SDREQUEST, SDList);
++ }
++ return NULL;
++}
++
++static INLINE SDIO_STATUS InitializeRequestQueue(PSDREQUESTQUEUE pRequestQueue) {
++ SDLIST_INIT(&pRequestQueue->Queue);
++ MarkQueueNotBusy(pRequestQueue);
++ return SDIO_STATUS_SUCCESS;
++}
++
++static INLINE void CleanupRequestQueue(PSDREQUESTQUEUE pRequestQueue) {
++
++}
++
++/* for bus driver internal use only */
++SDIO_STATUS _SDIO_BusDriverInitialize(void);
++SDIO_STATUS _SDIO_BusGetDefaultSettings(PBDCONTEXT pBdc);
++void _SDIO_BusDriverCleanup(void);
++SDIO_STATUS RemoveAllFunctions(void);
++SDIO_STATUS RemoveHcdFunctions(PSDHCD pHcd);
++PSDDEVICE AllocateDevice(PSDHCD pHcd);
++BOOL AddDeviceToList(PSDDEVICE pDevice);
++SDIO_STATUS DeleteDevices(PSDHCD pHcd);
++SDIO_STATUS NotifyDeviceRemove(PSDDEVICE pDevice);
++extern PBDCONTEXT pBusContext;
++extern const CT_VERSION_CODE g_Version;
++SDIO_STATUS _SDIO_RegisterHostController(PSDHCD pHcd);
++SDIO_STATUS _SDIO_UnregisterHostController(PSDHCD pHcd);
++SDIO_STATUS _SDIO_HandleHcdEvent(PSDHCD pHcd, HCD_EVENT Event);
++SDIO_STATUS _SDIO_RegisterFunction(PSDFUNCTION pFunction);
++SDIO_STATUS _SDIO_UnregisterFunction(PSDFUNCTION pFunction);
++SDIO_STATUS _SDIO_CheckResponse(PSDHCD pHcd, PSDREQUEST pReq, SDHCD_RESPONSE_CHECK_MODE CheckMode);
++SDIO_STATUS ProbeForFunction(PSDDEVICE pDevice, PSDHCD pHcd);
++SDIO_STATUS SDInitializeCard(PSDHCD pHcd);
++SDIO_STATUS SDQuerySDMMCInfo(PSDDEVICE pDevice);
++SDIO_STATUS SDQuerySDIOInfo(PSDDEVICE pDevice);
++SDIO_STATUS SDEnableFunction(PSDDEVICE pDevice, PSDCONFIG_FUNC_ENABLE_DISABLE_DATA pEnData);
++SDIO_STATUS SDAllocFreeSlotCurrent(PSDDEVICE pDevice, BOOL Allocate, PSDCONFIG_FUNC_SLOT_CURRENT_DATA pData);
++SDIO_STATUS SDMaskUnmaskFunctionIRQ(PSDDEVICE pDevice, BOOL Mask);
++SDIO_STATUS SDFunctionAckInterrupt(PSDDEVICE pDevice);
++SDIO_STATUS SDSPIModeEnableDisableCRC(PSDDEVICE pDevice,BOOL Enable);
++SDIO_STATUS IssueBusConfig(PSDDEVICE pDev, PSDCONFIG pConfig);
++SDIO_STATUS IssueBusRequest(PSDDEVICE pDev, PSDREQUEST pReq);
++PSDREQUEST IssueAllocRequest(PSDDEVICE pDev);
++void IssueFreeRequest(PSDDEVICE pDev, PSDREQUEST pReq);
++PSDREQUEST AllocateRequest(void);
++void FreeRequest(PSDREQUEST pReq);
++PSIGNAL_ITEM AllocateSignal(void);
++void FreeSignal(PSIGNAL_ITEM pSignal);
++SDIO_STATUS InitializeTimers(void);
++SDIO_STATUS CleanupTimers(void);
++SDIO_STATUS QueueTimer(INT TimerID, UINT32 TimeOut);
++SDIO_STATUS DeviceAttach(PSDHCD pHcd);
++SDIO_STATUS DeviceDetach(PSDHCD pHcd);
++SDIO_STATUS DeviceInterrupt(PSDHCD pHcd);
++SDIO_STATUS CardInitSetup(PSDHCD pHcd);
++void RunCardDetect(void);
++void SDIO_NotifyTimerTriggered(INT TimerID);
++SDIO_STATUS TestPresence(PSDHCD pHcd,
++ CARD_INFO_FLAGS TestType,
++ PSDREQUEST pReq);
++#define _IssueSimpleBusRequest(pHcd,Cmd,Arg,Flags,pReqToUse) \
++ _IssueBusRequestBd((pHcd),(Cmd),(Arg),(Flags),(pReqToUse),NULL,0)
++
++SDIO_STATUS Do_OS_IncHcdReference(PSDHCD pHcd);
++SDIO_STATUS Do_OS_DecHcdReference(PSDHCD pHcd);
++SDIO_STATUS TryNoIrqPendingCheck(PSDDEVICE pDev);
++
++ /* check API version compatibility of an HCD or function driver to a stack major/minor version
++ if the driver version is greater than the major number, we are compatible
++ if the driver version is equal, then we check if the minor is greater than or equal
++ we don't have to check for the less than major, because the bus driver never loads
++ drivers with different major numbers ...
++ if the busdriver compiled version major is greater than the major version being checked this
++ macro will resolved to ALWAYS true thus optimizing the code to not check the HCD since
++ as a rule we never load an HCD with a lower major number */
++#define CHECK_API_VERSION_COMPAT(p,major,minor) \
++ ((CT_SDIO_STACK_VERSION_MAJOR(CT_SDIO_STACK_VERSION_CODE) > (major)) || \
++ (GET_SDIO_STACK_VERSION_MINOR((p)) >= (minor)))
++
++static INLINE SDIO_STATUS OS_IncHcdReference(PSDHCD pHcd) {
++ /* this API was added in version 2.3 which requires access to a field in the HCD structure */
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,3)) {
++ /* we can safely call the OS-dependent function */
++ return Do_OS_IncHcdReference(pHcd);
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++static INLINE SDIO_STATUS OS_DecHcdReference(PSDHCD pHcd) {
++ /* this API was added in version 2.3 which requires access to a field in the HCD structure */
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,3)) {
++ /* we can safely call the OS-dependent function */
++ return Do_OS_DecHcdReference(pHcd);
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++SDIO_STATUS _IssueBusRequestBd(PSDHCD pHcd,
++ UINT8 Cmd,
++ UINT32 Argument,
++ SDREQUEST_FLAGS Flags,
++ PSDREQUEST pReqToUse,
++ PVOID pData,
++ INT Length);
++
++SDIO_STATUS IssueRequestToHCD(PSDHCD pHcd,PSDREQUEST pReq);
++
++#define CALL_HCD_CONFIG(pHcd,pCfg) (pHcd)->pConfigure((pHcd),(pCfg))
++ /* macro to force all requests to be asynchronous in the HCD */
++static INLINE BOOL ForceAllRequestsAsync(void) {
++ return (pBusContext->ConfigFlags & BD_CONFIG_SDREQ_FORCE_ALL_ASYNC);
++}
++
++static INLINE SDIO_STATUS CallHcdRequest(PSDHCD pHcd) {
++
++ if (pHcd->pCurrentRequest->Flags & SDREQ_FLAGS_PSEUDO) {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: PSEUDO Request 0x%X \n",
++ (INT)pHcd->pCurrentRequest));
++ /* return successful completion so that processing can finish */
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (ForceAllRequestsAsync()) {
++ /* all requests must be completed(indicated) in a separate context */
++ pHcd->pCurrentRequest->Flags |= SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE;
++ } else {
++ /* otherwise perform a test on flags in the HCD */
++ if (!CHECK_API_VERSION_COMPAT(pHcd,2,6) &&
++ AtomicTest_Set(&pHcd->HcdFlags, HCD_REQUEST_CALL_BIT)) {
++
++ /* bit was already set, this is a recursive call,
++ * we need to tell the HCD to complete the
++ * request in a separate context */
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Recursive CallHcdRequest \n"));
++ pHcd->pCurrentRequest->Flags |= SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE;
++ }
++ }
++#ifdef DEBUG
++ {
++ SDIO_STATUS status;
++ BOOL forceDeferred;
++ forceDeferred = pHcd->pCurrentRequest->Flags & SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE;
++ status = pHcd->pRequest(pHcd);
++ if (forceDeferred) {
++ /* status better be pending... */
++ DBG_ASSERT(status == SDIO_STATUS_PENDING);
++ }
++ return status;
++ }
++#else
++ return pHcd->pRequest(pHcd);
++#endif
++
++}
++
++/* note the caller of this macro must take the HCD lock to protect the count */
++#define CHECK_HCD_RECURSE(pHcd,pReq) \
++{ \
++ (pHcd)->Recursion++; \
++ DBG_ASSERT((pHcd)->Recursion < MAX_HCD_RECURSION_RUNAWAY); \
++ if ((pHcd)->Recursion > pBusContext->MaxHcdRecursion) { \
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Recursive Request Count Exceeded (%d) \n",(pHcd)->Recursion)); \
++ (pReq)->Flags |= SDREQ_FLAGS_FORCE_DEFERRED_COMPLETE; \
++ } \
++}
++
++/* InternalFlags bit number settings */
++#define SDBD_INIT 1
++#define SDBD_PENDING 15
++#define SDBD_ALLOC_IRQ_SAFE 2
++
++#define SDBD_ALLOC_IRQ_SAFE_MASK (1 << SDBD_ALLOC_IRQ_SAFE)
++
++static void INLINE DoRequestCompletion(PSDREQUEST pReq, PSDHCD pHcd) {
++ CLEAR_INTERNAL_REQ_FLAGS(pReq);
++ if (pReq->pCompletion != NULL) {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Calling completion on request:0x%X, CMD:%d \n",
++ (INT)pReq, pReq->Command));
++ /* call completion routine, mark request reusable */
++ AtomicTest_Clear(&pReq->InternalFlags, SDBD_PENDING);
++ pReq->pCompletion(pReq);
++ } else {
++ /* mark request reusable */
++ AtomicTest_Clear(&pReq->InternalFlags, SDBD_PENDING);
++ }
++}
++
++THREAD_RETURN CardDetectHelperFunction(POSKERNEL_HELPER pHelper);
++THREAD_RETURN SDIOIrqHelperFunction(POSKERNEL_HELPER pHelper);
++
++void ConvertSPI_Response(PSDREQUEST pReq, UINT8 *pRespBuffer);
++
++static INLINE SDIO_STATUS PostCardDetectEvent(PBDCONTEXT pSDB, HCD_EVENT Event, PSDHCD pHcd) {
++ HCD_EVENT_MESSAGE message;
++ SDIO_STATUS status;
++ message.Event = Event;
++ message.pHcd = pHcd;
++
++ if (pHcd != NULL) {
++ /* increment HCD reference count to process this HCD message */
++ status = OS_IncHcdReference(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ }
++ /* post card detect message */
++ status = SDLIB_PostMessage(pSDB->pCardDetectMsgQueue, &message, sizeof(message));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: PostCardDetectEvent error status %d\n",status));
++ if (pHcd != NULL) {
++ /* decrement count */
++ OS_DecHcdReference(pHcd);
++ }
++ return status;
++ }
++ /* wake card detect helper */
++ DBG_PRINT(SDIODBG_HCD_EVENTS, ("SDIO Bus Driver: PostCardDetectEvent waking\n"));
++ return SD_WAKE_OS_HELPER(&pSDB->CardDetectHelper);
++}
++
++/* initialize device fields */
++static INLINE void InitDeviceData(PSDHCD pHcd, PSDDEVICE pDevice) {
++ ZERO_POBJECT(pDevice);
++ SDLIST_INIT(&pDevice->SDList);
++ SDLIST_INIT(&pDevice->FuncListLink);
++ pDevice->pRequest = IssueBusRequest;
++ pDevice->pConfigure = IssueBusConfig;
++ pDevice->AllocRequest = IssueAllocRequest;
++ pDevice->FreeRequest = IssueFreeRequest;
++ /* set card flags in the ID */
++ pDevice->pId[0].CardFlags = pHcd->CardProperties.Flags;
++ pDevice->pFunction = NULL;
++ pDevice->pHcd = pHcd;
++ SET_SDIO_STACK_VERSION(pDevice);
++}
++
++/* de-initialize device fields */
++static INLINE void DeinitDeviceData(PSDDEVICE pDevice) {
++}
++
++/* reset hcd state */
++static INLINE void ResetHcdState(PSDHCD pHcd) {
++ ZERO_POBJECT(&pHcd->CardProperties);
++ pHcd->PendingHelperIrqs = 0;
++ pHcd->PendingIrqAcks = 0;
++ pHcd->IrqsEnabled = 0;
++ pHcd->pCurrentRequest = NULL;
++ pHcd->IrqProcState = SDHCD_IDLE;
++ /* mark this device as special */
++ pHcd->pPseudoDev->pId[0].CardFlags = CARD_PSEUDO;
++ pHcd->SlotCurrentAllocated = 0;
++}
++
++static INLINE SDIO_STATUS _IssueConfig(PSDHCD pHcd,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length){
++ SDCONFIG configHdr;
++ SET_SDCONFIG_CMD_INFO(&configHdr,Command,pData,Length);
++ return CALL_HCD_CONFIG(pHcd,&configHdr);
++}
++
++/* prototypes */
++#define _AcquireHcdLock(pHcd)CriticalSectionAcquireSyncIrq(&(pHcd)->HcdCritSection)
++#define _ReleaseHcdLock(pHcd)CriticalSectionReleaseSyncIrq(&(pHcd)->HcdCritSection)
++
++#define AcquireHcdLock(pDev) CriticalSectionAcquireSyncIrq(&(pDev)->pHcd->HcdCritSection)
++#define ReleaseHcdLock(pDev) CriticalSectionReleaseSyncIrq(&(pDev)->pHcd->HcdCritSection)
++
++SDIO_STATUS OS_AddDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction);
++void OS_RemoveDevice(PSDDEVICE pDevice);
++SDIO_STATUS OS_InitializeDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction);
++SDIO_STATUS SetOperationalBusMode(PSDDEVICE pDevice,
++ PSDCONFIG_BUS_MODE_DATA pBusMode);
++void FreeDevice(PSDDEVICE pDevice);
++BOOL IsPotentialIdMatch(PSD_PNP_INFO pIdsDev, PSD_PNP_INFO pIdsFuncList);
++
++
++#define CHECK_FUNCTION_DRIVER_VERSION(pF) \
++ (GET_SDIO_STACK_VERSION_MAJOR((pF)) == CT_SDIO_STACK_VERSION_MAJOR(g_Version))
++#define CHECK_HCD_DRIVER_VERSION(pH) \
++ (GET_SDIO_STACK_VERSION_MAJOR((pH)) == CT_SDIO_STACK_VERSION_MAJOR(g_Version))
++
++/* CLARIFICATION on SDREQ_FLAGS_PSEUDO and SDREQ_FLAGS_BARRIER flags :
++ *
++ * A request marked as PSEUDO is synchronized with bus requests and is not a true request
++ * that is issued to an HCD.
++ *
++ * A request marked with a BARRIER flag requires that the completion routine be called
++ * before the next bus request starts. This is required for HCD requests that can change
++ * bus or clock modes. Changing the clock or bus mode while a bus request is pending
++ * can cause problems.
++ *
++ *
++ *
++ * */
++#define SD_PSEUDO_REQ_FLAGS \
++ (SDREQ_FLAGS_PSEUDO | SDREQ_FLAGS_BARRIER | SDREQ_FLAGS_TRANS_ASYNC)
++
++#endif /*___BUSDRIVER_H___*/
+Index: linux-2.6.22/drivers/sdio/busdriver/sdio_bus.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/sdio_bus.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,2119 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bus.c
++
++ at abstract: OS independent bus driver support
++ at category abstract: HD_Reference Host Controller Driver Interfaces.
++ at category abstract: PD_Reference
++ Peripheral Driver Interfaces.
++
++#notes: this file supports the HCD's and generic functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDBUSDRIVER
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include <linux/sdio/mmc_defs.h>
++#include "_busdriver.h"
++
++/* list of host controller bus drivers */
++PBDCONTEXT pBusContext = NULL;
++static void CleanUpBusResources(void);
++static SDIO_STATUS AllocateBusResources(void);
++static PSIGNAL_ITEM BuildSignal(void);
++static void DestroySignal(PSIGNAL_ITEM pSignal);
++
++const CT_VERSION_CODE g_Version = CT_SDIO_STACK_VERSION_CODE;
++/*
++ * _SDIO_BusDriverInitialize - call once on driver loading
++ *
++*/
++SDIO_STATUS _SDIO_BusDriverInitialize(void)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Version: %d.%d\n",
++ CT_SDIO_STACK_VERSION_MAJOR(g_Version),CT_SDIO_STACK_VERSION_MINOR(g_Version)));
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: enter _SDIO_BusDriverInitialize\n"));
++
++ do {
++ /* allocate our internal data initialize it */
++ pBusContext = KernelAlloc(sizeof(BDCONTEXT));
++ if (pBusContext == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't allocate memory.\n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ memset(pBusContext,0,sizeof(BDCONTEXT));
++ SDLIST_INIT(&pBusContext->RequestList);
++ SDLIST_INIT(&pBusContext->HcdList);
++ SDLIST_INIT(&pBusContext->DeviceList);
++ SDLIST_INIT(&pBusContext->FunctionList);
++ SDLIST_INIT(&pBusContext->SignalList);
++
++ /* setup defaults */
++ pBusContext->RequestRetries = SDMMC_DEFAULT_CMD_RETRIES;
++ pBusContext->CardReadyPollingRetry = SDMMC_DEFAULT_CARD_READY_RETRIES;
++ pBusContext->PowerSettleDelay = SDMMC_POWER_SETTLE_DELAY;
++ pBusContext->DefaultOperClock = MMC_HS_MAX_BUS_CLOCK;
++ pBusContext->DefaultBusMode = SDCONFIG_BUS_WIDTH_4_BIT;
++ pBusContext->RequestListSize = SDBUS_DEFAULT_REQ_LIST_SIZE;
++ pBusContext->SignalSemListSize = SDBUS_DEFAULT_REQ_SIG_SIZE;
++ pBusContext->CDPollingInterval = SDBUS_DEFAULT_CD_POLLING_INTERVAL;
++ pBusContext->DefaultOperBlockLen = SDMMC_DEFAULT_BYTES_PER_BLOCK;
++ pBusContext->DefaultOperBlockCount = SDMMC_DEFAULT_BLOCKS_PER_TRANS;
++ pBusContext->ConfigFlags = BD_DEFAULT_CONFIG_FLAGS;
++ pBusContext->CMD13PollingMultiplier = SDMMC_CMD13_POLLING_MULTIPLIER;
++ pBusContext->MaxHcdRecursion = MAX_HCD_REQ_RECURSION;
++
++ /* get overrides for the defaults */
++ status = _SDIO_BusGetDefaultSettings(pBusContext);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ pBusContext->MaxRequestAllocations = pBusContext->RequestListSize << 1;
++ pBusContext->MaxSignalAllocations = pBusContext->SignalSemListSize << 1;
++
++ status = CriticalSectionInit(&pBusContext->RequestListCritSection);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't CriticalSectionInit.\n"));
++ break;
++ }
++ status = SemaphoreInitialize(&pBusContext->HcdListSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't SemaphoreInitialize HcdListSem.\n"));
++ break;
++ }
++ status = SemaphoreInitialize(&pBusContext->DeviceListSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't SemaphoreInitialize DeviceListSem.\n"));
++ break;
++ }
++ status = SemaphoreInitialize(&pBusContext->FunctionListSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't SemaphoreInitialize FunctionListSem.\n"));
++ break;
++ }
++ status = AllocateBusResources();
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't AllocateBusResources.\n"));
++ break;
++ }
++
++ pBusContext->InitMask |= RESOURCE_INIT;
++
++ pBusContext->pCardDetectMsgQueue = SDLIB_CreateMessageQueue(MAX_CARD_DETECT_MSGS,
++ sizeof(HCD_EVENT_MESSAGE));
++
++ if (NULL == pBusContext->pCardDetectMsgQueue) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't CreateMessageQueue.\n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ status = SDLIB_OSCreateHelper(&pBusContext->CardDetectHelper,
++ CardDetectHelperFunction,
++ NULL);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't OSCreateHelper.\n"));
++ break;
++ }
++
++ pBusContext->InitMask |= HELPER_INIT;
++
++ status = InitializeTimers();
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_BusDriverInitialize can't InitializeTimers.\n"));
++ break;
++ }
++ pBusContext->InitMask |= BD_TIMER_INIT;
++ } while(FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ _SDIO_BusDriverCleanup();
++ }
++
++ return status;
++}
++
++
++/*
++ * _SDIO_BusDriverBusDriverCleanup - call once on driver unloading
++ *
++*/
++void _SDIO_BusDriverCleanup(void) {
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: _SDIO_BusDriverCleanup\n"));
++
++ if (pBusContext->InitMask & BD_TIMER_INIT) {
++ CleanupTimers();
++ }
++
++ if (pBusContext->InitMask & HELPER_INIT) {
++ SDLIB_OSDeleteHelper(&pBusContext->CardDetectHelper);
++ }
++
++ if (pBusContext->pCardDetectMsgQueue != NULL) {
++ SDLIB_DeleteMessageQueue(pBusContext->pCardDetectMsgQueue);
++ pBusContext->pCardDetectMsgQueue = NULL;
++ }
++ /* remove functions */
++ RemoveAllFunctions();
++ /* cleanup all devices */
++ DeleteDevices(NULL);
++ CleanUpBusResources();
++ CriticalSectionDelete(&pBusContext->RequestListCritSection);
++ SemaphoreDelete(&pBusContext->HcdListSem);
++ SemaphoreDelete(&pBusContext->DeviceListSem);
++ SemaphoreDelete(&pBusContext->FunctionListSem);
++ KernelFree(pBusContext);
++ pBusContext = NULL;
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: _SDIO_BusDriverCleanup\n"));
++}
++
++
++/* cleanup hcd */
++static void CleanupHcd(PSDHCD pHcd)
++{
++ SDLIB_OSDeleteHelper(&pHcd->SDIOIrqHelper);
++ CleanupRequestQueue(&pHcd->CompletedRequestQueue);
++ CleanupRequestQueue(&pHcd->RequestQueue);
++ CriticalSectionDelete(&pHcd->HcdCritSection);
++ SemaphoreDelete(&pHcd->ConfigureOpsSem);
++ pHcd->pCurrentRequest = NULL;
++ if (pHcd->pPseudoDev != NULL) {
++ FreeDevice(pHcd->pPseudoDev);
++ pHcd->pPseudoDev = NULL;
++ }
++}
++
++/* set up the hcd */
++static SDIO_STATUS SetupHcd(PSDHCD pHcd)
++{
++ SDIO_STATUS status;
++
++ ZERO_POBJECT(&pHcd->SDIOIrqHelper);
++ ZERO_POBJECT(&pHcd->ConfigureOpsSem);
++ ZERO_POBJECT(&pHcd->HcdCritSection);
++ ZERO_POBJECT(&pHcd->RequestQueue);
++ ZERO_POBJECT(&pHcd->CompletedRequestQueue);
++ pHcd->pPseudoDev = NULL;
++ pHcd->Recursion = 0;
++
++ do {
++
++ pHcd->pPseudoDev = AllocateDevice(pHcd);
++
++ if (NULL == pHcd->pPseudoDev) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ ResetHcdState(pHcd);
++
++ status = SemaphoreInitialize(&pHcd->ConfigureOpsSem,1);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ status = CriticalSectionInit(&pHcd->HcdCritSection);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ status = InitializeRequestQueue(&pHcd->RequestQueue);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ status = InitializeRequestQueue(&pHcd->CompletedRequestQueue);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* create SDIO Irq helper */
++ status = SDLIB_OSCreateHelper(&pHcd->SDIOIrqHelper,
++ SDIOIrqHelperFunction,
++ (PVOID)pHcd);
++ } while(FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ /* undo what we did */
++ CleanupHcd(pHcd);
++ }
++ return status;
++}
++
++
++/*
++ * _SDIO_RegisterHostController - register a host controller bus driver
++ *
++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Register a host controller driver with the bus driver.
++
++ @function name: SDIO_RegisterHostController
++ @prototype: SDIO_STATUS SDIO_RegisterHostController (PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller definition structure.
++
++ @output: none
++
++ @return: SDIO_STATUS - SDIO_STATUS_SUCCESS when successful.
++
++ @notes: Each host controller driver must register with the bus driver when loaded.
++ The driver registers an SDHCD structure initialized with hardware properties
++ and callback functions for bus requests and configuration. On multi-slot
++ hardware ,each slot should be registered with a separate SDHCD structure.
++ The bus driver views each slot as a seperate host controller object.
++ The driver should be prepared to receive configuration requests before
++ this call returns. The host controller driver must unregister itself when
++ shutting down.
++
++ @example: Registering a host controller driver:
++ static SDHCD Hcd = {
++ .pName = "sdio_custom_hcd",
++ .Version = CT_SDIO_STACK_VERSION_CODE, // set stack version code
++ .SlotNumber = 0, // bus driver internal use
++ .Attributes = SDHCD_ATTRIB_BUS_1BIT | SDHCD_ATTRIB_BUS_4BIT | SDHCD_ATTRIB_MULTI_BLK_IRQ
++ SDHCD_ATTRIB_AUTO_CMD12 ,
++ .MaxBytesPerBlock = 2048 // each data block can be up to 2048 bytes
++ .MaxBlocksPerTrans = 1024, // each data transaction can consist of 1024 blocks
++ .MaxSlotCurrent = 500, // max FET switch current rating
++ .SlotVoltageCaps = SLOT_POWER_3_3V, // only 3.3V operation
++ .SlotVoltagePreferred = SLOT_POWER_3_3V,
++ .MaxClockRate = 24000000, // 24 Mhz max operation
++ .pContext = &HcdContext, // set our driver context
++ .pRequest = HcdRequest, // set SDIO bus request callback
++ .pConfigure = HcdConfig, // set SDIO bus configuration callback
++ };
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO HCD - failed to register with host, status =%d\n",
++ status));
++ }
++
++ @see also: SDIO_UnregisterHostController
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_RegisterHostController(PSDHCD pHcd) {
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: _SDIO_RegisterHostController - %s\n",pHcd->pName));
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: Host Controller Stack Version: %d.%d \n",
++ GET_SDIO_STACK_VERSION_MAJOR(pHcd),GET_SDIO_STACK_VERSION_MINOR(pHcd)));
++
++ if (!CHECK_HCD_DRIVER_VERSION(pHcd)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: HCD Major Version Mismatch (hcd = %d, bus driver = %d)\n",
++ GET_SDIO_STACK_VERSION_MAJOR(pHcd), CT_SDIO_STACK_VERSION_MAJOR(g_Version)));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++ /* setup hcd */
++ status = SetupHcd(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ do {
++ INT slotNumber;
++
++ /* protect the HCD list */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->HcdListSem)))) {
++ break; /* wait interrupted */
++ }
++ /* find a unique number for this HCD, must be done under semaphore protection */
++ slotNumber = FirstClearBit(&pBusContext->HcdInUseField);
++ if (slotNumber < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_RegisterHostController, error, slotNumber exceeded\n"));
++ /* fake something */
++ slotNumber = 31;
++ }
++ SetBit(&pBusContext->HcdInUseField, slotNumber);
++ pHcd->SlotNumber = slotNumber;
++ /* add HCD to the end of the internal list */
++ SDListAdd(&pBusContext->HcdList , &pHcd->SDList);
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->HcdListSem)))) {
++ break; /* wait interrupted */
++ }
++ if (pHcd->Attributes & SDHCD_ATTRIB_SLOT_POLLING) {
++ /* post message to card detect helper to do polling */
++ PostCardDetectEvent(pBusContext, EVENT_HCD_CD_POLLING, NULL);
++ }
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ CleanupHcd(pHcd);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_RegisterHostController, error 0x%X.\n", status));
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: _SDIO_RegisterHostController\n"));
++ return status;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Unregister a host controller driver with the bus driver.
++
++ @function name: SDIO_UnregisterHostController
++ @prototype: SDIO_STATUS SDIO_UnregisterHostController (PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller definition structure that was registered.
++
++ @output: none
++
++ @return: SDIO_STATUS - SDIO_STATUS_SUCCESS when successful.
++
++ @notes: Each host controller driver must unregister with the bus driver when
++ unloading. The driver is responsible for halting any outstanding I/O
++ operations. The bus driver will automatically unload function drivers
++ that may be attached assigned to cards inserted into slots.
++
++ @example: Unregistering a host controller driver:
++ if (!SDIO_SUCCESS((status = SDIO_UnregisterHostController(&Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO HCD - failed to unregister with host, status =%d\n",
++ status));
++ }
++
++ @see also: SDIO_RegisterHostController
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_UnregisterHostController(PSDHCD pHcd) {
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: _SDIO_UnregisterHostController\n"));
++
++ /* remove functions associated with the HCD */
++ RemoveHcdFunctions(pHcd);
++ /* remove any devices associated with the HCD */
++ DeleteDevices(pHcd);
++ /* wait for the message queue to be empty, so we don't have any delayed requests going
++ to this device */
++ while(!SDLIB_IsQueueEmpty(pBusContext->pCardDetectMsgQueue)) {
++ /* wait for the messages to be handled */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: _SDIO_UnregisterHostController, waiting on messages\n"));
++ OSSleep(250);
++ }
++
++ /* protect the HCD list */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->HcdListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ ClearBit(&pBusContext->HcdInUseField, pHcd->SlotNumber);
++ /* delete HCD from list */
++ SDListRemove(&pHcd->SDList);
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->HcdListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ /* cleanup anything we allocated */
++ CleanupHcd(pHcd);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: _SDIO_UnregisterHostController\n"));
++ return status;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_UnregisterHostController, error 0x%X.\n", status));
++ return status;
++}
++
++/* documentation headers only for Request and Configure */
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: The bus driver calls the request callback to start an SDIO bus transaction.
++ @function name: Request
++ @prototype: SDIO_STATUS (*pRequest) (struct _SDHCD *pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller structure that was registered
++
++ @output: none
++
++ @return: SDIO_STATUS
++
++ @notes:
++ The bus driver maintains an internal queue of SDREQUEST structures submited by function
++ drivers. The driver should use request macros to obtain a pointer to the current SDREQUEST
++ at the head of the queue. The driver can access the fields of the current request in order
++ to program hardware appropriately. Once the request completes, the driver should update
++ the current request information (final status, response bytes and/or data) and call
++ SDIO_HandleHcdEvent() with the event type of EVENT_HCD_TRANSFER_DONE.
++ The bus driver will remove the current request from the head of the queue and start the next
++ request.
++
++ @example: Example of a typical Request callback:
++ SDIO_STATUS HcdRequest(PSDHCD pHcd)
++ {
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT32 temp = 0;
++ PSDREQUEST pReq;
++ // get the current request
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++ // get controller settings based on response type
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_MMC_R4:
++ case SDREQ_FLAGS_RESP_MMC_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ temp |= CMDDAT_RES_R1_R4_R5;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp |= (CMDDAT_RES_R1_R4_R5 | CMDAT_RES_BUSY);
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp |= CMDDAT_RES_R2;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp |= CMDDAT_RES_R3;
++ break;
++ }
++ // check for data
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ temp |= CMDDAT_DATA_EN;
++ // set data remaining count
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(TRACE_DATA, ("SDIO %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ // write operation
++ }
++ }
++ // .... program hardware, interrupt handler will complete request
++ return SDIO_STATUS_PENDING;
++ }
++
++ @see also: SDIO_HandleHcdEvent
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: The bus driver calls the configure callback to set various options
++ and modes in the host controller hardware.
++
++ @function name: Configure
++ @prototype: SDIO_STATUS (*pConfigure) (struct _SDHCD *pHcd, PSDCONFIG pConfig)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller structure that was registered
++ @input: pConfig - configuration request structure
++
++ @output: none
++
++ @return: SDIO_STATUS
++
++ @notes:
++ The host controller driver recieves configuration requests for options
++ such as slot voltage, bus width, clock rates and interrupt detection.
++ The bus driver guarantees that only one configuration option request
++ can be issued at a time.
++
++ @example: Example of a typical configure callback:
++ SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++ {
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT16 command;
++ // get command
++ command = GET_SDCONFIG_CMD(pConfig);
++ // decode command
++ switch (command){
++ case SDCONFIG_GET_WP:
++ if (GetGpioPinLevel(pHct,SDIO_CARD_WP_GPIO) == WP_POLARITY) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ ClockStartStop(pHct,CLOCK_ON);
++ // sleep a little, should be at least 80 clocks at our lowest clock setting
++ status = OSSleep(100);
++ ClockStartStop(pHct,CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ // request to enable IRQ detection
++ } else {
++ // request to disable IRQ detectioon
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ // request to re-arm the card IRQ detection logic
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ // request to set bus mode
++ {
++ // get bus mode data structure
++ PSDCONFIG_BUS_MODE_DATA pBusMode =
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig);
++ // set bus mode based on settings in bus mode structure
++ // bus mode : pBusMode->BusModeFlags
++ // clock rate : pBusMode->ClockRate
++ }
++ break;
++ case SDCONFIG_POWER_CTRL:
++ // request to set power/voltage
++ {
++ PSDCONFIG_POWER_CTRL_DATA pPowerSetting =
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig);
++ if (pPowerSetting->SlotPowerEnable) {
++ // turn on slot power
++ //
++ } else {
++ // turn off slot power
++ }
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA255 PwrControl: En:%d, VCC:0x%X \n",
++ pPowerSetting->SlotPowerEnable,
++ pPowerSetting->SlotPowerVoltageMask));
++ }
++ break;
++ default:
++ // unsupported
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++ return status;
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++
++/*
++ * Allocate a Device instance
++ */
++PSDDEVICE AllocateDevice(PSDHCD pHcd)
++{
++ PSDDEVICE pDevice;
++
++ pDevice = KernelAlloc(sizeof(SDDEVICE));
++ if (pDevice != NULL) {
++ InitDeviceData(pHcd,pDevice);
++ }
++ return pDevice;
++}
++
++
++/*
++ * Free a Device instance
++ */
++void FreeDevice(PSDDEVICE pDevice)
++{
++ DeinitDeviceData(pDevice);
++ KernelFree(pDevice);
++}
++/*
++ * add this device to the list
++ */
++BOOL AddDeviceToList(PSDDEVICE pDevice)
++{
++ BOOL success = FALSE;
++
++ do {
++ /* protect the driver list */
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pBusContext->DeviceListSem))) {
++ break; /* wait interrupted */
++ }
++
++ /* add new device to the internal list */
++ SDListAdd(&pBusContext->DeviceList , &pDevice->SDList);
++
++ if (!SDIO_SUCCESS(SemaphorePost(&pBusContext->DeviceListSem))) {
++ break;
++ }
++
++ success = TRUE;
++ } while (FALSE);
++
++ return success;
++}
++
++/*
++ * Delete device associated with the HCD
++ * if pHCD is NULL this function cleans up all devices, the caller
++ * better have cleaned up functions first!
++ */
++SDIO_STATUS DeleteDevices(PSDHCD pHcd)
++{
++ SDIO_STATUS status;
++ PSDDEVICE pDevice;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: DeleteDevices hcd:0x%X \n", (INT)pHcd));
++ /* protect the device list */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->DeviceListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pBusContext->DeviceList,pDevice,SDDEVICE,SDList) {
++ /* only remove devices for the hcd or if we are cleaning up all */
++ if ((NULL == pHcd) || (pDevice->pHcd == pHcd)) {
++ SDListRemove(&pDevice->SDList);
++ DeinitDeviceData(pDevice);
++ FreeDevice(pDevice);
++ }
++ }SDITERATE_END;
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->DeviceListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: DeleteDevices \n"));
++ return status;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: DeleteDevice, error exit 0x%X\n", status));
++ return status;
++}
++
++
++static SDIO_STATUS AllocateBusResources(void)
++{
++ INT ii;
++ PSDREQUEST pReq;
++ PSIGNAL_ITEM pSignal;
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("+SDIO Bus Driver: AllocateBusResources (R:%d,S:%d) (CR:%d,MR:%d)(CS:%d,MS:%d) \n",
++ pBusContext->RequestListSize,
++ pBusContext->SignalSemListSize,
++ pBusContext->CurrentRequestAllocations,pBusContext->MaxRequestAllocations,
++ pBusContext->CurrentSignalAllocations,pBusContext->MaxSignalAllocations));
++
++ /* allocate some initial requests */
++ for (ii = 0; ii < pBusContext->RequestListSize; ii++) {
++ pReq = AllocateRequest();
++ if (pReq == NULL) {
++ break;
++ }
++ /* free requests adds the request to the list */
++ FreeRequest(pReq);
++ }
++
++ for (ii = 0; ii < pBusContext->SignalSemListSize; ii++) {
++ pSignal = AllocateSignal();
++ if (pSignal == NULL) {
++ break;
++ }
++ /* freeing it adds it to the list */
++ FreeSignal(pSignal);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: AllocateBusResources\n"));
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++/* cleanup bus resources */
++static void CleanUpBusResources(void)
++{
++ PSDLIST pItem;
++ PSDREQUEST pReq;
++ PSIGNAL_ITEM pSignal;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: CleanUpBusResources (CR:%d,MR:%d)(CS:%d,MS:%d) \n",
++ pBusContext->CurrentRequestAllocations,pBusContext->MaxRequestAllocations,
++ pBusContext->CurrentSignalAllocations,pBusContext->MaxSignalAllocations));
++
++ while(1) {
++ pItem = SDListRemoveItemFromHead(&pBusContext->RequestList);
++ if (NULL == pItem) {
++ break;
++ }
++ /* free the request */
++ pReq = CONTAINING_STRUCT(pItem, SDREQUEST, SDList);
++ if (pReq->InternalFlags & SDBD_ALLOC_IRQ_SAFE_MASK) {
++ KernelFreeIrqSafe(pReq);
++ } else {
++ KernelFree(pReq);
++ }
++ pBusContext->CurrentRequestAllocations--;
++ }
++
++ if (pBusContext->CurrentRequestAllocations != 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Request allocations are not ZERO! (CR:%d)\n",
++ pBusContext->CurrentRequestAllocations));
++ }
++
++ while(1) {
++ pItem = SDListRemoveItemFromHead(&pBusContext->SignalList);
++ if (NULL == pItem) {
++ break;
++ }
++ pSignal = CONTAINING_STRUCT(pItem, SIGNAL_ITEM, SDList);
++ DestroySignal(pSignal);
++ pBusContext->CurrentSignalAllocations--;
++ }
++
++ if (pBusContext->CurrentSignalAllocations != 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Signal allocations are not ZERO! (CR:%d)\n",
++ pBusContext->CurrentRequestAllocations));
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: CleanUpBusResources\n"));
++}
++
++
++/* free a request to the lookaside list */
++void FreeRequest(PSDREQUEST pReq)
++{
++ SDIO_STATUS status;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++ /* protect request list */
++ if (!SDIO_SUCCESS(status)) {
++ return;
++ }
++
++ if ((pBusContext->CurrentRequestAllocations <= pBusContext->MaxRequestAllocations) ||
++ !(pReq->InternalFlags & SDBD_ALLOC_IRQ_SAFE_MASK)) {
++ /* add it to the list */
++ SDListAdd(&pBusContext->RequestList, &pReq->SDList);
++ /* we will hold onto this one */
++ pReq = NULL;
++ } else {
++ /* decrement count */
++ pBusContext->CurrentRequestAllocations--;
++ }
++
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (pReq != NULL) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Free Request allocation (CR:%d,MR:%d)\n",
++ pBusContext->CurrentRequestAllocations,pBusContext->MaxRequestAllocations));
++ if (pReq->InternalFlags & SDBD_ALLOC_IRQ_SAFE_MASK) {
++ KernelFreeIrqSafe(pReq);
++ } else {
++ /* we should never free the ones that were normally allocated */
++ DBG_ASSERT(FALSE);
++ }
++ }
++}
++
++/* allocate a request from the lookaside list */
++PSDREQUEST AllocateRequest(void)
++{
++ PSDLIST pItem;
++ SDIO_STATUS status;
++ PSDREQUEST pReq = NULL;
++ ATOMIC_FLAGS internalflags;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (!SDIO_SUCCESS(status)) {
++ return NULL;
++ }
++
++ if (pBusContext->InitMask & RESOURCE_INIT) {
++ /* check the list, we are now running... */
++ pItem = SDListRemoveItemFromHead(&pBusContext->RequestList);
++ } else {
++ /* we are loading the list with requests at initialization */
++ pItem = NULL;
++ }
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (pItem != NULL) {
++ pReq = CONTAINING_STRUCT(pItem, SDREQUEST, SDList);
++ } else {
++ if (pBusContext->InitMask & RESOURCE_INIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Request List empty..allocating new one (irq-safe) (CR:%d,MR:%d)\n",
++ pBusContext->CurrentRequestAllocations,pBusContext->MaxRequestAllocations));
++ /* the resource list was already allocated, we must be running now.
++ * at run-time, we allocate using the safe IRQ */
++ pReq = (PSDREQUEST)KernelAllocIrqSafe(sizeof(SDREQUEST));
++ /* mark that this one was created using IRQ safe allocation */
++ internalflags = SDBD_ALLOC_IRQ_SAFE_MASK;
++ } else {
++ /* use the normal allocation since we are called at initialization */
++ pReq = (PSDREQUEST)KernelAlloc(sizeof(SDREQUEST));
++ internalflags = 0;
++ }
++
++ if (pReq != NULL) {
++ pReq->InternalFlags = internalflags;
++ /* keep track of allocations */
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++ pBusContext->CurrentRequestAllocations++;
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++ }
++ }
++
++
++ if (pReq != NULL) {
++ /* preserve internal flags */
++ internalflags = pReq->InternalFlags;
++ ZERO_POBJECT(pReq);
++ pReq->InternalFlags = internalflags;
++ }
++
++ return pReq;
++}
++
++void DestroySignal(PSIGNAL_ITEM pSignal)
++{
++ SignalDelete(&pSignal->Signal);
++ KernelFree(pSignal);
++}
++
++PSIGNAL_ITEM BuildSignal(void)
++{
++ PSIGNAL_ITEM pSignal;
++
++ pSignal = (PSIGNAL_ITEM)KernelAlloc(sizeof(SIGNAL_ITEM));
++ if (pSignal != NULL) {
++ /* initialize signal */
++ if (!SDIO_SUCCESS(SignalInitialize(&pSignal->Signal))) {
++ KernelFree(pSignal);
++ pSignal = NULL;
++ }
++ }
++ return pSignal;
++}
++/* free a signal*/
++void FreeSignal(PSIGNAL_ITEM pSignal)
++{
++ SDIO_STATUS status;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (!SDIO_SUCCESS(status)) {
++ return;
++ }
++
++ if (pBusContext->CurrentSignalAllocations <= pBusContext->MaxSignalAllocations) {
++ /* add it to the list */
++ SDListAdd(&pBusContext->SignalList, &pSignal->SDList);
++ /* flag that we are holding onto it */
++ pSignal = NULL;
++ } else {
++ /* decrement count */
++ pBusContext->CurrentSignalAllocations--;
++ }
++
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (pSignal != NULL) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Free signal allocation (CS:%d,MS:%d)\n",
++ pBusContext->CurrentSignalAllocations,pBusContext->MaxSignalAllocations));
++ DestroySignal(pSignal);
++ }
++}
++
++/* allocate a signal from the list */
++PSIGNAL_ITEM AllocateSignal(void)
++{
++ PSDLIST pItem;
++ PSIGNAL_ITEM pSignal;
++ SDIO_STATUS status;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++
++ if (!SDIO_SUCCESS(status)) {
++ return NULL;
++ }
++
++ if (pBusContext->InitMask & RESOURCE_INIT) {
++ /* check the list */
++ pItem = SDListRemoveItemFromHead(&pBusContext->SignalList);
++ } else {
++ /* we are loading the list */
++ pItem = NULL;
++ }
++
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++ if (pItem != NULL) {
++ /* return the one from the list */
++ pSignal = CONTAINING_STRUCT(pItem, SIGNAL_ITEM, SDList);
++ } else {
++ if (pBusContext->InitMask & RESOURCE_INIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Signal List empty..allocating new one (CS:%d,MS:%d)\n",
++ pBusContext->CurrentSignalAllocations,pBusContext->MaxSignalAllocations));
++ }
++ /* just allocate one */
++ pSignal = BuildSignal();
++ status = CriticalSectionAcquireSyncIrq(&pBusContext->RequestListCritSection);
++ if (pSignal != NULL) {
++ pBusContext->CurrentSignalAllocations++;
++ }
++ status = CriticalSectionReleaseSyncIrq(&pBusContext->RequestListCritSection);
++ }
++
++
++ return pSignal;
++}
++
++/*
++ * Issus Bus Request (exposed to function drivers)
++*/
++PSDREQUEST IssueAllocRequest(PSDDEVICE pDev)
++{
++ return AllocateRequest();
++}
++
++/*
++ * Free Request (exposed to function drivers)
++*/
++void IssueFreeRequest(PSDDEVICE pDev, PSDREQUEST pReq)
++{
++ FreeRequest(pReq);
++}
++
++/*
++ * Issus Bus Request (exposed to function drivers)
++*/
++SDIO_STATUS IssueBusRequest(PSDDEVICE pDev, PSDREQUEST pReq)
++{
++ pReq->pFunction = pDev->pFunction;
++ return IssueRequestToHCD(pDev->pHcd,pReq);
++}
++
++
++ /* completion routine for HCD configs, this is synchronized with normal bus requests */
++static void HcdConfigComplete(PSDREQUEST pReq)
++{
++
++ pReq->Status = CALL_HCD_CONFIG((PSDHCD)pReq->pDataBuffer, (PSDCONFIG)pReq->pCompleteContext);
++
++ SignalSet(&((PSIGNAL_ITEM)pReq->pHcdContext)->Signal);
++}
++
++SDIO_STATUS SendSyncedHcdBusConfig(PSDDEVICE pDevice, PSDCONFIG pConfig)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq = NULL;
++ PSIGNAL_ITEM pSignal = NULL;
++
++ do {
++
++ pSignal = AllocateSignal();
++ if (NULL == pSignal) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ /* issue pseudo request to sync this with bus requests */
++ pReq->pCompletion = HcdConfigComplete;
++ pReq->pCompleteContext = pConfig;
++ /* re-use hcd context to store the signal since this request
++ * never actually goes to an HCD */
++ pReq->pHcdContext = pSignal;
++ pReq->pDataBuffer = pDevice->pHcd;
++ /* flag this as barrier in case it may change the bus mode of the HCD */
++ pReq->Flags = SDREQ_FLAGS_PSEUDO | SDREQ_FLAGS_BARRIER | SDREQ_FLAGS_TRANS_ASYNC;
++ pReq->Status = SDIO_STATUS_SUCCESS;
++
++ /* issue request */
++ status = IssueRequestToHCD(pDevice->pHcd,pReq);
++
++ } while (FALSE);
++
++ if (SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Config Request Sync-Op waiting....\n"));
++ status = SignalWait(&pSignal->Signal);
++
++ if (SDIO_SUCCESS(status)) {
++ /* return the result of the configuration request */
++ status = pReq->Status;
++ }
++ }
++
++ /* cleanup */
++ if (pReq != NULL) {
++ FreeRequest(pReq);
++ }
++
++ if (pSignal != NULL) {
++ FreeSignal(pSignal);
++ }
++
++ return status;
++}
++
++/*
++ * Issus bus Configuration (exposed to function drivers)
++*/
++SDIO_STATUS IssueBusConfig(PSDDEVICE pDev, PSDCONFIG pConfig)
++{
++ SDIO_STATUS status;
++ INT cmdLength;
++
++ cmdLength = GET_SDCONFIG_CMD_LEN(pConfig);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++
++ do {
++ /* check buffers and length */
++ if (IS_SDCONFIG_CMD_GET(pConfig) || IS_SDCONFIG_CMD_PUT(pConfig)) {
++ if ((GET_SDCONFIG_CMD_DATA(PVOID,pConfig) == NULL) || (0 == cmdLength)) {
++ break;
++ }
++ }
++
++ switch (GET_SDCONFIG_CMD(pConfig)) {
++ case SDCONFIG_FUNC_ACK_IRQ:
++ status = SDFunctionAckInterrupt(pDev);
++ break;
++ case SDCONFIG_FUNC_ENABLE_DISABLE:
++ if (cmdLength < sizeof(SDCONFIG_FUNC_ENABLE_DISABLE_DATA)) {
++ break;
++ }
++ status = SDEnableFunction(pDev,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_FUNC_ENABLE_DISABLE_DATA,pConfig));
++ break;
++ case SDCONFIG_FUNC_UNMASK_IRQ:
++ status = SDMaskUnmaskFunctionIRQ(pDev,FALSE);
++ break;
++ case SDCONFIG_FUNC_MASK_IRQ:
++ status = SDMaskUnmaskFunctionIRQ(pDev,TRUE);
++ break;
++ case SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC:
++ status = SDSPIModeEnableDisableCRC(pDev,FALSE);
++ break;
++ case SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC:
++ status = SDSPIModeEnableDisableCRC(pDev,TRUE);
++ break;
++ case SDCONFIG_FUNC_ALLOC_SLOT_CURRENT:
++ status = SDAllocFreeSlotCurrent(pDev,
++ TRUE,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_FUNC_SLOT_CURRENT_DATA,pConfig));
++ break;
++ case SDCONFIG_FUNC_FREE_SLOT_CURRENT:
++ status = SDAllocFreeSlotCurrent(pDev, FALSE, NULL);
++ break;
++ case SDCONFIG_FUNC_CHANGE_BUS_MODE:
++
++ status = SetOperationalBusMode(pDev,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_BUS_MODE_DATA,
++ pConfig));
++ break;
++ case SDCONFIG_FUNC_NO_IRQ_PEND_CHECK:
++ status = TryNoIrqPendingCheck(pDev);
++ break;
++ default:
++
++ if (GET_SDCONFIG_CMD(pConfig) & SDCONFIG_FLAGS_HC_CONFIG) {
++ /* synchronize config requests with busrequests */
++ status = SendSyncedHcdBusConfig(pDev,pConfig);
++ } else {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: IssueBusConfig - unknown command:0x%X \n",
++ GET_SDCONFIG_CMD(pConfig)));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++ break;
++ }
++ } while(FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: IssueBusConfig - Error in command:0x%X, Buffer:0x%X, Length:%d Err:%d\n",
++ GET_SDCONFIG_CMD(pConfig),
++ GET_SDCONFIG_CMD_DATA(INT,pConfig),
++ cmdLength, status));
++ }
++ return status;
++}
++
++/* start a request */
++static INLINE SDIO_STATUS StartHcdRequest(PSDHCD pHcd, PSDREQUEST pReq)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ if ((pReq->pFunction != NULL) && (pReq->pFunction->Flags & SDFUNCTION_FLAG_REMOVING)) {
++ /* this device or function is going away, fail any new requests */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: StartHcdRequest, fail request 0x%X, device is removing\n", (UINT)pReq));
++ pReq->Status = SDIO_STATUS_CANCELED;
++ return SDIO_STATUS_SDREQ_QUEUE_FAILED;
++ }
++
++ status = _AcquireHcdLock(pHcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to acquire HCD request lock: Err:%d\n", status));
++ pReq->Status = SDIO_STATUS_SDREQ_QUEUE_FAILED;
++ return SDIO_STATUS_SDREQ_QUEUE_FAILED;
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_QUEUE_HEAD) {
++ /* caller wants this request queued to the head */
++
++ /* a completion routine for a barrier request is called
++ * while the queue is busy. A barrier request can
++ * insert a new request at the head of the queue */
++ DBG_ASSERT(IsQueueBusy(&pHcd->RequestQueue));
++ QueueRequestToFront(&pHcd->RequestQueue,pReq);
++ } else {
++ /* insert in queue at tail */
++ QueueRequest(&pHcd->RequestQueue,pReq);
++
++ /* is queue busy ? */
++ if (IsQueueBusy(&pHcd->RequestQueue)) {
++ /* release lock */
++ status = _ReleaseHcdLock(pHcd);
++ /* controller is busy already, no need to call the hcd */
++ return SDIO_STATUS_PENDING;
++ }
++ /* mark it as busy */
++ MarkQueueBusy(&pHcd->RequestQueue);
++ }
++
++ /* remove item from head and set current request */
++ SET_CURRENT_REQUEST(pHcd, DequeueRequest(&pHcd->RequestQueue));
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ CHECK_HCD_RECURSE(pHcd, pHcd->pCurrentRequest);
++ }
++ /* release lock */
++ status = _ReleaseHcdLock(pHcd);
++ /* controller was not busy, call into HCD to process current request */
++ status = CallHcdRequest(pHcd);
++ return status;
++}
++
++
++/* used by CMD12,CMD13 to save the original completion routine */
++#define GET_BD_RSV_REQUEST_COMPLETION(pR) (PSDEQUEST_COMPLETION)(pR)->pBdRsv1
++#define SET_BD_RSV_REQUEST_COMPLETION(pR,c) (pR)->pBdRsv1 = (PVOID)(c)
++
++/* used by CMD12 processing to save/restore the original data transfer status */
++#define GET_BD_RSV_ORIG_STATUS(pR) (SDIO_STATUS)(pR)->pBdRsv2
++#define SET_BD_RSV_ORIG_STATUS(pR,s) (pR)->pBdRsv2 = (PVOID)(s)
++
++/* used by CMD13 processing to get/set polling count */
++#define GET_BD_RSV_STATUS_POLL_COUNT(pR) (INT)(pR)->pBdRsv2
++#define SET_BD_RSV_STATUS_POLL_COUNT(pR,s) (pR)->pBdRsv2 = (PVOID)(s)
++
++/* used by CMD55 processing to save the second part of the request */
++#define GET_BD_RSV_ORIG_REQ(pR) (PSDREQUEST)(pR)->pBdRsv1
++#define SET_BD_RSV_ORIG_REQ(pR,r) (pR)->pBdRsv1 = (PVOID)(r)
++
++/* used by all to save HCD */
++#define GET_BD_RSV_HCD(pR) (PSDHCD)(pR)->pBdRsv3
++#define SET_BD_RSV_HCD(pR,h) (pR)->pBdRsv3 = (PVOID)(h)
++#ifndef CT_CONFIG_NO_SDMMC
++static void CMD13CompletionBarrier(PSDREQUEST pReq);
++
++static INLINE void SetupCMD13(PSDHCD pHcd, PSDREQUEST pReq)
++{
++ pReq->Command = CMD13;
++ /* sequence must be atomic, queue it to the head and flag as a barrier */
++ pReq->Flags = SDREQ_FLAGS_QUEUE_HEAD | SDREQ_FLAGS_BARRIER | SDREQ_FLAGS_TRANS_ASYNC;
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ pReq->Argument = 0;
++ pReq->Flags |= SDREQ_FLAGS_RESP_R2;
++ } else {
++ pReq->Flags |= SDREQ_FLAGS_RESP_R1;
++ pReq->Argument = (UINT32)pHcd->CardProperties.RCA << 16;
++ }
++ /* insert completion */
++ pReq->pCompletion = CMD13CompletionBarrier;
++}
++
++/* CMD13 (GET STATUS) completion */
++static void CMD13CompletionBarrier(PSDREQUEST pReq)
++{
++ PSDEQUEST_COMPLETION pOrigCompletion = GET_BD_RSV_REQUEST_COMPLETION(pReq);
++ PSDHCD pHcd = GET_BD_RSV_HCD(pReq);
++ INT pollingCount = GET_BD_RSV_STATUS_POLL_COUNT(pReq);
++ BOOL doCompletion = TRUE;
++ UINT32 cardStatus;
++
++ DBG_ASSERT(pOrigCompletion != NULL);
++ DBG_ASSERT(pHcd != NULL);
++ DBG_PRINT(SDIODBG_REQUESTS, ("+SDIO Bus Driver: CMD13CompletionBarrier (cnt:%d) \n",pollingCount));
++
++ do {
++ if (!SDIO_SUCCESS(pReq->Status)) {
++ break;
++ }
++
++ cardStatus = SD_R1_GET_CARD_STATUS(pReq->Response);
++
++ if (cardStatus & SD_CS_TRANSFER_ERRORS) {
++ DBG_PRINT(SDIODBG_REQUESTS,("SDIO Bus Driver: Card transfer errors : 0x%X \n",cardStatus));
++ pReq->Status = SDIO_STATUS_PROGRAM_STATUS_ERROR;
++ break;
++ }
++
++ if (SD_CS_GET_STATE(cardStatus) != SD_CS_STATE_PRG) {
++ DBG_PRINT(SDIODBG_REQUESTS,("SDIO Bus Driver: Card programming done \n"));
++ break;
++ }
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Card still programming.. \n"));
++ pollingCount--;
++
++ if (pollingCount < 0) {
++ pReq->Status = SDIO_STATUS_PROGRAM_TIMEOUT;
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: card programming timeout!\n"));
++ break;
++ }
++
++ doCompletion = FALSE;
++ /* keep trying */
++ SET_BD_RSV_STATUS_POLL_COUNT(pReq, pollingCount);
++ SetupCMD13(pHcd,pReq);
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: re-issuing CMD13 \n"));
++ /* re-issue */
++ IssueRequestToHCD(pHcd, pReq);
++
++ } while (FALSE);
++
++
++ if (doCompletion) {
++ /* restore original completion routine */
++ pReq->pCompletion = pOrigCompletion;
++ /* call original completion routine */
++ pOrigCompletion(pReq);
++ }
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: CMD13CompletionBarrier \n"));
++}
++
++/* command 13 (GET STATUS) preparation */
++static void PrepCMD13Barrier(PSDREQUEST pReq)
++{
++ SDIO_STATUS status = pReq->Status;
++ PSDHCD pHcd = GET_BD_RSV_HCD(pReq);
++ INT pollingCount;
++ PSDEQUEST_COMPLETION pOrigCompletion = GET_BD_RSV_REQUEST_COMPLETION(pReq);
++
++ DBG_ASSERT(pHcd != NULL);
++ DBG_ASSERT(pOrigCompletion != NULL);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("+SDIO Bus Driver: PrepCMD13Barrier \n"));
++
++ if (SDIO_SUCCESS(status)) {
++ /* re-use the request for CMD13 */
++ SetupCMD13(pHcd,pReq);
++ /* set polling count to a multiple of the Block count, if the BlockCount was
++ * zeroed by the HCD, then set it to 1X multiplier */
++ pollingCount = max(pBusContext->CMD13PollingMultiplier,
++ pBusContext->CMD13PollingMultiplier * (INT)pReq->BlockCount);
++ /* initialize count */
++ SET_BD_RSV_STATUS_POLL_COUNT(pReq, pollingCount);
++ /* re-issue it, we can call IssueRequest here since we are re-using the request */
++ IssueRequestToHCD(pHcd, pReq);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Request Failure (%d) , CMD13 bypassed.\n",status));
++ /* call the original completion routine */
++ pOrigCompletion(pReq);
++ }
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: PrepCMD13Barrier (%d) \n",status));
++}
++
++/* CMD12 completion */
++static void CMD12Completion(PSDREQUEST pReq)
++{
++ PSDEQUEST_COMPLETION pOrigCompletion = GET_BD_RSV_REQUEST_COMPLETION(pReq);
++
++ DBG_ASSERT(pOrigCompletion != NULL);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("+SDIO Bus Driver: CMD12Completion \n"));
++
++ /* restore original completion routine */
++ pReq->pCompletion = pOrigCompletion;
++
++ if (SDIO_SUCCESS(pReq->Status)) {
++ /* if CMD12 succeeds, we want to return the result of the original
++ * request */
++ pReq->Status = GET_BD_RSV_ORIG_STATUS(pReq);
++ DBG_PRINT(SDIODBG_REQUESTS,
++ ("SDIO Bus Driver: PrepCMD12Completion original status %d \n",pReq->Status));
++ }
++ /* call original completion routine */
++ pOrigCompletion(pReq);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: CMD12Completion \n"));
++}
++
++/* CMD12 preparation */
++static void PrepCMD12Barrier(PSDREQUEST pReq)
++{
++
++ SDIO_STATUS status = pReq->Status;
++ PSDHCD pHcd = GET_BD_RSV_HCD(pReq);
++ PSDEQUEST_COMPLETION pOrigCompletion = GET_BD_RSV_REQUEST_COMPLETION(pReq);
++
++ DBG_ASSERT(pHcd != NULL);
++ DBG_ASSERT(pOrigCompletion != NULL);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("+SDIO Bus Driver: PrepCMD12Barrier \n"));
++
++ if (SDIO_SUCCESS(status) || /* only issue CMD12 on success or specific bus errors */
++ (SDIO_STATUS_BUS_READ_TIMEOUT == status) ||
++ (SDIO_STATUS_BUS_READ_CRC_ERR == status) ||
++ (SDIO_STATUS_BUS_WRITE_ERROR == status)) {
++ if (!CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ if (!ForceAllRequestsAsync()) {
++ /* clear the call bit as an optimization, note clearing it wholesale here will
++ * allow request processing to recurse one more level */
++ AtomicTest_Clear(&pHcd->HcdFlags, HCD_REQUEST_CALL_BIT);
++ }
++ }
++ /* re-use the request for CMD12 */
++ pReq->Command = CMD12;
++ pReq->Argument = 0;
++
++ /* if the data transfer was successful, check for transfer check */
++ if (SDIO_SUCCESS(status) &&
++ (pReq->Flags & SDREQ_FLAGS_AUTO_TRANSFER_STATUS)) {
++ /* original data request requires a transfer status check, which is another
++ * barrier request */
++ pReq->Flags = SDREQ_FLAGS_RESP_R1B | SDREQ_FLAGS_QUEUE_HEAD | SDREQ_FLAGS_BARRIER |
++ SDREQ_FLAGS_TRANS_ASYNC;
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: PrepCMD12Barrier , chaining CMD13 \n"));
++ /* switch out completion to send the CMD13 next */
++ pReq->pCompletion = PrepCMD13Barrier;
++ } else {
++ pReq->Flags = SDREQ_FLAGS_RESP_R1B | SDREQ_FLAGS_QUEUE_HEAD | SDREQ_FLAGS_TRANS_ASYNC;
++ pReq->pCompletion = CMD12Completion;
++ }
++
++ /* save the original data transfer request status */
++ SET_BD_RSV_ORIG_STATUS(pReq,status);
++ /* re-issue it, we can call IssueRequest here since we are re-using the request */
++ IssueRequestToHCD(pHcd, pReq);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Request Failure (%d) , CMD12 bypassed.\n",status));
++ /* call the original completion routine */
++ pOrigCompletion(pReq);
++ }
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: PrepCMD12Barrier (%d) \n",status));
++}
++
++
++/* CMD55 barrier - this is a special barrier completion routine, we have to submit the second
++ * part of the command command sequence atomically */
++static void CMD55CompletionBarrier(PSDREQUEST pReq)
++{
++ SDIO_STATUS status = pReq->Status;
++ PSDREQUEST pOrigReq = GET_BD_RSV_ORIG_REQ(pReq);
++ PSDHCD pHcd = GET_BD_RSV_HCD(pReq);
++ BOOL doCompletion = FALSE;
++
++ DBG_ASSERT(pOrigReq != NULL);
++ DBG_ASSERT(pHcd != NULL);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("+SDIO Bus Driver: CMD55Completion \n"));
++
++ do {
++
++ if (!SDIO_SUCCESS(status)) {
++ /* command 55 failed */
++ pOrigReq->Status = status;
++ doCompletion = TRUE;
++ break;
++ }
++
++ if (!(SD_R1_GET_CARD_STATUS(pReq->Response) & SD_CS_APP_CMD)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Card is not accepting CMD55, status:0x%X \n",
++ SD_R1_GET_CARD_STATUS(pReq->Response)));
++ pOrigReq->Status = SDIO_STATUS_INVALID_COMMAND;
++ doCompletion = TRUE;
++ break;
++ }
++
++ if (!CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ if (!ForceAllRequestsAsync()) {
++ AtomicTest_Clear(&pHcd->HcdFlags, HCD_REQUEST_CALL_BIT);
++ }
++ }
++
++ /* flag the original request to queue to the head */
++ pOrigReq->Flags |= SDREQ_FLAGS_QUEUE_HEAD;
++ /* submit original request, we cannot call IssueRequestHCD() here because the
++ * original request has already gone through IssueRequestHCD() already */
++ status = StartHcdRequest(pHcd, pOrigReq);
++
++ if (SDIO_STATUS_PENDING == status) {
++ break;
++ }
++
++ pOrigReq->Status = status;
++
++ if (SDIO_STATUS_SDREQ_QUEUE_FAILED == status) {
++ /* never made it to the queue */
++ doCompletion = TRUE;
++ break;
++ }
++
++ /* request completed in-line */
++ _SDIO_HandleHcdEvent(pHcd, EVENT_HCD_TRANSFER_DONE);
++
++ } while (FALSE);
++
++ if (doCompletion) {
++ DoRequestCompletion(pOrigReq, pHcd);
++ }
++
++ /* free the CMD55 request */
++ FreeRequest(pReq);
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: CMD55Completion \n"));
++}
++
++#endif
++
++/* synch completion routine */
++static void SynchCompletion(PSDREQUEST pRequest)
++{
++ PSIGNAL_ITEM pSignal;
++
++ pSignal = (PSIGNAL_ITEM)pRequest->pCompleteContext;
++ DBG_ASSERT(pSignal != NULL);
++ if (!SDIO_SUCCESS(SignalSet(&pSignal->Signal))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: SynchCompletion - signal failed \n"));
++ }
++
++}
++
++/*
++ * Issue a request to the host controller
++ *
++ *
++ * The following flags are handled internally by the bus driver to guarantee atomicity.
++ *
++ * SDREQ_FLAGS_APP_CMD - SD Extended commands requiring CMD55 to precede the actual command
++ * SDREQ_FLAGS_AUTO_CMD12 - Memory Card Data transfer needs CMD12 to stop transfer
++ * (multi-block reads/writes)
++ * SDREQ_FLAGS_AUTO_TRANSFER_STATUS - Memory card data transfer needs transfer status polling
++ * using CMD13
++ *
++ * These request flags require additional commands prepended or appended to the original command
++ *
++ * The order of command execution :
++ *
++ * Order Condition Command Issued
++ * -------------------------------------------------------------
++ * 1. If APP_CMD CMD55 issued.
++ * 2. Always Caller command issued.
++ * 3. If AUTO_CMD12 CMD12 issued.
++ * 4. If AUTO_TRANSFER_STATUS CMD13 issued until card programming is complete
++*/
++SDIO_STATUS IssueRequestToHCD(PSDHCD pHcd, PSDREQUEST pReq)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSIGNAL_ITEM pSignal = NULL;
++ BOOL handleFailedReqSubmit = FALSE;
++
++ CLEAR_INTERNAL_REQ_FLAGS(pReq);
++
++ do {
++ /* mark request in-use */
++ ATOMIC_FLAGS internal = AtomicTest_Set(&pReq->InternalFlags, SDBD_PENDING);
++ if (internal & (1<<SDBD_PENDING)) {
++ DBG_ASSERT_WITH_MSG(FALSE,
++ "SDIO Bus Driver: IssueRequestToHCD - request already in use \n");
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Request already in use: 0x%X",(INT)pReq));
++ }
++
++ if (!(pReq->Flags & SDREQ_FLAGS_TRANS_ASYNC)) {
++ /* caller wants synchronous operation, insert our completion routine */
++ pReq->pCompletion = SynchCompletion;
++ pSignal = AllocateSignal();
++ if (NULL == pSignal) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ pReq->Status = SDIO_STATUS_NO_RESOURCES;
++ handleFailedReqSubmit = TRUE;
++ /* no need to continue */
++ break;
++ }
++ pReq->pCompleteContext = (PVOID)pSignal;
++ }
++
++
++ #ifndef CT_CONFIG_NO_SDMMC
++
++
++ if ((pReq->Flags & SDREQ_FLAGS_AUTO_CMD12) &&
++ !(pHcd->Attributes & SDHCD_ATTRIB_AUTO_CMD12) &&
++ !(IS_HCD_BUS_MODE_SPI(pHcd) && IS_SDREQ_WRITE_DATA(pReq->Flags))) {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Auto CMD12 on Request:0x%08X \n",(INT)pReq));
++ /* caller wants CMD12 auto-issued and the HCD does not support it */
++ /* setup caller's request as a barrier and replace their completion routine */
++ pReq->Flags |= SDREQ_FLAGS_BARRIER;
++ /* take off the flag, since the BD will be issuing it */
++ pReq->Flags &= ~SDREQ_FLAGS_AUTO_CMD12;
++ /* save original completion */
++ SET_BD_RSV_REQUEST_COMPLETION(pReq,pReq->pCompletion);
++ /* save the HCD we are on */
++ SET_BD_RSV_HCD(pReq,pHcd);
++ /* use completion for preping CMD12 */
++ pReq->pCompletion = PrepCMD12Barrier;
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_AUTO_TRANSFER_STATUS) {
++ /* caller wants transfer status checked. If a CMD12
++ * barrier request has been setup we let the CMD12 completion take care
++ * of setting up the transfer check */
++ if (pReq->pCompletion != PrepCMD12Barrier) {
++ /* make CMD13 prep a barrier */
++ pReq->Flags |= SDREQ_FLAGS_BARRIER;
++ /* save original completion */
++ SET_BD_RSV_REQUEST_COMPLETION(pReq,pReq->pCompletion);
++ /* save the HCD we are on */
++ SET_BD_RSV_HCD(pReq,pHcd);
++ /* use completion for preping CMD13 */
++ pReq->pCompletion = PrepCMD13Barrier;
++ }
++ }
++
++ /* check app command, the two command sequence must be handled atomically */
++ if (pReq->Flags & SDREQ_FLAGS_APP_CMD) {
++ PSDREQUEST pCmd55;
++ /* allocate request to handle initial CMD55 command */
++ pCmd55 = AllocateRequest();
++ if (NULL == pCmd55) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ pReq->Status = SDIO_STATUS_NO_RESOURCES;
++ /* complete the caller's request with error */
++ handleFailedReqSubmit = TRUE;
++ /* no need to continue */
++ break;
++ }
++ /* first submit CMD55 */
++ /* set RCA */
++ pCmd55->Argument = pHcd->CardProperties.RCA << 16;
++ /* mark as a barrier request */
++ pCmd55->Flags = SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_BARRIER | SDREQ_FLAGS_TRANS_ASYNC;
++ pCmd55->Command = CMD55;
++ /* call our barrier completion routine when done */
++ pCmd55->pCompletion = CMD55CompletionBarrier;
++ /* save request and target HCD */
++ SET_BD_RSV_ORIG_REQ(pCmd55,pReq);
++ SET_BD_RSV_HCD(pCmd55,pHcd);
++ /* recursively start the CMD55 request, since the CMD55 is a barrier
++ * request, it's completion routine will submit the actual request
++ * atomically */
++ status = IssueRequestToHCD(pHcd, pCmd55);
++
++ } else
++
++#endif // CT_CONFIG_NO_SDMMC
++
++
++ {
++ /* start the normal request */
++ status = StartHcdRequest(pHcd,pReq);
++ }
++
++
++ if (SDIO_STATUS_SDREQ_QUEUE_FAILED == status) {
++ handleFailedReqSubmit = TRUE;
++ /* no need to continue, clean up at the end */
++ break;
++ }
++
++ /* at this point, the request was either queued or was processed by the
++ * HCD */
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: HCD returned status:%d on request: 0x%X, (CMD:%d) \n",
++ status, (INT)pReq, pReq->Command));
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* the HCD completed the request within the HCD request callback,
++ * check and see if this is a synchronous request */
++ if (pSignal != NULL) {
++ /* it was synchronous */
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Sync-Op signal wait bypassed \n"));
++ /* NULL out completion info, there's no need to
++ * signal the semaphore */
++ pReq->pCompletion = NULL;
++
++ } else {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Async operation completed in-line \n"));
++ /* this was an async call, always return pending */
++ status = SDIO_STATUS_PENDING;
++ }
++ /* process this completed transfer on behalf of the HCD */
++ _SDIO_HandleHcdEvent(pHcd, EVENT_HCD_TRANSFER_DONE);
++
++ /* done processing */
++ break;
++ }
++ /* I/O is now pending, could be sync or async */
++ /* check for synch op */
++ if (pSignal != NULL) {
++ /* wait for completion */
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Sync-Op signal waiting....\n"));
++ /* this is not interruptable, as the HCD must complete it. */
++ status = SignalWait(&pSignal->Signal);
++ /* don't need the signal anymore */
++ FreeSignal(pSignal);
++ pSignal = NULL;
++
++ /* note: it is safe to touch pReq since we own
++ * the completion routine for synch transfers */
++
++ /* check signal wait status */
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver - IssueRequestToHCD: Synch transfer - signal wait failed, cancelling req 0X%X\n",
++ (UINT)pReq));
++ pReq->Status = SDIO_STATUS_CANCELED;
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Sync-Op woke up\n"));
++ /* return the completion status of the request */
++ status = pReq->Status;
++ } else {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Async operation Pending \n"));
++ }
++
++ } while (FALSE);
++
++ /* see if we need to clean up failed submissions */
++ if (handleFailedReqSubmit) {
++ /* make sure this is cleared */
++ AtomicTest_Clear(&pReq->InternalFlags, SDBD_PENDING);
++ /* the request processing failed before it was submitted to the HCD */
++ /* note: since it never made it to the queue we can touch pReq */
++ if (pReq->Flags & SDREQ_FLAGS_TRANS_ASYNC) {
++ /* for ASYNC requests, we need to call the completion routine */
++ DoRequestCompletion(pReq, pHcd);
++ /* return pending for all ASYNC requests */
++ status = SDIO_STATUS_PENDING;
++ }
++ }
++
++ /* check if we need to clean up the signal */
++ if (pSignal != NULL) {
++ /* make sure this is freed */
++ FreeSignal(pSignal);
++ }
++ /* return status */
++ return status;
++}
++
++/* documentation for configuration requests */
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Enable or Disable the SDIO Function
++
++ @function name: SDCONFIG_FUNC_ENABLE_DISABLE
++ @prototype: SDCONFIG_FUNC_ENABLE_DISABLE
++ @category: PD_Reference
++
++ @input: SDCONFIG_FUNC_ENABLE_DISABLE_DATA - Enable Data structure
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ uses the SDCONFIG_FUNC_ENABLE_DISABLE_DATA structure. The caller must set the
++ EnableFlags and specify the TimeOut value in milliseconds. The TimeOut
++ value is used for polling the I/O ready bit. This command returns a status
++ of SDIO_STATUS_FUNC_ENABLE_TIMEOUT if the ready bit was not set/cleared
++ by the card within the timeout period.
++
++ @example: Example of enabling an I/O function:
++ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
++ fData.TimeOut = 500;
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData,
++ sizeof(fData));
++
++ @see also: SDLIB_IssueConfig
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Unmask the function's IRQ
++
++ @function name: SDCONFIG_FUNC_UNMASK_IRQ
++ @prototype: SDCONFIG_FUNC_UNMASK_IRQ
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ unmasks the IRQ for the I/O function. This request sets the function's
++ interrupt enable bit in the INTENABLE register in the
++ common register space.
++
++ @example: Example of unmasking interrupt :
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_UNMASK_IRQ,
++ NULL,
++ 0);
++
++ @see also: SDCONFIG_FUNC_MASK_IRQ
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Mask the function's IRQ
++
++ @function name: SDCONFIG_FUNC_MASK_IRQ
++ @prototype: SDCONFIG_FUNC_MASK_IRQ
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ masks the IRQ for the I/O function.
++
++ @example: Example of unmasking interrupt :
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_MASK_IRQ,
++ NULL,
++ 0);
++
++ @see also: SDCONFIG_FUNC_UNMASK_IRQ
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Acknowledge that the function's IRQ has been handled
++
++ @function name: SDCONFIG_FUNC_ACK_IRQ
++ @prototype: SDCONFIG_FUNC_ACK_IRQ
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ indicates to the bus driver that the function driver has handled the
++ interrupt. The bus driver will notify the host controller to unmask the
++ interrupt source. SDIO interrupts are level triggered and are masked at the
++ host controller level until all function drivers have indicated that they
++ have handled their respective interrupt. This command can be issued in either
++ the IRQ handler or asynchronous IRQ handler.
++
++ @example: Example of acknowledging an interrupt :
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_ACK_IRQ,
++ NULL,
++ 0);
++
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Disable SD/MMC/SDIO card CRC checking.
++
++ @function name: SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC
++ @prototype: SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ issues CMD59 to disable SPI-CRC checking and requests the host controller
++ driver to stop checking the CRC. This is typically used in systems where
++ CRC checking is not required and performance is improved if the CRC checking
++ is ommitted (i.e. SPI implementations without hardware CRC support).
++
++ @example: Example of disabling SPI CRC checking:
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC,
++ NULL,
++ 0);
++
++ @see also: SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Enable SD/MMC/SDIO card CRC checking.
++
++ @function name: SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC
++ @prototype: SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ issues CMD59 to enable SPI-CRC checking and requests the host controller
++ driver to generate valid CRCs for commands and data as well as
++ check the CRC in responses and incomming data blocks.
++
++ @example: Example of enabling SPI CRC checking:
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_SPI_MODE_ENABLE_CRC,
++ NULL,
++ 0);
++
++ @see also: SDCONFIG_FUNC_SPI_MODE_DISABLE_CRC
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Allocate slot current for a card function.
++
++ @function name: SDCONFIG_FUNC_ALLOC_SLOT_CURRENT
++ @prototype: SDCONFIG_FUNC_ALLOC_SLOT_CURRENT
++ @category: PD_Reference
++
++ @input: SDCONFIG_FUNC_SLOT_CURRENT_DATA
++
++ @output: SDCONFIG_FUNC_SLOT_CURRENT_DATA
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ requests an allocation of slot current to satisfy the power requirements
++ of the function. The command uses the SDCONFIG_FUNC_SLOT_CURRENT_DATA
++ data structure to pass the required current in mA. Slot current allocation
++ is not cummulative and this command should only be issued once by each function
++ driver with the worse case slot current usage.
++ The command returns SDIO_STATUS_NO_RESOURCES if the
++ requirement cannot be met by the host hardware. The SlotCurrent field will
++ contain the remaining current available to the slot. The slot current should
++ be allocated before the function is enabled using SDCONFIG_FUNC_ENABLE_DISABLE.
++ When a function driver is unloaded it should free the slot current allocation
++ by using the SDCONFIG_FUNC_FREE_SLOT_CURRENT command.
++
++ @example: Example of allocating slot current:
++ slotCurrent.SlotCurrent = 150; // 150 mA
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
++ &slotCurrent,
++ sizeof(slotCurrent));
++
++
++ @see also: SDCONFIG_FUNC_FREE_SLOT_CURRENT
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Free slot current for a card function.
++
++ @function name: SDCONFIG_FUNC_FREE_SLOT_CURRENT
++ @prototype: SDCONFIG_FUNC_FREE_SLOT_CURRENT
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ frees the allocated current for a card function. This command should be
++ issued only once (per function) and only after an allocation was successfully made.
++
++ @example: Example of freeing slot current:
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_FREE_SLOT_CURRENT,
++ NULL,
++ 0);
++
++ @see also: SDCONFIG_FUNC_ALLOC_SLOT_CURRENT
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Set the bus mode for the SD/SDIO card.
++
++ @function name: SDCONFIG_FUNC_CHANGE_BUS_MODE
++ @prototype: SDCONFIG_FUNC_CHANGE_BUS_MODE
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ alters the card's bus mode (width and clock rate) to a driver specified
++ value. The driver must read the current bus mode flags, modify if necessary
++ and pass the value in the SDCONFIG_BUS_MODE_DATA structure.
++ If the bus width is changed (1 or 4 bit) the caller must adjust the mode flags
++ for the new width. Cards cannot be switched between 1/4 bit and SPI mode.
++ Switching to or from SPI mode requires a power cycle. Adjustments to the clock
++ rate is immediate on the next bus transaction. The actual clock rate value is
++ limited by the host controller and is reported in the ClockRate field when the
++ command completes successfully.
++ The bus mode change is card wide and may affect other SDIO functions on
++ multi-function cards. Use this feature with caution. This feature should NOT be
++ used to dynamically control clock rates during runtime and should only be used
++ at card initialization. Changing the bus mode must be done with SDIO function
++ interrupts masked.
++ This request can block and must only be called from a schedulable context.
++
++ @example: Example of changing the clock rate:
++ SDCONFIG_BUS_MODE_DATA busSettings;
++ ZERO_OBJECT(busSettings);
++ // get current bus flags and keep the same bus width
++ busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(pInstance->pDevice);
++ busSettings.ClockRate = 8000000; // adjust clock to 8 Mhz
++ // issue config request to override clock rate
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_CHANGE_BUS_MODE,
++ &busSettings,
++ sizeof(SDCONFIG_BUS_MODE_DATA));
++
++ @see also: SDDEVICE_GET_BUSMODE_FLAGS
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get the debug level of the underlying host controller driver.
++
++ @function name: SDCONFIG_GET_HCD_DEBUG
++ @prototype: SDCONFIG_GET_HCD_DEBUG
++ @category: PD_Reference
++
++ @input: none
++
++ @output: CT_DEBUG_LEVEL
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ requests the current debug level of the HCD driver. This API is useful for
++ saving the current debug level of the HCD prior to issuing SDCONFIG_SET_HCD_DEBUG
++ in order to increase the verbosity of the HCD. This API should be used only for
++ debugging purposes. If multiple functions attempt to save and set the HCD debug
++ level simultanously, the final debug level will be unknown. Not all HCDs support
++ this command.
++
++ @example: Example of saving the debug level:
++ CT_DEBUG_LEVEL savedDebug;
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_GET_HCD_DEBUG,
++ &savedDebug,
++ sizeof(savedDebug));
++
++ @see also: SDCONFIG_SET_HCD_DEBUG
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Set the debug level of the underlying host controller driver.
++
++ @function name: SDCONFIG_SET_HCD_DEBUG
++ @prototype: SDCONFIG_SET_HCD_DEBUG
++ @category: PD_Reference
++
++ @input: CT_DEBUG_LEVEL
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command
++ sets the current debug level of the HCD driver. This API is useful for
++ setting the debug level of the HCD programatically for debugging purposes.
++ If multiple functions attempt to save and set the HCD debug
++ level simultanously, the final debug level will be unknown. Not all HCDs support
++ this request.
++
++ @example: Example of setting the debug level:
++ CT_DEBUG_LEVEL setDebug = 15;
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_GET_HCD_DEBUG,
++ &setDebug,
++ sizeof(setDebug));
++
++ @see also: SDCONFIG_GET_HCD_DEBUG
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Instruct the bus driver to not check the SDIO card interrupt pending
++ register on card interrupts, if possible.
++
++ @function name: SDCONFIG_FUNC_NO_IRQ_PEND_CHECK
++ @prototype: SDCONFIG_FUNC_NO_IRQ_PEND_CHECK
++ @category: PD_Reference
++
++ @input: none
++
++ @output: none
++
++ @return: SDIO Status
++
++ @notes: This command code is used in the SDLIB_IssueConfig() API. The command instructs the
++ bus driver to skip checking the card interrupt pending register on each card
++ interrupt. The bus driver will assume the function is interrupting and immediately start
++ the interrupt processing stage. This option is only valid for single function cards.
++ The bus driver will reject the command for a card with more than 1 function.
++ For single function cards, this can improve interrupt response time.
++
++ @example: Example of skipping IRQ pending checks:
++
++ status = SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_NO_IRQ_PEND_CHECK,
++ NULL,
++ 0);
++
++ @see also: SDLIB_IssueConfig
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+Index: linux-2.6.22/drivers/sdio/busdriver/sdio_bus_events.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/sdio_bus_events.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1073 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bus_events.c
++
++ at abstract: OS independent bus driver support
++
++#notes: this file contains various event handlers and helpers
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDBUSDRIVER
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "_busdriver.h"
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/mmc_defs.h>
++
++static SDIO_STATUS ScanSlotForCard(PSDHCD pHcd,
++ PBOOL pCardPresent);
++static void GetPendingIrqComplete(PSDREQUEST pReq);
++static void ProcessPendingIrqs(PSDHCD pHcd, UINT8 IntPendingMsk);
++
++/*
++ * DeviceDetach - tell core a device was removed from a slot
++*/
++SDIO_STATUS DeviceDetach(PSDHCD pHcd)
++{
++ SDCONFIG_SDIO_INT_CTRL_DATA irqData;
++
++ ZERO_OBJECT(irqData);
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: DeviceDetach\n"));
++ /* tell any function drivers we are gone */
++ RemoveHcdFunctions(pHcd);
++ /* delete the devices associated with this HCD */
++ DeleteDevices(pHcd);
++ /* check and see if there are any IRQs that were left enabled */
++ if (pHcd->IrqsEnabled) {
++ irqData.SlotIRQEnable = FALSE;
++ /* turn off IRQ detection in HCD */
++ _IssueConfig(pHcd,SDCONFIG_SDIO_INT_CTRL,(PVOID)&irqData, sizeof(irqData));
++ }
++
++ /* reset hcd state */
++ ResetHcdState(pHcd);
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: DeviceDetach\n"));
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * DeviceAttach - tell core a device was inserted into a slot
++*/
++SDIO_STATUS DeviceAttach(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDDEVICE pDevice = NULL;
++ UINT ii;
++
++
++ if (IS_CARD_PRESENT(pHcd)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: DeviceAttach called on occupied slot!\n"));
++ return SDIO_STATUS_ERROR;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: DeviceAttach bdctxt:0x%X \n", (UINT32)pBusContext));
++
++ if (IS_HCD_RAW(pHcd)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: RAW HCD (%s) device attach \n",pHcd->pName));
++ /* this is a raw HCD */
++ memset(&pHcd->CardProperties,0,sizeof(pHcd->CardProperties));
++ pHcd->CardProperties.Flags = CARD_RAW;
++ pHcd->CardProperties.IOFnCount = 0;
++ /* for raw HCD, set up minimum parameters
++ * since we cannot determine these values using any standard, use values
++ * reported by the HCD */
++ /* the operational rate is just the max clock rate reported */
++ pHcd->CardProperties.OperBusClock = pHcd->MaxClockRate;
++ /* the max bytes per data transfer is just the max bytes per block */
++ pHcd->CardProperties.OperBlockLenLimit = pHcd->MaxBytesPerBlock;
++ /* if the raw HCD uses blocks to transfer, report the operational size
++ * from the HCD max value */
++ pHcd->CardProperties.OperBlockCountLimit = pHcd->MaxBlocksPerTrans;
++ /* set the slot preferred voltage */
++ pHcd->CardProperties.CardVoltage = pHcd->SlotVoltagePreferred;
++ } else {
++ /* initialize this card and get card properties */
++ if (!SDIO_SUCCESS((status = SDInitializeCard(pHcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: DeviceAttach, failed to initialize card, %d\n",
++ status));
++ return status;
++ }
++ }
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++
++
++ /* check for SD or MMC, this must be done first as the query may involve
++ * de-selecting the card */
++ do {
++ if (!(pHcd->CardProperties.Flags & (CARD_MMC | CARD_SD | CARD_RAW))) {
++ /* none of these were discovered */
++ break;
++ }
++ pDevice = AllocateDevice(pHcd);
++ if (NULL == pDevice) {
++ break;
++ }
++ if (pHcd->CardProperties.Flags & CARD_RAW) {
++ /* set function number to 1 for IRQ processing */
++ SDDEVICE_SET_SDIO_FUNCNO(pDevice,1);
++ } else {
++ /* get the ID info for the SD/MMC Card */
++ if (!SDIO_SUCCESS((status = SDQuerySDMMCInfo(pDevice)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: DeviceAttach, query SDMMC Info failed \n"));
++ FreeDevice(pDevice);
++ break;
++ }
++ }
++ AddDeviceToList(pDevice);
++ /* look for a function driver to handle this card */
++ ProbeForFunction(pDevice, pHcd);
++ } while (FALSE);
++
++
++#endif
++
++
++ /* create a device for each I/O function */
++ for(ii= 1; ii <= pHcd->CardProperties.IOFnCount; ii++) {
++ pDevice = AllocateDevice(pHcd);
++ if (NULL == pDevice) {
++ break;
++ }
++ /* set the function number */
++ SDDEVICE_SET_SDIO_FUNCNO(pDevice,ii);
++ /* get the ID info for each I/O function */
++ if (!SDIO_SUCCESS((status = SDQuerySDIOInfo(pDevice)))) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: DeviceAttach, could not query SDIO Info, funcNo:%d status:%d \n",
++ ii, status));
++ FreeDevice(pDevice);
++ /* keep loading other functions */
++ continue;
++ }
++ AddDeviceToList(pDevice);
++ /* look for a function driver to handle this card */
++ ProbeForFunction(pDevice, pHcd);
++ }
++
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: DeviceAttach \n"));
++ return status;
++}
++
++static INLINE void CompleteRequestCheckCancel(PSDHCD pHcd, PSDREQUEST pReqToComplete)
++{
++ BOOL cancel = FALSE;
++ PSDFUNCTION pFunc = NULL;
++
++ /* handle cancel of current request */
++ if (pReqToComplete->Flags & SDREQ_FLAGS_CANCELED) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - _SDIO_HandleHcdEvent: cancelling req 0X%X\n", (UINT)pReqToComplete));
++ cancel = TRUE;
++ pReqToComplete->Status = SDIO_STATUS_CANCELED;
++ pFunc = pReqToComplete->pFunction;
++ DBG_ASSERT(pFunc != NULL);
++ }
++
++ DoRequestCompletion(pReqToComplete, pHcd);
++
++ if (cancel) {
++ SignalSet(&pFunc->CleanupReqSig);
++ }
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Indicate to the SDIO bus driver (core) of an event in the host controller
++ driver.
++
++ @function name: SDIO_HandleHcdEvent
++ @prototype: SDIO_STATUS SDIO_HandleHcdEvent(PSDHCD pHcd, HCD_EVENT Event)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller structure that was registered
++ HCD_EVENT - event code
++
++ @output: none
++
++ @return: SDIO_STATUS
++
++ @notes:
++ The host controller driver can indicate asynchronous events by calling this
++ function with an appropriate event code. Refer to the HDK help manual for
++ more information on the event types
++
++ @example: Example of indicating a card insertion event:
++ SDIO_HandleHcdEvent(&Hcd, EVENT_HCD_ATTACH);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_HandleHcdEvent(PSDHCD pHcd, HCD_EVENT Event)
++{
++ PSDREQUEST pReq;
++ PSDREQUEST pReqToComplete = NULL;
++ PSDREQUEST pNextReq = NULL;
++ SDIO_STATUS status;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ DBG_PRINT(SDIODBG_HCD_EVENTS, ("SDIO Bus Driver: _SDIO_HandleHcdEvent, event type 0x%X, HCD:0x%X\n",
++ Event, (UINT)pHcd));
++
++ if (Event == EVENT_HCD_TRANSFER_DONE) {
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ if (NULL == pReq) {
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ }
++
++ status = _AcquireHcdLock(pHcd);
++ if (SDIO_SUCCESS(status)) {
++ /* null out the current request */
++ SET_CURRENT_REQUEST(pHcd, NULL);
++ status = _ReleaseHcdLock(pHcd);
++ } else {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: SDIO_HandleHcdEvent Failed to acquire HCD lock \n"));
++ return SDIO_STATUS_ERROR;
++ }
++
++ /* note: the queue is still marked busy to prevent other threads/tasks from starting
++ * new requests while we are handling completion , some completed requests are
++ * marked as barrier requests which must be handled atomically */
++
++ status = pReq->Status;
++ DBG_PRINT(SDIODBG_REQUESTS,
++ ("+SDIO Bus Driver: Handling Transfer Done (CMD:%d, Status:%d) from HCD:0x%08X \n",
++ pReq->Command, status, (INT)pHcd));
++ /* check SPI mode conversion */
++ if (IS_HCD_BUS_MODE_SPI(pHcd) && SDIO_SUCCESS(status)) {
++ if (!(pReq->Flags & SDREQ_FLAGS_RESP_SKIP_SPI_FILT) && !(pReq->Flags & SDREQ_FLAGS_PSEUDO) &&
++ (GET_SDREQ_RESP_TYPE(pReq->Flags) != SDREQ_FLAGS_NO_RESP)) {
++ ConvertSPI_Response(pReq, NULL);
++ }
++ }
++
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Completing Request:0x%08X \n",(INT)pReq));
++
++ if (!SDIO_SUCCESS(status) &&
++ (status != SDIO_STATUS_CANCELED) &&
++ !(pReq->Flags & SDREQ_FLAGS_CANCELED) &&
++ (pReq->RetryCount > 0)) {
++ /* retry the request if it failed, was NOT cancelled and the retry count
++ * is greater than zero */
++ pReq->RetryCount--;
++ pReqToComplete = NULL;
++ /* clear SPI converted flag */
++ pReq->Flags &= ~SDREQ_FLAGS_RESP_SPI_CONVERTED;
++ pNextReq = pReq;
++ } else {
++ /* complete the request */
++ if (pReq->Flags & SDREQ_FLAGS_BARRIER) {
++ /* a barrier request must be completed before the next bus request is
++ * started */
++ CompleteRequestCheckCancel(pHcd, pReq);
++ if (!ForceAllRequestsAsync()) {
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ /* the request was completed, decrement recursion count */
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ pHcd->Recursion--;
++ DBG_ASSERT(pHcd->Recursion >= 0);
++ status = _ReleaseHcdLock(pHcd);
++ } else {
++ /* reset bit */
++ AtomicTest_Clear(&pHcd->HcdFlags, HCD_REQUEST_CALL_BIT);
++ }
++ }
++ pReqToComplete = NULL;
++ } else {
++ /* complete this after the next request has
++ * been started */
++ pReqToComplete = pReq;
++ }
++ }
++
++ /* acquire the hcd lock to look at the queues */
++ status = _AcquireHcdLock(pHcd);
++ if (SDIO_SUCCESS(status)) {
++ if (pReqToComplete != NULL) {
++ /* queue the request that was completed */
++ QueueRequest(&pHcd->CompletedRequestQueue, pReqToComplete);
++ }
++ if (NULL == pNextReq) {
++ /* check the queue for the next request */
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Checking queue.. \n"));
++ /* check to see if the HCD was already working on one. This occurs if
++ * the current request being completed was a barrier request and the
++ * barrier completion routine submitted a new request to the head of the
++ * queue */
++ if (GET_CURRENT_REQUEST(pHcd) == NULL) {
++ pNextReq = DequeueRequest(&pHcd->RequestQueue);
++ if (NULL == pNextReq) {
++ /* nothing in the queue, mark it not busy */
++ MarkQueueNotBusy(&pHcd->RequestQueue);
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Queue idle \n"));
++ } else {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Next request in queue: 0x%X \n",
++ (INT)pNextReq));
++ }
++ } else {
++ DBG_PRINT(SDIODBG_REQUESTS,
++ ("SDIO Bus Driver: Busy Queue from barrier request \n"));
++ }
++ }
++
++ if (pNextReq != NULL) {
++ /* a new request will be submitted to the HCD below,
++ * check recursion while we have the lock */
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ CHECK_HCD_RECURSE(pHcd,pNextReq);
++ }
++ }
++ status = _ReleaseHcdLock(pHcd);
++ } else {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: SDIO_HandleHcdEvent Failed to acquire HCD lock \n"));
++ return SDIO_STATUS_ERROR;
++ }
++ /* check for the next request to issue */
++ if (pNextReq != NULL) {
++ DBG_PRINT(SDIODBG_REQUESTS, ("SDIO Bus Driver: Starting Next Request: 0x%X \n",
++ (INT)pNextReq));
++ SET_CURRENT_REQUEST(pHcd,pNextReq);
++ status = CallHcdRequest(pHcd);
++ /* check and see if the HCD completed the request in the callback */
++ if (status != SDIO_STATUS_PENDING) {
++ /* recurse and process the request */
++ _SDIO_HandleHcdEvent(pHcd, EVENT_HCD_TRANSFER_DONE);
++ }
++ }
++
++ /* now empty the completed request queue
++ * - this guarantees in-order completion even during recursion */
++ status = _AcquireHcdLock(pHcd);
++ if (SDIO_SUCCESS(status)) {
++ while (1) {
++ pReqToComplete = DequeueRequest(&pHcd->CompletedRequestQueue);
++ status = _ReleaseHcdLock(pHcd);
++ if (pReqToComplete != NULL) {
++ CompleteRequestCheckCancel(pHcd, pReqToComplete);
++ if (!CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ if (!ForceAllRequestsAsync()) {
++ /* reset bit */
++ AtomicTest_Clear(&pHcd->HcdFlags, HCD_REQUEST_CALL_BIT);
++ }
++ }
++ /* re-acquire lock */
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return SDIO_STATUS_ERROR;
++ }
++ if (CHECK_API_VERSION_COMPAT(pHcd,2,6)) {
++ if (!ForceAllRequestsAsync()) {
++ /* while we have the lock, decrement recursion count each time
++ * we complete a request */
++ pHcd->Recursion--;
++ DBG_ASSERT(pHcd->Recursion >= 0);
++ }
++ }
++ } else {
++ /* we're done */
++ break;
++ }
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: SDIO_HandleHcdEvent Failed to acquire HCD lock \n"));
++ return SDIO_STATUS_ERROR;
++ }
++ DBG_PRINT(SDIODBG_REQUESTS, ("-SDIO Bus Driver: Transfer Done Handled \n"));
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ switch(Event) {
++ case EVENT_HCD_ATTACH:
++ case EVENT_HCD_DETACH:
++ /* card detect helper does the actual attach detach */
++ return PostCardDetectEvent(pBusContext,Event,pHcd);
++ case EVENT_HCD_SDIO_IRQ_PENDING:
++ return DeviceInterrupt(pHcd);
++ default:
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: SDIO_HandleHcdEvent, invalid event type 0x%X, HCD:0x%X\n",
++ Event, (UINT)pHcd));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++}
++
++/* card detect helper function */
++THREAD_RETURN CardDetectHelperFunction(POSKERNEL_HELPER pHelper)
++{
++ SDIO_STATUS status;
++ HCD_EVENT_MESSAGE message;
++ INT length;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - CardDetectHelperFunction starting up: 0x%X \n", (INT)pHelper));
++
++ while (1) {
++
++ /* wait for wake up event */
++ status = SD_WAIT_FOR_WAKEUP(pHelper);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver - Card Detect Helper Semaphore Pend Error:%d \n",
++ status));
++ break;
++ }
++
++ if (SD_IS_HELPER_SHUTTING_DOWN(pHelper)) {
++ /* cleanup message queue on shutdown */
++ while (1) {
++ length = sizeof(message);
++ /* get a message */
++ status = SDLIB_GetMessage(pBusContext->pCardDetectMsgQueue,
++ &message, &length);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ if (message.pHcd != NULL) {
++ /* decrement HCD reference count */
++ OS_DecHcdReference(message.pHcd);
++ }
++ }
++
++ break;
++ }
++
++ while (1) {
++ length = sizeof(message);
++ /* get a message */
++ status = SDLIB_GetMessage(pBusContext->pCardDetectMsgQueue,
++ &message, &length);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ switch (message.Event) {
++ case EVENT_HCD_ATTACH:
++ DeviceAttach(message.pHcd);
++ break;
++ case EVENT_HCD_DETACH:
++ DeviceDetach(message.pHcd);
++ break;
++
++#ifndef CT_CONFIG_NO_CARD_POLLING
++ case EVENT_HCD_CD_POLLING:
++ /* run detector */
++ RunCardDetect();
++ break;
++
++#endif
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ if (message.pHcd != NULL) {
++ /* message was processed, decrement reference count */
++ OS_DecHcdReference(message.pHcd);
++ }
++ }
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - Card Detect Helper Exiting.. \n"));
++ return 0;
++}
++
++#ifndef CT_CONFIG_NO_CARD_POLLING
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ RunCardDetect - run card detect on host controller slots that require polling
++ Input:
++ Output:
++ Return:
++ Notes: This function is called from the card detect timer thread
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void RunCardDetect(void)
++{
++ BOOL CDPollingRequired = FALSE;
++ PSDLIST pListItem;
++ PSDHCD pHcd;
++ BOOL cardPresent;
++
++ DBG_PRINT(SDIODBG_CD_TIMER, ("+SDIO Bus Driver: RunCardDetect\n"));
++
++ /* protect the HCD list */
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pBusContext->HcdListSem))) {
++ DBG_ASSERT(FALSE);
++ return; /* wait interrupted */
++ }
++ /* while we are running the detector we are blocking HCD removal*/
++ SDITERATE_OVER_LIST(&pBusContext->HcdList, pListItem) {
++ pHcd = CONTAINING_STRUCT(pListItem, SDHCD, SDList);
++ /* does the HCD require polling ? */
++ if (pHcd->Attributes & SDHCD_ATTRIB_SLOT_POLLING) {
++ DBG_PRINT(SDIODBG_CD_TIMER, ("SDIO Bus Driver: Found HCD requiring polling \n"));
++ /* set flag to queue the timer */
++ CDPollingRequired = TRUE;
++ if (IS_CARD_PRESENT(pHcd)) {
++ /* there is a device in the slot */
++ cardPresent = TRUE;
++ if (SDIO_SUCCESS(ScanSlotForCard(pHcd,&cardPresent))) {
++ if (!cardPresent) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver CD Polling.. Card Removal Detected\n"));
++ DeviceDetach(pHcd);
++ }
++ }
++ } else {
++ cardPresent = FALSE;
++ if (SDIO_SUCCESS(ScanSlotForCard(pHcd,&cardPresent))) {
++ if (cardPresent) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver CD Polling.. Card Detected\n"));
++ DeviceAttach(pHcd);
++ }
++ }
++ }
++ }
++
++ DBG_PRINT(SDIODBG_CD_TIMER, ("SDIO Bus Driver: moving to next hcd:0x%X \n",
++ (INT)pListItem->pNext));
++ }
++
++ /* check if we need to queue the timer */
++ if (CDPollingRequired && !pBusContext->CDTimerQueued) {
++ pBusContext->CDTimerQueued = TRUE;
++ DBG_PRINT(SDIODBG_CD_TIMER, ("SDIO Bus Driver: Queuing Card detect timer \n"));
++ if (!SDIO_SUCCESS(
++ QueueTimer(SDIOBUS_CD_TIMER_ID, pBusContext->CDPollingInterval))) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: failed to queue CD timer \n"));
++ pBusContext->CDTimerQueued = FALSE;
++ }
++ }
++ /* release HCD list lock */
++ SemaphorePost(&pBusContext->HcdListSem);
++ DBG_PRINT(SDIODBG_CD_TIMER, ("-SDIO Bus Driver: RunCardDetect\n"));
++}
++
++#endif
++
++
++#ifndef CT_CONFIG_NO_CARD_POLLING
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ScanSlotForCard - scan slot for a card
++ Input: pHcd - the hcd
++ Output: pCardPresent - card present flag (set/cleared on return)
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS ScanSlotForCard(PSDHCD pHcd,PBOOL pCardPresent)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 temp;
++
++ DBG_PRINT(SDIODBG_CD_TIMER, ("+SDIO Bus Driver: ScanSlotForCard\n"));
++
++ do {
++ if (!IS_CARD_PRESENT(pHcd)) {
++#ifdef DEBUG
++ INT dbgLvl;
++ dbgLvl = DBG_GET_DEBUG_LEVEL();
++ DBG_SET_DEBUG_LEVEL(SDDBG_WARN);
++#endif
++ status = CardInitSetup(pHcd);
++
++#ifdef DEBUG
++ DBG_SET_DEBUG_LEVEL(dbgLvl);
++#endif
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* issue go-idle */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,NULL);
++ } else {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,NULL);
++ }
++ /* try SDIO */
++ status = TestPresence(pHcd,CARD_SDIO,NULL);
++ if (SDIO_SUCCESS(status)) {
++ *pCardPresent = TRUE;
++ break;
++ }
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* issue go-idle */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,NULL);
++ } else {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,NULL);
++ }
++ /* try SD */
++ status = TestPresence(pHcd,CARD_SD,NULL);
++ if (SDIO_SUCCESS(status)) {
++ *pCardPresent = TRUE;
++ break;
++ }
++ /* issue go-idle */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,NULL);
++ } else {
++ _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,NULL);
++ }
++ /* try MMC */
++ status = TestPresence(pHcd,CARD_MMC,NULL);
++ if (SDIO_SUCCESS(status)) {
++ *pCardPresent = TRUE;
++ break;
++ }
++
++#endif
++ } else {
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++#ifdef DUMP_INT_PENDING
++ temp = 0;
++ /* handy debug prints to check interrupt status and print pending register */
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev, SDIO_INT_ENABLE_REG, &temp);
++ if (SDIO_SUCCESS(status) && (temp != 0)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: INT Enable Reg: 0x%2.2X\n", temp));
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev, SDIO_INT_PENDING_REG, &temp);
++ if (SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: INT Pend Reg: 0x%2.2X\n", temp));
++ }
++ }
++#endif
++ /* for SDIO cards, read the revision register */
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev, CCCR_SDIO_REVISION_REG, &temp);
++ } else if (pHcd->CardProperties.Flags & (CARD_SD | CARD_MMC)) {
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* for SD/MMC cards, issue SEND_STATUS */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* SPI uses the SPI R2 response */
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD13,
++ 0,
++ SDREQ_FLAGS_RESP_R2,
++ NULL);
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD13,
++ (pHcd->CardProperties.RCA << 16),
++ SDREQ_FLAGS_RESP_R1,NULL);
++ }
++
++#endif
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++ if (!SDIO_SUCCESS(status)) {
++ /* card is gone */
++ *pCardPresent = FALSE;
++ }
++ }
++ } while (FALSE);
++
++ if (status == SDIO_STATUS_BUS_RESP_TIMEOUT) {
++ status = SDIO_STATUS_SUCCESS;
++ }
++
++ DBG_PRINT(SDIODBG_CD_TIMER, ("-SDIO Bus Driver: ScanSlotForCard status:%d\n",
++ status));
++
++ return status;
++}
++
++#endif
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ DeviceInterrupt - handle device interrupt
++ Input: pHcd - host controller
++ Output:
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS DeviceInterrupt(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ SDIO_STATUS status2;
++ PSDREQUEST pReq = NULL;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("+SDIO Bus Driver: DeviceInterrupt\n"));
++
++ if (!IS_CARD_PRESENT(pHcd)) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: Device interrupt asserted on empty slot!\n"));
++ return SDIO_STATUS_ERROR;
++ }
++
++ do {
++ /* for RAW HCDs or HCDs flagged for single-function IRQ optimization */
++ if (IS_HCD_RAW(pHcd) || (pHcd->HcdFlags & (1 << HCD_IRQ_NO_PEND_CHECK))) {
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ if (pHcd->IrqProcState != SDHCD_IDLE) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: Already processing interrupts! (state = %d) \n",
++ pHcd->IrqProcState));
++ status = SDIO_STATUS_ERROR;
++ status2 = _ReleaseHcdLock(pHcd);
++ } else {
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver : Device Interrupt \n"));
++ /* mark that we are processing */
++ pHcd->IrqProcState = SDHCD_IRQ_PENDING;
++ status2 = _ReleaseHcdLock(pHcd);
++ /* process Irqs for raw hcds or HCDs with the single function optimization */
++ /* force processing of function 1 interrupt */
++ ProcessPendingIrqs(pHcd, (1 << 1));
++ }
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("-SDIO Bus Driver: DeviceInterrupt: %d\n", status));
++ /* done with RAW irqs */
++ return status;
++ }
++
++ /* pre-allocate a request to get the pending bits, we have to do this outside the
++ * hcd lock acquisition */
++ pReq = AllocateRequest();
++
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ status = _AcquireHcdLock(pHcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (pHcd->IrqProcState != SDHCD_IDLE) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: Already processing interrupts! (state = %d) \n",
++ pHcd->IrqProcState));
++ status = SDIO_STATUS_ERROR;
++ } else {
++ /* mark that we are processing */
++ pHcd->IrqProcState = SDHCD_IRQ_PENDING;
++ /* build argument to read IRQ pending register */
++ SDIO_SET_CMD52_READ_ARG(pReq->Argument,0,SDIO_INT_PENDING_REG);
++ pReq->Command = CMD52;
++ pReq->Flags = SDREQ_FLAGS_TRANS_ASYNC | SDREQ_FLAGS_RESP_SDIO_R5;
++ pReq->pCompleteContext = (PVOID)pHcd;
++ pReq->pCompletion = GetPendingIrqComplete;
++ pReq->RetryCount = SDBUS_MAX_RETRY;
++ }
++
++ status2 = _ReleaseHcdLock(pHcd);
++
++ if (!SDIO_SUCCESS(status2)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: lock release error: %d\n", status2));
++ }
++
++ } while (FALSE);
++
++ if (SDIO_SUCCESS(status)) {
++ DBG_ASSERT(pReq != NULL);
++ IssueRequestToHCD(pHcd,pReq);
++ status = SDIO_STATUS_PENDING;
++ } else {
++ if (pReq != NULL) {
++ FreeRequest(pReq);
++ }
++ }
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("-SDIO Bus Driver: DeviceInterrupt: %d\n", status));
++ return status;
++}
++
++
++/* SDIO IRQ helper */
++THREAD_RETURN SDIOIrqHelperFunction(POSKERNEL_HELPER pHelper)
++{
++ PSDHCD pHcd;
++ SDIO_STATUS status;
++ PSDLIST pListItem;
++ PSDDEVICE pDevice;
++ UINT8 funcMask;
++ PSDDEVICE pDeviceIRQ[7];
++ UINT deviceIrqCount = 0;
++ UINT ii;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - SDIOIrqHelperFunction starting up \n"));
++
++ pHcd = (PSDHCD)pHelper->pContext;
++ DBG_ASSERT(pHcd != NULL);
++
++ while (1) {
++
++ /* wait for wake up event */
++ status = SD_WAIT_FOR_WAKEUP(pHelper);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver - SDIOIrqHelperFunction Pend Error:%d \n",
++ status));
++ break;
++ }
++
++ if (SD_IS_HELPER_SHUTTING_DOWN(pHelper)) {
++ break;
++ }
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver - Pending IRQs:0x%X \n",
++ pHcd->PendingHelperIrqs));
++
++ /* take the device list lock as we iterate through the list, this blocks
++ * device removals */
++ status = SemaphorePendInterruptable(&pBusContext->DeviceListSem);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* walk through the device list matching HCD and interrupting function */
++ SDITERATE_OVER_LIST(&pBusContext->DeviceList, pListItem) {
++ pDevice = CONTAINING_STRUCT(pListItem, SDDEVICE, SDList);
++ /* check if device belongs to the HCD */
++ if (pDevice->pHcd != pHcd){
++ /* not on this hcd */
++ continue;
++ }
++ funcMask = 1 << SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ /* check device function against the pending mask */
++ if (!(funcMask & pHcd->PendingHelperIrqs)) {
++ /* this one is not scheduled for the helper */
++ continue;
++ }
++ /* clear bit */
++ pHcd->PendingHelperIrqs &= ~funcMask;
++ /* check for sync IRQ and call handler */
++ if (pDevice->pIrqFunction != NULL) {
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: Calling IRQ Handler. Fn:%d\n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice)));
++ /* save the device so we can process it without holding any locks */
++ pDeviceIRQ[deviceIrqCount++] = pDevice;
++ } else {
++ /* this is actually okay if the device is removing, the callback
++ * is NULLed out */
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: No IRQ handler Fn:%d\n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice)));
++ }
++ }
++ /* should have handled all these */
++ DBG_ASSERT(pHcd->PendingHelperIrqs == 0);
++ pHcd->PendingHelperIrqs = 0;
++ SemaphorePost(&pBusContext->DeviceListSem);
++ for (ii = 0; ii < deviceIrqCount; ii++) {
++ /* now call the function */
++ SDDEVICE_CALL_IRQ_HANDLER(pDeviceIRQ[ii]);
++ }
++ deviceIrqCount = 0;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - SDIOIrqHelperFunction Exiting.. \n"));
++ return 0;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetPendingIrqComplete - completion routine for getting pending IRQs
++ Input: pRequest - completed request
++ Output:
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static void GetPendingIrqComplete(PSDREQUEST pReq)
++{
++ UINT8 intPendingMsk;
++ PSDHCD pHcd;
++
++ do {
++ pHcd = (PSDHCD)pReq->pCompleteContext;
++ DBG_ASSERT(pHcd != NULL);
++
++ if (!SDIO_SUCCESS(pReq->Status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get Interrupt pending register Err:%d\n",
++ pReq->Status));
++ break;
++ }
++
++ if (SD_R5_GET_RESP_FLAGS(pReq->Response) & SD_R5_ERRORS) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: CMD52 resp error: 0x%X \n",
++ SD_R5_GET_RESP_FLAGS(pReq->Response)));
++ break;
++ }
++ /* extract the pending mask */
++ intPendingMsk = SD_R5_GET_READ_DATA(pReq->Response) & SDIO_INT_PEND_MASK;
++ /* process them */
++ ProcessPendingIrqs(pHcd, intPendingMsk);
++
++ } while (FALSE);
++
++ FreeRequest(pReq);
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("-SDIO Bus Driver: GetPendingIrqComplete \n"));
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ProcessPendingIrqs - processing pending Irqs
++ Input: pHcd - host controller
++ Input: IntPendingMsk - pending irq bit mask
++ Output:
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static void ProcessPendingIrqs(PSDHCD pHcd, UINT8 IntPendingMsk)
++{
++ PSDLIST pListItem;
++ PSDDEVICE pDevice;
++ UINT8 funcMask;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("+SDIO Bus Driver: ProcessPendingIrqs \n"));
++ do {
++ /* acquire lock to protect configuration and irq enables */
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ /* sanity check */
++ if ((IntPendingMsk & pHcd->IrqsEnabled) != IntPendingMsk) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: IRQs asserting when not enabled : curr:0x%X , card reports: 0x%X\n",
++ pHcd->IrqsEnabled, IntPendingMsk));
++ /* remove the pending IRQs that are not enabled */
++ IntPendingMsk &= pHcd->IrqsEnabled;
++ /* fall through */
++ }
++
++ if (!IntPendingMsk) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: No interrupts on HCD:0x%X \n", (INT)pHcd));
++ pHcd->IrqProcState = SDHCD_IDLE;
++ if (pHcd->IrqsEnabled) {
++ /* only re-arm if there are IRQs enabled */
++ _IssueConfig(pHcd,SDCONFIG_SDIO_REARM_INT,NULL,0);
++ }
++ status = _ReleaseHcdLock(pHcd);
++ break;
++ }
++ /* reset helper IRQ bits */
++ pHcd->PendingHelperIrqs = 0;
++ /* save pending IRQ acks */
++ pHcd->PendingIrqAcks = IntPendingMsk;
++ status = _ReleaseHcdLock(pHcd);
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: INTs Pending - 0x%2.2X \n", IntPendingMsk));
++ /* take the device list lock as we iterate through the list, this blocks
++ * device removals */
++ status = SemaphorePendInterruptable(&pBusContext->DeviceListSem);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* walk through the device list matching HCD and interrupting function */
++ SDITERATE_OVER_LIST(&pBusContext->DeviceList, pListItem) {
++ pDevice = CONTAINING_STRUCT(pListItem, SDDEVICE, SDList);
++ /* check if device belongs to the HCD */
++ if (pDevice->pHcd != pHcd){
++ /* not on this hcd */
++ continue;
++ }
++ funcMask = 1 << SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ /* check device function against the pending mask */
++ if (!(funcMask & IntPendingMsk)) {
++ /* this one is not interrupting */
++ continue;
++ }
++ /* check for async IRQ and call handler */
++ if (pDevice->pIrqAsyncFunction != NULL) {
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: Calling Async IRQ Handler. Fn:%d\n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice)));
++ SDDEVICE_CALL_IRQ_ASYNC_HANDLER(pDevice);
++ } else {
++ /* this one needs the helper */
++ pHcd->PendingHelperIrqs |= funcMask;
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: No Async IRQ, Pending Helper Fn:%d\n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice)));
++ }
++ }
++ /* release HCD list lock */
++ SemaphorePost(&pBusContext->DeviceListSem);
++ /* check for helper IRQs */
++ if (pHcd->PendingHelperIrqs) {
++ pHcd->IrqProcState = SDHCD_IRQ_HELPER;
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: Waking IRQ Helper \n"));
++ if (!SDIO_SUCCESS(SD_WAKE_OS_HELPER(&pHcd->SDIOIrqHelper))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: failed to wake helper! \n"));
++ }
++ }
++ } while (FALSE);
++
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("-SDIO Bus Driver: ProcessPendingIrqs \n"));
++}
++
++SDIO_STATUS TryNoIrqPendingCheck(PSDDEVICE pDevice)
++{
++ if (pDevice->pHcd->CardProperties.IOFnCount > 1) {
++ /* not supported on multi-function cards */
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: IRQ Pending Check cannot be bypassed, (Funcs:%d)\n",
++ pDevice->pHcd->CardProperties.IOFnCount));
++ return SDIO_STATUS_UNSUPPORTED;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: pending IRQ check bypassed \n"));
++ /* set flag to optimize this */
++ AtomicTest_Set(&pDevice->pHcd->HcdFlags, HCD_IRQ_NO_PEND_CHECK);
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDIO_NotifyTimerTriggered - notification handler that a timer expired
++ Input: TimerID - ID of timer that expired
++ Output:
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SDIO_NotifyTimerTriggered(INT TimerID)
++{
++
++ switch (TimerID) {
++ case SDIOBUS_CD_TIMER_ID:
++ pBusContext->CDTimerQueued = FALSE;
++ /* post an HCD polling event to the helper thread */
++ PostCardDetectEvent(pBusContext, EVENT_HCD_CD_POLLING, NULL);
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ }
++
++}
+Index: linux-2.6.22/drivers/sdio/busdriver/sdio_bus_misc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/sdio_bus_misc.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,3184 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bus_misc.c
++
++ at abstract: OS independent bus driver support
++
++#notes: this file contains miscellaneous control functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++$ATH_LICENSE_SDIOSTACK0$
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDBUSDRIVER
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "_busdriver.h"
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/mmc_defs.h>
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ IssueBusRequestBd - issue a bus request
++ Input: pHcd - HCD object
++ Cmd - command to issue
++ Argument - command argument
++ Flags - request flags
++
++ Output: pReqToUse - request to use (if caller wants response data)
++ Return: SDIO Status
++ Notes: This function only issues 1 block data transfers
++ This function issues the request synchronously
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _IssueBusRequestBd(PSDHCD pHcd,
++ UINT8 Cmd,
++ UINT32 Argument,
++ SDREQUEST_FLAGS Flags,
++ PSDREQUEST pReqToUse,
++ PVOID pData,
++ INT Length)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq;
++
++ if (NULL == pReqToUse) {
++ /* caller doesn't care about the response data, allocate locally */
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ } else {
++ /* use the caller's request buffer */
++ pReq = pReqToUse;
++ }
++
++ pReq->Argument = Argument;
++ pReq->Flags = Flags;
++ pReq->Command = Cmd;
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ pReq->pDataBuffer = pData;
++ pReq->BlockCount = 1;
++ pReq->BlockLen = Length;
++ }
++
++ status = IssueRequestToHCD(pHcd,pReq);
++
++ if (NULL == pReqToUse) {
++ DBG_ASSERT(pReq != NULL);
++ FreeRequest(pReq);
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ConvertVoltageCapsToOCRMask - initialize card
++ Input: VoltageCaps - voltage cap to look up
++ Return: 32 bit OCR mask
++ Notes: this function sets voltage for +- 10%
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static UINT32 ConvertVoltageCapsToOCRMask(SLOT_VOLTAGE_MASK VoltageCaps)
++{
++ UINT32 ocrMask;
++
++ ocrMask = 0;
++
++ if (VoltageCaps & SLOT_POWER_3_3V) {
++ ocrMask |= SD_OCR_3_2_TO_3_3_VDD | SD_OCR_3_3_TO_3_4_VDD;
++ }
++ if (VoltageCaps & SLOT_POWER_3_0V) {
++ ocrMask |= SD_OCR_2_9_TO_3_0_VDD | SD_OCR_3_0_TO_3_1_VDD;
++ }
++ if (VoltageCaps & SLOT_POWER_2_8V) {
++ ocrMask |= SD_OCR_2_7_TO_2_8_VDD | SD_OCR_2_8_TO_2_9_VDD;
++ }
++ if (VoltageCaps & SLOT_POWER_2_0V) {
++ ocrMask |= SD_OCR_1_9_TO_2_0_VDD | SD_OCR_2_0_TO_2_1_VDD;
++ }
++ if (VoltageCaps & SLOT_POWER_1_8V) {
++ ocrMask |= SD_OCR_1_7_TO_1_8_VDD | SD_OCR_1_8_TO_1_9_VDD;
++ }
++ if (VoltageCaps & SLOT_POWER_1_6V) {
++ ocrMask |= SD_OCR_1_6_TO_1_7_VDD;
++ }
++
++ return ocrMask;
++}
++
++static UINT32 GetUsableOCRValue(UINT32 CardOCR, UINT32 SlotOCRMask)
++{
++ INT i;
++ UINT32 mask = 0;
++
++ for (i = 0; i < 32; i++) {
++ mask = 1 << i;
++ if ((SlotOCRMask & mask) && (CardOCR & mask)) {
++ return mask;
++ }
++ }
++
++ return mask;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetPowerSetting - power up the SDIO card
++ Input: pHcd - HCD object
++ pOCRvalue - OCR value of the card
++ Output: pOCRvalue - OCR to actually use
++ Return: power setting for HCD based on card's OCR, zero indicates unsupported
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SLOT_VOLTAGE_MASK GetPowerSetting(PSDHCD pHcd, UINT32 *pOCRvalue)
++{
++ UINT32 ocrMask;
++ SLOT_VOLTAGE_MASK hcdVoltage = 0;
++ SLOT_VOLTAGE_MASK hcdVMask;
++ INT i;
++
++ /* check preferred value */
++ ocrMask = ConvertVoltageCapsToOCRMask(pHcd->SlotVoltagePreferred);
++ if (ocrMask & *pOCRvalue) {
++ /* using preferred voltage */
++ *pOCRvalue = GetUsableOCRValue(*pOCRvalue, ocrMask);
++ hcdVoltage = pHcd->SlotVoltagePreferred;
++ } else {
++ /* walk through the slot voltage caps and find a match */
++ for (i = 0; i < 8; i++) {
++ hcdVMask = (1 << i);
++ if (hcdVMask & pHcd->SlotVoltageCaps) {
++ ocrMask = ConvertVoltageCapsToOCRMask((SLOT_VOLTAGE_MASK)(pHcd->SlotVoltageCaps & hcdVMask));
++ if (ocrMask & *pOCRvalue) {
++ /* found a match */
++ *pOCRvalue = GetUsableOCRValue(*pOCRvalue, ocrMask);
++ hcdVoltage = pHcd->SlotVoltageCaps & hcdVMask;
++ break;
++ }
++ }
++ }
++ }
++
++ return hcdVoltage;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TestPresence - test the presence of a card/function
++ Input: pHcd - HCD object
++ TestType - type of test to perform
++ Output: pReq - Request to use (optional)
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TestPresence(PSDHCD pHcd,
++ CARD_INFO_FLAGS TestType,
++ PSDREQUEST pReq)
++{
++ SDIO_STATUS status = SDIO_STATUS_ERROR;
++
++ switch (TestType) {
++ case CARD_SDIO:
++ /* issue CMD5 */
++ status = _IssueSimpleBusRequest(pHcd,CMD5,0,
++ SDREQ_FLAGS_RESP_SDIO_R4 | SDREQ_FLAGS_RESP_SKIP_SPI_FILT,pReq);
++ break;
++
++#ifndef CT_CONFIG_NO_SDMMC
++ case CARD_SD:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* ACMD41 just starts initialization when in SPI mode, argument is ignored
++ * Note: In SPI mode ACMD41 uses an R1 response */
++ status = _IssueSimpleBusRequest(pHcd,ACMD41,0,
++ SDREQ_FLAGS_APP_CMD | SDREQ_FLAGS_RESP_R1,pReq);
++
++ } else {
++ /* issue ACMD41 with OCR value of zero */
++ /* ACMD41 on SD uses an R3 response */
++ status = _IssueSimpleBusRequest(pHcd,ACMD41,0,
++ SDREQ_FLAGS_APP_CMD | SDREQ_FLAGS_RESP_R3,pReq);
++ }
++ break;
++ case CARD_MMC:
++ /* issue CMD1 */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* note: in SPI mode an R1 response is used */
++ status = _IssueSimpleBusRequest(pHcd,CMD1,0,SDREQ_FLAGS_RESP_R1,pReq);
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,CMD1,0,SDREQ_FLAGS_RESP_R3,pReq);
++ }
++ break;
++
++#endif
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ return status;
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ReadOCR - read the OCR
++ Input: pHcd - HCD object
++ ReadType - type of read to perform
++ OCRValue - OCR value to use as an argument
++ Output: pReq - Request to use
++ pOCRValueRd - OCR value read back (can be NULL)
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS ReadOCR(PSDHCD pHcd,
++ CARD_INFO_FLAGS ReadType,
++ PSDREQUEST pReq,
++ UINT32 OCRValue,
++ UINT32 *pOCRValueRd)
++{
++ SDIO_STATUS status = SDIO_STATUS_ERROR;
++
++ switch (ReadType) {
++ case CARD_SDIO:
++ /* CMD5 for SDIO cards */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* skip the SPI filter, we will decode the response here */
++ status = _IssueSimpleBusRequest(pHcd,CMD5,
++ OCRValue,
++ SDREQ_FLAGS_RESP_SDIO_R4 |
++ SDREQ_FLAGS_RESP_SKIP_SPI_FILT,
++ pReq);
++ } else {
++ /* native SD */
++ status = _IssueSimpleBusRequest(pHcd,CMD5,
++ OCRValue,
++ SDREQ_FLAGS_RESP_SDIO_R4,
++ pReq);
++ }
++ break;
++
++#ifndef CT_CONFIG_NO_SDMMC
++ case CARD_SD:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* CMD58 is used to read the OCR */
++ status = _IssueSimpleBusRequest(pHcd,CMD58,
++ 0, /* argument ignored */
++ (SDREQ_FLAGS_RESP_R3 | SDREQ_FLAGS_RESP_SKIP_SPI_FILT),
++ pReq);
++ } else {
++ /* SD Native uses ACMD41 */
++ status = _IssueSimpleBusRequest(pHcd,ACMD41,
++ OCRValue,
++ SDREQ_FLAGS_APP_CMD | SDREQ_FLAGS_RESP_R3,
++ pReq);
++ }
++ break;
++ case CARD_MMC:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* CMD58 is used to read the OCR */
++ status = _IssueSimpleBusRequest(pHcd,CMD58,
++ 0, /* argument ignored */
++ (SDREQ_FLAGS_RESP_R3 | SDREQ_FLAGS_RESP_SKIP_SPI_FILT),
++ pReq);
++ } else {
++ /* MMC Native uses CMD1 */
++ status = _IssueSimpleBusRequest(pHcd,CMD1,
++ OCRValue, SDREQ_FLAGS_RESP_R3,
++ pReq);
++ }
++ break;
++
++#endif
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ if (SDIO_SUCCESS(status) && (pOCRValueRd != NULL)) {
++ *pOCRValueRd = 0;
++ /* someone wants the OCR read back */
++ switch (ReadType) {
++ case CARD_SDIO:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ *pOCRValueRd = SPI_SDIO_R4_GET_OCR(pReq->Response);
++ } else {
++ *pOCRValueRd = SD_SDIO_R4_GET_OCR(pReq->Response);
++ }
++ break;
++
++#ifndef CT_CONFIG_NO_SDMMC
++ case CARD_SD:
++ case CARD_MMC:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ *pOCRValueRd = SPI_R3_GET_OCR(pReq->Response);
++ } else {
++ *pOCRValueRd = SD_R3_GET_OCR(pReq->Response);
++ }
++ break;
++
++#endif
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ PollCardReady - poll card till it's ready
++ Input: pHcd - HCD object
++ OCRValue - OCR value to poll with
++ PollType - polling type (based on card type)
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS PollCardReady(PSDHCD pHcd, UINT32 OCRValue, CARD_INFO_FLAGS PollType)
++{
++ INT cardReadyRetry;
++ SDIO_STATUS status;
++ PSDREQUEST pReq;
++
++ if (!((PollType == CARD_SDIO) || (PollType == CARD_SD) || (PollType == CARD_MMC))) {
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ status = SDIO_STATUS_SUCCESS;
++ cardReadyRetry = pBusContext->CardReadyPollingRetry;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Polling card ready, Using OCR:0x%8.8X, Poll Type:0x%X\n",
++ OCRValue,PollType));
++
++ /* now issue CMD with the actual OCR as an argument until the card is ready */
++ while (cardReadyRetry) {
++ if (IS_HCD_BUS_MODE_SPI(pHcd) && !(PollType == CARD_SDIO)) {
++
++#ifndef CT_CONFIG_NO_SDMMC
++ if (PollType == CARD_MMC) {
++ /* under SPI mode for MMC cards, we need to issue CMD1 and
++ * check the response for the "in-idle" bit */
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD1,
++ 0,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_RESP_SKIP_SPI_FILT,
++ pReq);
++ } else if (PollType == CARD_SD) {
++ /* under SPI mode for SD cards, we need to issue ACMD41 and
++ * check the response for the "in-idle" bit */
++ status = _IssueSimpleBusRequest(pHcd,
++ ACMD41,
++ 0,
++ SDREQ_FLAGS_RESP_R1 |
++ SDREQ_FLAGS_APP_CMD |
++ SDREQ_FLAGS_RESP_SKIP_SPI_FILT,
++ pReq);
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++
++#endif
++ } else {
++ /* for SD/MMC in native mode and SDIO (all modes) we need to read the OCR register */
++ /* read the OCR using the supplied OCR value as an argument, we don't care about the
++ * actual OCR read-back, but we are interested in the response */
++ status = ReadOCR(pHcd,PollType,pReq,OCRValue,NULL);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to issue CMD to poll ready \n"));
++ break;
++ }
++ if (PollType == CARD_SDIO) {
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ if (SPI_SDIO_R4_IS_CARD_READY(pReq->Response)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SDIO Card Ready! (SPI) \n"));
++ break;
++ }
++ } else {
++ if (SD_SDIO_R4_IS_CARD_READY(pReq->Response)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SDIO Card Ready! \n"));
++ break;
++ }
++ }
++ } else if ((PollType == CARD_SD) || (PollType == CARD_MMC)) {
++
++#ifndef CT_CONFIG_NO_SDMMC
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* check response when MMC or SD cards operate in SPI mode */
++ if (!(GET_SPI_R1_RESP_TOKEN(pReq->Response) & SPI_CS_STATE_IDLE)) {
++ /* card is no longer in idle */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD/MMC Card (SPI mode) is ready! \n"));
++ break;
++ }
++ } else {
++ /* check the OCR busy bit */
++ if (SD_R3_IS_CARD_READY(pReq->Response)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD/MMC (Native Mode) Card Ready! \n"));
++ break;
++ }
++ }
++
++#endif
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++ cardReadyRetry--;
++ /* delay */
++ status = OSSleep(OCR_READY_CHECK_DELAY_MS);
++ if (!SDIO_SUCCESS(status)){
++ break;
++ }
++ }
++
++ if (0 == cardReadyRetry) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Card Ready timeout! \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ }
++
++ FreeRequest(pReq);
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ AdjustSlotPower - adjust slot power
++ Input: pHcd - HCD object
++ Output: pOCRvalue - ocr value to use
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS AdjustSlotPower(PSDHCD pHcd, UINT32 *pOCRvalue)
++{
++ SDCONFIG_POWER_CTRL_DATA pwrSetting;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ ZERO_OBJECT(pwrSetting);
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver: Adjusting Slot Power, Requesting adjustment for OCR:0x%8.8X \n",
++ *pOCRvalue));
++
++ do {
++ pwrSetting.SlotPowerEnable = TRUE;
++ /* get optimal power setting */
++ pwrSetting.SlotPowerVoltageMask = GetPowerSetting(pHcd, pOCRvalue);
++ if (0 == pwrSetting.SlotPowerVoltageMask) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: No matching voltage for OCR \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Slot Pwr Mask 0x%X for OCR:0x%8.8X \n",
++ pwrSetting.SlotPowerVoltageMask,*pOCRvalue));
++ status = _IssueConfig(pHcd,SDCONFIG_POWER_CTRL,&pwrSetting,sizeof(pwrSetting));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set power in hcd \n"));
++ break;
++ }
++ /* delay for power to settle */
++ OSSleep(pBusContext->PowerSettleDelay);
++ /* save off for drivers */
++ pHcd->CardProperties.CardVoltage = pwrSetting.SlotPowerVoltageMask;
++
++ } while (FALSE);
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ConvertEncodedTransSpeed - convert encoded TRANS_SPEED value to a clock rate
++ Input: TransSpeedValue - encoded transfer speed value
++ Output:
++ Return: appropriate SD clock rate
++ Notes: This function returns a rate of 0, if it could not be determined.
++ This function can check tran speed values for SD,SDIO and MMC cards
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SD_BUSCLOCK_RATE ConvertEncodedTransSpeed(UINT8 TransSpeedValue)
++{
++ SD_BUSCLOCK_RATE transfMul = 0;
++ UINT8 timeVal = 0;
++
++ switch (TransSpeedValue & TRANSFER_UNIT_MULTIPIER_MASK) {
++ case 0:
++ transfMul = 10000;
++ break;
++ case 1:
++ transfMul = 100000;
++ break;
++ case 2:
++ transfMul = 1000000;
++ break;
++ case 3:
++ transfMul = 10000000;
++ break;
++ default:
++ transfMul = 0;
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Card transfer multipler is wrong (val=0x%X)! \n",
++ TransSpeedValue));
++ break;
++ }
++
++ switch ((TransSpeedValue & TIME_VALUE_MASK) >> TIME_VALUE_SHIFT) {
++ case 1: timeVal = 10; break;
++ case 2: timeVal = 12; break;
++ case 3: timeVal = 13; break;
++ case 4: timeVal = 15; break;
++ case 5: timeVal = 20; break;
++ case 6: timeVal = 25; break;
++ case 7: timeVal = 30; break;
++ case 8: timeVal = 35; break;
++ case 9: timeVal = 40; break;
++ case 10: timeVal = 45; break;
++ case 11: timeVal = 50; break;
++ case 12: timeVal = 55; break;
++ case 13: timeVal = 60; break;
++ case 14: timeVal = 70; break;
++ case 15: timeVal = 80; break;
++ default: timeVal = 0;
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Card time value is wrong (val=0x%X)! \n",
++ TransSpeedValue));
++ break;
++ }
++
++ if ((transfMul != 0) && (timeVal != 0)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Card Reported Max: %d Hz (0x%X) \n",
++ (timeVal*transfMul), TransSpeedValue));
++ return timeVal*transfMul;
++ }
++
++ return 0;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SelectDeselectCard - Select or deselect a card
++ Input: pHcd - HCD object
++ Select - select the card
++ Output:
++ Return: status
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS SelectDeselectCard(PSDHCD pHcd, BOOL Select)
++{
++ SDIO_STATUS status;
++
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* SPI mode cards do not support selection */
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ if (!Select) {
++ /* deselect, note that deselecting a card does not return a response */
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD7,0,
++ SDREQ_FLAGS_NO_RESP,NULL);
++ } else {
++ /* select */
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD7,(pHcd->CardProperties.RCA << 16),
++ SDREQ_FLAGS_RESP_R1B,NULL);
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Failed to %s card, RCA:0x%X Err:%d \n",
++ (Select ? "Select":"Deselect"), pHcd->CardProperties.RCA, status));
++ }
++ return status;
++}
++
++/* reorder a buffer by swapping MSB with LSB */
++static void ReorderBuffer(UINT8 *pBuffer, INT Bytes)
++{
++ UINT8 *pEnd;
++ UINT8 temp;
++
++ DBG_ASSERT(!(Bytes & 1));
++ /* point to the end */
++ pEnd = &pBuffer[Bytes - 1];
++ /* divide in half */
++ Bytes = Bytes >> 1;
++
++ while (Bytes) {
++ temp = *pBuffer;
++ /* swap bytes */
++ *pBuffer = *pEnd;
++ *pEnd = temp;
++ pBuffer++;
++ pEnd--;
++ Bytes--;
++ }
++}
++
++#define ADJUST_OPER_CLOCK(pBusMode,Clock) \
++ (pBusMode)->ClockRate = min((SD_BUSCLOCK_RATE)(Clock),(pBusMode)->ClockRate)
++#define ADJUST_OPER_BLOCK_LEN(pCaps,Length) \
++ (pCaps)->OperBlockLenLimit = min((UINT16)(Length),(pCaps)->OperBlockLenLimit)
++#define ADJUST_OPER_BLOCK_COUNT(pCaps,Count) \
++ (pCaps)->OperBlockCountLimit = min((UINT16)(Count),(pCaps)->OperBlockCountLimit)
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetBusParameters - Get bus parameters for a card
++ Input: pHcd - HCD object
++ pBusMode - current bus mode on entry
++ Output: pBusMode - new adjusted bus mode
++ Return: status
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS GetBusParameters(PSDHCD pHcd, PSDCONFIG_BUS_MODE_DATA pBusMode)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 temp;
++ UINT32 tplAddr;
++ struct SDIO_FUNC_EXT_COMMON_TPL func0ext;
++ UINT8 scrRegister[SD_SCR_BYTES];
++ SD_BUSCLOCK_RATE cardReportedRate = 0;
++ PSDREQUEST pReq = NULL;
++ BOOL spiMode = FALSE;
++
++
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_SPI) {
++ spiMode = TRUE;
++ }
++
++ if (!spiMode) {
++ /* set highest bus mode bus driver is allowing (non-SPI), the code below will
++ * adjust to lower or equal settings */
++ pBusMode->BusModeFlags = pBusContext->DefaultBusMode;
++ }
++ /* set operational parameters */
++ pBusMode->ClockRate = pBusContext->DefaultOperClock;
++ pHcd->CardProperties.OperBlockLenLimit = pBusContext->DefaultOperBlockLen;
++ pHcd->CardProperties.OperBlockCountLimit = pBusContext->DefaultOperBlockCount;
++
++ /* adjust operational block counts and length to match HCD */
++ ADJUST_OPER_BLOCK_LEN(&pHcd->CardProperties,pHcd->MaxBytesPerBlock);
++ ADJUST_OPER_BLOCK_COUNT(&pHcd->CardProperties,pHcd->MaxBlocksPerTrans);
++ /* limit operational clock to the max clock rate */
++ ADJUST_OPER_CLOCK(pBusMode,pHcd->MaxClockRate);
++
++ if (!spiMode) {
++ /* check HCD bus mode */
++ if (!(pHcd->Attributes & SDHCD_ATTRIB_BUS_4BIT) ||
++ ((pHcd->CardProperties.Flags & CARD_SDIO) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_NO_4BIT_IRQ)) ) {
++
++ if (pHcd->Attributes & SDHCD_ATTRIB_BUS_4BIT) {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO Card Detected, but host does not support IRQs in 4 bit mode - dropping to 1 bit. \n"));
++ }
++ /* force to 1 bit mode */
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++ }
++
++ /* now do various card inquiries to drop the bus mode or clock
++ * none of these checks can raise the bus mode or clock higher that what
++ * was initialized above */
++ do {
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ if (pHcd->CardProperties.Flags & (CARD_SD | CARD_MMC)) {
++ /* allocate a request for response data we'll need */
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ }
++
++ if (!spiMode && (pHcd->CardProperties.Flags & CARD_MMC)) {
++ /* MMC cards all run in 1 bit mode */
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++
++ if (pHcd->CardProperties.Flags & CARD_SD) {
++ DBG_ASSERT(pReq != NULL);
++ DBG_PRINT(SDDBG_TRACE, ("Getting SCR from SD Card..\n"));
++ /* read SCR (requires data transfer) to get supported modes */
++ status = _IssueBusRequestBd(pHcd,ACMD51,0,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_APP_CMD |
++ SDREQ_FLAGS_DATA_TRANS,
++ pReq,&scrRegister,SD_SCR_BYTES);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SD card does not have SCR. \n"));
++ if (!spiMode) {
++ /* switch it to 1 bit mode */
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ /* we have to reorder this buffer since the SCR is sent MSB first on the data
++ * data bus */
++ ReorderBuffer(scrRegister,SD_SCR_BYTES);
++ /* got the SCR */
++ DBG_PRINT(SDDBG_TRACE, ("SD SCR StructRev:0x%X, Flags:0x%X \n",
++ GET_SD_SCR_STRUCT_VER(scrRegister),
++ GET_SD_SCR_BUSWIDTHS_FLAGS(scrRegister)));
++ /* set the revision */
++ switch (GET_SD_SCR_SDSPEC_VER(scrRegister)) {
++ case SCR_SD_SPEC_1_00:
++ DBG_PRINT(SDDBG_TRACE, ("SD Spec Revision 1.01 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = SD_REVISION_1_01;
++ break;
++ case SCR_SD_SPEC_1_10:
++ DBG_PRINT(SDDBG_TRACE, ("SD Spec Revision 1.10 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = SD_REVISION_1_10;
++ break;
++ default:
++ DBG_PRINT(SDDBG_WARN, ("SD Spec Revision is greater than 1.10 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = SD_REVISION_1_10;
++ break;
++ }
++
++ if (!(GET_SD_SCR_BUSWIDTHS(scrRegister) & SCR_BUS_SUPPORTS_4_BIT)) {
++ if (!spiMode) {
++ DBG_PRINT(SDDBG_WARN, ("SD SCR reports 1bit only Mode \n"));
++ /* switch it to 1 bit mode */
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++ }
++ }
++ }
++
++ if (pHcd->CardProperties.Flags & (CARD_SD | CARD_MMC)) {
++ DBG_ASSERT(pReq != NULL);
++ /* de-select the card in order to get the CSD */
++ status = SelectDeselectCard(pHcd,FALSE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to deselect card before getting CSD \n"));
++ break;
++ }
++ /* Get CSD for SD or MMC cards */
++ if (spiMode) {
++ /* in SPI mode, getting the CSD requires a read data transfer */
++ status = _IssueBusRequestBd(pHcd,CMD9,0,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS,
++ pReq,
++ pHcd->CardProperties.CardCSD,
++ MAX_CSD_CID_BYTES);
++ if (SDIO_SUCCESS(status)) {
++ /* when the CSD is sent over in SPI data mode, it comes to us in MSB first
++ * and thus is not ordered correctly as defined in the SD spec */
++ ReorderBuffer(pHcd->CardProperties.CardCSD,MAX_CSD_CID_BYTES);
++ }
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD9,
++ (pHcd->CardProperties.RCA << 16),
++ SDREQ_FLAGS_RESP_R2,
++ pReq);
++ if (SDIO_SUCCESS(status)) {
++ /* save the CSD */
++ memcpy(pHcd->CardProperties.CardCSD,pReq->Response,MAX_CARD_RESPONSE_BYTES);
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get CSD, Err:%d \n",
++ status));
++ break;
++ }
++ /* for MMC cards, the spec version is in the CSD */
++ if (pHcd->CardProperties.Flags & CARD_MMC) {
++ DBG_PRINT(SDDBG_TRACE, ("MMC Spec version : (0x%2.2X) \n",
++ GET_MMC_SPEC_VERSION(pHcd->CardProperties.CardCSD)));
++ switch (GET_MMC_SPEC_VERSION(pHcd->CardProperties.CardCSD)) {
++ case MMC_SPEC_1_0_TO_1_2:
++ case MMC_SPEC_1_4:
++ case MMC_SPEC_2_0_TO_2_2:
++ DBG_PRINT(SDDBG_WARN, ("MMC Spec version less than 3.1 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = MMC_REVISION_1_0_2_2;
++ break;
++ case MMC_SPEC_3_1:
++ DBG_PRINT(SDDBG_TRACE, ("MMC Spec version 3.1 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = MMC_REVISION_3_1;
++ break;
++ case MMC_SPEC_4_0_TO_4_1:
++ DBG_PRINT(SDDBG_TRACE, ("MMC Spec version 4.0-4.1 \n"));
++ pHcd->CardProperties.SD_MMC_Revision = MMC_REVISION_4_0;
++ break;
++ default:
++ pHcd->CardProperties.SD_MMC_Revision = MMC_REVISION_3_1;
++ DBG_PRINT(SDDBG_WARN, ("MMC Spec version greater than 4.1\n"));
++ break;
++ }
++ }
++ /* re-select the card */
++ status = SelectDeselectCard(pHcd,TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to re-select card after getting CSD \n"));
++ break;
++ }
++ }
++#endif // CT_CONFIG_NO_SDMMC
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ if ((pHcd->CardProperties.Flags & CARD_SD) &&
++ !(pHcd->CardProperties.Flags & CARD_SDIO) &&
++ SDDEVICE_IS_SD_REV_GTEQ_1_10(pHcd->pPseudoDev) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_SD_HIGH_SPEED) &&
++ !spiMode) {
++ UINT32 arg;
++ PUINT8 pSwitchStatusBlock = KernelAlloc(SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++
++ if (NULL == pSwitchStatusBlock) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ arg = SD_SWITCH_FUNC_ARG_GROUP_CHECK(SD_SWITCH_HIGH_SPEED_GROUP,
++ SD_SWITCH_HIGH_SPEED_FUNC_NO);
++
++ /* for 1.10 SD cards, check if high speed mode is supported */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Checking SD Card for switchable functions (CMD6 arg:0x%X)\n",arg));
++
++ /* issue simple data transfer request to read the switch status */
++ status = _IssueBusRequestBd(pHcd,
++ CMD6,
++ arg,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS,
++ pReq,
++ pSwitchStatusBlock,
++ SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++
++ if (SDIO_SUCCESS(status)) {
++ UINT16 switchGroupMask;
++ /* need to reorder this since cards send this MSB first */
++ ReorderBuffer(pSwitchStatusBlock,SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++ switchGroupMask = SD_SWITCH_FUNC_STATUS_GET_GRP_BIT_MASK(pSwitchStatusBlock,SD_SWITCH_HIGH_SPEED_GROUP);
++ DBG_PRINT(SDDBG_TRACE, ("SD Card Switch Status Group1 Mask:0x%X Max Current:%d\n",
++ switchGroupMask, SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pSwitchStatusBlock) ));
++ if (SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pSwitchStatusBlock) == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: SD Switch Status block has zero max current \n"));
++ SDLIB_PrintBuffer(pSwitchStatusBlock,
++ SD_SWITCH_FUNC_STATUS_BLOCK_BYTES,
++ "SDIO Bus Driver: SD Switch Status Block Error");
++ } else {
++ /* check HS support */
++ if (switchGroupMask & (1 << SD_SWITCH_HIGH_SPEED_FUNC_NO)) {
++ DBG_PRINT(SDDBG_TRACE, ("SD Card Supports High Speed Mode\n"));
++ /* set the rate, this will override the CSD value */
++ cardReportedRate = SD_HS_MAX_BUS_CLOCK;
++ pBusMode->BusModeFlags |= SDCONFIG_BUS_MODE_SD_HS;
++ }
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get SD Switch Status block (%d)\n", status));
++ /* just fall through, we'll handle this like a normal SD card */
++ status = SDIO_STATUS_SUCCESS;
++ }
++
++ KernelFree(pSwitchStatusBlock);
++ }
++
++
++#endif // CT_CONFIG_NO_SDMMC
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++
++
++ if ((pHcd->CardProperties.Flags & CARD_MMC) &&
++ SDDEVICE_IS_MMC_REV_GTEQ_4_0(pHcd->pPseudoDev) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_MMC_HIGH_SPEED) &&
++ !spiMode) {
++ /* for MMC cards, get the Extended CSD to get the High speed and
++ * wide bus paramaters */
++
++ PUINT8 pExtData = KernelAlloc(MMC_EXT_CSD_SIZE);
++
++ if (NULL == pExtData) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ /* issue simple data transfer request to read the extended CSD */
++ status = _IssueBusRequestBd(pHcd,MMC_CMD8,0,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS,
++ pReq,
++ pExtData,
++ MMC_EXT_CSD_SIZE);
++ if (SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE, ("MMC Ext CSD Version: 0x%X Card Type: 0x%X\n",
++ pExtData[MMC_EXT_VER_OFFSET],pExtData[MMC_EXT_CARD_TYPE_OFFSET]));
++ /* check HS support */
++ if (pExtData[MMC_EXT_CARD_TYPE_OFFSET] & MMC_EXT_CARD_TYPE_HS_52) {
++ /* try 52 Mhz */
++ cardReportedRate = 52000000;
++ pBusMode->BusModeFlags |= SDCONFIG_BUS_MODE_MMC_HS;
++ } else if (pExtData[MMC_EXT_CARD_TYPE_OFFSET] & MMC_EXT_CARD_TYPE_HS_26) {
++ /* try 26MHZ */
++ cardReportedRate = 26000000;
++ pBusMode->BusModeFlags |= SDCONFIG_BUS_MODE_MMC_HS;
++ } else {
++ /* doesn't report high speed capable */
++ cardReportedRate = 0;
++ }
++
++ if (cardReportedRate && !spiMode) {
++ /* figure out the bus mode */
++ if (pHcd->Attributes & SDHCD_ATTRIB_BUS_MMC8BIT) {
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_MMC8_BIT);
++ } else if (pHcd->Attributes & SDHCD_ATTRIB_BUS_4BIT) {
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags, SDCONFIG_BUS_WIDTH_4_BIT);
++ } else {
++ /* we leave it to default to 1 bit mode */
++ }
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get MMC Extended CSD \n"));
++ /* just fall through, we'll do without the extended information
++ * and run it like a legacy MMC card */
++ status = SDIO_STATUS_SUCCESS;
++ }
++
++ KernelFree(pExtData);
++ }
++
++#endif // CT_CONFIG_NO_SDMMC
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++
++
++ if (pHcd->CardProperties.Flags & (CARD_SD | CARD_MMC)) {
++
++ if (0 == cardReportedRate) {
++ /* extract rate from CSD only if it was not set by earlier tests */
++ cardReportedRate = ConvertEncodedTransSpeed(
++ GET_SD_CSD_TRANS_SPEED(pHcd->CardProperties.CardCSD));
++ /* fall through and test for zero again */
++ }
++
++ if (cardReportedRate != 0) {
++ /* adjust clock based on what the card can handle */
++ ADJUST_OPER_CLOCK(pBusMode,cardReportedRate);
++ } else {
++#ifdef DEBUG
++ /* something is wrong with the CSD */
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_TRACE) {
++ SDLIB_PrintBuffer(pHcd->CardProperties.CardCSD,
++ MAX_CARD_RESPONSE_BYTES,
++ "SDIO Bus Driver: CSD Dump");
++ }
++#endif
++ /* can't figure out the card rate, so set reasonable defaults */
++ if (pHcd->CardProperties.Flags & CARD_SD) {
++ ADJUST_OPER_CLOCK(pBusMode,SD_MAX_BUS_CLOCK);
++ } else {
++ ADJUST_OPER_CLOCK(pBusMode,MMC_MAX_BUS_CLOCK);
++ }
++ }
++ }
++
++
++#endif // CT_CONFIG_NO_SDMMC
++
++
++ /* note, we do SDIO card "after" SD in case this is a combo card */
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++ /* read card capabilities */
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev,
++ SDIO_CARD_CAPS_REG,
++ &pHcd->CardProperties.SDIOCaps);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Card Caps: 0x%X \n",pHcd->CardProperties.SDIOCaps));
++ if (pHcd->CardProperties.SDIOCaps & SDIO_CAPS_LOW_SPEED) {
++ /* adjust max clock for LS device */
++ ADJUST_OPER_CLOCK(pBusMode,SDIO_LOW_SPEED_MAX_BUS_CLOCK);
++ /* adjust bus if LS device does not support 4 bit mode */
++ if (!(pHcd->CardProperties.SDIOCaps & SDIO_CAPS_4BIT_LS)) {
++ if (!spiMode) {
++ /* low speed device does not support 4 bit mode, force us to 1 bit */
++ SDCONFIG_SET_BUS_WIDTH(pBusMode->BusModeFlags,
++ SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++ }
++ }
++
++ /* check if 1.2 card supports high speed mode, checking HCD as well*/
++ if (SDDEVICE_IS_SDIO_REV_GTEQ_1_20(pHcd->pPseudoDev) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_SD_HIGH_SPEED) &&
++ !spiMode) {
++ UCHAR hsControl = 0;
++
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev,
++ SDIO_HS_CONTROL_REG,
++ &hsControl);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Failed to read high speed control (%d) \n",status));
++ /* reset status and continue */
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ if (hsControl & SDIO_HS_CONTROL_SHS) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Card Supports High Speed Mode\n"));
++ pBusMode->BusModeFlags |= SDCONFIG_BUS_MODE_SD_HS;
++ }
++ }
++
++ }
++
++ cardReportedRate = 0;
++ temp = sizeof(func0ext);
++ tplAddr = pHcd->CardProperties.CommonCISPtr;
++ /* get the FUNCE tuple */
++ status = SDLIB_FindTuple(pHcd->pPseudoDev,
++ CISTPL_FUNCE,
++ &tplAddr,
++ (PUINT8)&func0ext,
++ &temp);
++ if (!SDIO_SUCCESS(status) || (temp < sizeof(func0ext))) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Function 0 Ext. Tuple Missing (Got size:%d) \n", temp));
++ /* reset status */
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ /* convert encoded value to rate */
++ cardReportedRate = ConvertEncodedTransSpeed(func0ext.MaxTransSpeed);
++ }
++
++ if (cardReportedRate != 0) {
++ if (pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) {
++ if (cardReportedRate <= SD_MAX_BUS_CLOCK) {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO Function tuple reports clock:%d Hz, with advertised High Speed support \n", cardReportedRate));
++ /* back off high speed support */
++ pBusMode->BusModeFlags &= ~SDCONFIG_BUS_MODE_SD_HS;
++ }
++ } else {
++ if (cardReportedRate > SD_MAX_BUS_CLOCK) {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO Function tuple reports clock:%d Hz, without advertising High Speed support..using 25Mhz \n", cardReportedRate));
++ cardReportedRate = SD_MAX_BUS_CLOCK;
++ }
++ }
++ /* adjust clock based on what the card can handle */
++ ADJUST_OPER_CLOCK(pBusMode,cardReportedRate);
++
++ } else {
++ /* set a reasonable default */
++ ADJUST_OPER_CLOCK(pBusMode,SD_MAX_BUS_CLOCK);
++ }
++ }
++ } while (FALSE);
++
++ if (pReq != NULL) {
++ FreeRequest(pReq);
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetOperationalBusMode - set operational bus mode
++ Input: pDevice - pDevice that is requesting the change
++ pBusMode - operational bus mode
++ Output: pBusMode - on return will have the actual clock rate set
++ Return: status
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SetOperationalBusMode(PSDDEVICE pDevice,
++ PSDCONFIG_BUS_MODE_DATA pBusMode)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UCHAR regData;
++ UINT32 arg;
++ UINT32 switcharg;
++ PSDHCD pHcd = pDevice->pHcd;
++
++ /* synchronize access for updating bus mode settings */
++ status = SemaphorePendInterruptable(&pDevice->pHcd->ConfigureOpsSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ do {
++
++ if (!IS_CARD_PRESENT(pHcd)) {
++ /* for an empty slot (a Pseudo dev was passed in) we still allow the
++ * bus mode to be set for the card detect
++ * polling */
++ status = _IssueConfig(pHcd,SDCONFIG_BUS_MODE_CTRL,pBusMode,sizeof(SDCONFIG_BUS_MODE_DATA));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set bus mode in hcd : Err:%d \n",
++ status));
++ }
++ /* nothing more to do */
++ break;
++ }
++
++
++ if ((pBusMode->BusModeFlags == SDDEVICE_GET_BUSMODE_FLAGS(pDevice)) &&
++ (pBusMode->ClockRate == SDDEVICE_GET_OPER_CLOCK(pDevice))) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver: Bus mode already set, nothing to do\n"));
++ pBusMode->ActualClockRate = SDDEVICE_GET_OPER_CLOCK(pDevice);
++ break;
++ }
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ if (pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_MMC_HS) {
++ if (!(pHcd->Attributes & SDHCD_ATTRIB_MMC_HIGH_SPEED)) {
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: HCD does not support MMC High Speed\n"));
++ break;
++ }
++ }
++#endif
++
++
++ if (pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) {
++ if (!(pHcd->Attributes & SDHCD_ATTRIB_SD_HIGH_SPEED)) {
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: HCD does not support SD High Speed\n"));
++ break;
++ }
++ }
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* before we set the operational clock and mode, configure the clock for high
++ * speed mode on the card , if necessary */
++ if ((pHcd->CardProperties.Flags & CARD_MMC) &&
++ (pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_MMC_HS) &&
++ !(SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_MMC_HS)) {
++
++ switcharg = MMC_SWITCH_BUILD_ARG(MMC_SWITCH_CMD_SET0,
++ MMC_SWITCH_WRITE_BYTE,
++ MMC_EXT_HS_TIMING_OFFSET,
++ MMC_EXT_HS_TIMING_ENABLE);
++ status = _IssueSimpleBusRequest(pHcd,
++ MMC_CMD_SWITCH,
++ switcharg,
++ SDREQ_FLAGS_RESP_R1B,
++ NULL);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: Failed to switch MMC High Speed Mode (arg:0x%X): %d \n",
++ switcharg, status));
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: High Speed MMC enabled (arg:0x%X)\n",
++ switcharg));
++ }
++#endif
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++
++
++ /* before setting bus mode and clock in the HCD, switch card to high speed mode
++ * if necessary */
++ if ((pHcd->CardProperties.Flags & CARD_SD) &&
++ (pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) &&
++ !(SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_SD_HS)) {
++ UINT32 arg;
++ PUINT8 pSwitchStatusBlock;
++
++ pSwitchStatusBlock = KernelAlloc(SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++
++ if (NULL == pSwitchStatusBlock) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ /* set high speed group */
++ arg = SD_SWITCH_FUNC_ARG_GROUP_SET(SD_SWITCH_HIGH_SPEED_GROUP,
++ SD_SWITCH_HIGH_SPEED_FUNC_NO);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Setting SD Card for High Speed mode (CMD6 arg:0x%X)\n",arg));
++
++ /* issue simple data transfer request to switch modes */
++ status = _IssueBusRequestBd(pHcd,
++ CMD6,
++ arg,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS,
++ NULL,
++ pSwitchStatusBlock,
++ SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++
++ if (SDIO_SUCCESS(status)) {
++ ReorderBuffer(pSwitchStatusBlock,SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD High Speed Result, Got Max Current:%d mA, SwitchResult:0x%X \n",
++ SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pSwitchStatusBlock),
++ SDSwitchGetSwitchResult(pSwitchStatusBlock, SD_SWITCH_HIGH_SPEED_GROUP)));
++ if (SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pSwitchStatusBlock) == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Error in Status Block after High Speed Switch (current==0) \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ }
++ if (SDSwitchGetSwitchResult(pSwitchStatusBlock, SD_SWITCH_HIGH_SPEED_GROUP) !=
++ SD_SWITCH_HIGH_SPEED_FUNC_NO) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: Error in Status Block after High Speed Switch (Group1 did not switch) \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ }
++ if (SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD High Speed Mode Enabled \n"));
++ } else {
++ SDLIB_PrintBuffer(pSwitchStatusBlock,
++ SD_SWITCH_FUNC_STATUS_BLOCK_BYTES,
++ "SDIO Bus Driver: SD Switch Status Block Error");
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to Set SD High Speed Mode (%d) \n",status));
++ }
++ KernelFree(pSwitchStatusBlock);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++
++#endif
++
++
++ /* enable/disable high speed mode for SDIO card */
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++ BOOL doSet = TRUE;
++
++ if ((pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) &&
++ !(SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_SD_HS)) {
++ /* enable */
++ regData = SDIO_HS_CONTROL_EHS;
++ } else if (!(pBusMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) &&
++ (SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_SD_HS)) {
++ /* disable */
++ regData = 0;
++ } else {
++ /* do nothing */
++ doSet = FALSE;
++ }
++
++ if (doSet) {
++ status = Cmd52WriteByteCommon(pDevice,
++ SDIO_HS_CONTROL_REG,
++ ®Data);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to %s HS mode in SDIO card : Err:%d\n",
++ (SDIO_HS_CONTROL_EHS == regData) ? "enable":"disable" , status));
++ break;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver:SDIO Card %s for High Speed mode \n",
++ (SDIO_HS_CONTROL_EHS == regData) ? "enabled":"disabled" ));
++ }
++ }
++ }
++
++ /* use synchronize-with-bus request version, this may have been requested by a
++ * function driver */
++ status = SDLIB_IssueConfig(pDevice,
++ SDCONFIG_BUS_MODE_CTRL,
++ pBusMode,
++ sizeof(SDCONFIG_BUS_MODE_DATA));
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set bus mode in hcd : Err:%d \n",
++ status));
++ break;
++ }
++
++ /* check requested bus width against the current mode */
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) ==
++ SDCONFIG_GET_BUSWIDTH(pHcd->CardProperties.BusMode)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Bus mode set, no width change\n"));
++ break;
++ }
++
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_SPI) {
++ /* nothing more to do for SPI */
++ break;
++ }
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* set the bus width for SD and combo cards */
++ if (pHcd->CardProperties.Flags & CARD_SD) {
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_4_BIT) {
++ /* turn off card detect resistor */
++ status = _IssueSimpleBusRequest(pHcd,
++ ACMD42,
++ 0, /* disable CD */
++ SDREQ_FLAGS_APP_CMD | SDREQ_FLAGS_RESP_R1,
++ NULL);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Failed to disable CD Res: %d \n",
++ status)); /* this should be okay */
++ }
++ arg = SD_ACMD6_BUS_WIDTH_4_BIT;
++ } else {
++ /* don't need to turn off CD in 1 bit mode, just set mode */
++ arg = SD_ACMD6_BUS_WIDTH_1_BIT;
++
++ }
++ /* set the bus width */
++ status = _IssueSimpleBusRequest(pHcd,
++ ACMD6,
++ arg, /* set bus mode */
++ SDREQ_FLAGS_APP_CMD | SDREQ_FLAGS_RESP_R1,
++ NULL);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set bus width: %d \n",
++ status));
++ break;
++ }
++ }
++
++#endif
++
++
++ /* set bus width for SDIO cards */
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++ /* default */
++ regData = CARD_DETECT_DISABLE | SDIO_BUS_WIDTH_1_BIT;
++
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_4_BIT) {
++ /* turn off card detect resistor and set buswidth */
++ regData = CARD_DETECT_DISABLE | SDIO_BUS_WIDTH_4_BIT;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Enabling 4 bit mode on card \n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Enabling 1 bit mode on card \n"));
++ }
++ status = Cmd52WriteByteCommon(pDevice,
++ SDIO_BUS_IF_REG,
++ ®Data);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set bus mode in Card : Err:%d\n",
++ status));
++ break;
++ }
++
++ /* check for 4-bit interrupt detect mode */
++ if ((SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_4_BIT) &&
++ (pHcd->CardProperties.SDIOCaps & SDIO_CAPS_INT_MULTI_BLK) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_MULTI_BLK_IRQ)) {
++ /* enable interrupts between blocks, this doesn't actually turn on interrupts
++ * it merely allows interrupts to be asserted in the inter-block gap */
++ pHcd->CardProperties.SDIOCaps |= SDIO_CAPS_ENB_INT_MULTI_BLK;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: 4-Bit Multi-blk Interrupt support enabled\n"));
++ } else {
++ /* make sure this is disabled */
++ pHcd->CardProperties.SDIOCaps &= ~SDIO_CAPS_ENB_INT_MULTI_BLK;
++ }
++
++ status = Cmd52WriteByteCommon(pDevice,
++ SDIO_CARD_CAPS_REG,
++ &pHcd->CardProperties.SDIOCaps);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to update Card Caps register Err:%d\n",
++ status));
++ break;
++ }
++ }
++
++ /* set data bus width for MMC */
++ if (pHcd->CardProperties.Flags & CARD_MMC) {
++ UINT8 buswidth = 0;
++
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_4_BIT) {
++ buswidth = MMC_EXT_BUS_WIDTH_4_BIT;
++ } else if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_MMC8_BIT) {
++ buswidth = MMC_EXT_BUS_WIDTH_8_BIT;
++ } else {
++ /* normal 1 bit mode .. nothing to do */
++ break;
++ }
++ /* now set the bus mode on the card */
++ switcharg = MMC_SWITCH_BUILD_ARG(MMC_SWITCH_CMD_SET0,
++ MMC_SWITCH_WRITE_BYTE,
++ MMC_EXT_BUS_WIDTH_OFFSET,
++ buswidth);
++
++ status = _IssueSimpleBusRequest(pHcd,
++ MMC_CMD_SWITCH,
++ switcharg,
++ SDREQ_FLAGS_RESP_R1B,
++ NULL);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set MMC bus width (arg:0x%X): %d \n",
++ switcharg, status));
++ break;
++ }
++
++ if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_4_BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: 4 bit MMC mode enabled (arg:0x%X) \n",
++ switcharg));
++ } else if (SDCONFIG_GET_BUSWIDTH(pBusMode->BusModeFlags) == SDCONFIG_BUS_WIDTH_MMC8_BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: 8-Bit MMC mode enabled (arg:0x%X) \n",
++ switcharg));
++ }
++ }
++
++ } while (FALSE);
++
++ if (SDIO_SUCCESS(status)) {
++ /* set the operating mode */
++ pHcd->CardProperties.BusMode = pBusMode->BusModeFlags;
++ /* set the actual clock rate */
++ pHcd->CardProperties.OperBusClock = pBusMode->ActualClockRate;
++ }
++
++ SemaphorePost(&pDevice->pHcd->ConfigureOpsSem);
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ CardInitSetup - setup host for card initialization
++ Input: pHcd - HCD object
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS CardInitSetup(PSDHCD pHcd)
++{
++ SDCONFIG_INIT_CLOCKS_DATA initClocks;
++ SDCONFIG_BUS_MODE_DATA busMode;
++ UINT32 OCRvalue;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ ZERO_OBJECT(initClocks);
++ ZERO_OBJECT(busMode);
++ /* setup defaults */
++ initClocks.NumberOfClocks = SDMMC_MIN_INIT_CLOCKS;
++ busMode.ClockRate = SD_INIT_BUS_CLOCK;
++
++ /* check for SPI only */
++ if (pHcd->Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ /* SPI cards startup in non-CRC mode with the exception of CMD0, the
++ * HCDs must issue CMD0 with the correct CRC , the spec shows that a
++ * CMD 0 sequence is 0x40,0x00,0x00,0x00,0x00,0x95 */
++ busMode.BusModeFlags = SDCONFIG_BUS_WIDTH_SPI | SDCONFIG_BUS_MODE_SPI_NO_CRC;
++ }
++ /* check if host supports 1 bit mode */
++ /* TODO : if host supports power switching, we can
++ * could initialize cards in SPI mode first */
++ if (pHcd->Attributes & SDHCD_ATTRIB_BUS_1BIT) {
++ busMode.BusModeFlags = SDCONFIG_BUS_WIDTH_1_BIT;
++ }
++
++ /* set initial VDD, starting at the highest allowable voltage and working
++ * our way down */
++ if (pHcd->SlotVoltageCaps & SLOT_POWER_3_3V) {
++ OCRvalue = SD_OCR_3_2_TO_3_3_VDD;
++ } else if (pHcd->SlotVoltageCaps & SLOT_POWER_3_0V) {
++ OCRvalue = SD_OCR_2_9_TO_3_0_VDD;
++ } else if (pHcd->SlotVoltageCaps & SLOT_POWER_2_8V) {
++ OCRvalue = SD_OCR_2_7_TO_2_8_VDD;
++ } else if (pHcd->SlotVoltageCaps & SLOT_POWER_2_0V) {
++ OCRvalue = SD_OCR_1_9_TO_2_0_VDD;
++ } else if (pHcd->SlotVoltageCaps & SLOT_POWER_1_8V) {
++ OCRvalue = SD_OCR_1_7_TO_1_8_VDD;
++ } else if (pHcd->SlotVoltageCaps & SLOT_POWER_1_6V) {
++ OCRvalue = SD_OCR_1_6_TO_1_7_VDD;
++ } else {
++ DBG_ASSERT(FALSE);
++ OCRvalue = 0;
++ }
++
++ do {
++ /* power up the card */
++ status = AdjustSlotPower(pHcd, &OCRvalue);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to adjust slot power \n"));
++ break;
++ }
++ status = SetOperationalBusMode(pHcd->pPseudoDev,&busMode);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set bus mode \n"));
++ break;
++ }
++ status = _IssueConfig(pHcd,SDCONFIG_SEND_INIT_CLOCKS,&initClocks,sizeof(initClocks));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to send init clocks in hcd \n"));
++ break;
++ }
++
++ } while(FALSE);
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDInitializeCard - initialize card
++ Input: pHcd - HCD object
++ Output: pProperties - card properties
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDInitializeCard(PSDHCD pHcd)
++{
++ SDCONFIG_BUS_MODE_DATA busMode;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq = NULL;
++ UINT32 OCRvalue;
++ UINT32 tplAddr;
++ UINT8 temp;
++ struct SDIO_MANFID_TPL manfid;
++ SDCONFIG_WP_VALUE wpValue;
++ UINT8 cisBuffer[3];
++
++ OCRvalue = 0;
++
++ do {
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Initializing card in SPI mode \n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Initializing card in MMC/SD mode \n"));
++ }
++
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: failed to allocate bus request \n"));
++ break;
++ }
++ memset(pReq, 0, sizeof(SDREQUEST));
++
++ status = CardInitSetup(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to setup card \n"));
++ break;
++ }
++
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ status = _IssueConfig(pHcd,SDCONFIG_GET_WP,&wpValue,sizeof(wpValue));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: host doesn't support Write Protect \n"));
++ } else {
++ if (wpValue) {
++ pHcd->CardProperties.Flags |= CARD_SD_WP;
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: SD WP switch is on \n"));
++ }
++ }
++
++#endif
++
++ if (!(pHcd->Attributes & SDHCD_ATTRIB_SLOT_POLLING) &&
++ IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* for non-slot polling HCDs operating in SPI mode
++ * issue CMD0 to reset card state and to place the card
++ * in SPI mode. If slot polling is used, the polling thread
++ * will have already issued a CMD0 to place the card in SPI mode*/
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ INT ii = 256;
++ status = SDIO_STATUS_ERROR;
++ /* if the CMD0 fails, retry it. Some cards have a hard time getting into SPI mode.*/
++ while ((!SDIO_SUCCESS(status)) && (ii-- >= 0)) {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,pReq);
++ OSSleep(20);
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: cmd0 go SPI retries:(256) %d\n", ii));
++
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,pReq);
++ }
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: go-idle failed! \n"));
++ break;
++ }
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Looking for SDIO.. \n"));
++ /* check for SDIO card by trying to read it's OCR */
++ status = ReadOCR(pHcd,CARD_SDIO,pReq,0,&OCRvalue);
++ if (SDIO_SUCCESS(status)) {
++ /* we got a response, this is an SDIO card */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* handle SPI */
++ pHcd->CardProperties.IOFnCount = SPI_SDIO_R4_GET_IO_FUNC_COUNT(pReq->Response);
++ if (SPI_SDIO_R4_IS_MEMORY_PRESENT(pReq->Response)) {
++ /* flag an SD function exists */
++ pHcd->CardProperties.Flags |= CARD_SD;
++ }
++ } else {
++ /* handle native SD */
++ pHcd->CardProperties.IOFnCount = SD_SDIO_R4_GET_IO_FUNC_COUNT(pReq->Response);
++ if (SD_SDIO_R4_IS_MEMORY_PRESENT(pReq->Response)) {
++ /* flag an SD function exists */
++ pHcd->CardProperties.Flags |= CARD_SD;
++ }
++
++ }
++ if (0 == pHcd->CardProperties.IOFnCount) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SDIO Card reports no functions \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ pHcd->CardProperties.Flags = 0;
++ break;
++ }
++ pHcd->CardProperties.Flags |= CARD_SDIO;
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver: SDIO Card, Functions: %d Card Info Flags:0x%X OCR:0x%8.8X\n",
++ pHcd->CardProperties.IOFnCount, pHcd->CardProperties.Flags, OCRvalue));
++ /* adjust slot power for this SDIO card */
++ status = AdjustSlotPower(pHcd, &OCRvalue);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set power in hcd \n"));
++ break;
++ }
++ /* poll for SDIO card ready */
++ status = PollCardReady(pHcd,OCRvalue,CARD_SDIO);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ } else if (status != SDIO_STATUS_BUS_RESP_TIMEOUT){
++ /* major error in hcd, bail */
++ break;
++ }
++
++ /* check if this is an SDIO-only card before continuing */
++ if (!(pHcd->CardProperties.Flags & CARD_SD) && (pHcd->CardProperties.Flags & CARD_SDIO)) {
++ /* this is an SDIO card with no memory function */
++ goto prepareCard;
++ }
++#ifdef CT_CONFIG_NO_SDMMC
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: SDIO card not detected and SD/MMC cards not supported \n"));
++ status = SDIO_STATUS_ERROR;
++ break;
++
++#else
++ if (!(pHcd->CardProperties.Flags & CARD_SDIO)) {
++ /* issue go idle only if we did not find an SDIO function in our earlier test */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,pReq);
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,pReq);
++ }
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: go-idle failed! \n"));
++ break;
++ }
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Looking for SD Memory.. \n"));
++ /* SD Memory Card checking */
++ /* test for present of SD card (stand-alone or combo card) */
++ status = TestPresence(pHcd, CARD_SD, pReq);
++ if (SDIO_SUCCESS(status)) {
++ /* there is an SD Card present, could be part of a combo system */
++ pHcd->CardProperties.Flags |= CARD_SD;
++ if (0 == OCRvalue) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD Memory card detected. \n"));
++ /* no OCR value on entry this is a stand-alone card, go and get it*/
++ status = ReadOCR(pHcd,CARD_SD,pReq,0,&OCRvalue);
++ if (!SDIO_SUCCESS(status) || (OCRvalue == 0)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get OCR (status:%d) \n",
++ status));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD Card Reports OCR:0x%8.8X \n", OCRvalue));
++ status = AdjustSlotPower(pHcd, &OCRvalue);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to adjust power \n"));
++ break;
++ }
++ } else {
++ DBG_ASSERT((pHcd->CardProperties.Flags & (CARD_SD | CARD_SDIO)));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SDIO Combo Card detected \n"));
++ }
++ /* poll for SD card ready */
++ status = PollCardReady(pHcd,OCRvalue,CARD_SD);
++ if (!SDIO_SUCCESS(status)) {
++ /* check if this card has an SDIO function */
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Combo Detected but SD memory function failed \n"));
++ /* allow SDIO functions to load normally */
++ status = SDIO_STATUS_SUCCESS;
++ /* remove SD flag */
++ pHcd->CardProperties.Flags &= ~CARD_SD;
++ } else {
++ break;
++ }
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD Memory ready. \n"));
++ }
++ /* we're done, no need to check for MMC */
++ goto prepareCard;
++ } else if (status != SDIO_STATUS_BUS_RESP_TIMEOUT){
++ /* major error in hcd, bail */
++ break;
++ }
++
++ /* MMC card checking */
++ /* if we get here, these better not be set */
++ DBG_ASSERT(!(pHcd->CardProperties.Flags & (CARD_SD | CARD_SDIO)));
++ /* issue go idle */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_RESP_R1,pReq);
++ } else {
++ status = _IssueSimpleBusRequest(pHcd,CMD0,0,SDREQ_FLAGS_NO_RESP,pReq);
++ }
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: go-idle failed! \n"));
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Looking for MMC.. \n"));
++ status = TestPresence(pHcd, CARD_MMC, pReq);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: unknown card detected \n"));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: MMC Card Detected \n"));
++ pHcd->CardProperties.Flags |= CARD_MMC;
++ /* read the OCR value */
++ status = ReadOCR(pHcd,CARD_MMC,pReq,0,&OCRvalue);
++ if (!SDIO_SUCCESS(status) || (OCRvalue == 0)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Failed to get OCR (status:%d)",
++ status));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: MMC Card Reports OCR:0x%8.8X \n", OCRvalue));
++ /* adjust power */
++ status = AdjustSlotPower(pHcd, &OCRvalue);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to adjust power \n"));
++ break;
++ }
++ /* poll for MMC card ready */
++ status = PollCardReady(pHcd,OCRvalue,CARD_MMC);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* fall through and prepare MMC card */
++
++#endif // CT_CONFIG_NO_SDMMC
++
++
++prepareCard:
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* we're done figuring out what was inserted, and setting up
++ * optimal slot voltage, now we need to prepare the card */
++ if (!IS_HCD_BUS_MODE_SPI(pHcd) &&
++ (pHcd->CardProperties.Flags & (CARD_SD | CARD_MMC))) {
++ /* non-SPI SD or MMC cards need to be moved to the "ident" state before we can get the
++ * RCA or select the card using the new RCA */
++ status = _IssueSimpleBusRequest(pHcd,CMD2,0,SDREQ_FLAGS_RESP_R2,pReq);
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: failed to move SD/MMC card into ident state \n"));
++ break;
++ }
++ }
++#endif
++
++ if (!IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* non-SPI mode cards need their RCA's setup */
++ if (pHcd->CardProperties.Flags & (CARD_SD | CARD_SDIO)) {
++ /* issue CMD3 to get RCA on SD/SDIO cards */
++ status = _IssueSimpleBusRequest(pHcd,CMD3,0,SDREQ_FLAGS_RESP_R6,pReq);
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: failed to get RCA for SD/SDIO card \n"));
++ break;
++ }
++ pHcd->CardProperties.RCA = SD_R6_GET_RCA(pReq->Response);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: SD/SDIO RCA:0x%X \n",
++ pHcd->CardProperties.RCA));
++ } else if (pHcd->CardProperties.Flags & CARD_MMC) {
++
++#ifndef CT_CONFIG_NO_SDMMC
++ /* for MMC cards, we have to assign a relative card address */
++ /* just a non-zero number */
++ pHcd->CardProperties.RCA = 1;
++ /* issue CMD3 to set the RCA for MMC cards */
++ status = _IssueSimpleBusRequest(pHcd,
++ CMD3,(pHcd->CardProperties.RCA << 16),
++ SDREQ_FLAGS_RESP_R1,pReq);
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: failed to set RCA for MMC card! (err=%d) \n",status));
++ break;
++ }
++
++#endif
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++ }
++ /* select the card in order to get the rest of the card info, applies
++ * to SDIO/SD/MMC cards*/
++ status = SelectDeselectCard(pHcd, TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: failed to select card! \n"));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver, Card now Selected.. \n"));
++
++ if (pHcd->CardProperties.Flags & CARD_SDIO) {
++ /* read SDIO revision register */
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev, CCCR_SDIO_REVISION_REG, &temp);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Revision Reg: 0x%X \n", temp));
++ switch (temp & SDIO_REV_MASK) {
++ case SDIO_REV_1_00:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Spec Revision 1.00 \n"));
++ pHcd->CardProperties.SDIORevision = SDIO_REVISION_1_00;
++ break;
++ case SDIO_REV_1_10:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Spec Revision 1.10 \n"));
++ pHcd->CardProperties.SDIORevision = SDIO_REVISION_1_10;
++ break;
++ case SDIO_REV_1_20:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Spec Revision 1.20 \n"));
++ pHcd->CardProperties.SDIORevision = SDIO_REVISION_1_20;
++ break;
++ default:
++ DBG_PRINT(SDDBG_WARN, ("SDIO Warning: unknown SDIO revision, treating like 1.0 device \n"));
++ pHcd->CardProperties.SDIORevision = SDIO_REVISION_1_00;
++ break;
++ }
++ /* get the common CIS ptr */
++ status = Cmd52ReadMultipleCommon(pHcd->pPseudoDev,
++ SDIO_CMN_CIS_PTR_LOW_REG,
++ cisBuffer,
++ 3);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get CIS ptr, Err:%d", status));
++ break;
++ }
++ /* this is endian-safe*/
++ pHcd->CardProperties.CommonCISPtr = ((UINT32)cisBuffer[0]) |
++ (((UINT32)cisBuffer[1]) << 8) |
++ (((UINT32)cisBuffer[2]) << 16);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Card CIS Ptr: 0x%X \n", pHcd->CardProperties.CommonCISPtr));
++ temp = sizeof(manfid);
++ tplAddr = pHcd->CardProperties.CommonCISPtr;
++ /* get the MANFID tuple */
++ status = SDLIB_FindTuple(pHcd->pPseudoDev,
++ CISTPL_MANFID,
++ &tplAddr,
++ (PUINT8)&manfid,
++ &temp);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Failed to get MANFID tuple err:%d \n", status));
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ /* save this off so that it can be copied into each SDIO Func's SDDEVICE structure */
++ pHcd->CardProperties.SDIO_ManufacturerCode =
++ CT_LE16_TO_CPU_ENDIAN(manfid.ManufacturerCode);
++ pHcd->CardProperties.SDIO_ManufacturerID =
++ CT_LE16_TO_CPU_ENDIAN(manfid.ManufacturerInfo);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MANFID:0x%X, MANFINFO:0x%X \n",
++ pHcd->CardProperties.SDIO_ManufacturerID,
++ pHcd->CardProperties.SDIO_ManufacturerCode));
++ }
++
++ if (pHcd->CardProperties.SDIORevision >= SDIO_REVISION_1_10) {
++ /* read power control */
++ status = Cmd52ReadByteCommon(pHcd->pPseudoDev, SDIO_POWER_CONTROL_REG, &temp);
++ if (SDIO_SUCCESS(status)) {
++ /* check for power control support which indicates the card may use more
++ * than 200 mA */
++ if (temp & SDIO_POWER_CONTROL_SMPC) {
++ /* check that the host can support this. */
++ if (pHcd->MaxSlotCurrent >= SDIO_EMPC_CURRENT_THRESHOLD) {
++ temp = SDIO_POWER_CONTROL_EMPC;
++ /* enable power control on the card */
++ status = Cmd52WriteByteCommon(pHcd->pPseudoDev, SDIO_POWER_CONTROL_REG, &temp);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Busdriver: failed to enable power control (%d) \n",status));
++ break;
++ }
++ /* mark that the card is high power */
++ pHcd->CardProperties.Flags |= CARD_HIPWR;
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Busdriver: Power Control Enabled on SDIO (1.10 or greater) card \n"));
++ } else {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO Busdriver: Card can operate higher than 200mA, host cannot (max:%d) \n",
++ pHcd->MaxSlotCurrent));
++ /* this is not fatal, the card should operate at a reduced rate */
++ }
++ } else {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Busdriver: SDIO 1.10 (or greater) card draws less than 200mA \n"));
++ }
++ } else {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO Busdriver: failed to get POWER CONTROL REG (%d) \n",status));
++ /* fall through and continue on at reduced mode */
++ }
++ }
++ }
++ /* get the current bus parameters */
++ busMode.BusModeFlags = pHcd->CardProperties.BusMode;
++ busMode.ClockRate = pHcd->CardProperties.OperBusClock;
++ /* get the rest of the bus parameters like clock and supported bus width */
++ status = GetBusParameters(pHcd,&busMode);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* check HCD if it wants to run without SPI CRC */
++ if (pHcd->Attributes & SDHCD_ATTRIB_NO_SPI_CRC) {
++ /* hcd would rather not run with CRC we don't need to tell the card since SPI mode
++ * cards power up with CRC initially disabled */
++ busMode.BusModeFlags |= SDCONFIG_BUS_MODE_SPI_NO_CRC;
++ } else {
++ /* first enable SPI CRC checking if the HCD can handle it */
++ status = SDSPIModeEnableDisableCRC(pHcd->pPseudoDev, TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: Failed to set Enable SPI CRC on card \n"));
++ break;
++ }
++ }
++ }
++
++ status = SetOperationalBusMode(pHcd->pPseudoDev, &busMode);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set operational bus mode\n"));
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Oper. Mode: Clock:%d, Bus:0x%X \n",
++ pHcd->CardProperties.OperBusClock,pHcd->CardProperties.BusMode));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Card in TRANS state, Ready: CardInfo Flags 0x%X \n",
++ pHcd->CardProperties.Flags));
++
++ } while (FALSE);
++
++ if (pReq != NULL) {
++ FreeRequest(pReq);
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDQuerySDMMCInfo - query MMC card info
++ Input: pDevice - device
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDQuerySDMMCInfo(PSDDEVICE pDevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq = NULL;
++ UINT8 CID[MAX_CSD_CID_BYTES];
++
++ do {
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ /* de-select the card */
++ status = SelectDeselectCard(pDevice->pHcd,FALSE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to deselect card before getting CID \n"));
++ break;
++ }
++
++ if (SDDEVICE_IS_BUSMODE_SPI(pDevice)) {
++ /* in SPI mode, getting the CSD requires a data transfer */
++ status = _IssueBusRequestBd(pDevice->pHcd,CMD10,0,
++ SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS,
++ pReq,
++ CID,
++ MAX_CSD_CID_BYTES);
++ if (SDIO_SUCCESS(status)) {
++ /* in SPI mode we need to reorder to the CID since SPI data comes in MSB first*/
++ ReorderBuffer(CID,MAX_CSD_CID_BYTES);
++ }
++ } else {
++ /* get the CID */
++ status = _IssueSimpleBusRequest(pDevice->pHcd,
++ CMD10,
++ (SDDEVICE_GET_CARD_RCA(pDevice) << 16),
++ SDREQ_FLAGS_RESP_R2,
++ pReq);
++ if (SDIO_SUCCESS(status)) {
++ /* extract it from the reponse */
++ memcpy(CID,pReq->Response,MAX_CSD_CID_BYTES);
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDQuerySDMMCInfo: failed to get CID. \n"));
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ pDevice->pId[0].SDMMC_ManfacturerID = GET_SD_CID_MANFID(CID);
++ pDevice->pId[0].SDMMC_OEMApplicationID = GET_SD_CID_OEMID(CID);
++#ifdef DEBUG
++ {
++ char pBuf[7];
++
++ pBuf[0] = GET_SD_CID_PN_1(CID);
++ pBuf[1] = GET_SD_CID_PN_2(CID);
++ pBuf[2] = GET_SD_CID_PN_3(CID);
++ pBuf[3] = GET_SD_CID_PN_4(CID);
++ pBuf[4] = GET_SD_CID_PN_5(CID);
++ if (pDevice->pHcd->CardProperties.Flags & CARD_MMC) {
++ pBuf[5] = GET_SD_CID_PN_6(CID);
++ pBuf[6] = 0;
++ } else {
++ pBuf[5] = 0;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDQuerySDMMCInfo: Product String: %s\n", pBuf));
++ }
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("SDQuerySDMMCInfo: ManfID: 0x%X, OEMID:0x%X \n",
++ pDevice->pId[0].SDMMC_ManfacturerID, pDevice->pId[0].SDMMC_OEMApplicationID));
++ }
++ /* re-select card */
++ status = SelectDeselectCard(pDevice->pHcd,TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to re-select card after getting CID \n"));
++ break;
++ }
++ } while (FALSE);
++
++ if (pReq != NULL) {
++ FreeRequest(pReq);
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDQuerySDIOInfo - query SDIO card info
++ Input: pDevice - the device
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDQuerySDIOInfo(PSDDEVICE pDevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 faddress;
++ UINT8 fInfo;
++ UINT32 nextTpl;
++ UINT8 tplLength;
++ UINT8 cisPtrBuffer[3];
++ struct SDIO_FUNC_EXT_FUNCTION_TPL_1_1 funcTuple;
++
++ /* use the card-wide SDIO manufacturer code and ID previously read.*/
++ pDevice->pId[0].SDIO_ManufacturerCode = pDevice->pHcd->CardProperties.SDIO_ManufacturerCode;
++ pDevice->pId[0].SDIO_ManufacturerID = pDevice->pHcd->CardProperties.SDIO_ManufacturerID;
++
++ /* calculate function base address */
++ faddress = CalculateFBROffset(SDDEVICE_GET_SDIO_FUNCNO(pDevice));
++ DBG_ASSERT(faddress != 0);
++
++ do {
++ status = Cmd52ReadByteCommon(pDevice,
++ FBR_FUNC_INFO_REG_OFFSET(faddress),
++ &fInfo);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get function info, Err:%d , using Class:UNKNOWN\n", status));
++ fInfo = 0;
++ pDevice->pId[0].SDIO_FunctionClass = 0;
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ pDevice->pId[0].SDIO_FunctionClass = fInfo & FUNC_INFO_DEVICE_CODE_MASK;
++ }
++
++ if ((FUNC_INFO_DEVICE_CODE_LAST == pDevice->pId[0].SDIO_FunctionClass) &&
++ SDDEVICE_IS_SDIO_REV_GTEQ_1_10(pDevice)) {
++ /* if the device code is the last one, check for 1.1 revision and get the
++ * extended code */
++ status = Cmd52ReadByteCommon(pDevice,
++ FBR_FUNC_EXT_DEVICE_CODE_OFFSET(faddress),
++ &(pDevice->pId[0].SDIO_FunctionClass));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get 1.1 extended DC, Err:%d\n",
++ status));
++ break;
++ }
++ }
++
++ /* get the function CIS ptr */
++ status = Cmd52ReadMultipleCommon(pDevice,
++ FBR_FUNC_CIS_LOW_OFFSET(faddress),
++ cisPtrBuffer,
++ 3);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get FN CIS ptr, Err:%d\n", status));
++ break;
++ }
++ /* endian safe */
++ pDevice->DeviceInfo.AsSDIOInfo.FunctionCISPtr = ((UINT32)cisPtrBuffer[0]) |
++ (((UINT32)cisPtrBuffer[1]) << 8) |
++ (((UINT32)cisPtrBuffer[2]) << 16);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Function:%d, Class:%d FnCISPtr:0x%X \n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice),
++ pDevice->pId[0].SDIO_FunctionClass,pDevice->DeviceInfo.AsSDIOInfo.FunctionCISPtr));
++
++ if (fInfo & FUNC_INFO_SUPPORTS_CSA_MASK) {
++ /* get the function CSA ptr */
++ status = Cmd52ReadMultipleCommon(pDevice,
++ FBR_FUNC_CSA_LOW_OFFSET(faddress),
++ cisPtrBuffer,
++ 3);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get FN CSA ptr, Err:%d \n", status));
++ break;
++ }
++ /* endian safe */
++ pDevice->DeviceInfo.AsSDIOInfo.FunctionCSAPtr = ((UINT32)cisPtrBuffer[0]) |
++ (((UINT32)cisPtrBuffer[1]) << 8) |
++ (((UINT32)cisPtrBuffer[2]) << 16);
++
++ }
++
++ nextTpl = SDDEVICE_GET_SDIO_FUNC_CISPTR(pDevice);
++ /* look for the funce TPL */
++ tplLength = sizeof(funcTuple);
++ /* go get the func CE tuple */
++ status = SDLIB_FindTuple(pDevice,
++ CISTPL_FUNCE,
++ &nextTpl,
++ (PUINT8)&funcTuple,
++ &tplLength);
++
++ if (!SDIO_SUCCESS(status)){
++ /* handles case of bad CIS or missing tupple, allow function driver to handle */
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: Failed to get FuncCE Tuple: %d \n", status));
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++ /* set the max block size */
++ pDevice->DeviceInfo.AsSDIOInfo.FunctionMaxBlockSize =
++ CT_LE16_TO_CPU_ENDIAN(funcTuple.CommonInfo.MaxBlockSize);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Function:%d, MaxBlocks:%d \n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice),
++ pDevice->DeviceInfo.AsSDIOInfo.FunctionMaxBlockSize));
++
++ /* check for MANFID function tuple (SDIO 1.1 or greater) */
++ if (SDDEVICE_IS_SDIO_REV_GTEQ_1_10(pDevice)) {
++ struct SDIO_MANFID_TPL manfid;
++ nextTpl = SDDEVICE_GET_SDIO_FUNC_CISPTR(pDevice);
++ tplLength = sizeof(manfid);
++ /* get the MANFID tuple */
++ status = SDLIB_FindTuple(pDevice,
++ CISTPL_MANFID,
++ &nextTpl,
++ (PUINT8)&manfid,
++ &tplLength);
++ if (SDIO_SUCCESS(status)) {
++ /* this function has a MANFID tuple */
++ pDevice->pId[0].SDIO_ManufacturerCode =
++ CT_LE16_TO_CPU_ENDIAN(manfid.ManufacturerCode);
++ pDevice->pId[0].SDIO_ManufacturerID =
++ CT_LE16_TO_CPU_ENDIAN(manfid.ManufacturerInfo);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO 1.1 (Function Specific) MANFID:0x%X, MANFINFO:0x%X \n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode));
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO 1.1, No CISTPL_MANFID Tuple in FUNC CIS \n"));
++ status = SDIO_STATUS_SUCCESS;
++ }
++ }
++ } while (FALSE);
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDEnableFunction - enable function
++ Input: pDevice - the device/function
++ pEnData - enable data;
++ Output:
++ Return: status
++ Notes: Note, this performs synchronous calls
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDEnableFunction(PSDDEVICE pDevice, PSDCONFIG_FUNC_ENABLE_DISABLE_DATA pEnData)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 registerValue;
++ UINT8 mask;
++ FUNC_ENABLE_TIMEOUT retry;
++
++ /* take the configure op lock to make this atomic */
++ status = SemaphorePendInterruptable(&pDevice->pHcd->ConfigureOpsSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ do {
++ if (!(pDevice->pHcd->CardProperties.Flags & CARD_SDIO)){
++ /* nothing to do if it's not an SDIO card */
++ break;
++ }
++
++ if (!((SDDEVICE_GET_SDIO_FUNCNO(pDevice) >= SDIO_FIRST_FUNCTION_NUMBER) &&
++ (SDDEVICE_GET_SDIO_FUNCNO(pDevice) <= SDIO_LAST_FUNCTION_NUMBER))){
++ DBG_ASSERT(FALSE);
++ break;
++ }
++ /* make sure there is a timeout value */
++ if (0 == pEnData->TimeOut) {
++ break;
++ }
++
++ mask = 1 << SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ /* read the enable register */
++ status = Cmd52ReadByteCommon(pDevice, SDIO_ENABLE_REG, ®isterValue);
++ if (!SDIO_SUCCESS(status)){
++ break;
++ }
++ if (pEnData->EnableFlags & SDCONFIG_ENABLE_FUNC) {
++ /* set the enable register bit */
++ registerValue |= mask;
++ } else {
++ /* clear the bit */
++ registerValue &= ~mask;
++ }
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver %s Function, Mask:0x%X Enable Reg Value:0x%2.2X\n",
++ (pEnData->EnableFlags & SDCONFIG_ENABLE_FUNC) ? "Enabling":"Disabling",
++ mask,
++ registerValue));
++
++ /* write it back out */
++ status = Cmd52WriteByteCommon(pDevice, SDIO_ENABLE_REG, ®isterValue);
++ if (!SDIO_SUCCESS(status)){
++ break;
++ }
++ /* now poll the ready bit until it sets or clears */
++ retry = pEnData->TimeOut;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Function Enable/Disable Polling: %d retries \n",
++ retry));
++ while (retry) {
++ status = Cmd52ReadByteCommon(pDevice, SDIO_READY_REG, ®isterValue);
++ if (!SDIO_SUCCESS(status)){
++ break;
++ }
++ if (pEnData->EnableFlags & SDCONFIG_ENABLE_FUNC) {
++ /* if the bit is set, the device is ready */
++ if (registerValue & mask) {
++ /* device ready */
++ break;
++ }
++ } else {
++ if (!(registerValue & mask)) {
++ /* device is no longer ready */
++ break;
++ }
++ }
++ /* sleep before trying again */
++ status = OSSleep(1);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("OSSleep Failed! \n"));
++ break;
++ }
++ retry--;
++ }
++
++ if (0 == retry) {
++ status = SDIO_STATUS_FUNC_ENABLE_TIMEOUT;
++ break;
++ }
++
++ } while (FALSE);
++
++ SemaphorePost(&pDevice->pHcd->ConfigureOpsSem);
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDAllocFreeSlotCurrent - allocate or free slot current
++ Input: pDevice - the device/function
++ Allocate - Allocate current, else free
++ pData - slotcurrent data (non-NULL if Allocate is TRUE)
++ Output:
++ Return: status
++ Notes: if the function returns SDIO_STATUS_NO_RESOURCES, the pData->SlotCurrent field is
++ updated with the available current
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDAllocFreeSlotCurrent(PSDDEVICE pDevice, BOOL Allocate, PSDCONFIG_FUNC_SLOT_CURRENT_DATA pData)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: SDAllocFreeSlotCurrent\n"));
++
++ /* take the configure op lock to make this atomic */
++ status = SemaphorePendInterruptable(&pDevice->pHcd->ConfigureOpsSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ do {
++ /* check the current budget and allocate */
++ if (Allocate) {
++ if (0 == pData->SlotCurrent) {
++ /* caller must specify current requirement for the power mode */
++ break;
++ }
++ if (pDevice->SlotCurrentAlloc != 0) {
++ /* slot current has already been allocated, caller needs to free
++ * first */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Slot Current Already allocated! \n"));
++ break;
++ }
++ if (((UINT32)pDevice->pHcd->SlotCurrentAllocated + (UINT32)pData->SlotCurrent) >
++ (UINT32)pDevice->pHcd->MaxSlotCurrent) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Slot Current Budget exceeded, Requesting: %d, Allocated already: %d, Max: %d \n",
++ pData->SlotCurrent, pDevice->pHcd->SlotCurrentAllocated,
++ pDevice->pHcd->MaxSlotCurrent));
++ status = SDIO_STATUS_NO_RESOURCES;
++ /* return remaining */
++ pData->SlotCurrent = pDevice->pHcd->MaxSlotCurrent -
++ pDevice->pHcd->SlotCurrentAllocated;
++ break;
++ }
++ /* bump up allocation */
++ pDevice->pHcd->SlotCurrentAllocated += pData->SlotCurrent;
++ /* save this off for the call to free slot current */
++ pDevice->SlotCurrentAlloc = pData->SlotCurrent;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Slot Current Requested: %d, New Total: %d, Max: %d \n",
++ pData->SlotCurrent, pDevice->pHcd->SlotCurrentAllocated,
++ pDevice->pHcd->MaxSlotCurrent));
++
++ } else {
++ if (0 == pDevice->SlotCurrentAlloc) {
++ /* no allocation */
++ break;
++ }
++ /* return the allocation back */
++ if (pDevice->SlotCurrentAlloc <= pDevice->pHcd->SlotCurrentAllocated) {
++ pDevice->pHcd->SlotCurrentAllocated -= pDevice->SlotCurrentAlloc;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Slot Current Freed: %d, New Total: %d, Max: %d \n",
++ pDevice->SlotCurrentAlloc, pDevice->pHcd->SlotCurrentAllocated,
++ pDevice->pHcd->MaxSlotCurrent));
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++
++ /* make sure this is zeroed */
++ pDevice->SlotCurrentAlloc = 0;
++ }
++
++ status = SDIO_STATUS_SUCCESS;
++
++ } while (FALSE);
++
++ SemaphorePost(&pDevice->pHcd->ConfigureOpsSem);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: SDAllocFreeSlotCurrent, %d\n", status));
++ return status;
++}
++
++static void RawHcdIrqControl(PSDHCD pHcd, BOOL Enable)
++{
++ SDIO_STATUS status;
++ SDCONFIG_SDIO_INT_CTRL_DATA irqData;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ ZERO_OBJECT(irqData);
++
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return;
++ }
++
++ do {
++ /* for raw devices, we simply enable/disable in the HCD only */
++ if (Enable) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver (RAW) Unmasking Int \n"));
++ irqData.IRQDetectMode = IRQ_DETECT_RAW;
++ irqData.SlotIRQEnable = TRUE;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver (RAW) Masking Int \n"));
++ irqData.SlotIRQEnable = FALSE;
++ }
++
++ status = _IssueConfig(pHcd,SDCONFIG_SDIO_INT_CTRL,
++ (PVOID)&irqData, sizeof(irqData));
++
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver failed to enable/disable IRQ in (RAW) hcd :%d\n",
++ status));
++ }
++
++ } while (FALSE);
++
++ status = _ReleaseHcdLock(pHcd);
++}
++
++static void RawHcdEnableIrqPseudoComplete(PSDREQUEST pReq)
++{
++ if (SDIO_SUCCESS(pReq->Status)) {
++ RawHcdIrqControl((PSDHCD)pReq->pCompleteContext, TRUE);
++ }
++ FreeRequest(pReq);
++}
++
++static void RawHcdDisableIrqPseudoComplete(PSDREQUEST pReq)
++{
++ RawHcdIrqControl((PSDHCD)pReq->pCompleteContext, FALSE);
++ FreeRequest(pReq);
++}
++
++static void HcdIrqControl(PSDHCD pHcd, BOOL Enable)
++{
++ SDIO_STATUS status;
++ SDCONFIG_SDIO_INT_CTRL_DATA irqData;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ ZERO_OBJECT(irqData);
++
++ status = _AcquireHcdLock(pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return;
++ }
++
++ do {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: HcdIrqControl (%s), IrqsEnabled:0x%X \n",
++ Enable ? "Enable":"Disable",pHcd->IrqsEnabled ));
++
++ if (Enable) {
++ irqData.SlotIRQEnable = TRUE;
++ } else {
++ irqData.SlotIRQEnable = FALSE;
++ }
++ /* setup HCD to enable/disable it's detection hardware */
++ if (irqData.SlotIRQEnable) {
++ /* set the IRQ detection mode */
++ switch (SDCONFIG_GET_BUSWIDTH(pHcd->CardProperties.BusMode)) {
++ case SDCONFIG_BUS_WIDTH_SPI:
++ irqData.IRQDetectMode = IRQ_DETECT_SPI;
++ break;
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ irqData.IRQDetectMode = IRQ_DETECT_1_BIT;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ irqData.IRQDetectMode = IRQ_DETECT_4_BIT;
++ /* check card and HCD for 4bit multi-block interrupt support */
++ if ((pHcd->CardProperties.SDIOCaps & SDIO_CAPS_INT_MULTI_BLK) &&
++ (pHcd->Attributes & SDHCD_ATTRIB_MULTI_BLK_IRQ)) {
++ /* note: during initialization of the card, the mult-blk IRQ support
++ * is enabled in card caps register */
++ irqData.IRQDetectMode |= IRQ_DETECT_MULTI_BLK;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver enabling IRQ in multi-block mode:\n"));
++ }
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver enabling IRQ in HCD Mode:0x%X\n",
++ irqData.IRQDetectMode));
++ }
++
++ status = _IssueConfig(pHcd,SDCONFIG_SDIO_INT_CTRL,
++ (PVOID)&irqData, sizeof(irqData));
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver failed to enable/disable IRQ in hcd %d\n",
++ status));
++ }
++
++ } while (FALSE);
++
++ status = _ReleaseHcdLock(pHcd);
++}
++
++static BOOL CheckWriteIntEnableSuccess(PSDREQUEST pReq)
++{
++ if (!SDIO_SUCCESS(pReq->Status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to get write INT Enable register Err:%d\n",
++ pReq->Status));
++ return FALSE;
++ }
++
++ if (SD_R5_GET_RESP_FLAGS(pReq->Response) & SD_R5_ERRORS) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: WriteIntEnableComplete CMD52 resp error: 0x%X \n",
++ SD_R5_GET_RESP_FLAGS(pReq->Response)));
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++static void HcdIrqEnableComplete(PSDREQUEST pReq)
++{
++ if (CheckWriteIntEnableSuccess(pReq)) {
++ /* configure HCD */
++ HcdIrqControl((PSDHCD)pReq->pCompleteContext, TRUE);
++ }
++ FreeRequest(pReq);
++}
++
++static void HcdIrqDisableComplete(PSDREQUEST pReq)
++{
++ CheckWriteIntEnableSuccess(pReq);
++ HcdIrqControl((PSDHCD)pReq->pCompleteContext, FALSE);
++ FreeRequest(pReq);
++}
++
++static void WriteIntEnableComplete(PSDREQUEST pReq)
++{
++ if (CheckWriteIntEnableSuccess(pReq)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: Wrote INT Enable value:0x%X \n",
++ (INT)pReq->pCompleteContext));
++ }
++ FreeRequest(pReq);
++}
++
++static void HcdAckComplete(PSDREQUEST pReq)
++{
++ SDIO_STATUS status;
++ DBG_PRINT(SDIODBG_FUNC_IRQ, ("SDIO Bus Driver: Hcd (0x%X) Irq Ack \n",
++ (INT)pReq->pCompleteContext));
++ /* re-arm the HCD */
++ status = _IssueConfig((PSDHCD)pReq->pCompleteContext,SDCONFIG_SDIO_REARM_INT,NULL,0);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: HCD Re-Arm failed : %d\n",
++ status));
++ }
++ FreeRequest(pReq);
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDFunctionAckInterrupt - handle device interrupt acknowledgement
++ Input: pDevice - the device
++ Output:
++ Return:
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDFunctionAckInterrupt(PSDDEVICE pDevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UCHAR mask;
++ PSDREQUEST pReq = NULL;
++ BOOL setHcd = FALSE;
++ SDIO_STATUS status2;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ status = _AcquireHcdLock(pDevice->pHcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ FreeRequest(pReq);
++ return status;
++ }
++
++ do {
++ if (!((SDDEVICE_GET_SDIO_FUNCNO(pDevice) >= SDIO_FIRST_FUNCTION_NUMBER) &&
++ (SDDEVICE_GET_SDIO_FUNCNO(pDevice) <= SDIO_LAST_FUNCTION_NUMBER))){
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ DBG_ASSERT(FALSE);
++ break;
++ }
++ mask = 1 << SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ if (pDevice->pHcd->PendingIrqAcks & mask) {
++ /* clear the ack bit in question */
++ pDevice->pHcd->PendingIrqAcks &= ~mask;
++ if (0 == pDevice->pHcd->PendingIrqAcks) {
++ pDevice->pHcd->IrqProcState = SDHCD_IDLE;
++ /* no pending acks, so re-arm if irqs are stilled enabled */
++ if (pDevice->pHcd->IrqsEnabled) {
++ setHcd = TRUE;
++ /* issue pseudo request to sync this with bus requests */
++ pReq->Status = SDIO_STATUS_SUCCESS;
++ pReq->pCompletion = HcdAckComplete;
++ pReq->pCompleteContext = pDevice->pHcd;
++ pReq->Flags = SD_PSEUDO_REQ_FLAGS;
++ }
++ }
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: AckInterrupt: no IRQ pending on Function :%d, \n",
++ SDDEVICE_GET_SDIO_FUNCNO(pDevice)));
++ }
++ } while (FALSE);
++
++ status2 = ReleaseHcdLock(pDevice);
++
++ if (pReq != NULL) {
++ if (SDIO_SUCCESS(status) && (setHcd)) {
++ /* issue request */
++ IssueRequestToHCD(pDevice->pHcd,pReq);
++ } else {
++ FreeRequest(pReq);
++ }
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDMaskUnmaskFunctionIRQ - mask/unmask function IRQ
++ Input: pDevice - the device/function
++ MaskInt - mask interrupt
++ Output:
++ Return: status
++ Notes: Note, this function can be called from an ISR or completion context
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDMaskUnmaskFunctionIRQ(PSDDEVICE pDevice, BOOL MaskInt)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 mask;
++ UINT8 controlVal;
++ BOOL setHcd;
++ PSDREQUEST pReq = NULL;
++ SDIO_STATUS status2;
++
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ setHcd = FALSE;
++
++ pReq = AllocateRequest();
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ status = _AcquireHcdLock(pDevice->pHcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ FreeRequest(pReq);
++ return status;
++ }
++
++ do {
++
++ if (pDevice->pHcd->CardProperties.Flags & CARD_RAW) {
++ if (!MaskInt) {
++ if (!pDevice->pHcd->IrqsEnabled) {
++ pReq->pCompletion = RawHcdEnableIrqPseudoComplete;
++ setHcd = TRUE;
++ pDevice->pHcd->IrqsEnabled = 1 << 1;
++ }
++ } else {
++ if (pDevice->pHcd->IrqsEnabled) {
++ pReq->pCompletion = RawHcdDisableIrqPseudoComplete;
++ setHcd = TRUE;
++ pDevice->pHcd->IrqsEnabled = 0;
++ }
++ }
++
++ if (setHcd) {
++ /* hcd IRQ control requests must be synched with outstanding
++ * bus requests so we issue a pseudo bus request */
++ pReq->pCompleteContext = pDevice->pHcd;
++ pReq->Flags = SD_PSEUDO_REQ_FLAGS;
++ pReq->Status = SDIO_STATUS_SUCCESS;
++ } else {
++ /* no request to submit, just free it */
++ FreeRequest(pReq);
++ pReq = NULL;
++ }
++ /* we're done, submit the bus request if any */
++ break;
++ }
++
++ if (!(pDevice->pHcd->CardProperties.Flags & CARD_SDIO)){
++ /* nothing to do if it's not an SDIO card */
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++
++ if (!((SDDEVICE_GET_SDIO_FUNCNO(pDevice) >= SDIO_FIRST_FUNCTION_NUMBER) &&
++ (SDDEVICE_GET_SDIO_FUNCNO(pDevice) <= SDIO_LAST_FUNCTION_NUMBER))){
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ mask = 1 << SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ if (!MaskInt) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver Unmasking Int, Mask:0x%X\n", mask));
++ /* check interrupts that were enabled on entry */
++ if (0 == pDevice->pHcd->IrqsEnabled) {
++ /* need to turn on interrupts in HCD */
++ setHcd = TRUE;
++ /* use this completion routine */
++ pReq->pCompletion = HcdIrqEnableComplete;
++ }
++ /* set the enable bit, in the shadow register */
++ pDevice->pHcd->IrqsEnabled |= mask;
++ /* make sure control value includes the master enable */
++ controlVal = pDevice->pHcd->IrqsEnabled | SDIO_INT_MASTER_ENABLE;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver Masking Int, Mask:0x%X\n", mask));
++ /* clear the bit */
++ pDevice->pHcd->IrqsEnabled &= ~mask;
++ /* check and see if this clears all the bits */
++ if (0 == pDevice->pHcd->IrqsEnabled){
++ /* if none of the functions are enabled, clear this register */
++ controlVal = 0;
++ /* disable in host */
++ setHcd = TRUE;
++ /* use this completion routine */
++ pReq->pCompletion = HcdIrqDisableComplete;
++ } else {
++ /* set control value making sure master enable is left on */
++ controlVal = pDevice->pHcd->IrqsEnabled | SDIO_INT_MASTER_ENABLE;
++ }
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver INT_ENABLE_REG value:0x%X\n", controlVal));
++ /* setup bus request to update the mask register */
++ SDIO_SET_CMD52_WRITE_ARG(pReq->Argument,0,SDIO_INT_ENABLE_REG,controlVal);
++ pReq->Command = CMD52;
++ pReq->Flags = SDREQ_FLAGS_TRANS_ASYNC | SDREQ_FLAGS_RESP_SDIO_R5;
++
++ if (setHcd) {
++ /* make this a barrier request and set context*/
++ pReq->Flags |= SDREQ_FLAGS_BARRIER;
++ pReq->pCompleteContext = pDevice->pHcd;
++ } else {
++ /* does not require an update to the HCD */
++ pReq->pCompleteContext = (PVOID)(UINT32)controlVal;
++ pReq->pCompletion = WriteIntEnableComplete;
++ }
++
++ } while (FALSE);
++
++ status2 = _ReleaseHcdLock(pDevice->pHcd);
++
++ if (pReq != NULL) {
++ if (SDIO_SUCCESS(status)) {
++ /* issue request */
++ IssueRequestToHCD(pDevice->pHcd,pReq);
++ } else {
++ FreeRequest(pReq);
++ }
++ }
++
++ return status;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SDSPIModeEnableDisableCRC - Enable/Disable SPI Mode CRC checking
++ Input: pDevice - the device/function
++ Enable - Enable CRC
++ Output:
++ Return: status
++ Notes: Note, this function can be called from an ISR or completion context
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDSPIModeEnableDisableCRC(PSDDEVICE pDevice,BOOL Enable)
++{
++ SDCONFIG_BUS_MODE_DATA busMode;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 cmdARG = 0;
++
++ if (!SDDEVICE_IS_BUSMODE_SPI(pDevice)) {
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++ //??we should make these atomic using a barrier
++
++ /* get the current mode and clock */
++ busMode.BusModeFlags = pDevice->pHcd->CardProperties.BusMode;
++ busMode.ClockRate = pDevice->pHcd->CardProperties.OperBusClock;
++
++ if (Enable) {
++ /* clear the no-CRC flag */
++ busMode.BusModeFlags &= ~SDCONFIG_BUS_MODE_SPI_NO_CRC;
++ cmdARG = SD_CMD59_CRC_ON;
++ } else {
++ busMode.BusModeFlags |= SDCONFIG_BUS_MODE_SPI_NO_CRC;
++ cmdARG = SD_CMD59_CRC_OFF;
++ }
++
++ do {
++ /* issue CMD59 to turn on/off CRC */
++ status = _IssueSimpleBusRequest(pDevice->pHcd,
++ CMD59,
++ cmdARG,
++ SDREQ_FLAGS_RESP_R1,
++ NULL);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed issue CMD59 (arg=0x%X) Err:%d \n",
++ cmdARG, status));
++ break;
++ }
++ if (Enable) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: CRC Enabled in SPI mode \n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: CRC Disabled in SPI mode \n"));
++ }
++ status = SetOperationalBusMode(pDevice,&busMode);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Failed to set SPI NO CRC mode in hcd : Err:%d \n",
++ status));
++ break;
++ }
++ } while (FALSE);
++
++ return status;
++}
++
++
++static UINT32 ConvertSPIStatusToSDCardStatus(UINT8 SpiR1, UINT8 SpiR2)
++{
++ UINT32 cardStatus = 0;
++
++ if (SpiR1 != 0) {
++ /* convert the error */
++ if (SpiR1 & SPI_CS_ERASE_RESET) {
++ cardStatus |= SD_CS_ERASE_RESET;
++ }
++ if (SpiR1 & SPI_CS_ILLEGAL_CMD) {
++ cardStatus |= SD_CS_ILLEGAL_CMD_ERR;
++ }
++ if (SpiR1 & SPI_CS_CMD_CRC_ERR) {
++ cardStatus |= SD_CS_PREV_CMD_CRC_ERR;
++ }
++ if (SpiR1 & SPI_CS_ERASE_SEQ_ERR) {
++ cardStatus |= SD_CS_ERASE_SEQ_ERR;
++ }
++ if (SpiR1 & SPI_CS_ADDRESS_ERR) {
++ cardStatus |= SD_CS_ADDRESS_ERR;
++ }
++ if (SpiR1 & SPI_CS_PARAM_ERR) {
++ cardStatus |= SD_CS_CMD_OUT_OF_RANGE;
++ }
++ }
++
++ if (SpiR2 != 0) {
++ /* convert the error */
++ if (SpiR2 & SPI_CS_CARD_IS_LOCKED) {
++ cardStatus |= SD_CS_CARD_LOCKED;
++ }
++ if (SpiR2 & SPI_CS_LOCK_UNLOCK_FAILED) {
++ /* this bit is shared, just set both */
++ cardStatus |= (SD_CS_LK_UNLK_FAILED | SD_CS_WP_ERASE_SKIP);
++ }
++ if (SpiR2 & SPI_CS_ERROR) {
++ cardStatus |= SD_CS_GENERAL_ERR;
++ }
++ if (SpiR2 & SPI_CS_INTERNAL_ERROR) {
++ cardStatus |= SD_CS_CARD_INTERNAL_ERR;
++ }
++ if (SpiR2 & SPI_CS_ECC_FAILED) {
++ cardStatus |= SD_CS_ECC_FAILED;
++ }
++ if (SpiR2 & SPI_CS_WP_VIOLATION) {
++ cardStatus |= SD_CS_WP_ERR;
++ }
++ if (SpiR2 & SPI_CS_ERASE_PARAM_ERR) {
++ cardStatus |= SD_CS_ERASE_PARAM_ERR;
++ }
++ if (SpiR2 & SPI_CS_OUT_OF_RANGE) {
++ cardStatus |= SD_CS_CMD_OUT_OF_RANGE;
++ }
++ }
++
++ return cardStatus;
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ConvertSPI_Response - filter the SPI response and convert it to an SD Response
++ Input: pReq - request
++ Output: pReq - modified response, if pRespBuffer is not NULL
++ pRespBuffer - converted response (optional)
++ Return:
++ Notes: This function converts a SPI response into an SD response. A caller
++ can supply a buffer instead.
++ For SPI bus operation the HCD must send the SPI response as
++ a stream of bytes, the highest byte contains the first received byte from the
++ card. This function only filters simple responses (R1 primarily).
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ConvertSPI_Response(PSDREQUEST pReq, UINT8 *pRespBuffer)
++{
++
++ UINT32 cardStatus;
++
++ if (pReq->Flags & SDREQ_FLAGS_RESP_SPI_CONVERTED) {
++ /* already converted */
++ return;
++ }
++ if (NULL == pRespBuffer) {
++ pRespBuffer = pReq->Response;
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_R1B:
++ cardStatus = ConvertSPIStatusToSDCardStatus(GET_SPI_R1_RESP_TOKEN(pReq->Response),
++ 0);
++ if (CMD55 == pReq->Command) {
++ /* we emulate this since SPI does not have such a bit */
++ cardStatus |= SD_CS_APP_CMD;
++ }
++ /* stuff the SD card status */
++ SD_R1_SET_CMD_STATUS(pRespBuffer,cardStatus);
++ /* stuff the command */
++ SD_R1_SET_CMD(pRespBuffer,pReq->Command);
++ pReq->Flags |= SDREQ_FLAGS_RESP_SPI_CONVERTED;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ {
++ UINT8 respFlags;
++ UINT8 readData;
++
++ readData = GET_SPI_SDIO_R5_RESPONSE_RDATA(pReq->Response);
++ respFlags = GET_SPI_SDIO_R5_RESP_TOKEN(pReq->Response);
++
++ pRespBuffer[SD_R5_RESP_FLAGS_OFFSET] = 0;
++ if (respFlags != 0) {
++ if (respFlags & SPI_R5_ILLEGAL_CMD) {
++ pRespBuffer[SD_R5_RESP_FLAGS_OFFSET] |= SD_R5_ILLEGAL_CMD;
++ }
++ if (respFlags & SPI_R5_CMD_CRC) {
++ pRespBuffer[SD_R5_RESP_FLAGS_OFFSET] |= SD_R5_RESP_CMD_ERR;
++ }
++ if (respFlags & SPI_R5_FUNC_ERR) {
++ pRespBuffer[SD_R5_RESP_FLAGS_OFFSET] |= SD_R5_INVALID_FUNC;
++ }
++ if (respFlags & SPI_R5_PARAM_ERR) {
++ pRespBuffer[SD_R5_RESP_FLAGS_OFFSET] |= SD_R5_ARG_RANGE_ERR;
++ }
++ }
++ /* stuff read data */
++ pRespBuffer[SD_SDIO_R5_READ_DATA_OFFSET] = readData;
++ /* stuff the command */
++ SD_R5_SET_CMD(pRespBuffer,pReq->Command);
++ }
++ pReq->Flags |= SDREQ_FLAGS_RESP_SPI_CONVERTED;
++ break;
++
++
++#ifndef CT_CONFIG_NO_SDMMC
++ case SDREQ_FLAGS_RESP_R2:
++ /* for CMD13 and ACMD13 , SPI uses it's own R2 response format (2 bytes) */
++ /* the issue of CMD13 needs to change the response flag to R2 */
++ if (CMD13 == pReq->Command) {
++ cardStatus = ConvertSPIStatusToSDCardStatus(
++ GET_SPI_R2_RESP_TOKEN(pReq->Response),
++ GET_SPI_R2_STATUS_TOKEN(pReq->Response));
++ /* stuff the SD card status */
++ SD_R1_SET_CMD_STATUS(pRespBuffer,cardStatus);
++ /* stuff the command */
++ SD_R1_SET_CMD(pRespBuffer,pReq->Command);
++ pReq->Flags |= SDREQ_FLAGS_RESP_SPI_CONVERTED;
++ break;
++ }
++ /* no other commands should be using R2 when using SPI, if they are
++ * they should be bypassing the filter */
++ DBG_ASSERT(FALSE);
++ break;
++
++#endif
++ default:
++ /* for all others:
++ *
++ * SDREQ_FLAGS_RESP_R6 - SPI mode does not use RCA
++ * SDREQ_FLAGS_RESP_R3 - bus driver handles this internally
++ * SDREQ_FLAGS_RESP_SDIO_R4 - bus driver handles this internally
++ *
++ */
++ DBG_PRINT(SDDBG_ERROR, ("ConvertSPI_Response - invalid response type:0x%2.2X",
++ GET_SDREQ_RESP_TYPE(pReq->Flags)));
++ DBG_ASSERT(FALSE);
++ break;
++ }
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Check an SD/MMC/SDIO response.
++
++ @function name: SDIO_CheckResponse
++ @prototype: SDIO_STATUS SDIO_CheckResponse(PSDHCD pHcd, PSDREQUEST pReq, SDHCD_RESPONSE_CHECK_MODE CheckMode)
++ @category: HD_Reference
++
++ @input: pHcd - the host controller definition structure.
++ @input: pReq - request containing the response
++ @input: CheckMode - mode
++
++ @return: SDIO_STATUS
++
++ @notes: Host controller drivers must call into this function to validate various command
++ responses before continuing with data transfers or for decoding received SPI tokens.
++ The CheckMode option determines the type of validation to perform.
++ if (CheckMode == SDHCD_CHECK_DATA_TRANS_OK) :
++ The host controller must check the card response to determine whether it
++ is safe to perform a data transfer. This API only checks commands that
++ involve data transfers and checks various status fields in the command response.
++ If the card cannot accept data, this function will return a non-successful status that
++ should be treated as a request failure. The host driver should complete the request with the
++ returned status. Host controller should only call this function in preparation for a
++ data transfer.
++ if (CheckMode == SDHCD_CHECK_SPI_TOKEN) :
++ This API checks the SPI token and returns a timeout status if the illegal command bit is
++ set. This simulates the behavior of SD 1/4 bit operation where illegal commands result in
++ a command timeout. A driver that supports SPI mode should pass every response to this
++ function to determine the appropriate error status to complete the request with. If the
++ API returns success, the response indicates that the card accepted the command.
++
++ @example: Checking the response before starting the data transfer :
++ if (SDIO_SUCCESS(status) && (pReq->Flags & SDREQ_FLAGS_DATA_TRANS)) {
++ // check the response to see if we should continue with data
++ status = SDIO_CheckResponse(pHcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++ if (SDIO_SUCCESS(status)) {
++ .... start data transfer phase
++ } else {
++ ... card response indicates that the card cannot handle data
++ // set completion status
++ pRequest->Status = status;
++ }
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ _SDIO_CheckResponse - check response on behalf of the host controller
++ Input: pHcd - host controller
++ pReq - request containing the response
++ CheckMode - mode
++ Output:
++ Return: status
++ Notes:
++
++ CheckMode == SDHCD_CHECK_DATA_TRANS_OK :
++ The host controller requests a check on the response to determine whether it
++ is okay to perform a data transfer. This function only filters on commands that
++ involve data. Host controller should only call this function in preparation for a
++ data transfer.
++
++ CheckMode == SDHCD_CHECK_SPI_TOKEN :
++ The bus driver checks the SPI token and returns a timeout status if the illegal command bit is
++ set. This simulates the behavior of SD native operation.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_CheckResponse(PSDHCD pHcd, PSDREQUEST pReq, SDHCD_RESPONSE_CHECK_MODE CheckMode)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ if (CheckMode == SDHCD_CHECK_DATA_TRANS_OK) {
++ UINT32 cardStatus;
++ UINT8 *pResponse;
++ UINT8 convertedResponse[MAX_CARD_RESPONSE_BYTES];
++
++ if (!(pReq->Flags & SDREQ_FLAGS_DATA_TRANS) ||
++ (pReq->Flags & SDREQ_FLAGS_DATA_SKIP_RESP_CHK) ||
++ (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP)) {
++ return SDIO_STATUS_SUCCESS;
++ }
++ pResponse = pReq->Response;
++ /* check SPI mode */
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ if (!(pReq->Flags & SDREQ_FLAGS_RESP_SKIP_SPI_FILT)) {
++ /* apply conversion */
++ ConvertSPI_Response(pReq, NULL);
++ } else {
++ /* temporarily convert the response, without altering the original */
++ ConvertSPI_Response(pReq, convertedResponse);
++ /* point to the converted one */
++ pResponse = convertedResponse;
++ }
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_R1B:
++ cardStatus = SD_R1_GET_CARD_STATUS(pResponse);
++ if (!(cardStatus &
++ (SD_CS_ILLEGAL_CMD_ERR | SD_CS_CARD_INTERNAL_ERR | SD_CS_GENERAL_ERR))) {
++ /* okay for data */
++ break;
++ }
++ /* figure out what it was */
++ if (cardStatus & SD_CS_ILLEGAL_CMD_ERR) {
++ status = SDIO_STATUS_DATA_STATE_INVALID;
++ } else {
++ status = SDIO_STATUS_DATA_ERROR_UNKNOWN;
++ }
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Check Response Error. R1 CardStatus:0x%X \n",
++ cardStatus));
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ cardStatus = SD_R5_GET_RESP_FLAGS(pResponse);
++ if (!(cardStatus & SD_R5_CURRENT_CMD_ERRORS)){
++ /* all okay */
++ break;
++ }
++
++ status = ConvertCMD52ResponseToSDIOStatus((UINT8)cardStatus);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: Check Response Error. R5 CardStatus:0x%X \n",
++ cardStatus));
++ break;
++ default:
++ break;
++ }
++
++ return status;
++ }
++
++ {
++ UINT8 spiToken;
++
++ /* handle SPI token validation */
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_RESP_R2:
++ spiToken = GET_SPI_R2_RESP_TOKEN(pReq->Response);
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ spiToken = GET_SPI_SDIO_R5_RESP_TOKEN(pReq->Response);
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ spiToken = GET_SPI_R3_RESP_TOKEN(pReq->Response);
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ spiToken = GET_SPI_SDIO_R4_RESP_TOKEN(pReq->Response);
++ break;
++ default:
++ /* all other tokesn are SPI R1 type */
++ spiToken = GET_SPI_R1_RESP_TOKEN(pReq->Response);
++ break;
++ }
++
++ if ((GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_SDIO_R5) ||
++ (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_SDIO_R4)) {
++ /* handle SDIO status tokens */
++ if ((spiToken & SPI_R5_ILLEGAL_CMD) ||
++ (spiToken & SPI_R5_CMD_CRC)) {
++ status = SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++ } else {
++ /* handle all other status tokens */
++ if ((spiToken & SPI_CS_ILLEGAL_CMD) ||
++ (spiToken & SPI_CS_CMD_CRC_ERR)) {
++ status = SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++ }
++ }
++
++ return status;
++}
++
+Index: linux-2.6.22/drivers/sdio/busdriver/sdio_bus_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/sdio_bus_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,807 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bus_os.c
++
++ at abstract: Linux implementation module
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++#define DBG_DECLARE 3;
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include <linux/pnp.h>
++#include <linux/kthread.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "_busdriver.h"
++
++#define DESCRIPTION "SDIO Bus Driver"
++#define AUTHOR "Atheros Communications, Inc."
++
++/* configuration and default parameters */
++static int RequestRetries = SDMMC_DEFAULT_CMD_RETRIES;
++module_param(RequestRetries, int, 0644);
++MODULE_PARM_DESC(RequestRetries, "number of command retries");
++static int CardReadyPollingRetry = SDMMC_DEFAULT_CARD_READY_RETRIES;
++module_param(CardReadyPollingRetry, int, 0644);
++MODULE_PARM_DESC(CardReadyPollingRetry, "number of card ready retries");
++static int PowerSettleDelay = SDMMC_POWER_SETTLE_DELAY;
++module_param(PowerSettleDelay, int, 0644);
++MODULE_PARM_DESC(PowerSettleDelay, "delay in ms for power to settle after power changes");
++static int DefaultOperClock = 52000000;
++module_param(DefaultOperClock, int, 0644);
++MODULE_PARM_DESC(DefaultOperClock, "maximum operational clock limit");
++static int DefaultBusMode = SDCONFIG_BUS_WIDTH_4_BIT;
++module_param(DefaultBusMode, int, 0644);
++MODULE_PARM_DESC(DefaultBusMode, "default bus mode: see SDCONFIG_BUS_WIDTH_xxx");
++static int RequestListSize = SDBUS_DEFAULT_REQ_LIST_SIZE;
++module_param(RequestListSize, int, 0644);
++MODULE_PARM_DESC(RequestListSize, "");
++static int SignalSemListSize = SDBUS_DEFAULT_REQ_SIG_SIZE;
++module_param(SignalSemListSize, int, 0644);
++MODULE_PARM_DESC(SignalSemListSize, "");
++static int CDPollingInterval = SDBUS_DEFAULT_CD_POLLING_INTERVAL;
++module_param(CDPollingInterval, int, 0644);
++MODULE_PARM_DESC(CDPollingInterval, "");
++static int DefaultOperBlockLen = SDMMC_DEFAULT_BYTES_PER_BLOCK;
++module_param(DefaultOperBlockLen, int, 0644);
++MODULE_PARM_DESC(DefaultOperBlockLen, "operational block length");
++static int DefaultOperBlockCount = SDMMC_DEFAULT_BLOCKS_PER_TRANS;
++module_param(DefaultOperBlockCount, int, 0644);
++MODULE_PARM_DESC(DefaultOperBlockCount, "operational block count");
++static int ConfigFlags = BD_DEFAULT_CONFIG_FLAGS;
++module_param(ConfigFlags, int, 0644);
++MODULE_PARM_DESC(ConfigFlags, "config flags");
++
++static int HcdRCount = MAX_HCD_REQ_RECURSION;
++module_param(HcdRCount, int, 0644);
++MODULE_PARM_DESC(HcdRCount, "HCD request recursion count");
++
++static void CardDetect_WorkItem(struct work_struct * work);
++static void CardDetect_TimerFunc(unsigned long Context);
++static DECLARE_WORK(CardDetectPollWork, CardDetect_WorkItem);
++static int RegisterDriver(PSDFUNCTION pFunction);
++static int UnregisterDriver(PSDFUNCTION pFunction);
++
++static struct timer_list CardDetectTimer;
++
++#define SDDEVICE_FROM_OSDEVICE(pOSDevice) container_of(pOSDevice, SDDEVICE, Device)
++#define SDFUNCTION_FROM_OSDRIVER(pOSDriver) container_of(pOSDriver, SDFUNCTION, Driver)
++
++
++/*
++ * SDIO_RegisterHostController - register a host controller bus driver
++*/
++SDIO_STATUS SDIO_RegisterHostController(PSDHCD pHcd) {
++ /* we are the exported verison, call the internal verison */
++ return _SDIO_RegisterHostController(pHcd);
++}
++
++/*
++ * SDIO_UnregisterHostController - unregister a host controller bus driver
++*/
++SDIO_STATUS SDIO_UnregisterHostController(PSDHCD pHcd) {
++ /* we are the exported verison, call the internal verison */
++ return _SDIO_UnregisterHostController(pHcd);
++}
++
++/*
++ * SDIO_RegisterFunction - register a function driver
++*/
++SDIO_STATUS SDIO_RegisterFunction(PSDFUNCTION pFunction) {
++ int error;
++ SDIO_STATUS status;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - SDIO_RegisterFunction\n"));
++
++ /* since we do PnP registration first, we need to check the version */
++ if (!CHECK_FUNCTION_DRIVER_VERSION(pFunction)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: Function Major Version Mismatch (hcd = %d, bus driver = %d)\n",
++ GET_SDIO_STACK_VERSION_MAJOR(pFunction), CT_SDIO_STACK_VERSION_MAJOR(g_Version)));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ /* we are the exported verison, call the internal verison after registering with the bus
++ we handle probes internally to the bus driver */
++ if ((error = RegisterDriver(pFunction)) < 0) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BusDriver - SDIO_RegisterFunction, failed to register with system bus driver: %d\n",
++ error));
++ status = OSErrorToSDIOError(error);
++ } else {
++ status = _SDIO_RegisterFunction(pFunction);
++ if (!SDIO_SUCCESS(status)) {
++ UnregisterDriver(pFunction);
++ }
++ }
++
++ return status;
++}
++
++/*
++ * SDIO_UnregisterFunction - unregister a function driver
++*/
++SDIO_STATUS SDIO_UnregisterFunction(PSDFUNCTION pFunction) {
++ SDIO_STATUS status;
++ /* we are the exported verison, call the internal verison */
++ status = _SDIO_UnregisterFunction(pFunction);
++ UnregisterDriver(pFunction);
++ return status;
++}
++
++/*
++ * SDIO_HandleHcdEvent - tell core an event occurred
++*/
++SDIO_STATUS SDIO_HandleHcdEvent(PSDHCD pHcd, HCD_EVENT Event) {
++ /* we are the exported verison, call the internal verison */
++ DBG_PRINT(SDIODBG_HCD_EVENTS, ("SDIO Bus Driver: SDIO_HandleHcdEvent, event type 0x%X, HCD:0x%X\n",
++ Event, (UINT)pHcd));
++ return _SDIO_HandleHcdEvent(pHcd, Event);
++}
++
++/* get default settings */
++SDIO_STATUS _SDIO_BusGetDefaultSettings(PBDCONTEXT pBdc)
++{
++ /* these defaults are module params */
++ pBdc->RequestRetries = RequestRetries;
++ pBdc->CardReadyPollingRetry = CardReadyPollingRetry;
++ pBdc->PowerSettleDelay = PowerSettleDelay;
++ pBdc->DefaultOperClock = DefaultOperClock;
++ pBdc->DefaultBusMode = DefaultBusMode;
++ pBdc->RequestListSize = RequestListSize;
++ pBdc->SignalSemListSize = SignalSemListSize;
++ pBdc->CDPollingInterval = CDPollingInterval;
++ pBdc->DefaultOperBlockLen = DefaultOperBlockLen;
++ pBdc->DefaultOperBlockCount = DefaultOperBlockCount;
++ pBdc->ConfigFlags = ConfigFlags;
++ pBdc->MaxHcdRecursion = HcdRCount;
++ return SDIO_STATUS_SUCCESS;
++}
++
++static void CardDetect_TimerFunc(unsigned long Context)
++{
++ DBG_PRINT(SDIODBG_CD_TIMER, ("+ SDIO BusDriver Card Detect Timer\n"));
++
++ /* timers run in an ISR context and cannot block or sleep, so we need
++ * to queue a work item to call the bus driver timer notification */
++
++ if (schedule_work(&CardDetectPollWork) <= 0) {
++ DBG_PRINT(SDDBG_ERROR, ("Failed to queue Card Detect timer!\n"));
++ }
++
++ DBG_PRINT(SDIODBG_CD_TIMER, ("- SDIO BusDriver Card Detect Timer\n"));
++}
++
++/*
++ * Initialize any timers we are using
++*/
++SDIO_STATUS InitializeTimers(void)
++{
++ init_timer(&CardDetectTimer);
++ CardDetectTimer.function = CardDetect_TimerFunc;
++ CardDetectTimer.data = 0;
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * cleanup timers
++*/
++SDIO_STATUS CleanupTimers(void)
++{
++ del_timer(&CardDetectTimer);
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++/*
++ * Queue a timer, Timeout is in milliseconds
++*/
++SDIO_STATUS QueueTimer(INT TimerID, UINT32 TimeOut)
++{
++ UINT32 delta;
++
++ /* convert timeout to ticks */
++ delta = (TimeOut * HZ)/1000;
++ if (delta == 0) {
++ delta = 1;
++ }
++ DBG_PRINT(SDIODBG_CD_TIMER, ("SDIO BusDriver - SDIO_QueueTimer System Ticks Per Sec:%d \n",HZ));
++ DBG_PRINT(SDIODBG_CD_TIMER, ("SDIO BusDriver - SDIO_QueueTimer TimerID: %d TimeOut:%d MS, requires %d Ticks\n",
++ TimerID,TimeOut,delta));
++ switch (TimerID) {
++ case SDIOBUS_CD_TIMER_ID:
++ CardDetectTimer.expires = jiffies + delta;
++ add_timer(&CardDetectTimer);
++ break;
++ default:
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/* check a response on behalf of the host controller, to allow it to proceed with a
++ * data transfer */
++SDIO_STATUS SDIO_CheckResponse(PSDHCD pHcd, PSDREQUEST pReq, SDHCD_RESPONSE_CHECK_MODE CheckMode)
++{
++ return _SDIO_CheckResponse(pHcd,pReq,CheckMode);
++}
++
++/*
++ * CardDetect_WorkItem - the work item for handling card detect polling interrupt
++*/
++static void CardDetect_WorkItem(struct work_struct * work)
++{
++ /* call bus driver function */
++ SDIO_NotifyTimerTriggered(SDIOBUS_CD_TIMER_ID);
++}
++
++/*
++ * OS_IncHcdReference - increment host controller driver reference count
++*/
++SDIO_STATUS Do_OS_IncHcdReference(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ do {
++ if (NULL == pHcd->pModule) {
++ /* hcds that are 2.3 or higher should set this */
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: HCD:%s should set module ptr!\n",
++ (pHcd->pName != NULL) ? pHcd->pName : "Unknown"));
++ break;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ if (!try_module_get(pHcd->pModule)) {
++ status = SDIO_STATUS_ERROR;
++ }
++#else
++ if (!try_inc_mod_count(pHcd->pModule)) {
++ status = SDIO_STATUS_ERROR;
++ }
++#endif
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: HCD:%s failed to get module\n",
++ (pHcd->pName != NULL) ? pHcd->pName : "Unknown"));
++ }
++
++ return status;
++}
++
++/*
++ * OS_DecHcdReference - decrement host controller driver reference count
++*/
++SDIO_STATUS Do_OS_DecHcdReference(PSDHCD pHcd)
++{
++ if (pHcd->pModule != NULL) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ module_put(pHcd->pModule);
++#else
++ /* 2.4 or lower */
++ __MOD_DEC_USE_COUNT(pHcd->pModule);
++#endif
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++/****************************************************************************************/
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/pnp.h>
++
++#if !defined(CONFIG_PNP)
++#error "CONFIG_PNP not defined"
++#endif
++
++static ULONG InUseDevices = 0;
++static spinlock_t InUseDevicesLock = SPIN_LOCK_UNLOCKED;
++
++static const struct pnp_device_id pnp_idtable[] = {
++ {"SD_XXXX", 0}
++};
++static int sdio_get_resources(struct pnp_dev * pDev, struct pnp_resource_table * res)
++{
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - sdio_get_resources: %s\n",
++ pDev->dev.bus_id));
++ return 0;
++}
++static int sdio_set_resources(struct pnp_dev * pDev, struct pnp_resource_table * res)
++{
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - sdio_set_resources: %s\n",
++ pDev->dev.bus_id));
++ return 0;
++}
++
++static int sdio_disable_resources(struct pnp_dev *pDev)
++{
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - sdio_disable_resources: %s\n",
++ pDev->dev.bus_id));
++ if (pDev != NULL) {
++ pDev->active = 0;
++ }
++ return 0;
++}
++void release(struct device * pDev) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - release: %s\n",
++ pDev->bus_id));
++ return;
++}
++struct pnp_protocol sdio_protocol = {
++ .name = "SDIO",
++ .get = sdio_get_resources,
++ .set = sdio_set_resources,
++ .disable = sdio_disable_resources,
++ .dev.release = release,
++};
++
++/*
++ * driver_probe - probe for OS based driver
++*/
++static int driver_probe(struct pnp_dev* pOSDevice, const struct pnp_device_id *pId)
++{
++ PSDDEVICE pDevice = SDDEVICE_FROM_OSDEVICE(pOSDevice);
++ PSDFUNCTION pFunction = pDevice->Device.dev.driver_data;
++
++ if (pFunction == NULL) {
++ return -1;
++ }
++
++ if (strcmp(pFunction->pName, pOSDevice->dev.driver->name) == 0) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, match: %s/%s driver: %s\n",
++ pOSDevice->dev.bus_id, pFunction->pName, pOSDevice->dev.driver->name));
++ return 1;
++ } else {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, no match: %s/%s driver: %s\n",
++ pOSDevice->dev.bus_id, pFunction->pName, pOSDevice->dev.driver->name));
++ return -1;
++ }
++/* if (pOSDevice->id != NULL) {
++ if (strcmp(pOSDevice->id->id, pId->id) == 0) {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, match: %s/%s\n",
++ pOSDevice->dev.bus_id, pId->id));
++ return 1;
++ }
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, did not match: %s/%s/%s\n",
++ pOSDevice->dev.bus_id, pId->id, pOSDevice->id->id));
++ } else {
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, did not match: %s/%s\n",
++ pOSDevice->dev.bus_id, pId->id));
++ }
++ return -1;
++*/
++//?? if (pDevice->Device.dev.driver_data != NULL) {
++//?? if (pDevice->Device.dev.driver_data == pFunction) {
++//?? if (pDevice->Device.data != NULL) {
++//?? if (pDevice->Device.data == pFunction) {
++//?? DBG_PRINT(SDDBG_TRACE,
++//?? ("SDIO BusDriver - driver_probe, match: %s\n",
++//?? pOSDevice->dev.bus_id));
++//?? return 1;
++//?? }
++//?? }
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - driver_probe, match: %s\n",
++ pOSDevice->dev.bus_id));
++ return 1;
++}
++
++static int RegisterDriver(PSDFUNCTION pFunction)
++{
++ memset(&pFunction->Driver, 0, sizeof(pFunction->Driver));
++ pFunction->Driver.name = pFunction->pName;
++ pFunction->Driver.probe = driver_probe;
++ pFunction->Driver.id_table = pnp_idtable;
++ pFunction->Driver.flags = PNP_DRIVER_RES_DO_NOT_CHANGE;
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - SDIO_RegisterFunction, registering driver: %s\n",
++ pFunction->Driver.name));
++ return pnp_register_driver(&pFunction->Driver);
++}
++
++static int UnregisterDriver(PSDFUNCTION pFunction)
++{
++ DBG_PRINT(SDDBG_TRACE,
++ ("+SDIO BusDriver - UnregisterDriver, driver: %s\n",
++ pFunction->Driver.name));
++ pnp_unregister_driver(&pFunction->Driver);
++ DBG_PRINT(SDDBG_TRACE,
++ ("-SDIO BusDriver - UnregisterDriver\n"));
++ return 0;
++}
++
++/*
++ * OS_InitializeDevice - initialize device that will be registered
++*/
++SDIO_STATUS OS_InitializeDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction)
++{
++ struct pnp_id *pFdname;
++ memset(&pDevice->Device, 0, sizeof(pDevice->Device));
++ pDevice->Device.dev.driver_data = (PVOID)pFunction;
++//?? pDevice->Device.data = (PVOID)pFunction;
++//?? pDevice->Device.dev.driver = &pFunction->Driver.driver;
++//?? pDevice->Device.driver = &pFunction->Driver;
++//?? pDevice->Device.dev.release = release;
++ /* get a unique device number, must be done with locks held */
++ spin_lock(&InUseDevicesLock);
++ pDevice->Device.number = FirstClearBit(&InUseDevices);
++ SetBit(&InUseDevices, pDevice->Device.number);
++ spin_unlock(&InUseDevicesLock);
++ pDevice->Device.capabilities = PNP_REMOVABLE | PNP_DISABLE;
++ pDevice->Device.protocol = &sdio_protocol;
++ pDevice->Device.active = 1;
++
++ pnp_init_resource_table(&pDevice->Device.res);
++
++ pFdname = KernelAlloc(sizeof(struct pnp_id));
++
++ if (NULL == pFdname) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ /* set the id as slot number/function number */
++ snprintf(pFdname->id, sizeof(pFdname->id), "SD_%02X%02X",
++ pDevice->pHcd->SlotNumber, (UINT)SDDEVICE_GET_SDIO_FUNCNO(pDevice));
++ pFdname->next = NULL;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - OS_InitializeDevice adding id: %s\n",
++ pFdname->id));
++ pnp_add_id(pFdname, &pDevice->Device);
++
++ /* deal with DMA settings */
++ if (pDevice->pHcd->pDmaDescription != NULL) {
++ pDevice->Device.dev.dma_mask = &pDevice->pHcd->pDmaDescription->Mask;
++ pDevice->Device.dev.coherent_dma_mask = pDevice->pHcd->pDmaDescription->Mask;
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * OS_AddDevice - must be pre-initialized with OS_InitializeDevice
++*/
++SDIO_STATUS OS_AddDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction)
++{
++ int error;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - OS_AddDevice adding function: %s\n",
++ pFunction->pName));
++ error = pnp_add_device(&pDevice->Device);
++ if (error < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BusDriver - OS_AddDevice failed pnp_add_device: %d\n",
++ error));
++ }
++ /* replace the buggy pnp's release */
++ pDevice->Device.dev.release = release;
++
++ return OSErrorToSDIOError(error);
++}
++
++/*
++ * OS_RemoveDevice - unregister device with driver and bus
++*/
++void OS_RemoveDevice(PSDDEVICE pDevice)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - OS_RemoveDevice \n"));
++// pnp_remove_device(&pDevice->Device);
++ spin_lock(&InUseDevicesLock);
++ ClearBit(&InUseDevices, pDevice->Device.number);
++ spin_unlock(&InUseDevicesLock);
++
++ if (pDevice->Device.id != NULL) {
++ KernelFree(pDevice->Device.id);
++ pDevice->Device.id = NULL;
++ }
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Add OS device to bus driver.
++
++ @function name: SDIO_BusAddOSDevice
++ @category: HD_Reference
++
++ @output: pDma - descrip[tion of support DMA or NULL
++ @output: pDriver - assigned driver object
++ @output: pDevice - assigned device object
++
++ @return: SDIO_STATUS - SDIO_STATUS_SUCCESS when successful.
++
++ @notes: If the HCD does not register with the driver sub-system directly (like in the PCI case),
++ then it should register with the bus driver to obtain OS dependent device objects.
++ All input structures should be maintained throughout the life of the driver.
++
++ @example: getting device objects:
++ typedef struct _SDHCD_DRIVER {
++ OS_PNPDEVICE HcdDevice; / * the OS device for this HCD * /
++ OS_PNPDRIVER HcdDriver; / * the OS driver for this HCD * /
++ SDDMA_DESCRIPTION Dma; / * driver DMA description * /
++ }SDHCD_DRIVER, *PSDHCD_DRIVER;
++
++ typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; / * human readable device decsription * /
++ SDLIST DeviceList; / * the list of current devices handled by this driver * /
++ OS_SEMAPHORE DeviceListSem; / * protection for the DeviceList * /
++ UINT DeviceCount; / * number of devices currently installed * /
++ SDHCD_DRIVER Driver; / * OS dependent driver specific info * /
++ }SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++ static SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .DeviceCount = 0,
++ .Driver.HcdDevice.name = "sdio_xxx_hcd",
++ .Driver.HcdDriver.name = "sdio_xxx_hcd",
++ }
++ .....
++ status = SDIO_BusAddOSDevice(NULL, &HcdContext.Driver, &HcdContext.Device);
++ if (SDIO_SUCCESS(status) {
++ return Probe(&HcdContext.Device);
++ }
++ return SDIOErrorToOSError(status);
++
++ @see also: SDIO_BusRemoveOSDevice
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SDIO_BusAddOSDevice(PSDDMA_DESCRIPTION pDma, POS_PNPDRIVER pDriver, POS_PNPDEVICE pDevice)
++{
++ int err;
++ struct pnp_id *pFdname;
++ struct pnp_device_id *pFdid;
++ static int slotNumber = 0; /* we just use an increasing count for the slots number */
++
++ if (pDma != NULL) {
++ pDevice->dev.dma_mask = &pDma->Mask;
++ pDevice->dev.coherent_dma_mask = pDma->Mask;
++ }
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BusDriver - SDIO_GetBusOSDevice, registering driver: %s DMAmask: 0x%x\n",
++ pDriver->name, (UINT)*pDevice->dev.dma_mask));
++ pFdid = KernelAlloc(sizeof(struct pnp_device_id)*2);
++ /* set the id as slot number/function number */
++ snprintf(pFdid[0].id, sizeof(pFdid[0].id), "SD_%02X08",
++ slotNumber++);
++ pFdid[0].driver_data = 0;
++ pFdid[1].id[0] = '\0';
++ pFdid[1].driver_data = 0;
++
++ pDriver->id_table = pFdid;
++ pDriver->flags = PNP_DRIVER_RES_DO_NOT_CHANGE;
++ err = pnp_register_driver(pDriver);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BusDriver - SDIO_GetBusOSDevice, failed registering driver: %s, err: %d\n",
++ pDriver->name, err));
++ return OSErrorToSDIOError(err);
++ }
++
++ pDevice->protocol = &sdio_protocol;
++ pDevice->capabilities = PNP_REMOVABLE | PNP_DISABLE;
++ pDevice->active = 1;
++
++ pFdname = KernelAlloc(sizeof(struct pnp_id));
++ /* set the id as slot number/function number */
++ snprintf(pFdname->id, sizeof(pFdname->id), "SD_%02X08",
++ 0); //??pDevice->pHcd->SlotNumber);//?????fix this, slotnumber isn't vaialble yet
++ pFdname->next = NULL;
++ pnp_add_id(pFdname, pDevice);
++
++ /* get a unique device number */
++ spin_lock(&InUseDevicesLock);
++ pDevice->number = FirstClearBit(&InUseDevices);
++ SetBit(&InUseDevices, pDevice->number);
++ spin_unlock(&InUseDevicesLock);
++ pnp_init_resource_table(&pDevice->res);
++ err = pnp_add_device(pDevice);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BusDriver - SDIO_GetBusOSDevice failed pnp_device_add: %d\n",
++ err));
++ pnp_unregister_driver(pDriver);
++ }
++ /* replace the buggy pnp's release */
++ pDevice->dev.release = release;
++ return OSErrorToSDIOError(err);
++}
++
++/**+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Return OS device from bus driver.
++
++ @function name: SDIO_BusRemoveOSDevice
++ @category: HD_Reference
++
++ @input: pDriver - setup PNP driver object
++ @input: pDevice - setup PNP device object
++
++ @return: none
++
++
++ @example: returning device objects:
++ SDIO_BusRemoveOSDevice(&HcdContext.Driver, &HcdContext.Device);
++
++
++ @see also: SDIO_BusAddOSDevice
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SDIO_BusRemoveOSDevice(POS_PNPDRIVER pDriver, POS_PNPDEVICE pDevice)
++{
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BusDriver - SDIO_PutBusOSDevice, unregistering driver: %s\n",
++ pDriver->name));
++
++// pnp_remove_device(pDevice);
++ if (pDevice->id != NULL) {
++ KernelFree(pDevice->id);
++ pDevice->id = NULL;
++ }
++
++ spin_lock(&InUseDevicesLock);
++ ClearBit(&InUseDevices, pDevice->number);
++ spin_unlock(&InUseDevicesLock);
++
++ pnp_unregister_driver(pDriver);
++ if (pDriver->id_table != NULL) {
++ KernelFree((void *)pDriver->id_table);
++ pDriver->id_table = NULL;
++ }
++
++}
++
++
++/*
++ * module init
++*/
++static int __init sdio_busdriver_init(void) {
++ SDIO_STATUS status;
++ int error;
++ REL_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: loaded\n"));
++ if (!SDIO_SUCCESS((status = _SDIO_BusDriverInitialize()))) {
++ return SDIOErrorToOSError(status);
++ }
++ /* register the sdio bus */
++ error = pnp_register_protocol(&sdio_protocol);
++ if (error < 0) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: failed to register bus device, %d\n", error));
++ _SDIO_BusDriverCleanup();
++ return error;
++ }
++ return 0;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_busdriver_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO unloaded\n"));
++ _SDIO_BusDriverCleanup();
++ pnp_unregister_protocol(&sdio_protocol);
++DBG_PRINT(SDDBG_TRACE,
++ ("SDIO BusDriver - unloaded 1\n"));
++}
++EXPORT_SYMBOL(SDIO_BusAddOSDevice);
++EXPORT_SYMBOL(SDIO_BusRemoveOSDevice);
++
++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++ /* 2.4 */
++static int RegisterDriver(PSDFUNCTION pFunction)
++{
++ return 0;
++}
++
++static int UnregisterDriver(PSDFUNCTION pFunction)
++{
++ DBG_PRINT(SDDBG_TRACE,
++ ("+-SDIO BusDriver - UnregisterDriver, driver: \n"));
++ return 0;
++}
++
++/*
++ * OS_InitializeDevice - initialize device that will be registered
++*/
++SDIO_STATUS OS_InitializeDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction)
++{
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * OS_AddDevice - must be pre-initialized with OS_InitializeDevice
++*/
++SDIO_STATUS OS_AddDevice(PSDDEVICE pDevice, PSDFUNCTION pFunction)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - OS_AddDevice adding function: %s\n",
++ pFunction->pName));
++ return SDIO_STATUS_SUCCESS;
++
++}
++
++/*
++ * OS_RemoveDevice - unregister device with driver and bus
++*/
++void OS_RemoveDevice(PSDDEVICE pDevice)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BusDriver - OS_RemoveDevice \n"));
++}
++
++/*
++ * module init
++*/
++static int __init sdio_busdriver_init(void) {
++ SDIO_STATUS status;
++ REL_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: loaded\n"));
++ if (!SDIO_SUCCESS((status = _SDIO_BusDriverInitialize()))) {
++ return SDIOErrorToOSError(status);
++ }
++ return 0;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_busdriver_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO unloaded\n"));
++ _SDIO_BusDriverCleanup();
++}
++#else ////KERNEL_VERSION
++#error "unsupported kernel version: "UTS_RELEASE
++#endif //KERNEL_VERSION
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_busdriver_init);
++module_exit(sdio_busdriver_cleanup);
++EXPORT_SYMBOL(SDIO_RegisterHostController);
++EXPORT_SYMBOL(SDIO_UnregisterHostController);
++EXPORT_SYMBOL(SDIO_HandleHcdEvent);
++EXPORT_SYMBOL(SDIO_CheckResponse);
++EXPORT_SYMBOL(SDIO_RegisterFunction);
++EXPORT_SYMBOL(SDIO_UnregisterFunction);
+Index: linux-2.6.22/drivers/sdio/busdriver/sdio_function.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/busdriver/sdio_function.c 2007-11-08 17:15:26.000000000 +0100
+@@ -0,0 +1,713 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_function.c
++
++ at abstract: OS independent bus driver support for function drivers
++
++ at notes: This file supports the interface between SDIO function drivers and the bus driver.
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDBUSDRIVER
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "_busdriver.h"
++
++static SDIO_STATUS ProbeForDevice(PSDFUNCTION pFunction);
++
++#ifdef CT_MAN_CODE_CHECK
++static UINT16 ManCodeCheck = CT_MAN_CODE_CHECK;
++#endif
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Register a function driver with the bus driver.
++
++ @function name: SDIO_RegisterFunction
++ @prototype: SDIO_STATUS SDIO_RegisterFunction(PSDFUNCTION pFunction)
++ @category: PD_Reference
++ @input: pFunction - the function definition structure.
++
++ @output: none
++
++ @return: SDIO_STATUS - SDIO_STATUS_SUCCESS when succesful.
++
++ @notes: Each function driver must register with the bus driver once upon loading.
++ The calling function must be prepared to receive a Probe callback before
++ this function returns. This will occur when an perpheral device is already
++ pluugged in that is supported by this function.
++ The function driver should unregister itself when exiting.
++ The bus driver checks for possible function drivers to support a device
++ in reverse registration order.
++
++ @example: Registering a function driver:
++ //list of devices supported by this function driver
++ static SD_PNP_INFO Ids[] = {
++ {.SDIO_ManufacturerID = 0xaa55,
++ .SDIO_ManufacturerCode = 0x5555,
++ .SDIO_FunctionNo = 1},
++ {} //list is null termintaed
++ };
++ static GENERIC_FUNCTION_CONTEXT FunctionContext = {
++ .Function.pName = "sdio_generic", //name of the device
++ .Function.Version = CT_SDIO_STACK_VERSION_CODE, // set stack version
++ .Function.MaxDevices = 1, //maximum number of devices supported by this driver
++ .Function.NumDevices = 0, //current number of devices, always zero to start
++ .Function.pIds = Ids, //the list of devices supported by this device
++ .Function.pProbe = Probe, //pointer to the function drivers Probe function
++ // that will be called when a possibly supported device
++ // is inserted.
++ .Function.pRemove = Remove, //pointer to the function drivers Remove function
++ / that will be called when a device is removed.
++ .Function.pContext = &FunctionContext, //data value that will be passed into Probe and
++ // Remove callbacks.
++ };
++ SDIO_STATUS status;
++ status = SDIO_RegisterFunction(&FunctionContext.Function)
++ if (!SDIO_SUCCESS(status)) {
++ ...failed to register
++ }
++
++ @see also: SDIO_UnregisterFunction
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_RegisterFunction(PSDFUNCTION pFunction)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++#ifdef CT_MAN_CODE_CHECK
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Bus Driver: _SDIO_RegisterFunction: WARNING, this version is locked to Memory cards and SDIO cards with JEDEC IDs of: 0x%X\n",
++ ManCodeCheck));
++#else
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: _SDIO_RegisterFunction\n"));
++#endif
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: Function Driver Stack Version: %d.%d \n",
++ GET_SDIO_STACK_VERSION_MAJOR(pFunction),GET_SDIO_STACK_VERSION_MINOR(pFunction)));
++
++ if (!CHECK_FUNCTION_DRIVER_VERSION(pFunction)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Bus Driver: Function Major Version Mismatch (hcd = %d, bus driver = %d)\n",
++ GET_SDIO_STACK_VERSION_MAJOR(pFunction), CT_SDIO_STACK_VERSION_MAJOR(g_Version)));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++
++ /* sanity check the driver */
++ if ((pFunction == NULL) ||
++ (pFunction->pProbe == NULL) ||
++ (pFunction->pIds == NULL)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_RegisterFunction, invalid registration data\n"));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++ /* protect the function list and add the function */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ SignalInitialize(&pFunction->CleanupReqSig);
++ SDLIST_INIT(&pFunction->DeviceList);
++ SDListAdd(&pBusContext->FunctionList, &pFunction->SDList);
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++
++ /* see if we have devices for this new function driver */
++ ProbeForDevice(pFunction);
++
++ return status;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: _SDIO_RegisterFunction, error exit 0x%X\n", status));
++ return status;
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Unregister a function driver with the bus driver.
++
++ @function name: SDIO_UnregisterFunction
++ @prototype: SDIO_STATUS SDIO_UnregisterFunction(PSDFUNCTION pFunction)
++ @category: PD_Reference
++
++ @input: pFunction - the function definition structure.
++
++ @output: none
++
++ @return: SDIO_STATUS - SDIO_STATUS_SUCCESS when succesful.
++
++ @notes: Each function driver must unregister from the bus driver when the function driver
++ exits.
++ A function driver must disconnect from any interrupts before calling this function.
++
++ @example: Unregistering a function driver:
++ SDIO_UnregisterFunction(&FunctionContext.Function);
++
++ @see also: SDIO_RegisterFunction
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS _SDIO_UnregisterFunction(PSDFUNCTION pFunction)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDDEVICE pDevice;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: _SDIO_UnregisterFunction\n"));
++
++ /* protect the function list and synchronize with Probe() and Remove()*/
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ /* remove this function from the function list */
++ SDListRemove(&pFunction->SDList);
++ /* now remove this function as the handler for any of its devices */
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pFunction->DeviceList, pDevice, SDDEVICE,FuncListLink) {
++ if (pDevice->pFunction == pFunction) {
++ /* notify removal */
++ NotifyDeviceRemove(pDevice);
++ }
++ }SDITERATE_END;
++
++ SignalDelete(&pFunction->CleanupReqSig);
++
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: _SDIO_UnregisterFunction\n"));
++ return status;
++
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: _SDIO_UnregisterFunction, error exit 0x%X\n", status));
++ return status;
++}
++
++/* documentation headers only for Probe and Remove */
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: This function is called by the Busdriver when a device is inserted that can be supported by this function driver.
++
++ @function name: Probe
++ @prototype: BOOL (*pProbe)(struct _SDFUNCTION *pFunction, struct _SDDEVICE *pDevice)
++ @category: PD_Reference
++
++ @input: pFunction - the function definition structure that was passed to Busdriver
++ via the SDIO_RegisterFunction.
++ @input: pDevice - the description of the newly inserted device.
++
++ @output: none
++
++ @return: TRUE - this function driver will suport this device
++ FALSE - this function driver will not support this device
++
++ @notes: The Busdriver calls the Probe function of a function driver to inform it that device is
++ available for the function driver to control. The function driver should initialize the
++ device and be pepared to acceopt any interrupts from the device before returning.
++
++ @example: Example of typical Probe function callback:
++ static BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice) {
++ ...get the our context info passed into the SDIO_RegisterFunction
++ PSDXXX_DRIVER_CONTEXT pFunctionContext =
++ (PSDXXX_DRIVER_CONTEXT)pFunction->pContext;
++ SDIO_STATUS status;
++ //test the identification of this device and ensure we want to support it
++ // we can test based on class, or use more specific tests on SDIO_ManufacturerID, etc.
++ if (pDevice->pId[0].SDIO_FunctionClass == XXX) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO XXX Function: Probe - card matched (0x%X/0x%X/0x%X)\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode,
++ pDevice->pId[0].SDIO_FunctionNo));
++ ...
++
++ @see also: SDIO_RegisterFunction
++ @see also: Remove
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++BOOL FilterPnpInfo(PSDDEVICE pDevice)
++{
++#ifdef CT_MAN_CODE_CHECK
++ if (pDevice->pId[0].CardFlags & CARD_SDIO) {
++ if (pDevice->pId[0].SDIO_ManufacturerCode != ManCodeCheck) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO Card with JEDEC ID:0x%X , not Allowed! Driver check halted. "
++ "Please Contact sales at codetelligence.com.\n",
++ pDevice->pId[0].SDIO_ManufacturerCode));
++ return FALSE;
++ }
++ }
++ return TRUE;
++#else
++ return TRUE;
++#endif
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: This function is called by the Busdriver when a device controlled by this function
++ function driver is removed.
++
++ @function name: Remove
++ @prototype: void (*pRemove)(struct _SDFUNCTION *pFunction, struct _SDDEVICE *pDevice)
++ @category: PD_Reference
++
++ @input: pFunction - the function definition structure that was passed to Busdriver
++ via the SDIO_RegisterFunction.
++ @input: pDevice - the description of the device being removed.
++
++ @output: none
++
++ @return: none
++
++ @notes: The Busdriver calls the Remove function of a function driver to inform it that device it
++ was supporting has been removed. The device has already been removed, so no further I/O
++ to the device can be performed.
++
++ @example: Example of typical Remove function callback:
++ void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice) {
++ // get the our context info passed into the SDIO_RegisterFunction
++ PSDXXX_DRIVER_CONTEXT pFunctionContext =
++ (PSDXXX_DRIVER_CONTEXT)pFunction->pContext;
++ ...free any acquired resources.
++
++ @see also: SDIO_RegisterFunction
++ @see also: Probe
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/*
++ * ProbeForFunction - look for a function driver to handle this card
++ *
++*/
++SDIO_STATUS ProbeForFunction(PSDDEVICE pDevice, PSDHCD pHcd) {
++ SDIO_STATUS status;
++ PSDLIST pList;
++ PSDFUNCTION pFunction;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: ProbeForFunction\n"));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForFunction - Dump of Device PNP Data: \n"));
++ DBG_PRINT(SDDBG_TRACE, (" Card Flags 0x%X \n", pDevice->pId[0].CardFlags));
++ if (pDevice->pId[0].CardFlags & CARD_SDIO) {
++ DBG_PRINT(SDDBG_TRACE, (" SDIO MANF: 0x%X \n", pDevice->pId[0].SDIO_ManufacturerID));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO MANFCODE: 0x%X \n", pDevice->pId[0].SDIO_ManufacturerCode));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO FuncNo: %d \n", pDevice->pId[0].SDIO_FunctionNo));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO FuncClass: %d \n", pDevice->pId[0].SDIO_FunctionClass));
++ }
++ if (pDevice->pId[0].CardFlags & (CARD_MMC | CARD_SD)) {
++ DBG_PRINT(SDDBG_TRACE, (" SDMMC MANFID: 0x%X \n",pDevice->pId[0].SDMMC_ManfacturerID));
++ DBG_PRINT(SDDBG_TRACE, (" SDMMC OEMID: 0x%X \n",pDevice->pId[0].SDMMC_OEMApplicationID));
++ }
++
++ if (!FilterPnpInfo(pDevice)) {
++ status = SDIO_STATUS_SUCCESS;
++ goto cleanup;
++ }
++
++ /* protect the function list */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++
++ /* protect against ProbeForDevice */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->DeviceListSem)))) {
++ /* release the function list semaphore we just took */
++ SemaphorePost(&pBusContext->FunctionListSem);
++ goto cleanup;
++ }
++
++ if (pDevice->pFunction != NULL) {
++ /* device already has a function driver handling it */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForFunction, device already has function\n"));
++ /* release function list */
++ SemaphorePost(&pBusContext->DeviceListSem);
++ /* release function list */
++ SemaphorePost(&pBusContext->FunctionListSem);
++ /* just return success */
++ status = SDIO_STATUS_SUCCESS;
++ goto cleanup;
++ }
++
++ /* release device list */
++ SemaphorePost(&pBusContext->DeviceListSem);
++
++ /* walk functions looking for one that can handle this device */
++ SDITERATE_OVER_LIST(&pBusContext->FunctionList, pList) {
++ pFunction = CONTAINING_STRUCT(pList, SDFUNCTION, SDList);
++ if (pFunction->NumDevices >= pFunction->MaxDevices) {
++ /* function can't support any more devices */
++ continue;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForFunction - checking: %s \n",
++ pFunction->pName));
++
++ /* see if this function handles this device */
++ if (IsPotentialIdMatch(pDevice->pId, pFunction->pIds)) {
++ if (!FilterPnpInfo(pDevice)) {
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForFunction -Got Match, probing: %s \n",
++ pFunction->pName));
++ /* we need to setup with the OS bus driver before the probe, so probe can
++ do OS operations. */
++ OS_InitializeDevice(pDevice, pFunction);
++ if (!SDIO_SUCCESS(OS_AddDevice(pDevice, pFunction))) {
++ break;
++ }
++ /* close enough match, ask the function driver if it supports us */
++ if (pFunction->pProbe(pFunction, pDevice)) {
++ /* she accepted the device, add to list */
++ pDevice->pFunction = pFunction;
++ SDListAdd(&pFunction->DeviceList, &pDevice->FuncListLink);
++ pFunction->NumDevices++;
++ break;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: %s did not claim the device \n",
++ pFunction->pName));
++ /* didn't take this device */
++ OS_RemoveDevice(pDevice);
++ }
++
++ }
++ }
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: ProbeForFunction\n"));
++ return status;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: ProbeForFunction, error exit 0x%X\n", status));
++ return status;
++}
++
++/*
++ * ProbeForDevice - look for a device that this function driver supports
++ *
++*/
++static SDIO_STATUS ProbeForDevice(PSDFUNCTION pFunction) {
++ SDIO_STATUS status;
++ PSDLIST pList;
++ PSDDEVICE pDevice;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForDevice\n"));
++ if (pFunction->NumDevices >= pFunction->MaxDevices) {
++ /* function can't support any more devices */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForDevice, too many devices in function\n"));
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ /* protect the driver list */
++ if (!SDIO_SUCCESS((status = SemaphorePendInterruptable(&pBusContext->DeviceListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ /* walk device list */
++ SDITERATE_OVER_LIST(&pBusContext->DeviceList, pList) {
++ pDevice = CONTAINING_STRUCT(pList, SDDEVICE, SDList);
++ if (pDevice->pFunction != NULL) {
++ /* device already has a function driver handling it */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForDevice, device already has function\n"));
++ continue;
++ }
++ /* see if this function handles this device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForDevice, matching ID:%d %d class:%d\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_FunctionNo,
++ pDevice->pId[0].SDIO_FunctionClass));
++ if (IsPotentialIdMatch(pDevice->pId, pFunction->pIds)) {
++ if (!FilterPnpInfo(pDevice)) {
++ break;
++ }
++ /* we need to setup with the OS bus driver before the probe, so probe can
++ do OS operations. */
++ OS_InitializeDevice(pDevice, pFunction);
++ if (!SDIO_SUCCESS(OS_AddDevice(pDevice, pFunction))) {
++ break;
++ }
++ /* close enough match, ask the function driver if it supports us */
++ if (pFunction->pProbe(pFunction, pDevice)) {
++ /* she accepted the device, add to list */
++ pDevice->pFunction = pFunction;
++ SDListAdd(&pFunction->DeviceList, &pDevice->FuncListLink);
++ pFunction->NumDevices++;
++ break;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bus Driver: %s did not claim the device \n",
++ pFunction->pName));
++ /* didn't take this device */
++ OS_RemoveDevice(pDevice);
++ }
++ }
++ }
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->DeviceListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: ProbeForDevice, done: %d\n", status));
++
++ return status;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: ProbeForDevice, error exit 0x%X\n", status));
++ return status;
++}
++
++#if 0
++static void DumpPnpEntry(PSD_PNP_INFO pInfo)
++{
++ DBG_PRINT(SDDBG_TRACE, ("Function PnpInfo Dump: \n"));
++ DBG_PRINT(SDDBG_TRACE, (" Card Flags 0x%X \n", pInfo->CardFlags));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO MANF: 0x%X \n", pInfo->SDIO_ManufacturerID));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO MANFCODE: 0x%X \n", pInfo->SDIO_ManufacturerCode));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO FuncNo: %d \n", pInfo->SDIO_FunctionNo));
++ DBG_PRINT(SDDBG_TRACE, (" SDIO FuncClass: %d \n", pInfo->SDIO_FunctionClass));
++ DBG_PRINT(SDDBG_TRACE, (" SDMMC MANFID: 0x%X \n", pInfo->SDMMC_ManfacturerID));
++ DBG_PRINT(SDDBG_TRACE, (" SDMMC OEMID: 0x%X \n", pInfo->SDMMC_OEMApplicationID));
++}
++#endif
++/*
++ * IsPotentialIdMatch - test for potential device match
++ *
++*/
++BOOL IsPotentialIdMatch(PSD_PNP_INFO pIdsDev, PSD_PNP_INFO pIdsFuncList) {
++ PSD_PNP_INFO pTFn;
++ BOOL match = FALSE;
++
++ for (pTFn = pIdsFuncList;!IS_LAST_SDPNPINFO_ENTRY(pTFn);pTFn++) {
++ //DumpPnpEntry(pTFn);
++ /* check specific SDIO Card manufacturer ID, Code and Function number */
++ if ((pIdsDev->SDIO_ManufacturerID != 0) &&
++ (pTFn->SDIO_ManufacturerID != 0) &&
++ (pIdsDev->SDIO_ManufacturerID == pTFn->SDIO_ManufacturerID) &&
++ (pIdsDev->SDIO_ManufacturerCode == pTFn->SDIO_ManufacturerCode) &&
++ ((pIdsDev->SDIO_FunctionNo == pTFn->SDIO_FunctionNo) ||
++ (pTFn->SDIO_FunctionNo == 0)) ) {
++ match = TRUE;
++ break;
++ }
++ /* check generic function class */
++ if ((pIdsDev->SDIO_FunctionClass != 0) &&
++ (pTFn->SDIO_FunctionClass != 0) &&
++ (pIdsDev->SDIO_FunctionClass == pTFn->SDIO_FunctionClass)) {
++ match = TRUE;
++ break;
++ }
++ /* check specific SDMMC MANFID and APPLICATION ID, NOTE SANDISK
++ * uses a MANFID of zero! */
++ if ((pTFn->SDMMC_OEMApplicationID != 0) &&
++ (pIdsDev->SDMMC_ManfacturerID == pTFn->SDMMC_ManfacturerID) &&
++ (pIdsDev->SDMMC_OEMApplicationID == pTFn->SDMMC_OEMApplicationID)) {
++ match = TRUE;
++ break;
++ }
++
++ /* check generic SD Card */
++ if ((pIdsDev->CardFlags & CARD_SD) &&
++ (pTFn->CardFlags & CARD_SD)){
++ match = TRUE;
++ break;
++ }
++
++ /* check generic MMC Card */
++ if ((pIdsDev->CardFlags & CARD_MMC) &&
++ (pTFn->CardFlags & CARD_MMC)){
++ match = TRUE;
++ break;
++ }
++
++ /* check raw Card */
++ if ((pIdsDev->CardFlags & CARD_RAW) &&
++ (pTFn->CardFlags & CARD_RAW)){
++ match = TRUE;
++ break;
++ }
++ }
++
++ return match;
++}
++
++/*
++ * NotifyDeviceRemove - tell function driver on this device that the device is being removed
++ *
++*/
++SDIO_STATUS NotifyDeviceRemove(PSDDEVICE pDevice) {
++ SDIO_STATUS status;
++ SDREQUESTQUEUE cancelQueue;
++ PSDREQUEST pReq;
++ CT_DECLARE_IRQ_SYNC_CONTEXT();
++
++ InitializeRequestQueue(&cancelQueue);
++
++ if ((pDevice->pFunction != NULL) &&
++ (pDevice->pFunction->pRemove != NULL)){
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: removing device 0x%X\n", (INT)pDevice));
++ /* fail any outstanding requests for this device */
++ /* acquire lock for request queue */
++ status = _AcquireHcdLock(pDevice->pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ /* mark the function to block any more requests comming down */
++ pDevice->pFunction->Flags |= SDFUNCTION_FLAG_REMOVING;
++ /* walk through HCD queue and remove this function's requests */
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pDevice->pHcd->RequestQueue.Queue, pReq, SDREQUEST, SDList) {
++ if (pReq->pFunction == pDevice->pFunction) {
++ /* cancel this request, as this device or function is being removed */
++ /* note that these request are getting completed out of order */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - NotifyDeviceRemove: canceling req 0x%X\n", (UINT)pReq));
++ pReq->Status = SDIO_STATUS_CANCELED;
++ /* remove it from the HCD queue */
++ SDListRemove(&pReq->SDList);
++ /* add it to the cancel queue */
++ QueueRequest(&cancelQueue, pReq);
++ }
++ }SDITERATE_END;
++
++ status = _ReleaseHcdLock(pDevice->pHcd);
++
++ /* now empty the cancel queue if anything is in there */
++ while (TRUE) {
++ pReq = DequeueRequest(&cancelQueue);
++ if (NULL == pReq) {
++ break;
++ }
++ /* complete the request */
++ DoRequestCompletion(pReq, pDevice->pHcd);
++ }
++ /* re-acquire the lock to deal with the current request */
++ status = _AcquireHcdLock(pDevice->pHcd);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ /* now deal with the current request */
++ pReq = GET_CURRENT_REQUEST(pDevice->pHcd);
++ if ((pReq !=NULL) && (pReq->pFunction == pDevice->pFunction) && (pReq->pFunction != NULL)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - NotifyDeviceRemove: Outstanding Req 0x%X on HCD: 0x%X.. waiting...\n",
++ (UINT)pReq, (UINT)pDevice->pHcd));
++ /* the outstanding request on this device is for the function being removed */
++ pReq->Flags |= SDREQ_FLAGS_CANCELED;
++ /* wait for this request to get completed normally */
++ status = _ReleaseHcdLock(pDevice->pHcd);
++ SignalWait(&pDevice->pFunction->CleanupReqSig);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver - NotifyDeviceRemove: Outstanding HCD Req 0x%X completed \n", (UINT)pReq));
++ } else {
++ /* release lock */
++ status = _ReleaseHcdLock(pDevice->pHcd);
++ }
++
++ /* synchronize with ISR SYNC Handlers */
++ status = SemaphorePendInterruptable(&pBusContext->DeviceListSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++ /* call this devices Remove function */
++ pDevice->pFunction->pRemove(pDevice->pFunction,pDevice);
++ pDevice->pFunction->NumDevices--;
++ /* make sure the sync handler is NULLed out */
++ pDevice->pIrqFunction = NULL;
++ SemaphorePost(&pBusContext->DeviceListSem);
++
++ OS_RemoveDevice(pDevice);
++ /* detach this device from the function list it belongs to */
++ SDListRemove(&pDevice->FuncListLink);
++ pDevice->pFunction->Flags &= ~SDFUNCTION_FLAG_REMOVING;
++ pDevice->pFunction = NULL;
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++
++/*
++ * RemoveHcdFunctions - remove all functions attached to an HCD
++ *
++*/
++SDIO_STATUS RemoveHcdFunctions(PSDHCD pHcd) {
++ SDIO_STATUS status;
++ PSDLIST pList;
++ PSDFUNCTION pFunction;
++ PSDDEVICE pDevice;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bus Driver: RemoveHcdFunctions\n"));
++
++ /* walk through the functions and remove the ones associated with this HCD */
++ /* protect the driver list */
++ if (!SDIO_SUCCESS((status = SemaphorePend(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ /* mark that card is being removed */
++ pHcd->CardProperties.CardState |= CARD_STATE_REMOVED;
++ SDITERATE_OVER_LIST(&pBusContext->FunctionList, pList) {
++ pFunction = CONTAINING_STRUCT(pList, SDFUNCTION, SDList);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bus Driver: scanning function 0x%X, %s\n", (INT)pFunction,
++ (pFunction == NULL)?"NULL":pFunction->pName));
++
++ /* walk the devices on this function and look for a match */
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pFunction->DeviceList, pDevice, SDDEVICE,FuncListLink) {
++ if (pDevice->pHcd == pHcd) {
++ /* match, remove it */
++ NotifyDeviceRemove(pDevice);
++ }
++ SDITERATE_END;
++ SDITERATE_END;
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->FunctionListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bus Driver: RemoveHcdFunctions\n"));
++ return SDIO_STATUS_SUCCESS;
++
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO Bus Driver: RemoveHcdFunctions, error exit 0x%X\n", status));
++ return status;
++}
++
++/*
++ * RemoveAllFunctions - remove all functions attached
++ *
++*/
++SDIO_STATUS RemoveAllFunctions()
++{
++ SDIO_STATUS status;
++ PSDLIST pList;
++ PSDHCD pHcd;
++
++ /* walk through the HCDs */
++ /* protect the driver list */
++ if (!SDIO_SUCCESS((status = SemaphorePend(&pBusContext->HcdListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ SDITERATE_OVER_LIST(&pBusContext->HcdList, pList) {
++ pHcd = CONTAINING_STRUCT(pList, SDHCD, SDList);
++ /* remove the functions */
++ RemoveHcdFunctions(pHcd);
++ }
++ if (!SDIO_SUCCESS((status = SemaphorePost(&pBusContext->HcdListSem)))) {
++ goto cleanup; /* wait interrupted */
++ }
++ return SDIO_STATUS_SUCCESS;
++cleanup:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bus Driver: RemoveAllFunctions, error exit 0x%X\n", status));
++ return status;
++}
++
+Index: linux-2.6.22/drivers/sdio/hcd/Kconfig
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/Kconfig 2007-11-08 17:25:17.000000000 +0100
+@@ -0,0 +1,56 @@
++#
++#
++#
++
++menu "Host Controllers"
++
++config SDIO_ELLEN
++ tristate "PCI ELLEN (Tokyo Electron) host controller"
++ depends on PCI
++ default m
++ help
++ good luck.
++
++config SDIO_MX21
++ tristate "ARM MX21 host controller"
++ depends on ARCH_MX21
++ default m
++ help
++ good luck.
++
++config SDIO_OMAP
++ tristate "ARM OMAP host controller"
++ depends on ARCH_OMAP
++ default m
++ help
++ good luck.
++
++config SDIO_OMAP_2420
++ tristate "ARM OMAP 2420 host controller"
++ depends on ARCH_OMAP24XX
++ default m
++ help
++ good luck.
++
++config SDIO_PXA270
++ tristate "ARM PXA270 host controller"
++ depends on PXA27x
++ default m
++ help
++ good luck.
++
++config SDIO_PXA255
++ tristate "ARM PXA255 host controller"
++ depends on PXA255
++ default m
++ help
++ good luck.
++
++config SDIO_SPI
++ tristate "SPI host controller"
++ depends on SPI
++ default m
++ help
++ good luck.
++
++endmenu
+Index: linux-2.6.22/drivers/sdio/hcd/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/Makefile 2007-11-08 17:25:17.000000000 +0100
+@@ -0,0 +1,8 @@
++# SDIO stack host controller Makefile
++obj-$(CONFIG_SDIO_STDHCD) += stdhost/
++obj-$(CONFIG_SDIO_ELLEN) += pci_ellen/
++obj-$(CONFIG_ARCH_MX21) += mx21/
++obj-$(CONFIG_ARCH_OMAP) += omap/
++obj-$(CONFIG_ARCH_OMAP24XX) += omap_2420/
++obj-$(CONFIG_PXA27x) += pxa270/
++obj-$(CONFIG_PXA255) += pxa255/
+Index: linux-2.6.22/drivers/sdio/hcd/pci_ellen/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pci_ellen/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,7 @@
++#
++# SDIO pci_ellen host controller makefile
++#
++obj-m += sdio_pciellen_hcd.o
++
++sdio_pciellen_hcd-objs := sdio_hcd.o sdio_hcd_os.o
++
+Index: linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1238 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd.c
++
++ at abstract: Tokyo Electron PCI Ellen SDIO Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++#include "sdio_pciellen_hcd.h"
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++void Dbg_DumpBuffer(PUCHAR pBuffer, INT Length);
++SDIO_STATUS SetPowerLevel(PSDHCD_DEVICE pDeviceContext, BOOL On, SLOT_VOLTAGE_MASK Level);
++
++
++SD_CLOCK_TBL_ENTRY SDClockDivisorTable[SD_CLOCK_MAX_ENTRIES] =
++{ /* clock rate divisor, divisor setting */
++ {1, 0x0000},
++ {2, 0x0100},
++ {4, 0x0200},
++ {8, 0x0400},
++ {16,0x0800},
++ {32,0x1000},
++ {64,0x2000},
++ {128,0x4000},
++ {256,0x8000},
++};
++
++
++#define WAIT_REGISTER32_CHANGE(pDevice, pStatus, reg,mask,cmp,timout) \
++ {\
++ if (!WaitRegisterBitsChange((pDevice), \
++ (pStatus), \
++ (reg), \
++ (mask), \
++ (cmp), \
++ (timout))) { \
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - Reg Change Timeout : 0x%X src:%s, line:%d \n",\
++ (reg),__FILE__, __LINE__)); \
++ } \
++ }
++
++#define WAIT_FOR_DAT_CMD_DAT_READY(pDevice, pStatus) \
++ WAIT_REGISTER32_CHANGE(pDevice, \
++ pStatus, \
++ HOST_REG_PRESENT_STATE,(HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_DAT | \
++ HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD), \
++ 0, 30000)
++
++
++INLINE BOOL WaitRegisterBitsChange(PSDHCD_DEVICE pDevice,
++ SDIO_STATUS *pStatus,
++ UINT32 Reg,
++ UINT32 Mask,
++ UINT32 CompareMask,
++ UINT32 Count)
++{
++ while (Count) {
++
++ if ((READ_HOST_REG32(pDevice, Reg) & Mask) == CompareMask) {
++ break;
++ }
++
++ Count--;
++ }
++
++ if (0 == Count) {
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_ERROR;
++ }
++ return FALSE;
++ }
++
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_SUCCESS;
++ }
++
++ return TRUE;
++}
++
++
++/* reset command data line state machines - xx*/
++void ResetCmdDatLine(PSDHCD_DEVICE pDevice)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen Issuing CMD DAT Reset \n"));
++ // issue reset
++ WRITE_HOST_REG32(pDevice, HOST_REG_SW_RESET,
++ (HOST_REG_SW_RST_CMD_LINE | HOST_REG_SW_RST_DAT_LINE));
++ // wait for bits to clear
++ WAIT_REGISTER32_CHANGE(pDevice, NULL,
++ HOST_REG_SW_RESET,
++ HOST_REG_SW_RST_CMD_LINE | HOST_REG_SW_RST_DAT_LINE,
++ 0,
++ 30000);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen CMD DAT Reset Done \n"));
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pDevice - device context
++ pReq - the request
++ Output:
++ Return: returns status
++ Notes: This function returns SDIO_STATUS_SUCCESS for SD mode.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS GetResponseData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT dwordCount;
++ INT byteCount;
++ UINT32 readBuffer[4];
++ UINT ii;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return SDIO_STATUS_SUCCESS;
++ }
++
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES;
++ }
++ dwordCount = (byteCount + 3) / 4;
++
++ /* move data into read buffer */
++ for (ii = 0; ii < dwordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG32(pDevice, HOST_REG_RESPONSE+(ii*4));
++ }
++
++ /* handle normal SD/MMC responses */
++
++ /* the standard host strips the CRC for all responses and puts them in
++ * a nice linear order */
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_REQUESTS) {
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = 17;
++ }
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO PCI Ellen - Response Dump");
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ DumpCurrentRequestInfo - debug dump
++ Input: pDevice - device context
++ Output:
++ Return:
++ Notes: This function debug prints the current request
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void DumpCurrentRequestInfo(PSDHCD_DEVICE pDevice)
++{
++ if (pDevice->Hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - Current Request Command:%d, ARG:0x%8.8X\n",
++ pDevice->Hcd.pCurrentRequest->Command, pDevice->Hcd.pCurrentRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pDevice->Hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pDevice->Hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ pDevice->Hcd.pCurrentRequest->BlockCount,
++ pDevice->Hcd.pCurrentRequest->BlockLen,
++ pDevice->Hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateSDError - check for an SD error
++ Input: pDevice - device context
++ Status - error interrupt status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateSDError(PSDHCD_DEVICE pDevice, UINT16 Status)
++{
++ if (Status & HOST_REG_ERROR_INT_STATUS_CRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - RESP CRC ERROR \n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ } else if (Status & HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - DATA TIMEOUT ERROR \n"));
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ } else if (Status & HOST_REG_ERROR_INT_STATUS_DATACRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - READDATA CRC ERROR \n"));
++ DumpCurrentRequestInfo(pDevice);
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ } else if (Status & HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR) {
++ if (pDevice->CardInserted) {
++ /* hide error if we are polling an empty slot */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - RESPONSE TIMEOUT \n"));
++ }
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen - untranslated error 0x%X\n", (UINT)Status));
++
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - SD clock control
++ Input: pDevice - device object
++ On - turn on or off (TRUE/FALSE)
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_DEVICE pDevice, BOOL On)
++{
++ /* beware, an unprotected read-modify-write */
++ UINT16 state;
++
++ DBG_PRINT(PXA_TRACE_CLOCK, ("SDIO PCI Ellen - ClockStartStop, %d\n", (UINT)On));
++
++ state = READ_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL);
++
++ if (On) {
++ state |= HOST_REG_CLOCK_CONTROL_SD_ENABLE;
++ WRITE_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL, state);
++ } else {
++ state &= ~HOST_REG_CLOCK_CONTROL_SD_ENABLE;
++ WRITE_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL, state);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pDevice - device object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DEVICE pDevice, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int ii;
++ int clockIndex;
++ UINT16 state;
++ UINT32 rate;
++
++ DBG_PRINT(PXA_TRACE_CONFIG , ("SDIO PCI Ellen - SetMode\n"));
++
++ /* set clock index to the end, the table is sorted this way */
++ clockIndex = SD_CLOCK_MAX_ENTRIES - 1;
++ pMode->ActualClockRate = (pDevice->BaseClock) / SDClockDivisorTable[clockIndex].ClockRateDivisor;
++ for (ii = 0; ii < SD_CLOCK_MAX_ENTRIES; ii++) {
++ rate = pDevice->BaseClock / SDClockDivisorTable[ii].ClockRateDivisor;
++ if (pMode->ClockRate >= rate) {
++ pMode->ActualClockRate = rate;
++ clockIndex = ii;
++ break;
++ }
++ }
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ WRITE_HOST_REG8(pDevice, HOST_REG_CONTROL, HOST_REG_CONTROL_1BIT_WIDTH);
++ //WRITE_HOST_REG16(pDevice, HOST_REG_CONTROL, HOST_REG_CONTROL_1BIT_WIDTH);
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ WRITE_HOST_REG8(pDevice, HOST_REG_CONTROL, HOST_REG_CONTROL_4BIT_WIDTH);
++ //WRITE_HOST_REG16(pDevice, HOST_REG_CONTROL, HOST_REG_CONTROL_4BIT_WIDTH);
++ break;
++ default:
++ break;
++ }
++
++ /* set the clock divisor, unprotected read modify write */
++ state = SDClockDivisorTable[clockIndex].RegisterValue | HOST_REG_CLOCK_CONTROL_CLOCK_ENABLE;
++ WRITE_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL, state);
++
++ /* wait for stable */
++ while(!(READ_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL) & HOST_REG_CLOCK_CONTROL_CLOCK_STABLE)) {
++ ;
++ }
++ WRITE_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL, state | HOST_REG_CLOCK_CONTROL_SD_ENABLE);
++
++ state = READ_HOST_REG16(pDevice, HOST_REG_CLOCK_CONTROL);
++ DBG_PRINT(PXA_TRACE_CONFIG , ("SDIO PCI Ellen - Clock: %d Khz, ClockRate %d (%d) state:0x%X\n",
++ pMode->ActualClockRate, pMode->ClockRate, clockIndex, (UINT)state));
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdTransferTxData - data transmit transfer
++ Input: pDevice - device object
++ pReq - transfer request
++ Output:
++ Return:
++ Notes: writes request data
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++
++ dataCopy = min(pReq->DataRemaining, (UINT)pReq->BlockLen);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* set the block data */
++ while(dataCopy) {
++ UINT32 outData = 0;
++ UINT count = 0;
++ if (dataCopy > 4) {
++ outData = ((UINT32)(*(pBuf+0))) |
++ (((UINT32)(*(pBuf+1))) << 8) |
++ (((UINT32)(*(pBuf+2))) << 16) |
++ (((UINT32)(*(pBuf+3))) << 24);
++ WRITE_HOST_REG32(pDevice, HOST_REG_BUFFER_DATA_PORT, outData);
++ dataCopy -= 4;
++ pBuf += 4;
++ } else {
++ for(count = 0; (dataCopy > 0) && (count < 4); count++) {
++ outData |= (*pBuf) << (count*8);
++ pBuf++;
++ dataCopy--;
++ }
++ WRITE_HOST_REG32(pDevice, HOST_REG_BUFFER_DATA_PORT, outData);
++ }
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++ return TRUE;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdTransferRxData - data receive transfer
++ Input: pDevice - device object
++ pReq - transfer request
++ Output:
++ Return:
++ Notes: reads request data
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++
++ dataCopy = min(pReq->DataRemaining, (UINT)pReq->BlockLen);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* set the block data */
++ while(dataCopy) {
++ UINT32 inData;
++ UINT count = 0;
++ inData = READ_HOST_REG32(pDevice, HOST_REG_BUFFER_DATA_PORT);
++ for(count = 0; (dataCopy > 0) && (count < 4); count++) {
++ *pBuf = (inData >> (count*8)) & 0xFF;
++ dataCopy--;
++ pBuf++;
++ }
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ UINT16 temp;
++ UINT16 ints;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++ /* make sure clock is off */
++ ClockStartStop(pDevice, CLOCK_OFF);
++
++ if(pDevice->ShuttingDown) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen HcdRequest returning canceled\n"));
++ return SDIO_STATUS_CANCELED;
++ }
++ /* make sure error ints are disabled */
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ (UINT16)(~HOST_REG_ERROR_INT_STATUS_ALL_ERR));
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ default:
++ case SDREQ_FLAGS_NO_RESP:
++ temp = 0x00;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp = 0x01 |
++ HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp = 0x02;
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ temp = 0x02 | HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE
++ | HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp = 0x03 | HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE
++ | HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE;
++ break;
++ }
++
++ /* start the clock */
++ ClockStartStop(pDevice, CLOCK_ON);
++ /* mask the remove while we are spinning on the CMD ready bits */
++ MaskIrq(pDevice, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY);
++ WAIT_FOR_DAT_CMD_DAT_READY(pDevice, &status);
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetCmdDatLine(pDevice);
++ goto processComplete;
++ }
++ /* clear any error statuses */
++ WRITE_HOST_REG16(pDevice, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ WRITE_HOST_REG16(pDevice, HOST_REG_NORMAL_INT_STATUS, HOST_REG_NORMAL_INT_STATUS_ALL_ERR);
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ /* set the block size register */
++ WRITE_HOST_REG16(pDevice, HOST_REG_BLOCK_SIZE, pReq->BlockLen);
++ /* set block count register */
++ WRITE_HOST_REG16(pDevice, HOST_REG_BLOCK_COUNT, pReq->BlockCount);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PCI Ellen %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ temp |= HOST_REG_COMMAND_REGISTER_DATA_PRESENT;
++ }
++
++ /* set the argument register */
++ WRITE_HOST_REG32(pDevice, HOST_REG_ARGUMENT, pReq->Argument);
++ /* set transfer mode register */
++ WRITE_HOST_REG16(pDevice, HOST_REG_TRANSFER_MODE,
++ ((pReq->BlockCount > 1) ? HOST_REG_TRANSFER_MODE_MULTI_BLOCK:0) |
++ ((pReq->BlockCount > 1) ? HOST_REG_TRANSFER_MODE_BLOCKCOUNT_ENABLE:0) |
++ ((pReq->Flags & SDREQ_FLAGS_AUTO_CMD12) ? HOST_REG_TRANSFER_MODE_AUTOCMD12 : 0) |
++ ((IS_SDREQ_WRITE_DATA(pReq->Flags))?0 : HOST_REG_TRANSFER_MODE_READ));
++
++ /* block cmd timeout errors */
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR & ~HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR);
++
++ /* set command register, make sure it is clear to write */
++ temp |= (pReq->Command << HOST_REG_COMMAND_REGISTER_CMD_SHIFT);
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++
++ if (SDHCD_GET_OPER_CLOCK(pHcd) < pDevice->ClockSpinLimit) {
++ /* clock rate is very low, need to use interrupts here */
++ /* enable error interrupts */
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ UnmaskIrq(pDevice, HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE);
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ TRACE_SIGNAL_DATA_WRITE(pDevice, TRUE);
++ } else {
++ TRACE_SIGNAL_DATA_READ(pDevice, TRUE);
++ }
++ }
++
++ WRITE_HOST_REG16(pDevice, HOST_REG_COMMAND_REGISTER, temp);
++
++ status = SDIO_STATUS_PENDING;
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen using interrupt for command done.*** with data. (clock:%d, ref:%d)\n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ } else {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen using interrupt for command done. (clock:%d, ref:%d) \n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ }
++ return status;
++ } else {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ TRACE_SIGNAL_DATA_WRITE(pDevice, TRUE);
++ } else {
++ TRACE_SIGNAL_DATA_READ(pDevice, TRUE);
++ }
++ }
++ WRITE_HOST_REG16(pDevice, HOST_REG_COMMAND_REGISTER, temp);
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ WAIT_REGISTER32_CHANGE(pDevice,
++ &status,
++ HOST_REG_PRESENT_STATE,
++ HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD,
++ 0, 30000);
++ } else {
++ WAIT_FOR_DAT_CMD_DAT_READY(pDevice, &status);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetCmdDatLine(pDevice);
++ goto processComplete;
++ }
++ }
++
++ /* check for errors */
++ temp = READ_HOST_REG16(pDevice, HOST_REG_ERROR_INT_STATUS);
++ ints = READ_HOST_REG16(pDevice, HOST_REG_NORMAL_INT_STATUS);
++ if (ints & HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE) {
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdRequest clearing possible data timeout errors: 0x%X, ints: 0x%X \n",
++ temp, ints));
++ temp &= ~HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR;
++ }
++ WRITE_HOST_REG16(pDevice, HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE);
++
++ UnmaskIrq(pDevice, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY);
++
++ if (temp != 0) {
++ if (temp & HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR) {
++ /* toggle timeout gpio */
++ TRACE_SIGNAL_DATA_TIMEOUT(pDevice, TRUE);
++ TRACE_SIGNAL_DATA_TIMEOUT(pDevice, FALSE);
++ }
++ status = TranslateSDError(pDevice, temp);
++ /* clear any existing errors - non-synchronized clear */
++ WRITE_HOST_REG16(pDevice, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* reset statemachine, just in case */
++ ResetCmdDatLine(pDevice);
++ } else if (pDevice->Cancel) {
++ status = SDIO_STATUS_CANCELED;
++ } else {
++ /* get the response data for the command */
++ status = GetResponseData(pDevice, pReq);
++ }
++
++
++ /* check for data */
++ if (SDIO_SUCCESS(status) && (pReq->Flags & SDREQ_FLAGS_DATA_TRANS)){
++
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(pHcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (SDIO_SUCCESS(status)) {
++ /* re-enable the cmd timeout error */
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* see if the buffer is ready, it should be */
++ ints = READ_HOST_REG16(pDevice, HOST_REG_NORMAL_INT_STATUS);
++ if (ints & HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE) {
++ WRITE_HOST_REG16(pDevice,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY);
++
++ /* send the initial buffer */
++ /* transfer data */
++ HcdTransferTxData(pDevice, pReq);
++ }
++ /* expecting interrupt */
++ UnmaskIrq(pDevice, HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE
++ | HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE);
++ } else {
++ UnmaskIrq(pDevice, HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE
++ | HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE);
++ }
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PCI Ellen Pending %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++
++ /* return pending */
++ status = SDIO_STATUS_PENDING;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen : Response for Data transfer error :%d n",status));
++ ResetCmdDatLine(pDevice);
++ }
++ }
++
++processComplete:
++
++ if (status != SDIO_STATUS_PENDING) {
++ if (!pDevice->KeepClockOn) {
++ ClockStartStop(pDevice, CLOCK_OFF);
++ }
++ pReq->Status = status;
++
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags)) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ return SDIO_STATUS_PENDING;
++ } else {
++ /* complete the request */
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen Command Done, status:%d \n", status));
++ }
++ pDevice->Cancel = FALSE;
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 command;
++ UINT32 temp;
++
++ if(pDevice->ShuttingDown) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PCI Ellen HcdConfig returning canceled\n"));
++ return SDIO_STATUS_CANCELED;
++ }
++
++ command = GET_SDCONFIG_CMD(pConfig);
++
++ switch (command){
++ case SDCONFIG_GET_WP:
++ /* get write protect */
++ temp = READ_HOST_REG32(pDevice, HOST_REG_PRESENT_STATE);
++ /* if write enabled, set WP value to zero */
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) =
++ (temp & HOST_REG_PRESENT_STATE_WRITE_ENABLED )? 0 : 1;
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ ClockStartStop(pDevice,CLOCK_ON);
++ /* should be at least 80 clocks at our lowest clock setting */
++ status = OSSleep(100);
++ ClockStartStop(pDevice,CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++ UINT8 blockGapControl;
++
++ irqModeFlags = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen: 4 Bit IRQ mode \r\n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pDevice->KeepClockOn = TRUE;
++ blockGapControl = READ_HOST_REG8(pDevice,HOST_REG_BLOCK_GAP);
++ if (irqModeFlags & IRQ_DETECT_MULTI_BLK) {
++ blockGapControl |= HOST_REG_INT_DETECT_AT_BLOCK_GAP;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen: 4 Bit Multi-block IRQ detection enabled \r\n"));
++ } else {
++ // no interrupts between blocks
++ blockGapControl &= ~HOST_REG_INT_DETECT_AT_BLOCK_GAP;
++ }
++ WRITE_HOST_REG8(pDevice,HOST_REG_BLOCK_GAP,blockGapControl);
++ } else {
++ /* in 1 bit mode, the clock can be left off */
++ pDevice->KeepClockOn = FALSE;
++ }
++ }
++ /* enable detection */
++ EnableDisableSDIOIRQ(pDevice,TRUE,FALSE);
++ } else {
++ pDevice->KeepClockOn = FALSE;
++ EnableDisableSDIOIRQ(pDevice,FALSE,FALSE);
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ EnableDisableSDIOIRQ(pDevice,TRUE,FALSE);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pDevice, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PCI Ellen PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ status = SetPowerLevel(pDevice,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask);
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen Local HCD: HcdConfig - bad command: 0x%X\n",
++ command));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetPowerLevel - Set power level of board
++ Input: pDeviceContext - device context
++ On - if true turns power on, else off
++ Level - SLOT_VOLTAGE_MASK level
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SetPowerLevel(PSDHCD_DEVICE pDeviceContext, BOOL On, SLOT_VOLTAGE_MASK Level)
++{
++ UINT8 out;
++ UINT32 capCurrent;
++
++ capCurrent = READ_HOST_REG32(pDeviceContext, HOST_REG_MAX_CURRENT_CAPABILITIES);
++
++ switch (Level) {
++ case SLOT_POWER_3_3V:
++ out = HOST_REG_POWER_CONTROL_VOLT_3_3;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_SHIFT;
++ break;
++ case SLOT_POWER_3_0V:
++ out = HOST_REG_POWER_CONTROL_VOLT_3_0;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_SHIFT;
++ break;
++ case SLOT_POWER_1_8V:
++ out = HOST_REG_POWER_CONTROL_VOLT_1_8;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_SHIFT;
++ break;
++ default:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen SetPowerLevel - illegal power level %d\n",
++ (UINT)Level));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ if (capCurrent != 0) {
++ /* convert to mA and set max current */
++ pDeviceContext->Hcd.MaxSlotCurrent = capCurrent * HOST_REG_MAX_CURRENT_CAPABILITIES_SCALER;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PCI Ellen No Current Caps value for VMask:0x%X, using 200mA \n",
++ Level));
++ /* set a value */
++ pDeviceContext->Hcd.MaxSlotCurrent = 200;
++ }
++
++ if (On) {
++ out |= HOST_REG_POWER_CONTROL_ON;
++ }
++
++ WRITE_HOST_REG8(pDeviceContext, HOST_REG_POWER_CONTROL, out);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetPowerOn - Set power on or off for card
++ Input: pDeviceContext - device context
++ On - if true turns power on, else off
++ Output:
++ Return:
++ Notes: leavse the level alone
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetPowerOn(PSDHCD_DEVICE pDeviceContext, BOOL On)
++{
++ /* non-synchronized read modify write */
++ UINT8 out = READ_HOST_REG8(pDeviceContext, HOST_REG_POWER_CONTROL);
++ if (On) {
++ out |= HOST_REG_POWER_CONTROL_ON;
++ } else {
++ out &= ~HOST_REG_POWER_CONTROL_ON;
++ }
++ WRITE_HOST_REG8(pDeviceContext, HOST_REG_POWER_CONTROL, out);
++ return;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize MMC controller
++ Input: pDeviceContext - device context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ UINT32 caps;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 clockValue;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PCI Ellen HcdInitialize\n"));
++
++ /* reset the device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen HcdInitialize, resetting\n"));
++ WRITE_HOST_REG8(pDeviceContext, HOST_REG_SW_RESET, HOST_REG_SW_RESET_ALL);
++ /* wait for done */
++ while(READ_HOST_REG8(pDeviceContext, HOST_REG_SW_RESET) & HOST_REG_SW_RESET_ALL)
++ ;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen HcdInitialize, reset\n"));
++
++ /* turn off clock */
++ ClockStartStop(pDeviceContext, CLOCK_OFF);
++ /* display version info */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen HcdInitialize: Spec verison: %s, Vendor version: %d\n",
++ (((READ_HOST_REG16(pDeviceContext, HOST_REG_VERSION) & HOST_REG_VERSION_SPEC_VERSION_MASK )== 0)?
++ "SD Host Spec. 1.0": "SD Host Spec. **UNKNOWN**"),
++ (READ_HOST_REG16(pDeviceContext, HOST_REG_VERSION) >> HOST_REG_VERSION_VENDOR_VERSION_SHIFT) &&
++ HOST_REG_VERSION_VENDOR_VERSION_MASK));
++
++ /* get capabilities */
++ caps = READ_HOST_REG32(pDeviceContext, HOST_REG_CAPABILITIES);
++ pDeviceContext->HighSpeed = (caps & HOST_REG_CAPABILITIES_HIGH_SPEED);
++ switch((caps & HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_MASK) >> HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_SHIFT) {
++ case 0x00:
++ pDeviceContext->Hcd.MaxBytesPerBlock = 512;
++ break;
++ case 0x01:
++ pDeviceContext->Hcd.MaxBytesPerBlock = 1024;
++ break;
++ case 0x02:
++ pDeviceContext->Hcd.MaxBytesPerBlock = 2048;
++ break;
++ case 0x03:
++ pDeviceContext->Hcd.MaxBytesPerBlock = 512;
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen invalid buffer length\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ clockValue = (caps & HOST_REG_CAPABILITIES_CLOCK_MASK) >> HOST_REG_CAPABILITIES_CLOCK_SHIFT;
++ if (clockValue != 0) {
++ /* convert to Hz */
++ pDeviceContext->BaseClock = clockValue*1000*1000;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PCI Ellen base clock is zero! (caps:0x%X) \n",caps));
++ /* fall through and see if a default was setup */
++ }
++ if (pDeviceContext->BaseClock == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen invalid base clock setting\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ return status;
++ }
++
++ pDeviceContext->Hcd.MaxClockRate = pDeviceContext->BaseClock;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen Using clock %dHz, max. block %d, high speed %s\n",
++ pDeviceContext->BaseClock, pDeviceContext->Hcd.MaxBytesPerBlock,
++ (pDeviceContext->HighSpeed)? "supported" : "not supported"));
++ /* setup the supported voltages and max current */
++ pDeviceContext->Hcd.SlotVoltageCaps = 0;
++ /* max current is dynamically set based on the desired voltage, see SetPowerLevel() */
++ pDeviceContext->Hcd.MaxSlotCurrent = 0;
++
++ if (caps & HOST_REG_CAPABILITIES_VOLT_1_8) {
++ pDeviceContext->Hcd.SlotVoltageCaps |= SLOT_POWER_1_8V;
++ pDeviceContext->Hcd.SlotVoltagePreferred = SLOT_POWER_1_8V;
++ }
++ if(caps & HOST_REG_CAPABILITIES_VOLT_3_0) {
++ pDeviceContext->Hcd.SlotVoltageCaps |= SLOT_POWER_3_0V;
++ pDeviceContext->Hcd.SlotVoltagePreferred = SLOT_POWER_3_0V;
++ }
++ if(caps & HOST_REG_CAPABILITIES_VOLT_3_3) {
++ pDeviceContext->Hcd.SlotVoltageCaps |= SLOT_POWER_3_3V;
++ pDeviceContext->Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen HcdInitialize: caps: 0x%X, SlotVoltageCaps: 0x%X, MaxSlotCurrent: 0x%X\n",
++ (UINT)caps, (UINT)pDeviceContext->Hcd.SlotVoltageCaps, (UINT)pDeviceContext->Hcd.MaxSlotCurrent));
++
++ /* set the default timeout */
++ WRITE_HOST_REG8(pDeviceContext, HOST_REG_TIMEOUT_CONTROL, pDeviceContext->TimeOut);
++
++ /* clear any existing errors */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_NORMAL_INT_STATUS, HOST_REG_NORMAL_INT_STATUS_ALL_ERR);
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* enable error interrupts */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_ERR_STATUS_ENABLE, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++//?? WRITE_HOST_REG16(pDeviceContext, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++//?? HOST_REG_ERROR_INT_STATUS_ALL_ERR & ~HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR);
++ /* leave disabled for now */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ (UINT16)~HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* enble statuses */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_INT_STATUS_ENABLE, HOST_REG_INT_STATUS_ALL);
++
++
++ /* interrupts will get enabled by the caller after all of the OS dependent work is done */
++ /*UnmaskIrq(pDeviceContext, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY);*/
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCI Ellen HcdInitialize\n"));
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate controller
++ Input: pDeviceContext - context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PCI Ellen HcdDeinitialize\n"));
++ pDeviceContext->KeepClockOn = FALSE;
++ MaskIrq(pDeviceContext, HOST_REG_INT_STATUS_ALL);
++ pDeviceContext->ShuttingDown = TRUE;
++ /* disable error interrupts */
++ /* clear any existing errors */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* disable error interrupts */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ (UINT16)~HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_ERR_STATUS_ENABLE,
++ (UINT16)~HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ ClockStartStop(pDeviceContext, CLOCK_OFF);
++ SetPowerOn(pDeviceContext, FALSE);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCI Ellen HcdDeinitialize\n"));
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdSDInterrupt - process controller interrupt
++ Input: pDeviceContext - context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDeviceContext)
++{
++ UINT16 ints;
++ UINT16 errors;
++ UINT16 enables;
++ UINT16 statenables;
++ PSDREQUEST pReq;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("+SDIO PCI Ellen HcdSDInterrupt Int handler \n"));
++
++
++ ints = READ_HOST_REG16(pDeviceContext, HOST_REG_NORMAL_INT_STATUS);
++ errors = READ_HOST_REG16(pDeviceContext, HOST_REG_ERROR_INT_STATUS);
++
++ if ((ints == 0) && (errors == 0)) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO PCI Ellen HcdSDInterrupt False Interrupt! \n"));
++ return FALSE;
++ }
++ enables = READ_HOST_REG16(pDeviceContext, HOST_REG_INT_SIGNAL_ENABLE);
++ statenables = READ_HOST_REG16(pDeviceContext, HOST_REG_INT_STATUS_ENABLE);
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt, ints: 0x%X errors: 0x%x, sigenables: 0x%X, statenable: 0x%X\n",
++ (UINT)ints, (UINT)errors, (UINT)enables, (UINT)statenables));
++ /* clear any error statuses */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_ERROR_INT_STATUS, errors);
++
++ pReq = GET_CURRENT_REQUEST(&pDeviceContext->Hcd);
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE) {
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt clearing possible data timeout errors: 0x%X \n",
++ errors));
++ errors &= ~HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR;
++ }
++ /* handle the error cases first */
++ if (errors != 0) {
++ if (errors & HOST_REG_ERROR_INT_STATUS_VENDOR_MASK) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt vendor error 0x%X: \n",
++ (UINT)((errors & HOST_REG_ERROR_INT_STATUS_VENDOR_MASK) >>
++ HOST_REG_ERROR_INT_STATUS_VENDOR_SHIFT)));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_AUTOCMD12ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt auto cmd12 error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_CURRENTLIMITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt current limit error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_DATAENDBITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt data end bit error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_DATACRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt data CRC error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt data timeout error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_CMDINDEXERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt CMD index error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_CMDENDBITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt CMD end bit error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_CRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt CRC error\n"));
++ }
++ if (errors & HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR) {
++ /* toggle timeout gpio */
++ TRACE_SIGNAL_DATA_TIMEOUT(pDeviceContext, TRUE);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen HcdSDInterrupt CMD timeout error\n"));
++ TRACE_SIGNAL_DATA_TIMEOUT(pDeviceContext, FALSE);
++ }
++ if (ints & HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE) {
++ /* disable SDIO interrupt */
++ EnableDisableSDIOIRQ(pDeviceContext,FALSE,TRUE);
++ }
++ /* process insert/remove even on error conditions */
++ if (ints &
++ (HOST_REG_INT_STATUS_CARD_INSERT_ENABLE | HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE)){
++ /* card was inserted or removed, clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_INT_STATUS_CARD_INSERT_ENABLE |
++ HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE);
++ enables = MaskIrqFromIsr(pDeviceContext, HOST_REG_INT_STATUS_ALL);
++ QueueEventResponse(pDeviceContext, WORK_ITEM_CARD_DETECT);
++ }
++
++ } else {
++ /* only look at ints that are enabled */
++ ints &= enables;
++
++ //DBG_PRINT(SDDBG_TRACE, ("SDIO PCI Ellen ints: 0x%X errors: 0x%x, sigenables: 0x%X, statenable: 0x%X\n",
++ // (UINT)ints, (UINT)errors, (UINT)enables, (UINT)statenables));
++ if ((pDeviceContext->CardInserted) &&
++ (ints & HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE)) {
++ /* SD card interrupt*/
++ /* disable the interrupt, the user must clear the interrupt */
++ EnableDisableSDIOIRQ(pDeviceContext,FALSE,TRUE);
++ QueueEventResponse(pDeviceContext, WORK_ITEM_SDIO_IRQ);
++ /* continue looking for other interrupt causes */
++ } else if (ints & HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE) {
++ /* disable bogus interrupt */
++ EnableDisableSDIOIRQ(pDeviceContext,FALSE,TRUE);
++ }
++
++ if (ints &
++ (HOST_REG_INT_STATUS_CARD_INSERT_ENABLE | HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE)){
++ /* card was inserted or removed, clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_INT_STATUS_CARD_INSERT_ENABLE |
++ HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE);
++ enables = MaskIrqFromIsr(pDeviceContext, HOST_REG_INT_STATUS_ALL);
++ QueueEventResponse(pDeviceContext, WORK_ITEM_CARD_DETECT);
++ return TRUE;
++ }
++
++ if (pDeviceContext->CardInserted && (pReq != NULL)) {
++ if (ints & HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE) {
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE);
++ MaskIrqFromIsr(pDeviceContext, HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE);
++ /* get the response data for the command */
++ status = GetResponseData(pDeviceContext, pReq);
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt command complete, status: %d\n",status));
++
++ if (SDIO_SUCCESS(status) && (pReq->Flags & SDREQ_FLAGS_DATA_TRANS)){
++
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pDeviceContext->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ /* re-enable the cmd timeout error */
++ WRITE_HOST_REG16(pDeviceContext, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt status %d\n", status));
++ if (SDIO_SUCCESS(status)) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* expecting interrupt */
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt unmasking write\n"));
++ UnmaskIrqFromIsr(pDeviceContext, HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE
++ | HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE);
++ } else {
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt unmasking read\n"));
++ UnmaskIrqFromIsr(pDeviceContext, HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE
++ | HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE);
++ }
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PCI Ellen Pending from ISR %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ status = SDIO_STATUS_PENDING;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI Ellen : Response for Data transfer error :%d n",status));
++ ResetCmdDatLine(pDeviceContext);
++ }
++ } else {
++ status = SDIO_STATUS_SUCCESS;
++ }
++ } else {
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* TX processing */
++ if (ints &
++ (HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY)) {
++ /* clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY);
++ if (pReq->DataRemaining > 0) {
++ /* transfer data */
++ HcdTransferTxData(pDeviceContext, pReq);
++ return TRUE;
++ } else {
++ /* re-read the interrupt status message to allow us to catch the
++ transfer complete in one interrupt */
++ ints = READ_HOST_REG16(pDeviceContext, HOST_REG_NORMAL_INT_STATUS);
++ ints &= enables;
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt re-enable \n"));
++ }
++ }
++ } else {
++ /* RX processing */
++ if (ints &
++ (HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY)) {
++ /* clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY );
++ /* unload fifo */
++ HcdTransferRxData(pDeviceContext, pReq);
++ if (pReq->DataRemaining > 0) {
++ return TRUE;
++ }
++ }
++ }
++ }
++ }
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE) {
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt Transfer done \n"));
++ /* clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE);
++ /* if we get here without an error, we are done with the read
++ * data operation */
++ status = SDIO_STATUS_SUCCESS;
++ }
++ }
++ }
++ }
++ if (errors) {
++ /* alter status based on error */
++ status = TranslateSDError(pDeviceContext, errors);
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ TRACE_SIGNAL_DATA_WRITE(pDeviceContext, FALSE);
++ } else {
++ TRACE_SIGNAL_DATA_READ(pDeviceContext, FALSE);
++ }
++ }
++ /* turn off interrupts and clock */
++ MaskIrqFromIsr(pDeviceContext,
++ ~(HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY |
++ HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE) );
++
++ if (errors) {
++ /* reset statemachine */
++ ResetCmdDatLine(pDeviceContext);
++ }
++
++ if (!pDeviceContext->KeepClockOn) {
++ ClockStartStop(pDeviceContext, CLOCK_OFF);
++ }
++ if (pDeviceContext->CardInserted && (pReq != NULL)) {
++ /* set the status */
++ pReq->Status = status;
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pDeviceContext, WORK_ITEM_IO_COMPLETE);
++ } else {
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PCI Ellen HcdSDInterrupt, no request to report: status %d \n",
++ status));
++ }
++ }
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("-SDIO PCI Ellen HcdSDInterrupt Int handler \n"));
++ return TRUE;
++}
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,185 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_linux.h
++
++ at abstract: include file for Tokyo Electron PCI Ellen host controller, linux dependent code
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++
++
++#include <asm/irq.h>
++
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++#define CARD_INSERT_POLARITY FALSE
++#define WP_POLARITY TRUE
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++/* debounce delay for slot */
++#define SD_SLOT_DEBOUNCE_MS 500
++
++/* the config space slot number and start for SD host */
++#define PCI_CONFIG_SLOT 0x40
++#define GET_SLOT_COUNT(config)\
++ ((((config)>>4)& 0x7) +1)
++#define GET_SLOT_FIRST(config)\
++ ((config) & 0x7)
++
++/* device base name */
++#define SDIO_BD_BASE "sdiobd"
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef enum _SDHCD_TYPE {
++ TYPE_CLASS, /* standard class device */
++ TYPE_PCIELLEN, /* Tokuo Electron PCI Ellen card */
++}SDHCD_TYPE, *PSDHCD_TYPE;
++
++/* device data*/
++typedef struct _SDHCD_DEVICE {
++ struct pci_dev *pBusDevice; /* our device registered with bus driver */
++ SDLIST List; /* linked list */
++ SDHCD Hcd; /* HCD description for bus driver */
++ char DeviceName[SDHCD_MAX_DEVICE_NAME]; /* our chr device name */
++ SDHCD_MEMORY Address; /* memory address of this device */
++ spinlock_t AddressSpinlock; /* use to protect reghisters when needed */
++ SDHCD_MEMORY ControlRegs; /* memory address of shared control registers */
++ SDHCD_TYPE Type; /* type of this device */
++ UINT8 InitStateMask;
++#define SDIO_BAR_MAPPED 0x01
++#define SDIO_LAST_CONTROL_BAR_MAPPED 0x02 /* set on device that will unmap the shared control registers */
++#define SDIO_IRQ_INTERRUPT_INIT 0x04
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x40
++#define TIMER_INIT 0x80
++ spinlock_t Lock; /* lock against the ISR */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel;
++ BOOL ShuttingDown; /* indicates shut down of HCD) */
++ BOOL HighSpeed; /* device supports high speed, 25-50 Mhz */
++ UINT32 BaseClock; /* base clock in hz */
++ UINT32 TimeOut; /* timeout setting */
++ UINT32 ClockSpinLimit; /* clock limit for command spin loops */
++ BOOL KeepClockOn;
++ struct work_struct iocomplete_work; /* work item definintions */
++ struct work_struct carddetect_work; /* work item definintions */
++ struct work_struct sdioirq_work; /* work item definintions */
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++
++#define READ_HOST_REG32(pDevice, OFFSET) \
++ _READ_DWORD_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG32(pDevice, OFFSET, VALUE) \
++ _WRITE_DWORD_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET),(VALUE))
++#define READ_HOST_REG16(pDevice, OFFSET) \
++ _READ_WORD_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG16(pDevice, OFFSET, VALUE) \
++ _WRITE_WORD_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET),(VALUE))
++#define READ_HOST_REG8(pDevice, OFFSET) \
++ _READ_BYTE_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG8(pDevice, OFFSET, VALUE) \
++ _WRITE_BYTE_REG((((UINT32)((pDevice)->Address.pMapped))) + (OFFSET),(VALUE))
++
++#define READ_CONTROL_REG32(pDevice, OFFSET) \
++ _READ_DWORD_REG((((UINT32)((pDevice)->ControlRegs.pMapped))) + (OFFSET))
++#define WRITE_CONTROL_REG32(pDevice, OFFSET, VALUE) \
++ _WRITE_DWORD_REG((((UINT32)((pDevice)->ControlRegs.pMapped))) + (OFFSET),(VALUE))
++#define READ_CONTROL_REG16(pDevice, OFFSET) \
++ _READ_WORD_REG((((UINT32)((pDevice)->ControlRegs.pMapped))) + (OFFSET))
++#define WRITE_CONTROL_REG16(pDevice, OFFSET, VALUE) \
++ _WRITE_WORD_REG((((UINT32)((pDevice)->ControlRegs.pMapped))) + (OFFSET),(VALUE))
++
++/* PLX 9030 control registers */
++#define INTCSR 0x4C
++#define INTCSR_LINTi1ENABLE (1 << 0)
++#define INTCSR_LINTi1STATUS (1 << 2)
++#define INTCSR_LINTi2ENABLE (1 << 3)
++#define INTCSR_LINTi2STATUS (1 << 5)
++#define INTCSR_PCIINTENABLE (1 << 6)
++
++#define GPIOCTRL 0x54
++#define GPIO8_PIN_DIRECTION (1 << 25)
++#define GPIO8_DATA_MASK (1 << 26)
++#define GPIO3_PIN_SELECT (1 << 9)
++#define GPIO3_PIN_DIRECTION (1 << 10)
++#define GPIO3_DATA_MASK (1 << 11)
++#define GPIO2_PIN_SELECT (1 << 6)
++#define GPIO2_PIN_DIRECTION (1 << 7)
++#define GPIO2_DATA_MASK (1 << 8)
++#define GPIO4_PIN_SELECT (1 << 12)
++#define GPIO4_PIN_DIRECTION (1 << 13)
++#define GPIO4_DATA_MASK (1 << 14)
++
++#define GPIO_CONTROL(pDevice, on, GpioMask) \
++{ \
++ UINT32 temp; \
++ temp = READ_CONTROL_REG32((pDevice),GPIOCTRL); \
++ if (on) temp |= (GpioMask); else temp &= ~(GpioMask); \
++ WRITE_CONTROL_REG32((pDevice),GPIOCTRL, temp); \
++}
++
++//??#define TRACE_SIGNAL_DATA_WRITE(pDevice, on) GPIO_CONTROL((pDevice),(on),GPIO8_DATA_MASK)
++//??#define TRACE_SIGNAL_DATA_READ(pDevice, on) GPIO_CONTROL((pDevice),(on),GPIO2_DATA_MASK)
++//??#define TRACE_SIGNAL_DATA_ISR(pDevice, on) GPIO_CONTROL((pDevice),(on),GPIO4_DATA_MASK)
++//??#define TRACE_SIGNAL_DATA_IOCOMP(pDevice, on) GPIO_CONTROL((pDevice),(on),GPIO3_DATA_MASK)
++#define TRACE_SIGNAL_DATA_WRITE(pDevice, on)
++#define TRACE_SIGNAL_DATA_READ(pDevice, on)
++#define TRACE_SIGNAL_DATA_ISR(pDevice, on)
++#define TRACE_SIGNAL_DATA_IOCOMP(pDevice, on)
++#define TRACE_SIGNAL_DATA_TIMEOUT(pDevice, on) GPIO_CONTROL((pDevice),(on),GPIO3_DATA_MASK)
++
++/* prototypes */
++#endif /* __SDIO_HCD_LINUX_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_hcd_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,781 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Linux Tokyo Electron PCI Ellen SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++
++#define DBG_DECLARE 3;
++#include <linux/sdio/ctsystem.h>
++
++#include "sdio_pciellen_hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include <linux/pci.h>
++
++#define DESCRIPTION "SDIO Tokyo Electron PCI Ellen HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++static SYSTEM_STATUS Probe(struct pci_dev *pPCIdevice, const struct pci_device_id *pId);
++static void Remove(struct pci_dev *pPCIdevice);
++static int MapAddress(struct pci_dev *pPCIdevice, char *pName, UINT8 bar, PSDHCD_MEMORY pAddress);
++static void UnmapAddress(PSDHCD_MEMORY pMap);
++static void RemoveDevice(struct pci_dev *pPCIdevice, PSDHCD_DRIVER_CONTEXT pHcdContext);
++static SDIO_STATUS InitEllen(PSDHCD_DEVICE pDeviceContext);
++static void GetDefaults(PSDHCD_DEVICE pDeviceContext);
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r);
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++static void hcd_carddetect_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++#define DEFAULT_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | \
++ SDHCD_ATTRIB_BUS_4BIT | \
++ SDHCD_ATTRIB_MULTI_BLK_IRQ | \
++ SDHCD_ATTRIB_AUTO_CMD12 | \
++ SDHCD_ATTRIB_POWER_SWITCH )
++
++static UINT32 hcdattributes = DEFAULT_ATTRIBUTES;
++module_param(hcdattributes, int, 0644);
++MODULE_PARM_DESC(hcdattributes, "PCIELLEN Attributes");
++static INT BaseClock = 0;
++module_param(BaseClock, int, 0444);
++MODULE_PARM_DESC(BaseClock, "BaseClock Hz when not present in configuration");
++static UINT32 timeout = HOST_REG_TIMEOUT_CONTROL_DEFAULT;
++module_param(timeout, int, 0644);
++MODULE_PARM_DESC(timeout, "PCIELLEN timeout flags");
++static UINT32 ClockSpinLimit = HCD_COMMAND_MIN_POLLING_CLOCK;
++module_param(ClockSpinLimit, int, 0644);
++MODULE_PARM_DESC(ClockSpinLimit, "PCIELLEN command clock spin time");
++
++
++
++
++/* the driver context data */
++static SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .DeviceCount = 0,
++};
++
++#define PCI_CLASS_SYSTEM_SDIO 0x0805
++/* PCI devices supported */
++static const struct pci_device_id pci_ids [] = {
++ {
++ .vendor = 0x1679, .device = 0x3000,
++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
++ .driver_data = (unsigned long) &HcdContext,
++ },
++ {
++ PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDIO << 8, 0xFFFFFF00),
++ .driver_data = (unsigned long) &HcdContext,
++ },
++ { /* end: all zeroes */ }
++};
++MODULE_DEVICE_TABLE (pci, pci_ids);
++
++/* tell PCI bus driver about us */
++static struct pci_driver sdio_pci_driver = {
++ .name = "sdio_pciellenhcd",
++ .id_table = pci_ids,
++
++ .probe = Probe,
++ .remove = Remove,
++
++#ifdef CONFIG_PM
++ .suspend = NULL,
++ .resume = NULL,
++#endif
++};
++
++
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++static SYSTEM_STATUS Probe(struct pci_dev *pPCIdevice, const struct pci_device_id *pId)
++{
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHcdContext;
++ PSDHCD_DEVICE pDeviceContext = NULL;
++ PSDHCD_DEVICE pLastDeviceContext;
++ int ii;
++ int count;
++ int firstBar;
++ UINT8 config;
++ SDHCD_TYPE type = TYPE_CLASS;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN HCD: Probe - probing for new device\n"));
++ if ((pId == NULL) || (pId->driver_data == 0)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN HCD: Probe - no device\n"));
++ return -EINVAL;
++ }
++ pHcdContext = (PSDHCD_DRIVER_CONTEXT)pId->driver_data;
++
++ if (pci_enable_device(pPCIdevice) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN HCD: Probe - failed to enable device\n"));
++ return -ENODEV;
++ }
++ if ((pId->vendor == pci_ids[0].vendor) && (pId->device == pci_ids[0].device)) {
++ type = TYPE_PCIELLEN;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN HCD: Probe - setting PCI Ellen type\n"));
++ }
++ /* get the number of slots supported and the initial BAR for it */
++ pci_read_config_byte(pPCIdevice, PCI_CONFIG_SLOT, &config);
++ count = GET_SLOT_COUNT(config);
++ firstBar = GET_SLOT_FIRST(config);
++ if (type == TYPE_PCIELLEN) {
++ /* move the first bar to the right start place */
++ firstBar = 2;
++ }
++ if (count > 0) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCI BD: Probe - slot count: %d, first BAR: %d\n", count, firstBar));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI BD: Probe - no slots defined, first BAR: %d\n", firstBar));
++ pci_disable_device(pPCIdevice);
++ return -ENODEV;
++ }
++
++ /* create a device for each slot that we have */
++ for(ii = 0; ii < count; ii++, firstBar++) {
++ pLastDeviceContext = pDeviceContext;
++ /* allocate a device context for this new device */
++ pDeviceContext = (PSDHCD_DEVICE)KernelAlloc(sizeof(SDHCD_DEVICE));
++ if (pDeviceContext == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCI BD: Probe - no memory for device context\n"));
++ err = -ENOMEM;
++ break;
++ }
++ ZERO_POBJECT(pDeviceContext);
++ SDLIST_INIT(&pDeviceContext->List);
++ pDeviceContext->Type = type;
++ pDeviceContext->pBusDevice = pPCIdevice;
++ spin_lock_init(&pDeviceContext->Lock);
++ spin_lock_init(&pDeviceContext->AddressSpinlock);
++
++ SET_SDIO_STACK_VERSION(&pDeviceContext->Hcd);
++ pDeviceContext->Hcd.pName = (PTEXT)KernelAlloc(SDHCD_MAX_DEVICE_NAME+1);
++ snprintf(pDeviceContext->Hcd.pName, SDHCD_MAX_DEVICE_NAME, SDIO_BD_BASE"%i:%i",
++ pHcdContext->DeviceCount++, ii);
++ pDeviceContext->Hcd.Attributes = hcdattributes;
++ pDeviceContext->Hcd.MaxBlocksPerTrans = SDIO_SD_MAX_BLOCKS;
++ pDeviceContext->Hcd.pContext = pDeviceContext;
++ pDeviceContext->Hcd.pRequest = HcdRequest;
++ pDeviceContext->Hcd.pConfigure = HcdConfig;
++ pDeviceContext->Hcd.pDevice = &pPCIdevice->dev;
++ pDeviceContext->Hcd.pModule = THIS_MODULE;
++ pDeviceContext->BaseClock = BaseClock;
++ pDeviceContext->TimeOut = timeout;
++ pDeviceContext->ClockSpinLimit = ClockSpinLimit;
++ /* add device to our list of devices */
++ /* protect the devicelist */
++ if (!SDIO_SUCCESS(status = SemaphorePendInterruptable(&pHcdContext->DeviceListSem))) {
++ break;; /* wait interrupted */
++ }
++ SDListInsertTail(&pHcdContext->DeviceList, &pDeviceContext->List);
++ SemaphorePost(&pHcdContext->DeviceListSem);
++
++ /* map the slots memory BAR */
++ status = MapAddress(pPCIdevice, pDeviceContext->DeviceName,
++ (UINT8)firstBar, &pDeviceContext->Address);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO PCIELLEN HCD: Probe - failed to map device memory address %s 0x%X, status %d\n",
++ pDeviceContext->DeviceName, (UINT)pci_resource_start(pPCIdevice, firstBar),
++ status));
++ break;
++ }
++ pDeviceContext->InitStateMask |= SDIO_BAR_MAPPED;
++
++ if (type == TYPE_PCIELLEN) {
++ if (pLastDeviceContext == NULL) {
++ /* map the slots control register BAR */
++ status = MapAddress(pPCIdevice, pDeviceContext->DeviceName,
++ (UINT8)0, &pDeviceContext->ControlRegs);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO PCIELLEN HCD: Probe - failed to map device control address %s 0x%X, status %d\n",
++ pDeviceContext->DeviceName, (UINT)pci_resource_start(pPCIdevice, 0),
++ status));
++ break;
++ }
++ } else {
++ /* copy the prior mapping */
++ pDeviceContext->ControlRegs = pLastDeviceContext->ControlRegs;
++ }
++ if ((ii+1) == count) {
++ /* mark last one */
++ pDeviceContext->InitStateMask |= SDIO_LAST_CONTROL_BAR_MAPPED;
++ }
++ }
++ /* initialize work items */
++ INIT_WORK(&(pDeviceContext->iocomplete_work), hcd_iocomplete_wqueue_handler, pDeviceContext);
++ INIT_WORK(&(pDeviceContext->carddetect_work), hcd_carddetect_wqueue_handler, pDeviceContext);
++ INIT_WORK(&(pDeviceContext->sdioirq_work), hcd_sdioirq_wqueue_handler, pDeviceContext);
++
++ /* map the controller interrupt, we map it to each device.
++ Interrupts can be called from this point on */
++ err = request_irq(pPCIdevice->irq, hcd_sdio_irq, SA_SHIRQ,
++ pDeviceContext->DeviceName, pDeviceContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN - probe, unable to map interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++ pDeviceContext->InitStateMask |= SDIO_IRQ_INTERRUPT_INIT;
++
++ if (!SDIO_SUCCESS((status = HcdInitialize(pDeviceContext)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN Probe - failed to init HW, status =%d\n",status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++ pDeviceContext->InitStateMask |= SDHC_HW_INIT;
++
++ /* register with the SDIO bus driver */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pDeviceContext->Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN Probe - failed to register with host, status =%d\n",status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++ pDeviceContext->InitStateMask |= SDHC_REGISTERED;
++
++ /* queue a work item to check for a card present at start up
++ this call will unmask the insert/remove interrupts */
++ QueueEventResponse(pDeviceContext, WORK_ITEM_CARD_DETECT);
++ }
++
++
++ if ((err < 0) || (!SDIO_SUCCESS(status))){
++ pHcdContext->DeviceCount--;
++ RemoveDevice(pPCIdevice, pHcdContext);
++ } else {
++
++ if (type == TYPE_PCIELLEN) {
++ InitEllen(pDeviceContext);
++ }
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN Probe - HCD ready! \n"));
++ }
++ return 0;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++static void Remove(struct pci_dev *pPCIdevice)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PCIELLEN HCD: Remove - removing device\n"));
++
++ RemoveDevice(pPCIdevice, pHcdContext);
++ pHcdContext->DeviceCount--;
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCIELLEN HCD: Remove\n"));
++ return;
++}
++
++/*
++ * RemoveDevice - remove all devices associated with bus device
++*/
++static void RemoveDevice(struct pci_dev *pPCIdevice, PSDHCD_DRIVER_CONTEXT pHcdContext)
++{
++ PSDHCD_DEVICE pDeviceContext;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PCIELLEN HCD: RemoveDevice\n"));
++
++ /* protect the devicelist */
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pHcdContext->DeviceListSem))) {
++ return; /* wait interrupted */
++ }
++
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pHcdContext->DeviceList, pDeviceContext, SDHCD_DEVICE, List)
++ if (pDeviceContext->pBusDevice == pPCIdevice) {
++ if (pDeviceContext->InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pDeviceContext);
++ }
++
++ if (pDeviceContext->InitStateMask & SDHC_REGISTERED) {
++ SDIO_UnregisterHostController(&pDeviceContext->Hcd);
++ }
++
++ /* wait for any of our work items to run */
++ flush_scheduled_work();
++
++ if (pDeviceContext->InitStateMask & SDIO_IRQ_INTERRUPT_INIT) {
++ free_irq(pPCIdevice->irq, pDeviceContext);
++ }
++
++ if (pDeviceContext->InitStateMask & SDIO_BAR_MAPPED) {
++ UnmapAddress(&pDeviceContext->Address);
++ }
++
++ if (pDeviceContext->InitStateMask & SDIO_LAST_CONTROL_BAR_MAPPED) {
++ UnmapAddress(&pDeviceContext->ControlRegs);
++ }
++ if (pDeviceContext->Hcd.pName != NULL) {
++ KernelFree(pDeviceContext->Hcd.pName);
++ pDeviceContext->Hcd.pName = NULL;
++ }
++ KernelFree(pDeviceContext);
++ }
++ SDITERATE_END;
++ SemaphorePost(&pHcdContext->DeviceListSem);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCIELLEN HCD: RemoveDevice\n"));
++}
++
++/*
++ * MapAddress - sets up the address for a given BAR
++*/
++static int MapAddress(struct pci_dev *pPCIdevice, char *pName, UINT8 bar, PSDHCD_MEMORY pAddress)
++{
++ if (pci_resource_flags(pPCIdevice, bar) & PCI_BASE_ADDRESS_SPACE ) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PCIELLEN HCD: MapAddress, port I/O not supported\n"));
++ return -ENOMEM;
++ }
++ pAddress->Raw = pci_resource_start(pPCIdevice, bar);
++ pAddress->Length = pci_resource_len(pPCIdevice, bar);
++ if (!request_mem_region (pAddress->Raw, pAddress->Length, pName)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PCIELLEN HCD: MapAddress - memory in use: 0x%X(0x%X)\n",
++ (UINT)pAddress->Raw, (UINT)pAddress->Length));
++ return -EBUSY;
++ }
++ pAddress->pMapped = ioremap_nocache(pAddress->Raw, pAddress->Length);
++ if (pAddress->pMapped == NULL) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PCIELLEN HCD: MapAddress - unable to map memory\n"));
++ /* cleanup region */
++ release_mem_region (pAddress->Raw, pAddress->Length);
++ return -EFAULT;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN HCD: MapAddress - mapped memory: 0x%X(0x%X) to 0x%X\n",
++ (UINT)pAddress->Raw, (UINT)pAddress->Length, (UINT)pAddress->pMapped));
++ return 0;
++}
++
++
++
++/*
++ * UnmapAddress - unmaps the address
++*/
++static void UnmapAddress(PSDHCD_MEMORY pAddress) {
++ iounmap(pAddress->pMapped);
++ release_mem_region(pAddress->Raw, pAddress->Length);
++ pAddress->pMapped = NULL;
++}
++
++/*
++ * InitEllen - initialize the Ellen card control registers
++ *
++*/
++static SDIO_STATUS InitEllen(PSDHCD_DEVICE pDeviceContext)
++{
++ UINT32 temp = READ_CONTROL_REG16(pDeviceContext, INTCSR);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN HCD: InitEllen INTCSR - 0x%X\n", (UINT)temp));
++
++ WRITE_CONTROL_REG16(pDeviceContext, INTCSR,
++ (UINT16)temp | INTCSR_LINTi1ENABLE | INTCSR_LINTi2ENABLE | INTCSR_PCIINTENABLE);
++
++ temp = READ_CONTROL_REG32((pDeviceContext),GPIOCTRL);
++ /* set GPIO 2,3 and 8 as output */
++ temp &= ~(GPIO3_PIN_SELECT | GPIO2_PIN_SELECT | GPIO4_PIN_SELECT);
++ temp |= (GPIO8_PIN_DIRECTION | GPIO3_PIN_DIRECTION | GPIO2_PIN_DIRECTION | GPIO4_PIN_DIRECTION);
++ WRITE_CONTROL_REG32((pDeviceContext),GPIOCTRL, temp);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN HCD: InitEllen GPIOCTRL - 0x%X\n", (UINT)temp));
++ TRACE_SIGNAL_DATA_WRITE(pDeviceContext, FALSE);
++ TRACE_SIGNAL_DATA_READ(pDeviceContext, FALSE);
++ TRACE_SIGNAL_DATA_ISR(pDeviceContext, FALSE);
++ TRACE_SIGNAL_DATA_IOCOMP(pDeviceContext, FALSE);
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_DEVICE pDeviceContext, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ if (pDeviceContext->ShuttingDown) {
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ work = &pDeviceContext->iocomplete_work;
++ break;
++ case WORK_ITEM_CARD_DETECT:
++ work = &pDeviceContext->carddetect_work;
++ break;
++ case WORK_ITEM_SDIO_IRQ:
++ work = &pDeviceContext->sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_PENDING;
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ if (!pDeviceContext->ShuttingDown) {
++ TRACE_SIGNAL_DATA_IOCOMP(pDeviceContext, TRUE);
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++ TRACE_SIGNAL_DATA_IOCOMP(pDeviceContext, FALSE);
++ }
++}
++
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ HCD_EVENT event;
++ volatile UINT32 temp;
++
++ event = EVENT_HCD_NOP;
++
++ DBG_PRINT(SDDBG_TRACE, ("+ SDIO PCIELLEN Card Detect Work Item \n"));
++ if (pDeviceContext->ShuttingDown) {
++ return;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PCIELLEN Card Detect Delaying to debounce card... \n"));
++ /* sleep for slot debounce if there is no card */
++ OSSleep(SD_SLOT_DEBOUNCE_MS);
++
++ /* wait for stable */
++ while(!(temp = READ_HOST_REG32(pDeviceContext, HOST_REG_PRESENT_STATE))&
++ HOST_REG_PRESENT_STATE_CARD_STATE_STABLE) {
++ ;
++ }
++
++ if (pDeviceContext->CardInserted) {
++ /* look for removal */
++ if (!(temp & HOST_REG_PRESENT_STATE_CARD_INSERTED)) {
++ /* card not present */
++ event = EVENT_HCD_DETACH;
++ pDeviceContext->CardInserted = FALSE;
++ pDeviceContext->KeepClockOn = FALSE;
++ /* turn the power off */
++ SetPowerOn(pDeviceContext, FALSE);
++ MaskIrq(pDeviceContext, HOST_REG_INT_STATUS_ALL);
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("SDIO PCIELLEN Card Detect REMOVE\n"));
++ }
++ } else {
++ /* look for insert */
++ if (temp & HOST_REG_PRESENT_STATE_CARD_INSERTED) {
++ /* card present */
++ event = EVENT_HCD_ATTACH;
++ pDeviceContext->CardInserted = TRUE;
++ GetDefaults(pDeviceContext);
++
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("SDIO PCIELLEN Card Detect INSERT\n"));
++ }
++ }
++ /* clear interrupt */
++ WRITE_HOST_REG16(pDeviceContext,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_INT_STATUS_CARD_INSERT_ENABLE |
++ HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE);
++ UnmaskIrq(pDeviceContext, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY);
++
++ if (event != EVENT_HCD_NOP) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, event);
++ }
++
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("- SDIO PCIELLEN Card Detect Work Item \n"));
++}
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PCIELLEN: hcd_sdioirq_wqueue_handler \n"));
++ if (!pDeviceContext->ShuttingDown) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++ }
++}
++
++
++/* SDIO interrupt request */
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r)
++{
++ irqreturn_t retStat;
++ UINT16 intStat;
++
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PCIELLEN SDIO IRQ \n"));
++
++ if (((PSDHCD_DEVICE)context)->Type == TYPE_PCIELLEN) {
++ /* see if we interrupted */
++ intStat = READ_CONTROL_REG16((PSDHCD_DEVICE)context, INTCSR);
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("intStat: 0x%X\n", (UINT)intStat));
++ if (!(intStat & (INTCSR_LINTi1STATUS | INTCSR_LINTi2STATUS))) {
++ return IRQ_NONE;
++ }
++ }
++
++ TRACE_SIGNAL_DATA_ISR((PSDHCD_DEVICE)context, TRUE);
++ /* call OS independent ISR */
++ if (HcdSDInterrupt((PSDHCD_DEVICE)context)) {
++ retStat = IRQ_HANDLED;
++ } else {
++ retStat = IRQ_NONE;
++ }
++ TRACE_SIGNAL_DATA_ISR((PSDHCD_DEVICE)context, FALSE);
++ return retStat;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskIrq - Unmask SD interrupts
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 UnmaskIrq(PSDHCD_DEVICE pDevice, UINT32 Mask)
++{
++ UINT16 ints;
++ /* protected read-modify-write */
++ spin_lock_irq(&pDevice->AddressSpinlock);
++ ints = READ_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE);
++ ints |= Mask;
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE, ints);
++ spin_unlock_irq(&pDevice->AddressSpinlock);
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskIrq - Mask SD interrupts
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 MaskIrq(PSDHCD_DEVICE pDevice, UINT32 Mask)
++{
++ UINT16 ints;
++ /* protected read-modify-write */
++ spin_lock_irq(&pDevice->AddressSpinlock);
++ ints = READ_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE);
++ ints &= ~Mask;
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE, ints);
++ spin_unlock_irq(&pDevice->AddressSpinlock);
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskIrqFromIsr - Mask SD interrupts, called from ISR
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 MaskIrqFromIsr(PSDHCD_DEVICE pDevice, UINT32 Mask)
++{
++ UINT16 ints;
++ /* protected read-modify-write */
++ spin_lock(&pDevice->AddressSpinlock);
++ ints = READ_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE);
++ ints &= ~Mask;
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE, ints);
++ spin_unlock(&pDevice->AddressSpinlock);
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskIrqFromIsr - Unmask SD interrupts
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 UnmaskIrqFromIsr(PSDHCD_DEVICE pDevice, UINT32 Mask)
++{
++ UINT16 ints;
++ /* protected read-modify-write */
++ spin_lock(&pDevice->AddressSpinlock);
++ ints = READ_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE);
++ ints |= Mask;
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_SIGNAL_ENABLE, ints);
++ spin_unlock(&pDevice->AddressSpinlock);
++ return ints;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetDefaults - get the user modifiable data items
++ Input: pDeviceContext - host controller
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetDefaults(PSDHCD_DEVICE pDeviceContext)
++{
++ //can't change this dynanmically: pDeviceContext->BaseClock = BaseClock;
++ pDeviceContext->TimeOut = timeout;
++ pDeviceContext->ClockSpinLimit = ClockSpinLimit;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ EnableDisableSDIOIRQ - enable SDIO interrupt detection
++ Input: pDevice - host controller
++ Enable - enable SDIO IRQ detection
++ FromIsr - called from ISR
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void EnableDisableSDIOIRQ(PSDHCD_DEVICE pDevice, BOOL Enable, BOOL FromIsr)
++{
++ UINT16 intsEnables;
++
++ if (FromIsr) {
++ if (Enable) {
++ // isr should never re-enable
++ DBG_ASSERT(FALSE);
++ } else {
++ MaskIrqFromIsr(pDevice, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE);
++ }
++ } else {
++ if (Enable) {
++ UnmaskIrq(pDevice, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE);
++ } else {
++ MaskIrq(pDevice, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE);
++ }
++ }
++
++ /* protected read-modify-write */
++ if (FromIsr) {
++ spin_lock(&pDevice->AddressSpinlock);
++ } else {
++ spin_lock_irq(&pDevice->AddressSpinlock);
++ }
++
++ intsEnables = READ_HOST_REG16(pDevice, HOST_REG_INT_STATUS_ENABLE);
++ if (Enable) {
++ intsEnables |= HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE;
++ } else {
++ intsEnables &= ~HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE;
++ }
++
++ WRITE_HOST_REG16(pDevice, HOST_REG_INT_STATUS_ENABLE, intsEnables);
++
++ if (FromIsr) {
++ spin_unlock(&pDevice->AddressSpinlock);
++ } else {
++ spin_unlock_irq(&pDevice->AddressSpinlock);
++ }
++
++
++}
++
++/*
++ * module init
++*/
++static int __init sdio_pci_hcd_init(void) {
++ SYSTEM_STATUS err;
++ SDIO_STATUS status;
++
++ REL_PRINT(SDDBG_TRACE, ("+SDIO PCIELLEN HCD: loaded\n"));
++
++ SDLIST_INIT(&HcdContext.DeviceList);
++ status = SemaphoreInitialize(&HcdContext.DeviceListSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ return SDIOErrorToOSError(status);
++ }
++
++ /* register with the PCI bus driver */
++ err = pci_module_init(&sdio_pci_driver);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PCIELLEN HCD: failed to register with system PCI bus driver, %d\n",
++ err));
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCIELLEN HCD: sdio_pci_hcd_init\n"));
++ return err;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_pci_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO PCIELLEN HCD: unloaded\n"));
++ pci_unregister_driver(&sdio_pci_driver);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PCIELLEN HCD: leave sdio_pci_hcd_cleanup\n"));
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_pci_hcd_init);
++module_exit(sdio_pci_hcd_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_pciellen_hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pci_ellen/sdio_pciellen_hcd.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,253 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_pciellen_hcd.h
++
++ at abstract: include file for Tokyo Electron PCI Ellen host controller, OS independent code
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_PCIELLEN_HCD_H___
++#define __SDIO_PCIELLEN_HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++
++enum PXA_TRACE_ENUM {
++ PXA_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ PXA_TRACE_DATA = (SDDBG_TRACE + 2),
++ PXA_TRACE_REQUESTS,
++ PXA_TRACE_CONFIG,
++ PXA_TRACE_MMC_INT,
++ PXA_TRACE_CLOCK,
++ PXA_TRACE_SDIO_INT,
++ PXA_TRACE_LAST
++};
++
++#define HOST_REG_BLOCK_SIZE 0x04
++
++#define HOST_REG_BLOCK_COUNT 0x06
++
++#define HOST_REG_ARGUMENT 0x08
++
++#define HOST_REG_TRANSFER_MODE 0x0C
++#define HOST_REG_TRANSFER_MODE_MULTI_BLOCK (1 << 5)
++#define HOST_REG_TRANSFER_MODE_READ (1 << 4)
++#define HOST_REG_TRANSFER_MODE_AUTOCMD12 (1 << 2)
++#define HOST_REG_TRANSFER_MODE_BLOCKCOUNT_ENABLE (1 << 1)
++#define HOST_REG_TRANSFER_MODE_DMA_ENABLE (1 << 0)
++
++#define HOST_REG_COMMAND_REGISTER 0x0E
++#define HOST_REG_COMMAND_REGISTER_CMD_SHIFT 8
++#define HOST_REG_COMMAND_REGISTER_DATA_PRESENT (1 << 5)
++#define HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE (1 << 4)
++#define HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE (1 << 3)
++
++
++#define HOST_REG_RESPONSE 0x10 /* 32-bit reguisters 0x10 through 0x1C */
++
++#define HOST_REG_BUFFER_DATA_PORT 0x20
++
++#define HOST_REG_PRESENT_STATE 0x24
++#define HOST_REG_PRESENT_STATE_WRITE_ENABLED (1 << 19)
++#define HOST_REG_PRESENT_STATE_CARD_DETECT (1 << 18)
++#define HOST_REG_PRESENT_STATE_CARD_STATE_STABLE (1 << 17)
++#define HOST_REG_PRESENT_STATE_CARD_INSERTED (1 << 16)
++#define HOST_REG_PRESENT_STATE_BUFFER_READ_ENABLE (1 << 11)
++#define HOST_REG_PRESENT_STATE_BUFFER_WRITE_ENABLE (1 << 10)
++#define HOST_REG_PRESENT_STATE_BUFFER_READ_TRANSFER_ACTIVE (1 << 9)
++#define HOST_REG_PRESENT_STATE_BUFFER_WRITE_TRANSFER_ACTIVE (1 << 8)
++#define HOST_REG_PRESENT_STATE_BUFFER_DAT_LINE_ACTIVE (1 << 2)
++#define HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_DAT (1 << 1)
++#define HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD (1 << 0)
++
++
++#define HOST_REG_CONTROL 0x28
++#define HOST_REG_CONTROL_LED_ON (1 << 0)
++#define HOST_REG_CONTROL_1BIT_WIDTH 0x00
++#define HOST_REG_CONTROL_4BIT_WIDTH (1 << 1)
++#define HOST_REG_CONTROL_HI_SPEED (1 << 2)
++
++#define HOST_REG_POWER_CONTROL 0x29
++#define HOST_REG_POWER_CONTROL_ON (1 << 0)
++#define HOST_REG_POWER_CONTROL_VOLT_3_3 (7 << 1)
++#define HOST_REG_POWER_CONTROL_VOLT_3_0 (6 << 1)
++#define HOST_REG_POWER_CONTROL_VOLT_1_8 (5 << 1)
++
++#define HOST_REG_BLOCK_GAP 0x2A
++#define HOST_REG_INT_DETECT_AT_BLOCK_GAP (1 << 3)
++
++#define HOST_REG_CLOCK_CONTROL 0x2C
++#define HOST_REG_CLOCK_CONTROL_CLOCK_ENABLE (1 << 0)
++#define HOST_REG_CLOCK_CONTROL_CLOCK_STABLE (1 << 1)
++#define HOST_REG_CLOCK_CONTROL_SD_ENABLE (1 << 2)
++
++#define HOST_REG_TIMEOUT_CONTROL 0x2E
++#define HOST_REG_TIMEOUT_CONTROL_DEFAULT 0x0C
++
++#define HOST_REG_SW_RESET 0x2F
++#define HOST_REG_SW_RESET_ALL (1 << 0)
++#define HOST_REG_SW_RST_CMD_LINE (1 << 1)
++#define HOST_REG_SW_RST_DAT_LINE (1 << 2)
++
++#define HOST_REG_NORMAL_INT_STATUS 0x30
++#define HOST_REG_NORMAL_INT_STATUS_ERROR (1 << 15)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_INTERRUPT (1 << 8)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_REMOVAL (1 << 7)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_INSERT (1 << 6)
++#define HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY (1 << 5)
++#define HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY (1 << 4)
++#define HOST_REG_NORMAL_INT_STATUS_DMA_INT (1 << 3)
++#define HOST_REG_NORMAL_INT_STATUS_BLOCK_GAP (1 << 2)
++#define HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE (1 << 1)
++#define HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE (1 << 0)
++#define HOST_REG_NORMAL_INT_STATUS_ALL_ERR 0xFFFF
++
++#define HOST_REG_ERROR_INT_STATUS 0x32
++#define HOST_REG_ERROR_INT_STATUS_VENDOR_MASK 0xF000
++#define HOST_REG_ERROR_INT_STATUS_VENDOR_SHIFT 12
++#define HOST_REG_ERROR_INT_STATUS_AUTOCMD12ERR (1 << 8)
++#define HOST_REG_ERROR_INT_STATUS_CURRENTLIMITERR (1 << 7)
++#define HOST_REG_ERROR_INT_STATUS_DATAENDBITERR (1 << 6)
++#define HOST_REG_ERROR_INT_STATUS_DATACRCERR (1 << 5)
++#define HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR (1 << 4)
++#define HOST_REG_ERROR_INT_STATUS_CMDINDEXERR (1 << 3)
++#define HOST_REG_ERROR_INT_STATUS_CMDENDBITERR (1 << 2)
++#define HOST_REG_ERROR_INT_STATUS_CRCERR (1 << 1)
++#define HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR (1 << 0)
++#define HOST_REG_ERROR_INT_STATUS_ALL_ERR 0xFFFF
++
++#define HOST_REG_INT_STATUS_ENABLE 0x34
++#define HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE (1 << 8)
++#define HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE (1 << 7)
++#define HOST_REG_INT_STATUS_CARD_INSERT_ENABLE (1 << 6)
++#define HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE (1 << 5)
++#define HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE (1 << 4)
++#define HOST_REG_INT_STATUS_DMA_ENABLE (1 << 3)
++#define HOST_REG_INT_STATUS_BLOCK_GAP_ENABLE (1 << 2)
++#define HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE (1 << 1)
++#define HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE (1 << 0)
++#define HOST_REG_INT_STATUS_ALL 0x00F3
++#define HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY 0x00C0
++
++#define HOST_REG_ERR_STATUS_ENABLE 0x36
++/* same bits as HOST_REG_ERROR_INT_STATUS */
++
++#define HOST_REG_INT_SIGNAL_ENABLE 0x38
++/* same bits as HOST_REG_INT_STATUS_ENABLE */
++
++#define HOST_REG_INT_ERR_SIGNAL_ENABLE 0x3A
++/* same bits as HOST_REG_ERR_STATUS_ENABLE */
++
++#define HOST_REG_CAPABILITIES 0x40
++#define HOST_REG_CAPABILITIES_VOLT_1_8 (1 << 26)
++#define HOST_REG_CAPABILITIES_VOLT_3_0 (1 << 25)
++#define HOST_REG_CAPABILITIES_VOLT_3_3 (1 << 24)
++#define HOST_REG_CAPABILITIES_SUSPEND_RESUME (1 << 23)
++#define HOST_REG_CAPABILITIES_DMA (1 << 22)
++#define HOST_REG_CAPABILITIES_HIGH_SPEED (1 << 21)
++#define HOST_REG_CAPABILITIES_SUSPEND_RESUME (1 << 23)
++#define HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_MASK 0x30000
++#define HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_SHIFT 16
++#define HOST_REG_CAPABILITIES_CLOCK_MASK 0x3F00
++#define HOST_REG_CAPABILITIES_CLOCK_SHIFT 8
++#define HOST_REG_CAPABILITIES_TIMEOUT_CLOCK_UNITS (1 << 7)
++#define HOST_REG_CAPABILITIES_TIMEOUT_FREQ_MASK 0x3F
++#define HOST_REG_CAPABILITIES_TIMEOUT_FREQ_SHIFT 0
++
++#define HOST_REG_MAX_CURRENT_CAPABILITIES 0x48
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_MASK 0xFF0000
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_SHIFT 16
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_MASK 0x00FF00
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_SHIFT 8
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_MASK 0x0000FF
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_SHIFT 0
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_SCALER 4
++
++#define HOST_REG_VERSION 0xFE
++#define HOST_REG_VERSION_SPEC_VERSION_MASK 0xFF
++#define HOST_REG_VERSION_VENDOR_VERSION_MASK 0xFF00
++#define HOST_REG_VERSION_VENDOR_VERSION_SHIFT 8
++
++#define SDIO_BD_MAX_SLOTS 24
++#define SDIO_SD_MAX_BLOCKS ((UINT)0xFFFF)
++#define SDMMC_RESP_TIMEOUT_CLOCKS 64
++#define SDMMC_DATA_TIMEOUT_CLOCKS 0xFFFF
++
++#define SPI_ENABLE_WITH_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_CRC_ENABLE | MMC_SPI_SEL_CS0)
++#define SPI_ENABLE_NO_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_SEL_CS0)
++
++#define SD_DEFAULT_RESPONSE_BYTES 6
++#define SD_R2_RESPONSE_BYTES 16
++
++#define SD_CLOCK_MAX_ENTRIES 9
++
++typedef struct _SD_CLOCK_TBL_ENTRY {
++ INT ClockRateDivisor; /* divisor */
++ UINT16 RegisterValue; /* register value for clock divisor */
++}SD_CLOCK_TBL_ENTRY;
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDLIST DeviceList; /* the list of current devices handled by this driver */
++ OS_SEMAPHORE DeviceListSem; /* protection for the DeviceList */
++ UINT DeviceCount; /* number of devices currently installed */
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext);
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext);
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDeviceContext);
++SDIO_STATUS QueueEventResponse(PSDHCD_DEVICE pDeviceContext, INT WorkItemID);
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq);
++void HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq);
++void SetPowerOn(PSDHCD_DEVICE pDeviceContext, BOOL On);
++UINT16 MaskIrq(PSDHCD_DEVICE pDevice, UINT32 Mask);
++UINT16 UnmaskIrq(PSDHCD_DEVICE pDevice, UINT32 Mask);
++UINT16 MaskIrqFromIsr(PSDHCD_DEVICE pDevice, UINT32 Mask);
++UINT16 UnmaskIrqFromIsr(PSDHCD_DEVICE pDevice, UINT32 Mask);
++void EnableDisableSDIOIRQ(PSDHCD_DEVICE pDevice, BOOL Enable, BOOL FromIsr);
++
++
++#endif /* __SDIO_PCIELLEN_HCD_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/mx21/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/mx21/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,7 @@
++#
++# SDIO mx21 host controller makefile
++#
++obj-m += sdio_mx21_hcd.o
++
++sdio_mx21_hcd-objs := sdio_mx21_hcd.o sdio_mx21_hcd_os.o
++
+Index: linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1286 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_mx21c
++
++ at abstract: iMX21 Local Bus SDIO Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include "sdio_mx21.h"
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++#define FROM_ISR TRUE
++#define FROM_NORMAL FALSE
++
++#define POLL_TIMEOUT 10000000
++
++#define WAIT_FOR_HC_STATUS(pHct,DoneMask,pError,ErrorMask,Status,Timeout) \
++{ \
++ INT _timeoutCnt = (Timeout); \
++ while((_timeoutCnt > 0) && \
++ !(READ_HC_REG((pHct), SDHC_STATUS_REG) & (DoneMask)) && \
++ !(*(pError) = READ_HC_REG((pHct), SDHC_STATUS_REG) & (ErrorMask))){_timeoutCnt--;} \
++ *(pError) = READ_HC_REG((pHct), SDHC_STATUS_REG) & (ErrorMask); \
++ if (0 == _timeoutCnt) {(Status) = SDIO_STATUS_DEVICE_ERROR; \
++ DBG_PRINT(SDDBG_ERROR, \
++ ("SDIO MX21 - status timeout, waiting for %s (stat=0x%X)\n",\
++ #DoneMask, READ_HC_REG((pHct), SDHC_STATUS_REG))); \
++ DBG_ASSERT(FALSE);} \
++}
++
++#define SD_DEFAULT_RESPONSE_BYTES 6
++#define SD_R2_RESPONSE_BYTES 16
++
++void DMATransferComplete(PVOID pContext, SDIO_STATUS Status, BOOL FromIsr);
++void ResetController(PSDHCD_DRIVER_CONTEXT pHct, BOOL RestoreHcdSettings, BOOL FromIsr);
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pHct - host context
++ pReq - the request
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetResponseData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT wordCount;
++ INT byteCount;
++ UINT16 readBuffer[8];
++ UINT16 *pBuf;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return;
++ }
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES;
++ }
++
++ wordCount = byteCount >> 1;
++
++ /* start the buffer at the tail and work backwards since responses are sent MSB first
++ and shifted into the FIFO */
++ pBuf = &readBuffer[(wordCount - 1)];
++ while (wordCount) {
++ *pBuf = (UINT16)READ_HC_REG(pHct, SDHC_RES_FIFO_REG);
++ pBuf--;
++ wordCount--;
++ }
++
++ memcpy(pReq->Response,readBuffer,byteCount);
++ /* the CRC is not returned in the FIFO, just zero it out */
++ pReq->Response[0] = 0x00;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ /* on R2 responses, the start token is removed, just stick it in */
++ pReq->Response[SD_R2_RESPONSE_BYTES] = 0x3F;
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= SDHC_TRACE_REQUESTS) {
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = 17;
++ }
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO MX21 - Response Dump");
++ }
++
++ return;
++}
++
++void DumpCurrentRequestInfo(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ PSDREQUEST pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++ if (pReq != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - Current Request (0x%X) Command:%d, ARG:0x%8.8X\n",
++ (INT)pReq, pReq->Command, pReq->Argument));
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "WRITE":"READ",
++ pReq->BlockCount,
++ pReq->BlockLen,
++ pReq->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateHCError - translate error
++ Input: ErrorStatus - error status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateHCError(PSDHCD_DRIVER_CONTEXT pHct,UINT32 ErrorStatus)
++{
++ if (ErrorStatus & SDHC_STATUS_RESP_CRC_ERROR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - RESP CRC ERROR \n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ } else if (ErrorStatus & SDHC_STATUS_READ_CRC_ERROR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - READDATA CRC ERROR \n"));
++ DumpCurrentRequestInfo(pHct);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - READ ERROR (STAT:0x%X:IMASK:0x%X)\n",
++ READ_HC_REG(pHct,SDHC_STATUS_REG),READ_HC_REG(pHct, SDHC_INT_MASK_REG)));
++ if (pHct->DmaType != SDHC_DMA_NONE) {
++ DumpDmaInfo(pHct);
++ }
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ } else if (ErrorStatus & SDHC_STATUS_WRITE_CRC_ERROR) {
++ DumpCurrentRequestInfo(pHct);
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - WRITE CRC ERROR \n"));
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - WRITE ERROR (STAT:0x%X:IMASK:0x%X)\n",
++ READ_HC_REG(pHct,SDHC_STATUS_REG),READ_HC_REG(pHct, SDHC_INT_MASK_REG)));
++
++ if (pHct->DmaType != SDHC_DMA_NONE) {
++ DumpDmaInfo(pHct);
++ }
++ return SDIO_STATUS_BUS_WRITE_ERROR;
++ } else if (ErrorStatus & SDHC_STATUS_RESP_TIMEOUT) {
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ } else if (ErrorStatus & SDHC_STATUS_READ_TIMEOUT) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 - READ TIMEOUT \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - clock control
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL _DoClockStartStop(PSDHCD_DRIVER_CONTEXT pHct, BOOL On)
++{
++ INT timeout;
++ INT retry = 3;
++
++ while (retry) {
++ timeout = 70000;
++ if (On) {
++ WRITE_HC_REG(pHct,
++ SDHC_STR_STP_CLK_REG,
++ SDHC_STR_STP_CLK_ENABLE | SDHC_STR_STP_CLK_START);
++ /* wait for clock to start */
++ while (timeout) {
++ if ((READ_HC_REG(pHct, SDHC_STATUS_REG) & SDHC_STATUS_CLK_RUN)) {
++ break;
++ }
++ timeout--;
++ }
++ } else {
++ WRITE_HC_REG(pHct,
++ SDHC_STR_STP_CLK_REG,
++ SDHC_STR_STP_CLK_ENABLE | SDHC_STR_STP_CLK_STOP);
++ /* wait for clock to stop */
++ while (timeout) {
++ if (!(READ_HC_REG(pHct, SDHC_STATUS_REG) & SDHC_STATUS_CLK_RUN)) {
++ break;
++ }
++ timeout--;
++ }
++ }
++
++ if (0 == timeout) {
++ retry--;
++ } else {
++ break;
++ }
++ }
++
++ if (0 == retry) {
++ return FALSE;
++ }
++ return TRUE;
++}
++
++#define ClockStartStop(pHct, On) \
++{if (!_DoClockStartStop((pHct),(On))) DBG_ASSERT(FALSE);}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pHcd - HCD object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DRIVER_CONTEXT pHct, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int i;
++ int clockIndex;
++ UINT32 regValue;
++
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21 - SetMode\n"));
++
++ /* set clock index to the end, the table is sorted this way */
++ clockIndex = pHct->ValidClockEntries - 1;
++ pMode->ActualClockRate = pHct->ClockDivisorTable[clockIndex].ClockRate;
++ for (i = 0; i < pHct->ValidClockEntries; i++) {
++ if (pMode->ClockRate >= pHct->ClockDivisorTable[i].ClockRate) {
++ pMode->ActualClockRate = pHct->ClockDivisorTable[i].ClockRate;
++ clockIndex = i;
++ break;
++ }
++ }
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21 - 1-bit bus width\n"));
++ pHct->SD4Bit = FALSE;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21 - 4-bit bus width\n"));
++ pHct->SD4Bit = TRUE;
++ break;
++ default:
++ break;
++ }
++ /* get the base clock divisor value and preserve */
++ regValue = READ_HC_REG(pHct, SDHC_CLK_RATE_REG);
++ /* set new value */
++ regValue &= ~SDHC_CLK_RATE_PRESCALE_MASK;
++ regValue |= pHct->ClockDivisorTable[clockIndex].RegisterValue << SDHC_CLK_RATE_PRESCALE_SHIFT;
++ /* set the clock divisor */
++ WRITE_HC_REG(pHct, SDHC_CLK_RATE_REG, regValue);
++
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21 - SD Clock: %d Hz (CLK_RATE_REG:0x%X)\n",
++ pMode->ActualClockRate,regValue));
++
++ memcpy(&pHct->SavedBusMode,pMode,sizeof(pHct->SavedBusMode));
++
++}
++
++BOOL HcdTransferTxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT32 *pFifo;
++
++ pFifo = (volatile UINT32 *)(GET_HC_REG_BASE(pHct) + SDHC_BUF_ACCESS_REG);
++ dataCopy = min(pReq->DataRemaining,pHct->FifoDepth);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* copy to fifo */
++ while (dataCopy) {
++ data = *pBuf;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ data |= ((UINT16)*pBuf) << 8;
++ dataCopy--;
++ pBuf++;
++ }
++ _WRITE_DWORD_REG(pFifo,(UINT32)data);
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 Pending TX Remaining: %d \n",pReq->DataRemaining));
++
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++void HcdTransferRxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT32 *pFifo;
++
++ pFifo = (volatile UINT32 *)(GET_HC_REG_BASE(pHct) + SDHC_BUF_ACCESS_REG);
++
++ /* read the whole FIFO or up to what is left */
++ dataCopy = min(pReq->DataRemaining,pHct->FifoDepth);
++ /* get where we are */
++ pBuf = (PUINT8)pReq->pHcdContext;
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* copy from fifo */
++ while (dataCopy) {
++ data = (UINT16)_READ_DWORD_REG(pFifo);
++ *pBuf = (UINT8)data;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ *pBuf = (UINT8)(data >> 8);
++ pBuf++;
++ dataCopy--;
++ }
++ }
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 Pending RX Remaining: %d \n",pReq->DataRemaining));
++}
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ UINT32 HwErrors,
++ BOOL FromIsr)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ do {
++ if (HwErrors) {
++ status = TranslateHCError(pHct,HwErrors);
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 command failure: STAT:0x%X \n",HwErrors));
++ break;
++ } else {
++ /* get the response data for the command */
++ GetResponseData(pHct,pReq);
++ }
++
++ if (!IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ /* all done */
++ break;
++ }
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pHct->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ /* start up DMA for data transfers */
++ if (pHct->DmaType != SDHC_DMA_NONE) {
++
++ status = SetUpHCDDMA(pHct,
++ pReq,
++ DMATransferComplete,
++ pHct);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ /* data transfer pending */
++ status = SDIO_STATUS_PENDING;
++
++ } while (FALSE);
++
++ if (SDIO_STATUS_PENDING == status) {
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 Pending %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ }
++
++ return status;
++}
++
++void EndHCTransfer(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq, BOOL FromIsr)
++{
++ if (!SDIO_SUCCESS(pReq->Status)) {
++ /* bus responses are normal errors */
++ if (pReq->Status != SDIO_STATUS_BUS_RESP_TIMEOUT) {
++ ResetController(pHct,TRUE,FromIsr);
++ } else {
++ /* a bus response timeout occured, find it what command it was, some commands
++ * will normally time out */
++ if (!((pReq->Command == 5) || (pReq->Command == 55) || (pReq->Command == 1))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Bus Timeout: CMD:%d\n",pReq->Command));
++ }
++ }
++ } else {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ /* on data transfers, reset the controller, on occasion we
++ * see Write CRC errors */
++ ResetController(pHct,TRUE,FromIsr);
++ }
++ }
++ /* turn off interrupts (except SDIO IRQs) and clock */
++ MaskHcdIrq(pHct,(SDHC_INT_MASK_ALL & (~SDHC_INT_SDIO_MASK)),FromIsr);
++ /* stop the clock, this apparently clears statuses */
++ ClockStartStop(pHct, CLOCK_OFF);
++ /* restart the clock if we need interrupt detection */
++ if (pHct->KeepClockOn) {
++ ClockStartStop(pHct, CLOCK_ON);
++ }
++
++ if (pHct->SDIOIrqDetectArmed) {
++ /* re-arm interrupt detection */
++ UnmaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,FromIsr);
++ }
++}
++
++void DMATransferComplete(PVOID pContext, SDIO_STATUS Status, BOOL FromIsr)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pContext;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++ DBG_ASSERT(pReq != NULL);
++
++ DBG_PRINT(SDHC_TRACE_DATA,
++ ("+SDIO MX21 %s DMATransferComplete, Status:%d Req:0x%X \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",Status,(UINT32)pReq));
++
++ if (!SDIO_SUCCESS(Status)) {
++ /* if DMA failed, we need to complete the request here
++ * the SDIO controller ISR will not fire in this case */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 %s DMATransferComplete failed with status:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",Status));
++ pReq->Status = Status;
++ /* turn off interrupts and clock */
++ EndHCTransfer(pHct,pReq,FromIsr);
++ /* complete the request */
++ CompleteRequestSyncDMA(pHct,pReq,FromIsr);
++ } else {
++
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 From DMA, StatReg:0x%X IMASK:0x%X \n",
++ READ_HC_REG(pHct,SDHC_STATUS_REG),
++ READ_HC_REG(pHct, SDHC_INT_MASK_REG)));
++ }
++
++ DBG_PRINT(SDHC_TRACE_DATA, ("-SDIO MX21 DMATransferComplete\n"));
++}
++
++PTEXT GetRespString(PSDREQUEST pReq)
++{
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ return "NONE";
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ return "SDIO R5";
++ case SDREQ_FLAGS_RESP_R1:
++ return "R1";
++ case SDREQ_FLAGS_RESP_R1B:
++ return "R1B";
++ case SDREQ_FLAGS_RESP_R2:
++ return "R2";
++ case SDREQ_FLAGS_RESP_R3:
++ return "R3";
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ return "SDIO R4";
++ case SDREQ_FLAGS_RESP_R6:
++ return "R6";
++ default:
++ return "Unknown";
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT32 temp = 0;
++ PSDREQUEST pReq;
++ UINT32 irqsToUnMask = 0;
++ UINT32 shortTransferStatMask = 0;
++ UINT32 shortTransferErrorsMask = 0;
++ BOOL localIrqMasked = FALSE;
++
++ /* make sure clock is off before we do anything */
++ ClockStartStop(pHct, CLOCK_OFF);
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ /* reset current DMA type flag */
++ pHct->DmaType = SDHC_DMA_NONE;
++ pHct->CmdProcessed = FALSE;
++
++ if (pHct->SDIOIrqDetectArmed) {
++ /* mask SDIO interrupt detection if it was armed, bus activity seems to
++ * cause false triggering of SDIO interrupts which the bus driver has to
++ * process */
++ MaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,FALSE);
++ /* it will be re-enabled on request completion */
++ }
++
++ do {
++
++ if (pHct->SD4Bit) {
++ /* only set 4 bit mode for data */
++ temp = SDHCD_CMD_DAT_BUS_4BIT;
++ pHct->FifoDepth = SDHC_MAX_FIFO_4BIT;
++ } else {
++ temp = SDHCD_CMD_DAT_BUS_1BIT;
++ pHct->FifoDepth = SDHC_MAX_FIFO_1BIT;
++ }
++
++ if (pReq->BlockCount > 1) {
++ /* the MX21 by design is broken, for mult-block transfers the block size must
++ * be a multiple of the FIFO depth! */
++ if (pReq->BlockLen & (pHct->FifoDepth- 1)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 %s Multi-block transfer has BlockLen:%d, must be a multiple of:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockLen, pHct->FifoDepth));
++ status = SDIO_STATUS_UNSUPPORTED;
++ break;
++ }
++ }
++
++ if (pHct->IssueInitClocks) {
++ pHct->IssueInitClocks = FALSE;
++ temp |= SDHCD_CMD_DAT_INIT_CLKS;
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ /* an SDIO R5 response is the same as an R1 */
++ case SDREQ_FLAGS_RESP_R1:
++ temp |= SDHCD_CMD_DAT_RESP_R1R5R6;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp |= SDHCD_CMD_DAT_RESP_R1R5R6;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp |= SDHCD_CMD_DAT_RESP_R2;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp |= SDHCD_CMD_DAT_RESP_R3R4;
++ break;
++ case SDREQ_FLAGS_RESP_R6:
++ temp |= SDHCD_CMD_DAT_RESP_R1R5R6;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ temp |= SDHCD_CMD_DAT_DATA_ENABLE;
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ temp |= SDHCD_CMD_DAT_DATA_WRITE;
++ }
++ /* set block length */
++ WRITE_HC_REG(pHct, SDHC_BLK_LEN_REG, pReq->BlockLen);
++ WRITE_HC_REG(pHct, SDHC_NOB_REG, pReq->BlockCount);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ /* check scatter gather DMA */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ DBG_ASSERT(pHcd->pDmaDescription != NULL);
++ DBG_PRINT(SDHC_TRACE_DATA, (" : Data Transfer using Scatter Gather DMA: %d Descriptors\n",
++ pReq->DescriptorCount));
++ pHct->DmaType = SDHC_DMA_SCATTER_GATHER;
++ pReq->pHcdContext = NULL;
++ if (!IsDMAAllowed(pHct, pReq)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO MX21 DMA HCLK Errata, cannot support the current bus width with multi-block transfer \n"));
++ /* see DMA HCLK issues with SD controller
++ * need to punt this operation to PIO mode to work around
++ * chip errata */
++ status = SDIO_STATUS_UNSUPPORTED;
++ break;
++ }
++ } else {
++ /* non-scatter gather, could be common buffer or PIO */
++ if (IsDMAAllowed(pHct, pReq)) {
++ /* the FIFOs are a bit puny, so we use common buffer DMA (if available)
++ * to transfer the buffer if the data is larger than a FIFO's worth */
++ if (pReq->DataRemaining > pHct->FifoDepth) {
++ pHct->DmaType = SDHC_DMA_COMMON_BUFFER;
++ }
++ }
++
++ DBG_PRINT(SDHC_TRACE_DATA, (" : Data Transfer will use %s \n",
++ (pHct->DmaType == SDHC_DMA_COMMON_BUFFER) ? "common buffer DMA" : "PIO Mode"));
++
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++
++ /* check for short transfer optimization */
++ if ((pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) &&
++ (pHct->DmaType == SDHC_DMA_NONE) &&
++ (pReq->DataRemaining <= pHct->FifoDepth)) {
++ /* the data will fit in the FIFO and the caller indicates this
++ * transfer will be short */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ shortTransferStatMask = SDHC_STATUS_WRITE_DONE;
++ shortTransferErrorsMask = SDHC_STATUS_WRITE_CRC_ERROR;
++ } else {
++ shortTransferStatMask = SDHC_STATUS_READ_DONE;
++ shortTransferErrorsMask = SDHC_STATUS_READ_TIMEOUT |
++ SDHC_STATUS_READ_CRC_ERROR;
++ }
++ }
++ }
++ }
++
++ if (0 == shortTransferStatMask) {
++ /* normal PIO or DMA mode */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* interrupts will be used for data transfer completion */
++ irqsToUnMask |= SDHC_INT_WRITE_DONE_MASK;
++ } else {
++ /* interrupts will be used for data transfer completion */
++ irqsToUnMask |= SDHC_INT_DATA_TRANS_DONE_MASK;
++ }
++
++ if (pHct->DmaType == SDHC_DMA_NONE) {
++ /* data requires multiple FIFO fills, the spec is not clear if
++ * we can pre-load for TX, so we'll wait for a FIFO EMPTY interrupt */
++ /* Enable FIFO full and EMPTY interrupts */
++ irqsToUnMask |= SDHC_INT_BUFF_RDY_MASK;
++ }
++ } else {
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 Short %s transfer (stat:0x%X, errs:0x%X)\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ shortTransferStatMask,shortTransferErrorsMask ));
++ }
++
++ if (SDHCD_GET_OPER_CLOCK(pHcd) < HCD_COMMAND_MIN_POLLING_CLOCK) {
++ /* clock rate is very low, need to use interrupts here */
++ irqsToUnMask |= SDHC_INT_END_CMD_MASK;
++ }
++
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 CMD_DAT:0x%X (RespType:%s, Command:0x%X , Arg:0x%X Irqs:0x%X) \n",
++ temp, GetRespString(pReq), pReq->Command, pReq->Argument,irqsToUnMask));
++
++ WRITE_HC_REG(pHct, SDHC_CMD_REG, pReq->Command);
++ WRITE_HC_REG(pHct, SDHC_ARGH_REG, (pReq->Argument >> 16));
++ WRITE_HC_REG(pHct, SDHC_ARGL_REG, (pReq->Argument & 0xFFFF));
++ WRITE_HC_REG(pHct, SDHC_CMD_DAT_REG, temp);
++
++ if (irqsToUnMask & SDHC_INT_END_CMD_MASK) {
++ /* command/resp uses interrupts */
++ /* unmask required interrupts */
++ UnmaskHcdIrq(pHct, irqsToUnMask, FALSE);
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ status = SDIO_STATUS_PENDING;
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 using interrupt for command done.. \n"));
++ break;
++ }
++
++ /* if we get here, we are optimizing the transfer using command done polling */
++ if (irqsToUnMask) {
++ /* we can only write to the MASK register once during a transaction, so while
++ * we poll and check processing, we mask the interrupt at the CPU */
++ DisableHcdInterrupt(pHct, FROM_NORMAL);
++ localIrqMasked = TRUE;
++ UnmaskHcdIrq(pHct, irqsToUnMask, FALSE);
++ }
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 polling for command done.. \n"));
++ temp = 0;
++
++ if ((pReq->Flags & SDREQ_FLAGS_DATA_TRANS) &&
++ (!IS_SDREQ_WRITE_DATA(pReq->Flags))) {
++ /* on READ operations, the MX21 has a hardware bug:
++ * if the read data arrives early while the controller is
++ * reading in the response to the command, the READ_OP_DONE or FIFO_FULL
++ * bits will be set and the END_CMD will NEVER be set. For read operations
++ * we must poll for either of END_CMD or READ_OP_DONE or FIFO_FULL */
++ WAIT_FOR_HC_STATUS(pHct,
++ (SDHC_STATUS_END_CMD | SDHC_STATUS_READ_DONE | SDHC_STATUS_FIFO_FULL),
++ &temp,
++ SDHC_STATUS_RESP_ERRORS | SDHC_STATUS_RD_WR_ERRORS,
++ status,
++ POLL_TIMEOUT);
++ } else {
++ /* wait for command done */
++ WAIT_FOR_HC_STATUS(pHct,
++ SDHC_STATUS_END_CMD,
++ &temp,
++ SDHC_STATUS_RESP_ERRORS,
++ status,
++ POLL_TIMEOUT);
++ }
++
++ if (SDIO_SUCCESS(status)) {
++ /* process the command completion */
++ status = ProcessCommandDone(pHct,pReq,temp,FALSE);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (0 == shortTransferStatMask) {
++ /* no short data transfer necessary, we're done */
++ break;
++ }
++
++ /* if we get here, we need to deal with the short transfer DATA phase */
++
++ /* reset status for polling again */
++ status = SDIO_STATUS_SUCCESS;
++ temp = 0;
++ /* polling status here to accelerate processing */
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 Short %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* load the buffer */
++ HcdTransferTxData(pHct, pReq);
++ }
++
++ WAIT_FOR_HC_STATUS(pHct,
++ shortTransferStatMask,
++ &temp,
++ shortTransferErrorsMask,
++ status,
++ POLL_TIMEOUT);
++
++ if (!SDIO_SUCCESS(status)) {
++ /* command timed out */
++ break;
++ }
++
++ if (temp) {
++ /* some error bits were set */
++ DBG_PRINT(SDHC_TRACE_REQUESTS,
++ ("SDIO MX21 Short Transfer Failure: STAT:0x%X \n",temp));
++ status = TranslateHCError(pHct,temp);
++ break;
++ }
++ /* no errors */
++ if (!IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* drain the FIFO on reads */
++ HcdTransferRxData(pHct,pReq);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ pReq->Status = status;
++ EndHCTransfer(pHct,pReq,FROM_NORMAL);
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags) || (pHct->DmaType != SDHC_DMA_NONE)) {
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ if (SDHC_DMA_NONE == pHct->DmaType) {
++ /* normal deferred completion */
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* deferred completion that synchronizes with the DMA controller
++ * in case it got started */
++ CompleteRequestSyncDMA(pHct,pReq,FALSE);
++ }
++ status = SDIO_STATUS_PENDING;
++ } else {
++ /* complete the request */
++ DBG_PRINT(SDHC_TRACE_REQUESTS, ("SDIO MX21 Command Done - inline, status:%d \n", status));
++ /* fall through and return the non-pending status */
++ }
++ }
++
++ if (localIrqMasked) {
++ /* re-enable if we turned them off */
++ EnableHcdInterrupt(pHct, FROM_NORMAL);
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT16 command;
++
++ command = GET_SDCONFIG_CMD(pConfig);
++
++ switch (command){
++ case SDCONFIG_SDIO_REARM_INT:
++ pHct->SDIOIrqDetectArmed = TRUE;
++ /* re-enable IRQ detection */
++ UnmaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,FALSE);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++ /* get detect mode */
++ irqModeFlags = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21: 4 Bit IRQ mode \r\n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pHct->KeepClockOn = TRUE;
++ } else {
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21: 1 Bit IRQ mode \r\n"));
++ /* in 1 bit mode, the clock can be left off */
++ pHct->KeepClockOn = FALSE;
++ }
++ /* enable */
++ UnmaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,FALSE);
++ pHct->SDIOIrqDetectArmed = TRUE;
++ pHct->SDIOCardIrqDetectRequested = TRUE;
++ } else {
++ /* disable */
++ MaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,FALSE);
++ pHct->KeepClockOn = FALSE;
++ pHct->SDIOIrqDetectArmed = FALSE;
++ pHct->SDIOCardIrqDetectRequested = FALSE;
++ }
++ break;
++ case SDCONFIG_GET_WP:
++ if (IsSlotWPSet(pHct)) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ /* the first command will have the 80 clocks */
++ pHct->IssueInitClocks = TRUE;
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ /* reset the controller, there appears to be a FIFO problem when you switch
++ * between 4 and 1 bit modes, some residual data remains in the FIFO */
++ ResetController(pHct,TRUE,FROM_NORMAL);
++ SetBusMode(pHct, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ /* the slot just connects VCC straight to the slot nothing to adjust here */
++ DBG_PRINT(SDHC_TRACE_CONFIG, ("SDIO MX21 PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ *((CT_DEBUG_LEVEL *)pConfig->pData) = DBG_GET_DEBUG_LEVEL();
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_SET_DEBUG_LEVEL(*((CT_DEBUG_LEVEL *)pConfig->pData));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Local HCD: HcdConfig - bad command: 0x%X\n",command));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++void ResetController(PSDHCD_DRIVER_CONTEXT pHct, BOOL RestoreHcdSettings, BOOL FromIsr)
++{
++ INT i;
++
++ if (RestoreHcdSettings) {
++ /* disable interrupts, when a reset is applied some interrupts
++ * are unmasked */
++ DisableHcdInterrupt(pHct,FromIsr);
++ }
++ /* reset as per spec */
++ WRITE_HC_REG(pHct,SDHC_STR_STP_CLK_REG, SDHC_STR_STP_CLK_RESET);
++ WRITE_HC_REG(pHct,SDHC_STR_STP_CLK_REG, SDHC_STR_STP_CLK_RESET | SDHC_STR_STP_CLK_STOP);
++
++ /* eight register writes to finish reset cycle */
++ for (i = 0; i < 8; i++) {
++ WRITE_HC_REG(pHct,SDHC_STR_STP_CLK_REG, SDHC_STR_STP_CLK_STOP);
++ }
++ /* set base clock divisor */
++ WRITE_HC_REG(pHct,SDHC_CLK_RATE_REG, pHct->BaseClkDivisorReg);
++ /* set response and data timeouts */
++ WRITE_HC_REG(pHct, SDHC_CMD_RES_TO_REG, SDMMC_RESP_TIMEOUT_CLOCKS);
++ WRITE_HC_REG(pHct, SDHC_CMD_READ_TO_REG, SDMMC_DATA_TIMEOUT_CLOCKS);
++
++ MaskHcdIrq(pHct,SDHC_INT_MASK_ALL, FromIsr);
++
++ if (RestoreHcdSettings) {
++ EnableHcdInterrupt(pHct,FromIsr);
++ }
++
++ if (!RestoreHcdSettings) {
++ return;
++ }
++
++ /* restore the bus mode */
++ SetBusMode(pHct,&pHct->SavedBusMode);
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize host controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ int i;
++ int clkdivisor;
++ UINT32 actualBaseClk;
++
++ if (0 == pHct->Device.PeripheralClockRate) {
++ DBG_ASSERT(pHct->Device.PeripheralClockRate != 0);
++ return SDIO_STATUS_ERROR;
++ }
++
++ pHct->SDIOIrqDetectArmed = FALSE;
++ pHct->SDIOIrqMasked = FALSE;
++ pHct->SDIOCardIrqDetectRequested = FALSE;
++ pHct->KeepClockOn = FALSE;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MX21 SDIO Module Revision :0x%X \n",
++ READ_HC_REG(pHct, SDHC_REVISION_REG)));
++
++ clkdivisor = 1;
++ while (1) {
++ /* figure out the divisor to set module to <= 20Mhz */
++ actualBaseClk = pHct->Device.PeripheralClockRate/clkdivisor;
++ if (actualBaseClk <= SDHC_MODULE_MAX_CLK) {
++ break;
++ }
++ clkdivisor++;
++ }
++ /* clock divisor is 1 less */
++ clkdivisor--;
++
++ if (clkdivisor > 16) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Local HCD: HcdConfig - bad clk divisor: %d for base:%d\n",
++ clkdivisor,pHct->Device.PeripheralClockRate));
++ return SDIO_STATUS_ERROR;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MX21 Clock Base:%d Hz, Using Divisor:%d\n",
++ pHct->Device.PeripheralClockRate,clkdivisor));
++
++ /* save this for resets */
++ pHct->BaseClkDivisorReg = clkdivisor;
++
++ pHct->Hcd.MaxClockRate = actualBaseClk;
++ /* build the clock table */
++ /* the first entry is unity clock */
++ pHct->ValidClockEntries = 1;
++ pHct->ClockDivisorTable[0].ClockRate = actualBaseClk;
++ pHct->ClockDivisorTable[0].RegisterValue = 0;
++ /* the remaining entries are a divisor that is a power of 2 */
++ clkdivisor = 2;
++ for (i = 1; i < HCD_MAX_CLOCK_ENTRIES; i++) {
++ pHct->ClockDivisorTable[i].ClockRate = actualBaseClk/clkdivisor;
++ if (0 == pHct->ClockDivisorTable[i].ClockRate) {
++ break;
++ }
++ pHct->ClockDivisorTable[i].RegisterValue = 1 << (i - 1);
++ clkdivisor <<= 1;
++ pHct->ValidClockEntries++;
++ }
++
++ for (i = 0; i < pHct->ValidClockEntries; i++) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MX21 Clock Index:%d, Rate:%d Hz, CLKDIV:0x%X\n",
++ i,pHct->ClockDivisorTable[i].ClockRate,pHct->ClockDivisorTable[i].RegisterValue));
++ }
++
++ /* reset the controller */
++ ResetController(pHct,FALSE,FALSE);
++
++ MaskHcdIrq(pHct,SDHC_INT_MASK_ALL, FALSE);
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate MMC controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ MaskHcdIrq(pHct,SDHC_INT_MASK_ALL, FALSE);
++ ClockStartStop(pHct, CLOCK_OFF);
++}
++
++UINT32 GetValidStatusBitsForIRQ(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pCurrentReq)
++{
++ UINT32 statusBits = 0;
++ UINT32 ints;
++
++ ints = READ_HC_REG(pHct, SDHC_INT_MASK_REG);
++
++ if (ints & SDHC_INT_CARD_DETECT) {
++ statusBits |= SDHC_STATUS_CARD_PRESENT;
++ }
++
++ if (!(ints & SDHC_INT_SDIO_MASK)) {
++ statusBits |= SDHC_STATUS_SDIO_INT;
++ }
++
++ if (pCurrentReq != NULL) {
++ /* these require a current request */
++ /* command done */
++ if (!(ints & SDHC_INT_END_CMD_MASK)) {
++ statusBits |= SDHC_STATUS_END_CMD | SDHC_STATUS_RESP_ERRORS;
++ }
++ /* READ/WRITE processing */
++ if (IS_SDREQ_WRITE_DATA(pCurrentReq->Flags)) {
++ /* write data */
++ if (!(ints & SDHC_INT_BUFF_RDY_MASK)) {
++ statusBits |= SDHC_STATUS_FIFO_EMPTY;
++ }
++ if (!(ints & SDHC_INT_WRITE_DONE_MASK)) {
++ statusBits |= SDHC_STATUS_WRITE_DONE;
++ }
++ statusBits |= SDHC_STATUS_WRITE_CRC_ERROR;
++ } else {
++ if (!(ints & SDHC_INT_BUFF_RDY_MASK)) {
++ statusBits |= SDHC_STATUS_FIFO_FULL;
++ }
++ if (!(ints & SDHC_INT_DATA_TRANS_DONE_MASK)) {
++ statusBits |= SDHC_STATUS_READ_DONE;
++ }
++ statusBits |= SDHC_STATUS_READ_CRC_ERROR | SDHC_STATUS_READ_TIMEOUT;
++ }
++ }
++ DBG_PRINT(SDHC_TRACE_HC_INT, ("SDIO MX21 Valid Stats in IRQ:0x%X \n", statusBits));
++ return statusBits;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInterrupt - process controller interrupt
++ Input: pHct - HCD context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdInterrupt(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ UINT32 statReg,errors,validStatBits;
++ PSDREQUEST pReq;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(SDHC_TRACE_HC_INT, ("+SDIO MX21 HCD Int handler \n"));
++
++ errors = 0;
++
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++
++
++ while (1) {
++ /* get the status we care about */
++ statReg = READ_HC_REG(pHct,SDHC_STATUS_REG);
++ validStatBits = GetValidStatusBitsForIRQ(pHct,pReq);
++ DBG_PRINT(SDHC_TRACE_HC_INT, ("SDIO MX21 StatReg:0x%X IMASK:0x%X ValidBits:0x%X\n",
++ statReg, READ_HC_REG(pHct, SDHC_INT_MASK_REG), validStatBits));
++
++ /* keep only relevent status bits */
++ statReg &= validStatBits;
++
++ if (pHct->CmdProcessed) {
++ /* mask out command bit, this will stay set until the interrupt mask is written
++ * to or until the clock is stopped */
++ statReg &= ~SDHC_STATUS_END_CMD;
++ }
++
++ if (0 == statReg) {
++ break;
++ }
++
++ DBG_PRINT(SDHC_TRACE_HC_INT, ("SDIO MX21 After Mask: StatReg:0x%X \n", statReg));
++
++ if (statReg & SDHC_STATUS_SDIO_INT) {
++ DBG_PRINT(SDHC_TRACE_SDIO_INT, ("SDIO MX21 SDIO IRQ (STAT:0x%X:IMASK:0x%X)\n",
++ READ_HC_REG(pHct,SDHC_STATUS_REG),READ_HC_REG(pHct, SDHC_INT_MASK_REG)));
++ if (pHct->SDIOIrqMasked) {
++ DBG_ASSERT(FALSE);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 SDIO IRQ (STAT:0x%X:IMASK:0x%X)\n",
++ READ_HC_REG(pHct,SDHC_STATUS_REG),READ_HC_REG(pHct, SDHC_INT_MASK_REG)));
++ }
++ pHct->SDIOIrqDetectArmed = FALSE;
++ /* mask off */
++ MaskHcdIrq(pHct,SDHC_INT_SDIO_MASK,TRUE);
++ QueueEventResponse(pHct, WORK_ITEM_SDIO_IRQ);
++ }
++
++ if (NULL == pReq) {
++ /* might just be an SDIO irq */
++ break;
++ }
++
++ if (statReg & SDHC_STATUS_END_CMD) {
++ /* set flag to mask END_CMD status bit */
++ pHct->CmdProcessed = TRUE;
++ /* only care about response errors */
++ status = ProcessCommandDone(pHct,
++ pReq,
++ (statReg & SDHC_STATUS_RESP_ERRORS),
++ TRUE);
++ if (status != SDIO_STATUS_PENDING) {
++ /* no data phase or the command failed, get out */
++ break;
++ }
++ }
++
++ /* if we get here we are processing interrupts associated with DATA */
++
++ /* check for any read/write errors */
++ if (statReg & SDHC_STATUS_RD_WR_ERRORS) {
++ status = TranslateHCError(pHct,(statReg & SDHC_STATUS_RD_WR_ERRORS));
++ break;
++ }
++
++ /* at this point, there are no status errors */
++
++ if (statReg & SDHC_STATUS_FIFO_EMPTY) {
++ /* write use Fifo EMPTY signal */
++ DBG_ASSERT(SDHC_DMA_NONE == pHct->DmaType);
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* transfer data */
++ if (HcdTransferTxData(pHct, pReq)) {
++ MaskHcdIrq(pHct,SDHC_INT_BUFF_RDY_MASK, FROM_ISR);
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 TX Fifo writes done. Waiting for WRITE_DONE \n"));
++ }
++ }
++
++ if (statReg & SDHC_STATUS_FIFO_FULL) {
++ /* READs use Fifo FULL signal */
++ DBG_ASSERT(SDHC_DMA_NONE == pHct->DmaType);
++ DBG_ASSERT(!IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* unload fifo */
++ HcdTransferRxData(pHct,pReq);
++ if (pReq->DataRemaining < pHct->FifoDepth) {
++ UINT32 temp = 0;
++ MaskHcdIrq(pHct,SDHC_INT_BUFF_RDY_MASK, FROM_ISR);
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 RX Fifo reads done. waiting for READ_DONE \n"));
++
++ if (pReq->DataRemaining & 0x1) {
++ DBG_PRINT(SDHC_TRACE_DATA,
++ ("SDIO MX21 RX - Non-WORD aligned remaining bytes:%d \n",pReq->DataRemaining));
++ WAIT_FOR_HC_STATUS(pHct,
++ SDHC_STATUS_READ_DONE | SDHC_STATUS_FIFO_FULL,
++ &temp,
++ SDHC_STATUS_RESP_ERRORS | SDHC_STATUS_RD_WR_ERRORS,
++ status,
++ POLL_TIMEOUT);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 RX Fifo READ DONE Timeout! -- \n"));
++ }
++ if (temp & SDHC_STATUS_RD_WR_ERRORS) {
++ status = TranslateHCError(pHct,(temp & SDHC_STATUS_RD_WR_ERRORS));
++ break;
++ }
++ status = SDIO_STATUS_SUCCESS;
++ statReg |= SDHC_STATUS_READ_DONE;
++ }
++ /* fall through and let READ done processing continue */
++ }
++ }
++
++ if (statReg & SDHC_STATUS_READ_DONE) {
++ DBG_ASSERT(!IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* read operation is done */
++ if (SDHC_DMA_NONE == pHct->DmaType) {
++ if (pReq->DataRemaining) {
++ /* there was a partial FIFO, we need to drain it */
++ HcdTransferRxData(pHct,pReq);
++ /* this should drain it */
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ }
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 READ Transfer done. \n"));
++ break;
++ }
++
++ if (statReg & SDHC_STATUS_WRITE_DONE) {
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* write operation is done */
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(SDHC_TRACE_DATA, ("SDIO MX21 WRITE Transfer done. \n"));
++ break;
++ }
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* set the status */
++ pReq->Status = status;
++ EndHCTransfer(pHct,pReq,FROM_ISR);
++ if ((DBG_GET_DEBUG_LEVEL() >= SDHC_TRACE_DATA_DUMP) && SDIO_SUCCESS(status) &&
++ IS_SDREQ_DATA_TRANS(pReq->Flags) && !IS_SDREQ_WRITE_DATA(pReq->Flags) &&
++ (pHct->DmaType != SDHC_DMA_SCATTER_GATHER)) {
++ SDLIB_PrintBuffer(pReq->pDataBuffer,(pReq->BlockLen*pReq->BlockCount),"SDIO MX21 - RX DataDump");
++ }
++ if (SDHC_DMA_NONE == pHct->DmaType) {
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* the request used DMA, we need to let the OS-specific code deal with DMA */
++ CompleteRequestSyncDMA(pHct,pReq,TRUE);
++ }
++ }
++
++ DBG_PRINT(SDHC_TRACE_HC_INT, ("-SDIO MX21 HCD Int handler \n"));
++ return TRUE;
++}
++
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,210 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_mx21.h
++
++ at abstract: include file for Freescale MX21 SDIO bus host controller, OS independent code
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_MX21HCD_H___
++#define __SDIO_MX21HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_mx21_linux.h"
++
++enum SDHC_TRACE_ENUM {
++ SDHC_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ SDHC_TRACE_SDIO_INT = (SDDBG_TRACE + 2),
++ SDHC_TRACE_DATA,
++ SDHC_TRACE_DMA_DEBUG,
++ SDHC_TRACE_REQUESTS,
++ SDHC_TRACE_DATA_DUMP,
++ SDHC_TRACE_CONFIG,
++ SDHC_TRACE_HC_INT,
++ SDHC_TRACE_LAST
++};
++
++typedef enum _SDHC_DMA_TYPE {
++ SDHC_DMA_NONE = 0,
++ SDHC_DMA_COMMON_BUFFER = 1,
++ SDHC_DMA_SCATTER_GATHER
++}SDHC_DMA_TYPE, *PSDHC_DMA_TYPE;
++
++#define SDHC_MODULE_MAX_CLK 20000000
++#define SDHC_CONTROLLER1_BASE_ADDRESS 0x10013000
++#define SDHC_CONTROLLER2_BASE_ADDRESS 0x10014000
++#define SDHC_CONTROLLER_ADDRESS_LENGTH 0x1000
++
++#define SDIO_SDHC_MAX_BYTES_PER_BLOCK 2048
++
++#define SDIO_SDHC_MAX_BLOCKS 0xFFFF
++
++#define HCD_MAX_CLOCK_ENTRIES 8
++typedef struct _HCD_CLOCK_TBL_ENTRY {
++ SD_BUSCLOCK_RATE ClockRate; /* rate */
++ UINT16 RegisterValue;
++}HCD_CLOCK_TBL_ENTRY;
++
++/* register definitions */
++#define SDHC_STR_STP_CLK_REG 0x00
++#define SDHC_STR_STP_CLK_RESET (1 << 3)
++#define SDHC_STR_STP_CLK_ENABLE (1 << 2)
++#define SDHC_STR_STP_CLK_START (1 << 1)
++#define SDHC_STR_STP_CLK_STOP (1 << 0)
++
++#define SDHC_STATUS_REG 0x04
++#define SDHC_STATUS_CARD_PRESENT (1 << 15)
++#define SDHC_STATUS_SDIO_INT (1 << 14)
++#define SDHC_STATUS_END_CMD (1 << 13 )
++#define SDHC_STATUS_WRITE_DONE (1 << 12)
++#define SDHC_STATUS_READ_DONE (1 << 11)
++#define SDHC_STATUS_WRITE_CRC_CODE_MASK (3 << 9)
++#define SDHC_STATUS_CLK_RUN (1 << 8)
++#define SDHC_STATUS_FIFO_FULL (1 << 7)
++#define SDHC_STATUS_FIFO_EMPTY (1 << 6)
++#define SDHC_STATUS_RESP_CRC_ERROR (1 << 5)
++#define SDHC_STATUS_READ_CRC_ERROR (1 << 3)
++#define SDHC_STATUS_WRITE_CRC_ERROR (1 << 2)
++#define SDHC_STATUS_RESP_TIMEOUT (1 << 1)
++#define SDHC_STATUS_READ_TIMEOUT (1 << 0)
++
++#define SDHC_STATUS_RESP_ERRORS (SDHC_STATUS_RESP_CRC_ERROR | SDHC_STATUS_RESP_TIMEOUT)
++#define SDHC_STATUS_RD_WR_ERRORS (SDHC_STATUS_READ_CRC_ERROR | SDHC_STATUS_READ_TIMEOUT |\
++ SDHC_STATUS_WRITE_CRC_ERROR)
++
++#define SDHC_CLK_RATE_REG 0x08
++#define SDHC_CLK_RATE_PRESCALE_SHIFT 4
++#define SDHC_CLK_RATE_PRESCALE_MASK (0xFFF << SDHC_CLK_RATE_PRESCALE_SHIFT)
++
++#define SDHC_CMD_DAT_REG 0x0C
++#define SDHCD_CMD_DAT_BUS_1BIT 0x00
++#define SDHCD_CMD_DAT_BUS_4BIT (0x2 << 8)
++#define SDHCD_CMD_DAT_INIT_CLKS (1 << 7)
++#define SDHCD_CMD_DAT_RESP_BUSY (1 << 6) /* undocumented bit */
++#define SDHCD_CMD_DAT_DATA_WRITE (1 << 4)
++#define SDHCD_CMD_DAT_DATA_ENABLE (1 << 3)
++#define SDHCD_CMD_DAT_RESP_NO_RESP 0x00
++#define SDHCD_CMD_DAT_RESP_R1R5R6 0x01
++#define SDHCD_CMD_DAT_RESP_R2 0x02
++#define SDHCD_CMD_DAT_RESP_R3R4 0x03
++
++#define SDHC_CMD_RES_TO_REG 0x10
++#define SDMMC_RESP_TIMEOUT_CLOCKS 64
++
++#define SDHC_CMD_READ_TO_REG 0x14
++#define SDMMC_DATA_TIMEOUT_CLOCKS 0xFFFF
++
++#define SDHC_BLK_LEN_REG 0x18
++#define SDHC_NOB_REG 0x1C
++
++#define SDHC_REVISION_REG 0x20
++
++#define SDHC_INT_MASK_REG 0x24
++#define SDHC_INT_CARD_DETECT (1 << 15)
++#define SDHC_INT_SDIO_INT_WAKEUP (1 << 14)
++#define SDHC_INT_DAT0_ENABLE (1 << 5)
++
++#define SDHC_INT_SDIO_MASK (1 << 4)
++#define SDHC_INT_BUFF_RDY_MASK (1 << 3)
++#define SDHC_INT_END_CMD_MASK (1 << 2)
++#define SDHC_INT_WRITE_DONE_MASK (1 << 1)
++#define SDHC_INT_DATA_TRANS_DONE_MASK (1 << 0)
++#define SDHC_INT_MASK_ALL 0x1F
++
++#define SDHC_CMD_REG 0x28
++#define SDHC_ARGH_REG 0x2C
++#define SDHC_ARGL_REG 0x30
++#define SDHC_RES_FIFO_REG 0x34
++#define SDHC_BUF_ACCESS_REG 0x38
++
++#define SDHC_MAX_FIFO_1BIT 16
++#define SDHC_MAX_FIFO_4BIT 64
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDHCD Hcd; /* HCD description for bus driver */
++ SDHCD_DEVICE Device; /* the single device's info */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL KeepClockOn;
++ BOOL SD4Bit; /* 4 bit bus mode */
++ BOOL CmdProcessed; /* command phase was processed */
++ BOOL IssueInitClocks;
++ UINT32 FifoDepth; /* FIFO depth for the bus mode */
++ SDHC_DMA_TYPE DmaType;
++ INT ValidClockEntries;
++ HCD_CLOCK_TBL_ENTRY ClockDivisorTable[HCD_MAX_CLOCK_ENTRIES];
++ BOOL SDIOIrqMasked;
++ BOOL SDIOIrqDetectArmed;
++ BOOL SDIOCardIrqDetectRequested;
++ INT BaseClkDivisorReg;
++ SDCONFIG_BUS_MODE_DATA SavedBusMode;
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++BOOL HcdInterrupt(PSDHCD_DRIVER_CONTEXT pHcdContext);
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHcdContext, INT WorkItemID);
++BOOL GetGpioPinLevel(PSDHCD_DRIVER_CONTEXT pHcdContext, INT Pin);
++void ModifyCSForSPIIntDetection(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable);
++void UnmaskHcdIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr);
++void MaskHcdIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr);
++void SlotPowerOnOff(PSDHCD_DRIVER_CONTEXT pHct , BOOL On);
++BOOL IsSlotWPSet(PSDHCD_DRIVER_CONTEXT pHct);
++SDIO_STATUS SetUpHCDDMA(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext);
++SDIO_STATUS InitMX21(PSDHCD_DRIVER_CONTEXT pHct);
++void DeinitMX21(PSDHCD_DRIVER_CONTEXT pHct);
++void CompleteRequestSyncDMA(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq, BOOL FromIsr);
++void DisableHcdInterrupt(PSDHCD_DRIVER_CONTEXT pHct, BOOL FromIsr);
++void EnableHcdInterrupt(PSDHCD_DRIVER_CONTEXT pHct, BOOL FromIsr);
++BOOL IsDMAAllowed(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq);
++void DumpDmaInfo(PSDHCD_DRIVER_CONTEXT pHct);
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++#endif
+Index: linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,105 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_mx21_linux.h
++
++ at abstract: include file for MX21 local bus host controller, linux dependent code
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <asm/irq.h>
++
++#define SDHC_DMA_COMMON_BUFFER_SIZE 16*1024
++#define SDHC_MAX_BYTES_PER_DMA_DESCRIPTOR 16*1024*1024 /* 16MB per descriptor */
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef void (*PDMA_TRANSFER_COMPLETION)(PVOID,SDIO_STATUS,BOOL);
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++/* device data*/
++typedef struct _SDHCD_DEVICE {
++ OS_PNPDEVICE HcdDevice; /* the OS device for this HCD */
++ OS_PNPDRIVER HcdDriver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION Dma; /* driver DMA description */
++ POS_PNPDEVICE pBusDevice; /* our device registered with bus driver */
++ UINT ControllerInterrupt; /* controller interrupt */
++ UINT8 InitStateMask;
++#define SDHC_INTERRUPT_INIT 0x01
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x20
++#define SDHC_DMA_ALLOCATED 0x40
++ SDHCD_MEMORY ControlRegs; /* memory addresses of device */
++ spinlock_t Lock; /* lock against the ISR */
++ BOOL StartUpCheck;
++ PDMA_TRANSFER_COMPLETION pDmaCompletion;
++ PVOID pContext;
++ PUINT8 pDmaCommonBuffer; /* common buffer for DMA */
++ DMA_ADDRESS DmaCommonBufferPhys; /* physical address for common buffer */
++ UINT32 DmaCommonBufferSize; /* size of DMA common buffer */
++ INT DmaChannel; /* DMA channel to use */
++ BOOL DmaSgMapped;
++ INT LastRxCopy;
++ UINT32 PeripheralClockRate;
++ UINT32 DmaHclkErrata; /* see errata 13 in MX21 chip errata doc */
++ BOOL LocalIrqDisabled;
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++#define OsMicroDelay(x) udelay((x))
++
++#define READ_HC_REG(pC, OFFSET) \
++ _READ_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET))
++#define WRITE_HC_REG(pC, OFFSET, VALUE) \
++ _WRITE_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET),(VALUE))
++
++#define WRITE_HC_REG_D(pC, OFFSET, VALUE) \
++ { WRITE_HC_REG(pC, OFFSET, VALUE);OsMicroDelay(1);}
++
++#define GET_HC_REG_BASE(pC) ((UINT32)((pC)->Device.ControlRegs.pMapped))
++
++#endif
+Index: linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/mx21/sdio_mx21_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,435 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Linux MX21 Local Bus SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++
++#define DBG_DECLARE 7;
++#include <linux/sdio/ctsystem.h>
++#include "sdio_mx21.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#define DESCRIPTION "SDIO MX21 Local Bus HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId);
++static void Remove(struct pnp_dev *pBusDevice);
++#else
++static int Probe(POS_PNPDEVICE pBusDevice, const PUINT pId);
++static void Remove(POS_PNPDEVICE pBusDevice);
++#endif
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++
++#define BASE_HCD_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | \
++ SDHCD_ATTRIB_SLOT_POLLING)
++
++#define DEFAULT_ATTRIBUTES (BASE_HCD_ATTRIBUTES | SDHCD_ATTRIB_BUS_4BIT)
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++static SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .Hcd.pName = "sdio_mx21hcd",
++ .Hcd.Version = CT_SDIO_STACK_VERSION_CODE,
++ .Hcd.SlotNumber = 0,
++ .Hcd.Attributes = DEFAULT_ATTRIBUTES,
++ .Hcd.MaxBytesPerBlock = SDIO_SDHC_MAX_BYTES_PER_BLOCK,
++ .Hcd.MaxBlocksPerTrans = SDIO_SDHC_MAX_BLOCKS,
++ .Hcd.MaxSlotCurrent = 500, /* 1/2 amp */
++ .Hcd.SlotVoltageCaps = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.MaxClockRate = 20000000,
++ .Hcd.pContext = &HcdContext,
++ .Hcd.pRequest = HcdRequest,
++ .Hcd.pConfigure = HcdConfig,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ .Device.HcdDevice.name = "sdio_mx21_hcd",
++ .Device.HcdDriver.name = "sdio_mx21_hcd",
++ .Device.HcdDriver.probe = Probe,
++ .Device.HcdDriver.remove = Remove,
++#endif
++ .Device.Dma.Mask = 0xFFFFFFFF, /* any address */
++ .Device.Dma.Flags = SDDMA_DESCRIPTION_FLAG_DMA,
++ .Device.Dma.MaxBytesPerDescriptor = SDHC_MAX_BYTES_PER_DMA_DESCRIPTOR, /* max per descriptor */
++ .Device.Dma.AddressAlignment = 0x0, /* no illegal bits, buffers address can be on any boundary*/
++ .Device.Dma.LengthAlignment = 0x0, /* no illegal bits, buffer lengths can be any byte count */
++ .Device.Dma.MaxDescriptors = 1, /* only 1 scatter gather descriptor */
++};
++
++/* work queues */
++static struct work_struct iocomplete_work;
++static struct work_struct sdioirq_work;
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId)
++#else
++static int Probe(POS_PNPDEVICE pBusDevice, const PUINT pId)
++#endif
++{
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status;
++ PSDHCD_DRIVER_CONTEXT pHct = &HcdContext; /* for now , only 1 instance */
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MX21 Local HCD: Probe \n"));
++
++ do {
++
++ pHct->Device.pBusDevice = pBusDevice;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ pHct->Hcd.pDevice = &pBusDevice->dev;
++#endif
++
++ pHct->Hcd.pModule = THIS_MODULE;
++ pHct->Device.ControlRegs.Raw = SDHC_CONTROLLER1_BASE_ADDRESS;
++ pHct->Device.ControlRegs.Length = SDHC_CONTROLLER_ADDRESS_LENGTH;
++
++ spin_lock_init(&pHct->Device.Lock);
++
++ status = InitMX21(pHct);
++
++ if (!SDIO_SUCCESS(status)) {
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ status = HcdInitialize(pHct);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Probe - failed to init HW, status =%d\n", status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHct->Device.InitStateMask |= SDHC_HW_INIT;
++
++ /* register with the SDIO bus driver */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pHct->Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Probe - failed to register with host, status =%d\n",
++ status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHct->Device.InitStateMask |= SDHC_REGISTERED;
++
++ } while (FALSE);
++
++ if (err < 0) {
++ Remove(pBusDevice); /* TODO: the cleanup should not really be done in the Remove function */
++ } else {
++#ifdef USE_CARD_DETECT_HW
++ pHct->Device.StartUpCheck = TRUE;
++ /* queue the work item test the slot */
++ if (!SDIO_SUCCESS(QueueEventResponse(pHct, WORK_ITEM_CARD_DETECT))) {
++ /* failed */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Probe - queue event failed\n"));
++ }
++#endif
++ DBG_PRINT(SDDBG_ERROR, ("SDIO MX21 Probe - HCD ready! \n"));
++ }
++ return err;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static void Remove(struct pnp_dev *pBusDevice)
++#else
++static void Remove(POS_PNPDEVICE pBusDevice)
++#endif
++{
++ PSDHCD_DRIVER_CONTEXT pHct = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO MX21 Local HCD: Remove - removing device\n"));
++
++ if (pHct->Device.InitStateMask & SDHC_REGISTERED) {
++ /* unregister from the bus driver */
++ SDIO_UnregisterHostController(&pHct->Hcd);
++ pHct->Device.InitStateMask &= ~SDHC_REGISTERED;
++ }
++
++ if (pHct->Device.InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pHct);
++ pHct->Device.InitStateMask &= ~SDHC_HW_INIT;
++ }
++
++ DeinitMX21(pHct);
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO MX21 Local HCD: Remove\n"));
++}
++
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHct, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ work = &iocomplete_work;
++ break;
++#ifdef USE_CARD_DETECT_HW
++ case WORK_ITEM_CARD_DETECT:
++ work = &carddetect_work;
++ break;
++#endif
++ case WORK_ITEM_SDIO_IRQ:
++ work = &sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_PENDING;
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)context;
++
++ SDIO_HandleHcdEvent(&pHct->Hcd, EVENT_HCD_TRANSFER_DONE);
++}
++
++#ifdef USE_CARD_DETECT_HW
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)context;
++ HCD_EVENT event;
++
++ event = EVENT_HCD_NOP;
++ //SDHC_TRACE_CARD_INSERT
++
++ DBG_PRINT(SDDBG_TRACE, ("+ SDIO MX21 Card Detect Work Item \n"));
++
++ if (!pHct->CardInserted) {
++ DBG_PRINT(SDDBG_TRACE, ("Delaying to debounce card... \n"));
++ /* sleep for slot debounce if there is no card */
++ msleep(SDHC_SLOT_DEBOUNCE_MS);
++ }
++
++ /* check board status pin */
++ if (IsCardInserted(pHct)) {
++ if (!pHct->CardInserted) {
++ pHct->CardInserted = TRUE;
++ event = EVENT_HCD_ATTACH;
++ DBG_PRINT(SDDBG_TRACE, (" Card Inserted! \n"));
++ /* disable insert */
++ disable_irq(pHct->Device.CanomralrdInsertInterrupt);
++ /* enable remove */
++ enable_irq(pHct->Device.CardRemoveInterrupt);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Card detect interrupt , already inserted card! \n"));
++ }
++ } else {
++ if (pHct->CardInserted) {
++ event = EVENT_HCD_DETACH;
++ pHct->CardInserted = FALSE;
++ DBG_PRINT(SDDBG_TRACE, (" Card Removed! \n"));
++ /* disable remove */
++ disable_irq(pHct->Device.CardRemoveInterrupt);
++ /* enable insert */
++ enable_irq(pHct->Device.CardInsertInterrupt);
++ } else {
++ if (pHct->Device.StartUpCheck) {
++ pHct->Device.StartUpCheck = FALSE;
++ DBG_PRINT(SDDBG_TRACE, ("No card at power up. \n"));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, nomral("Card detect interrupt , already removed card! \n"));
++ }
++ }
++ }
++
++ if (event != EVENT_HCD_NOP) {
++ SDIO_HandleHcdEvent(&pHct->Hcd, event);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("- SDIO MX21 Card Detect Work Item \n"));
++}
++
++
++BOOL IsCardInserted(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ // TODO
++ return TRUE;
++}
++
++#endif
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)context;
++ DBG_PRINT(SDHC_TRACE_SDIO_INT, ("SDIO MX21: hcd_sdioirq_wqueue_handler \n"));
++ SDIO_HandleHcdEvent(&pHct->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskHcdIrq - Un mask a HCD interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void UnmaskHcdIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr)
++{
++ ULONG flags = 0;
++ UINT32 ints;
++
++ if (!FromIsr) {
++ spin_lock_irqsave(&pHct->Device.Lock,flags);
++ }
++ if (Mask & SDHC_INT_SDIO_MASK) {
++ pHct->SDIOIrqMasked = FALSE;
++ }
++
++ ints = READ_HC_REG(pHct, SDHC_INT_MASK_REG);
++ ints &= ~Mask;
++ WRITE_HC_REG(pHct, SDHC_INT_MASK_REG, ints);
++ if (!FromIsr) {
++ spin_unlock_irqrestore(&pHct->Device.Lock,flags);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskHcdIrq - Mask Hcd interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void MaskHcdIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr)
++{
++ UINT32 ints;
++ ULONG flags = 0;
++
++ if (!FromIsr) {
++ spin_lock_irqsave(&pHct->Device.Lock,flags);
++ }
++ if (Mask & SDHC_INT_SDIO_MASK) {
++ pHct->SDIOIrqMasked = TRUE;
++ }
++ ints = READ_HC_REG(pHct, SDHC_INT_MASK_REG);
++ ints |= Mask;
++ WRITE_HC_REG(pHct, SDHC_INT_MASK_REG, ints);
++ if (!FromIsr) {
++ spin_unlock_irqrestore(&pHct->Device.Lock,flags);
++ }
++}
++
++
++/*
++ * module init
++*/
++static int __init sdio_local_hcd_init(void) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ SDIO_STATUS status;
++#endif
++ INIT_WORK(&iocomplete_work, hcd_iocomplete_wqueue_handler, &HcdContext);
++ INIT_WORK(&sdioirq_work, hcd_sdioirq_wqueue_handler, &HcdContext);
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO MX21 Local HCD: loaded\n"));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ status = SDIO_BusAddOSDevice(&HcdContext.Driver.Dma, &HcdContext.Driver.HcdDriver, &HcdContext.Driver.HcdDevice);
++ return SDIOErrorToOSError(status);
++#else
++ DBG_PRINT(SDDBG_TRACE, ("SDIO MX21 Local HCD: sdio_local_hcd_init exit\n"));
++ /* 2.4 */
++ return Probe(NULL, NULL);
++#endif
++
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_local_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO MX21 Local HCD: unloaded\n"));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ SDIO_BusRemoveOSDevice(&HcdContext.Driver.HcdDriver, &HcdContext.Driver.HcdDevice);
++#else
++ /* 2.4 */
++ Remove(NULL);
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO MX21 Local HCD: leave sdio_local_hcd_cleanup\n"));
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_local_hcd_init);
++module_exit(sdio_local_hcd_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/hcd/omap/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,3 @@
++# SDIO omap host controller makefile
++sdio_omap_hcd-objs := sdio_hcd_os.o sdio_hcd_os_2_6.o
++obj-$(CONFIG_ARCH_OMAP) += sdio_hcd.o
+Index: linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1337 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd.c
++
++ at abstract: Texas Instruments OMAP native Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDOMAPHCD
++#include "sdio_omap_hcd.h"
++
++#define FROM_ISR TRUE
++#define FROM_NORMAL FALSE
++
++void EndHCTransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL FromIsr);
++void ResetController(PSDHCD_DEVICE pDevice, BOOL Restore, BOOL FromIsr);
++
++#ifdef OMAP_REQ_PROCESSING_USE_CLOCK_CONTROL
++ /* control clock during request processing */
++#define ReqProcClkStartStop(p,on) ClockStartStop((p),(on))
++#else
++ /* let clock run free */
++#define ReqProcClkStartStop(p,on)
++#endif
++
++#define OMAP_COMMAND_DONE_POLLING 2000000
++#define OMAP_SHORT_TRANSFER_DONE_POLLING 3000000
++
++#define WAIT_FOR_HC_STATUS(pHct,DoneMask,Error,ErrorMask,Status,Timeout) \
++{ \
++ INT _timeoutCnt = (Timeout); \
++ (Status) = SDIO_STATUS_SUCCESS; \
++ while((_timeoutCnt > 0) && \
++ !(READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (DoneMask)) && \
++ !((Error) = READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (ErrorMask))){_timeoutCnt--;} \
++ (Error) = READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (ErrorMask); \
++ if (0 == _timeoutCnt) {(Status) = SDIO_STATUS_DEVICE_ERROR; \
++ DBG_PRINT(SDDBG_ERROR, \
++ ("SDIO OMAP - status timeout, waiting for (mask=0x%X) (stat=0x%X)\n",\
++ (UINT)(DoneMask), READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS))); \
++ DBG_ASSERT(FALSE);} \
++}
++
++#define SetFifoAFL(pHct,Depth) \
++{ \
++ UINT16 fifoSettings = (Depth)/2; \
++ if (fifoSettings > 0) {fifoSettings--;} \
++ fifoSettings = ((fifoSettings) << OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT) & \
++ OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK; \
++ WRITE_HOST_REG16((pHct), OMAP_REG_MMC_BUFFER_CONFIG, fifoSettings); \
++}
++
++#define SetFifoAEL(pHct,Depth) \
++{ \
++ UINT16 fifoSettings = (Depth)/2; \
++ if (fifoSettings > 0) {fifoSettings--;} \
++ fifoSettings = ((fifoSettings) << OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT) & \
++ OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK; \
++ WRITE_HOST_REG16((pHct), OMAP_REG_MMC_BUFFER_CONFIG, fifoSettings); \
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pDevice - device context
++ pReq - the request
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetResponseData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT wordCount;
++ INT byteCount;
++ UINT16 readBuffer[8];
++ UINT ii;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return;
++ }
++
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES - 1;
++ wordCount = (byteCount + 1) / 2;
++ /* move data into read buffer */
++ for (ii = 0; ii < wordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_RESPONSE0+(ii*4));
++ }
++ memcpy(&pReq->Response[0],readBuffer,byteCount);
++ } else {
++ wordCount = (byteCount + 1) / 2;
++
++ /* move data into read buffer */
++ for (ii = 0; ii < wordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_RESPONSE6+(ii*4));
++ }
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++ }
++
++ if (DBG_GET_DEBUG_LEVEL() >= OMAP_TRACE_REQUESTS) {
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO OMAP - Response Dump");
++ }
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ DumpCurrentRequestInfo - debug dump
++ Input: pDevice - device context
++ Output:
++ Return:
++ Notes: This function debug prints the current request
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void DumpCurrentRequestInfo(PSDHCD_DEVICE pDevice)
++{
++ if (pDevice->Hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - Current Request Command:%d, ARG:0x%8.8X\n",
++ pDevice->Hcd.pCurrentRequest->Command, pDevice->Hcd.pCurrentRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pDevice->Hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pDevice->Hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ pDevice->Hcd.pCurrentRequest->BlockCount,
++ pDevice->Hcd.pCurrentRequest->BlockLen,
++ pDevice->Hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateSDError - check for an SD error
++ Input: pDevice - device context
++ Status - error interrupt status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateSDError(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, UINT16 Status)
++{
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CERR) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP TranslateSDError : Warning command response has error bits set\n"));
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CTO) {
++ if (!((pReq->Command == 5) || (pReq->Command == 55) || (pReq->Command == 1))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Command Timeout: CMD:%d\n",pReq->Command));
++ }
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP TranslateSDError : current controller status: 0x%X\n",
++ READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS)));
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CCRC) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : command CRC error\n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_DCRC) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : write data CRC error\n"));
++ return SDIO_STATUS_BUS_WRITE_ERROR;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : read data CRC error\n"));
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ }
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_DTO) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : data timeout\n"));
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - untranslated error 0x%X\n", (UINT)Status));
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - SD clock control
++ Input: pDevice - device object
++ On - turn on or off (TRUE/FALSE)
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_DEVICE pDevice, BOOL On)
++{
++ UINT16 state;
++
++ DBG_PRINT(OMAP_TRACE_CLOCK, ("SDIO OMAP - ClockStartStop, %d\n", (UINT)On));
++
++ state = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG);
++ if (On) {
++ ClockEnable(pDevice, TRUE);
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ state |= pDevice->Clock;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ } else {
++ ClockEnable(pDevice, FALSE);
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pDevice - device object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DEVICE pDevice, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int ii;
++ int clockIndex;
++ UINT16 state = 0;
++ UINT32 rate;
++
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetBusMode\n"));
++
++ /* set clock index to the end max. divide */
++ pMode->ActualClockRate = (pDevice->BaseClock) / OMAP_MAX_CLOCK_DIVIDE;
++ clockIndex = OMAP_MAX_CLOCK_DIVIDE;
++ for (ii = 1; ii <= OMAP_MAX_CLOCK_DIVIDE ; ii++) {
++ rate = pDevice->BaseClock / ii;
++ if (pMode->ClockRate >= rate) {
++ pMode->ActualClockRate = rate;
++ clockIndex = ii;
++ break;
++ }
++ }
++
++ state = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG);
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_4BIT;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ state |= OMAP_REG_MMC_MODULE_CONFIG_4BIT;
++ break;
++ default:
++ break;
++ }
++
++ pDevice->Clock = clockIndex;
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ state |= pDevice->Clock;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ MicroDelay(pDevice, 50);
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetBusMode Clock: %d Khz, ClockRate %d (%d) state:0x%X\n",
++ pMode->ActualClockRate, pMode->ClockRate, clockIndex, (UINT)state));
++}
++
++/*
++ * SetDataTimeout - set timeout for data transfers
++*/
++static void SetDataTimeout(PSDHCD_DEVICE pDevice, UINT TimeOut)
++{
++ UINT sdreg;
++ UINT to = TimeOut;
++
++ /* Check if we need to use timeout multiplier register */
++ sdreg = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ if (TimeOut > 0xFFFF) {
++ sdreg |= OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE;
++ to /= 1024;
++ } else {
++ sdreg &= ~OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE;
++ }
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetDataTimeout Timeout: %d, mode: 0x%x, to: 0x%x\n",
++ TimeOut, sdreg, to));
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, sdreg);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_DATA_READ_TIMEOUT, to);
++}
++
++/* DMA completion routine */
++void DMACompletion(PVOID pContext, SDIO_STATUS status, BOOL FromIsr)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pContext;
++ PSDREQUEST pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP (%s) (%s) DMA transfer failed, status: %d\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ (OMAP_DMA_COMMON == pDevice->DmaMode) ? "Common-Buffer" : "Direct",
++ status));
++ } else {
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP (%s) (%s) DMA transfer completed \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ (OMAP_DMA_COMMON == pDevice->DmaMode) ? "Common-Buffer" : "Direct"));
++ }
++ /* clear the any TXDE RXDE bits */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, 0);
++ CompleteRequestSyncDMA(pDevice, pReq, status);
++ return;
++}
++
++/* transfer a FIFO worth of data, returns TRUE of all data was transfered */
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT16 *pFifo;
++
++ pFifo = (volatile UINT16 *)(GET_HC_REG_BASE(pDevice) + OMAP_REG_MMC_DATA_ACCESS);
++
++ /* if we get called here because of an AEL interrupt, we know we have
++ * OMAP_MMC_FIFO_SIZE - OMAP_MMC_AEL_FIFO_THRESH room in the fifo to store more data */
++ dataCopy = min(pReq->DataRemaining,(UINT32)(OMAP_MMC_FIFO_SIZE - OMAP_MMC_AEL_FIFO_THRESH));
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++
++ /* copy to fifo */
++ while (dataCopy) {
++ data = *pBuf;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ data |= ((UINT16)*pBuf) << 8;
++ dataCopy--;
++ pBuf++;
++ }
++ *pFifo = data;
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Pending TX Remaining: %d \n",pReq->DataRemaining));
++
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++/* transfer a FIFO worth of data */
++BOOL HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL Flush)
++{
++
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT16 *pFifo;
++
++ pFifo = (volatile UINT16 *)(GET_HC_REG_BASE(pDevice) + OMAP_REG_MMC_DATA_ACCESS);
++
++ if (Flush) {
++ dataCopy = min(pReq->DataRemaining,(UINT32)OMAP_MMC_FIFO_SIZE);
++ } else {
++ /* each time we are called, we know we have at least a threshold's worth of data */
++ dataCopy = min(pReq->DataRemaining,(UINT32)OMAP_MMC_AFL_FIFO_THRESH);
++ }
++ /* get where we are */
++ pBuf = (PUINT8)pReq->pHcdContext;
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++
++ /* copy from fifo */
++ while (dataCopy) {
++ data = *pFifo;
++ *pBuf = (UINT8)data;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ *pBuf = (UINT8)(data >> 8);
++ pBuf++;
++ dataCopy--;
++ }
++ }
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Pending RX Remaining: %d \n",pReq->DataRemaining));
++
++ if (pReq->DataRemaining < OMAP_MMC_AFL_FIFO_THRESH) {
++ return TRUE;
++ }
++
++ return FALSE;
++}
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ BOOL FromIsr)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 irqUnmask = 0;
++
++ do {
++
++ /* get the response data for the command */
++ GetResponseData(pDevice, pReq);
++
++ /* check for data */
++ if (!IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ break;
++ }
++
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pDevice->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (pDevice->ShortTransfer) {
++ UINT16 hwErrors;
++ UINT16 waitMask;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Short %s data transfer (%d bytes) \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->DataRemaining));
++
++ /* wait for block sent/receive or error */
++ waitMask = OMAP_REG_MMC_MODULE_STATUS_BRS;
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* load FIFO */
++ HcdTransferTxData(pDevice, pReq);
++ waitMask |= OMAP_REG_MMC_MODULE_STATUS_EOFB;
++ }
++
++ WAIT_FOR_HC_STATUS(pDevice,
++ waitMask,
++ hwErrors,
++ OMAP_STATUS_DATA_PROCESSING_ERRORS,
++ status,
++ OMAP_SHORT_TRANSFER_DONE_POLLING)
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetController(pDevice,TRUE,FromIsr);
++ break;
++ }
++
++ if (hwErrors) {
++ status = TranslateSDError(pDevice, pReq, hwErrors);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* check for busy */
++ MicroDelay(pDevice, 1);
++ /* check if card entered busy */
++ if (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_CB)) {
++ /* we are done */
++ break;
++ }
++ /* card entered busy */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CB);
++
++ /* wait end of busy */
++ WAIT_FOR_HC_STATUS(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS_EOFB,
++ hwErrors,
++ 0, /* no need to check for errors */
++ status,
++ OMAP_SHORT_TRANSFER_DONE_POLLING)
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetController(pDevice,TRUE,FromIsr);
++ }
++
++ } else {
++ /* unload FIFO */
++ HcdTransferRxData(pDevice, pReq, TRUE);
++ }
++ /* done */
++ break;
++ }
++
++ /* enable error interrupts, data transfer will require interrupts */
++ irqUnmask = OMAP_REG_MMC_INTERRUPT_ERRORS;
++ status = SDIO_STATUS_PENDING;
++
++ if (pDevice->DmaMode != OMAP_DMA_NONE) {
++ /* for DMA let the DMA hardware run , we only want the interrupt
++ * for block sent/received in addition to the errors */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_BRS;
++ break;
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* set threshold for FIFO empty level */
++ SetFifoAEL(pDevice,OMAP_MMC_AEL_FIFO_THRESH);
++ /* wait for AEL interrupts */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_AE;
++ } else {
++ if (pReq->DataRemaining < OMAP_MMC_AFL_FIFO_THRESH) {
++ /* don't need AFL, wait for last block received interrupt instead */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_BRS;
++ } else {
++ /* set trigger level for FIFO full level */
++ SetFifoAFL(pDevice,OMAP_MMC_AFL_FIFO_THRESH);
++ /* more data is expected */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_AF;
++ }
++ }
++
++ } while (FALSE);
++
++ if (SDIO_STATUS_PENDING == status) {
++ if (irqUnmask != 0) {
++ UnmaskIrq(pDevice, irqUnmask, FromIsr);
++ }
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP HcdRequest Pending %s data transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ UINT16 temp;
++ PSDREQUEST pReq;
++
++ pDevice->CompletionCount = 0;
++ pDevice->DmaMode = OMAP_DMA_NONE;
++ pDevice->ShortTransfer = FALSE;
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ do {
++ if (pDevice->ShuttingDown) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest returning canceled\n"));
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++
++ /* make sure error ints and EOC is masked*/
++ MaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ERRORS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOC,
++ FROM_NORMAL);
++
++ /* clear all status bits (including error bits) that deals with request processing */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS);
++
++ if (READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP ERROR!!! status did not clear: 0x%X\n",
++ READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS)));
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ default:
++ case SDREQ_FLAGS_NO_RESP:
++ temp = OMAP_REG_MMC_CMD_NORESPONSE;
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ temp = OMAP_REG_MMC_CMD_R1;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp = OMAP_REG_MMC_CMD_R1 | OMAP_REG_MMC_CMD_R1BUSY;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp = OMAP_REG_MMC_CMD_R2;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ temp = OMAP_REG_MMC_CMD_R3;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* SDIO R4s are just OCR responses equivalent to an R3*/
++ temp = OMAP_REG_MMC_CMD_R3;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ /* R5s are just R1 responses, do not use the R5 type in this controller
++ * because it will disable response timeout detection unless you set
++ * the C5E,C14E..bits */
++ temp = OMAP_REG_MMC_CMD_R1;
++ break;
++ case SDREQ_FLAGS_RESP_R6:
++ temp = OMAP_REG_MMC_CMD_R6;
++ break;
++ }
++
++ /* get the command type */
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ /* broadcast no-response */
++ temp |= OMAP_REG_MMC_CMD_TYPE_BC;
++ break;
++
++ case SDREQ_FLAGS_RESP_R2:
++ if ((pReq->Command == CMD9) || (pReq->Command == CMD10)) {
++ temp |= OMAP_REG_MMC_CMD_TYPE_AC;
++ } else if (pReq->Command == CMD2) {
++ temp |= OMAP_REG_MMC_CMD_TYPE_BCR;
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_R6:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* responses that are broadcast */
++ temp |= OMAP_REG_MMC_CMD_TYPE_BCR;
++ break;
++ default:
++ /* all other commands are addressed responses */
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ /* commands with data */
++ temp |= OMAP_REG_MMC_CMD_TYPE_ADTC;
++ } else {
++ /* all commands without data */
++ temp |= OMAP_REG_MMC_CMD_TYPE_AC;
++ }
++ break;
++ }
++
++ GetDefaults(pDevice);
++
++ ReqProcClkStartStop(pDevice, CLOCK_ON);
++
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)){
++ /* set the block size register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH, pReq->BlockLen-1);
++ /* set block count register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT, pReq->BlockCount-1);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP HcdRequest: %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest: blen: %d, nblk: %d\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT)));
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ temp |= IS_SDREQ_WRITE_DATA(pReq->Flags) ?
++ OMAP_REG_MMC_CMD_DDIR_WRITE : OMAP_REG_MMC_CMD_DDIR_READ;
++
++ SetDataTimeout(pDevice, pDevice->DataTimeOut);
++
++ if ((pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) && (pReq->BlockCount == 1) &&
++ (pReq->BlockLen < OMAP_MAX_SHORT_TRANSFER_SIZE)) {
++ /* flag current request as a short transfer */
++ pDevice->ShortTransfer = TRUE;
++ }
++
++ if (!pDevice->ShortTransfer) {
++ /* setup dma transfer */
++ if (pDevice->DmaCapable) {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ /* caller passed a scatter gather list */
++ pDevice->DmaMode = OMAP_DMA_SG;
++ } else {
++ /* don't do DMA if the transfer will fit in one FIFO, just adds extra ints. */
++//force DMA use to avoid missing transfer completes if (pReq->DataRemaining > OMAP_MMC_FIFO_SIZE) {
++ /* try common buffer */
++ pDevice->DmaMode = OMAP_DMA_COMMON;
++//?? }
++ }
++ } else {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++ }
++ }
++
++ if (pDevice->DmaMode != OMAP_DMA_NONE) {
++ /* setup DMA */
++ status = SetUpHCDDMA(pDevice,
++ pReq,
++ DMACompletion,
++ pDevice);
++
++ if (!SDIO_SUCCESS(status)) {
++ if ((SDIO_STATUS_UNSUPPORTED == status) &&
++ (OMAP_DMA_COMMON == pDevice->DmaMode)){
++ /* if we tried common buffer, the length may be unaligned,
++ * punt it to PIO mode */
++ pDevice->DmaMode = OMAP_DMA_NONE;
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ /* fail the request */
++ break;
++ }
++ }
++ }
++
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest:(1) blen: %d, nblk: %d\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT)));
++ }
++
++ /* set the argument register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_ARG_LOW, (UINT16)(pReq->Argument & 0xFFFF));
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_ARG_HI, (UINT16)((pReq->Argument & 0xFFFF0000) >> 16));
++ /* set the command */
++ temp |= (pReq->Command & OMAP_REG_MMC_CMD_MASK);
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++ /* set command timeout */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_TIMEOUT, pDevice->TimeOut);
++
++ if ((SDHCD_GET_OPER_CLOCK(pHcd) < pDevice->ClockSpinLimit) &&
++ (pReq->Command != CMD3)){
++ /* clock rate is very low, need to use interrupts here
++ or cmd 3 that is not handled properly by OMAP controllers */
++ UnmaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ERRORS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOC,
++ FROM_NORMAL);
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, temp);
++
++ status = SDIO_STATUS_PENDING;
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest using interrupt for command done.*** with data. (clock:%d, ref:%d)\n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ } else {
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest using interrupt for command done. (clock:%d, ref:%d) \n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ }
++
++ break;
++ }
++
++ /* if we get here we are polling, interrupt errors and EOC should be masked */
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, temp);
++
++ WAIT_FOR_HC_STATUS(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS_EOC,
++ temp,
++ OMAP_STATUS_CMD_PROCESSING_ERRORS,
++ status,
++ OMAP_COMMAND_DONE_POLLING);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO OMAP HCD (cmd-inline) polling failed (sd command:%d,status:%d)\n",
++ pReq->Command,status));
++ ResetController(pDevice,TRUE,FROM_NORMAL);
++ if (pReq->Command == CMD3) {
++ /* fake the cmd3, if it was a real error it will be picked up in the cmd7 */
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ break;
++ }
++ break;
++ }
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HCD (cmd-inline) statreg: 0x%X config:0x%X\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG)));
++
++ if (temp & OMAP_STATUS_CMD_PROCESSING_ERRORS) {
++ status = TranslateSDError(pDevice, pReq, temp);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ status = ProcessCommandDone(pDevice,pReq,FALSE);
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ pReq->Status = status;
++ EndHCTransfer(pDevice, pReq, FROM_NORMAL);
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags)) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ return SDIO_STATUS_PENDING;
++ } else {
++ /* complete the request */
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest Command Done, status:%d \n", status));
++ }
++ pDevice->Cancel = FALSE;
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 configSave;
++
++ if(pDevice->ShuttingDown) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdConfig returning canceled\n"));
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (GET_SDCONFIG_CMD(pConfig)){
++ case SDCONFIG_GET_WP:
++ if (WriteProtectSwitchOn(pDevice)) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdConfig sending init clocks\n"));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ALL_INT,FROM_NORMAL);
++ ReqProcClkStartStop(pDevice, CLOCK_ON);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_ALL);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, OMAP_REG_MMC_CMD_INAB);
++ while(!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) & OMAP_REG_MMC_MODULE_STATUS_EOC))
++ ;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_EOC);
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++
++ irqModeFlags =
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: 4 Bit IRQ mode \n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pDevice->KeepClockOn = TRUE;
++ } else {
++ /* in 1 bit mode, the clock can be left off */
++ pDevice->KeepClockOn = FALSE;
++ }
++ }
++ pDevice->IrqDetectArmed = TRUE;
++
++ /* enable SDIO mode IRQ detection */
++ configSave = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ configSave |= OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, configSave);
++ /* enable detection IRQ */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: enable SDIO IRQ\n"));
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ } else {
++ pDevice->KeepClockOn = FALSE;
++ pDevice->IrqDetectArmed = FALSE;
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: disable SDIO IRQ\n"));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ configSave = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ configSave &= ~OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, configSave);
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig - SDIO IRQ re-armed\n"));
++ pDevice->IrqDetectArmed = TRUE;
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pDevice, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ /* save it in case we have to restore it later */
++ memcpy(&pDevice->SavedBusMode,pConfig->pData,sizeof(SDCONFIG_BUS_MODE_DATA));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ DBG_PRINT(OMAP_TRACE_CONFIG, ("SDIO OMAP HcdConfig PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ status = SetPowerLevel(pDevice,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask);
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ *((CT_DEBUG_LEVEL *)pConfig->pData) = DBG_GET_DEBUG_LEVEL();
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_SET_DEBUG_LEVEL(*((CT_DEBUG_LEVEL *)pConfig->pData));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP HCD: HcdConfig - unsupported command: 0x%X\n",
++ GET_SDCONFIG_CMD(pConfig)));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++void ResetController(PSDHCD_DEVICE pDevice, BOOL Restore, BOOL FromIsr)
++{
++ INT ii;
++
++ ClockStartStop(pDevice, CLOCK_OFF);
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_CONTROL, OMAP_REG_MMC_SYSTEM_CONTROL_SW_RESET);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_CONTROL, 0);
++
++ /* wait for done */
++ for(ii = 0;
++ (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_STATUS) & OMAP_REG_MMC_SYSTEM_STATUS_RESET_DONE))
++ && (ii < 1000);
++ ii++);
++
++ if (ii >= 1000) {
++ /* reset on 1610 is broken, see errata, use alternate approach */
++ /* cycle power */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, 0);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG,
++ OMAP_REG_MMC_MODULE_CONFIG_PWRON | 1);
++ }
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG,
++ OMAP_REG_MMC_MODULE_CONFIG_MODE_MMCSD | OMAP_REG_MMC_MODULE_CONFIG_PWRON);
++
++ /* configure the SDIO mode */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG,
++ OMAP_REG_MMC_SDIO_MODE_CONFIG_DCR4);
++
++ SetDataTimeout(pDevice, OMAP_DEFAULT_DATA_TIMEOUT);
++
++ /* set the default timeouts */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_TIMEOUT, pDevice->TimeOut);
++ /* clear all status bits, from chip erratta, the status may not clear on a reset */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_ALL);
++
++ if (!Restore) {
++ return;
++ }
++
++ /* restore bus clock and bus mode */
++ SetBusMode(pDevice,&pDevice->SavedBusMode);
++
++ /* restore interrupt state */
++ if (pDevice->IrqDetectArmed) {
++ UINT16 configSave;
++ configSave = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ configSave |= OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, configSave);
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FromIsr);
++ }
++
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize controller
++ Input: pDeviceContext - device context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 version;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HcdInitialize\n"));
++
++ /* reset the controller */
++ ResetController(pDeviceContext, FALSE,FROM_NORMAL);
++
++ /* display version info */
++ version = READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_MODULE_REV);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HcdInitialize: Module Spec verison: %d.%d\n",
++ ((version & OMAP_REG_MMC_MODULE_REV_MAJOR_MASK) >> OMAP_REG_MMC_MODULE_REV_MAJOR_SHIFT),
++ ((version & OMAP_REG_MMC_MODULE_REV_MINOR_MASK) >> OMAP_REG_MMC_MODULE_REV_MINOR_SHIFT)));
++
++ if (pDeviceContext->BaseClock == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP invalid base clock setting\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ return status;
++ }
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO OMAP Using base clock: %dHz, max bus clock: %dHz, max blocks: %d max bytes per block: %d\n",
++ pDeviceContext->BaseClock,
++ pDeviceContext->Hcd.MaxClockRate,
++ pDeviceContext->Hcd.MaxBlocksPerTrans,
++ pDeviceContext->Hcd.MaxBytesPerBlock));
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HcdInitialize: SlotVoltageCaps: 0x%X, MaxSlotCurrent: 0x%X\n",
++ (UINT)pDeviceContext->Hcd.SlotVoltageCaps, (UINT)pDeviceContext->Hcd.MaxSlotCurrent));
++
++ /* interrupts will get enabled by the caller after all of the OS dependent work is done */
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HcdInitialize\n"));
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate controller
++ Input: pDeviceContext - context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ PSDREQUEST pReq;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HcdDeinitialize\n"));
++
++
++ pReq = GET_CURRENT_REQUEST(&pDeviceContext->Hcd);
++
++ if (pReq != NULL) {
++ pReq->Status = SDIO_STATUS_CANCELED;
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO OMAP HcdDeinitialize - cancelling request. (command:%d) mod status:0x%X, IRQ Enables:0x%X\n",
++ pReq->Command, (UINT)READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_MODULE_STATUS),
++ (UINT)READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_INTERRUPT_ENABLE)));
++ }
++
++ pDeviceContext->KeepClockOn = FALSE;
++ MaskIrq(pDeviceContext, OMAP_REG_MMC_INTERRUPT_ALL_INT, FROM_NORMAL);
++ pDeviceContext->ShuttingDown = TRUE;
++ ClockStartStop(pDeviceContext, CLOCK_OFF);
++
++ if (pReq != NULL) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HcdDeinitialize\n"));
++}
++
++void EndHCTransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL FromIsr)
++{
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++
++ if (!SDIO_SUCCESS(pReq->Status) && (pDevice->DmaMode != OMAP_DMA_NONE)) {
++ /* DMA may be running cancel the DMA transfer */
++ SDCancelDMATransfer(pDevice);
++ }
++
++ MaskIrq(pDevice,
++ (OMAP_REG_MMC_INTERRUPT_ALL_INT & ~OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ),FromIsr);
++
++ if (!SDIO_SUCCESS(pReq->Status)) {
++ switch (pReq->Status) {
++ case SDIO_STATUS_BUS_READ_TIMEOUT:
++ case SDIO_STATUS_BUS_READ_CRC_ERR:
++ case SDIO_STATUS_BUS_WRITE_ERROR:
++ case SDIO_STATUS_BUS_RESP_CRC_ERR:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP - resetting controller on bus errors (CMD:%d) \n",
++ pReq->Command));
++ /* controller gets stuck on some errors */
++ ResetController(pDevice,TRUE,FromIsr);
++ break;
++ default:
++ break;
++ }
++ }
++
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdSDInterrupt - process controller interrupt
++ Input: pDeviceContext - context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDevice)
++{
++ UINT16 statusErrs,errorMask,statusMask;
++ PSDREQUEST pReq = NULL;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("+SDIO OMAP ISR handler \n"));
++
++ pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ while (1) {
++ /* get status */
++ statusErrs = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS);
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, status: 0x%X \n",
++ (UINT)statusErrs));
++
++ /* for ISR processing, only deal with interrupts that are actually enabled */
++ statusMask = READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE);
++ statusErrs &= statusMask;
++ /* ack the status bits we care about */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, (statusErrs & (~OMAP_REG_MMC_MODULE_STATUS_CIRQ)));
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, valid status: 0x%X, IRQ Enables:0x%X\n",
++ (UINT)statusErrs, statusMask));
++ /* deal with SDIO interrupts */
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_CIRQ) {
++ if (READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG)
++ & OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE) {
++ /* this interrupt is level triggered and will remain set until the card interrupt
++ source is cleared. */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP ISR - SDIO_IRQ detected\n"));
++ if (READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE)
++ & OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ) {
++ QueueEventResponse(pDevice, WORK_ITEM_SDIO_IRQ);
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_ISR);
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CIRQ);
++ }
++ } else {
++ DBG_ASSERT_WITH_MSG(FALSE,
++ "SDIO OMAP ISR - unexpected card interrupt!\n");
++ }
++ }
++
++ if (0 == statusErrs) {
++ /* nothing to process */
++ break;
++ }
++
++ if (NULL == pReq) {
++ /* nothing more to do */
++ break;
++ }
++
++ errorMask = OMAP_REG_MMC_MODULE_STATUS_CTO |
++ OMAP_REG_MMC_MODULE_STATUS_CCRC;
++
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)){
++ errorMask |= OMAP_REG_MMC_MODULE_STATUS_DTO | OMAP_REG_MMC_MODULE_STATUS_DCRC;
++ }
++
++ if (statusErrs & errorMask) {
++ status = TranslateSDError(pDevice, pReq, (statusErrs & errorMask));
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++
++ /* if we reach here, there were no command processing errors */
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_EOC) {
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOC, FROM_ISR);
++ status = ProcessCommandDone(pDevice,
++ pReq,
++ TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_AE) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR TX Transfer AE\n"));
++ /* refill the FIFO */
++ if (HcdTransferTxData(pDevice, pReq)) {
++ ToggleGPIOPin(pDevice, DBG_GPIO_PIN_1);
++ /* fifo contains final data, disable almost empty interrupts */
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_AE, FROM_ISR);
++ /* get ready for BRS or EOFB, it has been observed that EOFB can come early
++ * and mask out the BRS bit, this looks like a controller bug */
++ UnmaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ENABLE_BRS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,
++ FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_BUSY,
++ ("SDIO OMAP ISR, TX near complete, waiting for BRS or EOFB (bcnt:%d,blen:%d)\n",
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT),
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH)));
++ } else {
++ /* more data to go, if this is a multi-block transfer we want to make sure
++ * the EOFB is cleared for all blocks except the last one, we will
++ * actually wait for EOFB on the last block */
++ if (READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT) > 2) {
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_EOFB);
++ }
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_AF) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(!IS_SDREQ_WRITE_DATA(pReq->Flags));
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR RX Transfer AF\n"));
++ /* drain the FIFO */
++ if (HcdTransferRxData(pDevice, pReq, FALSE)) {
++ /* last bit of data remaining, we can wait for BRS */
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_AF, FROM_ISR);
++ /* get ready for BRS */
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_BRS,FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, RX near complete, waiting for BRS \n"));
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_BRS) {
++ ToggleGPIOPin(pDevice, DBG_GPIO_PIN_2);
++ DBG_PRINT(OMAP_TRACE_BUSY,("SDIO OMAP ISR BRS (bcnt:%d,blen:%d)\n",
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT),
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH)));
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_BRS, FROM_ISR);
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* check for busy on write operations */
++ MicroDelay(pDevice, 10);
++ /* check card enter busy */
++ if (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_CB)) {
++ ToggleGPIOPin(pDevice, DBG_GPIO_PIN_1);
++ DBG_PRINT(OMAP_TRACE_BUSY, ("SDIO OMAP ISR TX Transfer Done - not busy \n"));
++ status = SDIO_STATUS_SUCCESS;
++ /* we are done */
++ break;
++ }
++ /* clear status */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CB);
++ DBG_PRINT(OMAP_TRACE_BUSY, ("SDIO OMAP ISR TX Transfer Done - waiting on busy release \n"));
++ statusErrs &= ~OMAP_REG_MMC_MODULE_STATUS_CB;
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,FROM_ISR);
++
++ } else {
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR RX Transfer Done \n"));
++ if (pDevice->DmaMode == OMAP_DMA_NONE) {
++ /* In PIO mode, the FIFO may contain some residue data */
++ HcdTransferRxData(pDevice, pReq, TRUE);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_EOFB) {
++ ToggleGPIOPin(pDevice, DBG_GPIO_PIN_1);
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_BUSY,("SDIO OMAP ISR Card Busy Done (bcnt:%d,blen:%d)\n",
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT),
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH)));
++ /* the write operation is finally done */
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++
++ }
++
++
++ if (status != SDIO_STATUS_PENDING) {
++ pReq->Status = status;
++ EndHCTransfer(pDevice,pReq,FROM_ISR);
++ if (OMAP_DMA_NONE == pDevice->DmaMode) {
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* using some form of DMA */
++ if (!SDIO_SUCCESS(status)) {
++ /* EndHCTransfer will cancel DMA, no need to synch with DMA */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* sync request completion with DMA */
++ CompleteRequestSyncDMA(pDevice,pReq,status);
++ }
++ }
++ }
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("-SDIO OMAP ISR handler \n"));
++
++ return TRUE;
++}
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,165 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_linux.h
++
++ at abstract: include file for Texas Instruments OMAP host controller, linux dependent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/device.h>
++#endif
++#include <asm/arch/dma.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <asm/hardware/clock.h>
++#endif
++#include <asm/irq.h>
++#include <linux/delay.h>
++
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++#define OMAP_BASE_ADDRESS1 0xFFFB7800
++#define OMAP_BASE_ADDRESS2 0xFFFB7C00
++#define OMAP_INTERRUPT1 INT_MMC
++#define OMAP_INTERRUPT2 INT_1610_MMC2
++#define OMAP_DMA_RX1 OMAP_DMA_MMC_RX
++#define OMAP_DMA_TX1 OMAP_DMA_MMC_TX
++#define OMAP_DMA_RX2 OMAP_DMA_MMC2_RX
++#define OMAP_DMA_TX2 OMAP_DMA_MMC2_TX
++
++#define OMAP_BASE_LENGTH 0x6C
++#define OMAP_MODULE_CLOCK 48000000
++#define OMAP_MAX_DEVICE_COUNT 2
++#define OMAP_DEFAULT_DEVICE_COUNT 1
++#define OMAP_DEFAULT_FIRST_DEVICE 0
++#define OMAP_DMA_MASK 0xFFFFFFFE
++
++
++#define CARD_INSERT_POLARITY FALSE
++#define WP_POLARITY TRUE
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++/* debounce delay for slot */
++#define SD_SLOT_DEBOUNCE_MS 500
++
++
++/* device base name */
++#define SDIO_BD_BASE "sdiobd"
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef void (*PDMA_TRANSFER_COMPLETION)(PVOID,SDIO_STATUS,BOOL);
++
++/* device data*/
++typedef struct _HCD_OS_INFO {
++ POS_PNPDEVICE pBusDevice; /* our device registered with bus driver */
++ SDHCD_MEMORY Address; /* memory address of this device */
++ spinlock_t AddressSpinlock; /* use to protect reghisters when needed */
++ UINT8 InitStateMask;
++#define SDIO_BASE_MAPPED 0x01
++#define SDIO_IRQ_INTERRUPT_INIT 0x04
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x40
++#define SDHC_TIMER_INIT 0x80
++ spinlock_t Lock; /* lock against the ISR */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel;
++ BOOL ShuttingDown; /* indicates shut down of HCD) */
++ struct work_struct iocomplete_work; /* work item definintions */
++ struct work_struct carddetect_work; /* work item definintions */
++ struct work_struct sdioirq_work; /* work item definintions */
++ UINT32 Channel; /* DMA channel for this device */
++ DMA_ADDRESS hDmaBuffer; /* handle for data buffer */
++ PUINT8 pDmaBuffer; /* virtual address of command buffer */
++ UINT32 CommonBufferSize; /* size of CommonBuffer */
++ struct clk *pMMCClock; /* dma clock active */
++ s16 PowerPin;
++ s16 SwitchPin;
++ int Interrupt;
++ int DmaRxChannel; /* receive DMA channel */
++ int DmaTxChannel; /* transmit DMA channel */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ int DmaChannel; /* in use channel */
++#else
++ /* 2.4 */
++ dma_regs_t *DmaChannel; /* in use channel registers */
++#endif
++ int LastTransfer; /* length of last transfer */
++ PSDDMA_DESCRIPTOR pDmaList; /* in use scatter-gather list */
++ UINT SGcount; /* count of in-use scatter gather list */
++ PVOID TransferContext; /* context passed to TransferCompletion routine */
++ PDMA_TRANSFER_COMPLETION pTransferCompletion; /* transfer completion routine */
++}HCD_OS_INFO, *PHCD_OS_INFO;
++
++typedef struct _SDHCD_DRIVER {
++ OS_PNPDEVICE HcdDevice; /* the OS device for this HCD */
++ OS_PNPDRIVER HcdDriver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION Dma; /* driver DMA description */
++}SDHCD_DRIVER, *PSDHCD_DRIVER;
++
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++
++#define READ_HOST_REG32(pDevice, OFFSET) \
++ _READ_DWORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG32(pDevice, OFFSET, VALUE) \
++ _WRITE_DWORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET),(VALUE))
++#define READ_HOST_REG16(pDevice, OFFSET) \
++ _READ_WORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG16(pDevice, OFFSET, VALUE) \
++ _WRITE_WORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET),(VALUE))
++
++#define GET_HC_REG_BASE(pDevice) (pDevice)->OSInfo.Address.pMapped
++
++#define OMAP_USE_DBG_GPIO
++/* prototypes */
++#endif /* __SDIO_HCD_LINUX_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd_os_2_6.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap/sdio_hcd_os_2_6.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,574 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os_2_6.c
++
++ at abstract: Linux OMAP native SDIO Host Controller Driver, 2.6 and higher
++
++#notes: includes initialization and DMA code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include <linxu/sdio/ctsystem.h"
++#include "sdio_omap_hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#include <asm/mach-types.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/mux.h>
++#include <linux/dma-mapping.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/tps65010.h>
++
++extern INT gpiodebug;
++extern INT noDMA;
++extern SDHCD_DRIVER_CONTEXT HcdContext;
++
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r);
++static void setupOmapDma(PSDHCD_DEVICE pDevice,
++ int Length,
++ DMA_ADDRESS DmaAddress,
++ BOOL Transmit);
++/*
++ * unsetup the OMAP registers
++*/
++void DeinitOmap(PSDHCD_DEVICE pDevice)
++{
++ /* deallocate DMA buffer */
++ if (pDevice->OSInfo.pDmaBuffer != NULL) {
++ dma_free_coherent(&pDevice->OSInfo.pBusDevice->dev,
++ pDevice->OSInfo.CommonBufferSize,
++ pDevice->OSInfo.pDmaBuffer,
++ pDevice->OSInfo.hDmaBuffer);
++ pDevice->OSInfo.pDmaBuffer = NULL;
++ }
++
++ if (!IS_ERR(pDevice->OSInfo.pMMCClock)) {
++ clk_disable(pDevice->OSInfo.pMMCClock);
++ clk_put(pDevice->OSInfo.pMMCClock);
++ }
++
++ if (pDevice->OSInfo.InitStateMask & SDIO_IRQ_INTERRUPT_INIT) {
++ disable_irq(pDevice->OSInfo.Interrupt);
++ free_irq(pDevice->OSInfo.Interrupt, pDevice);
++ pDevice->OSInfo.InitStateMask &= ~SDIO_IRQ_INTERRUPT_INIT;
++ }
++
++ if (pDevice->OSInfo.PowerPin >= 0) {
++ omap_free_gpio(pDevice->OSInfo.PowerPin);
++ }
++}
++
++/*
++ * setup the OMAP registers
++*/
++SDIO_STATUS InitOmap(PSDHCD_DEVICE pDevice, UINT deviceNumber)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ const struct omap_mmc_config *pConfig = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
++ ULONG baseAddress;
++ int err;
++
++ if (pConfig == NULL) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP HCD: InitOmap - unable to get OMAP_TAG_MMC\n"));
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: InitOmap - OMAP_TAG_MMC blocks: %d, mmc1PowerPin: %d, mmc1SwitchPin: %d, mmc2PowerPin: %d, mmc2SwitchPin: %d\n",
++ (UINT)pConfig->mmc_blocks, (UINT)pConfig->mmc1_power_pin, (UINT)pConfig->mmc1_switch_pin, (UINT)pConfig->mmc2_power_pin, (UINT)pConfig->mmc2_switch_pin));
++
++ if (pConfig->mmc_blocks == 0) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP HCD: InitOmap - no host controller blocks enabled\n"));
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ if (deviceNumber == 0) {
++ pDevice->OSInfo.PowerPin = pConfig->mmc1_power_pin;
++ pDevice->OSInfo.SwitchPin = pConfig->mmc1_switch_pin;
++ } else {
++ if (pConfig->mmc_blocks & 2) {
++ pDevice->OSInfo.PowerPin = pConfig->mmc2_power_pin;
++ pDevice->OSInfo.SwitchPin = pConfig->mmc2_switch_pin;
++ }else {
++ pDevice->OSInfo.PowerPin = pConfig->mmc1_power_pin;
++ pDevice->OSInfo.SwitchPin = pConfig->mmc1_switch_pin;
++ }
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: InitOmap - Number: %d, PowerPin: %d, SwitchPin: %d, DMAmask: 0x%X\n",
++ deviceNumber, (UINT)pDevice->OSInfo.PowerPin, (UINT)pDevice->OSInfo.SwitchPin, (UINT)*pDevice->OSInfo.pBusDevice->dev.dma_mask));
++
++ do {
++ if (!noDMA) {
++
++ /* allocate a DMA buffer larger enough for the command buffers and the data buffers */
++ pDevice->OSInfo.pDmaBuffer = dma_alloc_coherent(&pDevice->OSInfo.pBusDevice->dev,
++ pDevice->OSInfo.CommonBufferSize,
++ &pDevice->OSInfo.hDmaBuffer,
++ GFP_DMA);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: InitOmap - pDmaBuffer: 0x%X, hDmaBuffer: 0x%X Size:%d\n",
++ (UINT)pDevice->OSInfo.pDmaBuffer ,
++ (UINT)pDevice->OSInfo.hDmaBuffer,
++ pDevice->OSInfo.CommonBufferSize));
++
++ if (pDevice->OSInfo.pDmaBuffer == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: InitOmap - unable to get DMA buffer\n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pDevice->DmaCapable = TRUE;
++ /* tell upper drivers that we support direct DMA */
++ pDevice->Hcd.pDmaDescription = &HcdContext.Driver.Dma;
++
++ }
++
++ pDevice->OSInfo.pMMCClock = clk_get(&pDevice->OSInfo.pBusDevice->dev,
++ (deviceNumber == 0) ? "mmc1_ck" : "mmc2_ck");
++ if (IS_ERR(pDevice->OSInfo.pMMCClock)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO OMAP HCD: InitOmap - unable to get clock: %s, err: %d, device: %d\n",
++ (deviceNumber) ? "mmc1_ck" : "mmc2_ck", (UINT)PTR_ERR(pDevice->OSInfo.pMMCClock), deviceNumber));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ clk_enable(pDevice->OSInfo.pMMCClock);
++
++ /* configure the mux for the sd controller */
++ if (deviceNumber == 0) {
++ omap_cfg_reg(MMC_CMD);
++ omap_cfg_reg(MMC_CLK);
++ omap_cfg_reg(MMC_DAT0);
++ omap_cfg_reg(MMC_DAT1);
++ omap_cfg_reg(MMC_DAT2);
++ omap_cfg_reg(MMC_DAT3);
++ baseAddress = OMAP_BASE_ADDRESS1;
++ pDevice->OSInfo.Interrupt = OMAP_INTERRUPT1;
++ pDevice->OSInfo.DmaRxChannel = OMAP_DMA_RX1;
++ pDevice->OSInfo.DmaTxChannel = OMAP_DMA_TX1;
++ } else {
++ omap_cfg_reg(Y8_1610_MMC2_CMD);
++ omap_cfg_reg(Y10_1610_MMC2_CLK);
++ omap_cfg_reg(R18_1610_MMC2_CLKIN);
++ omap_cfg_reg(W8_1610_MMC2_DAT0);
++ omap_cfg_reg(V8_1610_MMC2_DAT1);
++ omap_cfg_reg(W15_1610_MMC2_DAT2);
++ omap_cfg_reg(R10_1610_MMC2_DAT3);
++ omap_cfg_reg(V9_1610_MMC2_CMDDIR);
++ omap_cfg_reg(V5_1610_MMC2_DATDIR0);
++ omap_cfg_reg(W19_1610_MMC2_DATDIR1);
++ baseAddress = OMAP_BASE_ADDRESS2;
++ pDevice->OSInfo.Interrupt = OMAP_INTERRUPT2;
++ pDevice->OSInfo.DmaRxChannel = OMAP_DMA_RX2;
++ pDevice->OSInfo.DmaTxChannel = OMAP_DMA_TX2;
++ }
++ pDevice->OSInfo.DmaChannel = -1;
++ /* map the memory address for the control registers */
++ pDevice->OSInfo.Address.pMapped = (PVOID)IO_ADDRESS(baseAddress);
++ pDevice->OSInfo.Address.Raw = baseAddress;
++ DBG_PRINT(OMAP_TRACE_CONFIG ,
++ ("SDIO OMAP - InitOMAP 0x%X\n", (UINT)pDevice->OSInfo.Address.pMapped));
++
++ pDevice->OSInfo.InitStateMask |= SDIO_BASE_MAPPED;
++
++ /* map the controller interrupt, we map it to each device.
++ Interrupts can be called from this point on */
++ err = request_irq(pDevice->OSInfo.Interrupt, hcd_sdio_irq, 0,
++ "OMAP HCD", pDevice);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: OmapInit, unable to map interrupt \n"));
++ err = -ENODEV;
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pDevice->OSInfo.InitStateMask |= SDIO_IRQ_INTERRUPT_INIT;
++
++ if (pDevice->OSInfo.PowerPin >= 0) {
++ if (omap_request_gpio(pDevice->OSInfo.PowerPin) != 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: OmapInit, unable to get power pin GPIO, %d, (dev %d)\n",
++ pDevice->OSInfo.PowerPin, deviceNumber));
++ } else {
++ omap_set_gpio_direction(pDevice->OSInfo.PowerPin, 0);
++ }
++ }
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ DeinitOmap(pDevice);
++ }
++
++ return status;
++}
++
++void ToggleGPIOPin(PSDHCD_DEVICE pDevice, INT PinNo)
++{
++ /* not implemented */
++}
++
++
++void SetupTXCommonBufferDMATransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ UINT32 length;
++ /* adjust length */
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ /* copy to common buffer */
++ memcpy(pDevice->OSInfo.pDmaBuffer, pReq->pHcdContext, length);
++ /* adjust where we are */
++ pReq->pHcdContext = (PUCHAR)pReq->pHcdContext + length;
++ pReq->DataRemaining -= length;
++ /* setup this chunk */
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,TRUE);
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP TX Common Buffer DMA, This Transfer: %d, Remaining:%d\n",
++ length,pReq->DataRemaining));
++}
++/*
++ * DMA transmit complete callback
++*/
++static void SD_DMACompleteCallback(int Channel, u16 DMAStatus, PVOID pContext)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pContext;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP SD_DMACompleteCallback (%s)- DMAStatus: 0x%X, lch: %d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",(UINT)status, Channel));
++ do {
++
++ if (-1 == pDevice->OSInfo.DmaChannel) {
++ DBG_PRINT(SDDBG_WARN,
++ ("SDIO OMAP SD_DMACompleteCallback unexpected callback - DMAStatus: 0x%X, lch: %d\n",
++ (UINT)DMAStatus, Channel));
++ break;
++ }
++
++ if (DMAStatus == OMAP_DMA_SYNC_IRQ) {
++ /* only a synch int, ignore it */
++ break;
++ }
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ DBG_ASSERT(pDevice->OSInfo.pDmaList != NULL);
++ DBG_ASSERT(pDevice->OSInfo.SGcount != 0);
++ /* unmap scatter gather */
++ dma_unmap_sg(pDevice->Hcd.pDevice,
++ pDevice->OSInfo.pDmaList,
++ pDevice->OSInfo.SGcount,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ pDevice->OSInfo.pDmaList = NULL;
++ pDevice->OSInfo.SGcount = 0;
++ }
++
++ /* handle errors */
++ if (DMAStatus & (OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ)) {
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ if (!(DMAStatus & OMAP_DMA_BLOCK_IRQ)) {
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ /* no DMA errors */
++ status = SDIO_STATUS_SUCCESS;
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ /* nothing more to do */
++ break;
++ }
++
++ /* handle common buffer DMA */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ if (pReq->DataRemaining) {
++ /* send the next chunk */
++ SetupTXCommonBufferDMATransfer(pDevice,pReq);
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++ } else {
++ UINT32 length;
++ /* copy RX Data from common buffer */
++ memcpy(pReq->pHcdContext, pDevice->OSInfo.pDmaBuffer, pDevice->OSInfo.LastTransfer);
++ /* adjust where we are */
++ pReq->pHcdContext = (PUCHAR)pReq->pHcdContext + pDevice->OSInfo.LastTransfer;
++ pReq->DataRemaining -= pDevice->OSInfo.LastTransfer;
++ /* set up next transfer */
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ if (length) {
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP RX Common Buffer DMA, Pending Transfer: %d, Remaining:%d\n",
++ length, pReq->DataRemaining));
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,FALSE);
++ pDevice->OSInfo.LastTransfer = length;
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++ }
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ omap_free_dma(pDevice->OSInfo.DmaChannel);
++ pDevice->OSInfo.DmaChannel = -1;
++ /* call callback */
++ pDevice->OSInfo.pTransferCompletion(pDevice->OSInfo.TransferContext, status, TRUE);
++ }
++
++}
++
++#define FIFO_SYNC_BLOCK_SIZE 32
++
++/* setup DMA for transfer */
++static void setupOmapDma(PSDHCD_DEVICE pDevice,
++ int Length,
++ DMA_ADDRESS DmaAddress,
++ BOOL Transmit)
++{
++ INT fifoLen;
++
++ if (Length == (FIFO_SYNC_BLOCK_SIZE * (Length/FIFO_SYNC_BLOCK_SIZE))) {
++ /* multiple of fifo size */
++ omap_set_dma_transfer_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_DATA_TYPE_S16,
++ FIFO_SYNC_BLOCK_SIZE>>1, (Length/FIFO_SYNC_BLOCK_SIZE),
++ OMAP_DMA_SYNC_FRAME);
++ fifoLen = 0xF;
++ } else {
++ if (Length < FIFO_SYNC_BLOCK_SIZE) {
++ omap_set_dma_transfer_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_DATA_TYPE_S16,
++ Length>>1, 1,
++ OMAP_DMA_SYNC_FRAME);
++ fifoLen = (Length>>1)-1;
++ fifoLen = (fifoLen < 0) ? 0 : fifoLen;
++ } else {
++ if (Length == (8 * (Length/8))) {
++ omap_set_dma_transfer_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_DATA_TYPE_S16,
++ 1, (Length+1)>>1,
++ OMAP_DMA_SYNC_FRAME);
++ fifoLen = 0;
++ } else {
++ omap_set_dma_transfer_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_DATA_TYPE_S16,
++ 1, (Length+1)>>1,
++ OMAP_DMA_SYNC_FRAME);
++ fifoLen = 0;
++ }
++ }
++ }
++
++ if (Transmit) {
++ omap_set_dma_src_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_PORT_EMIFF,
++ OMAP_DMA_AMODE_POST_INC,
++ DmaAddress);
++
++ omap_set_dma_dest_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_PORT_TIPB,
++ OMAP_DMA_AMODE_CONSTANT,
++ (virt_to_phys((void *)pDevice->OSInfo.Address.pMapped) +
++ OMAP_REG_MMC_DATA_ACCESS));
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, OMAP_REG_MMC_BUFFER_CONFIG_TXDE |
++ ((fifoLen << OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT) & OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK));
++
++
++
++ } else {
++ omap_set_dma_src_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_PORT_TIPB,
++ OMAP_DMA_AMODE_CONSTANT,
++ (virt_to_phys((void *)pDevice->OSInfo.Address.pMapped) +
++ OMAP_REG_MMC_DATA_ACCESS));
++ omap_set_dma_dest_params(pDevice->OSInfo.DmaChannel,
++ OMAP_DMA_PORT_EMIFF,
++ OMAP_DMA_AMODE_POST_INC,
++ DmaAddress);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, OMAP_REG_MMC_BUFFER_CONFIG_RXDE |
++ ((fifoLen << OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT) & OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK));
++ }
++
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP SDReadBuffer: return pending, transfer size: %d, fifo: %d\n",
++ Length, fifoLen));
++ omap_start_dma(pDevice->OSInfo.DmaChannel);
++
++}
++
++SDIO_STATUS SetUpHCDDMA(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ SYSTEM_STATUS err;
++ UINT32 length = pReq->BlockCount * pReq->BlockLen;
++ PSDDMA_DESCRIPTOR pDesc = NULL;
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("+SDIO OMAP SetUpHCDDMA: length: %d\n",length));
++
++ do {
++
++ if ((OMAP_DMA_COMMON == pDevice->DmaMode) &&
++ (length & 0x1)) {
++ /* DMA requires WORD alignment, tell caller to punt it to PIO mode */
++ status = SDIO_STATUS_UNSUPPORTED;
++ break;
++ }
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ /* doing direct DMA */
++ if (pReq->DescriptorCount > 1) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++
++ pDesc = (PSDDMA_DESCRIPTOR)pReq->pDataBuffer;
++ DBG_ASSERT(pDesc != NULL);
++ }
++
++ pDevice->OSInfo.pTransferCompletion = pCompletion;
++ pDevice->OSInfo.TransferContext = pContext;
++
++ if (pDevice->OSInfo.DmaChannel != -1) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP SetUpHCDDMA: **DMA still in use, channel: %d\n",
++ (UINT)pDevice->OSInfo.DmaChannel));
++ omap_free_dma(pDevice->OSInfo.DmaChannel);
++ pDevice->OSInfo.DmaChannel = -1;
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ err = omap_request_dma(pDevice->OSInfo.DmaTxChannel,
++ "SDIO TX",
++ SD_DMACompleteCallback,
++ pDevice, &pDevice->OSInfo.DmaChannel);
++
++ } else {
++ err = omap_request_dma(pDevice->OSInfo.DmaRxChannel,
++ "SDIO RX",
++ SD_DMACompleteCallback,
++ pDevice,
++ &pDevice->OSInfo.DmaChannel);
++ }
++
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP SetUpHCDDMA: can't get DMA channel: %d, err:%d\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ?
++ pDevice->OSInfo.DmaTxChannel : pDevice->OSInfo.DmaRxChannel,
++ err));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ if (OMAP_DMA_COMMON == pDevice->DmaMode) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ SetupTXCommonBufferDMATransfer(pDevice,pReq);
++ } else {
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,FALSE);
++ pDevice->OSInfo.LastTransfer = length;
++ }
++ break;
++ }
++
++ /* setup scatter gather */
++ DBG_ASSERT(pDesc != NULL);
++ /* map DMA */
++ dma_map_sg(pDevice->Hcd.pDevice,
++ pDesc,
++ pReq->DescriptorCount,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++
++ pDevice->OSInfo.pDmaList = pDesc;
++ pDevice->OSInfo.SGcount = pReq->DescriptorCount;
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP SetUpHCDDMA, Direct DMA dma_address:0x%X\n", (UINT32)sg_dma_address(pDesc)));
++
++ setupOmapDma(pDevice,
++ length,
++ sg_dma_address(pDesc),
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? TRUE : FALSE);
++
++ } while (FALSE);
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("-SDIO OMAP SetUpHCDDMA: status %d\n",status));
++
++ return status;
++}
++
++/*
++ * SDCancelTransfer - stop DMA transfer
++*/
++void SDCancelDMATransfer(PSDHCD_DEVICE pDevice)
++{
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP SDCancelDMATransfer\n"));
++ if (pDevice->OSInfo.DmaChannel != -1) {
++ omap_stop_dma(pDevice->OSInfo.DmaChannel);
++ omap_free_dma(pDevice->OSInfo.DmaChannel);
++ pDevice->OSInfo.DmaChannel = -1;
++ }
++}
++
++/* SDIO interrupt request */
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r)
++{
++ irqreturn_t retStat;
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP SDIO IRQ \n"));
++
++ /* call OS independent ISR */
++ if (HcdSDInterrupt((PSDHCD_DEVICE)context)) {
++ retStat = IRQ_HANDLED;
++ } else {
++ retStat = IRQ_NONE;
++ }
++ return retStat;
++}
+Index: linux-2.6.22/drivers/sdio/hcd/omap/sdio_omap_hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap/sdio_omap_hcd.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,372 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_pmap_hcd.h
++
++ at abstract: include file for OMAP native MMC/SD host controller, OS independent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_OMAP_HCD_H___
++#define __SDIO_OMAP_HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++
++enum OMAP_TRACE_ENUM {
++ OMAP_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ OMAP_TRACE_SDIO_INT = (SDDBG_TRACE + 2),
++ OMAP_TRACE_WORK,
++ OMAP_TRACE_DATA,
++ OMAP_TRACE_REQUESTS,
++ OMAP_TRACE_CONFIG,
++ OMAP_TRACE_MMC_INT,
++ OMAP_TRACE_CLOCK,
++ OMAP_TRACE_LAST
++};
++
++#define OMAP_TRACE_BUSY OMAP_TRACE_DATA
++
++#define OMAP_MAX_BYTES_PER_BLOCK 2048
++#define OMAP_MAX_BLOCKS 2048
++#define OMAP_DEFAULT_VOLTAGE SLOT_POWER_3_3V
++#define OMAP_DEFAULT_CURRENT 500
++#define OMAP_DEFAULT_CLOCK 500
++#define OMAP_DEFAULT_CMD_TIMEOUT 64
++#define OMAP_DEFAULT_DATA_TIMEOUT 400000
++
++#define OMAP_MMC_FIFO_SIZE 64
++/* almost full, for RX */
++#define OMAP_MMC_AFL_FIFO_THRESH 32 //62
++ /* almost empty, for TX */
++#define OMAP_MMC_AEL_FIFO_THRESH 32 // 2
++#define OMAP_MAX_SHORT_TRANSFER_SIZE 8
++
++#define OMAP_REG_MMC_CMD 0x00
++ #define OMAP_REG_MMC_CMD_DDIR_READ (1<<15)
++ #define OMAP_REG_MMC_CMD_DDIR_WRITE (0)
++ #define OMAP_REG_MMC_CMD_STREAM_MODE_NORMAL (0)
++ #define OMAP_REG_MMC_CMD_TYPE_BC (0)
++ #define OMAP_REG_MMC_CMD_TYPE_BCR (1<<12)
++ #define OMAP_REG_MMC_CMD_TYPE_AC (2<<12)
++ #define OMAP_REG_MMC_CMD_TYPE_ADTC (3<<12)
++ #define OMAP_REG_MMC_CMD_R1BUSY (1<<11)
++ #define OMAP_REG_MMC_CMD_NORESPONSE (0)
++ #define OMAP_REG_MMC_CMD_R1 (1<<8)
++ #define OMAP_REG_MMC_CMD_R2 (2<<8)
++ #define OMAP_REG_MMC_CMD_R3 (3<<8)
++ #define OMAP_REG_MMC_CMD_R4 (4<<8)
++ #define OMAP_REG_MMC_CMD_R5 (5<<8)
++ #define OMAP_REG_MMC_CMD_R6 (6<<8)
++ #define OMAP_REG_MMC_CMD_INAB (1<<7)
++ #define OMAP_REG_MMC_CMD_CTO_DTO (1<<6)
++ #define OMAP_REG_MMC_CMD_MASK (0x3F)
++
++
++#define OMAP_REG_MMC_ARG_LOW 0x04
++#define OMAP_REG_MMC_ARG_HI 0x08
++
++#define OMAP_REG_MMC_MODULE_CONFIG 0x0C
++ #define OMAP_REG_MMC_MODULE_CONFIG_4BIT (1<<15)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_MMCSD (0<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_SPI (1<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_TEST (2<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_PWRON (1<<11)
++ #define OMAP_REG_MMC_MODULE_CONFIGE_BE (1<<10)
++ #define OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK (0x3FF)
++
++#define OMAP_REG_MMC_MODULE_STATUS 0x10
++ #define OMAP_REG_MMC_MODULE_STATUS_CERR (1<<14)
++ #define OMAP_REG_MMC_MODULE_STATUS_CIRQ (1<<13)
++ #define OMAP_REG_MMC_MODULE_STATUS_OCRB (1<<12)
++ #define OMAP_REG_MMC_MODULE_STATUS_AE (1<<11)
++ #define OMAP_REG_MMC_MODULE_STATUS_AF (1<<10)
++ #define OMAP_REG_MMC_MODULE_STATUS_CRW (1<<9)
++ #define OMAP_REG_MMC_MODULE_STATUS_CCRC (1<<8)
++ #define OMAP_REG_MMC_MODULE_STATUS_CTO (1<<7)
++ #define OMAP_REG_MMC_MODULE_STATUS_DCRC (1<<6)
++ #define OMAP_REG_MMC_MODULE_STATUS_DTO (1<<5)
++ #define OMAP_REG_MMC_MODULE_STATUS_EOFB (1<<4)
++ #define OMAP_REG_MMC_MODULE_STATUS_BRS (1<<3)
++ #define OMAP_REG_MMC_MODULE_STATUS_CB (1<<2)
++ #define OMAP_REG_MMC_MODULE_STATUS_CD (1<<1)
++ #define OMAP_REG_MMC_MODULE_STATUS_EOC (1<<0)
++ #define OMAP_REG_MMC_MODULE_STATUS_ALL (0x7FFF)
++ #define OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS \
++ ((~(OMAP_REG_MMC_MODULE_STATUS_CIRQ | OMAP_REG_MMC_MODULE_STATUS_CD\
++ )) & OMAP_REG_MMC_MODULE_STATUS_ALL)
++ #define OMAP_STATUS_CMD_PROCESSING_ERRORS \
++ (OMAP_REG_MMC_MODULE_STATUS_CERR | OMAP_REG_MMC_MODULE_STATUS_CTO | \
++ OMAP_REG_MMC_MODULE_STATUS_CCRC)
++ #define OMAP_STATUS_DATA_PROCESSING_ERRORS \
++ (OMAP_REG_MMC_MODULE_STATUS_DCRC | OMAP_REG_MMC_MODULE_STATUS_DTO)
++
++#define OMAP_REG_MMC_INTERRUPT_ENABLE 0x14
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CERR (1<<14)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ (1<<13)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_OCRB (1<<12)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_AE (1<<11)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_AF (1<<10)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CRW (1<<9)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CCRC (1<<8)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CTO (1<<7)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_DCRC (1<<6)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_DTO (1<<5)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB (1<<4)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_BRS (1<<3)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CB (1<<2)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CD (1<<1)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_EOC (1<<0)
++ #define OMAP_REG_MMC_INTERRUPT_ALL_INT (0x7FFF)
++ #define OMAP_REG_MMC_INTERRUPT_NONE_INT (0)
++ #define OMAP_REG_MMC_INTERRUPT_ERRORS (OMAP_REG_MMC_INTERRUPT_ENABLE_CCRC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_CTO | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_DCRC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_DTO | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_CERR)
++ #define OMAP_REG_MMC_INTERRUPT_REQUESTS (OMAP_REG_MMC_INTERRUPT_ERRORS | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_EOC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_AF | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_AE | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB )
++
++#define OMAP_REG_MMC_CMD_TIMEOUT 0x18
++ /* low 8-bit valid */
++
++#define OMAP_REG_MMC_DATA_READ_TIMEOUT 0x1C
++ /* 16-bit */
++
++#define OMAP_REG_MMC_DATA_ACCESS 0x20
++ /* 16-bit */
++
++#define OMAP_REG_MMC_BLOCK_LENGTH 0x24
++ /* low 11-bit */
++
++#define OMAP_REG_MMC_BLOCK_COUNT 0x28
++ /* low 11-bit */
++
++#define OMAP_REG_MMC_BUFFER_CONFIG 0x2C
++ #define OMAP_REG_MMC_BUFFER_CONFIG_RXDE (1<<15)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK (0x1F00)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT (8)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_TXDE (1<<7)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK (0x1F)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT (0)
++
++#define OMAP_REG_MMC_SPI_CONFIG 0x30
++ #define OMAP_REG_MMC_SPI_CONFIG_STR (1<<15)
++ #define OMAP_REG_MMC_SPI_CONFIG_WNR (1<<14)
++ #define OMAP_REG_MMC_SPI_CONFIG_SODV (1<<13)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSTR (1<<12)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD05 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD15 (1<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD25 (2<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD35 (3<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS1 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS2 (1<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS3 (2<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS4 (3<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSEL (1<<7)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS1 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS2 (1<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS3 (2<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS4 (3<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSM (1<<3)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSD (1<<2)
++ #define OMAP_REG_MMC_SPI_CONFIG_POL_RISE (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_POL_FALL (1)
++
++#define OMAP_REG_MMC_SDIO_MODE_CONFIG 0x34
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C5E (1<<15)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C14E (1<<14)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C13E (1<<13)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C12E (1<<12)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_D3PS (1<<11)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_D3ES (1<<10)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_CDWE (1<<9)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_IWE (1<<8)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_DCR4 (1<<7)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_XDTS (1<<6)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE (1<<5)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_RW (1<<4)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_CDE (1<<2)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_RWE (1<<1)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE (1<<0)
++
++#define OMAP_REG_MMC_SYSTEM_TEST 0x38
++ #define OMAP_REG_MMC_SYSTEM_TEST_WAKD (1<<15)
++ #define OMAP_REG_MMC_SYSTEM_TEST_SSB (1<<14)
++ #define OMAP_REG_MMC_SYSTEM_TEST_RDYD (1<<13)
++ #define OMAP_REG_MMC_SYSTEM_TEST_DDIR (1<<12)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D3D (1<<11)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D2D (1<<10)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D1D (1<<9)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D0D (1<<8)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CDIR (1<<7)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CDAT (1<<6)
++ #define OMAP_REG_MMC_SYSTEM_TEST_MCKD (1<<5)
++ #define OMAP_REG_MMC_SYSTEM_TEST_SCKD (1<<4)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS3D (1<<3)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS2D (1<<2)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS1D (1<<1)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS0D (1<<0)
++
++
++#define OMAP_REG_MMC_MODULE_REV 0x3C
++ #define OMAP_REG_MMC_MODULE_REV_MINOR_MASK (0xF)
++ #define OMAP_REG_MMC_MODULE_REV_MINOR_SHIFT (0)
++ #define OMAP_REG_MMC_MODULE_REV_MAJOR_MASK (0xF0)
++ #define OMAP_REG_MMC_MODULE_REV_MAJOR_SHIFT (4)
++
++#define OMAP_REG_MMC_CMD_RESPONSE0 0x40
++ /* response bits 15-0 */
++#define OMAP_REG_MMC_CMD_RESPONSE1 0x44
++ /* response bits 31-16 */
++#define OMAP_REG_MMC_CMD_RESPONSE2 0x48
++ /* response bits 47-32 */
++#define OMAP_REG_MMC_CMD_RESPONSE3 0x4C
++ /* response bits 63-48 */
++#define OMAP_REG_MMC_CMD_RESPONSE4 0x50
++ /* response bits 79-64 */
++#define OMAP_REG_MMC_CMD_RESPONSE5 0x54
++ /* response bits 95-80 */
++#define OMAP_REG_MMC_CMD_RESPONSE6 0x58
++ /* response bits 111-96 */
++#define OMAP_REG_MMC_CMD_RESPONSE7 0x5C
++ /* response bits 127-112 */
++
++#define OMAP_REG_MMC_SUSPEND_RESUME 0x60
++ #define OMAP_REG_MMC_SUSPEND_RESUME_STOP (1<<3)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_SAVE (1<<2)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_RESUME (1<<1)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_SUSPEND (1<<0)
++
++#define OMAP_REG_MMC_SYSTEM_CONTROL 0x64
++ #define OMAP_REG_MMC_SYSTEM_CONTROL_SW_RESET (1<<1)
++
++#define OMAP_REG_MMC_SYSTEM_STATUS 0x68
++ #define OMAP_REG_MMC_SYSTEM_STATUS_RESET_DONE (1<<0)
++
++
++
++#define SD_DEFAULT_RESPONSE_BYTES 6
++
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++#define OMAP_MAX_CLOCK_DIVIDE 1023
++
++typedef struct _SD_CLOCK_TBL_ENTRY {
++ INT ClockRateDivisor; /* divisor */
++ UINT16 RegisterValue; /* register value for clock divisor */
++}SD_CLOCK_TBL_ENTRY;
++
++typedef enum _OMAP_DMA_MODE {
++ OMAP_DMA_NONE = 0,
++ OMAP_DMA_COMMON,
++ OMAP_DMA_SG
++}OMAP_DMA_MODE,*POMAP_DMA_MODE;
++
++typedef struct _SDHCD_DEVICE {
++ SDLIST List; /* linked list */
++ SDHCD Hcd; /* HCD description for bus driver */
++ OMAP_DMA_MODE DmaMode; /* current DMA mode */
++ BOOL DmaCapable; /* os layer supports DMA */
++ UINT16 Clock; /* current clock bit settings */
++ UINT32 BaseClock; /* base clock in hz */
++ UINT32 TimeOut; /* command timeout setting */
++ UINT32 DataTimeOut; /* data timeout setting */
++ UINT32 ClockSpinLimit; /* clock limit for command spin loops */
++ BOOL KeepClockOn;
++ BOOL IrqDetectArmed; /* IRQ detect was armed */
++ UINT8 CompletionCount; /* used to track when both DMA and command complete are done */
++ BOOL Cancel;
++ BOOL ShuttingDown;
++ BOOL ShortTransfer; /* do short transfer */
++ SDCONFIG_BUS_MODE_DATA SavedBusMode; /* saved bus mode */
++ HCD_OS_INFO OSInfo; /* the single device's OS-Specific */
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDLIST DeviceList; /* the list of current devices handled by this driver */
++ OS_SEMAPHORE DeviceListSem; /* protection for the DeviceList */
++ UINT DeviceCount; /* number of devices currently installed */
++ SDHCD_DRIVER Driver; /* OS dependent driver specific info */
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext);
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext);
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDeviceContext);
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq);
++BOOL HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL Flush);
++
++
++/* OS-dependent layer prototypes */
++SDIO_STATUS QueueEventResponse(PSDHCD_DEVICE pDeviceContext, INT WorkItemID);
++UINT16 MaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr);
++UINT16 UnmaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr);
++SDIO_STATUS SetUpHCDDMA(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext);
++BOOL WriteProtectSwitchOn(PSDHCD_DEVICE pDevice);
++void SDCancelDMATransfer(PSDHCD_DEVICE pDevice);
++SDIO_STATUS SetPowerLevel(PSDHCD_DEVICE pDeviceContext, BOOL On, SLOT_VOLTAGE_MASK Level);
++void GetDefaults(PSDHCD_DEVICE pDeviceContext);
++void CompleteRequestSyncDMA(PSDHCD_DEVICE pDeviceContext, PSDREQUEST pRequest, SDIO_STATUS Status);
++void MicroDelay(PSDHCD_DEVICE pDevice, INT Microseconds);
++void ClockEnable(PSDHCD_DEVICE pDevice, BOOL Enable);
++#define DBG_GPIO_PIN_1 1
++#define DBG_GPIO_PIN_2 2
++
++#ifdef OMAP_USE_DBG_GPIO
++void ToggleGPIOPin(PSDHCD_DEVICE pDevice, INT PinNo);
++#else
++#define ToggleGPIOPin(p,n)
++#endif
++/* end OS layer prototypes */
++
++#endif /* __SDIO_OMAP_HCD_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,3 @@
++# SDIO omap host controller makefile
++obj-m += sdio_omap_hcd.o
++sdio_omap_hcd-objs := sdio_hcd.o sdio_hcd_os.o sdio_hcd_os_2_6.o
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1363 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd.c
++
++ at abstract: Texas Instruments OMAP native Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDOMAPHCD
++#include "sdio_omap_hcd.h"
++
++#define FROM_ISR TRUE
++#define FROM_NORMAL FALSE
++
++void EndHCTransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL FromIsr);
++void ResetController(PSDHCD_DEVICE pDevice, BOOL Restore, BOOL FromIsr);
++
++#define OMAP_REQ_PROCESSING_USE_CLOCK_CONTROL
++
++#ifdef OMAP_REQ_PROCESSING_USE_CLOCK_CONTROL
++ /* control clock during request processing */
++#define ReqProcClkStartStop(p,on) ClockStartStop((p),(on))
++#else
++ /* let clock run free */
++#define ReqProcClkStartStop(p,on)
++#endif
++
++#define OMAP_COMMAND_DONE_POLLING 2000000
++#define OMAP_SHORT_TRANSFER_DONE_POLLING 3000000
++
++#define WAIT_FOR_HC_STATUS(pHct,DoneMask,Error,ErrorMask,Status,Timeout) \
++{ \
++ INT _timeoutCnt = (Timeout); \
++ (Status) = SDIO_STATUS_SUCCESS; \
++ while((_timeoutCnt > 0) && \
++ !(READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (DoneMask)) && \
++ !((Error) = READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (ErrorMask))){_timeoutCnt--;} \
++ (Error) = READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS) & (ErrorMask); \
++ if (0 == _timeoutCnt) {(Status) = SDIO_STATUS_DEVICE_ERROR; \
++ DBG_PRINT(SDDBG_ERROR, \
++ ("SDIO OMAP - status timeout, waiting for (mask=0x%X) (stat=0x%X)\n",\
++ (UINT)(DoneMask), READ_HOST_REG16((pHct), OMAP_REG_MMC_MODULE_STATUS))); \
++ DBG_ASSERT(FALSE);} \
++}
++
++#define SetFifoAFL(pHct,Depth) \
++{ \
++ UINT16 fifoSettings = (Depth)/2; \
++ if (fifoSettings > 0) {fifoSettings--;} \
++ fifoSettings = ((fifoSettings) << OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT) & \
++ OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK; \
++ WRITE_HOST_REG16((pHct), OMAP_REG_MMC_BUFFER_CONFIG, fifoSettings); \
++}
++
++#define SetFifoAEL(pHct,Depth) \
++{ \
++ UINT16 fifoSettings = (Depth)/2; \
++ if (fifoSettings > 0) {fifoSettings--;} \
++ fifoSettings = ((fifoSettings) << OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT) & \
++ OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK; \
++ WRITE_HOST_REG16((pHct), OMAP_REG_MMC_BUFFER_CONFIG, fifoSettings); \
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pDevice - device context
++ pReq - the request
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetResponseData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT wordCount;
++ INT byteCount;
++ UINT16 readBuffer[8];
++ UINT ii;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return;
++ }
++
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES - 1;
++ wordCount = (byteCount + 1) / 2;
++ /* move data into read buffer */
++ for (ii = 0; ii < wordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_RESPONSE0+(ii*4));
++ }
++ memcpy(&pReq->Response[0],readBuffer,byteCount);
++ } else {
++ wordCount = (byteCount + 1) / 2;
++
++ /* move data into read buffer */
++ for (ii = 0; ii < wordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_RESPONSE6+(ii*4));
++ }
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++ }
++
++ if (DBG_GET_DEBUG_LEVEL() >= OMAP_TRACE_REQUESTS) {
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO OMAP - Response Dump");
++ }
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ DumpCurrentRequestInfo - debug dump
++ Input: pDevice - device context
++ Output:
++ Return:
++ Notes: This function debug prints the current request
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void DumpCurrentRequestInfo(PSDHCD_DEVICE pDevice)
++{
++ if (pDevice->Hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - Current Request Command:%d, ARG:0x%8.8X\n",
++ pDevice->Hcd.pCurrentRequest->Command, pDevice->Hcd.pCurrentRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pDevice->Hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pDevice->Hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ pDevice->Hcd.pCurrentRequest->BlockCount,
++ pDevice->Hcd.pCurrentRequest->BlockLen,
++ pDevice->Hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateSDError - check for an SD error
++ Input: pDevice - device context
++ Status - error interrupt status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateSDError(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, UINT16 Status)
++{
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CERR) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP TranslateSDError : Warning command response has error bits set\n"));
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CTO) {
++ if (!((pReq->Command == 5) || (pReq->Command == 55) || (pReq->Command == 1))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Command Timeout: CMD:%d\n",pReq->Command));
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO OMAP (CMD:%d) Timeout, %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ pReq->Command,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ }
++ }
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP TranslateSDError : current controller status: 0x%X\n",
++ READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS)));
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_CCRC) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : command CRC error\n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_DCRC) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : write data CRC error\n"));
++ return SDIO_STATUS_BUS_WRITE_ERROR;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : read data CRC error\n"));
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ }
++ }
++
++ if (Status & OMAP_REG_MMC_MODULE_STATUS_DTO) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP TranslateSDError : data timeout\n"));
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP - untranslated error 0x%X\n", (UINT)Status));
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - SD clock control
++ Input: pDevice - device object
++ On - turn on or off (TRUE/FALSE)
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_DEVICE pDevice, BOOL On)
++{
++ UINT16 state;
++
++ DBG_PRINT(OMAP_TRACE_CLOCK, ("SDIO OMAP - ClockStartStop, %d\n", (UINT)On));
++
++ state = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG);
++ if (On) {
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ state |= pDevice->Clock;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ } else {
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pDevice - device object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DEVICE pDevice, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int ii;
++ int clockIndex;
++ UINT16 state = 0;
++ UINT32 rate;
++
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetBusMode\n"));
++
++ /* set clock index to the end max. divide */
++ pMode->ActualClockRate = (pDevice->BaseClock) / OMAP_MAX_CLOCK_DIVIDE;
++ clockIndex = OMAP_MAX_CLOCK_DIVIDE;
++ for (ii = 1; ii <= OMAP_MAX_CLOCK_DIVIDE ; ii++) {
++ rate = pDevice->BaseClock / ii;
++ if (pMode->ClockRate >= rate) {
++ pMode->ActualClockRate = rate;
++ clockIndex = ii;
++ break;
++ }
++ }
++
++ state = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG);
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_4BIT;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ state |= OMAP_REG_MMC_MODULE_CONFIG_4BIT;
++ break;
++ default:
++ break;
++ }
++
++ pDevice->Clock = clockIndex;
++ state &= ~OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK;
++ state |= pDevice->Clock;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, state);
++ MicroDelay(50);
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetBusMode Clock: %d Khz, ClockRate %d (%d) state:0x%X\n",
++ pMode->ActualClockRate, pMode->ClockRate, clockIndex, (UINT)state));
++}
++
++/*
++ * SetDataTimeout - set timeout for data transfers
++*/
++static void SetDataTimeout(PSDHCD_DEVICE pDevice, UINT TimeOut)
++{
++ UINT sdreg;
++ UINT to = TimeOut;
++
++ /* Check if we need to use timeout multiplier register */
++ sdreg = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ if (TimeOut > 0xFFFF) {
++ sdreg |= OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE;
++ to /= 1024;
++ } else {
++ sdreg &= ~OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE;
++ }
++ DBG_PRINT(OMAP_TRACE_CONFIG , ("SDIO OMAP - SetDataTimeout Timeout: %d, mode: 0x%x, to: 0x%x\n",
++ TimeOut, sdreg, to));
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, sdreg);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_DATA_READ_TIMEOUT, to);
++}
++
++/* DMA completion routine */
++void DMACompletion(PVOID pContext, SDIO_STATUS status, BOOL FromIsr)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pContext;
++ PSDREQUEST pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP (%s) (%s) DMA transfer failed, status: %d\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ (OMAP_DMA_COMMON == pDevice->DmaMode) ? "Common-Buffer" : "Direct",
++ status));
++ } else {
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP (%s) (%s) DMA transfer completed \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ (OMAP_DMA_COMMON == pDevice->DmaMode) ? "Common-Buffer" : "Direct"));
++ }
++
++ CompleteRequestSyncDMA(pDevice, pReq, status);
++ return;
++}
++
++/* transfer a FIFO worth of data, returns TRUE of all data was transfered */
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT16 *pFifo;
++
++ pFifo = (volatile UINT16 *)((UINT32)GET_HC_REG_BASE(pDevice) + OMAP_REG_MMC_DATA_ACCESS);
++
++ /* if we get called here because of an AEL interrupt, we know we have
++ * OMAP_MMC_FIFO_SIZE - OMAP_MMC_AEL_FIFO_THRESH room in the fifo to store more data */
++ dataCopy = min(pReq->DataRemaining,(UINT32)(OMAP_MMC_FIFO_SIZE - OMAP_MMC_AEL_FIFO_THRESH));
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ DBG_ASSERT((INT)pReq->DataRemaining >= 0);
++
++ /* copy to fifo */
++ while (dataCopy) {
++ data = *pBuf;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ data |= ((UINT16)*pBuf) << 8;
++ dataCopy--;
++ pBuf++;
++ }
++ *pFifo = data;
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Pending TX Remaining: %d \n",pReq->DataRemaining));
++
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++/* transfer a FIFO worth of data */
++BOOL HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL Flush)
++{
++
++ INT dataCopy;
++ PUINT8 pBuf;
++ UINT16 data;
++ volatile UINT16 *pFifo;
++
++ pFifo = (volatile UINT16 *)((UINT32)GET_HC_REG_BASE(pDevice) + OMAP_REG_MMC_DATA_ACCESS);
++
++ if (Flush) {
++ dataCopy = min(pReq->DataRemaining,(UINT32)OMAP_MMC_FIFO_SIZE);
++ } else {
++ /* each time we are called, we know we have at least a threshold's worth of data */
++ dataCopy = min(pReq->DataRemaining,(UINT32)OMAP_MMC_AFL_FIFO_THRESH);
++ }
++ /* get where we are */
++ pBuf = (PUINT8)pReq->pHcdContext;
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++
++ DBG_ASSERT((INT)pReq->DataRemaining >= 0);
++
++ /* copy from fifo */
++ while (dataCopy) {
++ data = *pFifo;
++ *pBuf = (UINT8)data;
++ dataCopy--;
++ pBuf++;
++ if (dataCopy) {
++ *pBuf = (UINT8)(data >> 8);
++ pBuf++;
++ dataCopy--;
++ }
++ }
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Pending RX Remaining: %d \n",pReq->DataRemaining));
++
++ if (pReq->DataRemaining < OMAP_MMC_AFL_FIFO_THRESH) {
++ return TRUE;
++ }
++
++ return FALSE;
++}
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ BOOL FromIsr)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 irqUnmask = 0;
++
++ do {
++
++ /* get the response data for the command */
++ GetResponseData(pDevice, pReq);
++
++ /* check for data */
++ if (!IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ break;
++ }
++
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pDevice->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO OMAP Check Response failed (CMD:%d), %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ pReq->Command,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ break;
++ }
++
++ if (pDevice->ShortTransfer) {
++ UINT16 hwErrors;
++ UINT16 waitMask;
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP Short %s data transfer (%d bytes) \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->DataRemaining));
++
++ /* wait for block sent/receive or error */
++ waitMask = OMAP_REG_MMC_MODULE_STATUS_BRS;
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* load FIFO */
++ HcdTransferTxData(pDevice, pReq);
++ waitMask |= OMAP_REG_MMC_MODULE_STATUS_EOFB;
++ }
++
++ WAIT_FOR_HC_STATUS(pDevice,
++ waitMask,
++ hwErrors,
++ OMAP_STATUS_DATA_PROCESSING_ERRORS,
++ status,
++ OMAP_SHORT_TRANSFER_DONE_POLLING);
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetController(pDevice,TRUE,FromIsr);
++ break;
++ }
++
++ if (hwErrors) {
++ status = TranslateSDError(pDevice, pReq, hwErrors);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* check for busy */
++ MicroDelay(1);
++ /* check if card entered busy */
++ if (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_CB)) {
++ /* we are done */
++ break;
++ }
++ /* card entered busy */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CB);
++
++ /* wait end of busy */
++ WAIT_FOR_HC_STATUS(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS_EOFB,
++ hwErrors,
++ 0, /* no need to check for errors */
++ status,
++ OMAP_SHORT_TRANSFER_DONE_POLLING)
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetController(pDevice,TRUE,FromIsr);
++ }
++
++ } else {
++ /* unload FIFO */
++ HcdTransferRxData(pDevice, pReq, TRUE);
++ }
++ /* done */
++ break;
++ }
++
++ /* enable error interrupts, data transfer will require interrupts */
++ irqUnmask = OMAP_REG_MMC_INTERRUPT_ERRORS;
++ status = SDIO_STATUS_PENDING;
++
++ if (pDevice->DmaMode != OMAP_DMA_NONE) {
++ /* for DMA let the DMA hardware run , we only want the interrupt
++ * for block sent/received in addition to the errors */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_BRS;
++
++ break;
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* set threshold for FIFO empty level */
++ SetFifoAEL(pDevice,OMAP_MMC_AEL_FIFO_THRESH);
++ /* wait for AEL interrupts */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_AE;
++ } else {
++ if (pReq->DataRemaining < OMAP_MMC_AFL_FIFO_THRESH) {
++ /* don't need AFL, wait for last block received interrupt instead */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_BRS;
++ } else {
++ /* set trigger level for FIFO full level */
++ SetFifoAFL(pDevice,OMAP_MMC_AFL_FIFO_THRESH);
++ /* more data is expected */
++ irqUnmask |= OMAP_REG_MMC_INTERRUPT_ENABLE_AF;
++ }
++ }
++
++ } while (FALSE);
++
++ if (SDIO_STATUS_PENDING == status) {
++ if (irqUnmask != 0) {
++ UnmaskIrq(pDevice, irqUnmask, FromIsr);
++ }
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP HcdRequest Pending %s data transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ UINT16 temp;
++ PSDREQUEST pReq;
++
++ pDevice->CompletionCount = 0;
++ pDevice->DmaMode = OMAP_DMA_NONE;
++ pDevice->ShortTransfer = FALSE;
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ do {
++ if (pDevice->ShuttingDown) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest returning canceled\n"));
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++
++ /* make sure error ints and EOC is masked*/
++ MaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ERRORS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOC,
++ FROM_NORMAL);
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, 0);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_TIMEOUT, pDevice->TimeOut);
++
++ /* clear all status bits (including error bits) that deals with request processing */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS);
++
++ if (READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP ERROR!!! status did not clear: 0x%X\n",
++ READ_HOST_REG16(pDevice,OMAP_REG_MMC_MODULE_STATUS)));
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ default:
++ case SDREQ_FLAGS_NO_RESP:
++ temp = OMAP_REG_MMC_CMD_NORESPONSE;
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ temp = OMAP_REG_MMC_CMD_R1;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp = OMAP_REG_MMC_CMD_R1 | OMAP_REG_MMC_CMD_R1BUSY;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp = OMAP_REG_MMC_CMD_R2;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ temp = OMAP_REG_MMC_CMD_R3;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* SDIO R4s are just OCR responses equivalent to an R3*/
++ temp = OMAP_REG_MMC_CMD_R3;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ /* R5s are just R1 responses, do not use the R5 type in this controller
++ * because it will disable response timeout detection unless you set
++ * the C5E,C14E..bits */
++ temp = OMAP_REG_MMC_CMD_R1;
++ break;
++ case SDREQ_FLAGS_RESP_R6:
++ temp = OMAP_REG_MMC_CMD_R6;
++ break;
++ }
++
++ /* get the command type */
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ /* broadcast no-response */
++ temp |= OMAP_REG_MMC_CMD_TYPE_BC;
++ break;
++
++ case SDREQ_FLAGS_RESP_R2:
++ if ((pReq->Command == CMD9) || (pReq->Command == CMD10)) {
++ temp |= OMAP_REG_MMC_CMD_TYPE_AC;
++ } else if (pReq->Command == CMD2) {
++ temp |= OMAP_REG_MMC_CMD_TYPE_BCR;
++ } else {
++ DBG_ASSERT(FALSE);
++ }
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_R6:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* responses that are broadcast */
++ temp |= OMAP_REG_MMC_CMD_TYPE_BCR;
++ break;
++ default:
++ /* all other commands are addressed responses */
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ /* commands with data */
++ temp |= OMAP_REG_MMC_CMD_TYPE_ADTC;
++ } else {
++ /* all commands without data */
++ temp |= OMAP_REG_MMC_CMD_TYPE_AC;
++ }
++ break;
++ }
++
++ GetDefaults(pDevice);
++
++ ReqProcClkStartStop(pDevice, CLOCK_ON);
++
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)){
++ /* set the block size register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH, pReq->BlockLen-1);
++ /* set block count register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT, pReq->BlockCount-1);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP HcdRequest: %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest: blen: 0x%X, nblk: 0x%X\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT)));
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ temp |= IS_SDREQ_WRITE_DATA(pReq->Flags) ?
++ OMAP_REG_MMC_CMD_DDIR_WRITE : OMAP_REG_MMC_CMD_DDIR_READ;
++
++ SetDataTimeout(pDevice, pDevice->DataTimeOut);
++
++ if ((pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) &&
++ (pReq->DataRemaining < OMAP_MAX_SHORT_TRANSFER_SIZE)) {
++ /* flag current request as a short transfer */
++ pDevice->ShortTransfer = TRUE;
++ }
++
++ if (!pDevice->ShortTransfer) {
++ /* setup dma transfer */
++ if (pDevice->DmaCapable) {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ /* caller passed a scatter gather list */
++ pDevice->DmaMode = OMAP_DMA_SG;
++ } else {
++ /* try common buffer */
++ pDevice->DmaMode = OMAP_DMA_COMMON;
++ }
++ } else {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++ }
++ }
++
++ if (pDevice->DmaMode != OMAP_DMA_NONE) {
++ /* check DMA */
++ status = CheckDMA(pDevice, pReq);
++
++ if (!SDIO_SUCCESS(status)) {
++ if ((SDIO_STATUS_UNSUPPORTED == status) &&
++ (OMAP_DMA_COMMON == pDevice->DmaMode)){
++ /* if we tried common buffer, the length may be unaligned,
++ * punt it to PIO mode */
++ pDevice->DmaMode = OMAP_DMA_NONE;
++ status = SDIO_STATUS_SUCCESS;
++ /* fall through */
++ } else {
++ /* fail the request */
++ break;
++ }
++ } else {
++ /* we are doing DMA */
++ status = SetUpHCDDMA(pDevice,
++ pReq,
++ DMACompletion,
++ pDevice);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++ }
++
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest:(1) blen: %d, nblk: %d\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT)));
++ }
++
++ /* set the argument register */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_ARG_LOW, (UINT16)(pReq->Argument & 0xFFFF));
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_ARG_HI, (UINT16)((pReq->Argument & 0xFFFF0000) >> 16));
++ /* set the command */
++ temp |= (pReq->Command & OMAP_REG_MMC_CMD_MASK);
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++ /* set command timeout */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_TIMEOUT, pDevice->TimeOut);
++
++ if ((SDHCD_GET_OPER_CLOCK(pHcd) < pDevice->ClockSpinLimit) &&
++ (pReq->Command != CMD3)) {
++ /* clock rate is very low, need to use interrupts here */
++ UnmaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ERRORS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOC,
++ FROM_NORMAL);
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, temp);
++
++ status = SDIO_STATUS_PENDING;
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest using interrupt for command done.*** with data. (clock:%d, ref:%d)\n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ } else {
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HcdRequest using interrupt for command done. (clock:%d, ref:%d) \n",
++ SDHCD_GET_OPER_CLOCK(pHcd),pDevice->ClockSpinLimit));
++ }
++
++ break;
++ }
++
++ /* if we get here we are polling, interrupt errors and EOC should be masked */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, temp);
++
++ WAIT_FOR_HC_STATUS(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS_EOC,
++ temp,
++ OMAP_STATUS_CMD_PROCESSING_ERRORS,
++ status,
++ OMAP_COMMAND_DONE_POLLING);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO OMAP HCD (cmd-inline) polling failed (sd command:%d,status:%d)\n",
++ pReq->Command,status));
++ ResetController(pDevice,TRUE,FROM_NORMAL);
++ if (pReq->Command == CMD3) {
++ status = SDIO_STATUS_SUCCESS;
++ } else {
++ break;
++ }
++ }
++
++ DBG_PRINT(OMAP_TRACE_REQUESTS,
++ ("SDIO OMAP HCD (cmd-inline) statreg: 0x%X config:0x%X\n",
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS),
++ READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG)));
++
++ if (temp & OMAP_STATUS_CMD_PROCESSING_ERRORS) {
++ status = TranslateSDError(pDevice, pReq, temp);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ status = ProcessCommandDone(pDevice,pReq,FALSE);
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ pReq->Status = status;
++ EndHCTransfer(pDevice, pReq, FROM_NORMAL);
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags)) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ return SDIO_STATUS_PENDING;
++ } else {
++ /* complete the request */
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdRequest Command Done, status:%d \n", status));
++ }
++ pDevice->Cancel = FALSE;
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pHcd->pContext;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 configSave;
++
++ if(pDevice->ShuttingDown) {
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdConfig returning canceled\n"));
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (GET_SDCONFIG_CMD(pConfig)){
++ case SDCONFIG_GET_WP:
++ if (WriteProtectSwitchOn(pDevice)) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP HcdConfig sending init clocks\n"));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ALL_INT,FROM_NORMAL);
++ ReqProcClkStartStop(pDevice, CLOCK_ON);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD, OMAP_REG_MMC_CMD_INAB);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_ALL);
++ while(!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) & OMAP_REG_MMC_MODULE_STATUS_EOC))
++ ;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_EOC);
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++
++ irqModeFlags =
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: 4 Bit IRQ mode \n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pDevice->KeepClockOn = TRUE;
++ } else {
++ /* in 1 bit mode, the clock can be left off */
++ pDevice->KeepClockOn = FALSE;
++ }
++ }
++ pDevice->IrqDetectArmed = TRUE;
++
++ /* enable SDIO mode IRQ detection */
++ configSave = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ configSave |= OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, configSave);
++ /* enable detection IRQ */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: enable SDIO IRQ\n"));
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ } else {
++ pDevice->KeepClockOn = FALSE;
++ pDevice->IrqDetectArmed = FALSE;
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig: disable SDIO IRQ\n"));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ configSave = READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG);
++ configSave &= ~OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG, configSave);
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP HcdConfig - SDIO IRQ re-armed\n"));
++ /* make sure status is cleared */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CIRQ);
++ pDevice->IrqDetectArmed = TRUE;
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_NORMAL);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pDevice, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ /* save it in case we have to restore it later */
++ memcpy(&pDevice->SavedBusMode,pConfig->pData,sizeof(SDCONFIG_BUS_MODE_DATA));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ DBG_PRINT(OMAP_TRACE_CONFIG, ("SDIO OMAP HcdConfig PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ status = SetPowerLevel(pDevice,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask);
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ *((CT_DEBUG_LEVEL *)pConfig->pData) = DBG_GET_DEBUG_LEVEL();
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_SET_DEBUG_LEVEL(*((CT_DEBUG_LEVEL *)pConfig->pData));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_WARN, ("SDIO OMAP HCD: HcdConfig - unsupported command: 0x%X\n",
++ GET_SDCONFIG_CMD(pConfig)));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++void ResetController(PSDHCD_DEVICE pDevice, BOOL Restore, BOOL FromIsr)
++{
++ INT ii;
++
++ ClockStartStop(pDevice, CLOCK_OFF);
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_CONTROL, OMAP_REG_MMC_SYSTEM_CONTROL_SW_RESET);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_CONTROL, 0);
++
++ /* wait for done */
++ for(ii = 0;
++ (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_SYSTEM_STATUS) & OMAP_REG_MMC_SYSTEM_STATUS_RESET_DONE))
++ && (ii < 1000);
++ ii++);
++
++ if (ii >= 1000) {
++ /* reset on 1610 is broken, see errata, use alternate approach */
++ /* cycle power */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG, 0);
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG,
++ OMAP_REG_MMC_MODULE_CONFIG_PWRON | 1);
++ }
++
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_CONFIG,
++ OMAP_REG_MMC_MODULE_CONFIG_MODE_MMCSD | OMAP_REG_MMC_MODULE_CONFIG_PWRON);
++
++ /* configure the SDIO mode */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG,
++ OMAP_REG_MMC_SDIO_MODE_CONFIG_DCR4);
++
++ SetDataTimeout(pDevice, OMAP_DEFAULT_DATA_TIMEOUT);
++
++ /* set the default timeouts */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_CMD_TIMEOUT, pDevice->TimeOut);
++ /* clear all status bits, from chip erratta, the status may not clear on a reset */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, OMAP_REG_MMC_MODULE_STATUS_ALL);
++
++ if (!Restore) {
++ return;
++ }
++
++ /* restore bus clock and bus mode */
++ SetBusMode(pDevice,&pDevice->SavedBusMode);
++
++ /* restore interrupt state */
++ if (pDevice->IrqDetectArmed) {
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FromIsr);
++ }
++
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize controller
++ Input: pDeviceContext - device context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 version;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HcdInitialize\n"));
++
++ /* reset the controller */
++ ResetController(pDeviceContext, FALSE,FROM_NORMAL);
++
++ /* display version info */
++ version = READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_MODULE_REV);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HcdInitialize: Module Spec verison: %d.%d\n",
++ ((version & OMAP_REG_MMC_MODULE_REV_MAJOR_MASK) >> OMAP_REG_MMC_MODULE_REV_MAJOR_SHIFT),
++ ((version & OMAP_REG_MMC_MODULE_REV_MINOR_MASK) >> OMAP_REG_MMC_MODULE_REV_MINOR_SHIFT)));
++
++ if (pDeviceContext->BaseClock == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP invalid base clock setting\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ return status;
++ }
++
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO OMAP Using base clock: %dHz, max bus clock: %dHz, max blocks: %d max bytes per block: %d\n",
++ pDeviceContext->BaseClock,
++ pDeviceContext->Hcd.MaxClockRate,
++ pDeviceContext->Hcd.MaxBlocksPerTrans,
++ pDeviceContext->Hcd.MaxBytesPerBlock));
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HcdInitialize: SlotVoltageCaps: 0x%X, MaxSlotCurrent: 0x%X\n",
++ (UINT)pDeviceContext->Hcd.SlotVoltageCaps, (UINT)pDeviceContext->Hcd.MaxSlotCurrent));
++
++ /* interrupts will get enabled by the caller after all of the OS dependent work is done */
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HcdInitialize\n"));
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate controller
++ Input: pDeviceContext - context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext)
++{
++ PSDREQUEST pReq;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HcdDeinitialize\n"));
++
++
++ pReq = GET_CURRENT_REQUEST(&pDeviceContext->Hcd);
++
++ if (pReq != NULL) {
++ pReq->Status = SDIO_STATUS_CANCELED;
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO OMAP HcdDeinitialize - cancelling request. (command:%d) mod status:0x%X, IRQ Enables:0x%X\n",
++ pReq->Command, (UINT)READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_MODULE_STATUS),
++ (UINT)READ_HOST_REG16(pDeviceContext, OMAP_REG_MMC_INTERRUPT_ENABLE)));
++ }
++
++ pDeviceContext->KeepClockOn = FALSE;
++ MaskIrq(pDeviceContext, OMAP_REG_MMC_INTERRUPT_ALL_INT, FROM_NORMAL);
++ pDeviceContext->ShuttingDown = TRUE;
++ ClockStartStop(pDeviceContext, CLOCK_OFF);
++
++ if (pReq != NULL) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HcdDeinitialize\n"));
++}
++
++void EndHCTransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL FromIsr)
++{
++
++ if (!SDIO_SUCCESS(pReq->Status) && (pDevice->DmaMode != OMAP_DMA_NONE)) {
++ /* DMA may be running cancel the DMA transfer */
++ SDCancelDMATransfer(pDevice);
++ }
++
++ MaskIrq(pDevice,
++ (OMAP_REG_MMC_INTERRUPT_ALL_INT & ~OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ),FromIsr);
++
++ if (!pDevice->KeepClockOn) {
++ ReqProcClkStartStop(pDevice, CLOCK_OFF);
++ }
++
++ if (!SDIO_SUCCESS(pReq->Status)) {
++ switch (pReq->Status) {
++ case SDIO_STATUS_BUS_READ_TIMEOUT:
++ case SDIO_STATUS_BUS_READ_CRC_ERR:
++ case SDIO_STATUS_BUS_WRITE_ERROR:
++ case SDIO_STATUS_BUS_RESP_CRC_ERR:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP - resetting controller on bus errors (CMD:%d) \n",
++ pReq->Command));
++ /* controller gets stuck on some errors */
++ ResetController(pDevice,TRUE,FromIsr);
++ break;
++ default:
++ break;
++ }
++ }
++
++ if ((DBG_GET_DEBUG_LEVEL() >= OMAP_TRACE_DATA) && SDIO_SUCCESS(pReq->Status) &&
++ IS_SDREQ_DATA_TRANS(pReq->Flags) && (pDevice->DmaMode != OMAP_DMA_SG)) {
++ if (!IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ SDLIB_PrintBuffer(pReq->pDataBuffer,(pReq->BlockLen*pReq->BlockCount),"SDIO OMAP - RX DataDump");
++ } else {
++ SDLIB_PrintBuffer(pReq->pDataBuffer,(pReq->BlockLen*pReq->BlockCount),"SDIO OMAP - TX DataDump");
++ }
++ }
++
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdSDInterrupt - process controller interrupt
++ Input: pDeviceContext - context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDevice)
++{
++ UINT16 statusErrs,errorMask,statusMask;
++ PSDREQUEST pReq = NULL;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("+SDIO OMAP ISR handler \n"));
++
++ pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ while (1) {
++
++ /* get status */
++ statusErrs = READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS);
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, status: 0x%X \n",
++ (UINT)statusErrs));
++
++ /* for ISR processing, only deal with interrupts that are actually enabled */
++ statusMask = READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE);
++ statusErrs &= statusMask;
++ /* ack the status bits we care about */
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS, statusErrs);
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, valid status: 0x%X, IRQ Enables:0x%X\n",
++ (UINT)statusErrs, statusMask));
++
++ /* deal with SDIO interrupts */
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_CIRQ) {
++ if (READ_HOST_REG16(pDevice, OMAP_REG_MMC_SDIO_MODE_CONFIG)
++ & OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE) {
++ /* this interrupt is level triggered and will remain set until the card interrupt
++ source is cleared. */
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP ISR - SDIO_IRQ detected\n"));
++ /* ack*/
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CIRQ);
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ, FROM_ISR);
++ QueueEventResponse(pDevice, WORK_ITEM_SDIO_IRQ);
++ } else {
++ DBG_ASSERT_WITH_MSG(FALSE,
++ "SDIO OMAP ISR - unexpected card interrupt!\n");
++ }
++ }
++
++ if (0 == statusErrs) {
++ /* nothing to process */
++ break;
++ }
++
++ if (NULL == pReq) {
++ /* nothing more to do */
++ break;
++ }
++
++ errorMask = OMAP_REG_MMC_MODULE_STATUS_CTO |
++ OMAP_REG_MMC_MODULE_STATUS_CCRC;
++
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)){
++ errorMask |= OMAP_REG_MMC_MODULE_STATUS_DTO | OMAP_REG_MMC_MODULE_STATUS_DCRC;
++ }
++
++ if (statusErrs & errorMask) {
++ status = TranslateSDError(pDevice, pReq, (statusErrs & errorMask));
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++
++ /* if we reach here, there were no command processing errors */
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_EOC) {
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOC, FROM_ISR);
++ status = ProcessCommandDone(pDevice,
++ pReq,
++ TRUE);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_AE) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR TX Transfer AE\n"));
++
++ /* refill the FIFO */
++ if (HcdTransferTxData(pDevice, pReq)) {
++ /* fifo contains final data, disable almost empty interrupts */
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_AE, FROM_ISR);
++ /* get ready for BRS or EOFB, it has been observed that EOFB can come early
++ * and mask out the BRS bit, this looks like a controller bug */
++ UnmaskIrq(pDevice,
++ OMAP_REG_MMC_INTERRUPT_ENABLE_BRS | OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,
++ FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_BUSY,
++ ("SDIO OMAP ISR, TX near complete, waiting for BRS or EOFB (bcnt:%d,blen:%d)\n",
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT),
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH)));
++ } else {
++ /* more data to go, if this is a multi-block transfer we want to make sure
++ * the EOFB is cleared for all blocks except the last one, we will
++ * actually wait for EOFB on the last block */
++ if (READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT) > 2) {
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_EOFB);
++ }
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_AF) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(!IS_SDREQ_WRITE_DATA(pReq->Flags));
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR RX Transfer AF\n"));
++ /* drain the FIFO */
++ if (HcdTransferRxData(pDevice, pReq, FALSE)) {
++ /* last bit of data remaining, we can wait for BRS */
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_AF, FROM_ISR);
++ /* get ready for BRS */
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_BRS,FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR, RX near complete, waiting for BRS \n"));
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_BRS) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_BRS, FROM_ISR);
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* check for busy on write operations */
++ MicroDelay(10);
++ /* check card enter busy */
++ if (!(READ_HOST_REG16(pDevice, OMAP_REG_MMC_MODULE_STATUS) &
++ OMAP_REG_MMC_MODULE_STATUS_CB)) {
++ DBG_PRINT(OMAP_TRACE_BUSY, ("SDIO OMAP ISR TX Transfer Done - not busy \n"));
++ status = SDIO_STATUS_SUCCESS;
++ /* we are done */
++ break;
++ }
++
++ /* clear status */
++ WRITE_HOST_REG16(pDevice,
++ OMAP_REG_MMC_MODULE_STATUS,
++ OMAP_REG_MMC_MODULE_STATUS_CB);
++ DBG_PRINT(OMAP_TRACE_BUSY, ("SDIO OMAP ISR TX Transfer Done - waiting on busy release \n"));
++ statusErrs &= ~OMAP_REG_MMC_MODULE_STATUS_CB;
++ UnmaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,FROM_ISR);
++
++ } else {
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP ISR RX Transfer Done \n"));
++ if (pDevice->DmaMode == OMAP_DMA_NONE) {
++ /* In PIO mode, the FIFO may contain some residue data */
++ HcdTransferRxData(pDevice, pReq, TRUE);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++ }
++
++ if (statusErrs & OMAP_REG_MMC_MODULE_STATUS_EOFB) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ MaskIrq(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB,FROM_ISR);
++ DBG_PRINT(OMAP_TRACE_BUSY,("SDIO OMAP ISR Card Busy Done (bcnt:%d,blen:%d)\n",
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_COUNT),
++ (UINT)READ_HOST_REG16(pDevice, OMAP_REG_MMC_BLOCK_LENGTH)));
++ /* the write operation is finally done */
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ pReq->Status = status;
++ EndHCTransfer(pDevice,pReq,FROM_ISR);
++ if (OMAP_DMA_NONE == pDevice->DmaMode) {
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* using some form of DMA */
++ if (!SDIO_SUCCESS(status)) {
++ /* EndHCTransfer will cancel DMA, no need to synch with DMA */
++ QueueEventResponse(pDevice, WORK_ITEM_IO_COMPLETE);
++ } else {
++ /* sync request completion with DMA */
++ CompleteRequestSyncDMA(pDevice,pReq,status);
++ }
++ }
++ }
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("-SDIO OMAP ISR handler \n"));
++
++ return TRUE;
++}
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,147 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_linux.h
++
++ at abstract: include file for Texas Instruments OMAP host controller, linux dependent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/device.h>
++#endif
++#include <asm/arch/dma.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <asm/hardware/clock.h>
++#endif
++#include <asm/irq.h>
++#include <linux/delay.h>
++
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++#define OMAP_BASE_ADDRESS1 0x4809C000
++#define OMAP_BASE_LENGTH 0x6A
++
++#define OMAP_MODULE_CLOCK 96000000
++#define OMAP_MAX_DEVICE_COUNT 2
++#define OMAP_DEFAULT_DEVICE_COUNT 1
++#define OMAP_DEFAULT_FIRST_DEVICE 0
++#define OMAP_DMA_MASK 0xFFFFFFFF
++
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++/* debounce delay for slot */
++#define SD_SLOT_DEBOUNCE_MS 500
++
++
++/* device base name */
++#define SDIO_BD_BASE "sdiobd"
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef void (*PDMA_TRANSFER_COMPLETION)(PVOID,SDIO_STATUS,BOOL);
++
++/* device data*/
++typedef struct _HCD_OS_INFO {
++ POS_PNPDEVICE pBusDevice; /* our device registered with bus driver */
++ SDHCD_MEMORY Address; /* memory address of this device */
++ spinlock_t AddressSpinlock; /* use to protect reghisters when needed */
++ UINT8 InitStateMask;
++#define SDIO_BASE_MAPPED 0x01
++#define SDIO_IRQ_INTERRUPT_INIT 0x04
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x40
++#define SDHC_TIMER_INIT 0x80
++ spinlock_t Lock; /* lock against the ISR */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel;
++ BOOL ShuttingDown; /* indicates shut down of HCD) */
++ struct work_struct iocomplete_work; /* work item definintions */
++ struct work_struct carddetect_work; /* work item definintions */
++ struct work_struct sdioirq_work; /* work item definintions */
++ DMA_ADDRESS hDmaBuffer; /* handle for data buffer */
++ PUINT8 pDmaBuffer; /* virtual address of command buffer */
++ UINT32 CommonBufferSize; /* size of CommonBuffer */
++ int Interrupt;
++ int DmaRxId;
++ int DmaTxId;
++ int DmaRxChannel; /* receive DMA channel */
++ int DmaTxChannel; /* transmit DMA channel */
++ int LastTransfer; /* length of last transfer */
++ PSDDMA_DESCRIPTOR pDmaList; /* in use scatter-gather list */
++ UINT SGcount; /* count of in-use scatter gather list */
++ PVOID TransferContext; /* context passed to TransferCompletion routine */
++ PDMA_TRANSFER_COMPLETION pTransferCompletion; /* transfer completion routine */
++}HCD_OS_INFO, *PHCD_OS_INFO;
++
++typedef struct _SDHCD_DRIVER {
++ OS_PNPDEVICE HcdDevice; /* the OS device for this HCD */
++ OS_PNPDRIVER HcdDriver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION Dma; /* driver DMA description */
++}SDHCD_DRIVER, *PSDHCD_DRIVER;
++
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++
++#define READ_HOST_REG32(pDevice, OFFSET) \
++ _READ_DWORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG32(pDevice, OFFSET, VALUE) \
++ _WRITE_DWORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET),(VALUE))
++#define READ_HOST_REG16(pDevice, OFFSET) \
++ _READ_WORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET))
++#define WRITE_HOST_REG16(pDevice, OFFSET, VALUE) \
++ _WRITE_WORD_REG((((UINT32)((pDevice)->OSInfo.Address.pMapped))) + (OFFSET),(VALUE))
++
++#define GET_HC_REG_BASE(pDevice) (pDevice)->OSInfo.Address.pMapped
++
++#define OMAP_USE_DBG_GPIO
++/* prototypes */
++#endif /* __SDIO_HCD_LINUX_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,608 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Linux OMAP native SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++
++#define DBG_DECLARE 4;
++#include <linux/sdio/ctsystem.h>
++#include "sdio_omap_hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#include <asm/mach-types.h>
++#include <asm/arch/dma.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <asm/arch/mux.h>
++#include <linux/dma-mapping.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#else
++#include <asm/arch/irq.h>
++#endif
++
++#define DESCRIPTION "SDIO OMAP HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId);
++static void Remove(struct pnp_dev *pBusDevice);
++#else
++static int Probe(POS_PNPDEVICE pBusDevice, const PUINT pId);
++static void Remove(POS_PNPDEVICE pBusDevice);
++BOOL SetupTranceiver(void);
++void CleanupTranceiver(void);
++#endif
++
++static void RemoveDevice(POS_PNPDEVICE pBusDevice, PSDHCD_DRIVER_CONTEXT pHcdContext);
++SDIO_STATUS InitOmap(PSDHCD_DEVICE pDevice, UINT deviceNumber);
++void DeinitOmap(PSDHCD_DEVICE pDevice);
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++static void hcd_carddetect_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++#define DEFAULT_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | SDHCD_ATTRIB_BUS_4BIT | \
++ SDHCD_ATTRIB_POWER_SWITCH | \
++ 0)
++
++static UINT32 hcdattributes = DEFAULT_ATTRIBUTES;
++
++module_param(hcdattributes, int, 0644);
++MODULE_PARM_DESC(hcdattributes, "OMAP Attributes");
++static UINT32 base_clock = OMAP_MODULE_CLOCK;
++module_param(base_clock, int, 0444);
++MODULE_PARM_DESC(base_clock, "BaseClock Hz ");
++static UINT32 timeout = OMAP_DEFAULT_CMD_TIMEOUT;
++module_param(timeout, int, 0644);
++MODULE_PARM_DESC(timeout, "OMAP command timeout");
++static UINT32 data_timeout = OMAP_DEFAULT_DATA_TIMEOUT;
++module_param(data_timeout, int, 0644);
++MODULE_PARM_DESC(data_timeout, "OMAP data timeout");
++static UINT32 device_count = OMAP_DEFAULT_DEVICE_COUNT;
++module_param(device_count, int, 0644);
++MODULE_PARM_DESC(device_count, "OMAP number of devices");
++static UINT32 first_device = OMAP_DEFAULT_FIRST_DEVICE;
++module_param(first_device, int, 0644);
++MODULE_PARM_DESC(first_device, "OMAP first device to create");
++static UINT32 clock_spin_limit = HCD_COMMAND_MIN_POLLING_CLOCK;
++module_param(clock_spin_limit, int, 0644);
++MODULE_PARM_DESC(clock_spin_limit, "OMAP command clock spin time");
++
++static UINT32 max_sdbus_clock = OMAP_MODULE_CLOCK;
++module_param(max_sdbus_clock, int, 0644);
++MODULE_PARM_DESC(max_sdbus_clock, "OMAP max SDIO bus clock");
++
++UINT32 max_blocks = OMAP_MAX_BLOCKS;
++module_param(max_blocks, int, 0644);
++MODULE_PARM_DESC(max_blocks, "OMAP Max Blocks Per Transfer");
++UINT32 max_bytes_per_block = OMAP_MAX_BYTES_PER_BLOCK;
++module_param(max_bytes_per_block, int, 0644);
++MODULE_PARM_DESC(max_bytes_per_block, "OMAP Max Blocks per transfer");
++
++INT gpiodebug = 0;
++module_param(gpiodebug, int, 0444);
++MODULE_PARM_DESC(gpiodebug, "Special GPIO debug");
++
++INT noDMA = 0;
++module_param(noDMA, int, 0444);
++MODULE_PARM_DESC(noDMA, "Force No DMA");
++
++UINT32 dma_buffer_size = 16*1024;
++module_param(dma_buffer_size, int, 0644);
++MODULE_PARM_DESC(dma_buffer_size, "OMAP common buffer DMA size");
++
++UINT32 builtin_card = 0;
++module_param(builtin_card, int, 0644);
++MODULE_PARM_DESC(builtin_card, "SDIO card is built-in");
++
++UINT32 async_irq = 0;
++module_param(async_irq, int, 0644);
++MODULE_PARM_DESC(async_irq, "Allow async IRQ detection in 4 bit mode");
++
++/* the driver context data */
++SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .DeviceCount = 0,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ .Driver.HcdDevice.name = "sdio_omap_hcd",
++ .Driver.HcdDriver.name = "sdio_omap_hcd",
++ .Driver.HcdDriver.probe = Probe,
++ .Driver.HcdDriver.remove = Remove,
++#endif
++ .Driver.Dma.Mask = OMAP_DMA_MASK,
++ .Driver.Dma.Flags = SDDMA_DESCRIPTION_FLAG_DMA,
++ .Driver.Dma.MaxBytesPerDescriptor = 0xFFFFFFFF, /* the controller can DMA up to 4GB per DMA transfer*/
++ .Driver.Dma.AddressAlignment = 0x01, /* illegal address bits, buffers must be on even word bounadries */
++ .Driver.Dma.LengthAlignment = 0x1, /* illegal address bits, buffer lengths must be even */
++ .Driver.Dma.MaxDescriptors = 1, /* we don't suppport scatter-gather DMA, just a single buffer at a time */
++};
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId)
++#else
++static int Probe(POS_PNPDEVICE pBusDevice, const PUINT pId)
++#endif
++{
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DEVICE pDeviceContext = NULL;
++ int ii;
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HCD: Probe - probing for new device\n"));
++
++ if (!async_irq) {
++ hcdattributes |= SDHCD_ATTRIB_NO_4BIT_IRQ;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: No 4-bit IRQ detection\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: 4-bit IRQ detect without Clock enabled\n"));
++ }
++
++ if (!builtin_card) {
++ /* use slot polling */
++ hcdattributes |= SDHCD_ATTRIB_SLOT_POLLING;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: Built-in Card forcing ATTACH\n"));
++ }
++
++ max_blocks = min(max_blocks, (UINT32)OMAP_MAX_BLOCKS);
++ max_bytes_per_block = min(max_bytes_per_block, (UINT32)OMAP_MAX_BYTES_PER_BLOCK);
++
++ if (device_count > OMAP_MAX_DEVICE_COUNT) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: Probe - too many devices requested: %d\n", device_count));
++ return -EINVAL;
++ }
++
++ for (ii = first_device; ii < device_count+first_device; ii++) {
++ /* create a device the slot */
++ /* allocate a device context for this new device */
++ pDeviceContext = (PSDHCD_DEVICE)KernelAlloc(sizeof(SDHCD_DEVICE));
++ if (pDeviceContext == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: Probe - no memory for device context\n"));
++ err = -ENOMEM;
++ break;
++ }
++ ZERO_POBJECT(pDeviceContext);
++ SDLIST_INIT(&pDeviceContext->List);
++ pDeviceContext->OSInfo.pBusDevice = pBusDevice;
++ pDeviceContext->OSInfo.CommonBufferSize = dma_buffer_size;
++ SET_SDIO_STACK_VERSION(&pDeviceContext->Hcd);
++ pDeviceContext->Hcd.pName = (PTEXT)KernelAlloc(SDHCD_MAX_DEVICE_NAME+1);
++ snprintf(pDeviceContext->Hcd.pName, SDHCD_MAX_DEVICE_NAME, SDIO_BD_BASE"%i:%i",
++ pHcdContext->DeviceCount++, ii);
++ pDeviceContext->Hcd.Attributes = hcdattributes;
++ pDeviceContext->Hcd.pContext = pDeviceContext;
++ pDeviceContext->Hcd.pRequest = HcdRequest;
++ pDeviceContext->Hcd.pConfigure = HcdConfig;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ pDeviceContext->Hcd.pDevice = &pBusDevice->dev;
++#endif
++ pDeviceContext->Hcd.pModule = THIS_MODULE;
++ pDeviceContext->BaseClock = base_clock;
++ pDeviceContext->Hcd.MaxSlotCurrent = OMAP_DEFAULT_CURRENT;
++ pDeviceContext->Hcd.SlotVoltageCaps = SLOT_POWER_3_0V | SLOT_POWER_3_3V;
++ pDeviceContext->Hcd.SlotVoltagePreferred = SLOT_POWER_3_0V;
++ pDeviceContext->Hcd.MaxClockRate = min(max_sdbus_clock,base_clock);
++ pDeviceContext->TimeOut = timeout;
++ pDeviceContext->DataTimeOut = data_timeout;
++
++ pDeviceContext->Hcd.pConfigure = HcdConfig;
++
++ /* add device to our list of devices */
++ /* protect the devicelist */
++ if (!SDIO_SUCCESS(status = SemaphorePendInterruptable(&pHcdContext->DeviceListSem))) {
++ break;; /* wait interrupted */
++ }
++ SDListInsertTail(&pHcdContext->DeviceList, &pDeviceContext->List);
++ SemaphorePost(&pHcdContext->DeviceListSem);
++
++ /* initialize work items */
++ INIT_WORK(&(pDeviceContext->OSInfo.iocomplete_work), hcd_iocomplete_wqueue_handler, pDeviceContext);
++ INIT_WORK(&(pDeviceContext->OSInfo.carddetect_work), hcd_carddetect_wqueue_handler, pDeviceContext);
++ INIT_WORK(&(pDeviceContext->OSInfo.sdioirq_work), hcd_sdioirq_wqueue_handler, pDeviceContext);
++
++ if (!SDIO_SUCCESS((status = InitOmap(pDeviceContext, ii - first_device)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Probe - failed to init OMAP HW, status =%d\n", status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++ /* InitOmap may back off these values because of DMA common buffer restrictions */
++ pDeviceContext->Hcd.MaxBytesPerBlock = max_bytes_per_block;
++ pDeviceContext->Hcd.MaxBlocksPerTrans = max_blocks;
++
++ if (!SDIO_SUCCESS((status = HcdInitialize(pDeviceContext)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Probe - failed to init HW, status =%d\n", status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pDeviceContext->OSInfo.InitStateMask |= SDHC_HW_INIT;
++
++ /* register with the SDIO bus driver */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pDeviceContext->Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: Probe - failed to register with host, status =%d\n",status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++ pDeviceContext->OSInfo.InitStateMask |= SDHC_REGISTERED;
++
++ if (builtin_card) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD Forcing ATTACH on built-in card \n"));
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_ATTACH);
++ }
++ }
++ if (err < 0) {
++ Remove(pBusDevice); /* TODO: the cleanup should not really be done in the Remove function */
++ } else {
++ /* TODO: check and see if there is a card inserted at powerup */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP Probe - HCD ready! \n"));
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HCD: Probe - err:%d\n", err));
++ return err;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static void Remove(struct pnp_dev *pBusDevice)
++#else
++static void Remove(POS_PNPDEVICE pBusDevice)
++#endif
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HCD: Remove - removing device\n"));
++ RemoveDevice(pBusDevice, pHcdContext);
++ pHcdContext->DeviceCount--;
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HCD: Remove\n"));
++}
++
++/*
++ * RemoveDevice - remove all devices associated with bus device
++*/
++static void RemoveDevice(POS_PNPDEVICE pBusDevice, PSDHCD_DRIVER_CONTEXT pHcdContext)
++{
++ PSDHCD_DEVICE pDeviceContext;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO OMAP HCD: RemoveDevice\n"));
++
++ /* protect the devicelist */
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pHcdContext->DeviceListSem))) {
++ return; /* wait interrupted */
++ }
++
++ SDITERATE_OVER_LIST_ALLOW_REMOVE(&pHcdContext->DeviceList, pDeviceContext, SDHCD_DEVICE, List)
++ if (pDeviceContext->OSInfo.pBusDevice == pBusDevice) {
++ if (pDeviceContext->OSInfo.InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pDeviceContext);
++ }
++
++ if (pDeviceContext->OSInfo.InitStateMask & SDHC_REGISTERED) {
++ SDIO_UnregisterHostController(&pDeviceContext->Hcd);
++ }
++
++ /* wait for any of our work items to run */
++ flush_scheduled_work();
++
++ DeinitOmap(pDeviceContext);
++
++ if (pDeviceContext->Hcd.pName != NULL) {
++ KernelFree(pDeviceContext->Hcd.pName);
++ pDeviceContext->Hcd.pName = NULL;
++ }
++ KernelFree(pDeviceContext);
++ }
++ SDITERATE_END;
++ SemaphorePost(&pHcdContext->DeviceListSem);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HCD: RemoveDevice\n"));
++}
++
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_DEVICE pDeviceContext, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ DBG_PRINT(OMAP_TRACE_WORK, ("+SDIO OMAP QueueEventResponse\n"));
++ if (pDeviceContext->OSInfo.ShuttingDown) {
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP QueueEventResponse - WORK_ITEM_IO_COMPLETE \n"));
++ work = &pDeviceContext->OSInfo.iocomplete_work;
++ break;
++ case WORK_ITEM_CARD_DETECT:
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP QueueEventResponse - WORK_ITEM_CARD_DETECT \n"));
++ work = &pDeviceContext->OSInfo.carddetect_work;
++ break;
++ case WORK_ITEM_SDIO_IRQ:
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP QueueEventResponse - WORK_ITEM_SDIO_IRQ \n"));
++ work = &pDeviceContext->OSInfo.sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ DBG_PRINT(OMAP_TRACE_WORK, ("-SDIO OMAP QueueEventResponse - Success \n"));
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO OMAP QueueEventResponse - Error scheduling work\n"));
++ return SDIO_STATUS_PENDING;
++ }
++}
++/*
++ * CompleteRequestSyncDMA - handle a synchronized request completion between the ISR and the DMA complete
++*/
++void CompleteRequestSyncDMA(PSDHCD_DEVICE pDeviceContext, PSDREQUEST pRequest, SDIO_STATUS Status)
++{
++ unsigned long flags;
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP HcdCompleteRequest - enter, status: %d, count: %d\n",
++ Status, pDeviceContext->CompletionCount));
++
++ /* disable the DMA and the EOC interrupts */
++ local_irq_save(flags);
++ pDeviceContext->CompletionCount++;
++ DBG_ASSERT_WITH_MSG(pDeviceContext->CompletionCount < 3, "SDIO OMAP: HcdCompleteRequest completion count bad!")
++ DBG_ASSERT_WITH_MSG(Status != SDIO_STATUS_PENDING, "SDIO OMAP: HcdCompleteRequest completion still pending status!")
++ DBG_ASSERT_WITH_MSG(pRequest != NULL, "SDIO OMAP: HcdCompleteRequest completion NULL pRequest!")
++ if (((pDeviceContext->CompletionCount == 2) && (IS_SDREQ_DATA_TRANS(pRequest->Flags))) ||
++ ((pDeviceContext->CompletionCount >= 1) && (!IS_SDREQ_DATA_TRANS(pRequest->Flags))) ||
++ !SDIO_SUCCESS(Status)) {
++ local_irq_restore(flags);
++
++ if (pRequest != NULL) {
++ /* set the status */
++ pRequest->Status = Status;
++ DBG_PRINT(OMAP_TRACE_WORK, ("SDIO OMAP HcdCompleteRequest - queueing work from IRQ , status: %d\n", Status));
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pDeviceContext, WORK_ITEM_IO_COMPLETE);
++ } else {
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP HcdCompleteRequest - no request to report: status %d \n",
++ Status));
++ }
++ } else {
++ local_irq_restore(flags);
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ DBG_PRINT(OMAP_TRACE_REQUESTS, ("SDIO OMAP hcd_iocomplete_wqueue_handler \n"));
++ if (!pDeviceContext->OSInfo.ShuttingDown) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++}
++
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++
++#if 0 /* TODO */
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ HCD_EVENT event;
++
++ event = EVENT_HCD_ATTACH;
++ pDeviceContext->OSInfo.CardInserted = TRUE;
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, event);
++#endif
++}
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_DEVICE pDeviceContext = (PSDHCD_DEVICE)context;
++ DBG_PRINT(OMAP_TRACE_SDIO_INT, ("SDIO OMAP: hcd_sdioirq_wqueue_handler \n"));
++ if (!pDeviceContext->OSInfo.ShuttingDown) {
++ SDIO_HandleHcdEvent(&pDeviceContext->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++ }
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskIrq - Unmask SD interrupts
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 UnmaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr)
++{
++ UINT16 ints;
++ UINT16 ints2;
++ /* protected read-modify-write */
++ if (!FromIsr) {
++ spin_lock_irq(&pDevice->OSInfo.AddressSpinlock);
++ }
++ ints = READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE);
++ ints2 = ints;
++ ints |= Mask;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE, ints);
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP: UnmaskIrq ints: 0x%x, Mask: 0x%X, ints2: 0x%x, rge: 0x%X\n",
++ ints, Mask, ints2, READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE)));
++ if (!FromIsr) {
++ spin_unlock_irq(&pDevice->OSInfo.AddressSpinlock);
++ }
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskIrq - Mask SD interrupts
++ Input: pDevice - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 MaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr)
++{
++ UINT16 ints;
++ UINT16 ints2;
++ /* protected read-modify-write */
++ if (!FromIsr) {
++ spin_lock_irq(&pDevice->OSInfo.AddressSpinlock);
++ }
++ ints = READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE);
++ ints2 = ints;
++ ints &= ~Mask;
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE, ints);
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP: MaskIrq ints: 0x%x, Mask: 0x%X, ints2: 0x%x, rge: 0x%X\n",
++ ints, Mask, ints2, READ_HOST_REG16(pDevice, OMAP_REG_MMC_INTERRUPT_ENABLE)));
++ if (!FromIsr) {
++ spin_unlock_irq(&pDevice->OSInfo.AddressSpinlock);
++ }
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetDefaults - get the user modifiable data items
++ Input: pDevice - host controller instance
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetDefaults(PSDHCD_DEVICE pDevice)
++{
++ //can't change this dynanmically: pDeviceContext->OSInfo.BaseClock = BaseClock;
++ pDevice->TimeOut = timeout;
++ pDevice->DataTimeOut = data_timeout;
++ pDevice->ClockSpinLimit = clock_spin_limit;
++}
++
++/*
++ * SetPowerLevel - OS dependent set power
++*/
++SDIO_STATUS SetPowerLevel(PSDHCD_DEVICE pDevice, BOOL On, SLOT_VOLTAGE_MASK Level)
++{
++ return SDIO_STATUS_SUCCESS;
++
++}
++
++/* platform-specific write protect switch test */
++BOOL WriteProtectSwitchOn(PSDHCD_DEVICE pDevice)
++{
++ /* TODO if write protect is implemented and is set, return TRUE */
++ return FALSE;
++}
++
++/* micro second delay */
++void MicroDelay(INT Microseconds)
++{
++ udelay(Microseconds);
++}
++
++
++/*
++ * module init
++*/
++static int __init sdio_local_hcd_init(void) {
++ SDIO_STATUS status;
++
++ REL_PRINT(SDDBG_TRACE, ("+SDIO OMAP HCD: loaded\n"));
++
++ SDLIST_INIT(&HcdContext.DeviceList);
++ status = SemaphoreInitialize(&HcdContext.DeviceListSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ return SDIOErrorToOSError(status);
++ }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ status = SDIO_BusAddOSDevice(&HcdContext.Driver.Dma, &HcdContext.Driver.HcdDriver, &HcdContext.Driver.HcdDevice);
++ return SDIOErrorToOSError(status);
++#else
++ SetupTranceiver();
++ /* 2.4 */
++ return Probe(NULL, NULL);
++#endif
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_local_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO OMAP HCD: unloaded\n"));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ SDIO_BusRemoveOSDevice(&HcdContext.Driver.HcdDriver, &HcdContext.Driver.HcdDevice);
++#else
++ /* 2.4 */
++ Remove(NULL);
++ CleanupTranceiver();
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO OMAP HCD: leave sdio_local_hcd_cleanup\n"));
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_local_hcd_init);
++module_exit(sdio_local_hcd_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_os_2_6.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_hcd_os_2_6.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,731 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os_2_6.c
++
++ at abstract: Linux OMAP native SDIO Host Controller Driver, 2.6 and higher
++
++#notes: includes initialization and DMA code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include <linux/sdio/ctsystem.h>
++#include "sdio_omap_hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#include <asm/mach-types.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/mux.h>
++#include <linux/dma-mapping.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/menelaus.h>
++#include <asm/arch/clock.h>
++
++extern INT gpiodebug;
++extern INT noDMA;
++extern SDHCD_DRIVER_CONTEXT HcdContext;
++extern int clk_safe(struct clk *clk);
++
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r);
++static void setupOmapDma(PSDHCD_DEVICE pDevice,
++ int Length,
++ DMA_ADDRESS DmaAddress,
++ BOOL RX);
++static void SD_DMACompleteCallback(int Channel, u16 DMAStatus, PVOID pContext);
++
++void ToggleGPIOPin(PSDHCD_DEVICE pDevice, INT PinNo)
++{
++ if (!gpiodebug) {
++ return;
++ }
++
++ switch (PinNo) {
++ case DBG_GPIO_PIN_1:
++ omap_set_gpio_dataout(16,TRUE);
++ omap_set_gpio_dataout(16,FALSE);
++ break;
++ case DBG_GPIO_PIN_2:
++ break;
++ default:
++ break;
++ }
++}
++
++
++#define OMAP_CONTROL_PADCONF_BASE_ADDRESS 0x48000000
++#define OMAP_CONTROL_PADCONF_SIZE 0x0400
++#define OMAP_PAD_PULLUPDWN_ENABLE (1 << 3)
++#define OMAP_PAD_PULLUP_TYPE (1 << 4)
++#define OMAP_PAD_PULLDOWN_TYPE (0 << 4)
++
++void OmapPadConfig(UINT32 Offset, UINT8 BitPos, UINT8 PadValue)
++{
++ UINT32 value;
++ UINT32 padConfig = (UINT32)ioremap(OMAP_CONTROL_PADCONF_BASE_ADDRESS,
++ OMAP_CONTROL_PADCONF_SIZE);
++
++ value = readl(padConfig+Offset);
++ value &= ~((UINT32)0xff << BitPos);
++ value |= (UINT32)PadValue << BitPos;
++ writel(value,padConfig+Offset);
++}
++
++
++/*
++ * MapAddress - maps I/O address
++*/
++static SYSTEM_STATUS MapAddress(PSDHCD_MEMORY pMap, PTEXT pDescription) {
++
++ if (request_mem_region(pMap->Raw, pMap->Length, pDescription) == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Local HCD: MapAddress - memory in use\n"));
++ return -EBUSY;
++ }
++ pMap->pMapped = ioremap_nocache(pMap->Raw, pMap->Length);
++ if (pMap->pMapped == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP Local HCD: MapAddress - unable to map memory\n"));
++ /* cleanup region */
++ release_mem_region(pMap->Raw, pMap->Length);
++ return -EFAULT;
++ }
++ return 0;
++}
++
++/*
++ * UnmapAddress - unmaps the address
++*/
++static void UnmapAddress(PSDHCD_MEMORY pMap) {
++ iounmap(pMap->pMapped);
++ release_mem_region(pMap->Raw, pMap->Length);
++ pMap->pMapped = NULL;
++}
++
++SDIO_STATUS SlotEnableControl(BOOL Enable)
++{
++ int value;
++ SDIO_STATUS status = SDIO_STATUS_ERROR;
++
++ do {
++ value = menelaus_read(MENELAUS_LDO_CTRL7);
++ if (value == -1) {
++ DBG_ASSERT(FALSE);
++ break;
++ }
++ if (Enable) {
++ value |= 0x03;
++ } else {
++ value &= ~0x03;
++ }
++ value = menelaus_write(value, MENELAUS_LDO_CTRL7);
++ if (value == -1) {
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ value = menelaus_read(MENELAUS_MCT_CTRL3);
++ if (value == -1) {
++ DBG_ASSERT(FALSE);
++ break;
++ }
++ if (Enable) {
++ value |= 0x01;
++ } else {
++ value &= ~0x01;
++ }
++ value = menelaus_write(value, MENELAUS_MCT_CTRL3);
++ if (value == -1) {
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++
++ status = SDIO_STATUS_SUCCESS;
++ } while (FALSE);
++
++ return status;
++}
++/*
++ * unsetup the OMAP registers
++*/
++void DeinitOmap(PSDHCD_DEVICE pDevice)
++{
++
++ if (pDevice->OSInfo.InitStateMask & SDIO_IRQ_INTERRUPT_INIT) {
++ disable_irq(pDevice->OSInfo.Interrupt);
++ free_irq(pDevice->OSInfo.Interrupt, pDevice);
++ pDevice->OSInfo.InitStateMask &= ~SDIO_IRQ_INTERRUPT_INIT;
++ }
++
++ /* deallocate DMA buffer */
++ if (pDevice->OSInfo.pDmaBuffer != NULL) {
++ dma_free_coherent(&pDevice->OSInfo.pBusDevice->dev,
++ pDevice->OSInfo.CommonBufferSize,
++ pDevice->OSInfo.pDmaBuffer,
++ pDevice->OSInfo.hDmaBuffer);
++ pDevice->OSInfo.pDmaBuffer = NULL;
++ }
++
++ if (pDevice->OSInfo.DmaRxChannel != -1) {
++ omap_free_dma(pDevice->OSInfo.DmaRxChannel);
++ pDevice->OSInfo.DmaRxChannel = -1;
++ }
++
++ if (pDevice->OSInfo.DmaTxChannel != -1) {
++ omap_free_dma(pDevice->OSInfo.DmaTxChannel);
++ pDevice->OSInfo.DmaTxChannel = -1;
++ }
++
++ if (pDevice->OSInfo.InitStateMask & SDIO_BASE_MAPPED) {
++ pDevice->OSInfo.InitStateMask &= ~SDIO_BASE_MAPPED;
++ UnmapAddress(&pDevice->OSInfo.Address);
++ }
++
++ SlotEnableControl(FALSE);
++}
++
++void FifoTxTest(PSDHCD_DEVICE pDevice)
++{
++ INT dataCopy = 1000;
++ volatile UINT16 *pFifo;
++
++ pFifo = (volatile UINT16 *)((UINT32)GET_HC_REG_BASE(pDevice) + OMAP_REG_MMC_DATA_ACCESS);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: FifoTest (0x%X) \n", (UINT)pFifo));
++
++
++ while (dataCopy) {
++ *pFifo = (UINT16)dataCopy;
++ dataCopy--;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: FifoTest Done\n"));
++}
++
++/*
++ * setup the OMAP registers
++*/
++SDIO_STATUS InitOmap(PSDHCD_DEVICE pDevice, UINT deviceNumber)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ ULONG baseAddress;
++ int err;
++ struct clk *clksrc;
++
++ do {
++
++ pDevice->OSInfo.Interrupt = INT_MMC_IRQ;
++ baseAddress = OMAP_BASE_ADDRESS1;
++ pDevice->OSInfo.DmaRxId = OMAP_DMA_MMC1_RX;
++ pDevice->OSInfo.DmaTxId = OMAP_DMA_MMC1_TX;
++ pDevice->OSInfo.DmaRxChannel = -1;
++ pDevice->OSInfo.DmaTxChannel = -1;
++
++ SlotEnableControl(TRUE);
++
++ clksrc = clk_get(NULL,"mmc_ick");
++ if (NULL == clksrc) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ clk_use(clksrc);
++
++ clksrc = clk_get(NULL,"mmc_fck");
++ if (NULL == clksrc) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ clk_use(clksrc);
++ clk_safe(clksrc);
++
++
++ if (!noDMA) {
++ UINT32 gcrVal;
++
++ gcrVal = readl(OMAP_DMA4_GCR_REG);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: DMA4_GCR : 0x%X \n",gcrVal));
++ gcrVal &= ~0xff;
++ gcrVal |= 64;
++ writel(gcrVal, OMAP_DMA4_GCR_REG);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: DMA4_GCR reread: 0x%X \n",readl(OMAP_DMA4_GCR_REG)));
++ /* allocate a DMA buffer larger enough for the command buffers and the data buffers */
++ pDevice->OSInfo.pDmaBuffer = dma_alloc_coherent(&pDevice->OSInfo.pBusDevice->dev,
++ pDevice->OSInfo.CommonBufferSize,
++ &pDevice->OSInfo.hDmaBuffer,
++ GFP_DMA);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO OMAP HCD: InitOmap - pDmaBuffer: 0x%X, hDmaBuffer: 0x%X Size:%d\n",
++ (UINT)pDevice->OSInfo.pDmaBuffer ,
++ (UINT)pDevice->OSInfo.hDmaBuffer,
++ pDevice->OSInfo.CommonBufferSize));
++
++ if (pDevice->OSInfo.pDmaBuffer == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: InitOmap - unable to get DMA buffer\n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pDevice->DmaCapable = TRUE;
++ /* tell upper drivers that we support direct DMA */
++ pDevice->Hcd.pDmaDescription = &HcdContext.Driver.Dma;
++
++ }
++
++ if (gpiodebug) {
++ /* setup GPIO 16 */
++#define CONTROL_PADCONF_Y11 0x00E8
++ OmapPadConfig(CONTROL_PADCONF_Y11,
++ 0,
++ 0x3 | OMAP_PAD_PULLUPDWN_ENABLE | OMAP_PAD_PULLUP_TYPE);
++ omap_set_gpio_direction(16, OMAP24XX_DIR_OUTPUT);
++ omap_set_gpio_dataout(16,FALSE);
++ }
++
++ err = omap_request_dma(pDevice->OSInfo.DmaRxId,
++ "SDIO TX",
++ SD_DMACompleteCallback,
++ pDevice,
++ &pDevice->OSInfo.DmaRxChannel);
++
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: OmapInit, unable to get RX DMA channel, %d\n",err));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ err = omap_request_dma(pDevice->OSInfo.DmaTxId,
++ "SDIO TX",
++ SD_DMACompleteCallback,
++ pDevice,
++ &pDevice->OSInfo.DmaTxChannel);
++
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: OmapInit, unable to get TX DMA channel, %d\n",err));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ /* map the memory address for the control registers */
++ pDevice->OSInfo.Address.pMapped = (PVOID)IO_ADDRESS(baseAddress);
++ pDevice->OSInfo.Address.Raw = baseAddress;
++ pDevice->OSInfo.Address.Length = OMAP_BASE_LENGTH;
++ if (MapAddress(&pDevice->OSInfo.Address, "SDHC Regs") < 0) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO OMAP - InitOMAP I/O Virt:0x%X Phys:0x%X\n",
++ (UINT)pDevice->OSInfo.Address.pMapped, (UINT)pDevice->OSInfo.Address.Raw));
++
++ //FifoTxTest(pDevice);
++
++ pDevice->OSInfo.InitStateMask |= SDIO_BASE_MAPPED;
++
++
++ /* map the controller interrupt, we map it to each device.
++ Interrupts can be called from this point on */
++ err = request_irq(pDevice->OSInfo.Interrupt, hcd_sdio_irq, 0,
++ "OMAP HCD", pDevice);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO OMAP HCD: OmapInit, unable to map interrupt \n"));
++ err = -ENODEV;
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pDevice->OSInfo.InitStateMask |= SDIO_IRQ_INTERRUPT_INIT;
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ DeinitOmap(pDevice);
++ }
++
++ return status;
++}
++
++void SetupTXCommonBufferDMATransfer(PSDHCD_DEVICE pDevice, PSDREQUEST pReq)
++{
++ UINT32 length;
++ /* adjust length */
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ /* copy to common buffer */
++ memcpy(pDevice->OSInfo.pDmaBuffer, pReq->pHcdContext, length);
++ /* adjust where we are */
++ pReq->pHcdContext = (PUCHAR)pReq->pHcdContext + length;
++ pReq->DataRemaining -= length;
++ /* setup this chunk */
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,FALSE);
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP TX Common Buffer DMA, This Transfer: %d, Remaining:%d\n",
++ length,pReq->DataRemaining));
++}
++/*
++ * DMA transmit complete callback
++*/
++static void SD_DMACompleteCallback(int Channel, u16 DMAStatus, PVOID pContext)
++{
++ PSDHCD_DEVICE pDevice = (PSDHCD_DEVICE)pContext;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(&pDevice->Hcd);
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP SD_DMACompleteCallback (%s)- DMAStatus: 0x%X, lch: %d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",(UINT)status, Channel));
++ do {
++
++ if (DMAStatus == OMAP_DMA_SYNC_IRQ) {
++ /* only a synch int, ignore it */
++ break;
++ }
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ DBG_ASSERT(pDevice->OSInfo.pDmaList != NULL);
++ DBG_ASSERT(pDevice->OSInfo.SGcount != 0);
++ /* unmap scatter gather */
++ dma_unmap_sg(pDevice->Hcd.pDevice,
++ pDevice->OSInfo.pDmaList,
++ pDevice->OSInfo.SGcount,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ pDevice->OSInfo.pDmaList = NULL;
++ pDevice->OSInfo.SGcount = 0;
++ }
++
++ /* handle errors */
++ if (DMAStatus & (OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ)) {
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ /* no DMA errors */
++ status = SDIO_STATUS_SUCCESS;
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ /* nothing more to do */
++ break;
++ }
++
++ /* handle common buffer DMA */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ if (pReq->DataRemaining) {
++ /* send the next chunk */
++ SetupTXCommonBufferDMATransfer(pDevice,pReq);
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++ } else {
++ UINT32 length;
++
++ memcpy(pReq->pHcdContext, pDevice->OSInfo.pDmaBuffer, pDevice->OSInfo.LastTransfer);
++ /* adjust where we are */
++ pReq->pHcdContext = (PUCHAR)pReq->pHcdContext + pDevice->OSInfo.LastTransfer;
++ pReq->DataRemaining -= pDevice->OSInfo.LastTransfer;
++ /* set up next transfer */
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ if (length) {
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP RX Common Buffer DMA, Pending Transfer: %d, Remaining:%d\n",
++ length, pReq->DataRemaining));
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,TRUE);
++ pDevice->OSInfo.LastTransfer = length;
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++ }
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* call callback */
++ pDevice->OSInfo.pTransferCompletion(pDevice->OSInfo.TransferContext, status, TRUE);
++ }
++
++}
++
++
++void DumpDMASettings(PSDHCD_DEVICE pDevice, BOOL TX)
++{
++ int channel = TX ? pDevice->OSInfo.DmaTxChannel : pDevice->OSInfo.DmaRxChannel;
++
++ DBG_PRINT(SDDBG_TRACE, ("OMAP DMA Reg Dump (%s) Channel:0x%X, DMAREQ:%d \n",
++ TX ? "Transmit":"Receive", channel,
++ TX ? pDevice->OSInfo.DmaTxId:pDevice->OSInfo.DmaRxId));
++ DBG_PRINT(SDDBG_TRACE, (" CCR : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CCR_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CLNK_CTRL : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CLNK_CTRL_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CICR : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CICR_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSR : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CSR_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSDP : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CSDP_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CEN : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CEN_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CFN : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CFN_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSSA : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CSSA_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CDSA : 0x%X \n",_READ_DWORD_REG(OMAP_DMA4_CDSA_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSEI : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CSEI_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSFI : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CSFI_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CDEI : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CDEI_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CDFI : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CDFI_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CSAC : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CSAC_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CDAC : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CDAC_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CCEN : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CCEN_REG(channel))));
++ DBG_PRINT(SDDBG_TRACE, (" CCFN : 0x%X \n", _READ_DWORD_REG(OMAP_DMA4_CCFN_REG(channel))));
++
++}
++
++#define FIFO_SYNC_BLOCK_SIZE (OMAP_MMC_FIFO_SIZE/2) /* sync set to 1/2 full/empty*/
++
++/* setup DMA for transfer */
++static void setupOmapDma(PSDHCD_DEVICE pDevice,
++ int Length,
++ DMA_ADDRESS SystemAddress,
++ BOOL RX)
++{
++ INT fifoLen;
++ INT cen,cfn;
++ int channel = RX ? pDevice->OSInfo.DmaRxChannel : pDevice->OSInfo.DmaTxChannel;
++ BOOL burstEnable = FALSE;
++ UINT32 csdp;
++
++ UINT32 address = pDevice->OSInfo.Address.Raw + OMAP_REG_MMC_DATA_ACCESS;
++
++ if (Length == (FIFO_SYNC_BLOCK_SIZE * (Length/FIFO_SYNC_BLOCK_SIZE))) {
++ /* multiple of fifo synch size */
++ cen = FIFO_SYNC_BLOCK_SIZE>>1;
++ cfn = (Length/FIFO_SYNC_BLOCK_SIZE);
++ fifoLen = 0xF; /* threshold set to 32 bytes which is half way on the FIFOs */
++ /* enable bursting since we are nicely divisible by a FIFO size */
++ burstEnable = TRUE;
++ } else {
++ if (Length < FIFO_SYNC_BLOCK_SIZE) {
++ cen = Length>>1;
++ cfn = 1;
++ fifoLen = (Length>>1)-1;
++ fifoLen = (fifoLen < 0) ? 0 : fifoLen;
++ } else {
++ if (Length == (8 * (Length/8))) {
++ cen = 1;
++ cfn = (Length+1)>>1;
++ fifoLen = 0;
++ } else {
++ cen = 1;
++ cfn = (Length+1)>>1;
++ fifoLen = 0;
++ }
++ }
++ }
++
++ omap_set_dma_transfer_params(channel,
++ OMAP_DMA_DATA_TYPE_S16,
++ cen,
++ cfn,
++ OMAP_DMA_SYNC_BLOCK,
++ RX ? pDevice->OSInfo.DmaRxId : pDevice->OSInfo.DmaTxId,
++ RX ? TRUE : FALSE);
++
++
++ if (RX) {
++ omap_set_dma_src_params(channel,
++ OMAP_DMA_AMODE_CONSTANT,
++ (int)address,
++ 0,
++ 0);
++
++ omap_set_dma_dest_params(channel,
++ OMAP_DMA_AMODE_POST_INC,
++ SystemAddress,
++ 0,
++ 0);
++ } else {
++
++ /* source is system memory */
++ omap_set_dma_src_params(channel,
++ OMAP_DMA_AMODE_POST_INC,
++ (int)SystemAddress,
++ 0,
++ 0);
++
++ omap_set_dma_dest_params(channel,
++ OMAP_DMA_AMODE_CONSTANT,
++ (int)address,
++ 0,
++ 0);
++ }
++
++ DBG_PRINT(OMAP_TRACE_DATA, ("OMAP DMA channel sync ID: %d \n",
++ (RX) ? pDevice->OSInfo.DmaRxId : pDevice->OSInfo.DmaTxId));
++
++
++ if (DBG_GET_DEBUG_LEVEL() >= OMAP_TRACE_DMA_DUMP) {
++ DumpDMASettings(pDevice, RX ? FALSE:TRUE);
++ }
++
++ csdp = readl(OMAP_DMA4_CSDP_REG(channel));
++ /* clear previous burst settings */
++ csdp &= ~((0x3 << 7) | (0x3 << 14) | (1 << 13) | (1 << 6));
++
++ if (burstEnable) {
++ csdp |= (0x2 << 7) | (0x2 << 14) | (1 << 13) | (1 << 6); /* 32 byte burst enable */
++ }
++
++ writel(csdp, OMAP_DMA4_CSDP_REG(channel));
++
++ if (RX) {
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, OMAP_REG_MMC_BUFFER_CONFIG_RXDE |
++ ((fifoLen << OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT) & OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK));
++ } else {
++ WRITE_HOST_REG16(pDevice, OMAP_REG_MMC_BUFFER_CONFIG, OMAP_REG_MMC_BUFFER_CONFIG_TXDE |
++ ((fifoLen << OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT) & OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK));
++ }
++ /* start */
++ omap_start_dma(channel);
++}
++
++SDIO_STATUS CheckDMA(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ do {
++
++ if ((OMAP_DMA_COMMON == pDevice->DmaMode) &&
++ (pReq->DataRemaining & 0x1)) {
++ /* DMA requires WORD alignment, tell caller to punt it to PIO mode */
++ status = SDIO_STATUS_UNSUPPORTED;
++ break;
++ }
++
++ if (OMAP_DMA_SG == pDevice->DmaMode) {
++ /* doing direct DMA */
++ if (pReq->DescriptorCount > 1) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++ }
++ } while (FALSE);
++
++ return status;
++}
++
++SDIO_STATUS SetUpHCDDMA(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ UINT32 length = pReq->DataRemaining;
++ PSDDMA_DESCRIPTOR pDesc = NULL;
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("+SDIO OMAP SetUpHCDDMA: length: %d\n",length));
++
++ do {
++
++ pDevice->OSInfo.pTransferCompletion = pCompletion;
++ pDevice->OSInfo.TransferContext = pContext;
++
++ if (OMAP_DMA_COMMON == pDevice->DmaMode) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ SetupTXCommonBufferDMATransfer(pDevice,pReq);
++ } else {
++ length = min(pDevice->OSInfo.CommonBufferSize,
++ pReq->DataRemaining);
++ setupOmapDma(pDevice, length, pDevice->OSInfo.hDmaBuffer,TRUE);
++ pDevice->OSInfo.LastTransfer = length;
++ }
++ break;
++ }
++
++ /* setup scatter gather */
++ DBG_ASSERT(pDesc != NULL);
++ /* map DMA */
++ dma_map_sg(pDevice->Hcd.pDevice,
++ pDesc,
++ pReq->DescriptorCount,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++
++ pDevice->OSInfo.pDmaList = pDesc;
++ pDevice->OSInfo.SGcount = pReq->DescriptorCount;
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("SDIO OMAP SetUpHCDDMA, Direct DMA dma_address:0x%X\n", (UINT32)sg_dma_address(pDesc)));
++
++ setupOmapDma(pDevice,
++ length,
++ sg_dma_address(pDesc),
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? FALSE : TRUE);
++
++ } while (FALSE);
++
++ DBG_PRINT(OMAP_TRACE_DATA,
++ ("-SDIO OMAP SetUpHCDDMA: status %d\n",status));
++
++ return status;
++}
++
++/*
++ * SDCancelTransfer - stop DMA transfer
++*/
++void SDCancelDMATransfer(PSDHCD_DEVICE pDevice)
++{
++ DBG_PRINT(OMAP_TRACE_DATA, ("SDIO OMAP SDCancelDMATransfer\n"));
++ if (pDevice->OSInfo.DmaRxChannel != -1) {
++ omap_stop_dma(pDevice->OSInfo.DmaRxChannel);
++ }
++ if (pDevice->OSInfo.DmaTxChannel != -1) {
++ omap_stop_dma(pDevice->OSInfo.DmaTxChannel);
++ }
++}
++
++/* SDIO interrupt request */
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r)
++{
++ irqreturn_t retStat;
++
++ DBG_PRINT(OMAP_TRACE_MMC_INT, ("SDIO OMAP SDIO IRQ \n"));
++
++ /* call OS independent ISR */
++ if (HcdSDInterrupt((PSDHCD_DEVICE)context)) {
++ retStat = IRQ_HANDLED;
++ } else {
++ retStat = IRQ_NONE;
++ }
++ return retStat;
++}
+Index: linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_omap_hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/omap_2420/sdio_omap_hcd.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,370 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_pmap_hcd.h
++
++ at abstract: include file for OMAP native MMC/SD host controller, OS independent code
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_OMAP_HCD_H___
++#define __SDIO_OMAP_HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++
++enum OMAP_TRACE_ENUM {
++ OMAP_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ OMAP_TRACE_SDIO_INT = (SDDBG_TRACE + 2),
++ OMAP_TRACE_WORK,
++ OMAP_TRACE_REQUESTS,
++ OMAP_TRACE_DATA,
++ OMAP_TRACE_DMA_DUMP,
++ OMAP_TRACE_CONFIG,
++ OMAP_TRACE_MMC_INT,
++ OMAP_TRACE_CLOCK,
++ OMAP_TRACE_LAST
++};
++
++#define OMAP_TRACE_BUSY OMAP_TRACE_DATA
++
++#define OMAP_MAX_BYTES_PER_BLOCK 2048
++#define OMAP_MAX_BLOCKS 2048
++#define OMAP_DEFAULT_CURRENT 500
++#define OMAP_DEFAULT_CMD_TIMEOUT 64
++#define OMAP_DEFAULT_DATA_TIMEOUT 400000
++
++#define OMAP_MMC_FIFO_SIZE 64
++/* almost full, for RX */
++#define OMAP_MMC_AFL_FIFO_THRESH 32 //62
++ /* almost empty, for TX */
++#define OMAP_MMC_AEL_FIFO_THRESH 32 // 2
++#define OMAP_MAX_SHORT_TRANSFER_SIZE 16
++
++#define OMAP_REG_MMC_CMD 0x00
++ #define OMAP_REG_MMC_CMD_DDIR_READ (1<<15)
++ #define OMAP_REG_MMC_CMD_DDIR_WRITE (0)
++ #define OMAP_REG_MMC_CMD_STREAM_MODE_NORMAL (0)
++ #define OMAP_REG_MMC_CMD_TYPE_BC (0)
++ #define OMAP_REG_MMC_CMD_TYPE_BCR (1<<12)
++ #define OMAP_REG_MMC_CMD_TYPE_AC (2<<12)
++ #define OMAP_REG_MMC_CMD_TYPE_ADTC (3<<12)
++ #define OMAP_REG_MMC_CMD_R1BUSY (1<<11)
++ #define OMAP_REG_MMC_CMD_NORESPONSE (0)
++ #define OMAP_REG_MMC_CMD_R1 (1<<8)
++ #define OMAP_REG_MMC_CMD_R2 (2<<8)
++ #define OMAP_REG_MMC_CMD_R3 (3<<8)
++ #define OMAP_REG_MMC_CMD_R4 (4<<8)
++ #define OMAP_REG_MMC_CMD_R5 (5<<8)
++ #define OMAP_REG_MMC_CMD_R6 (6<<8)
++ #define OMAP_REG_MMC_CMD_INAB (1<<7)
++ #define OMAP_REG_MMC_CMD_CTO_DTO (1<<6)
++ #define OMAP_REG_MMC_CMD_MASK (0x3F)
++
++
++#define OMAP_REG_MMC_ARG_LOW 0x04
++#define OMAP_REG_MMC_ARG_HI 0x08
++
++#define OMAP_REG_MMC_MODULE_CONFIG 0x0C
++ #define OMAP_REG_MMC_MODULE_CONFIG_4BIT (1<<15)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_MMCSD (0<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_SPI (1<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_MODE_TEST (2<<12)
++ #define OMAP_REG_MMC_MODULE_CONFIG_PWRON (1<<11)
++ #define OMAP_REG_MMC_MODULE_CONFIGE_BE (1<<10)
++ #define OMAP_REG_MMC_MODULE_CONFIG_CLK_MASK (0x3FF)
++
++#define OMAP_REG_MMC_MODULE_STATUS 0x10
++ #define OMAP_REG_MMC_MODULE_STATUS_CERR (1<<14)
++ #define OMAP_REG_MMC_MODULE_STATUS_CIRQ (1<<13)
++ #define OMAP_REG_MMC_MODULE_STATUS_OCRB (1<<12)
++ #define OMAP_REG_MMC_MODULE_STATUS_AE (1<<11)
++ #define OMAP_REG_MMC_MODULE_STATUS_AF (1<<10)
++ #define OMAP_REG_MMC_MODULE_STATUS_CRW (1<<9)
++ #define OMAP_REG_MMC_MODULE_STATUS_CCRC (1<<8)
++ #define OMAP_REG_MMC_MODULE_STATUS_CTO (1<<7)
++ #define OMAP_REG_MMC_MODULE_STATUS_DCRC (1<<6)
++ #define OMAP_REG_MMC_MODULE_STATUS_DTO (1<<5)
++ #define OMAP_REG_MMC_MODULE_STATUS_EOFB (1<<4)
++ #define OMAP_REG_MMC_MODULE_STATUS_BRS (1<<3)
++ #define OMAP_REG_MMC_MODULE_STATUS_CB (1<<2)
++ #define OMAP_REG_MMC_MODULE_STATUS_CD (1<<1)
++ #define OMAP_REG_MMC_MODULE_STATUS_EOC (1<<0)
++ #define OMAP_REG_MMC_MODULE_STATUS_ALL (0x7FFF)
++ #define OMAP_REG_MMC_MODULE_STATUS_REQ_PROCESS \
++ ((~(OMAP_REG_MMC_MODULE_STATUS_CIRQ | OMAP_REG_MMC_MODULE_STATUS_CD\
++ )) & OMAP_REG_MMC_MODULE_STATUS_ALL)
++ #define OMAP_STATUS_CMD_PROCESSING_ERRORS \
++ (OMAP_REG_MMC_MODULE_STATUS_CERR | OMAP_REG_MMC_MODULE_STATUS_CTO | \
++ OMAP_REG_MMC_MODULE_STATUS_CCRC)
++ #define OMAP_STATUS_DATA_PROCESSING_ERRORS \
++ (OMAP_REG_MMC_MODULE_STATUS_DCRC | OMAP_REG_MMC_MODULE_STATUS_DTO)
++
++#define OMAP_REG_MMC_INTERRUPT_ENABLE 0x14
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CERR (1<<14)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CIRQ (1<<13)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_OCRB (1<<12)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_AE (1<<11)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_AF (1<<10)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CRW (1<<9)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CCRC (1<<8)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CTO (1<<7)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_DCRC (1<<6)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_DTO (1<<5)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB (1<<4)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_BRS (1<<3)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CB (1<<2)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_CD (1<<1)
++ #define OMAP_REG_MMC_INTERRUPT_ENABLE_EOC (1<<0)
++ #define OMAP_REG_MMC_INTERRUPT_ALL_INT (0x7FFF)
++ #define OMAP_REG_MMC_INTERRUPT_NONE_INT (0)
++ #define OMAP_REG_MMC_INTERRUPT_ERRORS (OMAP_REG_MMC_INTERRUPT_ENABLE_CCRC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_CTO | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_DCRC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_DTO | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_CERR)
++ #define OMAP_REG_MMC_INTERRUPT_REQUESTS (OMAP_REG_MMC_INTERRUPT_ERRORS | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_EOC | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_AF | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_AE | \
++ OMAP_REG_MMC_INTERRUPT_ENABLE_EOFB )
++
++#define OMAP_REG_MMC_CMD_TIMEOUT 0x18
++ /* low 8-bit valid */
++
++#define OMAP_REG_MMC_DATA_READ_TIMEOUT 0x1C
++ /* 16-bit */
++
++#define OMAP_REG_MMC_DATA_ACCESS 0x20
++ /* 16-bit */
++
++#define OMAP_REG_MMC_BLOCK_LENGTH 0x24
++ /* low 11-bit */
++
++#define OMAP_REG_MMC_BLOCK_COUNT 0x28
++ /* low 11-bit */
++
++#define OMAP_REG_MMC_BUFFER_CONFIG 0x2C
++ #define OMAP_REG_MMC_BUFFER_CONFIG_RXDE (1<<15)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AFL_MASK (0x1F00)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AFL_SHIFT (8)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_TXDE (1<<7)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AEL_MASK (0x1F)
++ #define OMAP_REG_MMC_BUFFER_CONFIG_AEL_SHIFT (0)
++
++#define OMAP_REG_MMC_SPI_CONFIG 0x30
++ #define OMAP_REG_MMC_SPI_CONFIG_STR (1<<15)
++ #define OMAP_REG_MMC_SPI_CONFIG_WNR (1<<14)
++ #define OMAP_REG_MMC_SPI_CONFIG_SODV (1<<13)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSTR (1<<12)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD05 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD15 (1<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD25 (2<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSHOLD35 (3<<10)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS1 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS2 (1<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS3 (2<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_TCSS4 (3<<8)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSEL (1<<7)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS1 (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS2 (1<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS3 (2<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CS4 (3<<4)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSM (1<<3)
++ #define OMAP_REG_MMC_SPI_CONFIG_CSD (1<<2)
++ #define OMAP_REG_MMC_SPI_CONFIG_POL_RISE (0)
++ #define OMAP_REG_MMC_SPI_CONFIG_POL_FALL (1)
++
++#define OMAP_REG_MMC_SDIO_MODE_CONFIG 0x34
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C5E (1<<15)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C14E (1<<14)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C13E (1<<13)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_C12E (1<<12)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_D3PS (1<<11)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_D3ES (1<<10)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_CDWE (1<<9)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_IWE (1<<8)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_DCR4 (1<<7)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_XDTS (1<<6)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_DPE (1<<5)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_RW (1<<4)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_CDE (1<<2)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_RWE (1<<1)
++ #define OMAP_REG_MMC_SDIO_MODE_CONFIG_IRQE (1<<0)
++
++#define OMAP_REG_MMC_SYSTEM_TEST 0x38
++ #define OMAP_REG_MMC_SYSTEM_TEST_WAKD (1<<15)
++ #define OMAP_REG_MMC_SYSTEM_TEST_SSB (1<<14)
++ #define OMAP_REG_MMC_SYSTEM_TEST_RDYD (1<<13)
++ #define OMAP_REG_MMC_SYSTEM_TEST_DDIR (1<<12)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D3D (1<<11)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D2D (1<<10)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D1D (1<<9)
++ #define OMAP_REG_MMC_SYSTEM_TEST_D0D (1<<8)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CDIR (1<<7)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CDAT (1<<6)
++ #define OMAP_REG_MMC_SYSTEM_TEST_MCKD (1<<5)
++ #define OMAP_REG_MMC_SYSTEM_TEST_SCKD (1<<4)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS3D (1<<3)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS2D (1<<2)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS1D (1<<1)
++ #define OMAP_REG_MMC_SYSTEM_TEST_CS0D (1<<0)
++
++
++#define OMAP_REG_MMC_MODULE_REV 0x3C
++ #define OMAP_REG_MMC_MODULE_REV_MINOR_MASK (0xF)
++ #define OMAP_REG_MMC_MODULE_REV_MINOR_SHIFT (0)
++ #define OMAP_REG_MMC_MODULE_REV_MAJOR_MASK (0xF0)
++ #define OMAP_REG_MMC_MODULE_REV_MAJOR_SHIFT (4)
++
++#define OMAP_REG_MMC_CMD_RESPONSE0 0x40
++ /* response bits 15-0 */
++#define OMAP_REG_MMC_CMD_RESPONSE1 0x44
++ /* response bits 31-16 */
++#define OMAP_REG_MMC_CMD_RESPONSE2 0x48
++ /* response bits 47-32 */
++#define OMAP_REG_MMC_CMD_RESPONSE3 0x4C
++ /* response bits 63-48 */
++#define OMAP_REG_MMC_CMD_RESPONSE4 0x50
++ /* response bits 79-64 */
++#define OMAP_REG_MMC_CMD_RESPONSE5 0x54
++ /* response bits 95-80 */
++#define OMAP_REG_MMC_CMD_RESPONSE6 0x58
++ /* response bits 111-96 */
++#define OMAP_REG_MMC_CMD_RESPONSE7 0x5C
++ /* response bits 127-112 */
++
++#define OMAP_REG_MMC_SUSPEND_RESUME 0x60
++ #define OMAP_REG_MMC_SUSPEND_RESUME_STOP (1<<3)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_SAVE (1<<2)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_RESUME (1<<1)
++ #define OMAP_REG_MMC_SUSPEND_RESUME_SUSPEND (1<<0)
++
++#define OMAP_REG_MMC_SYSTEM_CONTROL 0x64
++ #define OMAP_REG_MMC_SYSTEM_CONTROL_SW_RESET (1<<1)
++
++#define OMAP_REG_MMC_SYSTEM_STATUS 0x68
++ #define OMAP_REG_MMC_SYSTEM_STATUS_RESET_DONE (1<<0)
++
++
++
++#define SD_DEFAULT_RESPONSE_BYTES 6
++
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++#define OMAP_MAX_CLOCK_DIVIDE 1023
++
++typedef struct _SD_CLOCK_TBL_ENTRY {
++ INT ClockRateDivisor; /* divisor */
++ UINT16 RegisterValue; /* register value for clock divisor */
++}SD_CLOCK_TBL_ENTRY;
++
++typedef enum _OMAP_DMA_MODE {
++ OMAP_DMA_NONE = 0,
++ OMAP_DMA_COMMON,
++ OMAP_DMA_SG
++}OMAP_DMA_MODE,*POMAP_DMA_MODE;
++
++typedef struct _SDHCD_DEVICE {
++ SDLIST List; /* linked list */
++ SDHCD Hcd; /* HCD description for bus driver */
++ OMAP_DMA_MODE DmaMode; /* current DMA mode */
++ BOOL DmaCapable; /* os layer supports DMA */
++ UINT16 Clock; /* current clock bit settings */
++ UINT32 BaseClock; /* base clock in hz */
++ UINT32 TimeOut; /* command timeout setting */
++ UINT32 DataTimeOut; /* data timeout setting */
++ UINT32 ClockSpinLimit; /* clock limit for command spin loops */
++ BOOL KeepClockOn;
++ BOOL IrqDetectArmed; /* IRQ detect was armed */
++ UINT8 CompletionCount; /* used to track when both DMA and command complete are done */
++ BOOL Cancel;
++ BOOL ShuttingDown;
++ BOOL ShortTransfer; /* do short transfer */
++ SDCONFIG_BUS_MODE_DATA SavedBusMode; /* saved bus mode */
++ HCD_OS_INFO OSInfo; /* the single device's OS-Specific */
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDLIST DeviceList; /* the list of current devices handled by this driver */
++ OS_SEMAPHORE DeviceListSem; /* protection for the DeviceList */
++ UINT DeviceCount; /* number of devices currently installed */
++ SDHCD_DRIVER Driver; /* OS dependent driver specific info */
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DEVICE pDeviceContext);
++void HcdDeinitialize(PSDHCD_DEVICE pDeviceContext);
++BOOL HcdSDInterrupt(PSDHCD_DEVICE pDeviceContext);
++BOOL HcdTransferTxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq);
++BOOL HcdTransferRxData(PSDHCD_DEVICE pDevice, PSDREQUEST pReq, BOOL Flush);
++
++
++/* OS-dependent layer prototypes */
++SDIO_STATUS QueueEventResponse(PSDHCD_DEVICE pDeviceContext, INT WorkItemID);
++UINT16 MaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr);
++UINT16 UnmaskIrq(PSDHCD_DEVICE pDevice, UINT16 Mask, BOOL FromIsr);
++SDIO_STATUS SetUpHCDDMA(PSDHCD_DEVICE pDevice,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext);
++BOOL WriteProtectSwitchOn(PSDHCD_DEVICE pDevice);
++void SDCancelDMATransfer(PSDHCD_DEVICE pDevice);
++SDIO_STATUS SetPowerLevel(PSDHCD_DEVICE pDeviceContext, BOOL On, SLOT_VOLTAGE_MASK Level);
++void GetDefaults(PSDHCD_DEVICE pDeviceContext);
++void CompleteRequestSyncDMA(PSDHCD_DEVICE pDeviceContext, PSDREQUEST pRequest, SDIO_STATUS Status);
++void MicroDelay(INT Microseconds);
++#define DBG_GPIO_PIN_1 1
++#define DBG_GPIO_PIN_2 2
++
++#ifdef OMAP_USE_DBG_GPIO
++void ToggleGPIOPin(PSDHCD_DEVICE pDevice, INT PinNo);
++#else
++#define ToggleGPIOPin(p,n)
++#endif
++/* end OS layer prototypes */
++
++#endif /* __SDIO_OMAP_HCD_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/pxa255/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa255/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO pxa255 host controller
++#
++obj-m += sdio_pxa255hcd.o
++sdio_pxa255hcd-objs := sdio_hcd.o linux/sdio_hcd_os.o
+Index: linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,914 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd.c
++
++ at abstract: PXA255 Local Bus SDIO Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include "sdio_pxa255hcd.h"
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++void Dbg_DumpBuffer(PUCHAR pBuffer, INT Length);
++
++#define WAIT_FOR_MMC(pHct,pCancel,DoneMask,Error,ErrorMask) \
++{ \
++ while(!*(pCancel) && \
++ !(READ_MMC_REG((pHct), MMC_STAT_REG) & (DoneMask)) && \
++ !(*(Error) = READ_MMC_REG((pHct), MMC_STAT_REG) & (ErrorMask))); \
++ *(Error) = READ_MMC_REG((pHct), MMC_STAT_REG) & (ErrorMask); \
++}
++
++MMC_CLOCK_TBL_ENTRY MMCClockDivisorTable[MMC_MAX_CLOCK_ENTRIES] =
++{
++ {20000000,0x00}, /* must be in decending order */
++ {10000000,0x01},
++ {5000000,0x02},
++ {2500000,0x03},
++ {1250000,0x04},
++ {625000,0x05},
++ {312000,0x06}
++};
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskMMCIrq - Un mask an MMC interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void UnmaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask)
++{
++ UINT32 ints;
++ ints = READ_MMC_REG(pHct, MMC_I_MASK_REG);
++ ints &= ~Mask;
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, ints);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskMMCIrq - Mask MMC interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static inline void MaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask)
++{
++ UINT32 ints;
++ ints = READ_MMC_REG(pHct, MMC_I_MASK_REG);
++ ints |= Mask;
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, ints);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pHct - host context
++ pReq - the request
++ Output:
++ Return: returns status
++ Notes: This function returns SDIO_STATUS_SUCCESS for SD mode. In SPI mode, all cards return
++ response tokens regardless of whether the command is supported or not. In SD, the response times
++ times-out and we would never reach here. In SPI mode we query the bus driver to check the SPI
++ response and return an appropriate error status to "simulate" timeouts.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS GetResponseData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT wordCount;
++ INT byteCount;
++ UINT16 readBuffer[8];
++ UINT16 *pBuf;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ /* handle SPI oddities */
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_RESP_R2:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ /* this is the special SPI R2 and SPI SDIO R5 responses */
++ byteCount = 2;
++ wordCount = 1;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* SD, MMC, SDIO OCR reading */
++ byteCount = 5;
++ wordCount = 3;
++ break;
++ default:
++ byteCount = 1;
++ wordCount = 1;
++ break;
++ }
++ } else {
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES;
++ }
++ wordCount = byteCount / 2;
++ }
++
++ /* start the buffer at the tail and work backwards since responses are sent MSB first
++ and shifted into the FIFO */
++ pBuf = &readBuffer[(wordCount - 1)];
++ while (wordCount) {
++ *pBuf = (UINT16)READ_MMC_REG(pHct, MMC_RES_REG);
++ pBuf--;
++ wordCount--;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ switch (byteCount) {
++ case 1:
++ /* the single response byte is stuck in the MSB */
++ pReq->Response[0] = readBuffer[0] >> 8;
++ break;
++ case 2:
++ /* extended status token , shifted in last */
++ pReq->Response[0] = (UINT8)readBuffer[0];
++ /* response token shifted in first (in the high byte) */
++ pReq->Response[1] = (UINT8)(readBuffer[0] >> 8);
++ break;
++ case 5:
++ /* offset the read buffer by one byte since we read WORDs from fifo */
++ memcpy(&pReq->Response[0],((PUINT8)readBuffer) + 1, 5);
++ break;
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_REQUESTS) {
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO PXA255 - Response Dump (SPI)");
++ }
++ /* the bus driver will determine the appropriate status based on the SPI
++ * token received, the bus driver may return a time-out status for tokens indicating an
++ * illegal command */
++ return SDIO_CheckResponse(&pHct->Hcd, pReq, SDHCD_CHECK_SPI_TOKEN);
++ }
++
++ /* handle normal SD/MMC responses */
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ pReq->Response[0] = 0x00;
++ /* adjust for lack of CRC */
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++ } else {
++ memcpy(pReq->Response,readBuffer,byteCount);
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_REQUESTS) {
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = 17;
++ }
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO PXA255 - Response Dump");
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++void DumpCurrentRequestInfo(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ if (pHct->Hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - Current Request Command:%d, ARG:0x%8.8X\n",
++ pHct->Hcd.pCurrentRequest->Command, pHct->Hcd.pCurrentRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pHct->Hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pHct->Hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ pHct->Hcd.pCurrentRequest->BlockCount,
++ pHct->Hcd.pCurrentRequest->BlockLen,
++ pHct->Hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateMMCError - check for an MMC error
++ Input: MMCStatus - MMC status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateMMCError(PSDHCD_DRIVER_CONTEXT pHct,UINT32 MMCStatus)
++{
++
++
++
++ if (MMCStatus & MMC_STAT_RESP_CRC_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - RESP CRC ERROR \n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ } else if (MMCStatus & MMC_STAT_SPI_RDTKN_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - SPI RDTKN ERROR \n"));
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ } else if (MMCStatus & MMC_STAT_RDDAT_CRC_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - READDATA CRC ERROR \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ } else if (MMCStatus & MMC_STAT_WR_ERROR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - WRITE ERROR \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_WRITE_ERROR;
++ } else if (MMCStatus & MMC_STAT_RESP_TIMEOUT) {
++ if (pHct->CardInserted) {
++ /* hide error if we are polling an empty slot */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - RESPONSE TIMEOUT \n"));
++ }
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ } else if (MMCStatus & MMC_STAT_READ_TIMEOUT) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - READ TIMEOUT \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - MMC clock control
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_DRIVER_CONTEXT pHct, BOOL On)
++{
++
++ if (On) {
++ WRITE_MMC_REG(pHct, MMC_STRPCL_REG, MMC_CLOCK_START);
++ } else {
++ if (READ_MMC_REG(pHct, MMC_STAT_REG) & MMC_STAT_CLK_ON) {
++ WRITE_MMC_REG(pHct, MMC_STRPCL_REG, MMC_CLOCK_STOP);
++ /* wait for clock to stop */
++ while (READ_MMC_REG(pHct, MMC_STAT_REG) & MMC_STAT_CLK_ON);
++ }
++ CLEAR_TEST_PIN(pHct);
++ }
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pHcd - HCD object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DRIVER_CONTEXT pHct, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int i;
++ int clockIndex;
++
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA255 - SetMode\n"));
++
++ /* set clock index to the end, the table is sorted this way */
++ clockIndex = MMC_MAX_CLOCK_ENTRIES - 1;
++ pMode->ActualClockRate = MMCClockDivisorTable[clockIndex].ClockRate;
++ for (i = 0; i < MMC_MAX_CLOCK_ENTRIES; i++) {
++ if (pMode->ClockRate >= MMCClockDivisorTable[i].ClockRate) {
++ pMode->ActualClockRate = MMCClockDivisorTable[i].ClockRate;
++ clockIndex = i;
++ break;
++ }
++ }
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_SPI:
++ /* nothing to really do here */
++ if (pMode->BusModeFlags & SDCONFIG_BUS_MODE_SPI_NO_CRC) {
++ /* caller wants all SPI transactions without CRC */
++ } else {
++ /* caller wants all SPI transaction to use CRC */
++ }
++ break;
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ DBG_ASSERT(FALSE);
++ break;
++ default:
++ break;
++ }
++
++ /* set the clock divisor */
++ WRITE_MMC_REG(pHct, MMC_CLKRT_REG, MMCClockDivisorTable[clockIndex].Divisor);
++
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA255 - MMCClock: %d Khz\n", pMode->ActualClockRate));
++
++}
++
++BOOL HcdTransferTxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++ volatile UINT32 *pFifo;
++ BOOL partial = FALSE;
++
++ pFifo = (volatile UINT32 *)((UINT32)GET_MMC_BASE(pHct) + MMC_TXFIFO_REG);
++ dataCopy = min(pReq->DataRemaining,(UINT32)MMC_MAX_TXFIFO);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* clear partial flag */
++ WRITE_MMC_REG(pHct,MMC_PRTBUF_REG,0);
++
++ if (dataCopy < MMC_MAX_TXFIFO) {
++ /* need to set partial flag after we load the fifos */
++ partial = TRUE;
++ }
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* copy to fifo */
++ while(dataCopy) {
++ _WRITE_DWORD_REG(pFifo,(UINT32)(*pBuf));
++ dataCopy--;
++ pBuf++;
++ }
++
++ if (partial) {
++ /* partial buffer */
++ WRITE_MMC_REG(pHct,MMC_PRTBUF_REG,MMC_PRTBUF_PARTIAL);
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++ return TRUE;
++}
++
++void HcdTransferRxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT dataCopy, thisCopy;
++ PUINT8 pBuf;
++ volatile UINT32 *pFifo;
++
++ pFifo = (volatile UINT32 *)((UINT32)GET_MMC_BASE(pHct) + MMC_RXFIFO_REG);
++ dataCopy = min(pReq->DataRemaining,(UINT32)MMC_MAX_RXFIFO);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ thisCopy = dataCopy;
++ /* copy from fifo */
++ while(dataCopy) {
++ (*pBuf) = (UINT8)_READ_DWORD_REG(pFifo);
++ dataCopy--;
++ pBuf++;
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_DATA) {
++ SDLIB_PrintBuffer(pReq->pHcdContext,thisCopy,"SDIO PXA255 - RX FIFO Dump");
++ }
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++}
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ UINT32 HwErrors)
++{
++ SDIO_STATUS status;
++ UINT32 statValue = 0;
++ UINT32 errorMask = 0;
++
++ if (HwErrors) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 command failure: STAT:0x%X \n",HwErrors));
++ status = TranslateMMCError(pHct,HwErrors);
++ } else if (pHct->Cancel) {
++ status = SDIO_STATUS_CANCELED;
++ } else {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 command success: STAT:0x%X \n",
++ READ_MMC_REG((pHct), MMC_STAT_REG)));
++ /* get the response data for the command */
++ status = GetResponseData(pHct,pReq);
++ }
++ /* check for data */
++ if (SDIO_SUCCESS(status) && IS_SDREQ_DATA_TRANS(pReq->Flags)){
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pHct->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++ if (SDIO_SUCCESS(status)) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* for writes, we need to pre-load the TX FIFO */
++ if (HcdTransferTxData(pHct, pReq)) {
++ /* entire transfer fits inside the fifos */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) {
++ /* the requestor has provided us with a hint, we can poll for
++ * completion if it fits in the fifo */
++ statValue = MMC_STAT_PRG_DONE;
++ errorMask = MMC_STAT_WR_ERROR;
++
++ } else {
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS);
++ }
++ } else {
++ /* expecting a TX empty interrupt */
++ UnmaskMMCIrq(pHct, MMC_MASK_TXFIFO_WR);
++ }
++ } else {
++ if (pReq->DataRemaining <= MMC_MAX_RXFIFO) {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) {
++ /* the requestor has provided us with a hint, we can poll for
++ * completion since this is less than a FIFOs worth */
++ statValue = MMC_STAT_DATA_DONE;
++ errorMask = MMC_STAT_RD_ERRORS;
++ } else {
++ /* just wait for data transfer done, we won't get fifo full interrupts */
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS);
++ }
++ } else {
++ /* turn on fifo full interrupts */
++ UnmaskMMCIrq(pHct, MMC_MASK_RXFIFO_RD);
++ }
++ }
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 Pending %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++
++ if (0 == statValue) {
++ /* return pending */
++ status = SDIO_STATUS_PENDING;
++ } else {
++ /* this will be polled in-line */
++ status = SDIO_STATUS_SUCCESS;
++ }
++ }
++ }
++
++ if (statValue != 0) {
++ UINT32 temp = 0;
++ {
++ volatile BOOL *pCancel;
++ pCancel = (volatile BOOL *)&pHct->Cancel;
++
++ WAIT_FOR_MMC(pHct,pCancel,statValue,&temp,errorMask);
++ }
++
++ if (temp) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 Short Transfer Failure: STAT:0x%X \n",temp));
++ status = TranslateMMCError(pHct,temp);
++ } else {
++ if (!IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* drain the FIFO on reads */
++ HcdTransferRxData(pHct,pReq);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ }
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT32 temp = 0;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* check for CMD0 */
++ if (pReq->Command == 0x00) {
++ /* this command must always have a CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_WITH_CRC);
++ } else {
++ /* for all other SPI-mode commands, check bus mode */
++ if (IS_HCD_BUS_MODE_SPI_NO_CRC(pHcd)) {
++ /* not running with CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_NO_CRC);
++ } else {
++ /* running with CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_WITH_CRC);
++ }
++ }
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_MMC_R4:
++ case SDREQ_FLAGS_RESP_MMC_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ temp |= MMC_CMDDAT_RES_R1_R4_R5;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp |= (MMC_CMDDAT_RES_R1_R4_R5 | MMC_CMDAT_RES_BUSY);
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp |= MMC_CMDDAT_RES_R2;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* sdio R5s in SPI mode is really an R2 in SPI mode */
++ temp |= MMC_CMDDAT_RES_R2;
++ } else {
++ /* in SD mode, its an R1 */
++ temp |= MMC_CMDDAT_RES_R1_R4_R5;
++ }
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp |= MMC_CMDDAT_RES_R3;
++ break;
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ temp |= MMC_CMDDAT_DATA_EN;
++ /* set block length */
++ WRITE_MMC_REG(pHct, MMC_BLKLEN_REG, pReq->BlockLen);
++ WRITE_MMC_REG(pHct, MMC_NOB_REG_REG, pReq->BlockCount);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ temp |= MMC_CMDDAT_DATA_WR;
++ }
++ }
++
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++
++
++ WRITE_MMC_REG(pHct, MMC_CMD_REG, pReq->Command);
++ WRITE_MMC_REG(pHct, MMC_ARGH_REG, (pReq->Argument >> 16));
++ WRITE_MMC_REG(pHct, MMC_ARGL_REG, (pReq->Argument & 0xFFFF));
++ WRITE_MMC_REG(pHct, MMC_CMDAT_REG, temp);
++
++ if (SDHCD_GET_OPER_CLOCK(pHcd) < HCD_COMMAND_MIN_POLLING_CLOCK) {
++ /* clock rate is very low, need to use interrupts here */
++ UnmaskMMCIrq(pHct, MMC_MASK_END_CMD);
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ status = SDIO_STATUS_PENDING;
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 using interrupt for command done.. \n"));
++ } else {
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 waiting for command done.. \n"));
++ temp = 0;
++ {
++ volatile BOOL *pCancel;
++ pCancel = (volatile BOOL *)&pHct->Cancel;
++ /* this macro polls */
++ WAIT_FOR_MMC(pHct,pCancel,MMC_STAT_END_CMD,&temp,MMC_RESP_ERRORS);
++ }
++ /* process the command completion */
++ status = ProcessCommandDone(pHct,pReq,temp);
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ ClockStartStop(pHct, CLOCK_OFF);
++ pReq->Status = status;
++ pHct->Cancel = FALSE;
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags)) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ return SDIO_STATUS_PENDING;
++ }
++ /* complete the request */
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA255 Command Done - inline, status:%d \n", status));
++ /* fall through and return the non-pending status */
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT16 command;
++
++ command = GET_SDCONFIG_CMD(pConfig);
++
++ switch (command){
++ case SDCONFIG_GET_WP:
++ if (GetGpioPinLevel(pHct,SDIO_CARD_WP_GPIO) == WP_POLARITY) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ ClockStartStop(pHct,CLOCK_ON);
++ /* should be at least 80 clocks at our lowest clock setting */
++ status = OSSleep(100);
++ ClockStartStop(pHct,CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ status = EnableDisableSDIOIrq(pHct, TRUE);
++ if (SDIO_SUCCESS(status) && IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* turn on chip select */
++ ModifyCSForSPIIntDetection(pHct, TRUE);
++ }
++ } else {
++ status = EnableDisableSDIOIrq(pHct, FALSE);
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* switch CS */
++ ModifyCSForSPIIntDetection(pHct, FALSE);
++ }
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ AckSDIOIrq(pHct);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pHct, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ /* TODO, the slot just connects VCC straight to the slot nothing to adjust here */
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA255 PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: HcdConfig - bad command: 0x%X\n",command));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize MMC controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ /* turn off clock */
++ ClockStartStop(pHct, CLOCK_OFF);
++ /* init controller */
++ if (pHct->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 Using SPI Mode\n"));
++ /* each HCD request will set up SPI mode with or without CRC protection */
++ }else if (pHct->Hcd.Attributes & SDHCD_ATTRIB_BUS_1BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 Using 1-bit MMC Mode\n"));
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ 0x00);
++ }
++
++ WRITE_MMC_REG(pHct, MMC_RESTO_REG, SDMMC_RESP_TIMEOUT_CLOCKS);
++ WRITE_MMC_REG(pHct, MMC_RDTO_REG, SDMMC_DATA_TIMEOUT_CLOCKS);
++ MaskMMCIrq(pHct,MMC_MASK_ALL_INTS);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate MMC controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ EnableDisableSDIOIrq(pHct, FALSE);
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, MMC_MASK_ALL_INTS);
++ ClockStartStop(pHct, CLOCK_OFF);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdMMCInterrupt - process MMC controller interrupt
++ Input: pHct - HCD context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdMMCInterrupt(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ UINT32 ints,errors;
++ PSDREQUEST pReq;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("+SDIO PXA255 IMMC Int handler \n"));
++
++ ints = READ_MMC_REG(pHct, MMC_I_REG_REG);
++
++ if (!ints) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO PXA255 False Interrupt! \n"));
++ return FALSE;
++ }
++
++ errors = 0;
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++
++ while ((ints = READ_MMC_REG(pHct, MMC_I_REG_REG))){
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PXA255 Ints:0x%X \n", ints));
++
++ /* read status */
++ errors = READ_MMC_REG(pHct, MMC_STAT_REG);
++
++ if (ints & MMC_INT_END_CMD) {
++ /* mask off end cmd */
++ MaskMMCIrq(pHct, MMC_MASK_END_CMD);
++ /* only care about response errors */
++ errors &= MMC_RESP_ERRORS;
++ status = ProcessCommandDone(pHct,pReq,errors);
++ if (status != SDIO_STATUS_PENDING) {
++ /* no data phase or the command failed, get out */
++ break;
++ }
++ /* ProcessCommandDone will turn on interrupts for data transfers */
++ continue;
++ }
++
++ /* if we get here, its a data transfer interrupt */
++
++ /* filter data errors */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ errors &= MMC_STAT_WR_ERROR;
++ } else {
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ errors &= (MMC_STAT_RD_ERRORS | MMC_STAT_SPI_RDTKN_ERR);
++ } else {
++ errors &= MMC_STAT_RD_ERRORS;
++ }
++ }
++
++ if (errors) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA- Data Transfer has errors: Stat:0x%X \n", errors));
++ /* set status based on error */
++ status = TranslateMMCError(pHct,errors);
++ break;
++ }
++
++ if (ints & MMC_INT_TXFIFO_WR) {
++ /* transfer data */
++ if (HcdTransferTxData(pHct, pReq)) {
++ MaskMMCIrq(pHct, MMC_MASK_TXFIFO_WR);
++ /* transfer is complete, wait for done */
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 TX Fifo writes done. Waiting for TRANS_DONE \n"));
++ }
++ continue;
++ }
++
++ if (ints & MMC_INT_RXFIFO_RD) {
++ /* unload fifo */
++ HcdTransferRxData(pHct,pReq);
++ if (pReq->DataRemaining < MMC_MAX_RXFIFO) {
++ /* we're done or there is a partial FIFO left */
++ MaskMMCIrq(pHct, MMC_MASK_RXFIFO_RD);
++ /* transfer is complete wait for CRC check*/
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 RX Waiting for TRANS_DONE \n"));
++ }
++ continue;
++ }
++
++ if (ints & MMC_INT_DATA_TRANS) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* data transfer done */
++ MaskMMCIrq(pHct, MMC_MASK_DATA_TRANS);
++ /* now wait for program done signalling */
++ UnmaskMMCIrq(pHct, MMC_MASK_PRG_DONE);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 Transfer done, Waiting for PRG_DONE \n"));
++ continue;
++ } else {
++ if (pReq->DataRemaining) {
++ /* there was partial FIFO, we need to drain it */
++ HcdTransferRxData(pHct,pReq);
++ /* this should drain it */
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ /* if we get here without an error, we are done with the read
++ * data operation */
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 RX Transfer done \n"));
++ break;
++ }
++ }
++
++ if (ints & MMC_INT_PRG_DONE) {
++ /* if we get here without errors, we are done with the
++ * write data operation */
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA255 Got TX PRG_DONE. \n"));
++ break;
++ }
++
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* set the status */
++ pReq->Status = status;
++ /* turn off interrupts and clock */
++ MaskMMCIrq(pHct, MMC_MASK_ALL_INTS);
++ ClockStartStop(pHct, CLOCK_OFF);
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ }
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("-SDIO PXA255 IMMC Int handler \n"));
++ return TRUE;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetGpioPinLevel - get gpio pin level
++ Input: pHct - HCD context
++ Pin - gpio pin number
++ Output:
++ Return: TRUE if pin level is high, low otherwise
++ Notes:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL GetGpioPinLevel(PSDHCD_DRIVER_CONTEXT pHct, INT Pin)
++{
++ UINT32 gpio_pinlvl_offset = 0;
++ UINT32 gpio_state;
++ UINT32 mask;
++
++ mask = (1 << (Pin % 32));
++ gpio_pinlvl_offset = (Pin / 32);
++ gpio_pinlvl_offset = GPIO_GPLR0 + gpio_pinlvl_offset*4;
++
++ gpio_state = READ_GPIO_REG(pHct, gpio_pinlvl_offset);
++//?? DBG_PRINT(SDDBG_TRACE, ("+-gpio pin:%d, mask:0x%X, offset:0x%X, read:0x%X \n",
++//?? Pin,mask,gpio_pinlvl_offset,gpio_state));
++ return ((gpio_state & mask) ? TRUE : FALSE);
++}
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,136 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_linux.h
++
++ at abstract: include file for PX255 local bus host controller, linux dependent code
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++
++#include <asm/irq.h>
++
++#define SDIO_IRQ_GPIO 21 /* SDIO IRQ pin on DAT1 */
++#define SDIO_CARD_INSERT_GPIO 11 /* card insertion switch */
++//#define SDIO_CARD_INSERT_GPIO 29
++#define SDIO_CARD_WP_GPIO 22 /* write protect switch position */
++#define CARD_INSERT_POLARITY FALSE
++#define WP_POLARITY TRUE
++
++/* interrupt assignments */
++#define SDIO_PXA_CONTROLLER_IRQ IRQ_MMC
++#define SDIO_PXA_SDIO_IRQ IRQ_GPIO(SDIO_IRQ_GPIO)
++#define SDIO_PXA_CARD_INSERT_IRQ IRQ_GPIO(SDIO_CARD_INSERT_GPIO)
++
++/* debounce delay for slot */
++#define PXA_SLOT_DEBOUNCE_MS 2000
++
++/* major number, zero indicates assign dynamically */
++#define SDIO_BD_MAJOR_INIT 0
++
++/* device base name */
++#define SDIO_BD_BASE "sdiobd"
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++/* device data*/
++typedef struct _SDHCD_DEVICE {
++ OS_PNPDEVICE HcdDevice; /* the OS device for this HCD */
++ OS_PNPDRIVER HcdDriver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION Dma; /* driver DMA description */
++ POS_PNPDEVICE pBusDevice; /* our device registered with bus driver */
++ UINT MMCInterrupt; /* controller interrupt */
++ UINT CardInsertInterrupt; /* card insert interrupt */
++ UINT SDIOInterrupt; /* sdio interrupt interrupt */
++ UINT8 InitStateMask;
++#define MMC_INTERRUPT_INIT 0x01
++#define CARD_DETECT_INTERRUPT_INIT 0x02
++#define SDIO_IRQ_INTERRUPT_INIT 0x04
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x20
++#define TIMER_INIT 0x40
++ SDHCD_MEMORY ControlRegs; /* memory addresses of device */
++ SDHCD_MEMORY GpioRegs; /* memory addresses of device */
++ spinlock_t Lock; /* lock against the ISR */
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++#define GET_MMC_BASE(pC)(pC)->Device.ControlRegs.pMapped
++#define READ_GPIO_REG(pC, OFFSET) \
++ _READ_DWORD_REG(((UINT32)(pC)->Device.GpioRegs.pMapped) + (OFFSET))
++#define WRITE_GPIO_REG(pC, OFFSET,VALUE) \
++ _WRITE_DWORD_REG(((UINT32)(pC)->Device.GpioRegs.pMapped) + (OFFSET),(VALUE))
++#define READ_MMC_REG(pC, OFFSET) \
++ _READ_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET))
++#define WRITE_MMC_REG(pC, OFFSET, VALUE) \
++ _WRITE_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET),(VALUE))
++
++//#define ENABLE_TEST_PIN 1
++
++#ifdef ENABLE_TEST_PIN /* used for scope capture */
++#define TEST_PIN_GPIO GPIO59_LDD_1
++#define TEST_PIN_GPSR GPIO_GPSR1
++#define TEST_PIN_GPCR GPIO_GPCR1
++#define SET_TEST_PIN(pHct) { \
++ if (IS_HCD_BUS_MODE_SPI(&(pHct)->Hcd)) { \
++ WRITE_GPIO_REG((pHct),TEST_PIN_GPSR,GPIO_bit(TEST_PIN_GPIO)); \
++ } \
++}
++
++#define CLEAR_TEST_PIN(pHct) { \
++ if (IS_HCD_BUS_MODE_SPI(&(pHct)->Hcd)) { \
++ WRITE_GPIO_REG((pHct),TEST_PIN_GPCR,GPIO_bit(TEST_PIN_GPIO)); \
++ } \
++}
++#else
++#define SET_TEST_PIN(pHct)
++#define CLEAR_TEST_PIN(pHct)
++#endif
++/* prototypes */
++#endif /* __SDIO_HCD_LINUX_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_hcd_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,589 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Linux PXA255 Local Bus SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++
++#define DBG_DECLARE 7;
++#include <linux/sdio/ctsystem.h>
++
++#include "sdio_pxa255hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#define DESCRIPTION "SDIO PXA255 Local Bus HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId);
++static void Remove(struct pnp_dev *pBusDevice);
++static SYSTEM_STATUS MapAddress(PSDHCD_MEMORY pMap, PTEXT pDescription);
++static void UnmapAddress(PSDHCD_MEMORY pMap);
++
++static irqreturn_t hcd_mmc_irq(int irq, void *context, struct pt_regs * r);
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r);
++//static irqreturn_t hcd_card_detect_irq(int irq, void *context, struct pt_regs * r);
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++//static void hcd_carddetect_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++#define DEFAULT_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | SDHCD_ATTRIB_SLOT_POLLING)
++UINT32 hcdattributes = DEFAULT_ATTRIBUTES;
++module_param(hcdattributes, int, 0644);
++MODULE_PARM_DESC(hcdattributes, "PXA255 Attributes");
++
++
++
++/* the driver context data */
++static SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .Hcd.pName = "sdio_pxa255hcd",
++ .Hcd.Version = CT_SDIO_STACK_VERSION_CODE,
++ .Hcd.SlotNumber = 0,
++ .Hcd.Attributes = DEFAULT_ATTRIBUTES,
++ .Hcd.MaxBytesPerBlock = SDIO_PXA_MAX_BYTES_PER_BLOCK,
++ .Hcd.MaxBlocksPerTrans = SDIO_PXA_MAX_BLOCKS,
++ .Hcd.MaxSlotCurrent = 500, /* 1/2 amp */
++ .Hcd.SlotVoltageCaps = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.MaxClockRate = 20000000, /* 20 Mhz */
++ .Hcd.pContext = &HcdContext,
++ .Hcd.pRequest = HcdRequest,
++ .Hcd.pConfigure = HcdConfig,
++ .Device.HcdDevice.name = "sdio_pxa255_hcd",
++ .Device.HcdDriver.name = "sdio_pxa255_hcd",
++ .Device.HcdDriver.probe = Probe,
++ .Device.HcdDriver.remove = Remove,
++};
++
++
++/* work queues */
++static DECLARE_WORK(iocomplete_work, hcd_iocomplete_wqueue_handler, &HcdContext);
++//static DECLARE_WORK(carddetect_work, hcd_carddetect_wqueue_handler, &HcdContext);
++static DECLARE_WORK(sdioirq_work, hcd_sdioirq_wqueue_handler, &HcdContext);
++
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId)
++{
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status;
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 Local HCD: Probe - probing for new device\n"));
++
++ pHcdContext->Device.pBusDevice = pBusDevice;
++ pHcdContext->Hcd.pDevice = &pBusDevice->dev;
++ pHcdContext->Hcd.pModule = THIS_MODULE;
++ pHcdContext->Device.MMCInterrupt = SDIO_PXA_CONTROLLER_IRQ;
++ pHcdContext->Device.CardInsertInterrupt = SDIO_PXA_CARD_INSERT_IRQ;
++ pHcdContext->Device.SDIOInterrupt = SDIO_PXA_SDIO_IRQ;
++ pHcdContext->Device.ControlRegs.Raw = PXA_MMC_CONTROLLER_BASE_ADDRESS;
++ pHcdContext->Device.ControlRegs.Length = PXA_MMC_CONTROLLER_ADDRESS_LENGTH;
++ pHcdContext->Device.GpioRegs.Raw = PXA_GPIO_PIN_LVL_REGS_BASE;
++ pHcdContext->Device.GpioRegs.Length = PXA_GPIO_PIN_LVL_REGS_LENGTH;
++ spin_lock_init(&pHcdContext->Device.Lock);
++ pHcdContext->Hcd.Attributes = hcdattributes;
++
++ if (pHcdContext->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ /* in SPI mode, the controller only supports 1 block */
++ pHcdContext->Hcd.MaxBytesPerBlock = SPI_PXA_MAX_BYTES_PER_BLOCK;
++ pHcdContext->Hcd.MaxBlocksPerTrans = SPI_PXA_MAX_BLOCKS;
++ }
++
++ do {
++
++ /* map the devices memory addresses */
++ err = MapAddress(&pHcdContext->Device.ControlRegs, "SDIOPXA255");
++ if (err < 0) {
++ /* couldn't map the address */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: Probe - unable to map memory\n"));
++ break;
++ }
++
++ err = MapAddress(&pHcdContext->Device.GpioRegs, "SDIOPXA255");
++ if (err < 0) {
++ /* couldn't map the address */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: Probe - unable to map memory\n"));
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 Switching GPIO lines \n"));
++ /* switch GPIO6 to MMCClock */
++ pxa_gpio_mode(GPIO6_MMCCLK_MD);
++ pxa_gpio_mode(GPIO8_MMCCS0_MD);
++#ifdef ENABLE_TEST_PIN
++ if (pHcdContext->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ pxa_gpio_mode(TEST_PIN_GPIO | GPIO_OUT);
++ CLEAR_TEST_PIN(pHcdContext);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 GPDR:0x%X , GPLR:0x%X -x \n",
++ READ_GPIO_REG(pHcdContext,GPIO_GPDR1),
++ READ_GPIO_REG(pHcdContext,GPIO_GPLR1)));
++ }
++#endif
++ /* route MMC clock */
++ pxa_set_cken(CKEN12_MMC, 1);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 - MMC IRQ:%d \n",
++ pHcdContext->Device.MMCInterrupt));
++
++ /* map the controller interrupt */
++ err = request_irq (pHcdContext->Device.MMCInterrupt, hcd_mmc_irq, 0,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - unable to map MMC interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= MMC_INTERRUPT_INIT;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 - card insert IRQ:%d \n",
++ pHcdContext->Device.CardInsertInterrupt));
++
++#if 0 // card detect does not work reliably on gumstix
++ /* map the card insert interrupt */
++ err = request_irq (pHcdContext->Device.CardInsertInterrupt, hcd_card_detect_irq, SA_SHIRQ,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - unable to map CardInsert interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++
++ //err = set_irq_type(pHcdContext->Device.CardInsertInterrupt, IRQT_BOTHEDGE);
++ err = set_irq_type(pHcdContext->Device.CardInsertInterrupt, IRQT_RISING);
++
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - failed to set card insert IRQ edge \n"));
++ err = -ENODEV;
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= CARD_DETECT_INTERRUPT_INIT;
++#endif
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 - SDIO IRQ:%d \n", pHcdContext->Device.SDIOInterrupt));
++ /* map the SDIO IRQ interrupt */
++ err = request_irq (pHcdContext->Device.SDIOInterrupt, hcd_sdio_irq, SA_SHIRQ,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - unable to map SDIO-IRQ interrupt\n"));
++ err = -ENODEV;
++ break;
++ }
++ pHcdContext->Device.InitStateMask |= SDIO_IRQ_INTERRUPT_INIT;
++
++
++ if (!SDIO_SUCCESS((status = HcdInitialize(pHcdContext)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - failed to init HW, status =%d\n", status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= SDHC_HW_INIT;
++
++ /* register with the SDIO bus driver */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pHcdContext->Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - failed to register with host, status =%d\n",
++ status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= SDHC_REGISTERED;
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - GRER0 0x%X \n",
++ READ_GPIO_REG(pHcdContext, GPIO_GRER0)));
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - GFER0 0x%X \n",
++ READ_GPIO_REG(pHcdContext, GPIO_GFER0)));
++ } while (FALSE);
++
++ if (err < 0) {
++ Remove(pBusDevice); /* TODO: the cleanup should not really be done in the Remove function */
++ } else {
++ /* check and see if there is a card inserted at powerup */
++#if 0 /* GPIO pin read for insert does not work on Gumstix */
++ if (GetGpioPinLevel(pHcdContext,SDIO_CARD_INSERT_GPIO) == CARD_INSERT_POLARITY) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - Card Detected \n"));
++ /* queue the work item to notify the bus driver */
++ if (!SDIO_SUCCESS(QueueEventResponse(pHcdContext, WORK_ITEM_SDIO_IRQ))) {
++ /* failed */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - queue event failed\n"));
++ }
++ }
++#endif /* 0 */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Probe - HCD ready! \n"));
++ }
++ return err;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++static void Remove(struct pnp_dev *pBusDevice)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PXA255 Local HCD: Remove - removing device\n"));
++
++ if (pHcdContext->Device.InitStateMask & MMC_INTERRUPT_INIT) {
++ /* TODO mask all controller interrupts */
++ }
++
++ if (pHcdContext->Device.InitStateMask & SDHC_REGISTERED) {
++ /* unregister from the bus driver */
++ SDIO_UnregisterHostController(&pHcdContext->Hcd);
++ }
++ /* free irqs */
++ if (pHcdContext->Device.InitStateMask & MMC_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.MMCInterrupt, pHcdContext);
++ }
++ if (pHcdContext->Device.InitStateMask & CARD_DETECT_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.CardInsertInterrupt, pHcdContext);
++ }
++ if (pHcdContext->Device.InitStateMask & SDIO_IRQ_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.SDIOInterrupt, pHcdContext);
++ }
++
++ if (pHcdContext->Device.InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pHcdContext);
++ }
++
++ pHcdContext->Device.InitStateMask = 0;
++
++ /* free mapped registers */
++ if (pHcdContext->Device.ControlRegs.pMapped != NULL) {
++ UnmapAddress(&pHcdContext->Device.ControlRegs);
++ pHcdContext->Device.ControlRegs.pMapped = NULL;
++ }
++
++ if (pHcdContext->Device.GpioRegs.pMapped != NULL) {
++ UnmapAddress(&pHcdContext->Device.GpioRegs);
++ pHcdContext->Device.GpioRegs.pMapped = NULL;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PXA255 Local HCD: Remove\n"));
++}
++
++/*
++ * MapAddress - maps I/O address
++*/
++static SYSTEM_STATUS MapAddress(PSDHCD_MEMORY pMap, PTEXT pDescription) {
++
++ if (request_mem_region(pMap->Raw, pMap->Length, pDescription) == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: MapAddress - memory in use\n"));
++ return -EBUSY;
++ }
++ pMap->pMapped = ioremap_nocache(pMap->Raw, pMap->Length);
++ if (pMap->pMapped == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: MapAddress - unable to map memory\n"));
++ /* cleanup region */
++ release_mem_region(pMap->Raw, pMap->Length);
++ return -EFAULT;
++ }
++ return 0;
++}
++
++/*
++ * UnmapAddress - unmaps the address
++*/
++static void UnmapAddress(PSDHCD_MEMORY pMap) {
++ iounmap(pMap->pMapped);
++ release_mem_region(pMap->Raw, pMap->Length);
++ pMap->pMapped = NULL;
++}
++
++/* MMC controller interrupt routine */
++static irqreturn_t hcd_mmc_irq(int irq, void *context, struct pt_regs * r)
++{
++ /* call OS independent ISR */
++ if (HcdMMCInterrupt((PSDHCD_DRIVER_CONTEXT)context)) {
++ return IRQ_HANDLED;
++ } else {
++ return IRQ_NONE;
++ }
++}
++
++#if 0
++/* card detect interrupt request */
++static irqreturn_t hcd_card_detect_irq(int irq, void *context, struct pt_regs * r)
++{
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("SDIO PXA255 Card Detect Interrupt, queueing work item \n"));
++ /* just queue the work item to debounce the pin */
++ QueueEventResponse((PSDHCD_DRIVER_CONTEXT)context, WORK_ITEM_CARD_DETECT);
++ return IRQ_HANDLED;
++}
++#endif
++
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHcdContext, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ work = &iocomplete_work;
++ break;
++ //case WORK_ITEM_CARD_DETECT:
++ //work = &carddetect_work;
++ // break;
++ case WORK_ITEM_SDIO_IRQ:
++ work = &sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_PENDING;
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++}
++
++#if 0
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++ HCD_EVENT event;
++
++ event = EVENT_HCD_NOP;
++
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("+ SDIO PXA255 Card Detect Work Item \n"));
++
++ if (!pHcdContext->CardInserted) {
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("Delaying to debounce card... \n"));
++ /* sleep for slot debounce if there is no card */
++ msleep(PXA_SLOT_DEBOUNCE_MS);
++ }
++
++ if (GetGpioPinLevel(pHcdContext,SDIO_CARD_INSERT_GPIO) == CARD_INSERT_POLARITY) {
++ /* doesn't work on gumstix , we can only detect removal */
++ if (!pHcdContext->CardInserted) {
++ pHcdContext->CardInserted = TRUE;
++ event = EVENT_HCD_ATTACH;
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, (" Card Inserted! \n"));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Card detect interrupt , already inserted card! \n"));
++ }
++ } else {
++ if (pHcdContext->CardInserted) {
++ event = EVENT_HCD_DETACH;
++ pHcdContext->CardInserted = FALSE;
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, (" Card Removed! \n"));
++ /* requeue the CD timer to start polling again*/
++ QueueCDTimer(pHcdContext);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Card detect interrupt , already removed card! \n"));
++ }
++ }
++
++ if (event != EVENT_HCD_NOP) {
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, event);
++ }
++
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("- SDIO PXA255 Card Detect Work Item \n"));
++}
++#endif
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255: hcd_sdioirq_wqueue_handler \n"));
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++}
++
++
++/* SDIO interrupt request */
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r)
++{
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255 SDIO IRQ \n"));
++
++ /* check gpio pin for assertion */
++ if (GetGpioPinLevel((PSDHCD_DRIVER_CONTEXT)context,SDIO_IRQ_GPIO) == SDIO_IRQ_POLARITY) {
++ /* disable IRQ */
++ EnableDisableSDIOIrq((PSDHCD_DRIVER_CONTEXT)context, FALSE);
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255 SDIO IRQ Asserted.. Queueing Work Item \n"));
++ /* queue the work item to notify the bus driver*/
++ if (!SDIO_SUCCESS(QueueEventResponse((PSDHCD_DRIVER_CONTEXT)context, WORK_ITEM_SDIO_IRQ))) {
++ /* failed */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 Local HCD: HcdInterrupt - queue event failed\n"));
++ }
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255 SDIO IRQ Asserted.. Queued Work Item \n"));
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++
++/*
++ * AckSDIOIrq - acknowledge SDIO interrupt
++*/
++SDIO_STATUS AckSDIOIrq(PSDHCD_DRIVER_CONTEXT pHcdContext)
++{
++ ULONG flags;
++
++ /* block the SDIO-IRQ handler from running */
++ spin_lock_irqsave(&pHcdContext->Device.Lock,flags);
++ /* re-enable edge detection */
++ EnableDisableSDIOIrq(pHcdContext, TRUE);
++ /* delay enough so that we can sample a level interrupt if it's already
++ * asserted */
++ udelay(2);
++
++ if (GetGpioPinLevel(pHcdContext,SDIO_IRQ_GPIO) == SDIO_IRQ_POLARITY) {
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255: pending int during Ack, issuing event \n"));
++ /* disable SDIO irq detection */
++ EnableDisableSDIOIrq(pHcdContext, FALSE);
++ spin_unlock_irqrestore(&pHcdContext->Device.Lock,flags);
++ /* queue work item to process another interrupt */
++ return QueueEventResponse(pHcdContext, WORK_ITEM_SDIO_IRQ);
++ }
++ /* let the normal GPIO edge detect take over */
++ spin_unlock_irqrestore(&pHcdContext->Device.Lock,flags);
++ return SDIO_STATUS_SUCCESS;
++}
++
++void ModifyCSForSPIIntDetection(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable)
++{
++ if (Enable) {
++ /* set pin level low to keep CS0 line low all the time, this is required
++ * for some cards to assert their SDIO interrupt line , set the pin register low
++ * before switching functions so that it does not glitch*/
++ WRITE_GPIO_REG(pHcdContext,GPIO_GPCR0,GPIO_bit(GPIO8_MMCCS0));
++ /* set GPIO8 for output mode, ALTFN 0, general purpose I/O */
++ pxa_gpio_mode(GPIO8_MMCCS0 | GPIO_OUT);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 SPI Mode - CS0 driven low for interrupt detect \n"));
++ } else {
++ /* switch mode back to normal CS0 operation */
++ pxa_gpio_mode(GPIO8_MMCCS0_MD);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 SPI Mode - normal CS0 operation \n"));
++ }
++}
++
++/*
++ * EnableDisableSDIOIrq - enable or disable the interrupt
++*/
++SDIO_STATUS EnableDisableSDIOIrq(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable)
++{
++ if (Enable) {
++ if (set_irq_type(pHcdContext->Device.SDIOInterrupt, IRQT_FALLING) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - failed to enable SDIO IRQ edge detect \n"));
++ return SDIO_STATUS_DEVICE_ERROR;
++ }
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255 - SDIO IRQ Detection Enabled!\n"));
++ } else {
++ /* to mask the GPIO PXA interrupt we clear the falling edge bit */
++ if (set_irq_type(pHcdContext->Device.SDIOInterrupt, 0) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA255 - failed clear SDIO IRQ edge detect \n"));
++ return SDIO_STATUS_DEVICE_ERROR;
++ }
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA255 - SDIO IRQ Detection Disabled!\n"));
++
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * module init
++*/
++static int __init sdio_local_hcd_init(void) {
++ SDIO_STATUS status;
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO PXA255 Local HCD: loaded\n"));
++
++ status = SDIO_BusAddOSDevice(&HcdContext.Device.Dma,
++ &HcdContext.Device.HcdDriver,
++ &HcdContext.Device.HcdDevice);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA255 Local HCD: sdio_local_hcd_init exit\n"));
++ return SDIOErrorToOSError(status);
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_local_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO PXA255 Local HCD: unloaded\n"));
++ SDIO_BusRemoveOSDevice(&HcdContext.Device.HcdDriver, &HcdContext.Device.HcdDevice);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PXA255 Local HCD: leave sdio_local_hcd_cleanup\n"));
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_local_hcd_init);
++module_exit(sdio_local_hcd_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_pxa255hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa255/sdio_pxa255hcd.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,227 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_pxa255hcd.h
++
++ at abstract: include file for PX255 local bus host controller, OS independent code
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_PXA255HCD_H___
++#define __SDIO_PXA255HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++
++enum PXA_TRACE_ENUM {
++ PXA_TRACE_CARD_INSERT = 10,
++ PXA_TRACE_SDIO_INT = 11,
++ PXA_TRACE_DATA,
++ PXA_TRACE_REQUESTS,
++ PXA_TRACE_CONFIG,
++ PXA_TRACE_MMC_INT,
++ PXA_TRACE_LAST
++};
++
++#define SDIO_IRQ_POLARITY FALSE
++
++//default device location
++#define PXA_MMC_CONTROLLER_BASE_ADDRESS 0x41100000
++#define PXA_MMC_CONTROLLER_ADDRESS_LENGTH 0x44
++#define PXA_GPIO_PIN_LVL_REGS_BASE 0x40e00000
++#define PXA_GPIO_PIN_LVL_REGS_LENGTH 0x72
++#define SDIO_BD_MAX_SLOTS 1
++#define SDIO_PXA_MAX_BYTES_PER_BLOCK 1023
++#define SDIO_PXA_MAX_BLOCKS 0xFFFF
++#define SPI_PXA_MAX_BLOCKS 1 /* SPI mode only supports single block */
++#define SPI_PXA_MAX_BYTES_PER_BLOCK 1023
++#define SDMMC_RESP_TIMEOUT_CLOCKS 64
++#define SDMMC_DATA_TIMEOUT_CLOCKS 0xFFFF
++
++#define MMC_MAX_RXFIFO 32
++#define MMC_MAX_TXFIFO 32
++/* register definitions */
++#define GPIO_GPLR0 0x00
++#define GPIO_GPLR1 0x04
++#define GPIO_GPLR2 0x08
++#define GPIO_GPDR0 0x0C
++#define GPIO_GPDR1 0x10
++#define GPIO_GPDR2 0x14
++
++#define GPIO_GPSR0 0x18
++#define GPIO_GPSR1 0x1C
++#define GPIO_GPSR2 0x20
++#define GPIO_GPCR0 0x24
++#define GPIO_GPCR1 0x28
++#define GPIO_GPCR2 0x2C
++#define GPIO_GRER0 0x30
++#define GPIO_GRER1 0x34
++#define GPIO_GFER0 0x3c
++#define GPIO_GFER1 0x40
++/* clock control */
++#define MMC_STRPCL_REG 0x00
++#define MMC_CLOCK_START 0x02
++#define MMC_CLOCK_STOP 0x01
++/* mmc status */
++#define MMC_STAT_REG 0x04
++#define MMC_STAT_DATA_DONE (1 << 11)
++#define MMC_STAT_PRG_DONE (1 << 12)
++#define MMC_STAT_END_CMD (1 << 13)
++#define MMC_STAT_CLK_ON (1 << 8)
++#define MMC_STAT_RCV_FULL (1 << 7)
++#define MMC_STAT_XMIT_EMPTY (1 << 6)
++#define MMC_STAT_RESP_CRC_ERR (1 << 5)
++#define MMC_STAT_SPI_RDTKN_ERR (1 << 4)
++#define MMC_STAT_RDDAT_CRC_ERR (1 << 3)
++#define MMC_STAT_WR_ERROR (1 << 2)
++#define MMC_STAT_RESP_TIMEOUT (1 << 1)
++#define MMC_STAT_READ_TIMEOUT (1 << 0)
++#define MMC_STAT_ERRORS 0x0000003F
++#define MMC_RESP_ERRORS (MMC_STAT_RESP_CRC_ERR | MMC_STAT_RESP_TIMEOUT)
++#define MMC_STAT_RD_ERRORS (MMC_STAT_RDDAT_CRC_ERR | MMC_STAT_READ_TIMEOUT)
++/* clock rate */
++#define MMC_CLKRT_REG 0x08
++/* SPI control */
++#define MMC_SPI_REG 0x0c
++#define MMC_SPI_SEL_CS0 (1 << 3)
++#define MMC_SPI_CS_ENABLE (1 << 2)
++#define MMC_SPI_CRC_ENABLE (1 << 1)
++#define MMC_SPI_ENABLE (1 << 0)
++#define SPI_ENABLE_WITH_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_CRC_ENABLE | MMC_SPI_SEL_CS0)
++#define SPI_ENABLE_NO_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_SEL_CS0)
++/* command/data control */
++#define MMC_CMDAT_REG 0x10
++#define MMC_CMDAT_DMA_ENABEL (1 << 7)
++#define MMC_CMDAT_80_CLOCKS (1 << 6)
++#define MMC_CMDAT_RES_BUSY (1 << 5)
++#define MMC_CMDDAT_STREAM (1 << 4)
++#define MMC_CMDDAT_DATA_WR (1 << 3)
++#define MMC_CMDDAT_DATA_EN (1 << 2)
++#define MMC_CMDDAT_RES_NONE 0x00
++#define MMC_CMDDAT_RES_R1_R4_R5 0x01
++#define MMC_CMDDAT_RES_R2 0x02
++#define MMC_CMDDAT_RES_R3 0x03
++/* response timeout control */
++#define MMC_RESTO_REG 0x14
++#define MMC_RESTO_MASK 0x0000007F
++/* read data timeout */
++#define MMC_RDTO_REG 0x18
++#define MMC_RDTO_MASK 0x0000FFFF
++/* block length */
++#define MMC_BLKLEN_REG 0x1c
++#define MMC_BLKLEN_MASK 0x003FF
++/* number of blocks */
++#define MMC_NOB_REG_REG 0x20
++#define MMC_NOB_MASK 0x0000FFFF
++/* partial buffer */
++#define MMC_PRTBUF_REG 0x24
++#define MMC_PRTBUF_PARTIAL (1 << 0)
++/* interrupt mask register */
++#define MMC_I_MASK_REG 0x28
++#define MMC_MASK_TXFIFO_WR (1 << 6)
++#define MMC_MASK_RXFIFO_RD (1 << 5)
++#define MMC_MASK_CLK_OFF (1 << 4)
++#define MMC_MASK_STOP_CMD (1 << 3)
++#define MMC_MASK_END_CMD (1 << 2)
++#define MMC_MASK_PRG_DONE (1 << 1)
++#define MMC_MASK_DATA_TRANS (1 << 0)
++#define MMC_MASK_ALL_INTS 0x0000007F
++/* interrupt pending */
++#define MMC_I_REG_REG 0x2c
++#define MMC_INT_TXFIFO_WR (1 << 6)
++#define MMC_INT_RXFIFO_RD (1 << 5)
++#define MMC_INT_CLK_OFF (1 << 4)
++#define MMC_INT_STOP_CMD (1 << 3)
++#define MMC_INT_END_CMD (1 << 2)
++#define MMC_INT_PRG_DONE (1 << 1)
++#define MMC_INT_DATA_TRANS (1 << 0)
++/* command register */
++#define MMC_CMD_REG 0x30
++/* argument high */
++#define MMC_ARGH_REG 0x34
++/* argument low */
++#define MMC_ARGL_REG 0x38
++/* response fifo */
++#define MMC_RES_REG 0x3c
++#define SD_DEFAULT_RESPONSE_BYTES 6
++#define SD_R2_RESPONSE_BYTES 16
++/* RX Fifo */
++#define MMC_RXFIFO_REG 0x40
++/* TX Fifo */
++#define MMC_TXFIFO_REG 0x44
++
++#define MMC_MAX_CLOCK_ENTRIES 7
++
++typedef struct _MMC_CLOCK_TBL_ENTRY {
++ SD_BUSCLOCK_RATE ClockRate; /* rate in */
++ UINT8 Divisor;
++}MMC_CLOCK_TBL_ENTRY;
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDHCD Hcd; /* HCD description for bus driver */
++ SDHCD_DEVICE Device; /* the single device's info */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel;
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++BOOL HcdMMCInterrupt(PSDHCD_DRIVER_CONTEXT pHcdContext);
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHcdContext, INT WorkItemID);
++BOOL GetGpioPinLevel(PSDHCD_DRIVER_CONTEXT pHcdContext, INT Pin);
++
++SDIO_STATUS EnableDisableSDIOIrq(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable);
++SDIO_STATUS AckSDIOIrq(PSDHCD_DRIVER_CONTEXT pHcdContext);
++void ModifyCSForSPIIntDetection(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable);
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++#define WORK_ITEM_CD_POLL 3
++
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++#endif /* __SDIO_PXA255HCD_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/pxa270/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa270/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO pxa270 host controller
++#
++obj-m += sdio_pxa270hcd.o
++sdio_pxa270hcd-objs := sdio_hcd.o sdio_hcd_os.o
+Index: linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1087 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd.c
++
++ at abstract: PXA270 Local Bus SDIO Host Controller Driver
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include "sdio_pxa270hcd.h"
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++void DMATransferComplete(PVOID pContext, SDIO_STATUS Status, BOOL FromIsr);
++
++#define POLL_TIMEOUT 10000000
++
++#define WAIT_FOR_MMC(pHct,pCancel,DoneMask,Error,ErrorMask,Status,Timeout) \
++{ \
++ INT _timeoutCnt = (Timeout); \
++ while(!*(pCancel) && (_timeoutCnt > 0) && \
++ !(READ_MMC_REG((pHct), MMC_STAT_REG) & (DoneMask)) && \
++ !(*(Error) = READ_MMC_REG((pHct), MMC_STAT_REG) & (ErrorMask))){_timeoutCnt--;} \
++ *(Error) = READ_MMC_REG((pHct), MMC_STAT_REG) & (ErrorMask); \
++ if (0 == _timeoutCnt) {(Status) = SDIO_STATUS_DEVICE_ERROR; DBG_ASSERT(FALSE);} \
++}
++
++MMC_CLOCK_TBL_ENTRY MMCClockDivisorTable[MMC_MAX_CLOCK_ENTRIES] =
++{
++ {19500000,0x00}, /* must be in decending order */
++ {9750000,0x01},
++ {4880000,0x02},
++ {2440000,0x03},
++ {1220000,0x04},
++ {609000,0x05},
++ {304000,0x06}
++};
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pHct - host context
++ pReq - the request
++ Output:
++ Return: returns status
++ Notes: This function returns SDIO_STATUS_SUCCESS for SD mode. In SPI mode, all cards return
++ response tokens regardless of whether the command is supported or not. In SD, the response times
++ times-out and we would never reach here. In SPI mode we query the bus driver to check the SPI
++ response and return an appropriate error status to "simulate" timeouts.
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS GetResponseData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT wordCount;
++ INT byteCount;
++ UINT16 readBuffer[8];
++ UINT16 *pBuf;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ /* handle SPI oddities */
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_RESP_R2:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ /* this is the special SPI R2 and SPI SDIO R5 responses */
++ byteCount = 2;
++ wordCount = 1;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ /* SD, MMC, SDIO OCR reading */
++ byteCount = 5;
++ wordCount = 3;
++ break;
++ default:
++ byteCount = 1;
++ wordCount = 1;
++ break;
++ }
++ } else {
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES;
++ }
++ wordCount = byteCount / 2;
++ }
++
++ /* start the buffer at the tail and work backwards since responses are sent MSB first
++ and shifted into the FIFO */
++ pBuf = &readBuffer[(wordCount - 1)];
++ while (wordCount) {
++ *pBuf = (UINT16)READ_MMC_REG(pHct, MMC_RES_REG);
++ pBuf--;
++ wordCount--;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ switch (byteCount) {
++ case 1:
++ /* the single response byte is stuck in the MSB */
++ pReq->Response[0] = readBuffer[0] >> 8;
++ break;
++ case 2:
++ /* extended status token , shifted in last */
++ pReq->Response[0] = (UINT8)readBuffer[0];
++ /* response token shifted in first (in the high byte) */
++ pReq->Response[1] = (UINT8)(readBuffer[0] >> 8);
++ break;
++ case 5:
++ /* offset the read buffer by one byte since we read WORDs from fifo */
++ memcpy(&pReq->Response[0],((PUINT8)readBuffer) + 1, 5);
++ break;
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_REQUESTS) {
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO PXA270 - Response Dump (SPI)");
++ }
++ /* the bus driver will determine the appropriate status based on the SPI
++ * token received, the bus driver may return a time-out status for tokens indicating an
++ * illegal command */
++ return SDIO_CheckResponse(&pHct->Hcd, pReq, SDHCD_CHECK_SPI_TOKEN);
++ }
++
++ /* handle normal SD/MMC responses */
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ pReq->Response[0] = 0x00;
++ /* adjust for lack of CRC */
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++ } else {
++ memcpy(pReq->Response,readBuffer,byteCount);
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_REQUESTS) {
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = 17;
++ }
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO PXA270 - Response Dump");
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++void DumpCurrentRequestInfo(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ if (pHct->Hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - Current Request Command:%d, ARG:0x%8.8X\n",
++ pHct->Hcd.pCurrentRequest->Command, pHct->Hcd.pCurrentRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pHct->Hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pHct->Hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ pHct->Hcd.pCurrentRequest->BlockCount,
++ pHct->Hcd.pCurrentRequest->BlockLen,
++ pHct->Hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateMMCError - check for an MMC error
++ Input: MMCStatus - MMC status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateMMCError(PSDHCD_DRIVER_CONTEXT pHct,UINT32 MMCStatus)
++{
++
++ if (MMCStatus & MMC_STAT_RESP_CRC_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - RESP CRC ERROR \n"));
++ return SDIO_STATUS_BUS_RESP_CRC_ERR;
++ } else if (MMCStatus & MMC_STAT_SPI_RDTKN_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - SPI RDTKN ERROR \n"));
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ } else if (MMCStatus & MMC_STAT_RDDAT_CRC_ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - READDATA CRC ERROR \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_READ_CRC_ERR;
++ } else if (MMCStatus & MMC_STAT_WR_ERROR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - WRITE ERROR \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_WRITE_ERROR;
++ } else if (MMCStatus & MMC_STAT_RESP_TIMEOUT) {
++ if (pHct->CardInserted) {
++ /* hide error if we are polling an empty slot */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - RESPONSE TIMEOUT \n"));
++ }
++ return SDIO_STATUS_BUS_RESP_TIMEOUT;
++ } else if (MMCStatus & MMC_STAT_READ_TIMEOUT) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - READ TIMEOUT \n"));
++ DumpCurrentRequestInfo(pHct);
++ return SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ return SDIO_STATUS_DEVICE_ERROR;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - MMC clock control
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_DRIVER_CONTEXT pHct, BOOL On)
++{
++
++ if (On) {
++ WRITE_MMC_REG(pHct, MMC_STRPCL_REG, MMC_CLOCK_START);
++ } else {
++ if (READ_MMC_REG(pHct, MMC_STAT_REG) & MMC_STAT_CLK_ON) {
++ WRITE_MMC_REG(pHct, MMC_STRPCL_REG, MMC_CLOCK_STOP);
++ /* wait for clock to stop */
++ while (READ_MMC_REG(pHct, MMC_STAT_REG) & MMC_STAT_CLK_ON);
++ }
++ }
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pHcd - HCD object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_DRIVER_CONTEXT pHct, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int i;
++ int clockIndex;
++
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA270 - SetMode\n"));
++
++ /* set clock index to the end, the table is sorted this way */
++ clockIndex = MMC_MAX_CLOCK_ENTRIES - 1;
++ pMode->ActualClockRate = MMCClockDivisorTable[clockIndex].ClockRate;
++ for (i = 0; i < MMC_MAX_CLOCK_ENTRIES; i++) {
++ if (pMode->ClockRate >= MMCClockDivisorTable[i].ClockRate) {
++ pMode->ActualClockRate = MMCClockDivisorTable[i].ClockRate;
++ clockIndex = i;
++ break;
++ }
++ }
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_SPI:
++ /* nothing to really do here */
++ if (pMode->BusModeFlags & SDCONFIG_BUS_MODE_SPI_NO_CRC) {
++ /* caller wants all SPI transactions without CRC */
++ } else {
++ /* caller wants all SPI transaction to use CRC */
++ }
++ break;
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA270 - 1-bit bus width\n"));
++ pHct->SD4Bit = FALSE;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA270 - 4-bit bus width\n"));
++ pHct->SD4Bit = TRUE;
++ break;
++ default:
++ break;
++ }
++
++ /* set the clock divisor */
++ WRITE_MMC_REG(pHct, MMC_CLKRT_REG, MMCClockDivisorTable[clockIndex].Divisor);
++
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA270 - MMCClock: %d Khz\n", pMode->ActualClockRate));
++
++}
++
++BOOL HcdTransferTxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++ volatile UINT32 *pFifo;
++ BOOL partial = FALSE;
++
++ pFifo = (volatile UINT32 *)((UINT32)GET_MMC_BASE(pHct) + MMC_TXFIFO_REG);
++ dataCopy = min(pReq->DataRemaining,(UINT32)MMC_MAX_TXFIFO);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* clear partial flag */
++ WRITE_MMC_REG(pHct,MMC_PRTBUF_REG,0);
++
++ if (dataCopy < MMC_MAX_TXFIFO) {
++ /* need to set partial flag after we load the fifos */
++ partial = TRUE;
++ }
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* copy to fifo */
++ while(dataCopy) {
++ _WRITE_BYTE_REG(pFifo,*pBuf);
++ dataCopy--;
++ pBuf++;
++ }
++
++ if (partial) {
++ /* partial buffer */
++ WRITE_MMC_REG(pHct,MMC_PRTBUF_REG,MMC_PRTBUF_PARTIAL);
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++ return TRUE;
++}
++
++void HcdTransferRxData(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq)
++{
++ INT dataCopy, thisCopy;
++ PUINT8 pBuf;
++ volatile UINT32 *pFifo;
++ pFifo = (volatile UINT32 *)((UINT32)GET_MMC_BASE(pHct) + MMC_RXFIFO_REG);
++ dataCopy = min(pReq->DataRemaining,(UINT32)MMC_MAX_RXFIFO);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ thisCopy = dataCopy;
++ /* copy from fifo */
++ while(dataCopy) {
++ (*pBuf) = _READ_BYTE_REG(pFifo);
++ dataCopy--;
++ pBuf++;
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++}
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ UINT32 HwErrors,
++ BOOL FromIsr)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 statValue = 0;
++ UINT32 errorMask = 0;
++
++ do {
++ if (HwErrors) {
++ status = TranslateMMCError(pHct,HwErrors);
++ if ((HwErrors & MMC_STAT_RESP_CRC_ERR) &&
++ (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2)) {
++ if (SDIO_SUCCESS(GetResponseData(pHct,pReq))) {
++ if (pReq->Response[15] & 0x80) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO PXA270 Bypass CRC error due to CRC hardware bug on R2 response..\n"));
++ //SDLIB_PrintBuffer(pReq->Response,SD_R2_RESPONSE_BYTES,"SDIO PXA270 - R2 Response Dump");
++ /* 270 controller has a bug where bit 127 of an R2 response is not
++ * taken into account when the CRC is calculated */
++ status = SDIO_STATUS_SUCCESS;
++ }
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 command failure: STAT:0x%X \n",HwErrors));
++ break;
++ }
++
++ } else if (pHct->Cancel) {
++ status = SDIO_STATUS_CANCELED;
++ break;
++ } else {
++ /* get the response data for the command */
++ status = GetResponseData(pHct,pReq);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 command success: STAT:0x%X \n",
++ READ_MMC_REG((pHct), MMC_STAT_REG)));
++
++ if (!IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ /* all done */
++ break;
++ }
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pHct->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (pHct->DmaType != PXA_DMA_NONE) {
++ /* start DMA */
++ status = SetUpPXADMA(pHct,
++ pReq,
++ DMATransferComplete,
++ pHct);
++ break;
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* for writes, we need to pre-load the TX FIFO */
++ if (HcdTransferTxData(pHct, pReq)) {
++ /* entire transfer fits inside the fifos */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) {
++ /* the requestor has provided us with a hint, we can poll for
++ * completion if it fits in the fifo */
++ statValue = MMC_STAT_PRG_DONE;
++ errorMask = MMC_STAT_WR_ERROR;
++ } else {
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS,FromIsr);
++ }
++ } else {
++ /* expecting a TX empty interrupt */
++ UnmaskMMCIrq(pHct, MMC_MASK_TXFIFO_WR,FromIsr);
++ }
++ } else {
++ if (pReq->DataRemaining <= MMC_MAX_RXFIFO) {
++ if (pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) {
++ /* the requestor has provided us with a hint, we can poll for
++ * completion since this is less than a FIFOs worth */
++ statValue = MMC_STAT_DATA_DONE;
++ errorMask = MMC_STAT_RD_ERRORS;
++ } else {
++ /* just wait for data transfer done, we won't get fifo full interrupts */
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS,FromIsr);
++ }
++ } else {
++ /* turn on fifo full interrupts */
++ UnmaskMMCIrq(pHct, MMC_MASK_RXFIFO_RD,FromIsr);
++ }
++ }
++
++ if (0 == statValue) {
++ /* return pending, if this is not a short transfer */
++ status = SDIO_STATUS_PENDING;
++ } else {
++ /* this will be polled in-line */
++ status = SDIO_STATUS_SUCCESS;
++ }
++ } while (FALSE);
++
++ if (statValue != 0) {
++ UINT32 temp = 0;
++
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Short %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ {
++ volatile BOOL *pCancel;
++ pCancel = (volatile BOOL *)&pHct->Cancel;
++
++ WAIT_FOR_MMC(pHct,pCancel,statValue,&temp,errorMask, status, POLL_TIMEOUT);
++ }
++
++ if (SDIO_SUCCESS(status)) {
++ if (temp) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 Short Transfer Failure: STAT:0x%X \n",temp));
++ status = TranslateMMCError(pHct,temp);
++ } else {
++ if (!IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* drain the FIFO on reads */
++ HcdTransferRxData(pHct,pReq);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ }
++ }
++ }
++
++ if (SDIO_STATUS_PENDING == status) {
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Pending %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ }
++ return status;
++}
++
++void DMATransferComplete(PVOID pContext, SDIO_STATUS Status, BOOL FromIsr)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pContext;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++ DBG_ASSERT(pReq != NULL);
++
++ DBG_PRINT(PXA_TRACE_DATA,
++ ("+SDIO PXA270 %s DMATransferComplete, Status:%d Req:0x%X \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",Status,(UINT32)pReq));
++
++ if (!SDIO_SUCCESS(Status)) {
++ /* if DMA failed, we need to complete the request here
++ * the SDIO controller ISR will not fire in this case */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 %s DMATransferComplete failed with status:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",Status));
++ pReq->Status = Status;
++ /* turn off interrupts and clock */
++ MaskMMCIrq(pHct,(MMC_MASK_ALL_INTS & (~MMC_MASK_SDIO_IRQ)),FromIsr);
++ if (!pHct->KeepClockOn) {
++ ClockStartStop(pHct, CLOCK_OFF);
++ }
++ /* complete the request */
++ CompleteRequestSyncDMA(pHct,pReq,FromIsr);
++ } else {
++ if (pHct->PartialTxFIFO) {
++ /* the DMA transfer completed, but the TX fifo was not completely
++ * filled, we need to set the partial flag so that the controller can
++ * flip the buffer filled by DMA and send it out */
++ WRITE_MMC_REG(pHct,MMC_PRTBUF_REG,MMC_PRTBUF_PARTIAL);
++ }
++ /* now wait for data trans complete */
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS,FromIsr);
++ }
++
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Waiting for TRANS_DONE : (IMASK:0x%X) (IREG:0x%X)\n",
++ READ_MMC_REG(pHct, MMC_I_MASK_REG) , READ_MMC_REG((pHct), MMC_I_REG_REG)));
++ DBG_PRINT(PXA_TRACE_DATA, ("-SDIO PXA270 DMATransferComplete\n"));
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ pReq - request to issue
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT32 temp = 0;
++ PSDREQUEST pReq;
++
++ /* make sure clock is off before we do anything */
++ ClockStartStop(pHct, CLOCK_OFF);
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ /* reset current DMA type flag */
++ pHct->DmaType = PXA_DMA_NONE;
++
++ do {
++
++ if (IS_SDHCD_SHUTTING_DOWN(pHct)) {
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* check for CMD0 */
++ if (pReq->Command == 0x00) {
++ /* this command must always have a CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_WITH_CRC);
++ } else {
++ /* for all other SPI-mode commands, check bus mode */
++ if (IS_HCD_BUS_MODE_SPI_NO_CRC(pHcd)) {
++ /* not running with CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_NO_CRC);
++ } else {
++ /* running with CRC */
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ SPI_ENABLE_WITH_CRC);
++ }
++ }
++ }
++
++ if (pHct->SD4Bit) {
++ temp |= MMC_CMDAT_SD_4DAT;
++ }
++
++ if (pHct->SDIrqData) {
++ temp |= MMC_CMDAT_SDIO_IRQ_DETECT;
++ }
++
++ if (pHct->IssueInitClocks) {
++ pHct->IssueInitClocks = FALSE;
++ temp |= MMC_CMDAT_80_CLOCKS;
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_MMC_R4:
++ case SDREQ_FLAGS_RESP_MMC_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ temp |= MMC_CMDDAT_RES_R1_R4_R5;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp |= (MMC_CMDDAT_RES_R1_R4_R5 | MMC_CMDAT_RES_BUSY);
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp |= MMC_CMDDAT_RES_R2;
++ break;
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* sdio R5s in SPI mode is really an R2 in SPI mode */
++ temp |= MMC_CMDDAT_RES_R2;
++ } else {
++ /* in SD mode, its an R1 */
++ temp |= MMC_CMDDAT_RES_R1_R4_R5;
++ }
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp |= MMC_CMDDAT_RES_R3;
++ break;
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ temp |= MMC_CMDDAT_DATA_EN;
++ /* set block length */
++ WRITE_MMC_REG(pHct, MMC_BLKLEN_REG, pReq->BlockLen);
++ WRITE_MMC_REG(pHct, MMC_NOB_REG_REG, pReq->BlockCount);
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 %s Data Transfer, Blocks:%d, BlockLen:%d, Total:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen, pReq->DataRemaining));
++ /* check scatter gather DMA */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ DBG_ASSERT(pHcd->pDmaDescription != NULL);
++ DBG_PRINT(PXA_TRACE_DATA, (" : Data Transfer using Scatter Gather DMA: %d Descriptors\n",
++ pReq->DescriptorCount));
++ pHct->DmaType = PXA_DMA_SCATTER_GATHER;
++ pReq->pHcdContext = NULL;
++ } else {
++ /* non-scatter gather */
++ if (pHct->DmaCapable) {
++ /* the PXA270 FIFOs are a bit puny, so we use common buffer DMA (if available)
++ * to transfer the buffer */
++ if (pReq->DataRemaining > PXA_DMA_THRESHOLD) {
++ pHct->DmaType = PXA_DMA_COMMON_BUFFER;
++ DBG_PRINT(PXA_TRACE_DATA, (" : Data Transfer will use common buffer DMA\n"));
++ }
++ } else {
++ DBG_PRINT(PXA_TRACE_DATA, (" : Data Transfer will use PIO Mode \n"));
++ }
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ }
++
++ pHct->PartialTxFIFO = FALSE;
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ temp |= MMC_CMDDAT_DATA_WR;
++ if (pReq->DataRemaining & PXA_TX_PARTIAL_FIFO_MASK) {
++ /* let DMA completion know that this will result in a partial FIFO
++ * fill */
++ pHct->PartialTxFIFO = TRUE;
++ }
++ }
++
++ if (pHct->DmaType != PXA_DMA_NONE) {
++ /* enable DMA */
++ temp |= MMC_CMDAT_DMA_ENABLE;
++ }
++ }
++
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++ WRITE_MMC_REG(pHct, MMC_CMD_REG, pReq->Command);
++ WRITE_MMC_REG(pHct, MMC_ARGH_REG, (pReq->Argument >> 16));
++ WRITE_MMC_REG(pHct, MMC_ARGL_REG, (pReq->Argument & 0xFFFF));
++ WRITE_MMC_REG(pHct, MMC_CMDAT_REG, temp);
++
++ if (SDHCD_GET_OPER_CLOCK(pHcd) < HCD_COMMAND_MIN_POLLING_CLOCK) {
++ /* clock rate is very low, need to use interrupts here */
++ UnmaskMMCIrq(pHct, MMC_MASK_END_CMD, FALSE);
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ status = SDIO_STATUS_PENDING;
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 using interrupt for command done.. \n"));
++ } else {
++ /* start the clock */
++ ClockStartStop(pHct, CLOCK_ON);
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 waiting for command done.. \n"));
++ temp = 0;
++ {
++ volatile BOOL *pCancel;
++ pCancel = (volatile BOOL *)&pHct->Cancel;
++ /* this macro polls */
++ WAIT_FOR_MMC(pHct,pCancel,MMC_STAT_END_CMD,&temp,MMC_RESP_ERRORS, status, POLL_TIMEOUT);
++
++ }
++ if (SDIO_SUCCESS(status)) {
++ /* process the command completion */
++ status = ProcessCommandDone(pHct,pReq,temp,FALSE);
++ }
++ }
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++
++ if (!pHct->KeepClockOn) {
++ ClockStartStop(pHct, CLOCK_OFF);
++ }
++
++ pReq->Status = status;
++ pHct->Cancel = FALSE;
++
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags) || (pHct->DmaType != PXA_DMA_NONE)) {
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ if (PXA_DMA_NONE == pHct->DmaType) {
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ } else {
++ CompleteRequestSyncDMA(pHct,pReq,FALSE);
++ }
++ return SDIO_STATUS_PENDING;
++ }
++ /* complete the request */
++ DBG_PRINT(PXA_TRACE_REQUESTS, ("SDIO PXA270 Command Done - inline, status:%d \n", status));
++ /* fall through and return the non-pending status */
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)pHcd->pContext;
++ UINT16 command;
++
++ command = GET_SDCONFIG_CMD(pConfig);
++
++ if (IS_SDHCD_SHUTTING_DOWN(pHct)) {
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (command){
++ case SDCONFIG_GET_WP:
++ if (IsSlotWPSet(pHct)) {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 1;
++ } else {
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) = 0;
++ }
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ pHct->IssueInitClocks = TRUE;
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ /* enable */
++ UnmaskMMCIrq(pHct,MMC_MASK_SDIO_IRQ,FALSE);
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* turn on chip select */
++ ModifyCSForSPIIntDetection(pHct, TRUE);
++ } else {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++ /* get detect mode */
++ irqModeFlags = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ pHct->SDIrqData = TRUE;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270: 4 Bit IRQ mode \r\n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pHct->KeepClockOn = TRUE;
++ if (irqModeFlags & IRQ_DETECT_MULTI_BLK) {
++ // interrupt between blocks
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270: IRQ between blocks, detect enabled \r\n"));
++
++ } else {
++ // no interrupts between blocks
++ }
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270: 4 Bit IRQ mode \r\n"));
++ /* in 1 bit mode, the clock can be left off */
++ pHct->KeepClockOn = FALSE;
++ }
++ }
++ } else {
++ /* disable */
++ MaskMMCIrq(pHct,MMC_MASK_SDIO_IRQ,FALSE);
++ if (IS_HCD_BUS_MODE_SPI(pHcd)) {
++ /* switch CS */
++ ModifyCSForSPIIntDetection(pHct, FALSE);
++ }
++ pHct->KeepClockOn = FALSE;
++ pHct->SDIrqData = FALSE;
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ UnmaskMMCIrq(pHct,MMC_MASK_SDIO_IRQ,FALSE);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pHct, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ /* TODO, the slot just connects VCC straight to the slot nothing to adjust here */
++ DBG_PRINT(PXA_TRACE_CONFIG, ("SDIO PXA270 PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ *((CT_DEBUG_LEVEL *)pConfig->pData) = DBG_GET_DEBUG_LEVEL();
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_SET_DEBUG_LEVEL(*((CT_DEBUG_LEVEL *)pConfig->pData));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Local HCD: HcdConfig - bad command: 0x%X\n",command));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize MMC controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ /* turn off clock */
++ ClockStartStop(pHct, CLOCK_OFF);
++ /* init controller */
++ if (pHct->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Using SPI Mode\n"));
++ /* each HCD request will set up SPI mode with or without CRC protection */
++ }else if (pHct->Hcd.Attributes & SDHCD_ATTRIB_BUS_1BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Using Normal SD,SDIO Mode\n"));
++ WRITE_MMC_REG(pHct,
++ MMC_SPI_REG,
++ 0x00);
++ }
++
++ WRITE_MMC_REG(pHct, MMC_RESTO_REG, SDMMC_RESP_TIMEOUT_CLOCKS);
++ WRITE_MMC_REG(pHct, MMC_RDTO_REG, SDMMC_DATA_TIMEOUT_CLOCKS);
++ MaskMMCIrq(pHct,MMC_MASK_ALL_INTS, FALSE);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate MMC controller
++ Input: pHct - HCD context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, MMC_MASK_ALL_INTS);
++ ClockStartStop(pHct, CLOCK_OFF);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdMMCInterrupt - process MMC controller interrupt
++ Input: pHct - HCD context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdMMCInterrupt(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ UINT32 ints,errors;
++ PSDREQUEST pReq;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("+SDIO PXA270 IMMC Int handler \n"));
++
++ ints = READ_MMC_REG(pHct, MMC_I_REG_REG);
++
++ if (!ints) {
++ DBG_PRINT(SDDBG_ERROR, ("-SDIO PXA270 False Interrupt! \n"));
++ return FALSE;
++ }
++
++ errors = 0;
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++
++ while (1) {
++ ints = READ_MMC_REG(pHct, MMC_I_REG_REG);
++ /* mask out ones we don't care about */
++ ints &= ~(READ_MMC_REG(pHct, MMC_I_MASK_REG));
++
++ if (0 == ints) {
++ break;
++ }
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("SDIO PXA270 Ints:0x%X \n", ints));
++ /* read status */
++ errors = READ_MMC_REG(pHct, MMC_STAT_REG);
++
++ if (ints & MMC_INT_SDIO_IRQ) {
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA270 SDIO IRQ \n"));
++ /* mask off */
++ MaskMMCIrq(pHct,MMC_MASK_SDIO_IRQ,TRUE);
++ QueueEventResponse(pHct, WORK_ITEM_SDIO_IRQ);
++ }
++
++ if (NULL == pReq) {
++ /* might just be an SDIO irq */
++ break;
++ }
++
++ if (ints & MMC_INT_END_CMD) {
++ /* mask off end cmd */
++ MaskMMCIrq(pHct, MMC_MASK_END_CMD, TRUE);
++ /* only care about response errors */
++ errors &= MMC_RESP_ERRORS;
++ status = ProcessCommandDone(pHct,pReq,errors,TRUE);
++ if (status != SDIO_STATUS_PENDING) {
++ /* no data phase or the command failed, get out */
++ break;
++ }
++ /* ProcessCommandDone will turn on interrupts for data transfers */
++ continue;
++ }
++
++ /* if we get here, its a data transfer interrupt */
++
++ /* filter data errors */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ errors &= MMC_STAT_WR_ERROR;
++ } else {
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ errors &= (MMC_STAT_RD_ERRORS | MMC_STAT_SPI_RDTKN_ERR);
++ } else {
++ errors &= MMC_STAT_RD_ERRORS;
++ }
++ }
++
++ if (errors) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA- Data Transfer has errors: Stat:0x%X \n", errors));
++ /* set status based on error */
++ status = TranslateMMCError(pHct,errors);
++ break;
++ }
++
++ if (ints & MMC_INT_TXFIFO_WR) {
++ DBG_ASSERT(PXA_DMA_NONE == pHct->DmaType);
++ /* transfer data */
++ if (HcdTransferTxData(pHct, pReq)) {
++ MaskMMCIrq(pHct, MMC_MASK_TXFIFO_WR, TRUE);
++ /* transfer is complete, wait for done */
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS, TRUE);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 TX Fifo writes done. Waiting for TRANS_DONE \n"));
++ }
++ continue;
++ }
++
++ if (ints & MMC_INT_RXFIFO_RD) {
++ DBG_ASSERT(PXA_DMA_NONE == pHct->DmaType);
++ /* unload fifo */
++ HcdTransferRxData(pHct,pReq);
++ if (pReq->DataRemaining < MMC_MAX_RXFIFO) {
++ /* we're done or there is a partial FIFO left */
++ MaskMMCIrq(pHct, MMC_MASK_RXFIFO_RD, TRUE);
++ /* transfer is complete wait for CRC check*/
++ UnmaskMMCIrq(pHct, MMC_MASK_DATA_TRANS, TRUE);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 RX Waiting for TRANS_DONE \n"));
++ }
++ continue;
++ }
++
++ if (ints & MMC_INT_DATA_TRANS) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* data transfer done */
++ MaskMMCIrq(pHct, MMC_MASK_DATA_TRANS, TRUE);
++ /* now wait for program done signalling */
++ UnmaskMMCIrq(pHct, MMC_MASK_PRG_DONE, TRUE);
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Transfer done, Waiting for PRG_DONE \n"));
++ continue;
++ } else {
++ if (PXA_DMA_NONE == pHct->DmaType) {
++ if (pReq->DataRemaining) {
++ /* there was a partial FIFO, we need to drain it */
++ HcdTransferRxData(pHct,pReq);
++ /* this should drain it */
++ DBG_ASSERT(pReq->DataRemaining == 0);
++ }
++ }
++ /* if we get here without an error, we are done with the read
++ * data operation */
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 RX Transfer done \n"));
++ break;
++ }
++ }
++
++ if (ints & MMC_INT_PRG_DONE) {
++ /* if we get here without errors, we are done with the
++ * write data operation */
++ status = SDIO_STATUS_SUCCESS;
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Got TX PRG_DONE. \n"));
++ break;
++ }
++
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* set the status */
++ pReq->Status = status;
++ /* turn off interrupts and clock */
++ MaskMMCIrq(pHct,(MMC_MASK_ALL_INTS & (~MMC_MASK_SDIO_IRQ)),TRUE);
++ if (!pHct->KeepClockOn) {
++ ClockStartStop(pHct, CLOCK_OFF);
++ }
++
++ if ((DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_DATA_DUMP) && SDIO_SUCCESS(status) &&
++ IS_SDREQ_DATA_TRANS(pReq->Flags) && !IS_SDREQ_WRITE_DATA(pReq->Flags) &&
++ (pHct->DmaType != PXA_DMA_SCATTER_GATHER)) {
++ //SDLIB_PrintBuffer(pReq->pDataBuffer,(pReq->BlockLen*pReq->BlockCount),"SDIO PXA270 - RX DataDump");
++ }
++
++ if (PXA_DMA_NONE == pHct->DmaType) {
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++ } else {
++ if (!SDIO_SUCCESS(status)) {
++ SDCancelDMATransfer(pHct);
++ }
++ /* the request used DMA, we need to let the OS-specific code deal with DMA */
++ CompleteRequestSyncDMA(pHct,pReq,TRUE);
++
++ }
++ }
++
++ DBG_PRINT(PXA_TRACE_MMC_INT, ("-SDIO PXA270 IMMC Int handler \n"));
++ return TRUE;
++}
++
++
++
++
+Index: linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,150 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_linux.h
++
++ at abstract: include file for PXA270 local bus host controller, linux dependent code
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_LINUX_H___
++#define __SDIO_HCD_LINUX_H___
++
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++
++#include <asm/irq.h>
++
++#define SDIO_CARD_INSERT_GPIO 11 /* card insertion switch */
++//#define SDIO_CARD_INSERT_GPIO 29
++#define SDIO_CARD_WP_GPIO 22 /* write protect switch position */
++#define CARD_INSERT_POLARITY FALSE
++#define WP_POLARITY TRUE
++
++/* interrupt assignments */
++#define SDIO_PXA_CONTROLLER_IRQ IRQ_MMC
++#define SDIO_PXA_CARD_INSERT_IRQ IRQ_GPIO(SDIO_CARD_INSERT_GPIO)
++
++/* debounce delay for slot */
++#define PXA_SLOT_DEBOUNCE_MS 2000
++
++/* major number, zero indicates assign dynamically */
++#define SDIO_BD_MAJOR_INIT 0
++
++/* device base name */
++#define SDIO_BD_BASE "sdiobd"
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef void (*PDMA_TRANSFER_COMPLETION)(PVOID,SDIO_STATUS,BOOL);
++
++#define SDHCD_MAX_DEVICE_NAME 12
++
++#define IS_SDHCD_SHUTTING_DOWN(pC) ((pC)->Device.ShutDown)
++
++/* device data*/
++typedef struct _SDHCD_DEVICE {
++ OS_PNPDEVICE HcdDevice; /* the OS device for this HCD */
++ OS_PNPDRIVER HcdDriver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION Dma; /* driver DMA description */
++ POS_PNPDEVICE pBusDevice; /* our device registered with bus driver */
++ UINT MMCInterrupt; /* controller interrupt */
++ UINT CardInsertInterrupt; /* card insert interrupt */
++ UINT CardRemoveInterrupt; /* card remove interrupt */
++ UINT SDIOInterrupt; /* sdio interrupt interrupt */
++ UINT8 InitStateMask;
++ BOOL ShutDown;
++#define MMC_INTERRUPT_INIT 0x01
++#define CARD_DETECT_INSERT_INTERRUPT_INIT 0x02
++#define CARD_DETECT_REMOVE_INTERRUPT_INIT 0x04
++#define SDHC_REGISTERED 0x10
++#define SDHC_HW_INIT 0x20
++#define TIMER_INIT 0x40
++ SDHCD_MEMORY ControlRegs; /* memory addresses of device */
++ SDHCD_MEMORY GpioRegs; /* memory addresses of GPIO regs */
++ spinlock_t Lock; /* lock against the ISR */
++ BOOL StartUpCheck;
++ PDMA_TRANSFER_COMPLETION pDmaCompletion;
++ PVOID pContext;
++ PUINT32 pDmaDescriptorBuffer; /* buffer for descriptors */
++ DMA_ADDRESS DmaDescriptorPhys; /* physical address for descriptor buffer */
++ PUINT8 pDmaCommonBuffer; /* common buffer for DMA */
++ DMA_ADDRESS DmaCommonBufferPhys; /* physical address for common buffer */
++ INT DmaChannel;
++ BOOL DmaSgMapped;
++ INT LastRxCopy;
++}SDHCD_DEVICE, *PSDHCD_DEVICE;
++
++#define GET_MMC_BASE(pC)(pC)->Device.ControlRegs.pMapped
++#define READ_GPIO_REG(pC, OFFSET) \
++ _READ_DWORD_REG(((UINT32)(pC)->Device.GpioRegs.pMapped) + (OFFSET))
++#define WRITE_GPIO_REG(pC, OFFSET,VALUE) \
++ _WRITE_DWORD_REG(((UINT32)(pC)->Device.GpioRegs.pMapped) + (OFFSET),(VALUE))
++#define READ_MMC_REG(pC, OFFSET) \
++ _READ_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET))
++#define WRITE_MMC_REG(pC, OFFSET, VALUE) \
++ _WRITE_DWORD_REG(((UINT32)(pC)->Device.ControlRegs.pMapped) + (OFFSET),(VALUE))
++
++//#define ENABLE_TEST_PIN 1
++
++#ifdef ENABLE_TEST_PIN /* used for scope capture */
++#define TEST_PIN_GPIO GPIO59_LDD_1
++#define TEST_PIN_GPSR GPIO_GPSR1
++#define TEST_PIN_GPCR GPIO_GPCR1
++#define SET_TEST_PIN(pHct) { \
++ if (IS_HCD_BUS_MODE_SPI(&(pHct)->Hcd)) { \
++ WRITE_GPIO_REG((pHct),TEST_PIN_GPSR,GPIO_bit(TEST_PIN_GPIO)); \
++ } \
++}
++
++#define CLEAR_TEST_PIN(pHct) { \
++ if (IS_HCD_BUS_MODE_SPI(&(pHct)->Hcd)) { \
++ WRITE_GPIO_REG((pHct),TEST_PIN_GPCR,GPIO_bit(TEST_PIN_GPIO)); \
++ } \
++}
++#else
++#define SET_TEST_PIN(pHct)
++#define CLEAR_TEST_PIN(pHct)
++#endif
++/* prototypes */
++#endif /* __SDIO_HCD_LINUX_H___ */
+Index: linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_hcd_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1084 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Linux PXA270 Local Bus SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++
++#define DBG_DECLARE 7;
++#include <linux/sdio/ctsystem.h>
++
++#include "sdio_pxa270hcd.h"
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include <asm/arch/pxa-regs.h>
++#include <asm/arch/dma.h>
++#include <linux/dma-mapping.h>
++
++#ifdef CONFIG_MACH_SANDGATE2P
++#include <asm/arch/sandgate2p.h>
++#elif defined(CONFIG_MACH_SANDGATE2G)
++#include <asm/arch/sandgate2g.h>
++#elif defined(CONFIG_MACH_SANDGATE2)
++#include <asm/arch/sandgate2.h>
++#elif defined(CONFIG_MACH_MAINSTONE)
++#include <asm/arch/mainstone.h>
++#endif
++
++#define DESCRIPTION "SDIO PXA270 Local Bus HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++#if defined(CONFIG_MACH_SANDGATE2G)
++unsigned long sandgate2_bcr = 0x000003c0;
++#elif defined(CONFIG_MACH_MAINSTONE)
++unsigned long mainstone_bcr;
++#endif
++
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId);
++static void Remove(struct pnp_dev *pBusDevice);
++static SYSTEM_STATUS MapAddress(PSDHCD_MEMORY pMap, PTEXT pDescription);
++static void UnmapAddress(PSDHCD_MEMORY pMap);
++
++static irqreturn_t hcd_mmc_irq(int irq, void *context, struct pt_regs * r);
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++static void DmaCompletionCallBack(int dma, void *devid, struct pt_regs *regs);
++
++#define BASE_HCD_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | \
++ SDHCD_ATTRIB_BUS_4BIT)
++
++#define BASE_HCD_SPI_ATTRIBUTES SDHCD_ATTRIB_BUS_SPI
++
++#ifdef USE_CARD_DETECT_HW
++static void hcd_carddetect_wqueue_handler(void *context);
++static irqreturn_t hcd_card_detect_insert_irq(int irq, void *context, struct pt_regs * r);
++static irqreturn_t hcd_card_detect_remove_irq(int irq, void *context, struct pt_regs * r);
++static DECLARE_WORK(carddetect_work, hcd_carddetect_wqueue_handler, &HcdContext);
++#define DEFAULT_ATTRIBUTES BASE_HCD_ATTRIBUTES
++#define DEFAULT_SPI_ATTRIBUTES BASE_HCD_SPI_ATTRIBUTES
++#else
++#define DEFAULT_ATTRIBUTES (BASE_HCD_ATTRIBUTES | SDHCD_ATTRIB_SLOT_POLLING)
++#define DEFAULT_SPI_ATTRIBUTES (BASE_HCD_SPI_ATTRIBUTES | SDHCD_ATTRIB_SLOT_POLLING)
++#endif
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++
++UINT32 UseSpi = 0;
++module_param(UseSpi, int, 0644);
++MODULE_PARM_DESC(UseSpi, "PXA270 HCD use SPI Mode");
++
++UINT32 noDMA = 0;
++module_param(noDMA, int, 0644);
++MODULE_PARM_DESC(noDMA, "PXA270 HCD disable DMA");
++
++UINT32 max_blocks = SDIO_PXA_MAX_BLOCKS;
++module_param(max_blocks, int, 0644);
++MODULE_PARM_DESC(max_blocks, "PXA270 HCD max blocks per transfer");
++
++UINT32 max_bytes_per_block = SDIO_PXA_MAX_BYTES_PER_BLOCK;
++module_param(max_bytes_per_block, int, 0644);
++MODULE_PARM_DESC(max_bytes_per_block, "PXA270 HCD max bytes per block");
++
++UINT32 builtin_card = 0;
++module_param(builtin_card, int, 0644);
++MODULE_PARM_DESC(builtin_card, "SDIO card is built-in");
++
++UINT32 multiblock_irq = 0;
++module_param(multiblock_irq, int, 0644);
++MODULE_PARM_DESC(multiblock_irq, "Enable Multi-block IRQ detect");
++
++/* the driver context data */
++BOOL IsCardInserted(PSDHCD_DRIVER_CONTEXT pHct);
++
++#define MAX_DMA_DESCRIPTORS 64
++
++#define PXA_DESCRIPTOR_BUFFER_SIZE (MAX_DMA_DESCRIPTORS*4)
++
++
++#define PXA_MAX_BYTES_PER_DESCRIPTOR 8160 /* (8K - FIFO SIZE) */
++#define PXA_DMA_COMMON_BUFFER_SIZE PXA_MAX_BYTES_PER_DESCRIPTOR
++
++
++static SDHCD_DRIVER_CONTEXT HcdContext = {
++ .pDescription = DESCRIPTION,
++ .Hcd.pName = "sdio_pxa2270hcd",
++ .Hcd.Version = CT_SDIO_STACK_VERSION_CODE,
++ .Hcd.SlotNumber = 0,
++ .Hcd.Attributes = 0,
++ .Hcd.MaxBytesPerBlock = 0, /* see below */
++ .Hcd.MaxBlocksPerTrans = 0,
++ .Hcd.MaxSlotCurrent = 500, /* 1/2 amp */
++ .Hcd.SlotVoltageCaps = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V, /* 3.3V */
++ .Hcd.MaxClockRate = 19500000, /* 19.5 Mhz */
++ .Hcd.pContext = &HcdContext,
++ .Hcd.pRequest = HcdRequest,
++ .Hcd.pConfigure = HcdConfig,
++ .Device.HcdDevice.name = "sdio_pxa270_hcd",
++ .Device.HcdDriver.name = "sdio_pxa270_hcd",
++ .Device.HcdDriver.probe = Probe,
++ .Device.HcdDriver.remove = Remove,
++ .Device.Dma.Mask = 0xFFFFFFFF, /* any address */
++ .Device.Dma.Flags = SDDMA_DESCRIPTION_FLAG_DMA | SDDMA_DESCRIPTION_FLAG_SGDMA,
++ .Device.Dma.MaxBytesPerDescriptor = PXA_MAX_BYTES_PER_DESCRIPTOR,
++ .Device.Dma.AddressAlignment = 0x0, /* no illegal bits, buffers address can be on any boundary*/
++ .Device.Dma.LengthAlignment = 0x0, /* no illegal bits, buffer lengths can be any byte count */
++ .Device.Dma.MaxDescriptors = MAX_DMA_DESCRIPTORS, /* */
++};
++
++
++/* work queues */
++static DECLARE_WORK(iocomplete_work, hcd_iocomplete_wqueue_handler, &HcdContext);
++static DECLARE_WORK(sdioirq_work, hcd_sdioirq_wqueue_handler, &HcdContext);
++
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++static int Probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId)
++{
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status;
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Local HCD: Probe - probing for new device\n"));
++
++ pHcdContext->Device.pBusDevice = pBusDevice;
++ pHcdContext->Hcd.pDevice = &pBusDevice->dev;
++ pHcdContext->Hcd.pModule = THIS_MODULE;
++ pHcdContext->Device.MMCInterrupt = SDIO_PXA_CONTROLLER_IRQ;
++ pHcdContext->Device.CardInsertInterrupt = SDIO_PXA_CARD_INSERT_IRQ;
++ pHcdContext->Device.ControlRegs.Raw = PXA_MMC_CONTROLLER_BASE_ADDRESS;
++ pHcdContext->Device.ControlRegs.Length = PXA_MMC_CONTROLLER_ADDRESS_LENGTH;
++ pHcdContext->Device.GpioRegs.Raw = PXA_GPIO_PIN_LVL_REGS_BASE;
++ pHcdContext->Device.GpioRegs.Length = PXA_GPIO_PIN_LVL_REGS_LENGTH;
++
++ spin_lock_init(&pHcdContext->Device.Lock);
++
++ if (0 == UseSpi) {
++ pHcdContext->Hcd.Attributes = DEFAULT_ATTRIBUTES;
++ if (multiblock_irq) {
++ pHcdContext->Hcd.Attributes |= SDHCD_ATTRIB_MULTI_BLK_IRQ;
++ }
++ } else {
++ /* pHcdContext->Hcd.Attributes = DEFAULT_SPI_ATTRIBUTES; */
++ /* not tested */
++ DBG_ASSERT(FALSE);
++ }
++
++ if (builtin_card) {
++ /* remove slot polling */
++ pHcdContext->Hcd.Attributes &= ~SDHCD_ATTRIB_SLOT_POLLING;
++ }
++
++ if (pHcdContext->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ /* in SPI mode, the controller only supports 1 block */
++ pHcdContext->Hcd.MaxBytesPerBlock = SPI_PXA_MAX_BYTES_PER_BLOCK;
++ pHcdContext->Hcd.MaxBlocksPerTrans = SPI_PXA_MAX_BLOCKS;
++ } else {
++ pHcdContext->Hcd.MaxBytesPerBlock = min(max_bytes_per_block,(UINT32)SDIO_PXA_MAX_BYTES_PER_BLOCK);
++ pHcdContext->Hcd.MaxBlocksPerTrans = min(max_blocks,(UINT32)SDIO_PXA_MAX_BLOCKS);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 - Max Blocks:%d, Max Bytes Per Block:%d \n",
++ pHcdContext->Hcd.MaxBlocksPerTrans, pHcdContext->Hcd.MaxBytesPerBlock));
++
++ do {
++
++ pHcdContext->Device.DmaChannel = -1;
++
++ if (!noDMA) {
++
++ pHcdContext->Device.pDmaDescriptorBuffer = (PUINT32)dma_alloc_coherent(
++ &pHcdContext->Device.pBusDevice->dev,
++ PXA_DESCRIPTOR_BUFFER_SIZE,
++ &pHcdContext->Device.DmaDescriptorPhys,
++ GFP_DMA);
++
++ if (NULL == pHcdContext->Device.pDmaDescriptorBuffer) {
++ err = -ENOMEM;
++ break;
++ }
++
++ if (pHcdContext->Device.DmaDescriptorPhys & 0xF) {
++ err = -ENOMEM;
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO PXA270 Local HCD: Descriptor buffer is not 16 byte aligned! 0x%X\n",
++ pHcdContext->Device.DmaDescriptorPhys));
++ break;
++ }
++
++ pHcdContext->Device.pDmaCommonBuffer = (PUINT8)dma_alloc_coherent(
++ &pHcdContext->Device.pBusDevice->dev,
++ PXA_DMA_COMMON_BUFFER_SIZE,
++ &pHcdContext->Device.DmaCommonBufferPhys,
++ GFP_DMA);
++
++ if (NULL == pHcdContext->Device.pDmaCommonBuffer) {
++ err = -ENOMEM;
++ break;
++ }
++
++ pHcdContext->Hcd.pDmaDescription = &HcdContext.Device.Dma;
++ pHcdContext->DmaCapable = TRUE;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 - Common Buffer:0x%X Size:%d \n",
++ (UINT32)pHcdContext->Device.DmaCommonBufferPhys, PXA_DMA_COMMON_BUFFER_SIZE));
++ }
++
++ /* map the devices memory addresses */
++ err = MapAddress(&pHcdContext->Device.ControlRegs, "SDIOPXA270");
++ if (err < 0) {
++ /* couldn't map the address */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Local HCD: Probe - unable to map memory\n"));
++ break;
++ }
++
++ err = MapAddress(&pHcdContext->Device.GpioRegs, "SDIOPXA270");
++ if (err < 0) {
++ /* couldn't map the address */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Local HCD: Probe - unable to map memory\n"));
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Switching GPIO lines \n"));
++ pxa_gpio_mode(GPIO92_MMCDAT0_MD);
++ pxa_gpio_mode(GPIO109_MMCDAT1_MD);
++ pxa_gpio_mode(GPIO110_MMCDAT2_MD);
++ if (pHcdContext->Hcd.Attributes & SDHCD_ATTRIB_BUS_SPI) {
++ pxa_gpio_mode(GPIO110_MMCCS1_MD); /* GPIO110_MMCCS1_MD is a typo in pxa-regs.h */
++ } else {
++ pxa_gpio_mode(GPIO111_MMCDAT3_MD);
++ }
++ pxa_gpio_mode(GPIO112_MMCCMD_MD);
++ pxa_gpio_mode(GPIO32_MMCCLK_MD);
++
++ /* route MMC clock */
++ pxa_set_cken(CKEN12_MMC, 1);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 - MMC IRQ:%d \n",
++ pHcdContext->Device.MMCInterrupt));
++
++ /* map the controller interrupt */
++ err = request_irq (pHcdContext->Device.MMCInterrupt, hcd_mmc_irq, 0,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - unable to map MMC interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= MMC_INTERRUPT_INIT;
++
++#if defined(CONFIG_MACH_SANDGATE2P) || defined(CONFIG_MACH_SANDGATE2G) || defined(CONFIG_MACH_SANDGATE2)
++ /* turn it on for now...the BCR register access is not protected,
++ * so we only want to touch this once */
++ SlotPowerOnOff(pHcdContext, TRUE);
++#endif
++
++ if (!SDIO_SUCCESS((status = HcdInitialize(pHcdContext)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Probe - failed to init HW, status =%d\n", status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= SDHC_HW_INIT;
++
++ pHcdContext->Device.DmaChannel = pxa_request_dma(pHcdContext->pDescription,
++ DMA_PRIO_LOW,
++ DmaCompletionCallBack,
++ pHcdContext);
++ if (pHcdContext->Device.DmaChannel < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Probe - failed to allocate DMA channel\n"));
++ err = -ENODEV;
++ break;
++ }
++
++ /* register with the SDIO bus driver */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pHcdContext->Hcd)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Probe - failed to register with host, status =%d\n",
++ status));
++ err = SDIOErrorToOSError(status);
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= SDHC_REGISTERED;
++
++#ifdef CONFIG_MACH_SANDGATE2P
++#ifdef USE_CARD_DETECT_HW
++ pHcdContext->Device.CardInsertInterrupt = SANDGATE2P_MMC_IN_IRQ;
++ pHcdContext->Device.CardRemoveInterrupt = SANDGATE2P_MMC_OUT_IRQ;
++
++ DBG_PRINT(SDDBG_TRACE,("SDIO PXA270 - card insert IRQ :%d, card remove IRQ:%d \n",
++ pHcdContext->Device.CardInsertInterrupt,
++ pHcdContext->Device.CardRemoveInterrupt));
++
++ /* map the card insert interrupt */
++ err = request_irq (pHcdContext->Device.CardInsertInterrupt, hcd_card_detect_insert_irq, 0,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - unable to map CardInsert interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++
++ pHcdContext->Device.InitStateMask |= CARD_DETECT_INSERT_INTERRUPT_INIT;
++
++ /* map the card remove interrupt */
++ err = request_irq (pHcdContext->Device.CardRemoveInterrupt, hcd_card_detect_remove_irq, 0,
++ pHcdContext->pDescription, pHcdContext);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 - unable to map CardRemove interrupt \n"));
++ err = -ENODEV;
++ break;
++ }
++ /* disable remove */
++ disable_irq(pHcdContext->Device.CardRemoveInterrupt);
++
++ pHcdContext->Device.InitStateMask |= CARD_DETECT_REMOVE_INTERRUPT_INIT;
++#endif
++#endif
++
++ if (builtin_card) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Forcing ATTACH on built-in card \n"));
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, EVENT_HCD_ATTACH);
++ }
++
++ } while (FALSE);
++
++ if (err < 0) {
++ Remove(pBusDevice); /* TODO: the cleanup should not really be done in the Remove function */
++ } else {
++#ifdef USE_CARD_DETECT_HW
++ pHcdContext->Device.StartUpCheck = TRUE;
++ /* queue the work item test the slot */
++ if (!SDIO_SUCCESS(QueueEventResponse(pHcdContext, WORK_ITEM_CARD_DETECT))) {
++ /* failed */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Probe - queue event failed\n"));
++ }
++#endif
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Probe - HCD ready! \n"));
++ }
++ return err;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++static void Remove(struct pnp_dev *pBusDevice)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = &HcdContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO PXA270 Local HCD: Remove - removing device\n"));
++
++ pHcdContext->Device.ShutDown = TRUE;
++
++ OSSleep(1000);
++
++ if (pHcdContext->Device.InitStateMask & MMC_INTERRUPT_INIT) {
++ WRITE_MMC_REG(pHcdContext, MMC_I_MASK_REG, MMC_MASK_ALL_INTS);
++ }
++
++ if (pHcdContext->Device.InitStateMask & SDHC_REGISTERED) {
++ /* unregister from the bus driver */
++ SDIO_UnregisterHostController(&pHcdContext->Hcd);
++ }
++
++ if (pHcdContext->Device.DmaChannel >= 0) {
++ pxa_free_dma(pHcdContext->Device.DmaChannel);
++ pHcdContext->Device.DmaChannel = -1;
++ }
++
++ /* free irqs */
++ if (pHcdContext->Device.InitStateMask & MMC_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.MMCInterrupt, pHcdContext);
++ }
++ if (pHcdContext->Device.InitStateMask & CARD_DETECT_INSERT_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.CardInsertInterrupt, pHcdContext);
++ }
++ if (pHcdContext->Device.InitStateMask & CARD_DETECT_REMOVE_INTERRUPT_INIT) {
++ free_irq(pHcdContext->Device.CardRemoveInterrupt, pHcdContext);
++ }
++ if (pHcdContext->Device.InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pHcdContext);
++ }
++
++ pHcdContext->Device.InitStateMask = 0;
++
++ /* free mapped registers */
++ if (pHcdContext->Device.ControlRegs.pMapped != NULL) {
++ UnmapAddress(&pHcdContext->Device.ControlRegs);
++ pHcdContext->Device.ControlRegs.pMapped = NULL;
++ }
++
++ if (pHcdContext->Device.GpioRegs.pMapped != NULL) {
++ UnmapAddress(&pHcdContext->Device.GpioRegs);
++ pHcdContext->Device.GpioRegs.pMapped = NULL;
++ }
++
++
++ if (pHcdContext->Device.pDmaDescriptorBuffer != NULL) {
++ dma_free_coherent(&pHcdContext->Device.pBusDevice->dev,
++ PXA_DESCRIPTOR_BUFFER_SIZE,
++ pHcdContext->Device.pDmaDescriptorBuffer,
++ pHcdContext->Device.DmaDescriptorPhys);
++ pHcdContext->Device.pDmaDescriptorBuffer = NULL;
++ }
++
++ if (pHcdContext->Device.pDmaCommonBuffer != NULL) {
++ dma_free_coherent(&pHcdContext->Device.pBusDevice->dev,
++ PXA_DMA_COMMON_BUFFER_SIZE,
++ pHcdContext->Device.pDmaCommonBuffer,
++ pHcdContext->Device.DmaCommonBufferPhys);
++ pHcdContext->Device.pDmaCommonBuffer = NULL;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PXA270 Local HCD: Remove\n"));
++}
++
++/*
++ * MapAddress - maps I/O address
++*/
++static SYSTEM_STATUS MapAddress(PSDHCD_MEMORY pMap, PTEXT pDescription) {
++
++ if (request_mem_region(pMap->Raw, pMap->Length, pDescription) == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Local HCD: MapAddress - memory in use\n"));
++ return -EBUSY;
++ }
++ pMap->pMapped = ioremap_nocache(pMap->Raw, pMap->Length);
++ if (pMap->pMapped == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Local HCD: MapAddress - unable to map memory\n"));
++ /* cleanup region */
++ release_mem_region(pMap->Raw, pMap->Length);
++ return -EFAULT;
++ }
++ return 0;
++}
++
++/*
++ * UnmapAddress - unmaps the address
++*/
++static void UnmapAddress(PSDHCD_MEMORY pMap) {
++ iounmap(pMap->pMapped);
++ release_mem_region(pMap->Raw, pMap->Length);
++ pMap->pMapped = NULL;
++}
++
++static void DmaCompletionCallBack(int dma, void *devid, struct pt_regs *regs)
++{
++ PSDHCD_DRIVER_CONTEXT pHct = (PSDHCD_DRIVER_CONTEXT)devid;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq;
++ UINT32 dcsr;
++
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++
++ dcsr = DCSR(pHct->Device.DmaChannel);
++
++ DBG_PRINT(PXA_TRACE_DATA, ("+SDIO PXA270 DMA Complete, DCSR :0x%X\n",dcsr));
++
++ do {
++ if (dcsr & DCSR_BUSERR) {
++ DBG_PRINT(SDDBG_ERROR, (" DCSR Bus Error\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ } else if (dcsr & DCSR_ENDINTR) {
++ DBG_PRINT(PXA_TRACE_DATA, (" DMA complete\n"));
++ } else if (dcsr & DCSR_STOPSTATE) {
++ DBG_PRINT(PXA_TRACE_DATA, (" DMA stopped\n"));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO PXA270 Unhandled DMA status : 0x%X \n",dcsr));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ }
++
++ /* stop DMA and clear interrupt sources */
++ DCSR(pHct->Device.DmaChannel) = DCSR_ENDINTR | DCSR_BUSERR;
++
++ if (NULL == pReq) {
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ if (pHct->DmaType != PXA_DMA_COMMON_BUFFER) {
++ break;
++ }
++ /* handle common buffer case */
++ if (!IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* read DMA */
++ pReq->DataRemaining -= pHct->Device.LastRxCopy;
++ /* copy from common buffer */
++ memcpy(pReq->pHcdContext, pHct->Device.pDmaCommonBuffer,pHct->Device.LastRxCopy);
++ /* advance buffer position */
++ pReq->pHcdContext = (PUINT8)pReq->pHcdContext + pHct->Device.LastRxCopy;
++ DBG_PRINT(PXA_TRACE_DATA,
++ ("SDIO PXA270 DMA data remaining RX: %d \n",pReq->DataRemaining));
++ }
++
++ if (pReq->DataRemaining) {
++ /* setup next common buffer */
++ status = SetUpPXADMA(pHct,
++ pReq,
++ pHct->Device.pDmaCompletion,
++ pHct->Device.pContext);
++ if (SDIO_SUCCESS(status) && IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ DBG_PRINT(PXA_TRACE_DATA,
++ ("SDIO PXA270 DMA data remaining TX: %d \n", pReq->DataRemaining));
++ }
++ }
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* call completion callback */
++ pHct->Device.pDmaCompletion(pHct->Device.pContext, status, TRUE);
++ }
++
++ DBG_PRINT(PXA_TRACE_DATA, ("-SDIO PXA270 DMA Complete\n"));
++}
++
++static void DumpDescriptors(struct pxa_dma_desc *pDesc,
++ INT DescCnt)
++{
++ INT i;
++ DBG_PRINT(SDDBG_WARN, ("SDIO PXA270 Dumping DMA Descriptors at 0x%X :\n",(UINT32)pDesc));
++
++ for (i = 0; i < DescCnt; i++,pDesc++) {
++ DBG_PRINT(SDDBG_WARN, (" Entry %d \n",i));
++ DBG_PRINT(SDDBG_WARN, (" DSADR: 0x%X \n", pDesc->dsadr));
++ DBG_PRINT(SDDBG_WARN, (" DTADR: 0x%X \n", pDesc->dtadr));
++ DBG_PRINT(SDDBG_WARN, (" DCMD : 0x%X \n", pDesc->dcmd));
++ DBG_PRINT(SDDBG_WARN, (" DDADR: 0x%X \n",pDesc->ddadr));
++ }
++}
++
++/* DMA setup */
++SDIO_STATUS SetUpPXADMA(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext)
++{
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ UINT32 dmaCommand;
++ struct pxa_dma_desc *pDesc;
++ INT i;
++ INT descCnt;
++ PSDDMA_DESCRIPTOR pSgItem;
++ UINT32 dmaTransferLength;
++ UINT32 thisDescrLength;
++
++ pHct->Device.pDmaCompletion = pCompletion;
++ pHct->Device.pContext = pContext;
++
++ DBG_ASSERT(pReq->DataRemaining != 0);
++
++ /* disable any existing channel mappings */
++ DRCMRRXMMC = 0;
++ DRCMRTXMMC = 0;
++
++ /* make sure DMA is disabled */
++ DCSR(pHct->Device.DmaChannel) = 0;
++ /* get ptr to descriptor memory area */
++ pDesc = (struct pxa_dma_desc *)pHct->Device.pDmaDescriptorBuffer;
++ descCnt = 0;
++ /* clear descriptors */
++ memset(pDesc, 0, (sizeof(struct pxa_dma_desc))*MAX_DMA_DESCRIPTORS);
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* write DMA, target is SDIO TX FIFO, source is memory*/
++ dmaCommand = DCMD_FLOWTRG | DCMD_INCSRCADDR;
++ /* map DMA channel to TX DMA request line */
++ DRCMRTXMMC = pHct->Device.DmaChannel | DRCMR_MAPVLD;
++ } else {
++ /* read DMA, target is memory, source is SDIO RX FIFO*/
++ dmaCommand = DCMD_FLOWSRC| DCMD_INCTRGADDR;
++ /* map DMA channel to RX DMA request line */
++ DRCMRRXMMC = pHct->Device.DmaChannel | DRCMR_MAPVLD;
++ }
++ /* try bursting and set width to 1 byte, enable IRQ at end of DMA */
++ dmaCommand |= DCMD_WIDTH1 | DCMD_BURST32;
++
++ do {
++ if (pHct->DmaType == PXA_DMA_COMMON_BUFFER) {
++ UINT32 dataCopy;
++
++ dataCopy = min(pReq->DataRemaining,(UINT32)PXA_DMA_COMMON_BUFFER_SIZE);
++ descCnt = 1;
++ /* just one scatter gather list for the common buffer */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* write DMA */
++ pReq->DataRemaining -= dataCopy;
++ /* copy to common buffer */
++ memcpy(pHct->Device.pDmaCommonBuffer, pReq->pHcdContext,dataCopy);
++ pReq->pHcdContext = (PUINT8)pReq->pHcdContext + dataCopy;
++ pDesc[0].dsadr = pHct->Device.DmaCommonBufferPhys;
++ pDesc[0].dtadr = PXA_MMC_CONTROLLER_BASE_ADDRESS + MMC_TXFIFO_REG;
++ } else {
++ /* read DMA , just save the amount we need to copy */
++ pHct->Device.LastRxCopy = dataCopy;
++ pDesc[0].dsadr = PXA_MMC_CONTROLLER_BASE_ADDRESS + MMC_RXFIFO_REG;
++ pDesc[0].dtadr = pHct->Device.DmaCommonBufferPhys;
++ }
++ /* only 1 descriptor, so generate END interrupt */
++ dmaCommand |= DCMD_ENDIRQEN;
++ /* set command and length */
++ pDesc[0].dcmd = dmaCommand | dataCopy;
++ pDesc[0].ddadr = DDADR_STOP;
++ /* we're done */
++ break;
++ }
++
++ /* scatter gather version */
++ DBG_ASSERT(pHct->DmaType == PXA_DMA_SCATTER_GATHER);
++ /* get the start of the list */
++ pSgItem = (PSDDMA_DESCRIPTOR)pReq->pDataBuffer;
++ dmaTransferLength = pReq->DataRemaining;
++ descCnt = pReq->DescriptorCount;
++
++ dma_map_sg(pHct->Hcd.pDevice,
++ pSgItem,
++ descCnt,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ pHct->Device.DmaSgMapped = TRUE;
++
++ for (i = 0; i < descCnt; i++,pDesc++,pSgItem++) {
++ DBG_ASSERT(sg_dma_len(pSgItem) <= PXA_MAX_BYTES_PER_DESCRIPTOR);
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* write DMA */
++ pDesc->dsadr = sg_dma_address(pSgItem);
++ pDesc->dtadr = PXA_MMC_CONTROLLER_BASE_ADDRESS + MMC_TXFIFO_REG;
++ } else {
++ /* read DMA */
++ pDesc->dsadr = PXA_MMC_CONTROLLER_BASE_ADDRESS + MMC_RXFIFO_REG;
++ pDesc->dtadr = sg_dma_address(pSgItem);
++ }
++
++ if (i == (descCnt - 1)) {
++ /* last one */
++ pDesc->ddadr = DDADR_STOP;
++ /* trigger DMA interrupt when the last one is finished */
++ dmaCommand |= DCMD_ENDIRQEN;
++ /* handle the last one in a special way */
++ thisDescrLength = min(dmaTransferLength,sg_dma_len(pSgItem));
++ } else {
++ /* chain to the next one */
++ pDesc->ddadr = pHct->Device.DmaDescriptorPhys +
++ ((i + 1) * (sizeof(struct pxa_dma_desc)));
++ thisDescrLength = sg_dma_len(pSgItem);
++ }
++
++ /* set command and length */
++ pDesc->dcmd = dmaCommand | thisDescrLength;
++ dmaTransferLength -= thisDescrLength;
++ }
++
++ } while (FALSE);
++
++ if (SDIO_SUCCESS(status)) {
++ if (DBG_GET_DEBUG_LEVEL() >= PXA_TRACE_DATA) {
++ DumpDescriptors((struct pxa_dma_desc *)pHct->Device.pDmaDescriptorBuffer,
++ descCnt);
++ }
++ DBG_PRINT(PXA_TRACE_DATA, ("SDIO PXA270 Starting DMA (Descriptors at Phys: 0x%X)\n",pHct->Device.DmaDescriptorPhys));
++ /* set descriptor start address */
++ DDADR(pHct->Device.DmaChannel) = pHct->Device.DmaDescriptorPhys;
++ DCSR(pHct->Device.DmaChannel) = DCSR_RUN;
++ }
++
++
++ return status;
++}
++
++void SDCancelDMATransfer(PSDHCD_DRIVER_CONTEXT pHct)
++{
++ DCSR(pHct->Device.DmaChannel) = 0;
++ /* wait for DMA channel to stop */
++ while (!(DCSR(pHct->Device.DmaChannel) & DCSR_STOPSTATE)) {};
++}
++
++void CompleteRequestSyncDMA(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq, BOOL FromIsr)
++{
++ ULONG flags;
++
++ if (!FromIsr) {
++ spin_lock_irqsave(&pHct->Device.Lock,flags);
++ }
++ /* make sure DMA has stopped and interrupt sources are cleared */
++ DCSR(pHct->Device.DmaChannel) = DCSR_ENDINTR | DCSR_BUSERR;
++
++ /* clean up SG mapping */
++ if (pHct->Device.DmaSgMapped) {
++ pHct->Device.DmaSgMapped = FALSE;
++ dma_unmap_sg(pHct->Hcd.pDevice,
++ (PSDDMA_DESCRIPTOR)pReq->pDataBuffer,
++ pReq->DescriptorCount,
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ }
++
++ if (!FromIsr) {
++ spin_unlock_irqrestore(&pHct->Device.Lock,flags);
++ }
++
++ QueueEventResponse(pHct, WORK_ITEM_IO_COMPLETE);
++}
++
++/* MMC controller interrupt routine */
++static irqreturn_t hcd_mmc_irq(int irq, void *context, struct pt_regs * r)
++{
++ /* call OS independent ISR */
++ if (HcdMMCInterrupt((PSDHCD_DRIVER_CONTEXT)context)) {
++ return IRQ_HANDLED;
++ } else {
++ return IRQ_NONE;
++ }
++}
++
++#ifdef USE_CARD_DETECT_HW
++/* card detect insert interrupt request */
++static irqreturn_t hcd_card_detect_insert_irq(int irq, void *context, struct pt_regs * r)
++{
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("SDIO PXA270 Card Detect Insert Interrupt, queueing work item \n"));
++ /* just queue the work item to debounce the pin */
++ QueueEventResponse((PSDHCD_DRIVER_CONTEXT)context, WORK_ITEM_CARD_DETECT);
++ return IRQ_HANDLED;
++}
++
++/* card detect remove interrupt request */
++static irqreturn_t hcd_card_detect_remove_irq(int irq, void *context, struct pt_regs * r)
++{
++ DBG_PRINT(PXA_TRACE_CARD_INSERT, ("SDIO PXA270 Card Detect Remove Interrupt, queueing work item \n"));
++ /* just queue the work item to debounce the pin */
++ QueueEventResponse((PSDHCD_DRIVER_CONTEXT)context, WORK_ITEM_CARD_DETECT);
++ return IRQ_HANDLED;
++}
++#endif
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHcdContext, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ work = &iocomplete_work;
++ break;
++#ifdef USE_CARD_DETECT_HW
++ case WORK_ITEM_CARD_DETECT:
++ work = &carddetect_work;
++ break;
++#endif
++ case WORK_ITEM_SDIO_IRQ:
++ work = &sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_PENDING;
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, EVENT_HCD_TRANSFER_DONE);
++}
++
++#ifdef USE_CARD_DETECT_HW
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++ HCD_EVENT event;
++
++ event = EVENT_HCD_NOP;
++ //PXA_TRACE_CARD_INSERT
++
++ DBG_PRINT(SDDBG_TRACE, ("+ SDIO PXA270 Card Detect Work Item \n"));
++
++ if (!pHcdContext->CardInserted) {
++ DBG_PRINT(SDDBG_TRACE, ("Delaying to debounce card... \n"));
++ /* sleep for slot debounce if there is no card */
++ msleep(PXA_SLOT_DEBOUNCE_MS);
++ }
++
++ /* check board status pin */
++ if (IsCardInserted(pHcdContext)) {
++ if (!pHcdContext->CardInserted) {
++ pHcdContext->CardInserted = TRUE;
++ event = EVENT_HCD_ATTACH;
++ DBG_PRINT(SDDBG_TRACE, (" Card Inserted! \n"));
++ /* disable insert */
++ disable_irq(pHcdContext->Device.CardInsertInterrupt);
++ /* enable remove */
++ enable_irq(pHcdContext->Device.CardRemoveInterrupt);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Card detect interrupt , already inserted card! \n"));
++ }
++ } else {
++ if (pHcdContext->CardInserted) {
++ event = EVENT_HCD_DETACH;
++ pHcdContext->CardInserted = FALSE;
++ DBG_PRINT(SDDBG_TRACE, (" Card Removed! \n"));
++ /* disable remove */
++ disable_irq(pHcdContext->Device.CardRemoveInterrupt);
++ /* enable insert */
++ enable_irq(pHcdContext->Device.CardInsertInterrupt);
++ } else {
++ if (pHcdContext->Device.StartUpCheck) {
++ pHcdContext->Device.StartUpCheck = FALSE;
++ DBG_PRINT(SDDBG_TRACE, ("No card at power up. \n"));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Card detect interrupt , already removed card! \n"));
++ }
++ }
++ }
++
++ if (event != EVENT_HCD_NOP) {
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, event);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("- SDIO PXA270 Card Detect Work Item \n"));
++}
++
++
++BOOL IsCardInserted(PSDHCD_DRIVER_CONTEXT pHct)
++{
++#ifdef CONFIG_MACH_SANDGATE2P
++ /* check board status FPGA, active low */
++ return !(SG2P_STATUS & SG2P_STATUS_nSD_DETECT);
++#elif defined(CONFIG_MACH_SANDGATE2G)
++ return !(SG2G_STATUS & SG2G_STATUS_MMC_DETECT);
++#elif defined(CONFIG_MACH_SANDGATE2)
++ return !(SG2_STATUS & SG2_STATUS_MMC_DETECT);
++#else
++#error "Must define card insertion for PXA270 HCD"
++#endif
++}
++
++#endif
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_DRIVER_CONTEXT pHcdContext = (PSDHCD_DRIVER_CONTEXT)context;
++ DBG_PRINT(PXA_TRACE_SDIO_INT, ("SDIO PXA270: hcd_sdioirq_wqueue_handler \n"));
++ SDIO_HandleHcdEvent(&pHcdContext->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskMMCIrq - Un mask an MMC interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void UnmaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr)
++{
++ ULONG flags;
++ UINT32 ints;
++
++ if (!FromIsr) {
++ spin_lock_irqsave(&pHct->Device.Lock,flags);
++ }
++ ints = READ_MMC_REG(pHct, MMC_I_MASK_REG);
++ ints &= ~Mask;
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, ints);
++ if (!FromIsr) {
++ spin_unlock_irqrestore(&pHct->Device.Lock,flags);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskMMCIrq - Mask MMC interrupts
++ Input: pHct - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void MaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr)
++{
++ UINT32 ints;
++ ULONG flags;
++
++ if (!FromIsr) {
++ spin_lock_irqsave(&pHct->Device.Lock,flags);
++ }
++ ints = READ_MMC_REG(pHct, MMC_I_MASK_REG);
++ ints |= Mask;
++ WRITE_MMC_REG(pHct, MMC_I_MASK_REG, ints);
++ if (!FromIsr) {
++ spin_unlock_irqrestore(&pHct->Device.Lock,flags);
++ }
++}
++
++void ModifyCSForSPIIntDetection(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable)
++{
++ if (Enable) {
++ /* set pin level low to keep CS0 line low all the time, this is required
++ * for some cards to assert their SDIO interrupt line , set the pin register low
++ * before switching functions so that it does not glitch*/
++ WRITE_GPIO_REG(pHcdContext,GPIO_GPCR0,GPIO_bit(GPIO8_MMCCS0));
++ /* set GPIO8 for output mode, ALTFN 0, general purpose I/O */
++ pxa_gpio_mode(GPIO8_MMCCS0 | GPIO_OUT);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 SPI Mode - CS0 driven low for interrupt detect \n"));
++ } else {
++ /* switch mode back to normal CS0 operation */
++ pxa_gpio_mode(GPIO8_MMCCS0_MD);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 SPI Mode - normal CS0 operation \n"));
++ }
++}
++
++
++void SlotPowerOnOff(PSDHCD_DRIVER_CONTEXT pHct , BOOL On)
++{
++#ifdef CONFIG_MACH_SANDGATE2P
++ if (On) {
++ SG2P_BCR |= SG2P_BCR_SD_PWR_ON;
++ } else {
++ SG2P_BCR &= ~SG2P_BCR_SD_PWR_ON;
++ }
++#elif defined(CONFIG_MACH_SANDGATE2G)
++ if (On) {
++ sandgate2_bcr |= SG2G_BCR1_MMC_PWR_ON;
++ SG2G_BCR1 = sandgate2_bcr;
++ } else {
++ sandgate2_bcr &= ~SG2G_BCR1_MMC_PWR_ON;
++ SG2G_BCR1 = sandgate2_bcr;
++ }
++#elif defined(CONFIG_MACH_SANDGATE2)
++ if (On) {
++ sandgate2_bcr |= SG2_BCR_MMC_PWR_ON;
++ SG2_BCR = sandgate2_bcr;
++ } else {
++ sandgate2_bcr &= ~SG2_BCR_MMC_PWR_ON;
++ SG2_BCR = sandgate2_bcr;
++ }
++#elif defined(CONFIG_MACH_MAINSTONE)
++ mainstone_bcr = MST_MSCWR1;
++ if (On) {
++ mainstone_bcr |= MST_MSCWR1_MMC_ON;
++ mainstone_bcr &= ~MST_MSCWR1_MS_SEL;
++ MST_MSCWR1 = mainstone_bcr;
++ } else {
++ mainstone_bcr &= ~MST_MSCWR1_MMC_ON;
++ MST_MSCWR1 = mainstone_bcr;
++ }
++#else
++#error "Must define slot power on/off for PXA270 HCD"
++#endif
++}
++
++BOOL IsSlotWPSet(PSDHCD_DRIVER_CONTEXT pHct)
++{
++#ifdef CONFIG_MACH_SANDGATE2P
++ return SG2P_STATUS & SG2P_STATUS_SD_WP;
++#elif defined(CONFIG_MACH_SANDGATE2G)
++ return SG2G_STATUS & SG2G_STATUS_MMC_WP;
++#elif defined(CONFIG_MACH_SANDGATE2)
++ return SG2_STATUS & SG2_STATUS_MMC_WP;
++#else
++ return 0;
++#endif
++}
++
++
++/*
++ * module init
++*/
++static int __init sdio_local_hcd_init(void) {
++ SDIO_STATUS status;
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO PXA270 Local HCD: loaded\n"));
++
++ status = SDIO_BusAddOSDevice(&HcdContext.Device.Dma,
++ &HcdContext.Device.HcdDriver,
++ &HcdContext.Device.HcdDevice);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO PXA270 Local HCD: sdio_local_hcd_init exit\n"));
++ return SDIOErrorToOSError(status);
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_local_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO PXA270 Local HCD: unloaded\n"));
++ SDIO_BusRemoveOSDevice(&HcdContext.Device.HcdDriver, &HcdContext.Device.HcdDevice);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO PXA270 Local HCD: leave sdio_local_hcd_cleanup\n"));
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_local_hcd_init);
++module_exit(sdio_local_hcd_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_pxa270hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/pxa270/sdio_pxa270hcd.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,273 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_pxa270hcd.h
++
++ at abstract: include file for PXA270local bus host controller, OS independent code
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_PXA270HCD_H___
++#define __SDIO_PXA270HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_hcd_linux.h"
++
++enum PXA_TRACE_ENUM {
++ PXA_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ PXA_TRACE_SDIO_INT = (SDDBG_TRACE + 2),
++ PXA_TRACE_DATA,
++ PXA_TRACE_REQUESTS,
++ PXA_TRACE_DATA_DUMP,
++ PXA_TRACE_CONFIG,
++ PXA_TRACE_MMC_INT,
++ PXA_TRACE_LAST
++};
++
++typedef enum _PXA_DMA_TYPE {
++ PXA_DMA_NONE = 0,
++ PXA_DMA_COMMON_BUFFER = 1,
++ PXA_DMA_SCATTER_GATHER
++}PXA_DMA_TYPE, *PPXA_DMA_TYPE;
++
++
++//default device location
++#define PXA_MMC_CONTROLLER_BASE_ADDRESS 0x41100000
++#define PXA_MMC_CONTROLLER_ADDRESS_LENGTH 0x44
++#define PXA_GPIO_PIN_LVL_REGS_BASE 0x40e00000
++#define PXA_GPIO_PIN_LVL_REGS_LENGTH 0x14c
++#define SDIO_BD_MAX_SLOTS 1
++#define SDIO_PXA_MAX_BYTES_PER_BLOCK 1023
++#define SDIO_PXA_MAX_BLOCKS 0xFFFF
++#define SPI_PXA_MAX_BLOCKS 1 /* SPI mode only supports single block */
++#define SPI_PXA_MAX_BYTES_PER_BLOCK 1023
++#define SDMMC_RESP_TIMEOUT_CLOCKS 64
++#define SDMMC_DATA_TIMEOUT_CLOCKS 0xFFFF
++
++#define PXA_DMA_THRESHOLD 32
++#define MMC_MAX_RXFIFO 32
++#define MMC_MAX_TXFIFO 32
++#define PXA_TX_PARTIAL_FIFO_MASK (MMC_MAX_TXFIFO - 1)
++/* register definitions */
++#define GPIO_GPLR0 0x00
++#define GPIO_GPLR1 0x04
++#define GPIO_GPLR2 0x08
++#define GPIO_GPLR3 0x100
++#define GPIO_GPDR0 0x0C
++#define GPIO_GPDR1 0x10
++#define GPIO_GPDR2 0x14
++#define GPIO_GPDR3 0x10C
++
++#define GPIO_GPSR0 0x18
++#define GPIO_GPSR1 0x1C
++#define GPIO_GPSR2 0x20
++#define GPIO_GPSR3 0x118
++#define GPIO_GPCR0 0x24
++#define GPIO_GPCR1 0x28
++#define GPIO_GPCR2 0x2C
++#define GPIO_GPCR3 0x124
++
++#define GPIO_GRER0 0x30
++#define GPIO_GRER1 0x34
++#define GPIO_GFER0 0x3c
++#define GPIO_GFER1 0x40
++
++#define GPIO_GAFR0_L 0x54
++#define GPIO_GAFR0_U 0x58
++#define GPIO_GAFR1_L 0x5C
++#define GPIO_GAFR1_U 0x60
++#define GPIO_GAFR2_L 0x64
++#define GPIO_GAFR2_U 0x68
++#define GPIO_GAFR3_L 0x6C
++#define GPIO_GAFR3_U 0x70
++
++/* clock control */
++#define MMC_STRPCL_REG 0x00
++#define MMC_CLOCK_START 0x02
++#define MMC_CLOCK_STOP 0x01
++/* mmc status */
++#define MMC_STAT_REG 0x04
++#define MMC_STAT_DATA_DONE (1 << 11)
++#define MMC_STAT_PRG_DONE (1 << 12)
++#define MMC_STAT_END_CMD (1 << 13)
++#define MMC_STAT_CLK_ON (1 << 8)
++#define MMC_STAT_RCV_FULL (1 << 7)
++#define MMC_STAT_XMIT_EMPTY (1 << 6)
++#define MMC_STAT_RESP_CRC_ERR (1 << 5)
++#define MMC_STAT_SPI_RDTKN_ERR (1 << 4)
++#define MMC_STAT_RDDAT_CRC_ERR (1 << 3)
++#define MMC_STAT_WR_ERROR (1 << 2)
++#define MMC_STAT_RESP_TIMEOUT (1 << 1)
++#define MMC_STAT_READ_TIMEOUT (1 << 0)
++#define MMC_STAT_ERRORS 0x0000003F
++#define MMC_RESP_ERRORS (MMC_STAT_RESP_CRC_ERR | MMC_STAT_RESP_TIMEOUT)
++#define MMC_STAT_RD_ERRORS (MMC_STAT_RDDAT_CRC_ERR | MMC_STAT_READ_TIMEOUT)
++/* clock rate */
++#define MMC_CLKRT_REG 0x08
++/* SPI control */
++#define MMC_SPI_REG 0x0c
++#define MMC_SPI_SEL_CS0 (1 << 3)
++#define MMC_SPI_CS_ENABLE (1 << 2)
++#define MMC_SPI_CRC_ENABLE (1 << 1)
++#define MMC_SPI_ENABLE (1 << 0)
++#define SPI_ENABLE_WITH_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_CRC_ENABLE | MMC_SPI_SEL_CS0)
++#define SPI_ENABLE_NO_CRC (MMC_SPI_CS_ENABLE | MMC_SPI_ENABLE | \
++ MMC_SPI_SEL_CS0)
++/* command/data control */
++#define MMC_CMDAT_REG 0x10
++#define MMC_CMDAT_SDIO_IRQ_DETECT (1 << 11)
++#define MMC_CMDAT_SD_4DAT (1 << 8)
++#define MMC_CMDAT_DMA_ENABLE (1 << 7)
++#define MMC_CMDAT_80_CLOCKS (1 << 6)
++#define MMC_CMDAT_RES_BUSY (1 << 5)
++#define MMC_CMDDAT_STREAM (1 << 4)
++#define MMC_CMDDAT_DATA_WR (1 << 3)
++#define MMC_CMDDAT_DATA_EN (1 << 2)
++#define MMC_CMDDAT_RES_NONE 0x00
++#define MMC_CMDDAT_RES_R1_R4_R5 0x01
++#define MMC_CMDDAT_RES_R2 0x02
++#define MMC_CMDDAT_RES_R3 0x03
++/* response timeout control */
++#define MMC_RESTO_REG 0x14
++#define MMC_RESTO_MASK 0x0000007F
++/* read data timeout */
++#define MMC_RDTO_REG 0x18
++#define MMC_RDTO_MASK 0x0000FFFF
++/* block length */
++#define MMC_BLKLEN_REG 0x1c
++#define MMC_BLKLEN_MASK 0x003FF
++/* number of blocks */
++#define MMC_NOB_REG_REG 0x20
++#define MMC_NOB_MASK 0x0000FFFF
++/* partial buffer */
++#define MMC_PRTBUF_REG 0x24
++#define MMC_PRTBUF_PARTIAL (1 << 0)
++/* interrupt mask register */
++#define MMC_I_MASK_REG 0x28
++
++#define MMC_MASK_SUSP_ACK (1 << 12)
++#define MMC_MASK_SDIO_IRQ (1 << 11)
++#define MMC_MASK_RD_STALLED (1 << 10)
++#define MMC_MASK_RES_ERR (1 << 9)
++#define MMC_MASK_DAT_ERR (1 << 8)
++#define MMC_MASK_TINT (1 << 7)
++
++#define MMC_MASK_TXFIFO_WR (1 << 6)
++#define MMC_MASK_RXFIFO_RD (1 << 5)
++#define MMC_MASK_CLK_OFF (1 << 4)
++#define MMC_MASK_STOP_CMD (1 << 3)
++#define MMC_MASK_END_CMD (1 << 2)
++#define MMC_MASK_PRG_DONE (1 << 1)
++#define MMC_MASK_DATA_TRANS (1 << 0)
++#define MMC_MASK_ALL_INTS 0x00001FFF
++/* interrupt pending */
++#define MMC_I_REG_REG 0x2c
++#define MMC_INT_SDIO_IRQ (1 << 11)
++#define MMC_INT_TXFIFO_WR (1 << 6)
++#define MMC_INT_RXFIFO_RD (1 << 5)
++#define MMC_INT_CLK_OFF (1 << 4)
++#define MMC_INT_STOP_CMD (1 << 3)
++#define MMC_INT_END_CMD (1 << 2)
++#define MMC_INT_PRG_DONE (1 << 1)
++#define MMC_INT_DATA_TRANS (1 << 0)
++/* command register */
++#define MMC_CMD_REG 0x30
++/* argument high */
++#define MMC_ARGH_REG 0x34
++/* argument low */
++#define MMC_ARGL_REG 0x38
++/* response fifo */
++#define MMC_RES_REG 0x3c
++#define SD_DEFAULT_RESPONSE_BYTES 6
++#define SD_R2_RESPONSE_BYTES 16
++/* RX Fifo */
++#define MMC_RXFIFO_REG 0x40
++/* TX Fifo */
++#define MMC_TXFIFO_REG 0x44
++
++#define MMC_MAX_CLOCK_ENTRIES 7
++
++typedef struct _MMC_CLOCK_TBL_ENTRY {
++ SD_BUSCLOCK_RATE ClockRate; /* rate in */
++ UINT8 Divisor;
++}MMC_CLOCK_TBL_ENTRY;
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++typedef struct _SDHCD_DRIVER_CONTEXT {
++ PTEXT pDescription; /* human readable device decsription */
++ SDHCD Hcd; /* HCD description for bus driver */
++ SDHCD_DEVICE Device; /* the single device's info OS-Specific */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel;
++ BOOL KeepClockOn;
++ BOOL SD4Bit; /* 4 bit bus mode */
++ BOOL SDIrqData; /* irq check during transfers */
++ PXA_DMA_TYPE DmaType;
++ BOOL DmaCapable; /* DMA Capable */
++ BOOL PartialTxFIFO; /* partial TX fifo flag for DMA completion */
++ BOOL IssueInitClocks;
++}SDHCD_DRIVER_CONTEXT, *PSDHCD_DRIVER_CONTEXT;
++
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++void HcdDeinitialize(PSDHCD_DRIVER_CONTEXT pHcdContext);
++BOOL HcdMMCInterrupt(PSDHCD_DRIVER_CONTEXT pHcdContext);
++SDIO_STATUS QueueEventResponse(PSDHCD_DRIVER_CONTEXT pHcdContext, INT WorkItemID);
++BOOL GetGpioPinLevel(PSDHCD_DRIVER_CONTEXT pHcdContext, INT Pin);
++void ModifyCSForSPIIntDetection(PSDHCD_DRIVER_CONTEXT pHcdContext, BOOL Enable);
++void UnmaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr);
++void MaskMMCIrq(PSDHCD_DRIVER_CONTEXT pHct, UINT32 Mask, BOOL FromIsr);
++void SlotPowerOnOff(PSDHCD_DRIVER_CONTEXT pHct , BOOL On);
++BOOL IsSlotWPSet(PSDHCD_DRIVER_CONTEXT pHct);
++SDIO_STATUS SetUpPXADMA(PSDHCD_DRIVER_CONTEXT pHct,
++ PSDREQUEST pReq,
++ PDMA_TRANSFER_COMPLETION pCompletion,
++ PVOID pContext);
++void CompleteRequestSyncDMA(PSDHCD_DRIVER_CONTEXT pHct, PSDREQUEST pReq, BOOL FromIsr);
++void SDCancelDMATransfer(PSDHCD_DRIVER_CONTEXT pHct);
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++#endif /* __SDIO_PXA255HCD_H___ */
+Index: linux-2.6.22/drivers/Makefile
+===================================================================
+--- linux-2.6.22.orig/drivers/Makefile 2007-11-08 15:42:31.000000000 +0100
++++ linux-2.6.22/drivers/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -71,6 +71,7 @@
+ obj-$(CONFIG_EISA) += eisa/
+ obj-$(CONFIG_CPU_FREQ) += cpufreq/
+ obj-$(CONFIG_MMC) += mmc/
++obj-$(CONFIG_SDIO) += sdio/
+ obj-$(CONFIG_NEW_LEDS) += leds/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+ obj-$(CONFIG_SGI_SN) += sn/
+Index: linux-2.6.22/include/linux/sdio/sdlist.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/sdlist.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,137 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdlist.h
++
++ at abstract: OS independent list functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDLIST_H___
++#define __SDLIST_H___
++
++/* list functions */
++/* pointers for the list */
++typedef struct _SDLIST {
++ struct _SDLIST *pPrev;
++ struct _SDLIST *pNext;
++}SDLIST, *PSDLIST;
++/*
++ * SDLIST_INIT , circular list
++*/
++#define SDLIST_INIT(pList)\
++ {(pList)->pPrev = pList; (pList)->pNext = pList;}
++#define SDLIST_INIT_DECLARE(List)\
++ SDLIST List = {&List, &List}
++
++
++#define SDLIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
++#define SDLIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
++#define SDLIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
++/*
++ * SDITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
++ * NOT: do not use this function if the items in the list are deleted inside the
++ * iteration loop
++*/
++#define SDITERATE_OVER_LIST(pStart, pTemp) \
++ for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
++
++
++/* safe iterate macro that allows the item to be removed from the list
++ * the iteration continues to the next item in the list
++ */
++#define SDITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \
++{ \
++ PSDLIST pTemp; \
++ pTemp = (pStart)->pNext; \
++ while (pTemp != (pStart)) { \
++ (pItem) = CONTAINING_STRUCT(pTemp,st,offset); \
++ pTemp = pTemp->pNext; \
++
++#define SDITERATE_END }}
++
++/*
++ * SDListInsertTail - insert pAdd to the end of the list
++*/
++static INLINE PSDLIST SDListInsertTail(PSDLIST pList, PSDLIST pAdd) {
++ /* this assert catches when an item is added twice */
++ DBG_ASSERT(pAdd->pNext != pList);
++ /* insert at tail */
++ pAdd->pPrev = pList->pPrev;
++ pAdd->pNext = pList;
++ pList->pPrev->pNext = pAdd;
++ pList->pPrev = pAdd;
++ return pAdd;
++}
++
++/*
++ * SDListInsertHead - insert pAdd into the head of the list
++*/
++static INLINE PSDLIST SDListInsertHead(PSDLIST pList, PSDLIST pAdd) {
++ /* this assert catches when an item is added twice */
++ DBG_ASSERT(pAdd->pPrev != pList);
++ /* insert at head */
++ pAdd->pPrev = pList;
++ pAdd->pNext = pList->pNext;
++ pList->pNext->pPrev = pAdd;
++ pList->pNext = pAdd;
++ return pAdd;
++}
++
++#define SDListAdd(pList,pItem) SDListInsertHead((pList),(pItem))
++/*
++ * SDListRemove - remove pDel from list
++*/
++static INLINE PSDLIST SDListRemove(PSDLIST pDel) {
++ pDel->pNext->pPrev = pDel->pPrev;
++ pDel->pPrev->pNext = pDel->pNext;
++ /* point back to itself just to be safe, incase remove is called again */
++ pDel->pNext = pDel;
++ pDel->pPrev = pDel;
++ return pDel;
++}
++
++/*
++ * SDListRemoveItemFromHead - get a list item from the head
++*/
++static INLINE PSDLIST SDListRemoveItemFromHead(PSDLIST pList) {
++ PSDLIST pItem = NULL;
++ if (pList->pNext != pList) {
++ pItem = pList->pNext;
++ /* remove the first item from head */
++ SDListRemove(pItem);
++ }
++ return pItem;
++}
++#endif /* __SDLIST_H___ */
+Index: linux-2.6.22/include/linux/sdio/sdio_hcd_defs.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/sdio_hcd_defs.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,215 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_defs.h
++
++ at abstract: host controller driver definitions
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_HCD_DEFS_H___
++#define __SDIO_HCD_DEFS_H___
++
++ /* write protect switch position data */
++typedef UINT8 SDCONFIG_WP_VALUE;
++
++ /* HC commands */
++#define SDCONFIG_SEND_INIT_CLOCKS (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_PUT | 1)
++#define SDCONFIG_SDIO_INT_CTRL (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_PUT | 2)
++#define SDCONFIG_SDIO_REARM_INT (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_NONE | 3)
++#define SDCONFIG_BUS_MODE_CTRL (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_BOTH | 4)
++#define SDCONFIG_POWER_CTRL (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_PUT | 5)
++#define SDCONFIG_GET_WP (SDCONFIG_FLAGS_HC_CONFIG | SDCONFIG_FLAGS_DATA_GET | 6)
++
++ /* slot init clocks control */
++typedef struct _SDCONFIG_INIT_CLOCKS_DATA {
++ UINT16 NumberOfClocks; /* number of clocks to issue in the current bus mode*/
++}SDCONFIG_INIT_CLOCKS_DATA, *PSDCONFIG_INIT_CLOCKS_DATA;
++
++/* slot power control */
++typedef struct _SDCONFIG_POWER_CTRL_DATA {
++ BOOL SlotPowerEnable; /* turn on/off slot power */
++ SLOT_VOLTAGE_MASK SlotPowerVoltageMask; /* slot power voltage mask */
++}SDCONFIG_POWER_CTRL_DATA, *PSDCONFIG_POWER_CTRL_DATA;
++
++typedef UINT8 SDIO_IRQ_MODE_FLAGS;
++/* SDIO Interrupt control */
++typedef struct _SDCONFIG_SDIO_INT_CTRL_DATA {
++ BOOL SlotIRQEnable; /* turn on/off Slot IRQ detection */
++ SDIO_IRQ_MODE_FLAGS IRQDetectMode; /* slot IRQ detect mode , only valid if Enabled = TRUE */
++#define IRQ_DETECT_RAW 0x00
++#define IRQ_DETECT_MULTI_BLK 0x01
++#define IRQ_DETECT_4_BIT 0x02
++#define IRQ_DETECT_1_BIT 0x04
++#define IRQ_DETECT_SPI 0x08
++}SDCONFIG_SDIO_INT_CTRL_DATA, *PSDCONFIG_SDIO_INT_CTRL_DATA;
++
++/* card insert */
++#define EVENT_HCD_ATTACH 1
++/* card remove */
++#define EVENT_HCD_DETACH 2
++/* card slot interrupt */
++#define EVENT_HCD_SDIO_IRQ_PENDING 3
++/* transfer done */
++#define EVENT_HCD_TRANSFER_DONE 4
++/* (internal use only) */
++#define EVENT_HCD_CD_POLLING 5
++/* NOP */
++#define EVENT_HCD_NOP 0
++
++/* attrib_flags */
++#define SDHCD_ATTRIB_SUPPORTS_POWER 0x0001 /* host controller driver supports power managment */
++#define SDHCD_ATTRIB_BUS_1BIT 0x0002 /* SD Native 1 - bit mode */
++#define SDHCD_ATTRIB_BUS_4BIT 0x0004 /* SD Native 4 - bit mode */
++#define SDHCD_ATTRIB_BUS_SPI 0x0008 /* SPI mode capable */
++#define SDHCD_ATTRIB_READ_WAIT 0x0010 /* read wait supported (SD-only) */
++#define SDHCD_ATTRIB_MULTI_BLK_IRQ 0x0020 /* interrupts between multi-block capable (SD-only) */
++#define SDHCD_ATTRIB_BUS_MMC8BIT 0x0040 /* MMC 8-bit */
++#define SDHCD_ATTRIB_SLOT_POLLING 0x0080 /* requires slot polling for Card Detect */
++#define SDHCD_ATTRIB_POWER_SWITCH 0x0100 /* host has power switch control, must be set if SPI
++ mode can be switched to 1 or 4 bit mode */
++#define SDHCD_ATTRIB_NO_SPI_CRC 0x0200 /* when in SPI mode,
++ host wants to run without SPI CRC */
++#define SDHCD_ATTRIB_AUTO_CMD12 0x0400 /* host controller supports auto CMD12 */
++#define SDHCD_ATTRIB_NO_4BIT_IRQ 0x0800 /* host controller does not support 4 bit IRQ mode*/
++#define SDHCD_ATTRIB_RAW_MODE 0x1000 /* host controller is a raw mode hcd*/
++#define SDHCD_ATTRIB_SD_HIGH_SPEED 0x2000 /* host controller supports SD high speed interface */
++#define SDHCD_ATTRIB_MMC_HIGH_SPEED 0x4000 /* host controller supports MMC high speed interface */
++
++#define IS_CARD_PRESENT(pHcd) ((pHcd)->CardProperties.Flags & CARD_TYPE_MASK)
++#define SET_CURRENT_REQUEST(pHcd,Req) (pHcd)->pCurrentRequest = (Req)
++#define IS_HCD_RAW(pHcd) ((pHcd)->Attributes & SDHCD_ATTRIB_RAW_MODE)
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get a pointer to the current bus request for a host controller
++
++ @function name: GET_CURRENT_REQUEST
++ @prototype: PSDREQUEST GET_CURRENT_REQUEST (PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - host structure
++
++ @return: current SD/SDIO bus request being worked on
++
++ @notes: Implemented as a macro. This macro returns the current SD request that is
++ being worked on.
++
++ @example: getting the current request:
++ pReq = GET_CURRENT_REQUEST(&pHct->Hcd);
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define GET_CURRENT_REQUEST(pHcd) (pHcd)->pCurrentRequest
++#define GET_CURRENT_BUS_WIDTH(pHcd) SDCONFIG_GET_BUSWIDTH((pHcd)->CardProperties.BusMode)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Get host controller's current operational bus clock
++
++ @function name: SDHCD_GET_OPER_CLOCK
++ @prototype: SD_BUSCLOCK_RATE SDHCD_GET_OPER_CLOCK(PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - the registered host structure
++
++ @output: none
++
++ @return: clock rate
++
++ @notes: Implemented as a macro. Returns the current bus clock rate.
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDHCD_GET_OPER_CLOCK(pHcd) (pHcd)->CardProperties.OperBusClock
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Is host controller operating in SPI mode
++
++ @function name: IS_HCD_BUS_MODE_SPI
++ @prototype: BOOL IS_HCD_BUS_MODE_SPI (PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - host structure
++
++ @return: TRUE if in SPI mode
++
++ @notes: Implemented as a macro. Host controllers that operate in SPI mode
++ dynamically can use this macro to check for SPI operation.
++
++ @example: testing for SPI mode:
++ if (IS_HCD_BUS_MODE_SPI(&pHct->Hcd)) {
++ .. in spi mode
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define IS_HCD_BUS_MODE_SPI(pHcd) (GET_CURRENT_BUS_WIDTH(pHcd) == SDCONFIG_BUS_WIDTH_SPI)
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Is host controller using SPI in non-CRC mode
++
++ @function name: IS_HCD_BUS_MODE_SPI_NO_CRC
++ @prototype: BOOL IS_HCD_BUS_MODE_SPI_NO_CRC(PSDHCD pHcd)
++ @category: HD_Reference
++
++ @input: pHcd - host structure
++
++ @return: TRUE if CRC mode is off
++
++ @notes: Implemented as a macro. SPI-capable cards and systems can operate in
++ non-CRC protected mode. In this mode the host controller should ignore
++ CRC fields and/or disable CRC generation when issuing command or data
++ packets. This option is useful for software based SPI mode where CRC
++ should be turned off in order to reduce processing overhead.
++
++ @example: test for non-CRC SPI mode:
++ if (IS_HCD_BUS_MODE_SPI_NO_CRC(&pHct->Hcd)) {
++ .. disable CRC checking in hardware.
++ }
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define IS_HCD_BUS_MODE_SPI_NO_CRC(pHcd) ((pHcd)->CardProperties.BusMode & \
++ SDCONFIG_BUS_MODE_SPI_NO_CRC)
++
++typedef UINT8 SDHCD_RESPONSE_CHECK_MODE;
++/* have SDIO core check the response token and see if it is okay to continue with
++ * the data portion */
++#define SDHCD_CHECK_DATA_TRANS_OK 0x01
++/* have SDIO core check the SPI token received */
++#define SDHCD_CHECK_SPI_TOKEN 0x02
++
++/* prototypes */
++/* for HCD use */
++SDIO_STATUS SDIO_RegisterHostController(PSDHCD pHcd);
++SDIO_STATUS SDIO_UnregisterHostController(PSDHCD pHcd);
++SDIO_STATUS SDIO_HandleHcdEvent(PSDHCD pHcd, HCD_EVENT Event);
++SDIO_STATUS SDIO_CheckResponse(PSDHCD pHcd, PSDREQUEST pReq, SDHCD_RESPONSE_CHECK_MODE CheckMode);
++SDIO_STATUS SDIO_BusAddOSDevice(PSDDMA_DESCRIPTION pDma, POS_PNPDRIVER pDriver, POS_PNPDEVICE pDevice);
++void SDIO_BusRemoveOSDevice(POS_PNPDRIVER pDriver, POS_PNPDEVICE pDevice);
++
++#endif /* __SDIO_BUSDRIVER_H___ */
+Index: linux-2.6.22/include/linux/sdio/sdio_lib.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/include/linux/sdio/sdio_lib.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,262 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_lib.h
++
++ at abstract: SDIO Library include
++
++#notes:
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_LIB_H___
++#define __SDIO_LIB_H___
++
++#define CMD52_DO_READ FALSE
++#define CMD52_DO_WRITE TRUE
++
++ /* read/write macros to any function */
++#define Cmd52WriteByteFunc(pDev,Func,Address,pValue) \
++ SDLIB_IssueCMD52((pDev),(Func),(Address),(pValue),1,CMD52_DO_WRITE)
++#define Cmd52ReadByteFunc(pDev,Func,Address,pValue) \
++ SDLIB_IssueCMD52((pDev),(Func),(Address),pValue,1,CMD52_DO_READ)
++#define Cmd52ReadMultipleFunc(pDev,Func, Address, pBuf,length) \
++ SDLIB_IssueCMD52((pDev),(Func),(Address),(pBuf),(length),CMD52_DO_READ)
++
++ /* macros to access common registers */
++#define Cmd52WriteByteCommon(pDev, Address, pValue) \
++ Cmd52WriteByteFunc((pDev),0,(Address),(pValue))
++#define Cmd52ReadByteCommon(pDev, Address, pValue) \
++ Cmd52ReadByteFunc((pDev),0,(Address),(pValue))
++#define Cmd52ReadMultipleCommon(pDev, Address, pBuf,length) \
++ Cmd52ReadMultipleFunc((pDev),0,(Address),(pBuf),(length))
++
++#define SDLIB_SetupCMD52RequestAsync(f,a,w,wd,pR) \
++{ \
++ SDLIB_SetupCMD52Request((f),(a),(w),(wd),(pR)); \
++ (pR)->Flags |= SDREQ_FLAGS_TRANS_ASYNC; \
++}
++
++ /* a message block */
++typedef struct _SDMESSAGE_BLOCK {
++ SDLIST SDList; /* list entry */
++ INT MessageLength; /* number of bytes in this message */
++ UINT8 MessageStart[1]; /* message start */
++}SDMESSAGE_BLOCK, *PSDMESSAGE_BLOCK;
++
++ /* message queue */
++typedef struct _SDMESSAGE_QUEUE {
++ SDLIST MessageList; /* message list */
++ OS_CRITICALSECTION MessageCritSection; /* message semaphore */
++ SDLIST FreeMessageList; /* free message list */
++ INT MaxMessageLength; /* max message block length */
++}SDMESSAGE_QUEUE, *PSDMESSAGE_QUEUE;
++
++/* internal library prototypes that can be proxied */
++SDIO_STATUS _SDLIB_IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUINT8 pData,
++ INT ByteCount,
++ BOOL Write);
++SDIO_STATUS _SDLIB_FindTuple(PSDDEVICE pDevice,
++ UINT8 Tuple,
++ UINT32 *pTupleScanAddress,
++ PUINT8 pBuffer,
++ UINT8 *pLength);
++SDIO_STATUS _SDLIB_IssueConfig(PSDDEVICE pDevice,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length);
++void _SDLIB_PrintBuffer(PUCHAR pBuffer, INT Length,PTEXT pDescription);
++void _SDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest);
++SDIO_STATUS _SDLIB_SetFunctionBlockSize(PSDDEVICE pDevice,
++ UINT16 BlockSize);
++
++SDIO_STATUS _SDLIB_GetDefaultOpCurrent(PSDDEVICE pDevice,
++ SD_SLOT_CURRENT *pOpCurrent);
++PSDMESSAGE_QUEUE _CreateMessageQueue(INT MaxMessages, INT MaxMessageLength);
++void _DeleteMessageQueue(PSDMESSAGE_QUEUE pQueue);
++SDIO_STATUS _PostMessage(PSDMESSAGE_QUEUE pQueue, PVOID pMessage, INT MessageLength);
++SDIO_STATUS _GetMessage(PSDMESSAGE_QUEUE pQueue, PVOID pData, INT *pBufferLength);
++
++#ifdef CTSYSTEM_NO_FUNCTION_PROXIES
++ /* OS port requires no proxy functions, use methods directly from the library */
++#define SDLIB_IssueCMD52 _SDLIB_IssueCMD52
++#define SDLIB_SetupCMD52Request _SDLIB_SetupCMD52Request
++#define SDLIB_FindTuple _SDLIB_FindTuple
++#define SDLIB_IssueConfig _SDLIB_IssueConfig
++#define SDLIB_SetFunctionBlockSize _SDLIB_SetFunctionBlockSize
++#define SDLIB_GetDefaultOpCurrent _SDLIB_GetDefaultOpCurrent
++#define SDLIB_CreateMessageQueue _CreateMessageQueue
++#define SDLIB_DeleteMessageQueue _DeleteMessageQueue
++#define SDLIB_PostMessage _PostMessage
++#define SDLIB_GetMessage _GetMessage
++#define SDLIB_PrintBuffer _SDLIB_PrintBuffer
++#else
++
++/* proxied versions */
++SDIO_STATUS SDLIB_IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUINT8 pData,
++ INT ByteCount,
++ BOOL Write);
++
++void SDLIB_SetupCMD52Request(UINT8 FuncNo,
++ UINT32 Address,
++ BOOL Write,
++ UINT8 WriteData,
++ PSDREQUEST pRequest);
++
++SDIO_STATUS SDLIB_FindTuple(PSDDEVICE pDevice,
++ UINT8 Tuple,
++ UINT32 *pTupleScanAddress,
++ PUINT8 pBuffer,
++ UINT8 *pLength);
++
++SDIO_STATUS SDLIB_IssueConfig(PSDDEVICE pDevice,
++ SDCONFIG_COMMAND Command,
++ PVOID pData,
++ INT Length);
++
++SDIO_STATUS SDLIB_SetFunctionBlockSize(PSDDEVICE pDevice,
++ UINT16 BlockSize);
++
++void SDLIB_PrintBuffer(PUCHAR pBuffer, INT Length,PTEXT pDescription);
++
++SDIO_STATUS SDLIB_GetDefaultOpCurrent(PSDDEVICE pDevice, SD_SLOT_CURRENT *pOpCurrent);
++
++PSDMESSAGE_QUEUE SDLIB_CreateMessageQueue(INT MaxMessages, INT MaxMessageLength);
++
++void SDLIB_DeleteMessageQueue(PSDMESSAGE_QUEUE pQueue);
++
++SDIO_STATUS SDLIB_PostMessage(PSDMESSAGE_QUEUE pQueue, PVOID pMessage, INT MessageLength);
++
++SDIO_STATUS SDLIB_GetMessage(PSDMESSAGE_QUEUE pQueue, PVOID pData, INT *pBufferLength);
++#endif /* CTSYSTEM_NO_FUNCTION_PROXIES */
++
++
++SDIO_STATUS SDLIB_OSCreateHelper(POSKERNEL_HELPER pHelper,
++ PHELPER_FUNCTION pFunction,
++ PVOID pContext);
++
++void SDLIB_OSDeleteHelper(POSKERNEL_HELPER pHelper);
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Check message queue is empty
++
++ @function name: SDLIB_IsQueueEmpty
++ @prototype: BOOL SDLIB_IsQueueEmpty(PSDMESSAGE_QUEUE pQueue)
++ @category: Support_Reference
++
++ @input: pQueue - message queue to check
++
++ @return: TRUE if empty else false
++
++ @see also: SDLIB_CreateMessageQueue
++
++ @example: Check message queue :
++ if (SDLIB_IsQueueEmpty(pInstance->pQueue)) {
++ .. message queue is empty
++ }
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static INLINE BOOL SDLIB_IsQueueEmpty(PSDMESSAGE_QUEUE pQueue) {
++ return SDLIST_IS_EMPTY(&pQueue->MessageList);
++}
++
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Issue an I/O abort request
++
++ @function name: SDLIB_IssueIOAbort
++ @prototype: SDIO_STATUS SDLIB_IssueIOAbort(PSDDEVICE pDevice)
++ @category: PD_Reference
++
++ @input: pDevice - the device that is the target of this request
++
++ @return: SDIO_STATUS
++
++ @notes: This procedure can be called to issue an I/O abort request to an I/O function.
++ This procedure cannot be used to abort a data (block) transfer already in progress.
++ It is intended to be used when a data (block) transfer completes with an error and only if
++ the I/O function requires an abort action. Some I/O functions may automatically
++ recover from such failures and not require this action. This function issues
++ the abort command synchronously and can potentially block.
++ If an async request is required, you must allocate a request and use
++ SDLIB_SetupIOAbortAsync() to prepare the request.
++
++ @example: Issuing I/O Abort synchronously :
++ .. check status from last block operation:
++ if (status == SDIO_STATUS_BUS_READ_TIMEOUT) {
++ .. on failure, issue I/O abort
++ status2 = SDLIB_IssueIOAbort(pDevice);
++ }
++ Issuing I/O Abort asynchronously:
++ ... allocate a request
++ ... setup the request:
++ SDLIB_SetupIOAbortAsync(pDevice,pReq);
++ pReq->pCompletion = myIOAbortCompletion;
++ pReq->pCompleteContext = pDevice;
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice,pReq);
++
++ @see also: SDLIB_SetupIOAbortAsync
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static INLINE SDIO_STATUS SDLIB_IssueIOAbort(PSDDEVICE pDevice) {
++ UINT8 value = SDDEVICE_GET_SDIO_FUNCNO(pDevice);
++ return Cmd52WriteByteCommon(pDevice,0x06,&value);
++}
++
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ @function: Setup an I/O abort request for async operation
++
++ @function name: SDLIB_SetupIOAbortAsync
++ @prototype: SDLIB_SetupIOAbortAsync(PSDDEVICE pDevice, PSDREQUEST pRequest)
++ @category: PD_Reference
++
++ @input: pDevice - the device that is the target of this request
++ pRequest - the request to set up
++
++ @see also: SDLIB_IssueIOAbort
++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define SDLIB_SetupIOAbortAsync(pDevice, pReq) \
++ SDLIB_SetupCMD52RequestAsync(0,0x06,TRUE,SDDEVICE_GET_SDIO_FUNCNO(pDevice),(pReq))
++
++
++#endif /* __SDIO_LIB_H___*/
+Index: linux-2.6.22/arch/arm/Kconfig
+===================================================================
+--- linux-2.6.22.orig/arch/arm/Kconfig 2007-11-08 15:42:31.000000000 +0100
++++ linux-2.6.22/arch/arm/Kconfig 2007-11-08 15:47:58.000000000 +0100
+@@ -971,6 +971,8 @@
+
+ source "drivers/pnp/Kconfig"
+
++source "drivers/sdio/Kconfig"
++
+ source "drivers/block/Kconfig"
+
+ source "drivers/acorn/block/Kconfig"
Added: developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_ar6000_wlan.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_ar6000_wlan.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_ar6000_wlan.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,23501 @@
+---
+ drivers/pnp/Kconfig | 2
+ drivers/pnp/core.c | 4
+ drivers/pnp/driver.c | 2
+ drivers/sdio/function/wlan/Makefile | 4
+ drivers/sdio/function/wlan/ar6000/Makefile | 29
+ drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.c | 5752 ++++++++++
+ drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.h | 133
+ drivers/sdio/function/wlan/ar6000/bmi/Makefile | 1
+ drivers/sdio/function/wlan/ar6000/bmi/bmi.c | 473
+ drivers/sdio/function/wlan/ar6000/bmi/bmi_internal.h | 31
+ drivers/sdio/function/wlan/ar6000/hif/Makefile | 2
+ drivers/sdio/function/wlan/ar6000/hif/cf/Makefile | 11
+ drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.c | 1001 +
+ drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.h | 110
+ drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs_internal.h | 62
+ drivers/sdio/function/wlan/ar6000/hif/cf/hif.c | 390
+ drivers/sdio/function/wlan/ar6000/hif/cf/hif_internal.h | 78
+ drivers/sdio/function/wlan/ar6000/hif/hif.c | 664 +
+ drivers/sdio/function/wlan/ar6000/hif/hif_internal.h | 85
+ drivers/sdio/function/wlan/ar6000/htc/Makefile | 5
+ drivers/sdio/function/wlan/ar6000/htc/htc.c | 433
+ drivers/sdio/function/wlan/ar6000/htc/htc_events.c | 1056 +
+ drivers/sdio/function/wlan/ar6000/htc/htc_internal.h | 464
+ drivers/sdio/function/wlan/ar6000/htc/htc_recv.c | 209
+ drivers/sdio/function/wlan/ar6000/htc/htc_send.c | 395
+ drivers/sdio/function/wlan/ar6000/htc/htc_utils.c | 374
+ drivers/sdio/function/wlan/ar6000/include/AR6000_bmi.h | 136
+ drivers/sdio/function/wlan/ar6000/include/AR6000_gpio.h | 39
+ drivers/sdio/function/wlan/ar6000/include/AR6000_version.h | 46
+ drivers/sdio/function/wlan/ar6000/include/app/dset.h | 77
+ drivers/sdio/function/wlan/ar6000/include/ar6000_api.h | 84
+ drivers/sdio/function/wlan/ar6000/include/athdefs.h | 82
+ drivers/sdio/function/wlan/ar6000/include/athdrv.h | 598 +
+ drivers/sdio/function/wlan/ar6000/include/athtypes.h | 43
+ drivers/sdio/function/wlan/ar6000/include/bmi.h | 76
+ drivers/sdio/function/wlan/ar6000/include/dset_api.h | 49
+ drivers/sdio/function/wlan/ar6000/include/gpio_api.h | 64
+ drivers/sdio/function/wlan/ar6000/include/hif.h | 207
+ drivers/sdio/function/wlan/ar6000/include/host_version.h | 48
+ drivers/sdio/function/wlan/ar6000/include/htc.h | 120
+ drivers/sdio/function/wlan/ar6000/include/hw/mbox_host_reg.h | 416
+ drivers/sdio/function/wlan/ar6000/include/hw/mbox_reg.h | 550
+ drivers/sdio/function/wlan/ar6000/include/hw/mc_reg.h | 1129 +
+ drivers/sdio/function/wlan/ar6000/include/hw/rtc_reg.h | 1204 ++
+ drivers/sdio/function/wlan/ar6000/include/ieee80211.h | 333
+ drivers/sdio/function/wlan/ar6000/include/ieee80211_ioctl.h | 120
+ drivers/sdio/function/wlan/ar6000/include/ieee80211_node.h | 74
+ drivers/sdio/function/wlan/ar6000/include/osapi.h | 63
+ drivers/sdio/function/wlan/ar6000/include/osapi_linux.h | 167
+ drivers/sdio/function/wlan/ar6000/include/queue.h | 552
+ drivers/sdio/function/wlan/ar6000/include/wlan_api.h | 90
+ drivers/sdio/function/wlan/ar6000/include/wmi.h | 1141 +
+ drivers/sdio/function/wlan/ar6000/include/wmi_api.h | 173
+ drivers/sdio/function/wlan/ar6000/include/wmi_host.h | 75
+ drivers/sdio/function/wlan/ar6000/include/wmix.h | 197
+ drivers/sdio/function/wlan/ar6000/wlan/Makefile | 2
+ drivers/sdio/function/wlan/ar6000/wlan/wlan_node.c | 285
+ drivers/sdio/function/wlan/ar6000/wlan/wlan_recv_beacon.c | 169
+ drivers/sdio/function/wlan/ar6000/wlan/wlan_utils.c | 56
+ drivers/sdio/function/wlan/ar6000/wmi/wmi.c | 2871 ++++
+ 60 files changed, 23099 insertions(+), 7 deletions(-)
+
+Index: linux-2.6.22/drivers/sdio/function/wlan/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,4 @@
++#
++# SDIO wlan ar600 card function driver
++#
++obj-$(CONFIG_SDIO_AR6000_WLAN) += ar6000/
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,29 @@
++#
++# AR6K Kernel Module makefile.
++#
++REV ?= 2
++
++
++EXTRA_CFLAGS += -DLINUX -DDEBUG -D__KERNEL__ -DHTC_RAW_INTERFACE \
++ -DSEND_EVENT_TO_APP#\
++ -DMULTIPLE_FRAMES_PER_INTERRUPT -DAR6000REV$(REV) \
++ -DBLOCK_TX_PATH_FLAG \
++
++EXTRA_CFLAGS += -DKERNEL_2_6
++
++obj-dir := /bmi /htc /hif
++
++obj-$(CONFIG_SDIO_AR6000_WLAN) += ar6000.o
++ar6000-objs += htc/htc.o \
++ htc/htc_send.o \
++ htc/htc_recv.o \
++ htc/htc_utils.o \
++ htc/htc_events.o \
++ bmi/bmi.o \
++ hif/hif.o \
++ ar6000/ar6000_drv.o \
++ wmi/wmi.o \
++ wlan/wlan_node.o \
++ wlan/wlan_recv_beacon.o \
++ wlan/wlan_utils.o
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/bmi.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/bmi.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * BMI declarations and prototypes
++ */
++
++#ifndef _BMI_H_
++#define _BMI_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++/* Header files */
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/hif.h"
++#include "../include/osapi.h"
++
++void
++BMIInit(void);
++
++A_STATUS
++BMIDone(HIF_DEVICE *device);
++
++A_STATUS
++BMIGetTargetId(HIF_DEVICE *device, A_UINT32 *id);
++
++A_STATUS
++BMIReadMemory(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length);
++
++A_STATUS
++BMIWriteMemory(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length);
++
++A_STATUS
++BMIExecute(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 *param);
++
++A_STATUS
++BMISetAppStart(HIF_DEVICE *device,
++ A_UINT32 address);
++
++A_STATUS
++BMIReadSOCRegister(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 *param);
++
++A_STATUS
++BMIWriteSOCRegister(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 param);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _BMI_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,133 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the AR6000 linux driver.
++ *
++ */
++
++#ifndef _AR6000_H_
++#define _AR6000_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define MAX_AR6000 1
++#define AR6000_MAX_RX_BUFFERS 16
++#define AR6000_BUFFER_SIZE 1552
++#define AR6000_DATA_OFFSET 64
++#define AR6000_TX_TIMEOUT 10
++#define AR6000_ETH_ADDR_LEN 6
++#define AR6000_MAX_ENDPOINTS 4
++#define MAX_NODE_NUM 15
++#define MAX_COOKIE_NUM 150
++
++struct ar_wep_key {
++ A_UINT8 arKeyIndex;
++ A_UINT8 arKeyLen;
++ A_UINT8 arKey[64];
++} ;
++
++struct ar_node_mapping {
++ A_UINT8 macAddress[6];
++ A_UINT8 epId;
++ A_UINT8 txPending;
++};
++
++struct ar_cookie {
++ A_UINT32 arc_bp[2]; /* Must be first field */
++ struct ar_cookie *arc_list_next;
++};
++
++typedef struct ar6_softc {
++ struct net_device *arNetDev; /* net_device pointer */
++ void *arWmi;
++ int arTxPending[AR6000_MAX_ENDPOINTS];
++ int arTotalTxDataPending;
++ A_UINT8 arNumDataEndPts;
++ A_BOOL arWmiEnabled;
++ A_BOOL arWmiReady;
++ A_BOOL arConnected;
++ void *arHtcTarget;
++ void *arHifDevice;
++ spinlock_t arLock;
++ struct semaphore arSem;
++ int arRxBuffers[AR6000_MAX_ENDPOINTS];
++ int arSsidLen;
++ u_char arSsid[32];
++ A_UINT8 arNetworkType;
++ A_UINT8 arDot11AuthMode;
++ A_UINT8 arAuthMode;
++ A_UINT8 arPairwiseCrypto;
++ A_UINT8 arPairwiseCryptoLen;
++ A_UINT8 arGroupCrypto;
++ A_UINT8 arGroupCryptoLen;
++ A_UINT8 arDefTxKeyIndex;
++ struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1];
++ A_UINT8 arBssid[6];
++ A_UINT8 arReqBssid[6];
++ A_UINT16 arChannelHint;
++ A_UINT16 arBssChannel;
++ A_UINT16 arListenInterval;
++ struct ar6000_version arVersion;
++ A_INT8 arRssi;
++ A_UINT8 arTxPwr;
++ A_BOOL arTxPwrSet;
++ A_INT32 arBitRate;
++ struct net_device_stats arNetStats;
++ struct iw_statistics arIwStats;
++ A_INT8 arNumChannels;
++ A_UINT16 arChannelList[32];
++ A_UINT32 arRegCode;
++ A_BOOL statsUpdatePending;
++ TARGET_STATS arTargetStats;
++ A_INT8 arMaxRetries;
++ A_UINT8 arPhyCapability;
++ AR6000_WLAN_STATE arWlanState;
++ struct ar_node_mapping arNodeMap[MAX_NODE_NUM];
++ A_UINT8 arIbssPsEnable;
++ A_UINT8 arNodeNum;
++ A_UINT8 arNexEpId;
++ struct ar_cookie *arCookieList;
++ A_BOOL arConnectPending;
++} AR_SOFTC_T;
++
++struct ar_giwscan_param {
++ char *current_ev;
++ char *end_buf;
++ A_BOOL firstPass;
++};
++
++#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++)
++
++#define AR6000_SPIN_LOCK(lock, param) do { \
++ if (irqs_disabled()) { \
++ AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \
++ } \
++ spin_lock_bh(lock); \
++} while (0)
++
++#define AR6000_SPIN_UNLOCK(lock, param) do { \
++ if (irqs_disabled()) { \
++ AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \
++ } \
++ spin_unlock_bh(lock); \
++} while (0)
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _AR6000_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ar6000_api.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ar6000_api.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the API to access the OS dependent atheros host driver
++ * by the WMI or WLAN generic modules.
++ *
++ */
++
++#ifndef _AR6000_API_H_
++#define _AR6000_API_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++struct ar6_softc;
++
++void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap);
++A_UINT8 ar6000_iptos_to_userPriority(A_UINT8 *pkt);
++A_STATUS ar6000_control_tx(void *devt, void *osbuf, int endPt);
++void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
++ A_UINT8 *bssid, A_UINT16 listenInterval,
++ A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
++ A_UINT8 assocRespLen,A_UINT8 *assocInfo);
++void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
++ A_UINT8 *bssid, A_UINT8 assocRespLen,
++ A_UINT8 *assocInfo);
++void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
++ A_BOOL ismcast);
++void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
++void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
++void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
++void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
++void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
++ WMI_NEIGHBOR_INFO *info);
++void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
++void ar6000_scanComplete_event(struct ar6_softc *ar);
++void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats);
++void ar6000_rssiThreshold_event(struct ar6_softc *, WMI_RSSI_THRESHOLD_VAL);
++void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
++void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
++ A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
++
++void
++ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
++
++void
++ar6000_roam_data_event(struct ar6_softc **ar, WMI_TARGET_ROAM_DATA *p);
++
++void ar6000_dset_open_req(void *devt,
++ A_UINT32 id,
++ A_UINT32 targ_handle,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg);
++void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
++void ar6000_dset_data_req(void *devt,
++ A_UINT32 access_cookie,
++ A_UINT32 offset,
++ A_UINT32 length,
++ A_UINT32 targ_buf,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg);
++
++void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
++void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
++void ar6000_gpio_ack_rx(void);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _AR6000_API_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athdrv.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athdrv.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,598 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the AR6000 linux driver.
++ *
++ */
++
++#ifndef _ATHDRV_H_
++#define _ATHDRV_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*
++ * There are two types of ioctl's here: Standard ioctls and
++ * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed
++ * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The
++ * arguments for every XIOCTL starts with a 32-bit command word
++ * that is used to select which extended ioctl is in use. After
++ * the command word are command-specific arguments.
++ */
++
++/* Linux standard Wireless Extensions, private ioctl interfaces */
++#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0)
++#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+1)
++#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+2)
++#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+3)
++#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+4)
++#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+5)
++#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+6)
++#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+6)
++#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+7)
++#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+8)
++//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10)
++#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+9)
++
++
++
++/* ====WMI Ioctls==== */
++/*
++ *
++ * Many ioctls simply provide WMI services to application code:
++ * an application makes such an ioctl call with a set of arguments
++ * that are packaged into the corresponding WMI message, and sent
++ * to the Target.
++ */
++
++#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+10)
++/*
++ * arguments:
++ * ar6000_version *revision
++ */
++
++#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+11)
++/*
++ * arguments:
++ * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
++ * uses: WMI_SET_POWER_MODE_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+12)
++/*
++ * arguments:
++ * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
++ * uses: WMI_SET_SCAN_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+13)
++/*
++ * arguments:
++ * UINT32 listenInterval
++ * uses: WMI_SET_LISTEN_INT_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+14)
++/*
++ * arguments:
++ * WMI_BSS_FILTER filter (see include/wmi.h)
++ * uses: WMI_SET_BSS_FILTER_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16)
++/*
++ * arguments:
++ * WMI_CHANNEL_PARAMS_CMD chParams
++ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17)
++/*
++ * arguments:
++ * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
++ * uses: WMI_SETPROBED_SSID_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18)
++/*
++ * arguments:
++ * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
++ * uses: WMI_SET_POWER_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19)
++/*
++ * arguments:
++ * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
++ * uses: WMI_ADD_BAD_AP_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20)
++/*
++ * arguments:
++ * ar6000_queuereq queueRequest (see below)
++ */
++
++#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21)
++/*
++ * arguments:
++ * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
++ * uses: WMI_CREATE_PSTREAM_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22)
++/*
++ * arguments:
++ * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
++ * uses: WMI_DELETE_PSTREAM_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_LINKTHRESHOLD (SIOCIWFIRSTPRIV+23)
++/*
++ * arguments:
++ * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
++ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
++/*
++ * arguments:
++ * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
++ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25)
++/*
++ * arguments:
++ * TARGET_STATS *targetStats (see below)
++ * uses: WMI_GET_STATISTICS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26)
++/*
++ * arguments:
++ * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
++ * uses: WMI_SET_ASSOC_INFO_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27)
++/*
++ * arguments:
++ * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
++ * uses: WMI_SET_ACCESS_PARAMS_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28)
++/*
++ * arguments:
++ * UINT32 beaconMissTime
++ * uses: WMI_SET_BMISS_TIME_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29)
++/*
++ * arguments:
++ * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
++ * uses: WMI_SET_DISC_TIMEOUT_CMDID
++ */
++
++#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30)
++/*
++ * arguments:
++ * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
++ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
++ */
++
++/*
++ * There is a very small space available for driver-private
++ * wireless ioctls. In order to circumvent this limitation,
++ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
++ * single AR6000_IOCTL_EXTENDED ioctl.
++ */
++#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31)
++
++
++/* ====BMI Extended Ioctls==== */
++
++#define AR6000_XIOCTL_BMI_DONE 1
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
++ * uses: BMI_DONE
++ */
++
++#define AR6000_XIOCTL_BMI_READ_MEMORY 2
++/*
++ * arguments:
++ * union {
++ * struct {
++ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
++ * UINT32 address
++ * UINT32 length
++ * }
++ * char results[length]
++ * }
++ * uses: BMI_READ_MEMORY
++ */
++
++#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
++ * UINT32 address
++ * UINT32 length
++ * char data[length]
++ * uses: BMI_WRITE_MEMORY
++ */
++
++#define AR6000_XIOCTL_BMI_EXECUTE 4
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
++ * UINT32 TargetAddress
++ * UINT32 parameter
++ * uses: BMI_EXECUTE
++ */
++
++#define AR6000_XIOCTL_BMI_SET_APP_START 5
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
++ * UINT32 TargetAddress
++ * uses: BMI_SET_APP_START
++ */
++
++#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6
++/*
++ * arguments:
++ * union {
++ * struct {
++ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
++ * UINT32 TargetAddress, 32-bit aligned
++ * }
++ * UINT32 result
++ * }
++ * uses: BMI_READ_SOC_REGISTER
++ */
++
++#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7
++/*
++ * arguments:
++ * struct {
++ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
++ * UINT32 TargetAddress, 32-bit aligned
++ * UINT32 newValue
++ * }
++ * uses: BMI_WRITE_SOC_REGISTER
++ */
++
++#define AR6000_XIOCTL_BMI_TEST 8
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
++ * UINT32 address
++ * UINT32 length
++ * UINT32 count
++ */
++
++
++
++/* ====DataSet Extended Ioctls==== */
++
++#define AR6000_XIOCTL_WMI_DSET_WAIT_REQ 9
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_WMI_DSET_WAIT_REQ)
++ */
++
++#define AR6000_XIOCTL_WMI_DSET_OPEN_REPLY 10
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_WMI_DSET_OPEN_REPLY)
++ * dset_open_reply_t (see host/include/app/dset.h)
++ * uses: WMIX_DSETOPEN_REPLY_CMDID
++ */
++
++#define AR6000_XIOCTL_WMI_DSET_DATA_REPLY 11
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_WMI_DSET_DATA_REPLY)
++ * dset_data_reply_t (see host/include/app/dset.h)
++ * uses: WMIX_DSETDATA_REPLY_CMDID
++ */
++
++#define AR6000_XIOCTL_FORCE_TARGET_RESET 12
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
++ */
++
++
++#ifdef HTC_RAW_INTERFACE
++/* HTC Raw Interface Ioctls */
++#define AR6000_XIOCTL_HTC_RAW_OPEN 13
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_CLOSE 14
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_READ 15
++/*
++ * arguments:
++ * union {
++ * struct {
++ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
++ * UINT32 mailboxID
++ * UINT32 length
++ * }
++ * results[length]
++ * }
++ */
++
++#define AR6000_XIOCTL_HTC_RAW_WRITE 16
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
++ * UINT32 mailboxID
++ * UINT32 length
++ * char buffer[length]
++ */
++#endif /* HTC_RAW_INTERFACE */
++
++#define AR6000_XIOCTL_CHECK_TARGET_READY 17
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
++ */
++
++
++
++/* ====GPIO (General Purpose I/O) Extended Ioctls==== */
++
++#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
++ * ar6000_gpio_output_set_cmd_s (see below)
++ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INPUT_GET 19
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
++ * uses: WMIX_GPIO_INPUT_GET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_REGISTER_SET 20
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
++ * ar6000_gpio_register_cmd_s (see below)
++ * uses: WMIX_GPIO_REGISTER_SET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_REGISTER_GET 21
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
++ * ar6000_gpio_register_cmd_s (see below)
++ * uses: WMIX_GPIO_REGISTER_GET_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INTR_ACK 22
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
++ * ar6000_cpio_intr_ack_cmd_s (see below)
++ * uses: WMIX_GPIO_INTR_ACK_CMDID
++ */
++
++#define AR6000_XIOCTL_GPIO_INTR_WAIT 23
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
++ */
++
++
++
++/* ====more wireless commands==== */
++
++#define AR6000_XIOCTL_SET_ADHOC_BSSID 24
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
++ * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
++ */
++
++#define AR6000_XIOCTL_SET_OPT_MODE 25
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
++ * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
++ * uses: WMI_SET_OPT_MODE_CMDID
++ */
++
++#define AR6000_XIOCTL_OPT_SEND_FRAME 26
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
++ * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
++ * uses: WMI_OPT_TX_FRAME_CMDID
++ */
++
++#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL 27
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL)
++ * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
++ * uses: WMI_SET_BEACON_INT_CMDID
++ */
++
++
++#define IEEE80211_IOCTL_SETAUTHALG 28
++
++
++#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
++ * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
++ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
++ */
++
++
++#define AR6000_XIOCTL_SET_MAX_SP 30
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
++ * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
++ * uses: WMI_SET_MAX_SP_LEN_CMDID
++ */
++
++#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31
++
++#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32
++
++#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
++ * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
++ * WMI_SET_POWERSAVE_TIMERS_CMDID
++ */
++
++#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34
++/*
++ * arguments:
++ * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
++ */
++
++#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35
++typedef enum {
++ WLAN_DISABLED,
++ WLAN_ENABLED
++} AR6000_WLAN_STATE;
++/*
++ * arguments:
++ * enable/disable
++ */
++
++#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36
++
++/* used by AR6000_IOCTL_WMI_GETREV */
++struct ar6000_version {
++ A_UINT32 host_ver;
++ A_UINT32 target_ver;
++};
++
++/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
++struct ar6000_queuereq{
++ A_UINT8 trafficDirection;
++ A_UINT8 trafficClass;
++ A_INT8 queueNumber;
++};
++
++/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
++typedef struct targetStats_t {
++ A_UINT64 tx_packets;
++ A_UINT64 tx_bytes;
++ A_UINT64 tx_unicast_pkts;
++ A_UINT64 tx_unicast_bytes;
++ A_UINT64 tx_multicast_pkts;
++ A_UINT64 tx_multicast_bytes;
++ A_UINT64 tx_broadcast_pkts;
++ A_UINT64 tx_broadcast_bytes;
++ A_UINT64 tx_rts_success_cnt;
++ A_UINT64 tx_packet_per_ac[4];
++
++ A_UINT64 tx_errors;
++ A_UINT64 tx_failed_cnt;
++ A_UINT64 tx_retry_cnt;
++ A_UINT64 tx_rts_fail_cnt;
++ A_UINT64 rx_packets;
++ A_UINT64 rx_bytes;
++ A_UINT64 rx_unicast_pkts;
++ A_UINT64 rx_unicast_bytes;
++ A_UINT64 rx_multicast_pkts;
++ A_UINT64 rx_multicast_bytes;
++ A_UINT64 rx_broadcast_pkts;
++ A_UINT64 rx_broadcast_bytes;
++ A_UINT64 rx_fragment_pkt;
++
++ A_UINT64 rx_errors;
++ A_UINT64 rx_crcerr;
++ A_UINT64 rx_key_cache_miss;
++ A_UINT64 rx_decrypt_err;
++ A_UINT64 rx_duplicate_frames;
++
++ A_UINT64 tkip_local_mic_failure;
++ A_UINT64 tkip_counter_measures_invoked;
++ A_UINT64 tkip_replays;
++ A_UINT64 tkip_format_errors;
++ A_UINT64 ccmp_format_errors;
++ A_UINT64 ccmp_replays;
++
++ A_UINT64 power_save_failure_cnt;
++ A_INT16 noise_floor_calibation;
++
++ A_UINT64 cs_bmiss_cnt;
++ A_UINT64 cs_lowRssi_cnt;
++ A_UINT64 cs_connect_cnt;
++ A_UINT64 cs_disconnect_cnt;
++ A_UINT8 cs_aveBeacon_rssi;
++ A_UINT8 cs_lastRoam_msec;
++}TARGET_STATS;
++
++/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
++struct ar6000_gpio_output_set_cmd_s {
++ A_UINT32 set_mask;
++ A_UINT32 clear_mask;
++ A_UINT32 enable_mask;
++ A_UINT32 disable_mask;
++};
++
++/*
++ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
++ */
++struct ar6000_gpio_register_cmd_s {
++ A_UINT32 gpioreg_id;
++ A_UINT32 value;
++};
++
++/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
++struct ar6000_gpio_intr_ack_cmd_s {
++ A_UINT32 ack_mask;
++};
++
++/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
++struct ar6000_gpio_intr_wait_cmd_s {
++ A_UINT32 intr_mask;
++ A_UINT32 input_values;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _ATHDRV_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athtypes.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athtypes.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2003-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions of the basic atheros data types.
++ * It is used to map the data types in atheros files to a platform specific
++ * type.
++ *
++ */
++
++#ifndef _ATHTYPES_LINUX_H_
++#define _ATHTYPES_LINUX_H_
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#endif
++
++typedef int8_t A_INT8;
++typedef int16_t A_INT16;
++typedef int32_t A_INT32;
++typedef int64_t A_INT64;
++
++typedef u_int8_t A_UINT8;
++typedef u_int16_t A_UINT16;
++typedef u_int32_t A_UINT32;
++typedef u_int64_t A_UINT64;
++
++typedef int A_BOOL;
++typedef char A_CHAR;
++typedef unsigned char A_UCHAR;
++
++#endif /* _ATHTYPES_LINUX_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,333 @@
++/*-
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 ATheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * */
++#ifndef _NET80211_IEEE80211_H_
++#define _NET80211_IEEE80211_H_
++
++/*
++ * 802.11 protocol definitions.
++ */
++
++#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */
++/* is 802.11 address multicast/broadcast? */
++#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01)
++#define IEEE80211_ADDR_EQ(addr1, addr2) \
++ (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
++
++#define IEEE80211_KEYBUF_SIZE 16
++#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */
++
++/*
++ * NB: these values are ordered carefully; there are lots of
++ * of implications in any reordering. In particular beware
++ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
++ */
++#define IEEE80211_CIPHER_WEP 0
++#define IEEE80211_CIPHER_TKIP 1
++#define IEEE80211_CIPHER_AES_OCB 2
++#define IEEE80211_CIPHER_AES_CCM 3
++#define IEEE80211_CIPHER_CKIP 5
++#define IEEE80211_CIPHER_CCKM_KRK 6
++#define IEEE80211_CIPHER_NONE 7 /* pseudo value */
++
++#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1)
++
++#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
++ (((len) == 5) || ((len) == 13) || ((len) == 16))
++
++/*
++ * generic definitions for IEEE 802.11 frames
++ */
++struct ieee80211_frame {
++ A_UINT8 i_fc[2];
++ A_UINT8 i_dur[2];
++ A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
++ A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
++ A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
++ A_UINT8 i_seq[2];
++ /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
++ /* see below */
++} __ATTRIB_PACK;
++
++#define IEEE80211_FC0_VERSION_MASK 0x03
++#define IEEE80211_FC0_VERSION_SHIFT 0
++#define IEEE80211_FC0_VERSION_0 0x00
++#define IEEE80211_FC0_TYPE_MASK 0x0c
++#define IEEE80211_FC0_TYPE_SHIFT 2
++#define IEEE80211_FC0_TYPE_MGT 0x00
++#define IEEE80211_FC0_TYPE_CTL 0x04
++#define IEEE80211_FC0_TYPE_DATA 0x08
++
++#define IEEE80211_FC0_SUBTYPE_MASK 0xf0
++#define IEEE80211_FC0_SUBTYPE_SHIFT 4
++/* for TYPE_MGT */
++#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00
++#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10
++#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20
++#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30
++#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40
++#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50
++#define IEEE80211_FC0_SUBTYPE_BEACON 0x80
++#define IEEE80211_FC0_SUBTYPE_ATIM 0x90
++#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0
++#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0
++#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0
++/* for TYPE_CTL */
++#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0
++#define IEEE80211_FC0_SUBTYPE_RTS 0xb0
++#define IEEE80211_FC0_SUBTYPE_CTS 0xc0
++#define IEEE80211_FC0_SUBTYPE_ACK 0xd0
++#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0
++#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0
++/* for TYPE_DATA (bit combination) */
++#define IEEE80211_FC0_SUBTYPE_DATA 0x00
++#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10
++#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20
++#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30
++#define IEEE80211_FC0_SUBTYPE_NODATA 0x40
++#define IEEE80211_FC0_SUBTYPE_CFACK 0x50
++#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60
++#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
++#define IEEE80211_FC0_SUBTYPE_QOS 0x80
++#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0
++
++#define IEEE80211_FC1_DIR_MASK 0x03
++#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */
++#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */
++#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */
++#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */
++
++#define IEEE80211_FC1_MORE_FRAG 0x04
++#define IEEE80211_FC1_RETRY 0x08
++#define IEEE80211_FC1_PWR_MGT 0x10
++#define IEEE80211_FC1_MORE_DATA 0x20
++#define IEEE80211_FC1_WEP 0x40
++#define IEEE80211_FC1_ORDER 0x80
++
++#define IEEE80211_SEQ_FRAG_MASK 0x000f
++#define IEEE80211_SEQ_FRAG_SHIFT 0
++#define IEEE80211_SEQ_SEQ_MASK 0xfff0
++#define IEEE80211_SEQ_SEQ_SHIFT 4
++
++#define IEEE80211_NWID_LEN 32
++
++/*
++ * 802.11 rate set.
++ */
++#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */
++#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */
++
++#define WMM_NUM_AC 4 /* 4 AC categories */
++
++#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */
++#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */
++#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */
++#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */
++#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */
++#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */
++#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */
++#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */
++
++#define WMM_AC_TO_TID(_ac) ( \
++ ((_ac) == WMM_AC_VO) ? 6 : \
++ ((_ac) == WMM_AC_VI) ? 5 : \
++ ((_ac) == WMM_AC_BK) ? 1 : \
++ 0)
++
++#define TID_TO_WMM_AC(_tid) ( \
++ ((_tid) < 1) ? WMM_AC_BE : \
++ ((_tid) < 3) ? WMM_AC_BK : \
++ ((_tid) < 6) ? WMM_AC_VI : \
++ WMM_AC_VO)
++/*
++ * Management information element payloads.
++ */
++
++enum {
++ IEEE80211_ELEMID_SSID = 0,
++ IEEE80211_ELEMID_RATES = 1,
++ IEEE80211_ELEMID_FHPARMS = 2,
++ IEEE80211_ELEMID_DSPARMS = 3,
++ IEEE80211_ELEMID_CFPARMS = 4,
++ IEEE80211_ELEMID_TIM = 5,
++ IEEE80211_ELEMID_IBSSPARMS = 6,
++ IEEE80211_ELEMID_COUNTRY = 7,
++ IEEE80211_ELEMID_CHALLENGE = 16,
++ /* 17-31 reserved for challenge text extension */
++ IEEE80211_ELEMID_PWRCNSTR = 32,
++ IEEE80211_ELEMID_PWRCAP = 33,
++ IEEE80211_ELEMID_TPCREQ = 34,
++ IEEE80211_ELEMID_TPCREP = 35,
++ IEEE80211_ELEMID_SUPPCHAN = 36,
++ IEEE80211_ELEMID_CHANSWITCH = 37,
++ IEEE80211_ELEMID_MEASREQ = 38,
++ IEEE80211_ELEMID_MEASREP = 39,
++ IEEE80211_ELEMID_QUIET = 40,
++ IEEE80211_ELEMID_IBSSDFS = 41,
++ IEEE80211_ELEMID_ERP = 42,
++ IEEE80211_ELEMID_RSN = 48,
++ IEEE80211_ELEMID_XRATES = 50,
++ IEEE80211_ELEMID_TPC = 150,
++ IEEE80211_ELEMID_CCKM = 156,
++ IEEE80211_ELEMID_VENDOR = 221, /* vendor private */
++};
++
++#define ATH_OUI 0x7f0300 /* Atheros OUI */
++#define ATH_OUI_TYPE 0x01
++#define ATH_OUI_SUBTYPE 0x01
++#define ATH_OUI_VERSION 0x00
++
++#define WPA_OUI 0xf25000
++#define WPA_OUI_TYPE 0x01
++#define WPA_VERSION 1 /* current supported version */
++
++#define WPA_CSE_NULL 0x00
++#define WPA_CSE_WEP40 0x01
++#define WPA_CSE_TKIP 0x02
++#define WPA_CSE_CCMP 0x04
++#define WPA_CSE_WEP104 0x05
++
++#define WPA_ASE_NONE 0x00
++#define WPA_ASE_8021X_UNSPEC 0x01
++#define WPA_ASE_8021X_PSK 0x02
++
++#define RSN_OUI 0xac0f00
++#define RSN_VERSION 1 /* current supported version */
++
++#define RSN_CSE_NULL 0x00
++#define RSN_CSE_WEP40 0x01
++#define RSN_CSE_TKIP 0x02
++#define RSN_CSE_WRAP 0x03
++#define RSN_CSE_CCMP 0x04
++#define RSN_CSE_WEP104 0x05
++
++#define RSN_ASE_NONE 0x00
++#define RSN_ASE_8021X_UNSPEC 0x01
++#define RSN_ASE_8021X_PSK 0x02
++
++#define RSN_CAP_PREAUTH 0x01
++
++#define WMM_OUI 0xf25000
++#define WMM_OUI_TYPE 0x02
++#define WMM_INFO_OUI_SUBTYPE 0x00
++#define WMM_PARAM_OUI_SUBTYPE 0x01
++#define WMM_VERSION 1
++
++/* WMM stream classes */
++#define WMM_NUM_AC 4
++#define WMM_AC_BE 0 /* best effort */
++#define WMM_AC_BK 1 /* background */
++#define WMM_AC_VI 2 /* video */
++#define WMM_AC_VO 3 /* voice */
++
++/* TSPEC related */
++#define ACTION_CATEGORY_CODE_TSPEC 17
++#define ACTION_CODE_TSPEC_ADDTS 0
++#define ACTION_CODE_TSPEC_ADDTS_RESP 1
++#define ACTION_CODE_TSPEC_DELTS 2
++
++typedef enum {
++ TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
++ TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
++ TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
++ TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
++ TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
++ TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
++ TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
++ TSPEC_STATUS_CODE_DELTS_SENT = 0x30,
++ TSPEC_STATUS_CODE_DELTS_RECV = 0x31,
++} TSPEC_STATUS_CODE;
++
++/*
++ * WMM/802.11e Tspec Element
++ */
++typedef struct wmm_tspec_ie_t {
++ A_UINT8 elementId;
++ A_UINT8 len;
++ A_UINT8 oui[3];
++ A_UINT8 ouiType;
++ A_UINT8 ouiSubType;
++ A_UINT8 version;
++ A_UINT16 tsInfo_info;
++ A_UINT8 tsInfo_reserved;
++ A_UINT16 nominalMSDU;
++ A_UINT16 maxMSDU;
++ A_UINT32 minServiceInt;
++ A_UINT32 maxServiceInt;
++ A_UINT32 inactivityInt;
++ A_UINT32 suspensionInt;
++ A_UINT32 serviceStartTime;
++ A_UINT32 minDataRate;
++ A_UINT32 meanDataRate;
++ A_UINT32 peakDataRate;
++ A_UINT32 maxBurstSize;
++ A_UINT32 delayBound;
++ A_UINT32 minPhyRate;
++ A_UINT16 sba;
++ A_UINT16 mediumTime;
++} __ATTRIB_PACK WMM_TSPEC_IE;
++
++
++/*
++ * BEACON management packets
++ *
++ * octet timestamp[8]
++ * octet beacon interval[2]
++ * octet capability information[2]
++ * information element
++ * octet elemid
++ * octet length
++ * octet information[length]
++ */
++
++#define IEEE80211_BEACON_INTERVAL(beacon) \
++ ((beacon)[8] | ((beacon)[9] << 8))
++#define IEEE80211_BEACON_CAPABILITY(beacon) \
++ ((beacon)[10] | ((beacon)[11] << 8))
++
++#define IEEE80211_CAPINFO_ESS 0x0001
++#define IEEE80211_CAPINFO_IBSS 0x0002
++#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004
++#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008
++#define IEEE80211_CAPINFO_PRIVACY 0x0010
++#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020
++#define IEEE80211_CAPINFO_PBCC 0x0040
++#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080
++/* bits 8-9 are reserved */
++#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400
++#define IEEE80211_CAPINFO_APSD 0x0800
++/* bit 12 is reserved */
++#define IEEE80211_CAPINFO_DSSSOFDM 0x2000
++/* bits 14-15 are reserved */
++
++/*
++ * Authentication Modes
++ */
++
++enum ieee80211_authmode {
++ IEEE80211_AUTH_NONE = 0,
++ IEEE80211_AUTH_OPEN = 1,
++ IEEE80211_AUTH_SHARED = 2,
++ IEEE80211_AUTH_8021X = 3,
++ IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */
++ /* NB: these are used only for ioctls */
++ IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */
++ IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */
++ IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */
++};
++
++#endif /* _NET80211_IEEE80211_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211_ioctl.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211_ioctl.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,120 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Portions Copyright (c) 2001 Atsushi Onoe, 2002-2005 Sam Leffler, Errno Consulting
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the AR6000 linux driver.
++ *
++ */
++
++#ifndef _IEEE80211_IOCTL_H_
++#define _IEEE80211_IOCTL_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
++ */
++
++/*
++ * WPA/RSN get/set key request. Specify the key/cipher
++ * type and whether the key is to be used for sending and/or
++ * receiving. The key index should be set only when working
++ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
++ * Otherwise a unicast/pairwise key is specified by the bssid
++ * (on a station) or mac address (on an ap). They key length
++ * must include any MIC key data; otherwise it should be no
++ more than IEEE80211_KEYBUF_SIZE.
++ */
++struct ieee80211req_key {
++ u_int8_t ik_type; /* key/cipher type */
++ u_int8_t ik_pad;
++ u_int16_t ik_keyix; /* key index */
++ u_int8_t ik_keylen; /* key length in bytes */
++ u_int8_t ik_flags;
++#define IEEE80211_KEY_XMIT 0x01
++#define IEEE80211_KEY_RECV 0x02
++#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */
++ u_int8_t ik_macaddr[IEEE80211_ADDR_LEN];
++ u_int64_t ik_keyrsc; /* key receive sequence counter */
++ u_int64_t ik_keytsc; /* key transmit sequence counter */
++ u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
++};
++/*
++ * Delete a key either by index or address. Set the index
++ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
++ */
++struct ieee80211req_del_key {
++ u_int8_t idk_keyix; /* key index */
++ u_int8_t idk_macaddr[IEEE80211_ADDR_LEN];
++};
++/*
++ * MLME state manipulation request. IEEE80211_MLME_ASSOC
++ * only makes sense when operating as a station. The other
++ * requests can be used when operating as a station or an
++ * ap (to effect a station).
++ */
++struct ieee80211req_mlme {
++ u_int8_t im_op; /* operation to perform */
++#define IEEE80211_MLME_ASSOC 1 /* associate station */
++#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */
++#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */
++#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */
++#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */
++ u_int16_t im_reason; /* 802.11 reason code */
++ u_int8_t im_macaddr[IEEE80211_ADDR_LEN];
++};
++
++struct ieee80211req_addpmkid {
++ u_int8_t pi_bssid[IEEE80211_ADDR_LEN];
++ u_int8_t pi_enable;
++ u_int8_t pi_pmkid[16];
++};
++
++#define AUTH_ALG_OPEN_SYSTEM 0x01
++#define AUTH_ALG_SHARED_KEY 0x02
++#define AUTH_ALG_LEAP 0x04
++
++struct ieee80211req_authalg {
++ u_int8_t auth_alg;
++};
++
++enum {
++ IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */
++ IEEE80211_PARAM_MCASTCIPHER = 5,
++ IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */
++ IEEE80211_PARAM_UCASTCIPHER = 8,
++ IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */
++ IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */
++ IEEE80211_PARAM_ROAMING = 12, /* roaming mode */
++ IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */
++ IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */
++ IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */
++};
++
++/*
++ * Values for IEEE80211_PARAM_WPA
++ */
++#define WPA_MODE_WPA1 1
++#define WPA_MODE_WPA2 2
++#define WPA_MODE_AUTO 3
++#define WPA_MODE_NONE 4
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _IEEE80211_IOCTL_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211_node.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/ieee80211_node.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 ATheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _IEEE80211_NODE_H_
++#define _IEEE80211_NODE_H_
++
++/*
++ * Node locking definitions.
++ */
++#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_DESTROY(_nt)
++#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
++#define IEEE80211_NODE_LOCK_ASSERT(_nt)
++
++/*
++ * Node reference counting definitions.
++ *
++ * ieee80211_node_initref initialize the reference count to 1
++ * ieee80211_node_incref add a reference
++ * ieee80211_node_decref remove a reference
++ * ieee80211_node_dectestref remove a reference and return 1 if this
++ * is the last reference, otherwise 0
++ * ieee80211_node_refcnt reference count for printing (only)
++ */
++#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1)
++#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++)
++#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--)
++#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 0)
++#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt)
++
++#define IEEE80211_NODE_HASHSIZE 32
++/* simple hash is enough for variation of macaddr */
++#define IEEE80211_NODE_HASH(addr) \
++ (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
++ IEEE80211_NODE_HASHSIZE)
++
++/*
++ * Table of ieee80211_node instances. Each ieee80211com
++ * has at least one for holding the scan candidates.
++ * When operating as an access point or in ibss mode there
++ * is a second table for associated stations or neighbors.
++ */
++struct ieee80211_node_table {
++ void *nt_wmip; /* back reference */
++ A_MUTEX_T nt_nodelock; /* on node table */
++ struct bss *nt_node_first; /* information of all nodes */
++ struct bss *nt_node_last; /* information of all nodes */
++ struct bss *nt_hash[IEEE80211_NODE_HASHSIZE];
++ const char *nt_name; /* for debugging */
++ A_UINT32 nt_scangen; /* gen# for timeout scan */
++ A_TIMER nt_inact_timer;
++};
++
++#define WLAN_NODE_INACT_TIMEOUT_MSEC 10000
++
++#endif /* _IEEE80211_NODE_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/osapi_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/osapi_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,167 @@
++/*
++ * Copyright 2003-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions of the basic atheros data types.
++ * It is used to map the data types in atheros files to a platform specific
++ * type.
++ *
++ */
++
++#ifndef _OSAPI_LINUX_H_
++#define _OSAPI_LINUX_H_
++
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <linux/jiffies.h>
++#endif
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/wait.h>
++#ifdef KERNEL_2_4
++#include <asm/arch/irq.h>
++#include <asm/irq.h>
++#endif
++
++/*
++ * Endianes macros
++ */
++#define A_BE2CPU8(x) ntohb(x)
++#define A_BE2CPU16(x) ntohs(x)
++#define A_BE2CPU32(x) ntohl(x)
++
++#define A_LE2CPU8(x) (x)
++#define A_LE2CPU16(x) (x)
++#define A_LE2CPU32(x) (x)
++
++#define A_CPU2BE8(x) htonb(x)
++#define A_CPU2BE16(x) htons(x)
++#define A_CPU2BE32(x) htonl(x)
++
++#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len))
++#define A_MEMZERO(addr, len) memset(addr, 0, len)
++#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len))
++#define A_MALLOC(size) kmalloc((size), GFP_KERNEL)
++#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC)
++#define A_FREE(addr) kfree(addr)
++#define A_PRINTF(args...) printk(args)
++
++/* Mutual Exclusion */
++typedef spinlock_t A_MUTEX_T;
++#define A_MUTEX_INIT(mutex) spin_lock_init(mutex)
++#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex)
++#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex)
++
++/*
++ * Timer Functions
++ */
++#define A_MDELAY(msecs) mdelay(msecs)
++typedef struct timer_list A_TIMER;
++
++#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \
++ init_timer(pTimer); \
++ (pTimer)->function = (pFunction); \
++ (pTimer)->data = (unsigned long)(pArg); \
++} while (0)
++
++/*
++ * Start a Timer that elapses after 'periodMSec' milli-seconds
++ * Support is provided for a one-shot timer. The 'repeatFlag' is
++ * ignored.
++ */
++#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \
++ if (repeatFlag) { \
++ printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \
++ panic("Timer Repeat"); \
++ } \
++ mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \
++} while (0)
++
++/*
++ * Cancel the Timer.
++ */
++#define A_UNTIMEOUT(pTimer) do { \
++ del_timer((pTimer)); \
++} while (0)
++
++#define A_DELETE_TIMER(pTimer) do { \
++} while (0)
++
++/*
++ * Wait Queue related functions
++ */
++typedef wait_queue_head_t A_WAITQUEUE_HEAD;
++#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head)
++#ifdef mvlcee31_2_4_20_omap2420_gsm_gprs
++#ifndef wait_event_interruptible_timeout
++#define __wait_event_interruptible_timeout(wq, condition, ret) \
++do { \
++ wait_queue_t __wait; \
++ init_waitqueue_entry(&__wait, current); \
++ \
++ add_wait_queue(&wq, &__wait); \
++ for (;;) { \
++ set_current_state(TASK_INTERRUPTIBLE); \
++ if (condition) \
++ break; \
++ if (!signal_pending(current)) { \
++ ret = schedule_timeout(ret); \
++ if (!ret) \
++ break; \
++ continue; \
++ } \
++ ret = -ERESTARTSYS; \
++ break; \
++ } \
++ current->state = TASK_RUNNING; \
++ remove_wait_queue(&wq, &__wait); \
++} while (0)
++
++#define wait_event_interruptible_timeout(wq, condition, timeout) \
++({ \
++ long __ret = timeout; \
++ if (!(condition)) \
++ __wait_event_interruptible_timeout(wq, condition, __ret); \
++ __ret; \
++})
++#endif /* wait_event_interruptible_timeout */
++
++#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
++ wait_event_interruptible_timeout(head, condition, timeout); \
++} while (0)
++#else
++#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
++ wait_event_interruptible_timeout(head, condition, timeout); \
++} while (0)
++#endif /* mvlcee31_2_4_20-omap2420_gsm_gprs */
++
++#define A_WAKE_UP(head) wake_up(head)
++
++#ifdef DEBUG
++#define A_ASSERT(expr) \
++ if (!(expr)) { \
++ printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
++ panic(#expr); \
++ }
++
++#else
++#define A_ASSERT(expr)
++#endif /* DEBUG */
++
++#endif /* _OSAPI_LINUX_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi_host.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi_host.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,75 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains local definitios for the wmi host module.
++ *
++ */
++
++#ifndef _WMI_HOST_H_
++#define _WMI_HOST_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * IP QoS Field definitions according to 802.1p
++ */
++#define BEST_EFFORT_PRI 0
++#define BACKGROUND_PRI 1
++#define EXCELLENT_EFFORT_PRI 3
++#define CONTROLLED_LOAD_PRI 4
++#define VIDEO_PRI 5
++#define VOICE_PRI 6
++#define NETWORK_CONTROL_PRI 7
++
++struct wmi_stats {
++ A_UINT32 cmd_len_err;
++ A_UINT32 cmd_id_err;
++};
++
++struct wmi_priority_state {
++ A_UINT8 inUse;
++ A_UINT8 mbox;
++};
++
++struct wmi_mbox_state {
++ A_UINT8 trafficClass;
++ A_INT8 priorityNum;
++};
++
++struct wmi_t {
++ A_BOOL wmi_ready;
++ A_BOOL wmi_numQoSStream;
++ struct wmi_priority_state wmi_priority[WMI_MAX_NUM_PRI_STREAMS];
++ struct wmi_mbox_state wmi_mboxMap[2][WMI_MBOX_COUNT];
++ A_INT8 wmi_trafficClassMap[2][WMM_NUM_AC];
++ A_UINT8 wmi_olderPriRxMbox;
++ A_UINT8 wmi_newerPriRxMbox;
++ void *wmi_devt;
++ struct wmi_stats wmi_stats;
++ struct ieee80211_node_table wmi_scan_table;
++ A_BOOL wmi_pstreamCmdInProgress[2][WMM_NUM_AC];
++ A_BOOL wmi_cpstreamCmdInProgress;
++ A_UINT8 wmi_bssid[ATH_MAC_LEN];
++ A_UINT8 wmi_powerMode;
++ A_UINT8 wmi_phyMode;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _WMI_HOST_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/bmi_internal.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/bmi_internal.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ */
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/hw/mbox_host_reg.h"
++#include "../include/AR6000_bmi.h"
++
++#define BMI_COMMUNICATION_TIMEOUT 100000
++
++A_STATUS
++bmiBufferSend(HIF_DEVICE *device,
++ A_UCHAR *buffer,
++ A_UINT32 length);
++
++A_STATUS
++bmiBufferReceive(HIF_DEVICE *device,
++ A_UCHAR *buffer,
++ A_UINT32 length);
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/hif.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/hif.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,664 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the interaction with the SDIO
++ * driver
++ */
++#include "hif_internal.h"
++
++/* ------ Static Variables ------ */
++
++/* ------ Global Variable Declarations ------- */
++SD_PNP_INFO Ids[] = {
++ {
++ .SDIO_ManufacturerID = MANUFACTURER_ID_BASE | 0xB,
++ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
++ .SDIO_FunctionClass = FUNCTION_CLASS,
++ .SDIO_FunctionNo = 1
++ },
++ {
++ .SDIO_ManufacturerID = MANUFACTURER_ID_BASE | 0xA,
++ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
++ .SDIO_FunctionClass = FUNCTION_CLASS,
++ .SDIO_FunctionNo = 1
++ },
++ {
++ .SDIO_ManufacturerID = MANUFACTURER_ID_BASE | 0x9,
++ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
++ .SDIO_FunctionClass = FUNCTION_CLASS,
++ .SDIO_FunctionNo = 1
++ },
++ {
++ .SDIO_ManufacturerID = MANUFACTURER_ID_BASE | 0x8,
++ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
++ .SDIO_FunctionClass = FUNCTION_CLASS,
++ .SDIO_FunctionNo = 1
++ },
++ {
++ } //list is null termintaed
++};
++
++TARGET_FUNCTION_CONTEXT FunctionContext = {
++ .function.Version = CT_SDIO_STACK_VERSION_CODE,
++ .function.pName = "sdio_wlan",
++ .function.MaxDevices = 1,
++ .function.NumDevices = 0,
++ .function.pIds = Ids,
++ .function.pProbe = hifDeviceInserted,
++ .function.pRemove = hifDeviceRemoved,
++ .function.pSuspend = NULL,
++ .function.pResume = NULL,
++ .function.pWake = NULL,
++ .function.pContext = &FunctionContext,
++};
++
++HIF_DEVICE hifDevice[HIF_MAX_DEVICES];
++HTC_CALLBACKS htcCallbacks;
++BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM];
++OS_CRITICALSECTION lock;
++extern A_UINT32 onebitmode;
++extern A_UINT32 busspeedlow;
++extern A_UINT32 debughif;
++
++#ifdef DEBUG
++#define ATH_DEBUG_ERROR 1
++#define ATH_DEBUG_WARN 2
++#define ATH_DEBUG_TRACE 3
++#define _AR_DEBUG_PRINTX_ARG(arg...) arg
++#define AR_DEBUG_PRINTF(lvl, args)\
++ {if (lvl <= debughif)\
++ A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\
++ }
++#else
++#define AR_DEBUG_PRINTF(lvl, args)
++#endif
++
++/* ------ Functions ------ */
++void
++HIFRegisterCallbacks(HTC_CALLBACKS *callbacks)
++{
++ SDIO_STATUS status;
++ DBG_ASSERT(callbacks != NULL);
++
++ /* Store the callback and event handlers */
++ htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
++ htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
++ htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
++ htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
++ htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
++ htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
++ htcCallbacks.dsrHandler = callbacks->dsrHandler;
++
++ CriticalSectionInit(&lock);
++
++ /* Register with bus driver core */
++ status = SDIO_RegisterFunction(&FunctionContext.function);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++}
++
++A_STATUS
++HIFReadWrite(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length,
++ HIF_REQUEST *request,
++ void *context)
++{
++ A_UINT8 rw;
++ A_UINT8 mode;
++ A_UINT8 funcNo;
++ A_UINT8 opcode;
++ A_UINT16 count;
++ SDREQUEST *sdrequest;
++ SDIO_STATUS status;
++ DBG_ASSERT(device != NULL);
++ DBG_ASSERT(device->handle != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ sdrequest = hifAllocateDeviceRequest(device->handle);
++ if (sdrequest == NULL) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Unable to allocate bus request\n"));
++ return A_ERROR;
++ }
++
++ sdrequest->pDataBuffer = buffer;
++ if (request->emode == HIF_SYNCHRONOUS) {
++ sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS;
++ sdrequest->pCompleteContext = NULL;
++ sdrequest->pCompletion = NULL;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Synchronous\n"));
++ } else if (request->emode == HIF_ASYNCHRONOUS) {
++ sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS |
++ SDREQ_FLAGS_TRANS_ASYNC;
++ sdrequest->pCompleteContext = context;
++ sdrequest->pCompletion = hifRWCompletionHandler;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Asynchronous\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid execution mode: %d\n", request->emode));
++ return A_ERROR;
++ }
++
++ if (request->type == HIF_EXTENDED_IO) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Command type: CMD53\n"));
++ sdrequest->Command = CMD53;
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid command type: %d\n", request->type));
++ return A_ERROR;
++ }
++
++ if (request->dmode == HIF_BLOCK_BASIS) {
++ mode = CMD53_BLOCK_BASIS;
++ sdrequest->BlockLen = HIF_MBOX_BLOCK_SIZE;
++ sdrequest->BlockCount = length / HIF_MBOX_BLOCK_SIZE;
++ count = sdrequest->BlockCount;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("Block mode (BlockLen: %d, BlockCount: %d)\n",
++ sdrequest->BlockLen, sdrequest->BlockCount));
++ } else if (request->dmode == HIF_BYTE_BASIS) {
++ mode = CMD53_BYTE_BASIS;
++ sdrequest->BlockLen = length;
++ sdrequest->BlockCount = 1;
++ count = sdrequest->BlockLen;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("Byte mode (BlockLen: %d, BlockCount: %d)\n",
++ sdrequest->BlockLen, sdrequest->BlockCount));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid data mode: %d\n", request->dmode));
++ return A_ERROR;
++ }
++
++ if ((address >= HIF_MBOX_START_ADDR(0)) &&
++ (address <= HIF_MBOX_END_ADDR(3)))
++ {
++ /*
++ * Mailbox write. Adjust the address so that the last byte
++ * falls on the EOM address.
++ */
++ address += (HIF_MBOX_WIDTH - length);
++ }
++
++ if (request->direction == HIF_WRITE) {
++ rw = CMD53_WRITE;
++ sdrequest->Flags |= SDREQ_FLAGS_DATA_WRITE;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Write\n"));
++ } else if (request->direction == HIF_READ) {
++ rw = CMD53_READ;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Read\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid direction: %d\n", request->direction));
++ return A_ERROR;
++ }
++
++ if (request->amode == HIF_FIXED_ADDRESS) {
++ opcode = CMD53_FIXED_ADDRESS;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Fixed\n"));
++ } else if (request->amode == HIF_INCREMENTAL_ADDRESS) {
++ opcode = CMD53_INCR_ADDRESS;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Incremental\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid address mode: %d\n", request->amode));
++ return A_ERROR;
++ }
++
++ funcNo = SDDEVICE_GET_SDIO_FUNCNO(device->handle);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Function number: %d\n", funcNo));
++ SDIO_SET_CMD53_ARG(sdrequest->Argument, rw, funcNo,
++ mode, opcode, address, count);
++
++ /* Send the command out */
++ status = SDDEVICE_CALL_REQUEST_FUNC(device->handle, sdrequest);
++ if (status == SDIO_STATUS_PENDING) {
++ DBG_ASSERT(request->emode == HIF_ASYNCHRONOUS);
++ return A_OK;
++ } else if (status == SDIO_STATUS_SUCCESS) {
++ DBG_ASSERT(request->emode == HIF_SYNCHRONOUS);
++ hifFreeDeviceRequest(sdrequest);
++ return A_OK;
++ }
++
++ return A_ERROR;
++}
++
++A_STATUS
++HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
++ void *config, A_UINT32 configLen)
++{
++ A_UINT32 count;
++
++ switch(opcode) {
++ case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
++ ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
++ ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
++ ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
++ ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
++ break;
++
++ case HIF_DEVICE_GET_MBOX_ADDR:
++ for (count = 0; count < 4; count ++) {
++ ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
++ }
++ break;
++
++ default:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid configuration opcode: %d\n", opcode));
++ return A_ERROR;
++ }
++
++ return A_OK;
++}
++
++void
++HIFShutDownDevice(HIF_DEVICE *device)
++{
++ A_UINT8 data;
++ A_UINT32 count;
++ SDIO_STATUS status;
++ SDCONFIG_BUS_MODE_DATA busSettings;
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++
++ if (device != NULL) {
++ DBG_ASSERT(device->handle != NULL);
++
++ /* Remove the allocated current if any */
++ status = SDLIB_IssueConfig(device->handle,
++ SDCONFIG_FUNC_FREE_SLOT_CURRENT, NULL, 0);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++
++ /* Disable the card */
++ fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
++ fData.TimeOut = 1;
++ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData, sizeof(fData));
++ DBG_ASSERT(SDIO_SUCCESS(status));
++
++ /* Perform a soft I/O reset */
++ data = SDIO_IO_RESET;
++ status = SDLIB_IssueCMD52(device->handle, 0, SDIO_IO_ABORT_REG,
++ &data, 1, 1);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++
++ /*
++ * WAR - Codetelligence driver does not seem to shutdown correctly in 1
++ * bit mode. By default it configures the HC in the 4 bit. Its later in
++ * our driver that we switch to 1 bit mode. If we try to shutdown, the
++ * driver hangs so we revert to 4 bit mode, to be transparent to the
++ * underlying bus driver.
++ */
++ if (onebitmode) {
++ ZERO_OBJECT(busSettings);
++ busSettings.BusModeFlags =
++ device->handle->pHcd->CardProperties.BusMode;
++ SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
++ SDCONFIG_BUS_WIDTH_4_BIT);
++
++ /* Issue config request to change the bus width to 4 bit */
++ status = SDLIB_IssueConfig(device->handle, SDCONFIG_BUS_MODE_CTRL,
++ &busSettings,
++ sizeof(SDCONFIG_BUS_MODE_DATA));
++ DBG_ASSERT(SDIO_SUCCESS(status));
++ }
++
++ /* Free the bus requests */
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
++ SDDeviceFreeRequest(device->handle, busRequest[count].request);
++ busRequest[count].free = FALSE;
++ }
++ } else {
++ /* Unregister with bus driver core */
++ status = SDIO_UnregisterFunction(&FunctionContext.function);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++ }
++}
++
++void
++hifRWCompletionHandler(SDREQUEST *request)
++{
++ A_STATUS status;
++ void *context;
++
++ if (SDIO_SUCCESS(request->Status)) {
++ status = A_OK;
++ } else {
++ status = A_ERROR;
++ }
++ context = (void *)request->pCompleteContext;
++
++ htcCallbacks.rwCompletionHandler(context, status);
++ DBG_ASSERT(status == A_OK);
++
++ hifFreeDeviceRequest(request);
++}
++
++void
++hifIRQHandler(void *context)
++{
++ A_STATUS status;
++ HIF_DEVICE *device;
++
++ device = (HIF_DEVICE *)context;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ status = htcCallbacks.dsrHandler(device);
++ DBG_ASSERT(status == A_OK);
++}
++
++BOOL
++hifDeviceInserted(SDFUNCTION *function, SDDEVICE *handle)
++{
++ BOOL enabled;
++ A_UINT8 data;
++ A_UINT32 count;
++ HIF_DEVICE *device;
++ SDIO_STATUS status;
++ A_UINT16 maxBlocks;
++ A_UINT16 maxBlockSize;
++ SDCONFIG_BUS_MODE_DATA busSettings;
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++ TARGET_FUNCTION_CONTEXT *functionContext;
++ SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
++ DBG_ASSERT(function != NULL);
++ DBG_ASSERT(handle != NULL);
++
++ device = addHifDevice(handle);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ functionContext = (TARGET_FUNCTION_CONTEXT *)function->pContext;
++
++ /*
++ * Issue commands to get the manufacturer ID and stuff and compare it
++ * against the rev Id derived from the ID registered during the
++ * initialization process. Report the device only in the case there
++ * is a match. In the case od SDIO, the bus driver has already queried
++ * these details so we just need to use their data structures to get the
++ * relevant values. Infact, the driver has already matched it against
++ * the Ids that we registered with it so we dont need to the step here.
++ */
++
++ /* Configure the SDIO Bus Width */
++ if (onebitmode) {
++ data = SDIO_BUS_WIDTH_1_BIT;
++ status = SDLIB_IssueCMD52(handle, 0, SDIO_BUS_IF_REG, &data, 1, 1);
++ if (!SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Unable to set the bus width to 1 bit\n"));
++ return FALSE;
++ }
++ }
++
++ /* Get current bus flags */
++ ZERO_OBJECT(busSettings);
++ busSettings.BusModeFlags = handle->pHcd->CardProperties.BusMode;
++ if (onebitmode) {
++ SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
++ SDCONFIG_BUS_WIDTH_1_BIT);
++ }
++ busSettings.ClockRate = (busspeedlow ? SDIO_CLOCK_FREQUENCY_REDUCED :
++ SDIO_CLOCK_FREQUENCY_DEFAULT);
++
++ /* Issue config request to override clock rate */
++ status = SDLIB_IssueConfig(handle, SDCONFIG_BUS_MODE_CTRL, &busSettings,
++ sizeof(SDCONFIG_BUS_MODE_DATA));
++ if (!SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Unable to configure the host clock\n"));
++ return FALSE;
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("Configured clock: %d, Maximum clock: %d\n",
++ busSettings.ActualClockRate,
++ SDDEVICE_GET_MAX_CLOCK(handle)));
++ }
++
++ /*
++ * Check if the target supports block mode. This result of this check
++ * can be used to implement the HIFReadWrite API.
++ */
++ if (SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle)) {
++ /* Limit block size to operational block limit or card function
++ capability */
++ maxBlockSize = min(SDDEVICE_GET_OPER_BLOCK_LEN(handle),
++ SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle));
++
++ /* check if the card support multi-block transfers */
++ if (!(SDDEVICE_GET_SDIOCARD_CAPS(handle) & SDIO_CAPS_MULTI_BLOCK)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Byte basis only\n"));
++
++ /* Limit block size to max byte basis */
++ maxBlockSize = min(maxBlockSize,
++ (A_UINT16)SDIO_MAX_LENGTH_BYTE_BASIS);
++ maxBlocks = 1;
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Multi-block capable\n"));
++ maxBlocks = SDDEVICE_GET_OPER_BLOCKS(handle);
++ status = SDLIB_SetFunctionBlockSize(handle, HIF_MBOX_BLOCK_SIZE);
++ if (!SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Failed to set block size. Err:%d\n", status));
++ return FALSE;
++ }
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("Bytes Per Block: %d bytes, Block Count:%d \n",
++ maxBlockSize, maxBlocks));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Function does not support Block Mode!\n"));
++ return FALSE;
++ }
++
++ /* Allocate the slot current */
++ status = SDLIB_GetDefaultOpCurrent(handle, &slotCurrent.SlotCurrent);
++ if (SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Allocating Slot current: %d mA\n",
++ slotCurrent.SlotCurrent));
++ status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
++ &slotCurrent, sizeof(slotCurrent));
++ if (!SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Failed to allocate slot current %d\n", status));
++ return FALSE;
++ }
++ }
++
++ /* Enable the dragon function */
++ count = 0;
++ enabled = FALSE;
++ fData.TimeOut = 1;
++ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
++ while ((count++ < SDWLAN_ENABLE_DISABLE_TIMEOUT) && !enabled)
++ {
++ /* Enable dragon */
++ status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData, sizeof(fData));
++ if (!SDIO_SUCCESS(status)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("Attempting to enable the card again\n"));
++ continue;
++ }
++
++ /* Mark the status as enabled */
++ enabled = TRUE;
++ }
++
++ /* Check if we were succesful in enabling the target */
++ if (!enabled) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Failed to communicate with the target\n"));
++ return FALSE;
++ }
++
++ /* Allocate the bus requests to be used later */
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
++ if ((busRequest[count].request = SDDeviceAllocRequest(handle)) == NULL){
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Unable to allocate memory\n"));
++ /* TODO: Free the memory that has already been allocated */
++ return FALSE;
++ }
++ busRequest[count].free = TRUE;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("busRequest[%d].request = 0x%p, busRequest[%d].free = %d\n", count, busRequest[count].request, count, busRequest[count].free));
++ }
++
++ /*
++ * Adding a wait of around a second before we issue the very first
++ * command to dragon. During the process of loading/unloading the
++ * driver repeatedly it was observed that we get a data timeout
++ * while accessing function 1 registers in the chip. The theory at
++ * this point is that some initialization delay in dragon is
++ * causing the SDIO state in dragon core to be not ready even after
++ * the ready bit indicates that function 1 is ready. Accomodating
++ * for this behavior by adding some delay in the driver before it
++ * issues the first command after switching on dragon. Need to
++ * investigate this a bit more - TODO
++ */
++ A_MDELAY(1000);
++
++ /* Inform HTC */
++ if ((htcCallbacks.deviceInsertedHandler(device)) != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++void
++HIFAckInterrupt(HIF_DEVICE *device)
++{
++ SDIO_STATUS status;
++ DBG_ASSERT(device != NULL);
++ DBG_ASSERT(device->handle != NULL);
++
++ /* Acknowledge our function IRQ */
++ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ACK_IRQ,
++ NULL, 0);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++}
++
++void
++HIFUnMaskInterrupt(HIF_DEVICE *device)
++{
++ SDIO_STATUS status;
++
++ DBG_ASSERT(device != NULL);
++ DBG_ASSERT(device->handle != NULL);
++
++ /* Register the IRQ Handler */
++ SDDEVICE_SET_IRQ_HANDLER(device->handle, hifIRQHandler, device);
++
++ /* Unmask our function IRQ */
++ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_UNMASK_IRQ,
++ NULL, 0);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++}
++
++void HIFMaskInterrupt(HIF_DEVICE *device)
++{
++ SDIO_STATUS status;
++ DBG_ASSERT(device != NULL);
++ DBG_ASSERT(device->handle != NULL);
++
++ /* Mask our function IRQ */
++ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_MASK_IRQ,
++ NULL, 0);
++ DBG_ASSERT(SDIO_SUCCESS(status));
++
++ /* Unregister the IRQ Handler */
++ SDDEVICE_SET_IRQ_HANDLER(device->handle, NULL, NULL);
++}
++
++SDREQUEST *
++hifAllocateDeviceRequest(SDDEVICE *device)
++{
++ SDREQUEST *request;
++ A_UINT32 count;
++ DBG_ASSERT(device != NULL);
++
++ /* Acquire lock */
++ CriticalSectionAcquire(&lock);
++ request = NULL;
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("busRequest[%d].request = 0x%p, busRequest[%d].free = %d\n", count, busRequest[count].request, count, busRequest[count].free));
++ if (busRequest[count].free) {
++ request = busRequest[count].request;
++ busRequest[count].free = FALSE;
++ break;
++ }
++ }
++ /* Release lock */
++ CriticalSectionRelease(&lock);
++
++ return request;
++}
++
++void
++hifFreeDeviceRequest(SDREQUEST *request)
++{
++ A_UINT32 count;
++ DBG_ASSERT(request != NULL);
++
++ /* Acquire lock */
++ CriticalSectionAcquire(&lock);
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
++ if (busRequest[count].request == request) {
++ busRequest[count].free = TRUE;
++ break;
++ }
++ }
++ /* Release lock */
++ CriticalSectionRelease(&lock);
++}
++
++void
++hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *handle)
++{
++ A_STATUS status;
++ HIF_DEVICE *device;
++ DBG_ASSERT(function != NULL);
++ DBG_ASSERT(handle != NULL);
++
++ device = getHifDevice(handle);
++ status = htcCallbacks.deviceRemovedHandler(device);
++ delHifDevice(handle);
++ DBG_ASSERT(status == A_OK);
++}
++
++HIF_DEVICE *
++addHifDevice(SDDEVICE *handle)
++{
++ DBG_ASSERT(handle != NULL);
++ hifDevice[0].handle = handle;
++ return &hifDevice[0];
++}
++
++HIF_DEVICE *
++getHifDevice(SDDEVICE *handle)
++{
++ DBG_ASSERT(handle != NULL);
++ return &hifDevice[0];
++}
++
++void
++delHifDevice(SDDEVICE *handle)
++{
++ DBG_ASSERT(handle != NULL);
++ hifDevice[0].handle = NULL;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,433 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the HTC APIs that are exposed to higher layers.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++HTC_TARGET *AtherosTargetList[HIF_MAX_DEVICES];
++HTC_GLOBAL_EVENT_TABLE AtherosEventTable;
++A_MUTEX_T creditCS, counterCS, instanceCS;
++A_WAITQUEUE_HEAD htcEvent;
++
++#ifdef DEBUG
++extern A_UINT32 debughtc;
++extern A_UINT32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++
++extern int tx_attempt[HTC_MAILBOX_NUM_MAX]; /* Num of attempts to add */
++extern int tx_post[HTC_MAILBOX_NUM_MAX]; /* Num of attemps succeded */
++extern int tx_complete[HTC_MAILBOX_NUM_MAX]; /* Num of tx complete */
++
++/* Initializes the HTC module */
++A_STATUS
++HTCInit(void)
++{
++ HTC_CALLBACKS htcCallbacks;
++ static A_BOOL HTCInitialized = FALSE;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n"));
++ if (HTCInitialized) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
++ return A_OK;
++ }
++
++ A_MEMZERO(&AtherosEventTable, sizeof(HTC_GLOBAL_EVENT_TABLE));
++ A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
++ A_INIT_WAITQUEUE_HEAD(&htcEvent);
++
++ htcCallbacks.deviceInsertedHandler = htcTargetInsertedHandler;
++ htcCallbacks.deviceRemovedHandler = htcTargetRemovedHandler;
++ htcCallbacks.rwCompletionHandler = htcRWCompletionHandler;
++#ifdef CF
++ htcCallbacks.deviceInterruptEnabler = htcInterruptEnabler;
++ htcCallbacks.deviceInterruptDisabler = htcInterruptDisabler;
++#endif /* CF */
++
++ htcCallbacks.dsrHandler = htcDSRHandler;
++ HIFRegisterCallbacks(&htcCallbacks);
++ HTCInitialized = TRUE;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
++ return A_OK;
++}
++
++/* Enables Dragon interrupts */
++A_STATUS
++HTCStart(HTC_TARGET *target)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
++
++ /* Unmask the host controller interrupts */
++ HIFUnMaskInterrupt(target->device);
++
++ /* Enable all the interrupts except for the dragon interrupt */
++ target->table.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
++ INT_STATUS_ENABLE_CPU_SET(0x01) |
++ INT_STATUS_ENABLE_COUNTER_SET(0x01) |
++ INT_STATUS_ENABLE_MBOX_DATA_SET(0x0F);
++
++ /* Set up the CPU Interrupt Status Register */
++ target->table.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
++
++ /* Set up the Error Interrupt Status Register */
++ target->table.error_status_enable =
++ ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
++ ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
++
++ /* Set up the Counter Interrupt Status Register */
++ target->table.counter_int_status_enable =
++ COUNTER_INT_STATUS_ENABLE_BIT_SET(0xFF);
++
++ /* Write to the register */
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_status_enable, 4, &request, NULL);
++ if (status != A_OK) {
++ /* Can't write it for some reason */
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Failed to enable INT_STATUS_ENABLE | CPU_INT_STATUS_ENABLE | ERROR_STATUS_ENABLE | COUNTER_INT_STATUS_ENABLE, err: %d\n", status));
++ HTCStop(target);
++ return status;
++ }
++
++#ifdef DEBUG
++ txcreditintrenable[ENDPOINT1] += 1;
++ txcreditintrenable[ENDPOINT2] += 1;
++ txcreditintrenable[ENDPOINT3] += 1;
++ txcreditintrenable[ENDPOINT4] += 1;
++ txcreditintrenableaggregate[ENDPOINT1] += 1;
++ txcreditintrenableaggregate[ENDPOINT2] += 1;
++ txcreditintrenableaggregate[ENDPOINT3] += 1;
++ txcreditintrenableaggregate[ENDPOINT4] += 1;
++#endif /* DEBUG */
++
++ /* Wait on a timed semaphore that will get signalled once the block
++ size negotiation with the target has completed. Furthermore, we have
++ to do it only once during the lifetime of the target detection */
++ if (!target->ready) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Waiting for the block size negotiation to finish\n"));
++ A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(htcEvent, (target->ready == TRUE),
++ HTC_TARGET_RESPONSE_TIMEOUT);
++
++ if (target->ready) {
++ status = A_OK;
++ } else {
++ status = A_ERROR;
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Failed to negotiate the block sizes\n"));
++ HTCStop(target);
++ }
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
++ return status;
++}
++
++/*
++ * Provides an interface for the higher layer module to register for
++ * different events supported by the HTC module
++ */
++A_STATUS
++HTCEventReg(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId, HTC_EVENT_HANDLER eventHandler,
++ void *param)
++{
++ /*
++ * Add the event handler against the specified event and store it in
++ * the event table
++ */
++ A_STATUS status;
++ HTC_ENDPOINT *endPoint;
++ HTC_EVENT_INFO eventInfo;
++ HTC_DATA_REQUEST_QUEUE *sendQueue, *recvQueue;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++ ("HTCEventReg: Enter (eventId: 0x%x, endPointId: %d)\n",
++ eventId, endPointId));
++
++ if (eventHandler) {
++ if ((status = addToEventTable(target, endPointId, eventId,
++ eventHandler, param)) != A_OK)
++ {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Could not add the event 0x%x to the event table\n", eventId));
++ return status;
++ }
++ }
++
++ switch(eventId) {
++ case HTC_TARGET_AVAILABLE:
++ if (eventHandler != NULL) {
++ /*
++ * Dispatch a Target Available event for all the targets
++ * present. Iterate through the global list of targets but
++ * currently we shall simply look for the first instance
++ */
++ target = AtherosTargetList[0];
++ if (target != NULL) {
++ FRAME_EVENT(eventInfo, (A_UCHAR *)target->device,
++ sizeof(HIF_DEVICE *), sizeof(HIF_DEVICE *),
++ A_OK, NULL);
++ dispatchEvent(target, ENDPOINT_UNUSED, eventId, &eventInfo);
++ }
++ } else {
++ /* Initiate a shut down procedure */
++ }
++ break;
++
++ case HTC_TARGET_UNAVAILABLE:
++ break;
++
++ case HTC_BUFFER_RECEIVED:
++ if (eventHandler == NULL) {
++ /* Flush the queue before unregistering the event handler */
++ endPoint = &target->endPoint[endPointId];
++ recvQueue = &endPoint->recvQueue;
++ flushMboxQueue(endPoint, recvQueue, HTC_BUFFER_RECEIVED);
++ }
++ break;
++
++ case HTC_SKB_RECEIVED:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("skb not handled currently\n"));
++ break;
++
++ case HTC_BUFFER_SENT:
++ if (eventHandler == NULL) {
++ /* Flush the queue before unregistering the event handler */
++ endPoint = &target->endPoint[endPointId];
++ sendQueue = &endPoint->sendQueue;
++ flushMboxQueue(endPoint, sendQueue, HTC_BUFFER_SENT);
++ }
++ break;
++
++ case HTC_SKB_SENT:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("skb not handled currently\n"));
++ break;
++
++ case HTC_DATA_AVAILABLE:
++ /*
++ * Dispatch a data available event with the length. We are
++ * not handling this specific case currently because registering
++ * for HTC_DATA_AVAILABLE event is a part of the discipline
++ * that is imposed before one starts using HTC
++ */
++ break;
++
++ default:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Unknown Event ID: 0x%x\n", eventId));
++ return A_EINVAL;
++ }
++
++ /* Check if its a call for registering the event or unregistering it */
++ if (eventHandler == NULL) {
++ if ((status = removeFromEventTable(target, endPointId,
++ eventId)) != A_OK)
++ {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Could not remove the event 0x%x from the event table\n", eventId));
++ return status;
++ }
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCEventReg: Exit\n"));
++ return A_OK;
++}
++
++/*
++ * Commit an address to either WINDOW_WRITE_ADDR_REG or to
++ * WINDOW_READ_ADDR_REG. We write the least significan byte (LSB)
++ * last, since it triggers the read/write.
++ */
++static void
++_WRITE_WINDOW_ADDR(HTC_TARGET *target, A_UINT32 whichreg, A_UINT32 value)
++{
++ A_UINT32 window_addr;
++ HIF_REQUEST request;
++ A_STATUS status;
++ A_UINT32 address;
++
++ window_addr = value;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++
++ address = getRegAddr(whichreg, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address+1,
++ (A_UCHAR *)&window_addr+1, 3, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ status = HIFReadWrite(target->device, address,
++ (A_UCHAR *)&window_addr, 1, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++}
++
++void
++HTCStop(HTC_TARGET *target)
++{
++ A_UINT32 count;
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ A_UINT32 window_data;
++ HTC_ENDPOINT *endPoint;
++ HTC_REG_REQUEST_LIST *regList;
++ HTC_REG_REQUEST_ELEMENT *element;
++ HTC_DATA_REQUEST_QUEUE *sendQueue;
++ HTC_DATA_REQUEST_QUEUE *recvQueue;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStop: Enter"));
++
++ /* Disable all the dragon interrupts */
++ target->table.int_status_enable = 0;
++ target->table.cpu_int_status_enable = 0;
++ target->table.error_status_enable = 0;
++ target->table.counter_int_status_enable = 0;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_status_enable, 4, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ /* Disable the host controller interrupts */
++ HIFMaskInterrupt(target->device);
++
++ /* Flush all the queues and return the buffers to their owner */
++ for (count = ENDPOINT1; count <= ENDPOINT4; count ++) {
++ endPoint = &target->endPoint[count];
++
++ /* Decrement the number of credits consumed */
++ if (endPoint->txCreditsConsumed) {
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
++ HIF_SYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_FIXED_ADDRESS);
++ address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, count);
++ status = HIFReadWrite(target->device, address,
++ endPoint->txCreditsAvailable,
++ endPoint->txCreditsConsumed, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++ }
++
++ SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++ SET_TX_CREDITS_CONSUMED(endPoint, 0);
++
++#ifdef DEBUG
++ txcreditsavailable[count] = GET_TX_CREDITS_AVAILABLE(endPoint);
++ txcreditsconsumed[count] = GET_TX_CREDITS_CONSUMED(endPoint);
++#endif
++
++ endPoint->txCreditsIntrEnable = FALSE;
++ endPoint->rxLengthPending = 0;
++ endPoint->enabled = FALSE;
++
++ /* Flush the Pending Receive Queue */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Flushing the recv queue & returning the buffers\n"));
++
++ recvQueue = &endPoint->recvQueue;
++ flushMboxQueue(endPoint, recvQueue, HTC_BUFFER_RECEIVED);
++
++ /* Flush the Pending Send Queue */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Flushing the send queue & returning the buffers\n"));
++ sendQueue = &endPoint->sendQueue;
++ flushMboxQueue(endPoint, sendQueue, HTC_BUFFER_SENT);
++ }
++
++ /* Clear the tx counters */
++ memset(tx_attempt, 0, sizeof(tx_attempt));
++ memset(tx_post, 0, sizeof(tx_post));
++ memset(tx_complete, 0, sizeof(tx_complete));
++
++ /* Attempting a force reset of the target */
++ window_data = RESET_CONTROL_COLD_RST_MASK;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address, (A_UCHAR *)&window_data,
++ 4, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ _WRITE_WINDOW_ADDR(target, WINDOW_WRITE_ADDR_REG, RESET_CONTROL_ADDRESS);
++
++ /*
++ * Read back the RESET CAUSE register to ensure that the cold reset
++ * went through.
++ */
++ A_MDELAY(2000); /* 2 second delay to allow dragon to settle down */
++ _WRITE_WINDOW_ADDR(target, WINDOW_READ_ADDR_REG, RESET_CAUSE_ADDRESS);
++
++ window_data = 0;
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address, (A_UCHAR *)&window_data,
++ 4, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("window data: %d\n", window_data));
++ window_data &= RESET_CAUSE_LAST_MASK;
++
++ if (window_data != 2) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to cold reset the target\n"));
++ }
++
++ /*
++ * Ensure that all the pending asynchronous register read/writes have
++ * been finished.
++ */
++ regList = &target->regList;
++ for (count = 0; count < HTC_REG_REQUEST_LIST_SIZE; count ++) {
++ element = ®List->element[count];
++ AR_DEBUG_ASSERT(IS_ELEMENT_FREE(element));
++ }
++
++ /* Initialize the shadow copy of the target register table */
++ A_MEMZERO(&target->table, sizeof(HTC_REGISTER_TABLE));
++ target->ready = FALSE;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStop: Exit"));
++}
++
++
++void
++HTCShutDown(HTC_TARGET *target)
++{
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCShutDown: Enter\n"));
++
++ if (target != NULL) {
++ HIFShutDownDevice(target->device);
++ delTargetInstance(target);
++ A_MEMZERO(target, sizeof(HTC_TARGET));
++ A_FREE(target);
++ } else {
++ HIFShutDownDevice(NULL);
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCShutDown: Exit\n"));
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_events.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_events.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1056 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the different events and callbacks
++ * from the hardware interface layer.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern A_MUTEX_T instanceCS, counterCS, creditCS;
++extern A_WAITQUEUE_HEAD htcEvent;
++
++#ifdef DEBUG
++extern A_UINT32 debughtc;
++extern A_UINT32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++
++extern A_UINT32 tx_complete[HTC_MAILBOX_NUM_MAX]; /* Num of tx complete */
++
++/* ------ Static Variables ------ */
++
++
++/* ------ Functions ------ */
++#ifdef CF
++A_STATUS htcInterruptEnabler(HIF_DEVICE *device) {
++
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ HTC_TARGET *target;
++
++ target = getTargetInstance(device);
++ AR_DEBUG_ASSERT(target != NULL);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++ ("htcInterruptEnabler Enter target: 0x%p\n", target));
++
++ target->table.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
++ INT_STATUS_ENABLE_CPU_SET(0x01) |
++ INT_STATUS_ENABLE_COUNTER_SET(0x01) |
++ INT_STATUS_ENABLE_MBOX_DATA_SET(0x0F);
++ /* Reenable Dragon Interrupts */
++
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_status_enable, 1,
++ &request, NULL);
++
++ AR_DEBUG_ASSERT(status == A_OK);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("htcInterruptEnabler Exit\n"));
++
++ return A_OK;
++}
++#endif /* CF */
++
++
++A_STATUS
++htcRWCompletionHandler(void *context,
++ A_STATUS status)
++{
++ HTC_QUEUE_ELEMENT *element;
++
++ element = (HTC_QUEUE_ELEMENT *)context;
++ AR_DEBUG_ASSERT(element != NULL);
++
++ return(element->completionCB(element, status));
++}
++
++A_STATUS
++htcTxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status)
++{
++ HTC_TARGET *target;
++ HTC_ENDPOINT_ID endPointId;
++ HTC_ENDPOINT *endPoint;
++ HTC_EVENT_INFO eventInfo;
++ HTC_MBOX_BUFFER *mboxBuffer;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcTxCompletionCB - Enter\n"));
++
++ /* Get the context */
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ AR_DEBUG_ASSERT(mboxBuffer != NULL);
++ endPoint = mboxBuffer->endPoint;
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("mboxBuffer: 0x%p, buffer: 0x%p, endPoint(%d): 0x%p, target: 0x%p\n", mboxBuffer, mboxBuffer->buffer, endPointId, endPoint, target));
++
++ /* Return the buffer to the user if the transmission was not successful */
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++ ("Frame transmission failed\n"));
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++ ("EndPoint: %d, Tx credits available: %d\n",
++ endPointId, GET_TX_CREDITS_AVAILABLE(endPoint)));
++ /*
++ * In the failure case it is possible that while queueing of the
++ * request itself it returned an error status in which case we
++ * would have dispatched an event and freed the element there
++ * itself. Ideally if it failed to queue the request then it
++ * should not generate a callback but we are being a little
++ * conservative.
++ */
++ if (!(IS_ELEMENT_FREE(element))) {
++ mboxBuffer->buffer += HTC_HEADER_LEN;
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++ mboxBuffer->bufferLength, mboxBuffer->actualLength,
++ A_ECANCELED, mboxBuffer->cookie);
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++ dispatchEvent(target, endPointId, HTC_BUFFER_SENT, &eventInfo);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcTxCompletionCB - Exit\n"));
++ }
++ return A_OK;
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Frame transmission complete\n"));
++
++ /*
++ * The user should see the actual length and buffer length
++ * to be the same. In case of block mode, we use the actual length
++ * parameter to reflect the total number of bytes transmitted after
++ * padding.
++ */
++ mboxBuffer->actualLength = mboxBuffer->bufferLength;
++ mboxBuffer->buffer += HTC_HEADER_LEN;
++
++ /*
++ * Return the transmit buffer to the user through the HTC_BUFFER_SENT
++ * event indicating that the frame was transmitted successfully.
++ */
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer, mboxBuffer->bufferLength,
++ mboxBuffer->actualLength, A_OK, mboxBuffer->cookie);
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++
++ tx_complete[endPointId] += 1;
++
++ dispatchEvent(target, endPointId, HTC_BUFFER_SENT, &eventInfo);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcTxCompletionCB - Exit\n"));
++
++ return A_OK;
++}
++
++A_STATUS
++htcBlkSzNegCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status)
++{
++ HTC_TARGET *target;
++ HTC_ENDPOINT *endPoint;
++ HIF_REQUEST request;
++ HTC_MBOX_BUFFER *mboxBuffer;
++ HTC_REG_REQUEST_ELEMENT *regElement;
++ A_UINT32 address;
++
++ /* Get the context */
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ AR_DEBUG_ASSERT(mboxBuffer != NULL);
++ endPoint = mboxBuffer->endPoint;
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++
++ /* Recycle the request element */
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++ element->completionCB = htcTxCompletionCB;
++
++ if (status == A_OK) {
++ /* Mark the state to be ready */
++ endPoint->enabled = TRUE;
++
++ /* Set the state of the target as ready */
++ if (target->endPoint[ENDPOINT1].enabled &&
++ target->endPoint[ENDPOINT2].enabled &&
++ target->endPoint[ENDPOINT3].enabled &&
++ target->endPoint[ENDPOINT4].enabled )
++ {
++ /* Send the INT_WLAN interrupt to the target */
++ target->table.int_wlan = 1;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_FIXED_ADDRESS);
++ address = getRegAddr(INT_WLAN_REG, ENDPOINT_UNUSED);
++ regElement = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(regElement != NULL);
++ FILL_REG_BUFFER(regElement, &target->table.int_wlan, 1,
++ INT_WLAN_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_wlan,
++ 1, &request, regElement);
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if(status == A_OK) {
++ regElement->completionCB(regElement, status);
++ }
++#endif
++ }
++ }
++
++ return A_OK;
++}
++
++A_STATUS
++htcRxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status)
++{
++ HTC_TARGET *target;
++ HTC_ENDPOINT *endPoint;
++ HTC_EVENT_INFO eventInfo;
++ HTC_ENDPOINT_ID endPointId;
++ HTC_MBOX_BUFFER *mboxBuffer;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcRxCompletionCB - Enter\n"));
++
++ /* Get the context */
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ AR_DEBUG_ASSERT(mboxBuffer != NULL);
++ endPoint = mboxBuffer->endPoint;
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV,
++ ("mboxBuffer: 0x%p, buffer: 0x%p, endPoint(%d): 0x%p, target: 0x%p\n", mboxBuffer, mboxBuffer->buffer, endPointId, endPoint, target));
++
++ /* Return the buffer to the user if the reception was not successful */
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++ ("Frame reception failed\n"));
++ /*
++ * In the failure case it is possible that while queueing of the
++ * request itself it returned an error status in which case we
++ * would have dispatched an event and freed the element there
++ * itself. Ideally if it failed to queue the request then it
++ * should not generate a callback but we are being a little
++ * conservative.
++ */
++ if (!(IS_ELEMENT_FREE(element))) {
++ mboxBuffer->actualLength = 0;
++ mboxBuffer->buffer += HTC_HEADER_LEN;
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++ mboxBuffer->bufferLength, mboxBuffer->actualLength,
++ A_ECANCELED, mboxBuffer->cookie);
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++ dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED, &eventInfo);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("htcRxCompletionCB - Exit\n"));
++ }
++ return A_OK;
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV,
++ ("Frame reception complete\n"));
++
++ AR_DEBUG_PRINTBUF(mboxBuffer->buffer, mboxBuffer->actualLength);
++
++ /*
++ * Advance the pointer by the size of HTC header and pass the payload
++ * pointer to the upper layer.
++ */
++ mboxBuffer->actualLength = ((mboxBuffer->buffer[0] << 0) |
++ (mboxBuffer->buffer[1] << 8));
++ mboxBuffer->buffer += HTC_HEADER_LEN;
++
++ /*
++ * Frame the HTC_BUFFER_RECEIVED to the upper layer indicating that the
++ * packet has been succesfully received.
++ */
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer, mboxBuffer->bufferLength,
++ mboxBuffer->actualLength, A_OK, mboxBuffer->cookie);
++
++ /* Recycle the bufferElement structure */
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++
++ /* Dispatch the event */
++ dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED, &eventInfo);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("htcRxCompletion - Exit\n"));
++
++ return A_OK;
++}
++
++A_STATUS
++htcRegCompletionCB(HTC_REG_REQUEST_ELEMENT *element,
++ A_STATUS status)
++{
++ A_STATUS ret;
++ HTC_TARGET *target;
++ HTC_ENDPOINT *endPoint;
++ HTC_REG_BUFFER *regBuffer;
++ A_UINT8 txCreditsConsumed;
++ A_UINT8 txCreditsAvailable;
++ HTC_ENDPOINT_ID endPointId;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV | ATH_DEBUG_SEND,
++ ("htcRegCompletion - Enter\n"));
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ /* Get the context */
++ AR_DEBUG_ASSERT(element != NULL);
++ regBuffer = GET_REG_BUFFER(element);
++ AR_DEBUG_ASSERT(regBuffer != NULL);
++ target = regBuffer->target;
++ AR_DEBUG_ASSERT(target != NULL);
++
++ /* Identify the register and the operation responsible for the callback */
++ ret = A_OK;
++ switch(regBuffer->base) {
++ case TX_CREDIT_COUNTER_DECREMENT_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("TX_CREDIT_COUNTER_DECREMENT_REG\n"));
++ endPointId = regBuffer->offset;
++ endPoint = &target->endPoint[endPointId];
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): LOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&creditCS);
++
++ /* Calculate the number of credits available */
++ AR_DEBUG_ASSERT(GET_TX_CREDITS_CONSUMED(endPoint) == regBuffer->length);
++ AR_DEBUG_ASSERT(regBuffer->buffer[0] >=
++ GET_TX_CREDITS_CONSUMED(endPoint));
++ SET_TX_CREDITS_AVAILABLE(endPoint, regBuffer->buffer[0] -
++ GET_TX_CREDITS_CONSUMED(endPoint));
++ SET_TX_CREDITS_CONSUMED(endPoint, 0);
++ txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++ txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&creditCS);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Pulling %d tx credits from the target\n",
++ txCreditsAvailable));
++
++#ifdef DEBUG
++ txcreditsavailable[endPointId] = txCreditsAvailable;
++ txcreditsconsumed[endPointId] = txCreditsConsumed;
++#endif /* DEBUG */
++
++ if (txCreditsAvailable) {
++ htcSendFrame(endPoint);
++ } else {
++ /*
++ * Enable the Tx credit counter interrupt so that we can get the
++ * credits posted by the target.
++ */
++ htcEnableCreditCounterInterrupt(target, endPointId);
++
++#ifdef DEBUG
++ txcreditintrenable[endPointId] += 1;
++ txcreditintrenableaggregate[endPointId] += 1;
++#endif /* DEBUG */
++ }
++ break;
++
++ case TX_CREDIT_COUNTER_RESET_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("TX_CREDIT_COUNTER_RESET_REG\n"));
++ endPointId = regBuffer->offset;
++
++ /*
++ * Enable the Tx credit counter interrupt so that we can get the
++ * credits posted by the target.
++ */
++ htcEnableCreditCounterInterrupt(target, endPointId);
++
++#ifdef DEBUG
++ txcreditintrenable[endPointId] += 1;
++ txcreditintrenableaggregate[endPointId] += 1;
++#endif /* DEBUG */
++ break;
++
++ case COUNTER_INT_STATUS_ENABLE_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("COUNTER_INT_STATUS_ENABLE: 0x%x\n",
++ target->table.counter_int_status_enable));
++ break;
++
++ case COUNTER_INT_STATUS_DISABLE_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("COUNTER_INT_STATUS_DISABLE:0x%x\n",
++ target->table.counter_int_status_enable));
++ HIFAckInterrupt(target->device);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler - ACK\n"));
++ break;
++
++ case INT_WLAN_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("INT_WLAN: 0x%x\n",
++ target->table.int_wlan));
++ target->table.int_wlan = 0;
++
++ /* Mark the target state as ready and signal the waiting sem */
++ target->ready = TRUE;
++ A_WAKE_UP(&htcEvent);
++ break;
++
++ case INT_STATUS_ENABLE_REG:
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,("INT_STATUS_ENABLE: 0x%x\n",
++ target->table.int_status_enable));
++ break;
++
++ default:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("Invalid register address: %d\n", regBuffer->base));
++ }
++
++ /* Free the register request structure */
++ freeRegRequestElement(element);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcRegCompletion - Exit\n"));
++
++ return ret;
++}
++
++
++A_STATUS
++htcTargetInsertedHandler(HIF_DEVICE *device)
++{
++ HTC_TARGET *target;
++ HTC_ENDPOINT *endPoint;
++ A_UINT8 count1, count2;
++ HTC_EVENT_INFO eventInfo;
++ HTC_REG_BUFFER *regBuffer;
++ HTC_QUEUE_ELEMENT *element;
++ HTC_MBOX_BUFFER *mboxBuffer;
++ HTC_REG_REQUEST_LIST *regList;
++ HTC_DATA_REQUEST_QUEUE *sendQueue, *recvQueue;
++ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
++ A_UINT32 blockSize[HTC_MAILBOX_NUM_MAX];
++#ifdef CF
++ HIF_REQUEST request;
++ A_STATUS status;
++ A_UINT32 address;
++#endif /* CF */
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n"));
++
++ /* Initialize the locks */
++ A_MUTEX_INIT(&instanceCS);
++ A_MUTEX_INIT(&creditCS);
++ A_MUTEX_INIT(&counterCS);
++
++ /* Allocate target memory */
++ if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
++ return A_ERROR;
++ }
++ A_MEMZERO(target, sizeof(HTC_TARGET));
++ target->device = device;
++ target->ready = FALSE;
++
++ /* Initialize the endpoints, mbox queues, event table */
++ for (count1 = ENDPOINT1; count1 <= ENDPOINT4; count1 ++) {
++ endPoint = &target->endPoint[count1];
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("endPoint[%d]: %p\n", count1, endPoint));
++ A_MEMZERO(endPoint->txCreditsAvailable, HTC_TX_CREDITS_NUM_MAX);
++ endPoint->txCreditsConsumed = 0;
++ endPoint->txCreditsIntrEnable = FALSE;
++ endPoint->rxLengthPending = 0;
++ endPoint->target = target;
++ endPoint->enabled = FALSE;
++ for (count2 = 0; count2<HTC_DATA_REQUEST_RING_BUFFER_SIZE; count2 ++) {
++ /* Send Queue */
++ sendQueue = &endPoint->sendQueue;
++ sendQueue->head = sendQueue->size = 0;
++ element = &sendQueue->element[count2];
++ A_MEMZERO(element, sizeof(HTC_DATA_REQUEST_ELEMENT));
++ element->buffer.free = TRUE;
++ element->completionCB = htcTxCompletionCB;
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ mboxBuffer->endPoint = endPoint;
++
++ /* Receive Queue */
++ recvQueue = &endPoint->recvQueue;
++ recvQueue->head = recvQueue->size = 0;
++ element = &recvQueue->element[count2];
++ A_MEMZERO(element, sizeof(HTC_DATA_REQUEST_ELEMENT));
++ element->buffer.free = TRUE;
++ element->completionCB = htcRxCompletionCB;
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ mboxBuffer->endPoint = endPoint;
++ }
++ A_MEMZERO(&target->endPoint[count1].eventTable,
++ sizeof(HTC_ENDPOINT_EVENT_TABLE));
++ }
++
++ /* Populate the block size for each of the end points */
++ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
++ &blockSize, sizeof(blockSize));
++ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
++ &mboxAddress, sizeof(mboxAddress));
++ for (count1 = ENDPOINT1; count1 <= ENDPOINT4; count1 ++) {
++ endPoint = &target->endPoint[count1];
++ endPoint->blockSize = blockSize[count1];
++ endPoint->address = mboxAddress[count1];
++ }
++
++ /* Initialize the shadow copy of the target register table */
++ A_MEMZERO(&target->table, sizeof(HTC_REGISTER_TABLE));
++
++ /* Initialize the register request list */
++ regList = &target->regList;
++ for (count1 = 0; count1 < HTC_REG_REQUEST_LIST_SIZE; count1 ++) {
++ element = ®List->element[count1];
++ A_MEMZERO(element, sizeof(HTC_REG_REQUEST_ELEMENT));
++ element->buffer.free = TRUE;
++ element->completionCB = htcRegCompletionCB;
++ regBuffer = GET_REG_BUFFER(element);
++ regBuffer->target = target;
++ }
++
++ /* Add the target instance to the global list */
++ addTargetInstance(target);
++#ifdef CF
++ /* Disable all the dragon interrupts */
++ target->table.int_status_enable = 0;
++ target->table.cpu_int_status_enable = 0;
++ target->table.error_status_enable = 0;
++ target->table.counter_int_status_enable = 0;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_status_enable, 4, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++#endif /* CF */
++
++ /*
++ * Frame a TARGET_AVAILABLE event and send it to the host. Return the
++ * HIF_DEVICE handle as a parameter with the event.
++ */
++ FRAME_EVENT(eventInfo, (A_UCHAR *)device, sizeof(HIF_DEVICE *),
++ sizeof(HIF_DEVICE *), A_OK, NULL);
++ dispatchEvent(target, ENDPOINT_UNUSED, HTC_TARGET_AVAILABLE, &eventInfo);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n"));
++
++ return A_OK;
++}
++
++A_STATUS
++htcTargetRemovedHandler(HIF_DEVICE *device)
++{
++ HTC_TARGET *target;
++ HTC_EVENT_INFO eventInfo;
++
++ /* Get the target instance bound to this device */
++ target = getTargetInstance(device);
++
++ if (target != NULL) {
++ /* Frame a TARGET_UNAVAILABLE event and send it to the host */
++ FRAME_EVENT(eventInfo, NULL, 0, 0, A_OK, NULL);
++ dispatchEvent(target, ENDPOINT_UNUSED, HTC_TARGET_UNAVAILABLE,
++ &eventInfo);
++ }
++
++ return A_OK;
++}
++
++
++#ifdef CF
++A_STATUS
++htcInterruptDisabler(HIF_DEVICE *device,A_BOOL *callDsr)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HTC_TARGET *target;
++ HIF_REQUEST request;
++
++ target = getTargetInstance(device);
++ AR_DEBUG_ASSERT(target != NULL);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++ ("htcInterruptDisabler Enter target: 0x%p\n", target));
++
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(INT_STATUS_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.host_int_status, 1, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++ /* Handle Suprise removal of CF card. Upon removal of the card the
++ * host_int_status reads 0xFF
++ */
++ if (target->table.host_int_status == 0xFF) {
++ *callDsr=FALSE;
++ return A_OK;
++ }
++
++ if ((target->table.int_status_enable & target->table.host_int_status) == 0) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++ ("htcInterruptDisabler: MisRouted / Spurious interrupt : 0x%p\n", target));
++ *callDsr=FALSE;
++ } else {
++ /*
++ * Disable the interrupts from Dragon.
++ * We do the interrupt servicing in the bottom half and reenable the
++ * Dragon interrupts at the end of the bottom-half
++ */
++
++ target->table.int_status_enable = 0;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.int_status_enable, 1, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++ *callDsr=TRUE;
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcInterruptDisabler: Exit\n"));
++ return A_OK;
++}
++#endif /* CF */
++
++A_STATUS
++htcDSRHandler(HIF_DEVICE *device)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HTC_TARGET *target;
++ HIF_REQUEST request;
++ A_UCHAR host_int_status;
++
++ target = getTargetInstance(device);
++ AR_DEBUG_ASSERT(target != NULL);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
++ ("htcDsrHandler: Enter (target: 0x%p\n", target));
++
++ /*
++ * Read the first 28 bytes of the HTC register table. This will yield us
++ * the value of different int status registers and the lookahead
++ * registers.
++ * length = sizeof(int_status) + sizeof(cpu_int_status) +
++ * sizeof(error_int_status) + sizeof(counter_int_status) +
++ * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
++ * sizeof(hole) + sizeof(rx_lookahead) +
++ * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
++ * sizeof(error_status_enable) +
++ * sizeof(counter_int_status_enable);
++ */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(INT_STATUS_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.host_int_status, 28,
++ &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++
++#ifdef DEBUG
++ dumpRegisters(target);
++#endif /* DEBUG */
++#ifdef CF
++ /* Update only those registers that are enabled */
++ /* This is not required as we have already checked for spurious interrupt
++ * in htcInterruptDisabler
++ */
++
++ host_int_status = target->table.host_int_status;
++#else
++ /* Update only those registers that are enabled */
++ host_int_status = target->table.host_int_status &
++ target->table.int_status_enable;
++#endif /* CF */
++
++ AR_DEBUG_ASSERT(host_int_status);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Valid interrupt source(s) in INT_STATUS: 0x%x\n",
++ host_int_status));
++ if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
++ /* CPU Interrupt */
++ htcServiceCPUInterrupt(target);
++ }
++
++ if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
++ /* Error Interrupt */
++ htcServiceErrorInterrupt(target);
++ }
++
++ if (HOST_INT_STATUS_MBOX_DATA_GET(host_int_status)) {
++ /* Mailbox Interrupt */
++ htcServiceMailboxInterrupt(target);
++ }
++
++ if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
++ /* Counter Interrupt */
++ htcServiceCounterInterrupt(target);
++ } else {
++ /* Ack the interrupt */
++ HIFAckInterrupt(target->device);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler - ACK\n"));
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcDSRHandler: Exit\n"));
++ return A_OK;
++}
++
++void
++htcServiceCPUInterrupt(HTC_TARGET *target)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ A_UINT8 cpu_int_status;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("CPU Interrupt\n"));
++ cpu_int_status = target->table.cpu_int_status &
++ target->table.cpu_int_status_enable;
++ AR_DEBUG_ASSERT(cpu_int_status);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
++ cpu_int_status));
++
++ /* Figure out the interrupt number */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Interrupt Number: 0x%x\n",
++ htcGetBitNumSet(cpu_int_status)));
++
++ /* Clear the interrupt */
++ target->table.cpu_int_status = cpu_int_status; /* W1C */
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(CPU_INT_STATUS_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.cpu_int_status, 1, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++}
++
++
++void
++htcServiceErrorInterrupt(HTC_TARGET *target)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ A_UINT8 error_int_status;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Error Interrupt\n"));
++ error_int_status = target->table.error_int_status &
++ target->table.error_status_enable;
++ AR_DEBUG_ASSERT(error_int_status);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
++ error_int_status));
++
++ if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
++ /* Wakeup */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Wakeup\n"));
++ }
++
++ if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
++ /* Rx Underflow */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Rx Underflow\n"));
++ }
++
++ if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
++ /* Tx Overflow */
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Tx Overflow\n"));
++ }
++
++ /* Clear the interrupt */
++ target->table.error_int_status = error_int_status; /* W1C */
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(ERROR_INT_STATUS_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.error_int_status, 1,
++ &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++}
++
++void
++htcServiceCounterInterrupt(HTC_TARGET *target)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ HTC_ENDPOINT *endPoint;
++ HTC_ENDPOINT_ID endPointId;
++ A_UINT8 counter_int_status;
++ A_UINT8 reset_credit_int_status;
++ A_UINT8 update_credit_int_status;
++ HTC_REG_REQUEST_ELEMENT *element;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Counter Interrupt\n"));
++
++ counter_int_status = target->table.counter_int_status &
++ target->table.counter_int_status_enable;
++ AR_DEBUG_ASSERT(counter_int_status);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
++ counter_int_status));
++
++ /* Service the reset credit counter interrupt */
++ reset_credit_int_status = (counter_int_status & 0x0F);
++ while(reset_credit_int_status) {
++ endPointId = htcGetBitNumSet(reset_credit_int_status);
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("endPoint(%d): %p\n", endPointId, endPoint));
++
++ /* Initialize the number of credits available to zero */
++ SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++
++ /* Clear the interrupt */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(TX_CREDIT_COUNTER_RESET_REG, endPointId);
++ element = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(element != NULL);
++ FILL_REG_BUFFER(element, &endPoint->txCreditsAvailable[1], 1,
++ TX_CREDIT_COUNTER_RESET_REG, endPointId);
++ status = HIFReadWrite(target->device, address,
++ &endPoint->txCreditsAvailable[1],
++ 1, &request, element);
++
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if (status == A_OK) {
++ /* Enable the Tx credit counter interrupt so that we can get the
++ * credits posted by the target */
++ htcEnableCreditCounterInterrupt(target, endPointId);
++ }
++#endif
++ reset_credit_int_status &=
++ ~(1 << htcGetBitNumSet(reset_credit_int_status));
++ }
++
++ /* Disable the credit counter interrupt */
++ htcDisableCreditCounterInterrupt(target, ENDPOINT_UNUSED);
++
++ /* Service the credit counter interrupt */
++ update_credit_int_status = counter_int_status & 0xF0;
++ while(update_credit_int_status) {
++ endPointId = htcGetBitNumSet(update_credit_int_status) -
++ HTC_MAILBOX_NUM_MAX;
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ /* This is the minimum number of credits that we would have got */
++ AR_DEBUG_ASSERT(GET_TX_CREDITS_AVAILABLE(endPoint) == 0);
++ SET_TX_CREDITS_AVAILABLE(endPoint, 1);
++
++#ifdef DEBUG
++ txcreditsavailable[endPointId] = GET_TX_CREDITS_AVAILABLE(endPoint);
++ txcreditintrenable[endPointId] -= 1;
++#endif /* DEBUG */
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Tx Credits Available: %d\n",
++ GET_TX_CREDITS_AVAILABLE(endPoint)));
++
++ if (!target->ready) {
++ htcSendBlkSize(endPoint);
++ } else {
++ htcSendFrame(endPoint);
++ }
++
++ update_credit_int_status &=
++ ~(1 << htcGetBitNumSet(update_credit_int_status));
++ }
++}
++
++void
++htcEnableCreditCounterInterrupt(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ HTC_ENDPOINT *endPoint;
++ HTC_REG_REQUEST_ELEMENT *element;
++
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ A_MUTEX_LOCK(&counterCS);
++
++ endPoint->txCreditsIntrEnable = TRUE;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_FIXED_ADDRESS);
++
++ address = getRegAddr(COUNTER_INT_STATUS_ENABLE_REG,
++ ENDPOINT_UNUSED);
++ element = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(element != NULL);
++ FILL_REG_BUFFER(element, NULL, 1, COUNTER_INT_STATUS_ENABLE_REG,
++ (target->endPoint[0].txCreditsIntrEnable << (4)) |
++ (target->endPoint[1].txCreditsIntrEnable << (5)) |
++ (target->endPoint[2].txCreditsIntrEnable << (6)) |
++ (target->endPoint[3].txCreditsIntrEnable << (7)) | 0x0F);
++ status = HIFReadWrite(target->device, address,
++ (A_UCHAR *)&((GET_REG_BUFFER(element))->offset),
++ 1, &request, element);
++
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if(status == A_OK) {
++ element->completionCB(element, status);
++ }
++#endif
++
++ A_MUTEX_UNLOCK(&counterCS);
++}
++
++void
++htcDisableCreditCounterInterrupt(HTC_TARGET *target,
++ HTC_ENDPOINT_ID unused)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ HTC_ENDPOINT *endPoint;
++ HTC_ENDPOINT_ID endPointId;
++ A_UINT8 counter_int_status;
++ A_UINT8 update_credit_int_status;
++ HTC_REG_REQUEST_ELEMENT *element;
++
++ A_MUTEX_LOCK(&counterCS);
++
++ /* The Tx credit counter update bits are reflected in the upper nibble */
++ counter_int_status = target->table.counter_int_status &
++ target->table.counter_int_status_enable;
++ update_credit_int_status = counter_int_status & 0xF0;
++ while(update_credit_int_status) {
++ endPointId = htcGetBitNumSet(update_credit_int_status) -
++ HTC_MAILBOX_NUM_MAX;
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("endPoint(%d): %p\n", endPointId, endPoint));
++
++ /* Disable the tx credit interrupt */
++ endPoint->txCreditsIntrEnable = FALSE;
++
++ update_credit_int_status &=
++ ~(1 << htcGetBitNumSet(update_credit_int_status));
++ }
++
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_ASYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(COUNTER_INT_STATUS_DISABLE_REG, ENDPOINT_UNUSED);
++ element = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(element != NULL);
++ FILL_REG_BUFFER(element, NULL, 1,
++ COUNTER_INT_STATUS_DISABLE_REG,
++ (target->endPoint[0].txCreditsIntrEnable << (4)) |
++ (target->endPoint[1].txCreditsIntrEnable << (5)) |
++ (target->endPoint[2].txCreditsIntrEnable << (6)) |
++ (target->endPoint[3].txCreditsIntrEnable << (7)) | 0x0F);
++ status = HIFReadWrite(target->device, address,
++ (A_UCHAR *)&((GET_REG_BUFFER(element))->offset),
++ 1, &request, element);
++
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if ( status == A_OK ) {
++ element->completionCB(element, status);
++ }
++#endif
++
++ A_MUTEX_UNLOCK(&counterCS);
++}
++
++void
++htcServiceMailboxInterrupt(HTC_TARGET *target)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_REQUEST request;
++ HTC_ENDPOINT *endPoint;
++ HTC_ENDPOINT_ID endPointId;
++ A_UINT8 mailbox_int_status;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF, ("Mailbox Interrupt\n"));
++
++ /* The Rx interrupt bits are reflected in the lower nibble */
++ mailbox_int_status = target->table.host_int_status &
++ HOST_INT_STATUS_MBOX_DATA_MASK;
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("Valid mailbox interrupt source(s) in INT_STATUS: 0x%x\n",
++ mailbox_int_status));
++
++ /* Disable the receive interrupt for all four mailboxes */
++ target->table.int_status_enable &= ~(HOST_INT_STATUS_MBOX_DATA_MASK);
++
++ do {
++ while(mailbox_int_status) {
++ endPointId = htcGetBitNumSet(mailbox_int_status);
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("endPoint(%d): %p\n", endPointId, endPoint));
++
++ /* Service the Rx interrupt */
++ htcReceiveFrame(endPoint);
++ mailbox_int_status &= ~(1 << htcGetBitNumSet(mailbox_int_status));
++ }
++
++ /*
++ * Read the register table again. Repeat the process until there are
++ * no more valid packets queued up on receive. It is assumed that
++ * the following request will be serialized along with the request
++ * above and will be completed in the order in which it is received
++ * by the bus driver.
++ */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO,
++ HIF_SYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_INCREMENTAL_ADDRESS);
++ address = getRegAddr(INT_STATUS_REG, ENDPOINT_UNUSED);
++ status = HIFReadWrite(target->device, address,
++ &target->table.host_int_status,
++ 24, &request, NULL);
++ AR_DEBUG_ASSERT(status == A_OK);
++ mailbox_int_status = target->table.host_int_status &
++ HOST_INT_STATUS_MBOX_DATA_MASK;
++ } while (mailbox_int_status);
++
++ target->table.int_status_enable |= HOST_INT_STATUS_MBOX_DATA_MASK;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_internal.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_internal.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,464 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. The name of the author may not be used to endorse or promote products
++ * derived from this software withough specific prior written permission
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * HTC internal specific declarations and prototypes
++ */
++
++#ifndef _HTC_INTERNAL_H_
++#define _HTC_INTERNAL_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++/* Header files */
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/hw/mbox_host_reg.h"
++#include "../include/hw/rtc_reg.h"
++#include "../include/htc.h"
++#include "../include/AR6000_bmi.h"
++#include "../include/osapi.h"
++#include "../include/hif.h"
++
++/* HTC operational parameters */
++#define HTC_GLOBAL_EVENT_NUM_MAX 2 /* Target available/unavailable */
++#define HTC_ENDPOINT_EVENT_NUM_MAX 5 /* Endpoint specific */
++#define HTC_REG_REQUEST_LIST_SIZE 16
++#define HTC_MESSAGE_SIZE_MAX 1536 - HTC_HEADER_LEN /* Default maximum message size for each mailbox */
++#define HTC_TX_CREDITS_NUM_MAX 64
++#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
++
++/* Useful macros */
++#define GET_ENDPOINT_ID(endPoint) (endPoint - endPoint->target->endPoint)
++
++/* ------- Debug related stuff ------- */
++enum {
++ ATH_DEBUG_SEND = 0x0001,
++ ATH_DEBUG_RECV = 0x0002,
++ ATH_DEBUG_SYNC = 0x0004,
++ ATH_DEBUG_DUMP = 0x0008,
++ ATH_DEBUG_INF = 0x0010,
++ ATH_DEBUG_TRC = 0x0020,
++ ATH_DEBUG_WARN = 0x0040,
++ ATH_DEBUG_ERR = 0x0080,
++ ATH_DEBUG_ANY = 0xFFFF,
++};
++
++#ifdef DEBUG
++#define AR_DEBUG_PRINTBUF(buffer, length) do { \
++ if (debughtc & ATH_DEBUG_DUMP) { \
++ dumpBytes(buffer, length); \
++ } \
++} while(0)
++#define PRINTX_ARG(arg...) arg
++#define AR_DEBUG_PRINTF(flags, args) do { \
++ if (debughtc & (flags)) { \
++ A_PRINTF(KERN_ALERT PRINTX_ARG args); \
++ } \
++} while (0)
++#define AR_DEBUG_ASSERT(test) do { \
++ if (!(test)) { \
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \
++ } \
++} while(0)
++#else
++#define AR_DEBUG_PRINTF(flags, args)
++#define AR_DEBUG_PRINTBUF(buffer, length)
++#define AR_DEBUG_ASSERT(test)
++#endif
++
++/* ------- Event Related Data Structures ------- */
++typedef struct htc_event_map HTC_EVENT_MAP;
++typedef struct event_table_element EVENT_TABLE_ELEMENT;
++typedef struct htc_endpoint_event_table HTC_ENDPOINT_EVENT_TABLE;
++typedef struct htc_global_event_table HTC_GLOBAL_EVENT_TABLE;
++
++#define FRAME_EVENT(_eventInfo, _buffer, _bufferLength, \
++ _actualLength, _status, _cookie) do { \
++ _eventInfo.buffer = _buffer; \
++ _eventInfo.bufferLength = _bufferLength; \
++ _eventInfo.actualLength = _actualLength; \
++ _eventInfo.status = _status; \
++ _eventInfo.cookie = _cookie; \
++} while (0)
++
++struct event_table_element {
++ HTC_EVENT_ID id;
++ HTC_EVENT_HANDLER handler;
++ void *param;
++};
++
++struct htc_endpoint_event_table {
++ EVENT_TABLE_ELEMENT element[HTC_ENDPOINT_EVENT_NUM_MAX];
++};
++
++struct htc_global_event_table {
++ EVENT_TABLE_ELEMENT element[HTC_GLOBAL_EVENT_NUM_MAX];
++
++};
++
++/* ------ Mailbox Related Data Structures ------ */
++typedef struct htc_queue_element HTC_QUEUE_ELEMENT, HTC_REG_REQUEST_ELEMENT, HTC_DATA_REQUEST_ELEMENT;
++typedef struct htc_mbox_buffer HTC_MBOX_BUFFER;
++typedef struct htc_reg_buffer HTC_REG_BUFFER;
++typedef struct htc_data_request_queue HTC_DATA_REQUEST_QUEUE;
++typedef struct htc_reg_request_list HTC_REG_REQUEST_LIST;
++typedef struct htc_endpoint HTC_ENDPOINT;
++
++typedef enum {
++ INT_STATUS_REG,
++ ERROR_INT_STATUS_REG,
++ CPU_INT_STATUS_REG,
++ RX_LOOKAHEAD_VALID_REG,
++ RX_LOOKAHEAD0_REG,
++ RX_LOOKAHEAD1_REG,
++ RX_LOOKAHEAD2_REG,
++ RX_LOOKAHEAD3_REG,
++ TX_CREDIT_COUNTER_REG,
++ TX_CREDIT_COUNTER_RESET_REG,
++ TX_CREDIT_COUNTER_DECREMENT_REG,
++ SCRATCH_REG,
++ INT_STATUS_ENABLE_REG,
++ CPU_INT_STATUS_ENABLE_REG,
++ ERROR_STATUS_ENABLE_REG,
++ COUNTER_INT_STATUS_READ_REG,
++ COUNTER_INT_STATUS_ENABLE_REG,
++ COUNTER_INT_STATUS_DISABLE_REG,
++ INT_WLAN_REG,
++ WINDOW_DATA_REG,
++ WINDOW_WRITE_ADDR_REG,
++ WINDOW_READ_ADDR_REG
++} TARGET_REGISTERS;
++
++#define SET_TX_CREDITS_AVAILABLE(endPoint, credits) \
++ endPoint->txCreditsAvailable[0] = (credits)
++#define SET_TX_CREDITS_CONSUMED(endPoint, credits) \
++ endPoint->txCreditsConsumed = (credits)
++#define GET_TX_CREDITS_AVAILABLE(endPoint) \
++ endPoint->txCreditsAvailable[0]
++#define GET_TX_CREDITS_CONSUMED(endPoint) \
++ endPoint->txCreditsConsumed
++
++#define IS_ELEMENT_FREE(element) element->buffer.free
++#define GET_MBOX_BUFFER(element) &((element)->buffer.u.mboxBuffer)
++#define GET_REG_BUFFER(element) &((element)->buffer.u.regBuffer)
++#define GET_QUEUE_TAIL(queue) &queue->element[(queue->head + queue->size) % HTC_DATA_REQUEST_RING_BUFFER_SIZE]
++#define GET_QUEUE_HEAD(queue) &queue->element[queue->head]
++#define IS_DATA_QUEUE_EMPTY(queue) (!queue->size)
++#define IS_DATA_QUEUE_FULL(queue) (!(HTC_DATA_REQUEST_RING_BUFFER_SIZE - queue->size))
++
++#define RECYCLE_DATA_REQUEST_ELEMENT(element) do { \
++ FILL_MBOX_BUFFER(element, NULL, 0, 0, NULL); \
++ (element)->buffer.free = TRUE; \
++} while (0)
++
++#define FILL_MBOX_BUFFER(element, _buffer, _bufferLength, _actualLength, _cookie) do { \
++ (GET_MBOX_BUFFER(element))->buffer = _buffer; \
++ (GET_MBOX_BUFFER(element))->bufferLength = _bufferLength; \
++ (GET_MBOX_BUFFER(element))->actualLength = _actualLength; \
++ (GET_MBOX_BUFFER(element))->cookie = _cookie; \
++} while (0)
++
++#define FILL_REG_BUFFER(element, _buffer, _length, _base, _offset) do { \
++ (GET_REG_BUFFER(element))->buffer = _buffer; \
++ (GET_REG_BUFFER(element))->length = _length; \
++ (GET_REG_BUFFER(element))->base = _base; \
++ (GET_REG_BUFFER(element))->offset = _offset; \
++} while (0)
++
++struct htc_queue_element {
++ A_STATUS (*completionCB)(HTC_QUEUE_ELEMENT *element, A_STATUS status);
++ struct htc_buffer {
++ /* In use or available */
++ A_BOOL free;
++ union {
++ struct htc_mbox_buffer {
++ /*
++ * Given by the caller and is associated with the buffer being
++ * queued up.
++ */
++ void *cookie;
++
++ /*
++ * Pointer to the start of the buffer. In the transmit
++ * direction this points to the start of the payload. In the
++ * receive direction, however, the buffer when queued up
++ * points to the start of the HTC header but when returned
++ * to the caller points to the start of the payload
++ */
++ A_UCHAR *buffer;
++
++ /* Holds the length of the buffer */
++ A_UINT32 bufferLength;
++
++ /* Holds the length of the payload */
++ A_UINT32 actualLength;
++
++ HTC_ENDPOINT *endPoint;
++ } mboxBuffer;
++ struct htc_reg_buffer {
++ HTC_TARGET *target;
++ A_UCHAR *buffer;
++ A_UINT32 length;
++ TARGET_REGISTERS base;
++ A_UINT32 offset;
++ } regBuffer;
++ } u;
++ } buffer;
++};
++
++/* This is a FIFO queue of the pending data read/write requests. When a request
++has to be issued, the element at the head of the queue is dequeued and
++processed. New requests are added at the tail of the queue. The queue can only
++support a fixed number of requests and stops adding new requests once the total
++number of requests that are pending to be processed and the ones that are still
++under process reach the queue capacity */
++struct htc_data_request_queue {
++ A_UINT32 head;
++ A_UINT32 size;
++ HTC_DATA_REQUEST_ELEMENT element[HTC_DATA_REQUEST_RING_BUFFER_SIZE];
++};
++
++/* This is a list of 'free' register read/write requests. When a request has to
++be issued an element is taken from this list and after the completion of the
++request is added back to the list */
++struct htc_reg_request_list {
++ HTC_REG_REQUEST_ELEMENT element[HTC_REG_REQUEST_LIST_SIZE];
++};
++
++struct htc_endpoint {
++ /* Enabled or Disabled */
++ A_BOOL enabled;
++
++ /*
++ * Used to hold the length of the frame received from the target in
++ * case there are no buffers that have been queued up to receive the
++ * data.
++ */
++ A_UINT32 rxLengthPending;
++
++ /* Number of frames for which the target has space for at any time */
++ A_UINT8 txCreditsAvailable[1 + HTC_TX_CREDITS_NUM_MAX];
++
++ /*
++ * Number of frames that have been sent since the transmit credits
++ * were last updated.
++ */
++ A_UINT8 txCreditsConsumed;
++
++ A_BOOL txCreditsIntrEnable;
++
++ /* Pending Send Queue */
++ HTC_DATA_REQUEST_QUEUE sendQueue;
++
++ /* Pending Receive Queue */
++ HTC_DATA_REQUEST_QUEUE recvQueue;
++
++ /* Inverse reference to the target */
++ HTC_TARGET *target;
++
++ /* Block size configured for the endpoint */
++ A_UINT32 blockSize;
++
++ /* Event Table */
++ HTC_ENDPOINT_EVENT_TABLE eventTable;
++
++ /* Stating address of the endpoint */
++ A_UINT32 address;
++};
++
++/* ------- Target Related Data structures ------- */
++typedef struct htc_register_table HTC_REGISTER_TABLE;
++
++/*
++ * The following Register table only contain those registers that are used
++ * in HTC. It does not reflect the actual register layout in the hardware
++ */
++struct htc_register_table {
++ A_UINT8 host_int_status;
++ A_UINT8 cpu_int_status;
++ A_UINT8 error_int_status;
++ A_UINT8 counter_int_status;
++ A_UINT8 mbox_frame;
++ A_UINT8 rx_lookahead_valid;
++ A_UINT8 hole[2];
++ A_UINT32 rx_lookahead[HTC_MAILBOX_NUM_MAX];
++ A_UINT8 int_status_enable;
++ A_UINT8 cpu_int_status_enable;
++ A_UINT8 error_status_enable;
++ A_UINT8 counter_int_status_enable;
++ A_UINT8 int_wlan;
++};
++
++struct htc_target {
++ A_BOOL ready;
++ void *device; /* Handle to the device instance
++ reported by the bus driver */
++ HTC_ENDPOINT endPoint[HTC_MAILBOX_NUM_MAX];
++ HTC_REGISTER_TABLE table;
++ HTC_REG_REQUEST_LIST regList;
++};
++
++
++/* ------- Function Prototypes for Receive -------- */
++void
++htcReceiveFrame(HTC_ENDPOINT *endPoint);
++
++A_UINT32
++htcGetFrameLength(HTC_ENDPOINT *endPoint);
++
++
++/* ------- Function Prototypes for Transmit -------- */
++void
++htcSendFrame(HTC_ENDPOINT *endPoint);
++
++void
++htcSendBlkSize(HTC_ENDPOINT *endPoint);
++
++
++/* ------- Function Prototypes for Events and Callbacks ------- */
++A_STATUS
++htcRWCompletionHandler(void *element,
++ A_STATUS status);
++
++A_STATUS
++htcTxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status);
++
++A_STATUS
++htcBlkSzNegCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status);
++
++A_STATUS
++htcRxCompletionCB(HTC_DATA_REQUEST_ELEMENT *element,
++ A_STATUS status);
++
++A_STATUS
++htcRegCompletionCB(HTC_REG_REQUEST_ELEMENT *element,
++ A_STATUS status);
++
++A_STATUS
++htcTargetInsertedHandler(HIF_DEVICE *device);
++
++A_STATUS
++htcTargetRemovedHandler(HIF_DEVICE *device);
++
++A_STATUS
++htcDSRHandler(HIF_DEVICE *device);
++
++#ifdef CF
++A_STATUS
++htcInterruptDisabler(HIF_DEVICE *device,A_BOOL *callDsr);
++
++A_STATUS
++htcInterruptEnabler(HIF_DEVICE *device);
++#endif /* CF */
++
++void
++htcServiceCPUInterrupt(HTC_TARGET *target);
++
++void
++htcServiceErrorInterrupt(HTC_TARGET *target);
++
++void
++htcServiceCounterInterrupt(HTC_TARGET *target);
++
++void
++htcServiceMailboxInterrupt(HTC_TARGET *target);
++
++void
++htcEnableCreditCounterInterrupt(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId);
++
++void
++htcDisableCreditCounterInterrupt(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId);
++
++/* ------- Function Prototypes for Utility routines ------- */
++A_STATUS
++addToMboxQueue(HTC_DATA_REQUEST_QUEUE *queue,
++ A_UCHAR *buffer,
++ A_UINT32 bufferLength,
++ A_UINT32 actualLength,
++ void *cookie);
++
++HTC_DATA_REQUEST_ELEMENT *
++removeFromMboxQueue(HTC_DATA_REQUEST_QUEUE *queue);
++
++void
++flushMboxQueue(HTC_ENDPOINT *endPoint,
++ HTC_DATA_REQUEST_QUEUE *queue,
++ HTC_EVENT_ID eventId);
++
++HTC_REG_REQUEST_ELEMENT *
++allocateRegRequestElement(HTC_TARGET *target);
++
++void
++freeRegRequestElement(HTC_REG_REQUEST_ELEMENT *element);
++
++A_STATUS
++addToEventTable(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId,
++ HTC_EVENT_HANDLER handler,
++ void *param);
++
++A_STATUS
++removeFromEventTable(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId);
++
++void
++dispatchEvent(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId,
++ HTC_EVENT_INFO *eventInfo);
++
++HTC_TARGET *
++getTargetInstance(void *device);
++
++void
++addTargetInstance(HTC_TARGET *target);
++
++void
++delTargetInstance(HTC_TARGET *target);
++
++A_UINT32
++getRegAddr(TARGET_REGISTERS base,
++ HTC_ENDPOINT_ID endPointId);
++
++A_UINT8
++htcGetBitNumSet(A_UINT32 data);
++
++void
++dumpBytes(A_UCHAR *buffer, A_UINT16 length);
++
++void
++dumpRegisters(HTC_TARGET *target);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _HTC_INTERNAL_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_recv.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_recv.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,209 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the receive path.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++#ifdef DEBUG
++extern A_UINT32 debughtc;
++#endif
++
++/* ------ Static Variables ------ */
++
++
++/* ------ Functions ------ */
++/* Makes a buffer available to the HTC module */
++A_STATUS
++HTCBufferReceive(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ A_UCHAR *buffer,
++ A_UINT32 length,
++ void *cookie)
++{
++ A_STATUS status;
++ HTC_ENDPOINT *endPoint;
++ HTC_DATA_REQUEST_QUEUE *recvQueue;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("HTCBufferReceive: Enter (endPointId: %d, buffer: 0x%p, length: %d, cookie: 0x%p)\n", endPointId, buffer, length, cookie));
++
++ AR_DEBUG_ASSERT((endPointId >= ENDPOINT1) && (endPointId <= ENDPOINT4));
++
++ /* Extract the end point instance */
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++
++ recvQueue = &endPoint->recvQueue;
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV, ("recvQueue: %p\n",
++ recvQueue));
++
++ /* Add this posted buffer to the pending receive queue */
++ status = addToMboxQueue(recvQueue, buffer, length, 0, cookie);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++ ("Mailbox (%d) Send queue full. Unable to add buffer\n",
++ GET_ENDPOINT_ID(endPoint)));
++ return A_ERROR;
++ }
++
++ /*
++ * If this API was called as a result of a HTC_DATA_AVAILABLE event to
++ * the upper layer, indicating that HTC is out of buffers, then we should
++ * receive the frame in the buffer supplied otherwise we simply add the
++ * buffer to the Pending Receive Queue
++ */
++ if (endPoint->rxLengthPending) {
++ htcReceiveFrame(endPoint);
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("HTCBufferReceive: Exit\n"));
++ return A_OK;
++}
++
++void
++htcReceiveFrame(HTC_ENDPOINT *endPoint)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ A_UINT32 paddedLength;
++ A_UINT32 frameLength;
++ HIF_REQUEST request;
++ HTC_ENDPOINT_ID endPointId;
++ HTC_QUEUE_ELEMENT *element;
++ HTC_MBOX_BUFFER *mboxBuffer;
++ HTC_DATA_REQUEST_QUEUE *recvQueue;
++ HTC_TARGET *target;
++ HTC_EVENT_INFO eventInfo;
++ HIF_DATAMODE dmode;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("htcReceiveFrame - Enter\n"));
++
++ /* Get the context */
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ recvQueue = &endPoint->recvQueue;
++ AR_DEBUG_ASSERT(recvQueue != NULL);
++
++ /*
++ * Receive the frame if we have any pending frames and a buffer to
++ * receive it into.
++ */
++ if (IS_DATA_QUEUE_EMPTY(recvQueue)) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_WARN | ATH_DEBUG_RECV,
++ ("Mailbox (%d) recv queue empty. Unable to remove buffer\n", endPointId));
++
++ /*
++ * Communicate this situation to the host via the HTC_DATA_AVAILABLE
++ * event to request some buffers in the queue.
++ */
++ endPoint->rxLengthPending = htcGetFrameLength(endPoint);
++ AR_DEBUG_ASSERT(endPoint->rxLengthPending);
++ FRAME_EVENT(eventInfo, NULL, endPoint->rxLengthPending,
++ 0, A_OK, NULL);
++ dispatchEvent(target, endPointId, HTC_DATA_AVAILABLE, &eventInfo);
++ return;
++ }
++
++ /*
++ * Get the length from the lookahead register if there is nothing
++ * pending.
++ */
++ if (endPoint->rxLengthPending) {
++ frameLength = endPoint->rxLengthPending;
++ endPoint->rxLengthPending = 0;
++ } else {
++ frameLength = htcGetFrameLength(endPoint);
++ }
++ AR_DEBUG_ASSERT((frameLength > 0) &&
++ (frameLength <= HTC_MESSAGE_SIZE_MAX));
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_RECV, ("Frame Length: %d\n",
++ frameLength));
++
++ /* Adjust the length to be a multiple of block size if appropriate */
++ paddedLength = (frameLength + (endPoint->blockSize - 1)) &
++ (~(endPoint->blockSize - 1));
++
++ /*
++ * Receive the frame(s). Pull an empty buffer from the head of the
++ * Pending Receive Queue.
++ */
++ element = removeFromMboxQueue(recvQueue);
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ mboxBuffer->actualLength = paddedLength;
++ dmode = (endPoint->blockSize > 1) ? HIF_BLOCK_BASIS : HIF_BYTE_BASIS;
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, dmode, HIF_INCREMENTAL_ADDRESS);
++ address = endPoint->address;
++ status = HIFReadWrite(target->device, address, mboxBuffer->buffer,
++ mboxBuffer->actualLength, &request, element);
++#ifndef HTC_SYNC
++ if (status != A_OK) {
++#else
++ if (status != A_OK && status != A_PENDING) {
++#endif
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_RECV,
++ ("Frame reception failed\n"));
++ if (!IS_ELEMENT_FREE(element)) {
++ mboxBuffer->actualLength = 0;
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++ mboxBuffer->bufferLength, mboxBuffer->actualLength,
++ A_ECANCELED, mboxBuffer->cookie);
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++ dispatchEvent(target, endPointId, HTC_BUFFER_RECEIVED,
++ &eventInfo);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("htcReceiveFrame - Exit\n"));
++ return;
++ }
++ }
++#ifdef HTC_SYNC
++ else if (status == A_OK) {
++ element->completionCB(element, status);
++ }
++#endif
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_RECV,
++ ("htcReceiveFrame - Exit\n"));
++}
++
++A_UINT32
++htcGetFrameLength(HTC_ENDPOINT *endPoint)
++{
++ HTC_TARGET *target;
++ A_UINT32 frameLength;
++ HTC_ENDPOINT_ID endPointId;
++
++ /* Get the context */
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++
++ AR_DEBUG_ASSERT(target->table.rx_lookahead_valid & (1 << endPointId));
++
++ /* The length is contained in the first two bytes - HTC_HEADER_LEN */
++ frameLength = (target->table.rx_lookahead[endPointId] & 0xFFFF) +
++ HTC_HEADER_LEN;
++ AR_DEBUG_ASSERT(frameLength);
++
++ return frameLength;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_send.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_send.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,395 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the transmit path.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern A_MUTEX_T creditCS;
++
++#ifdef DEBUG
++extern A_UINT32 debughtc;
++extern A_UINT32 txcreditsavailable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditsconsumed[HTC_MAILBOX_NUM_MAX];
++#ifdef HTC_SYNC
++extern A_UINT32 txcreditintrenable[HTC_MAILBOX_NUM_MAX];
++extern A_UINT32 txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX];
++#endif
++#endif
++
++extern A_UINT32 tx_attempt[HTC_MAILBOX_NUM_MAX]; /* Num of attempts to add */
++extern A_UINT32 tx_post[HTC_MAILBOX_NUM_MAX]; /* Num of attemps succeded */
++extern A_UINT32 tx_complete[HTC_MAILBOX_NUM_MAX]; /* Num of tx complete */
++
++/* ------ Functions ------ */
++A_STATUS
++HTCBufferSend(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ A_UCHAR *buffer,
++ A_UINT32 length,
++ void *cookie)
++{
++ A_STATUS status;
++ HTC_ENDPOINT *endPoint;
++ HTC_DATA_REQUEST_QUEUE *sendQueue;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("HTCBufferSend: Enter (endPointId: %d, buffer: 0x%p, length: %d, cookie: 0x%p)\n", endPointId, buffer, length, cookie));
++
++ AR_DEBUG_ASSERT((endPointId >= ENDPOINT1) && (endPointId <= ENDPOINT4));
++ AR_DEBUG_ASSERT(length);
++
++ /* Extract the end point instance */
++ endPoint = &target->endPoint[endPointId];
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ sendQueue = &endPoint->sendQueue;
++ AR_DEBUG_ASSERT(sendQueue != NULL);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("mboxQueue: %p\n", sendQueue));
++
++ /*
++ * Add this posted buffer to the pending send queue. We need to allocate
++ * a bufferElement to store the packet information and we borrow that
++ * buffer from the pending send queue. If circumstances allow us to
++ * transmit it right away then we dequeue it otherwise we let it remain
++ * to be picked in the interrupt handler context.
++ */
++ tx_attempt[endPointId] += 1;
++
++ if (!endPoint->enabled) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Endpoint not enabled: %d\n",
++ GET_ENDPOINT_ID(endPoint)));
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("tx_attempt[%d] = %d, tx_post[%d] = %d, tx_complete[%d] = %d\n", endPointId, tx_attempt[endPointId], endPointId, tx_post[endPointId], endPointId, tx_complete[endPointId]));
++ return A_ERROR;
++ }
++
++ status = addToMboxQueue(sendQueue, buffer, length, 0, cookie);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++ ("Mailbox (%d) PSQ full. Unable to add buffer\n",
++ endPointId));
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
++ ("tx_attempt[%d] = %d, tx_post[%d] = %d, tx_complete[%d] = %d\n", endPointId, tx_attempt[endPointId], endPointId, tx_post[endPointId], endPointId, tx_complete[endPointId]));
++ return A_ERROR;
++ }
++
++ tx_post[endPointId] += 1;
++
++ /*
++ * The frame shall be dequeued and sent if there are any credits
++ * available.
++ */
++ htcSendFrame(endPoint);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND, ("HTCBufferSend: Exit\n"));
++ return A_OK;
++}
++
++
++void
++htcSendFrame(HTC_ENDPOINT *endPoint)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HIF_DATAMODE dmode;
++ HTC_TARGET *target;
++ HIF_REQUEST request;
++ A_UINT32 frameLength;
++ A_UINT32 paddedLength;
++ HTC_EVENT_INFO eventInfo;
++ A_UINT8 txCreditsConsumed;
++ A_UINT8 txCreditsAvailable;
++ HTC_ENDPOINT_ID endPointId;
++ HTC_QUEUE_ELEMENT *element;
++ HTC_MBOX_BUFFER *mboxBuffer;
++ HTC_REG_REQUEST_LIST *regList;
++ HTC_DATA_REQUEST_QUEUE *sendQueue;
++#ifdef HTC_SYNC
++ HTC_REG_BUFFER *regBuffer;
++#endif
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND, ("htcSendFrame - Enter\n"));
++
++ /* Get the context */
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ sendQueue = &endPoint->sendQueue;
++ AR_DEBUG_ASSERT(sendQueue != NULL);
++ regList = &target->regList;
++ AR_DEBUG_ASSERT(regList != NULL);
++
++ /*
++ * Transmit the frames as long as we have the credits available and
++ * the queue is not out of them
++ */
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): LOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&creditCS);
++ txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++ txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++ SET_TX_CREDITS_AVAILABLE(endPoint, 0);
++ SET_TX_CREDITS_CONSUMED(endPoint, txCreditsConsumed + txCreditsAvailable);
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&creditCS);
++
++ /*
++ * Send the packet only when there are packets to be sent and there
++ * are positive number of credits available.
++ */
++ while((!IS_DATA_QUEUE_EMPTY(sendQueue)) && txCreditsAvailable)
++ {
++ /* Get the request buffer from the Pending Send Queue */
++ element = removeFromMboxQueue(sendQueue);
++ mboxBuffer = GET_MBOX_BUFFER(element);
++
++ /*
++ * Prepend the actual length in the first 2 bytes of the outgoing
++ * packet.
++ */
++ mboxBuffer->buffer -= HTC_HEADER_LEN;
++ A_MEMCPY(mboxBuffer->buffer, &mboxBuffer->bufferLength, HTC_HEADER_LEN);
++
++ /*
++ * Adjust the length in the block mode only when its not an integral
++ * multiple of the block size. Assumption is that the block size is
++ * a power of 2.
++ */
++ frameLength = mboxBuffer->bufferLength + HTC_HEADER_LEN;
++ paddedLength = (frameLength + (endPoint->blockSize - 1)) &
++ (~(endPoint->blockSize - 1));
++ mboxBuffer->actualLength = paddedLength;
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Original frame length: %d, Padded frame length: %d\n", frameLength, paddedLength));
++
++ AR_DEBUG_PRINTBUF(mboxBuffer->buffer, mboxBuffer->actualLength);
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Available Tx credits: %d\n", txCreditsAvailable));
++
++ /* Frame the interface request */
++ dmode = (endPoint->blockSize > 1) ? HIF_BLOCK_BASIS : HIF_BYTE_BASIS;
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, dmode, HIF_INCREMENTAL_ADDRESS);
++ address = endPoint->address;
++
++ /* Send the data to the bus driver */
++ status = HIFReadWrite(target->device, address, mboxBuffer->buffer,
++ mboxBuffer->actualLength, &request, element);
++#ifndef HTC_SYNC
++ if (status != A_OK) {
++#else
++ if (status != A_OK && status != A_PENDING) {
++#endif
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++ ("Frame transmission failed\n"));
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR | ATH_DEBUG_SEND,
++ ("EndPoint: %d, Tx credits available: %d\n",
++ endPointId, GET_TX_CREDITS_AVAILABLE(endPoint)));
++ /*
++ * We need to check just in case the callback routine was called
++ * with the error status before we reach this point and in that
++ * context we fee up the buffer so its just a conservative design.
++ */
++ if (!IS_ELEMENT_FREE(element)) {
++ mboxBuffer->buffer += HTC_HEADER_LEN;
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++ mboxBuffer->bufferLength,
++ mboxBuffer->actualLength,
++ A_ECANCELED, mboxBuffer->cookie);
++ RECYCLE_DATA_REQUEST_ELEMENT(element);
++ dispatchEvent(target, endPointId, HTC_BUFFER_SENT, &eventInfo);
++ }
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcSendFrame - Exit\n"));
++ return;
++ }
++#ifdef HTC_SYNC
++ else if (status == A_OK) {
++ element->completionCB(element, status);
++ }
++#endif
++ txCreditsAvailable -= 1;
++ txCreditsConsumed += 1;
++
++#ifdef DEBUG
++ txcreditsavailable[endPointId] = txCreditsAvailable;
++ txcreditsconsumed[endPointId] = txCreditsConsumed;
++#endif /* DEBUG */
++
++ if (!txCreditsAvailable) {
++
++ AR_DEBUG_ASSERT(txCreditsConsumed);
++
++ /*
++ * Instead of taking an interrupt we can just poll for more
++ * credits that might have been queued up by now.
++ */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO,
++ HIF_ASYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_FIXED_ADDRESS);
++ address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, endPointId);
++ element = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(element != NULL);
++ FILL_REG_BUFFER(element, &endPoint->txCreditsAvailable[1],
++ txCreditsConsumed, TX_CREDIT_COUNTER_DECREMENT_REG,
++ endPointId);
++ status = HIFReadWrite(target->device, address,
++ &endPoint->txCreditsAvailable[1],
++ txCreditsConsumed, &request, element);
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND,
++ ("htcSendFrame - Exit\n"));
++ return;
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if ( status == A_OK ) {
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): LOCK at line %d in file %s \n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&creditCS);
++
++ regBuffer = GET_REG_BUFFER(element);
++ /* Calculate the number of credits available */
++ AR_DEBUG_ASSERT(GET_TX_CREDITS_CONSUMED(endPoint) == \
++ regBuffer->length);
++ SET_TX_CREDITS_AVAILABLE(endPoint, regBuffer->buffer[0] -
++ GET_TX_CREDITS_CONSUMED(endPoint));
++ SET_TX_CREDITS_CONSUMED(endPoint, 0);
++ txCreditsAvailable = GET_TX_CREDITS_AVAILABLE(endPoint);
++ txCreditsConsumed = GET_TX_CREDITS_CONSUMED(endPoint);
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&creditCS);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Pulling %d tx credits from the target\n",
++ txCreditsAvailable));
++
++ #ifdef DEBUG
++ txcreditsavailable[endPointId] = txCreditsAvailable;
++ txcreditsconsumed[endPointId] = txCreditsConsumed;
++ #endif /* DEBUG */
++
++ freeRegRequestElement(element);
++
++ if (!txCreditsAvailable) {
++
++ /* Enable the Tx credit counter interrupt so that we can get
++ * the credits posted by the target */
++
++ htcEnableCreditCounterInterrupt(target, endPointId);
++
++ /* Counter Interrupts have been enabled if
++ * txCreditsAvailable is still 0 after polling. We need to
++ * return here as there is nothing we can send till we get
++ * a Counter Interrupt.
++ */
++ return;
++ }
++ }
++#endif
++ }
++ }
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): LOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&creditCS);
++ SET_TX_CREDITS_AVAILABLE(endPoint, txCreditsAvailable);
++ SET_TX_CREDITS_CONSUMED(endPoint, txCreditsConsumed);
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (credit): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&creditCS);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRC | ATH_DEBUG_SEND, ("htcSendFrame - Exit\n"));
++}
++
++void
++htcSendBlkSize(HTC_ENDPOINT *endPoint)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ HTC_TARGET *target;
++ HIF_REQUEST request;
++ HTC_ENDPOINT_ID endPointId;
++ HTC_QUEUE_ELEMENT *element;
++ HTC_MBOX_BUFFER *mboxBuffer;
++ HTC_DATA_REQUEST_QUEUE *sendQueue;
++ HTC_REG_REQUEST_LIST *regList;
++
++ /* Get the context */
++ AR_DEBUG_ASSERT(endPoint != NULL);
++ target = endPoint->target;
++ AR_DEBUG_ASSERT(target != NULL);
++ regList = &target->regList;
++ AR_DEBUG_ASSERT(regList != NULL);
++ sendQueue = &endPoint->sendQueue;
++ AR_DEBUG_ASSERT(sendQueue != NULL);
++ endPointId = GET_ENDPOINT_ID(endPoint);
++
++ /* Decrement the tx credit count */
++ AR_DEBUG_ASSERT(endPoint->txCreditsConsumed == 0);
++ endPoint->txCreditsConsumed = 1;
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_ASYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, endPointId);
++ element = allocateRegRequestElement(target);
++ AR_DEBUG_ASSERT(element != NULL);
++ FILL_REG_BUFFER(element, &endPoint->txCreditsAvailable[1],
++ endPoint->txCreditsConsumed,
++ TX_CREDIT_COUNTER_DECREMENT_REG, endPointId);
++ status = HIFReadWrite(target->device, address,
++ &endPoint->txCreditsAvailable[1],
++ endPoint->txCreditsConsumed, &request, element);
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if (status == A_OK) {
++ element->completionCB(element, status);
++ }
++#endif
++
++ /* Negotiate the maximum block size for the endpoint */
++ addToMboxQueue(sendQueue, (A_UCHAR *)&endPoint->blockSize,
++ sizeof(endPoint->blockSize), sizeof(endPoint->blockSize),
++ NULL);
++ element = removeFromMboxQueue(sendQueue);
++ element->completionCB = htcBlkSzNegCompletionCB;
++ mboxBuffer = GET_MBOX_BUFFER(element);
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_ASYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
++ address = endPoint->address;
++ status = HIFReadWrite(target->device, address, mboxBuffer->buffer,
++ mboxBuffer->bufferLength, &request, element);
++#ifndef HTC_SYNC
++ AR_DEBUG_ASSERT(status == A_OK);
++#else
++ AR_DEBUG_ASSERT(status == A_OK || status == A_PENDING);
++ if (status == A_OK) {
++ element->completionCB(element, status);
++ }
++#endif
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF | ATH_DEBUG_SEND,
++ ("Mailbox(%d), Block size: %d\n",
++ endPointId, endPoint->blockSize));
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_utils.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/htc_utils.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,374 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the utility routines used across the entire HTC module.
++ */
++
++#include "htc_internal.h"
++
++/* ------ Global Variable Declarations ------- */
++extern HTC_TARGET *AtherosTargetList[HIF_MAX_DEVICES];
++extern HTC_GLOBAL_EVENT_TABLE AtherosEventTable;
++extern A_MUTEX_T instanceCS;
++
++#ifdef DEBUG
++extern A_UINT32 debughtc;
++#endif
++
++/* ------ Static Variables ------ */
++
++/* ------ Functions ------ */
++void
++dispatchEvent(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId,
++ HTC_EVENT_INFO *eventInfo)
++{
++ EVENT_TABLE_ELEMENT *eventElement;
++
++ if (eventId == HTC_TARGET_AVAILABLE) {
++ eventElement = &AtherosEventTable.element[0];
++ } else if (eventId == HTC_TARGET_UNAVAILABLE) {
++ eventElement = &AtherosEventTable.element[1];
++ } else {
++ eventElement =
++ &target->endPoint[endPointId].eventTable.element[eventId];
++ }
++ AR_DEBUG_ASSERT(eventElement != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("dispatchEvent(endpoint: %d, eventId: 0x%d, handler: 0x%p)\n", endPointId, eventElement->id, eventElement->handler));
++ if (eventElement->handler) {
++ eventElement->handler(target, endPointId, eventId, eventInfo,
++ eventElement->param);
++ }
++}
++
++
++A_STATUS
++addToEventTable(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId,
++ HTC_EVENT_HANDLER handler,
++ void *param)
++{
++ EVENT_TABLE_ELEMENT *new;
++
++ if (eventId == HTC_TARGET_AVAILABLE) {
++ new = &AtherosEventTable.element[0];
++ } else if (eventId == HTC_TARGET_UNAVAILABLE) {
++ new = &AtherosEventTable.element[1];
++ } else {
++ new = &target->endPoint[endPointId].eventTable.element[eventId];
++ }
++
++ /* Store the event id, the corresponding handler and the param passed */
++ new->id = eventId;
++ new->handler = handler;
++ new->param = param;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("addToEventTable(endpoint: %d, eventId: 0x%d, handler: 0x%p)\n", endPointId, new->id, new->handler));
++
++ return A_OK;
++}
++
++
++A_STATUS
++removeFromEventTable(HTC_TARGET *target,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId)
++{
++ EVENT_TABLE_ELEMENT *remove;
++
++ if (eventId == HTC_TARGET_AVAILABLE) {
++ remove = &AtherosEventTable.element[0];
++ } else if (eventId == HTC_TARGET_UNAVAILABLE) {
++ remove = &AtherosEventTable.element[1];
++ } else {
++ remove = &target->endPoint[endPointId].eventTable.element[eventId];
++ }
++
++ /* Remove the event handler */
++ A_MEMZERO(remove, sizeof(EVENT_TABLE_ELEMENT));
++
++ return A_OK;
++}
++
++A_STATUS
++addToMboxQueue(HTC_DATA_REQUEST_QUEUE *queue,
++ A_UCHAR *buffer,
++ A_UINT32 bufferLength,
++ A_UINT32 actualLength,
++ void *cookie)
++{
++ A_STATUS status;
++ HTC_DATA_REQUEST_ELEMENT *element;
++
++ AR_DEBUG_ASSERT(queue != NULL);
++ AR_DEBUG_ASSERT(bufferLength);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (queue): LOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&instanceCS);
++ element = GET_QUEUE_TAIL(queue);
++ if (!(IS_DATA_QUEUE_FULL(queue)) && IS_ELEMENT_FREE(element)) {
++ element->buffer.free = FALSE;
++ FILL_MBOX_BUFFER(element, buffer, bufferLength, actualLength, cookie);
++ queue->size += 1;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("addToMboxQueue (index: %d, size: %d, bufferElement: 0x%p, bufferElement->buffer: 0x%p, bufferElement->cookie: 0x%p)\n", (queue->head + queue->size - 1) % HTC_DATA_REQUEST_RING_BUFFER_SIZE, queue->size, element, (GET_MBOX_BUFFER(element))->buffer, (GET_MBOX_BUFFER(element))->cookie));
++ status = A_OK;
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Queue size: %d\n", queue->size));
++ status = A_ERROR;
++ }
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (queue): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&instanceCS);
++
++ return status;
++}
++
++HTC_DATA_REQUEST_ELEMENT *
++removeFromMboxQueue(HTC_DATA_REQUEST_QUEUE *queue) {
++ HTC_DATA_REQUEST_ELEMENT *element;
++ AR_DEBUG_ASSERT(queue != NULL);
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (queue): LOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_LOCK(&instanceCS);
++ if (!(IS_DATA_QUEUE_EMPTY(queue))) {
++ element = GET_QUEUE_HEAD(queue);
++ queue->head = (queue->head + 1) % HTC_DATA_REQUEST_RING_BUFFER_SIZE;
++ queue->size -= 1;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_INF,
++ ("removeFromMboxQueue (index: %d, size: %d, bufferElement: 0x%p, bufferElement->buffer: 0x%p, bufferElement->cookie: 0x%p)\n", queue->head, queue->size, element, (GET_MBOX_BUFFER(element))->buffer, (GET_MBOX_BUFFER(element))->cookie));
++ } else {
++ element = NULL;
++ }
++ AR_DEBUG_PRINTF(ATH_DEBUG_SYNC,
++ ("Critical Section (queue): UNLOCK at line %d in file %s\n", __LINE__, __FILE__));
++ A_MUTEX_UNLOCK(&instanceCS);
++
++ return element;
++}
++
++void
++flushMboxQueue(HTC_ENDPOINT *endPoint,
++ HTC_DATA_REQUEST_QUEUE *queue,
++ HTC_EVENT_ID eventId)
++{
++ HTC_DATA_REQUEST_ELEMENT *curr;
++ HTC_EVENT_INFO eventInfo;
++ HTC_ENDPOINT_EVENT_TABLE *eventTable;
++ HTC_ENDPOINT_ID endPointId;
++ EVENT_TABLE_ELEMENT *eventElement;
++ HTC_MBOX_BUFFER *mboxBuffer;
++
++ eventTable = &endPoint->eventTable;
++ endPointId = GET_ENDPOINT_ID(endPoint);
++
++ /*
++ * Release the buffer to WMI using the registered event handler. If WMI
++ * has not registered any callbacks for a particular endpoint then it
++ * means that its queues will not have any buffers so we skip that
++ * endpoint.
++ */
++ if ((eventElement = &eventTable->element[eventId]) != NULL) {
++ while ((curr = removeFromMboxQueue(queue)) != NULL) {
++ /* Frame the event and dispatch it */
++ mboxBuffer = GET_MBOX_BUFFER(curr);
++ FRAME_EVENT(eventInfo, mboxBuffer->buffer,
++ mboxBuffer->bufferLength, mboxBuffer->actualLength,
++ A_ECANCELED, mboxBuffer->cookie);
++ if (eventElement->handler) {
++ eventElement->handler(endPoint->target, endPointId, eventId,
++ &eventInfo, eventElement->param);
++ }
++ RECYCLE_DATA_REQUEST_ELEMENT(curr);
++ }
++ }
++
++ /* Initialize the head and tail pointer */
++ queue->head = 0;
++ queue->size = 0;
++}
++
++HTC_REG_REQUEST_ELEMENT *
++allocateRegRequestElement(HTC_TARGET *target) {
++ A_UINT32 count;
++ HTC_REG_REQUEST_ELEMENT *element;
++
++ A_MUTEX_LOCK(&instanceCS);
++ element = NULL;
++ for (count = 0; count < HTC_REG_REQUEST_LIST_SIZE; count ++) {
++ element = &target->regList.element[count];
++ if (IS_ELEMENT_FREE(element)) {
++ element->buffer.free = FALSE;
++ break;
++ }
++ }
++ A_MUTEX_UNLOCK(&instanceCS);
++
++ return element;
++}
++
++void
++freeRegRequestElement(HTC_REG_REQUEST_ELEMENT *element) {
++ A_MUTEX_LOCK(&instanceCS);
++ FILL_REG_BUFFER(element, NULL, 0, 0, 0);
++ element->buffer.free = TRUE;
++ A_MUTEX_UNLOCK(&instanceCS);
++}
++
++HTC_TARGET *
++getTargetInstance(void *device)
++{
++ return AtherosTargetList[0];
++}
++
++void
++addTargetInstance(HTC_TARGET *target)
++{
++ AtherosTargetList[0] = target;
++}
++
++void
++delTargetInstance(HTC_TARGET *target)
++{
++ AtherosTargetList[0] = NULL;
++}
++
++A_UINT32
++getRegAddr(TARGET_REGISTERS base,
++ HTC_ENDPOINT_ID endPointId)
++{
++ A_UINT32 address;
++
++ switch(base) {
++ case TX_CREDIT_COUNTER_RESET_REG:
++ address = COUNT_DEC_ADDRESS + endPointId * 4;
++ break;
++
++ case TX_CREDIT_COUNTER_DECREMENT_REG:
++ address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + endPointId) * 4;
++ break;
++
++ case TX_CREDIT_COUNTER_REG:
++ address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + endPointId) * 4;
++ break;
++
++ case INT_STATUS_ENABLE_REG:
++ address = INT_STATUS_ENABLE_ADDRESS;
++ break;
++
++ case COUNTER_INT_STATUS_ENABLE_REG:
++ case COUNTER_INT_STATUS_DISABLE_REG:
++ address = COUNTER_INT_STATUS_ENABLE_ADDRESS;
++ break;
++
++ case INT_STATUS_REG:
++ address = HOST_INT_STATUS_ADDRESS;
++ break;
++
++ case CPU_INT_STATUS_REG:
++ address = CPU_INT_STATUS_ADDRESS;
++ break;
++
++ case ERROR_INT_STATUS_REG:
++ address = ERROR_INT_STATUS_ADDRESS;
++ break;
++
++ case INT_WLAN_REG:
++ address = INT_WLAN_ADDRESS;
++ break;
++
++ case WINDOW_DATA_REG:
++ address = WINDOW_DATA_ADDRESS;
++ break;
++
++ case WINDOW_WRITE_ADDR_REG:
++ address = WINDOW_WRITE_ADDR_ADDRESS;
++ break;
++
++ case WINDOW_READ_ADDR_REG:
++ address = WINDOW_READ_ADDR_ADDRESS;
++ break;
++
++ default:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid register: %d\n", base));
++ AR_DEBUG_ASSERT(0);
++ address = 0;
++ break;
++ }
++
++ return address;
++}
++
++void
++dumpBytes(A_UCHAR *buffer, A_UINT16 length)
++{
++ A_CHAR stream[60];
++ A_UINT32 i;
++ A_UINT16 offset, count;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("Dumping %d Bytes : ------>\n", length));
++
++ count = 0;
++ offset = 0;
++ for(i = 0; i < length; i++) {
++ sprintf(stream + offset, "%2x ", buffer[i]);
++ count ++;
++ offset += 3;
++
++ if(count == 16) {
++ count = 0;
++ offset = 0;
++ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("[H]: %s\n", stream));
++ A_MEMZERO(stream, 60);
++ }
++ }
++
++ if(offset != 0) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("[H]: %s\n", stream));
++ }
++}
++
++void
++dumpRegisters(HTC_TARGET *target)
++{
++ HTC_REGISTER_TABLE *reg;
++
++ reg = &target->table;
++ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\nInt Status: 0x%x\nCPU Int Status: 0x%x\nError Int Status: 0x%x\nCounter Int Status: 0x%x\nMbox Frame: 0x%x\nRx Lookahead Valid: 0x%x\nRx Lookahead 0: 0x%x\nRx Lookahead 1: 0x%x\nRx Lookahead 2: 0x%x\nRx Lookahead 3: 0x%x\nInt Status Enable: 0x%x\nCounter Int Status Enable: 0x%x\n<------------------------------->\n", reg->host_int_status, reg->cpu_int_status, reg->error_int_status, reg->counter_int_status, reg->mbox_frame, reg->rx_lookahead_valid, reg->rx_lookahead[ENDPOINT1], reg->rx_lookahead[ENDPOINT2], reg->rx_lookahead[ENDPOINT3], reg->rx_lookahead[ENDPOINT4], reg->int_status_enable, reg->counter_int_status_enable));
++}
++
++A_UINT8
++htcGetBitNumSet(A_UINT32 data)
++{
++ A_UINT8 count;
++
++ count = 0;
++ while(!(data & 0x1)) {
++ count += 1;
++ data >>= 1;
++ }
++
++ return count;
++}
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/dset_api.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/dset_api.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,49 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * Host-side DataSet API.
++ *
++ */
++
++#ifndef _DSET_API_H_
++#define _DSET_API_H_
++
++/*
++ * Host-side DataSet support is optional, and is not
++ * currently required for correct operation. To disable
++ * Host-side DataSet support, set this to 0.
++ */
++#define CONFIG_HOST_DSET_SUPPORT 1
++
++/* Called to send a DataSet Open Reply back to the Target. */
++A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
++ A_UINT32 status,
++ A_UINT32 access_cookie,
++ A_UINT32 size,
++ A_UINT32 version,
++ A_UINT32 targ_handle,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg);
++
++/* Called to send a DataSet Data Reply back to the Target. */
++A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
++ A_UINT32 status,
++ A_UINT8 *host_buf,
++ A_UINT32 length,
++ A_UINT32 targ_buf,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg);
++
++#endif /* _DSET_API_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/gpio_api.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/gpio_api.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,64 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ */
++
++#ifndef _GPIO_API_H_
++#define _GPIO_API_H_
++
++/*
++ * Host-side GPIO support is optional.
++ * If run-time access to GPIO pins is not required, then
++ * this should be changed to 0.
++ */
++#define CONFIG_HOST_GPIO_SUPPORT 1
++
++/*
++ * Host-side General Purpose I/O API.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/host/include/gpio_api.h#2 $
++ */
++
++/*
++ * Send a command to the Target in order to change output on GPIO pins.
++ */
++A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
++ A_UINT32 set_mask,
++ A_UINT32 clear_mask,
++ A_UINT32 enable_mask,
++ A_UINT32 disable_mask);
++
++/*
++ * Send a command to the Target requesting input state of GPIO pins.
++ */
++A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
++
++/*
++ * Send a command to the Target to change the value of a GPIO register.
++ */
++A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
++ A_UINT32 gpioreg_id,
++ A_UINT32 value);
++
++/*
++ * Send a command to the Target to fetch the value of a GPIO register.
++ */
++A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
++
++/*
++ * Send a command to the Target, acknowledging some GPIO interrupts.
++ */
++A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
++
++#endif /* _GPIO_API_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hif.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hif.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,207 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * HIF specific declarations and prototypes
++ */
++
++#ifndef _HIF_H_
++#define _HIF_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++/* Header files */
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++
++typedef struct htc_callbacks HTC_CALLBACKS;
++typedef struct hif_request HIF_REQUEST;
++typedef struct hif_device HIF_DEVICE;
++
++typedef enum {
++ HIF_READ,
++ HIF_WRITE
++} HIF_DIRECTION;
++
++typedef enum {
++ HIF_BASIC_IO,
++ HIF_EXTENDED_IO
++} HIF_CMDTYPE;
++
++typedef enum {
++ HIF_SYNCHRONOUS,
++ HIF_ASYNCHRONOUS
++} HIF_EXECMODE;
++
++typedef enum {
++ HIF_BYTE_BASIS,
++ HIF_BLOCK_BASIS
++} HIF_DATAMODE;
++
++typedef enum {
++ HIF_FIXED_ADDRESS,
++ HIF_INCREMENTAL_ADDRESS
++} HIF_ADDRMODE;
++
++typedef enum {
++ HIF_DEVICE_POWER_STATE,
++ HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
++ HIF_DEVICE_GET_MBOX_ADDR,
++} HIF_DEVICE_CONFIG_OPCODE;
++
++#define HIF_MAX_DEVICES 1
++
++#define HIF_FRAME_REQUEST(request, _direction, _type, \
++ _emode, _dmode, _amode) do { \
++ (request)->direction = _direction; \
++ (request)->type = _type; \
++ (request)->emode = _emode; \
++ (request)->dmode = _dmode; \
++ (request)->amode = _amode; \
++} while(0)
++
++struct htc_callbacks {
++ A_UCHAR *name;
++ A_UINT32 id;
++ A_STATUS (* deviceInsertedHandler)(HIF_DEVICE *device);
++ A_STATUS (* deviceRemovedHandler)(HIF_DEVICE *device);
++ A_STATUS (* deviceSuspendHandler)(HIF_DEVICE *device);
++ A_STATUS (* deviceResumeHandler)(HIF_DEVICE *device);
++ A_STATUS (* deviceWakeupHandler)(HIF_DEVICE *device);
++ A_STATUS (* rwCompletionHandler)(void *context, A_STATUS status);
++#ifdef CF
++ A_STATUS (* deviceInterruptDisabler)(HIF_DEVICE *device,A_BOOL *callDsr);
++ A_STATUS (* deviceInterruptEnabler)(HIF_DEVICE *device);
++#endif /* CF */
++ A_STATUS (* dsrHandler)(HIF_DEVICE *device);
++};
++
++/*
++ * The request structure captures different attributes that can precisely
++ * characterize a command and its behavior for different physical interfaces.
++ */
++struct hif_request {
++ HIF_DIRECTION direction; /* HIF_READ/HIF_WRITE */
++ HIF_CMDTYPE type; /* HIF_BASIC_IO/HIF_EXTENDED_IO */
++ HIF_EXECMODE emode; /* HIF_SYNCHRONOUS/HIF_ASYNCHRONOUS */
++ HIF_DATAMODE dmode; /* HIF_BYTE_BASIS/HIF_BLOCK_BASIS */
++ HIF_ADDRMODE amode; /* HIF_FIXED_ADDRESS/HIF_INCREMENTAL_ADDRESS */
++};
++
++/*
++ * This API is used by the HTC layer to register different callback routines
++ * with the HIF layer. Support for following events has been captured - DSR,
++ * Read/Write completion, Device insertion/removal, Device suspension/
++ * resumption/wakeup. In addition to this, the API is also used to register
++ * the name and the revision of the chip. The latter can be used to verify
++ * the revision of the chip read from the device before reporting it to HTC.
++ */
++void
++HIFRegisterCallbacks(HTC_CALLBACKS *callbacks);
++
++/*
++ * This API is used to provide the read/write interface over the specific bus
++ * interface.
++ * address - Starting address in the dragon's address space. For mailbox
++ * writes, it refers to the start of the mbox boundary. It should
++ * be ensured that the last byte falls on the mailbox's EOM. For
++ * mailbox reads, it refers to the end of the mbox boundary.
++ * buffer - Pointer to the buffer containg the data to be transmitted or
++ * received.
++ * length - Amount of data to be transmitted or received.
++ * request - Characterizes the attributes of the command.
++ * direction - Direction of transfer (HIF_READ/HIF_WRITE).
++ * type - An interface may support different kind of read/write commands.
++ * For example: SDIO supports CMD52/CMD53s. The command type
++ * is thus divided into a basic and an extended command and can
++ * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
++ * emode - This indicates the whether the command is to be executed in a
++ * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
++ * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
++ * implemented using the asynchronous mode allowing the the bus
++ * driver to indicate the completion of operation through the
++ * registered callback routine. The requirement primarily comes
++ * from the contexts these operations get called from (a driver's
++ * transmit context or the ISR context in case of receive).
++ * Support for both of these modes is essential.
++ * dmode - An interface may support different kinds of commands based on
++ * the tradeoff between the amount of data it can carry and the
++ * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
++ * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
++ * to the nearest block size by padding. The size of the block is
++ * configurable at compile time using the HIF_BLOCK_SIZE and is
++ * negotiated with the target during initialization after the
++ * dragon interrupts are enabled.
++ * amode - This indicates if the address has to be incremented on dragon
++ * after every read/write operation (HIF?FIXED_ADDRESS/
++ * HIF_INCREMENTAL_ADDRESS).
++ */
++A_STATUS
++HIFReadWrite(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length,
++ HIF_REQUEST *request,
++ void *context);
++
++#if 0
++Not required since the hif layer can automatically do all this once the device
++is discovered and then report the instance to the HTC layer only after
++everything is successfully finished.
++/*
++ * This is called right after the device insertion event is reported to HTC.
++ * It is expected to perform atleast the following functions:
++ * i) Configure the interface - bus width, clock rate, operational current.
++ * ii) Enable the interrupts and unmask any IRQs.
++ * iii) Enable dragon by writing to the IO Enable bit if the interface supports
++ * one.
++ */
++A_STATUS
++HIFInitializeInterface(void *device);
++#endif
++
++/*
++ * This can be initiated from the unload driver context ie when the HTCShutdown
++ * routine is called.
++ */
++void
++HIFShutDownDevice(HIF_DEVICE *device);
++
++/*
++ * This should translate to an acknowledgment to the bus driver indicating that
++ * the previous interrupt request has been serviced and the all the relevant
++ * sources have been cleared. HTC is ready to process more interrupts.
++ * This should prevent the bus driver from raising an interrupt unless the
++ * previous one has been serviced and acknowledged using the previous API.
++ */
++void
++HIFAckInterrupt(HIF_DEVICE *device);
++
++void
++HIFMaskInterrupt(HIF_DEVICE *device);
++
++void
++HIFUnMaskInterrupt(HIF_DEVICE *device);
++
++A_STATUS
++HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
++ void *config, A_UINT32 configLen);
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _HIF_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/host_version.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/host_version.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains version information for the sample host driver for the
++ * AR6000 chip
++ *
++ *
++ */
++
++#ifndef _HOST_VERSION_H_
++#define _HOST_VERSION_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "../include/AR6000_version.h"
++
++/*
++ * The version number is made up of major, minor, patch and build
++ * numbers. These are 16 bit numbers. The build and release script will
++ * set the build number using a Perforce counter. Here the build number is
++ * set to 9999 so that builds done without the build-release script are easily
++ * identifiable.
++ */
++
++#define ATH_SW_VER_MAJOR __VER_MAJOR_
++#define ATH_SW_VER_MINOR __VER_MINOR_
++#define ATH_SW_VER_PATCH __VER_PATCH_
++#define ATH_SW_VER_BUILD 2
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _HOST_VERSION_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/htc.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/htc.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,120 @@
++/*
++ * Copyright (c) 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * htc.h - HTC Module specific declarations and prototypes
++ */
++
++#ifndef _HTC_H_
++#define _HTC_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++/* ------ MBOX ID ------ */
++typedef enum
++{
++ ENDPOINT_UNUSED = -1,
++ ENDPOINT1 = 0,
++ ENDPOINT2,
++ ENDPOINT3,
++ ENDPOINT4,
++} HTC_ENDPOINT_ID;
++
++/* ------ Event Types ------ */
++typedef enum
++{
++ HTC_BUFFER_RECEIVED = 0,
++ HTC_SKB_RECEIVED,
++ HTC_BUFFER_SENT,
++ HTC_SKB_SENT,
++ HTC_DATA_AVAILABLE,
++ HTC_TARGET_AVAILABLE,
++ HTC_TARGET_UNAVAILABLE,
++} HTC_EVENT_ID;
++
++#define HTC_MAILBOX_NUM_MAX 4
++#define HTC_HEADER_LEN 2
++#define HTC_DATA_REQUEST_RING_BUFFER_SIZE 30
++
++/* ------- Target Specific Data structures ------- */
++typedef struct htc_target HTC_TARGET;
++
++/* ------- Event Specific Data Structures ------- */
++typedef struct htc_event_info HTC_EVENT_INFO;
++typedef void (*HTC_EVENT_HANDLER) (HTC_TARGET *,
++ HTC_ENDPOINT_ID,
++ HTC_EVENT_ID,
++ HTC_EVENT_INFO *,
++ void *);
++
++/* WMI layer extracts the relevant information from this data structure */
++struct htc_event_info
++{
++ A_UCHAR *buffer;
++ void *cookie;
++ A_UINT32 bufferLength;
++ A_UINT32 actualLength;
++ A_STATUS status;
++};
++
++/* ------ Function Prototypes ------ */
++A_STATUS
++HTCInit(void);
++
++A_STATUS
++HTCStart(HTC_TARGET *target);
++/* target - IN */
++
++A_STATUS
++HTCEventReg(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID eventId, HTC_EVENT_HANDLER eventHandler,
++ void *param);
++/* target - IN, endPointId - IN, eventId - IN, eventHandler - IN, param - IN */
++
++A_STATUS
++HTCBufferReceive(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ A_UCHAR *buffer, A_UINT32 length, void *cookie);
++/* target - IN, endPointId - IN, buffer - IN, length - IN, cookie - IN */
++
++#if 0
++A_STATUS
++HTCSkbReceive(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ struct sk_buff *skb, void *cookie);
++#endif
++
++A_STATUS
++HTCBufferSend(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ A_UCHAR *buffer, A_UINT32 length, void *cookie);
++/* target - IN, endPointId - IN, buffer - IN, length - IN, cookie - IN */
++
++#if 0
++A_STATUS
++HTCSkbSend(HTC_TARGET *target, HTC_ENDPOINT_ID endPointId,
++ struct sk_buff *skb, void *cookie);
++#endif
++
++void
++HTCStop(HTC_TARGET *target);
++/* target - IN */
++
++void
++HTCShutDown(HTC_TARGET *target);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _HTC_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/osapi.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/osapi.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,63 @@
++/*
++ * Copyright 2003-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions of the basic atheros data types.
++ * It is used to map the data types in atheros files to a platform specific
++ * type.
++ *
++ */
++
++#ifndef _OSAPI_H_
++#define _OSAPI_H_
++
++#ifdef __KERNEL__
++
++#ifdef __linux__
++#include "../include/osapi_linux.h"
++#endif
++
++/*
++ * OS specific network buffer acess routines
++ */
++void *a_netbuf_alloc(int size);
++void a_netbuf_free(void *bufPtr);
++void *a_netbuf_to_data(void *bufPtr);
++A_UINT32 a_netbuf_to_len(void *bufPtr);
++A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
++A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
++A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
++A_INT32 a_netbuf_headroom(void *bufPtr);
++A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
++A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
++A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
++#endif /* __KERNEL__ */
++
++#ifdef __GNUC__
++#define __ATTRIB_PACK __attribute__ ((packed))
++#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
++#define __ATTRIB_NORETURN __attribute__ ((noreturn))
++#ifndef INLINE
++#define INLINE __inline__
++#endif
++#else /* Not GCC */
++#define __ATTRIB_PACK
++#define __ATTRIB_PRINTF
++#define __ATTRIB_NORETURN
++#ifndef INLINE
++#define INLINE __inline
++#endif
++#endif /* End __GNUC__ */
++
++#endif /* _OSAPI_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/queue.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/queue.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,552 @@
++/*
++ * Copyright (c) 1991, 1993
++ * The Regents of the University of California. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 4. Neither the name of the University nor the names of its contributors
++ * may be used to endorse or promote products derived from this software
++ * without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ *
++ * @(#)queue.h 8.5 (Berkeley) 8/20/94
++ * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $
++ * $Id: //depot/sw/releases/etnaGPL1.1/host/include/queue.h#1 $
++ */
++
++#ifndef _SYS_QUEUE_H_
++#define _SYS_QUEUE_H_
++
++/*
++ * This file defines four types of data structures: singly-linked lists,
++ * singly-linked tail queues, lists and tail queues.
++ *
++ * A singly-linked list is headed by a single forward pointer. The elements
++ * are singly linked for minimum space and pointer manipulation overhead at
++ * the expense of O(n) removal for arbitrary elements. New elements can be
++ * added to the list after an existing element or at the head of the list.
++ * Elements being removed from the head of the list should use the explicit
++ * macro for this purpose for optimum efficiency. A singly-linked list may
++ * only be traversed in the forward direction. Singly-linked lists are ideal
++ * for applications with large datasets and few or no removals or for
++ * implementing a LIFO queue.
++ *
++ * A singly-linked tail queue is headed by a pair of pointers, one to the
++ * head of the list and the other to the tail of the list. The elements are
++ * singly linked for minimum space and pointer manipulation overhead at the
++ * expense of O(n) removal for arbitrary elements. New elements can be added
++ * to the list after an existing element, at the head of the list, or at the
++ * end of the list. Elements being removed from the head of the tail queue
++ * should use the explicit macro for this purpose for optimum efficiency.
++ * A singly-linked tail queue may only be traversed in the forward direction.
++ * Singly-linked tail queues are ideal for applications with large datasets
++ * and few or no removals or for implementing a FIFO queue.
++ *
++ * A list is headed by a single forward pointer (or an array of forward
++ * pointers for a hash table header). The elements are doubly linked
++ * so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before
++ * or after an existing element or at the head of the list. A list
++ * may only be traversed in the forward direction.
++ *
++ * A tail queue is headed by a pair of pointers, one to the head of the
++ * list and the other to the tail of the list. The elements are doubly
++ * linked so that an arbitrary element can be removed without a need to
++ * traverse the list. New elements can be added to the list before or
++ * after an existing element, at the head of the list, or at the end of
++ * the list. A tail queue may be traversed in either direction.
++ *
++ * For details on the use of these macros, see the queue(3) manual page.
++ *
++ *
++ * SLIST LIST STAILQ TAILQ
++ * _HEAD + + + +
++ * _HEAD_INITIALIZER + + + +
++ * _ENTRY + + + +
++ * _INIT + + + +
++ * _EMPTY + + + +
++ * _FIRST + + + +
++ * _NEXT + + + +
++ * _PREV - - - +
++ * _LAST - - + +
++ * _FOREACH + + + +
++ * _FOREACH_SAFE + + + +
++ * _FOREACH_REVERSE - - - +
++ * _FOREACH_REVERSE_SAFE - - - +
++ * _INSERT_HEAD + + + +
++ * _INSERT_BEFORE - + - +
++ * _INSERT_AFTER + + + +
++ * _INSERT_TAIL - - + +
++ * _CONCAT - - + +
++ * _REMOVE_HEAD + - + -
++ * _REMOVE + + + +
++ *
++ */
++#define QUEUE_MACRO_DEBUG 0
++#if QUEUE_MACRO_DEBUG
++/* Store the last 2 places the queue element or head was altered */
++struct qm_trace {
++ char * lastfile;
++ int lastline;
++ char * prevfile;
++ int prevline;
++};
++
++#define TRACEBUF struct qm_trace trace;
++#define TRASHIT(x) do {(x) = (void *)-1;} while (0)
++
++#define QMD_TRACE_HEAD(head) do { \
++ (head)->trace.prevline = (head)->trace.lastline; \
++ (head)->trace.prevfile = (head)->trace.lastfile; \
++ (head)->trace.lastline = __LINE__; \
++ (head)->trace.lastfile = __FILE__; \
++} while (0)
++
++#define QMD_TRACE_ELEM(elem) do { \
++ (elem)->trace.prevline = (elem)->trace.lastline; \
++ (elem)->trace.prevfile = (elem)->trace.lastfile; \
++ (elem)->trace.lastline = __LINE__; \
++ (elem)->trace.lastfile = __FILE__; \
++} while (0)
++
++#else
++#define QMD_TRACE_ELEM(elem)
++#define QMD_TRACE_HEAD(head)
++#define TRACEBUF
++#define TRASHIT(x)
++#endif /* QUEUE_MACRO_DEBUG */
++
++/*
++ * Singly-linked List declarations.
++ */
++#define SLIST_HEAD(name, type) \
++struct name { \
++ struct type *slh_first; /* first element */ \
++}
++
++#define SLIST_HEAD_INITIALIZER(head) \
++ { NULL }
++
++#define SLIST_ENTRY(type) \
++struct { \
++ struct type *sle_next; /* next element */ \
++}
++
++/*
++ * Singly-linked List functions.
++ */
++#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
++
++#define SLIST_FIRST(head) ((head)->slh_first)
++
++#define SLIST_FOREACH(var, head, field) \
++ for ((var) = SLIST_FIRST((head)); \
++ (var); \
++ (var) = SLIST_NEXT((var), field))
++
++#define SLIST_FOREACH_SAFE(var, head, field, tvar) \
++ for ((var) = SLIST_FIRST((head)); \
++ (var) && ((tvar) = SLIST_NEXT((var), field), 1); \
++ (var) = (tvar))
++
++#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \
++ for ((varp) = &SLIST_FIRST((head)); \
++ ((var) = *(varp)) != NULL; \
++ (varp) = &SLIST_NEXT((var), field))
++
++#define SLIST_INIT(head) do { \
++ SLIST_FIRST((head)) = NULL; \
++} while (0)
++
++#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
++ SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
++ SLIST_NEXT((slistelm), field) = (elm); \
++} while (0)
++
++#define SLIST_INSERT_HEAD(head, elm, field) do { \
++ SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
++ SLIST_FIRST((head)) = (elm); \
++} while (0)
++
++#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
++
++#define SLIST_REMOVE(head, elm, type, field) do { \
++ if (SLIST_FIRST((head)) == (elm)) { \
++ SLIST_REMOVE_HEAD((head), field); \
++ } \
++ else { \
++ struct type *curelm = SLIST_FIRST((head)); \
++ while (SLIST_NEXT(curelm, field) != (elm)) \
++ curelm = SLIST_NEXT(curelm, field); \
++ SLIST_NEXT(curelm, field) = \
++ SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
++ } \
++} while (0)
++
++#define SLIST_REMOVE_HEAD(head, field) do { \
++ SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
++} while (0)
++
++/*
++ * Singly-linked Tail queue declarations.
++ */
++#define STAILQ_HEAD(name, type) \
++struct name { \
++ struct type *stqh_first;/* first element */ \
++ struct type **stqh_last;/* addr of last next element */ \
++}
++
++#define STAILQ_HEAD_INITIALIZER(head) \
++ { NULL, &(head).stqh_first }
++
++#define STAILQ_ENTRY(type) \
++struct { \
++ struct type *stqe_next; /* next element */ \
++}
++
++/*
++ * Singly-linked Tail queue functions.
++ */
++#define STAILQ_CONCAT(head1, head2) do { \
++ if (!STAILQ_EMPTY((head2))) { \
++ *(head1)->stqh_last = (head2)->stqh_first; \
++ (head1)->stqh_last = (head2)->stqh_last; \
++ STAILQ_INIT((head2)); \
++ } \
++} while (0)
++
++#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
++
++#define STAILQ_FIRST(head) ((head)->stqh_first)
++
++#define STAILQ_FOREACH(var, head, field) \
++ for((var) = STAILQ_FIRST((head)); \
++ (var); \
++ (var) = STAILQ_NEXT((var), field))
++
++
++#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
++ for ((var) = STAILQ_FIRST((head)); \
++ (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
++ (var) = (tvar))
++
++#define STAILQ_INIT(head) do { \
++ STAILQ_FIRST((head)) = NULL; \
++ (head)->stqh_last = &STAILQ_FIRST((head)); \
++} while (0)
++
++#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
++ if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
++ (head)->stqh_last = &STAILQ_NEXT((elm), field); \
++ STAILQ_NEXT((tqelm), field) = (elm); \
++} while (0)
++
++#define STAILQ_INSERT_HEAD(head, elm, field) do { \
++ if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
++ (head)->stqh_last = &STAILQ_NEXT((elm), field); \
++ STAILQ_FIRST((head)) = (elm); \
++} while (0)
++
++#define STAILQ_INSERT_TAIL(head, elm, field) do { \
++ STAILQ_NEXT((elm), field) = NULL; \
++ *(head)->stqh_last = (elm); \
++ (head)->stqh_last = &STAILQ_NEXT((elm), field); \
++} while (0)
++
++#define STAILQ_LAST(head, type, field) \
++ (STAILQ_EMPTY((head)) ? \
++ NULL : \
++ ((struct type *) \
++ ((char *)((head)->stqh_last) - __offsetof(struct type, field))))
++
++#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
++
++#define STAILQ_REMOVE(head, elm, type, field) do { \
++ if (STAILQ_FIRST((head)) == (elm)) { \
++ STAILQ_REMOVE_HEAD((head), field); \
++ } \
++ else { \
++ struct type *curelm = STAILQ_FIRST((head)); \
++ while (STAILQ_NEXT(curelm, field) != (elm)) \
++ curelm = STAILQ_NEXT(curelm, field); \
++ if ((STAILQ_NEXT(curelm, field) = \
++ STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
++ (head)->stqh_last = &STAILQ_NEXT((curelm), field);\
++ } \
++} while (0)
++
++#define STAILQ_REMOVE_HEAD(head, field) do { \
++ if ((STAILQ_FIRST((head)) = \
++ STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
++ (head)->stqh_last = &STAILQ_FIRST((head)); \
++} while (0)
++
++#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \
++ if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \
++ (head)->stqh_last = &STAILQ_FIRST((head)); \
++} while (0)
++
++/*
++ * List declarations.
++ */
++#define ATH_LIST_HEAD(name, type) \
++struct name { \
++ struct type *lh_first; /* first element */ \
++}
++
++#define LIST_HEAD_INITIALIZER(head) \
++ { NULL }
++
++#define LIST_ENTRY(type) \
++struct { \
++ struct type *le_next; /* next element */ \
++ struct type **le_prev; /* address of previous next element */ \
++}
++
++/*
++ * List functions.
++ */
++
++#define LIST_EMPTY(head) ((head)->lh_first == NULL)
++
++#define LIST_FIRST(head) ((head)->lh_first)
++
++#define LIST_FOREACH(var, head, field) \
++ for ((var) = LIST_FIRST((head)); \
++ (var); \
++ (var) = LIST_NEXT((var), field))
++
++#define LIST_FOREACH_SAFE(var, head, field, tvar) \
++ for ((var) = LIST_FIRST((head)); \
++ (var) && ((tvar) = LIST_NEXT((var), field), 1); \
++ (var) = (tvar))
++
++#define LIST_INIT(head) do { \
++ LIST_FIRST((head)) = NULL; \
++} while (0)
++
++#define LIST_INSERT_AFTER(listelm, elm, field) do { \
++ if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
++ LIST_NEXT((listelm), field)->field.le_prev = \
++ &LIST_NEXT((elm), field); \
++ LIST_NEXT((listelm), field) = (elm); \
++ (elm)->field.le_prev = &LIST_NEXT((listelm), field); \
++} while (0)
++
++#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
++ (elm)->field.le_prev = (listelm)->field.le_prev; \
++ LIST_NEXT((elm), field) = (listelm); \
++ *(listelm)->field.le_prev = (elm); \
++ (listelm)->field.le_prev = &LIST_NEXT((elm), field); \
++} while (0)
++
++#define LIST_INSERT_HEAD(head, elm, field) do { \
++ if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
++ LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
++ LIST_FIRST((head)) = (elm); \
++ (elm)->field.le_prev = &LIST_FIRST((head)); \
++} while (0)
++
++#define LIST_NEXT(elm, field) ((elm)->field.le_next)
++
++#define LIST_REMOVE(elm, field) do { \
++ if (LIST_NEXT((elm), field) != NULL) \
++ LIST_NEXT((elm), field)->field.le_prev = \
++ (elm)->field.le_prev; \
++ *(elm)->field.le_prev = LIST_NEXT((elm), field); \
++} while (0)
++
++/*
++ * Tail queue declarations.
++ */
++#define TAILQ_HEAD(name, type) \
++struct name { \
++ struct type *tqh_first; /* first element */ \
++ struct type **tqh_last; /* addr of last next element */ \
++ TRACEBUF \
++}
++
++#define TAILQ_HEAD_INITIALIZER(head) \
++ { NULL, &(head).tqh_first }
++
++#define TAILQ_ENTRY(type) \
++struct { \
++ struct type *tqe_next; /* next element */ \
++ struct type **tqe_prev; /* address of previous next element */ \
++ TRACEBUF \
++}
++
++/*
++ * Tail queue functions.
++ */
++#define TAILQ_CONCAT(head1, head2, field) do { \
++ if (!TAILQ_EMPTY(head2)) { \
++ *(head1)->tqh_last = (head2)->tqh_first; \
++ (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
++ (head1)->tqh_last = (head2)->tqh_last; \
++ TAILQ_INIT((head2)); \
++ QMD_TRACE_HEAD(head); \
++ QMD_TRACE_HEAD(head2); \
++ } \
++} while (0)
++
++#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
++
++#define TAILQ_FIRST(head) ((head)->tqh_first)
++
++#define TAILQ_FOREACH(var, head, field) \
++ for ((var) = TAILQ_FIRST((head)); \
++ (var); \
++ (var) = TAILQ_NEXT((var), field))
++
++#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \
++ for ((var) = TAILQ_FIRST((head)); \
++ (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
++ (var) = (tvar))
++
++#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
++ for ((var) = TAILQ_LAST((head), headname); \
++ (var); \
++ (var) = TAILQ_PREV((var), headname, field))
++
++#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \
++ for ((var) = TAILQ_LAST((head), headname); \
++ (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
++ (var) = (tvar))
++
++#define TAILQ_INIT(head) do { \
++ TAILQ_FIRST((head)) = NULL; \
++ (head)->tqh_last = &TAILQ_FIRST((head)); \
++ QMD_TRACE_HEAD(head); \
++} while (0)
++
++#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
++ if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
++ TAILQ_NEXT((elm), field)->field.tqe_prev = \
++ &TAILQ_NEXT((elm), field); \
++ else { \
++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \
++ QMD_TRACE_HEAD(head); \
++ } \
++ TAILQ_NEXT((listelm), field) = (elm); \
++ (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
++ QMD_TRACE_ELEM(&(elm)->field); \
++ QMD_TRACE_ELEM(&listelm->field); \
++} while (0)
++
++#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
++ TAILQ_NEXT((elm), field) = (listelm); \
++ *(listelm)->field.tqe_prev = (elm); \
++ (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
++ QMD_TRACE_ELEM(&(elm)->field); \
++ QMD_TRACE_ELEM(&listelm->field); \
++} while (0)
++
++#define TAILQ_INSERT_HEAD(head, elm, field) do { \
++ if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
++ TAILQ_FIRST((head))->field.tqe_prev = \
++ &TAILQ_NEXT((elm), field); \
++ else \
++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \
++ TAILQ_FIRST((head)) = (elm); \
++ (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
++ QMD_TRACE_HEAD(head); \
++ QMD_TRACE_ELEM(&(elm)->field); \
++} while (0)
++
++#define TAILQ_INSERT_TAIL(head, elm, field) do { \
++ TAILQ_NEXT((elm), field) = NULL; \
++ (elm)->field.tqe_prev = (head)->tqh_last; \
++ *(head)->tqh_last = (elm); \
++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \
++ QMD_TRACE_HEAD(head); \
++ QMD_TRACE_ELEM(&(elm)->field); \
++} while (0)
++
++#define TAILQ_LAST(head, headname) \
++ (*(((struct headname *)((head)->tqh_last))->tqh_last))
++
++#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
++
++#define TAILQ_PREV(elm, headname, field) \
++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
++
++#define TAILQ_REMOVE(head, elm, field) do { \
++ if ((TAILQ_NEXT((elm), field)) != NULL) \
++ TAILQ_NEXT((elm), field)->field.tqe_prev = \
++ (elm)->field.tqe_prev; \
++ else { \
++ (head)->tqh_last = (elm)->field.tqe_prev; \
++ QMD_TRACE_HEAD(head); \
++ } \
++ *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
++ TRASHIT((elm)->field.tqe_next); \
++ TRASHIT((elm)->field.tqe_prev); \
++ QMD_TRACE_ELEM(&(elm)->field); \
++} while (0)
++
++
++#ifdef _KERNEL
++
++/*
++ * XXX insque() and remque() are an old way of handling certain queues.
++ * They bogusly assumes that all queue heads look alike.
++ */
++
++struct quehead {
++ struct quehead *qh_link;
++ struct quehead *qh_rlink;
++};
++
++#if defined(__GNUC__) || defined(__INTEL_COMPILER)
++
++static __inline void
++insque(void *a, void *b)
++{
++ struct quehead *element = (struct quehead *)a,
++ *head = (struct quehead *)b;
++
++ element->qh_link = head->qh_link;
++ element->qh_rlink = head;
++ head->qh_link = element;
++ element->qh_link->qh_rlink = element;
++}
++
++static __inline void
++remque(void *a)
++{
++ struct quehead *element = (struct quehead *)a;
++
++ element->qh_link->qh_rlink = element->qh_rlink;
++ element->qh_rlink->qh_link = element->qh_link;
++ element->qh_rlink = 0;
++}
++
++#else /* !(__GNUC__ || __INTEL_COMPILER) */
++
++void insque(void *a, void *b);
++void remque(void *a);
++
++#endif /* __GNUC__ || __INTEL_COMPILER */
++
++#endif /* _KERNEL */
++
++#endif /* !_SYS_QUEUE_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wlan_api.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wlan_api.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the API for the host wlan module
++ *
++ *
++ */
++
++#ifndef _HOST_WLAN_API_H_
++#define _HOST_WLAN_API_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++struct ieee80211_node_table;
++struct ieee80211_frame;
++
++struct ieee80211_common_ie {
++ A_UINT16 ie_chan;
++ A_UINT8 *ie_tstamp;
++ A_UINT8 *ie_ssid;
++ A_UINT8 *ie_rates;
++ A_UINT8 *ie_xrates;
++ A_UINT8 *ie_country;
++ A_UINT8 *ie_wpa;
++ A_UINT8 *ie_wmm;
++ A_UINT8 *ie_ath;
++ A_UINT16 ie_capInfo;
++ A_UINT16 ie_beaconInt;
++ A_UINT8 *ie_tim;
++ A_UINT8 *ie_chswitch;
++ A_UINT8 ie_erp;
++};
++
++typedef struct bss {
++ A_UINT8 ni_macaddr[6];
++ A_INT8 ni_rssi;
++ struct bss *ni_list_next;
++ struct bss *ni_list_prev;
++ struct bss *ni_hash_next;
++ struct bss *ni_hash_prev;
++ struct ieee80211_common_ie ni_cie;
++ A_UINT8 *ni_buf;
++ struct ieee80211_node_table *ni_table;
++ A_UINT32 ni_refcnt;
++ int ni_scangen;
++ A_UINT32 ni_tstamp;
++} bss_t;
++
++typedef void wlan_node_iter_func(void *arg, bss_t *);
++
++bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
++void wlan_node_free(bss_t *ni);
++void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
++ const A_UINT8 *macaddr);
++bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
++void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
++void wlan_free_allnodes(struct ieee80211_node_table *nt);
++void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
++ void *arg);
++
++void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
++void wlan_node_table_reset(struct ieee80211_node_table *nt);
++void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
++
++A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
++ struct ieee80211_common_ie *cie);
++
++A_UINT16 wlan_ieee2freq(int chan);
++A_UINT32 wlan_freq2ieee(A_UINT16 freq);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _HOST_WLAN_API_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi_api.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi_api.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,173 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the definitions for the Wireless Module Interface (WMI).
++ *
++ *
++ */
++
++#ifndef _WMI_API_H_
++#define _WMI_API_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define WMI_HIGH_PRIORITY_MBOX ENDPOINT4
++#define WMI_LOW_PRIORITY_MBOX ENDPOINT3
++#define WMI_BEST_EFFORT_MBOX ENDPOINT2
++#define WMI_CONTROL_MBOX ENDPOINT1
++#define WMI_MBOX_COUNT 4
++#define WMI_MAX_NUM_PRI_STREAMS 2
++#define WMI_NOT_MAPPED (-1)
++#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
++
++typedef enum {
++ CCX_V4_COMPLIANCE = 0x1,
++}TSPEC_PARAM_COMPLIANCE;
++
++struct wmi_t;
++
++void *wmi_init(void *devt);
++
++void wmi_qos_state_init(struct wmi_t *wmip);
++void wmi_shutdown(struct wmi_t *wmip);
++A_INT8 wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 dir, A_UINT8 trafficClass);
++A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
++A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType);
++A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf);
++A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
++A_STATUS wmi_syncpoint(struct wmi_t *wmip);
++A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
++HTC_ENDPOINT_ID wmi_get_endpoint(struct wmi_t *wmip, A_UINT8 trafficClass);
++A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir);
++
++A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
++void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
++
++typedef enum {
++ NO_SYNC_WMIFLAG = 0,
++ SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */
++ SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */
++ SYNC_BOTH_WMIFLAG,
++ END_WMIFLAG /* end marker */
++} WMI_SYNC_FLAG;
++
++A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
++ WMI_SYNC_FLAG flag);
++A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
++ NETWORK_TYPE netType,
++ DOT11_AUTH_MODE dot11AuthMode,
++ AUTH_MODE authMode,
++ CRYPTO_TYPE pairwiseCrypto,
++ A_UINT8 pairwiseCryptoLen,
++ CRYPTO_TYPE groupCrypto,
++ A_UINT8 groupCryptoLen,
++ int ssidLength,
++ A_UCHAR *ssid,
++ A_UINT8 *bssid,
++ A_UINT16 channel);
++A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
++ A_UINT8 *bssid,
++ A_UINT16 channel);
++A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
++A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
++A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType);
++A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
++ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
++ A_UINT16 act_chdw_msec, A_UINT16 pas_chdw_msec,
++ A_UINT8 shScanRatio);
++A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter);
++A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
++ A_UINT8 ssidLength, A_UCHAR *ssid);
++A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
++A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
++A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
++ A_UINT8 ieLen, A_UINT8 *ieInfo);
++A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
++A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
++ A_UINT16 atim_windows, A_UINT16 timeout_value);
++A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
++ A_UINT16 psPollNum, A_UINT16 dtimPolicy);
++A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
++A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
++A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
++A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 txQueueNumber,
++ A_UINT8 rxQueueNumber, A_UINT8 trafficDirection);
++A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate);
++A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
++A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
++A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
++A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
++A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, WMI_PHY_MODE mode,
++ A_INT8 numChan, A_UINT16 *channelList);
++A_STATUS wmi_set_link_threshold_params(struct wmi_t *wmip,
++ A_UINT8 highThreshold_upperVal,
++ A_UINT8 highThreshold_lowerVal,
++ A_UINT8 lowThreshold_upperVal,
++ A_UINT8 lowThreshold_lowerVal,
++ A_UINT32 pollTime);
++A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
++
++A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
++A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
++ CRYPTO_TYPE keyType, A_UINT8 keyUsage,
++ A_UINT8 keyLength,A_UINT8 *keyRSC,
++ A_UINT8 *keyMaterial, WMI_SYNC_FLAG sync_flag);
++A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
++A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
++A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
++A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
++A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
++A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
++A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
++A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
++A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
++ A_BOOL set);
++A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop,
++ A_UINT8 eCWmin, A_UINT8 eCWmax,
++ A_UINT8 aifsn);
++A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
++ A_UINT8 trafficClass, A_UINT8 maxRetries);
++
++void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
++
++A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
++A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
++A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
++ A_UINT8 size);
++A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
++ WMI_POWERSAVE_TIMERS_CMD *pCmd,
++ A_UINT8 size);
++
++A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
++A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
++ A_UINT8 frmType,
++ A_UINT8 *dstMacAddr,
++ A_UINT8 *bssid,
++ A_UINT16 optIEDataLen,
++ A_UINT8 *optIEData);
++
++A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
++A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
++A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
++A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority);
++A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
++A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _WMI_API_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_node.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_node.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,285 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright (c) 2004-2006 Atheros Communications
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++/*
++ * IEEE 802.11 node handling support.
++ */
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/ieee80211.h"
++#include "../include/wlan_api.h"
++#include "../include/ieee80211_node.h"
++#include "../include/htc.h"
++#include "../include/wmi.h"
++#include "../include/wmi_api.h"
++
++#ifdef DEBUG
++static int wlan_node_debug= 1;
++#define ND_PRINTF if (wlan_node_debug) A_PRINTF
++#else
++#define ND_PRINTF(args...)
++#endif
++
++static void wlan_node_timeout(unsigned long arg);
++static bss_t * _ieee80211_find_node(struct ieee80211_node_table *nt,
++ const A_UINT8 *macaddr);
++
++bss_t *
++wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
++{
++ bss_t *ni;
++
++ ni = A_MALLOC_NOWAIT(sizeof(bss_t));
++
++ if (ni != NULL) {
++ ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
++ if (ni->ni_buf == NULL) {
++ A_FREE(ni);
++ ni = NULL;
++ }
++ }
++
++ /* Make sure our lists are clean */
++ ni->ni_list_next = NULL;
++ ni->ni_list_prev = NULL;
++ ni->ni_hash_next = NULL;
++ ni->ni_hash_prev = NULL;
++
++ return ni;
++}
++
++void
++wlan_node_free(bss_t *ni)
++{
++ if (ni->ni_buf != NULL) {
++ A_FREE(ni->ni_buf);
++ }
++
++ A_FREE(ni);
++}
++
++void
++wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
++ const A_UINT8 *macaddr)
++{
++ int hash;
++
++ A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
++ hash = IEEE80211_NODE_HASH(macaddr);
++ ieee80211_node_initref(ni); /* mark referenced */
++
++ ni->ni_tstamp = jiffies + (WLAN_NODE_INACT_TIMEOUT_MSEC / 1000) * HZ;
++ IEEE80211_NODE_LOCK_BH(nt);
++
++ /* Insert at the end of the node list */
++ ni->ni_list_next = NULL;
++ ni->ni_list_prev = nt->nt_node_last;
++ if(nt->nt_node_last != NULL)
++ {
++ nt->nt_node_last->ni_list_next = ni;
++ }
++ nt->nt_node_last = ni;
++ if(nt->nt_node_first == NULL)
++ {
++ nt->nt_node_first = ni;
++ }
++
++ /* Insert into the hash list i.e. the bucket */
++ if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
++ {
++ nt->nt_hash[hash]->ni_hash_prev = ni;
++ }
++ ni->ni_hash_prev = NULL;
++ nt->nt_hash[hash] = ni;
++
++ IEEE80211_NODE_UNLOCK_BH(nt);
++}
++
++static bss_t *
++_ieee80211_find_node(struct ieee80211_node_table *nt,
++ const A_UINT8 *macaddr)
++{
++ bss_t *ni;
++ int hash;
++
++ IEEE80211_NODE_LOCK_ASSERT(nt);
++
++ hash = IEEE80211_NODE_HASH(macaddr);
++ for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
++ if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
++ ieee80211_node_incref(ni); /* mark referenced */
++ return ni;
++ }
++ }
++ return NULL;
++}
++
++bss_t *
++wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
++{
++ bss_t *ni;
++
++ IEEE80211_NODE_LOCK(nt);
++ ni = _ieee80211_find_node(nt, macaddr);
++ IEEE80211_NODE_UNLOCK(nt);
++ return ni;
++}
++
++/*
++ * Reclaim a node. If this is the last reference count then
++ * do the normal free work. Otherwise remove it from the node
++ * table and mark it gone by clearing the back-reference.
++ */
++void
++wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
++{
++ IEEE80211_NODE_LOCK(nt);
++
++ if(ni->ni_list_prev == NULL)
++ {
++ /* First in list so fix the list head */
++ nt->nt_node_first = ni->ni_list_next;
++ }
++ else
++ {
++ ni->ni_list_prev->ni_list_next = ni->ni_list_next;
++ }
++
++ if(ni->ni_list_next == NULL)
++ {
++ /* Last in list so fix list tail */
++ nt->nt_node_last = ni->ni_list_prev;
++ }
++ else
++ {
++ ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
++ }
++
++ if(ni->ni_hash_prev == NULL)
++ {
++ /* First in list so fix the list head */
++ int hash;
++ hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
++ nt->nt_hash[hash] = ni->ni_hash_next;
++ }
++ else
++ {
++ ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
++ }
++
++ if(ni->ni_hash_next != NULL)
++ {
++ ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
++ }
++ wlan_node_free(ni);
++
++ IEEE80211_NODE_UNLOCK(nt);
++}
++
++static void
++wlan_node_dec_free(bss_t *ni)
++{
++ if (ieee80211_node_dectestref(ni)) {
++ wlan_node_free(ni);
++ }
++}
++
++void
++wlan_free_allnodes(struct ieee80211_node_table *nt)
++{
++ bss_t *ni;
++
++ while ((ni = nt->nt_node_first) != NULL) {
++ wlan_node_reclaim(nt, ni);
++ }
++}
++
++void
++wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
++ void *arg)
++{
++ bss_t *ni;
++ A_UINT32 gen;
++
++ gen = nt->nt_scangen++;
++ IEEE80211_NODE_LOCK(nt);
++ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
++ if (ni->ni_scangen != gen) {
++ ni->ni_scangen = gen;
++ (void) ieee80211_node_incref(ni);
++ (*f)(arg, ni);
++ wlan_node_dec_free(ni);
++ }
++ }
++ IEEE80211_NODE_UNLOCK(nt);
++}
++
++/*
++ * Node table support.
++ */
++void
++wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
++{
++ int i;
++ ND_PRINTF("node table = 0x%x\n", (A_UINT32)nt);
++ IEEE80211_NODE_LOCK_INIT(nt);
++
++ nt->nt_node_first = nt->nt_node_last = NULL;
++ for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
++ {
++ nt->nt_hash[i] = NULL;
++ }
++ A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
++ A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
++ nt->nt_wmip = wmip;
++}
++
++static void
++wlan_node_timeout(unsigned long arg)
++{
++ struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
++ bss_t *bss, *nextBss;
++ A_UINT8 myBssid[IEEE80211_ADDR_LEN];
++
++ wmi_get_current_bssid(nt->nt_wmip, myBssid);
++
++ bss = nt->nt_node_first;
++ while (bss != NULL) {
++ nextBss = bss->ni_list_next;
++ if ((A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) &&
++ (bss->ni_tstamp <= jiffies))
++ {
++ /*
++ * free up all but the current bss - if set
++ */
++ wlan_node_reclaim(nt, bss);
++ }
++ bss = nextBss;
++ }
++
++ A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
++}
++
++void
++wlan_node_table_cleanup(struct ieee80211_node_table *nt)
++{
++ A_UNTIMEOUT(&nt->nt_inact_timer);
++ wlan_free_allnodes(nt);
++ IEEE80211_NODE_LOCK_DESTROY(nt);
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_utils.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_utils.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This module implements frequently used wlan utilies
++ *
++ */
++
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++
++/*
++ * converts ieee channel number to frequency
++ */
++A_UINT16
++wlan_ieee2freq(int chan)
++{
++ if (chan == 14) {
++ return 2484;
++ }
++ if (chan < 14) { /* 0-13 */
++ return (2407 + (chan*5));
++ }
++ if (chan < 27) { /* 15-26 */
++ return (2512 + ((chan-15)*20));
++ }
++ return (5000 + (chan*5));
++}
++
++/*
++ * Converts MHz frequency to IEEE channel number.
++ */
++A_UINT32
++wlan_freq2ieee(A_UINT16 freq)
++{
++ if (freq == 2484)
++ return 14;
++ if (freq < 2484)
++ return (freq - 2407) / 5;
++ if (freq < 5000)
++ return 15 + ((freq - 2512) / 20);
++ return (freq - 5000) / 5;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/wmi/wmi.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/wmi/wmi.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,2871 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This module implements the hardware independent layer of the
++ * Wireless Module Interface (WMI) protocol.
++ *
++ */
++
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/htc.h"
++#include "../include/wmi.h"
++#include "../include/ieee80211.h"
++#include "../include/ieee80211_node.h"
++#include "../include/wlan_api.h"
++#include "../include/wmi_api.h"
++#include "../include/dset_api.h"
++#include "../include/gpio_api.h"
++#include "../include/wmi_host.h"
++#include "../include/athdrv.h"
++#include "../include/ar6000_api.h"
++
++#ifdef DEBUG
++int wmi_debug = 0;
++#define WMI_DEBUG_PRINTF(args...) if (wmi_debug) printk(args);
++#define WMI_DEBUG_PRINTF2(args...) if (wmi_debug > 1) printk(args);
++#else
++#define WMI_DEBUG_PRINTF(args...)
++#define WMI_DEBUG_PRINTF2(args...)
++#endif
++
++static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++
++static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_sync_point(struct wmi_t *wmip);
++
++static A_STATUS wmi_create_pstream_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_delete_pstream_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++#if CONFIG_HOST_DSET_SUPPORT
++static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
++ int len);
++#if CONFIG_HOST_GPIO_SUPPORT
++static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++static const A_INT32 wmi_rateTable[] = {
++ 1000,
++ 2000,
++ 5500,
++ 11000,
++ 6000,
++ 9000,
++ 12000,
++ 18000,
++ 24000,
++ 36000,
++ 48000,
++ 54000,
++ 0};
++
++#define MODE_A_SUPPORT_RATE_START 4
++#define MODE_A_SUPPORT_RATE_STOP 11
++
++#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START
++#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP
++
++#define MODE_B_SUPPORT_RATE_START 0
++#define MODE_B_SUPPORT_RATE_STOP 3
++
++
++/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
++const A_UINT8 up_to_ac[]= {
++ WMM_AC_BE,
++ WMM_AC_BK,
++ WMM_AC_BK,
++ WMM_AC_BE,
++ WMM_AC_VI,
++ WMM_AC_VI,
++ WMM_AC_VO,
++ WMM_AC_VO,
++ };
++void *
++wmi_init(void *devt)
++{
++ struct wmi_t *wmip;
++
++ A_UINT8 i;
++ wmip = A_MALLOC(sizeof(struct wmi_t));
++ if (wmip == NULL) {
++ return (NULL);
++ }
++ A_MEMZERO(wmip, sizeof(*wmip));
++
++ wmip->wmi_devt = devt;
++ wlan_node_table_init(wmip, &wmip->wmi_scan_table);
++ for (i = UPLINK_TRAFFIC; i < BIDIR_TRAFFIC; i++) {
++ wmip->wmi_pstreamCmdInProgress[i][WMM_AC_BE] = FALSE;
++ wmip->wmi_pstreamCmdInProgress[i][WMM_AC_BK] = FALSE;
++ wmip->wmi_pstreamCmdInProgress[i][WMM_AC_VI] = FALSE;
++ wmip->wmi_pstreamCmdInProgress[i][WMM_AC_VO] = FALSE;
++ }
++ wmip->wmi_cpstreamCmdInProgress = FALSE;
++ wmi_qos_state_init(wmip);
++ wmip->wmi_powerMode = REC_POWER;
++ wmip->wmi_phyMode = WMI_11G_MODE;
++
++ return (wmip);
++}
++
++void
++wmi_qos_state_init(struct wmi_t *wmip)
++{
++ A_UINT8 i;
++
++ if (wmip == NULL) {
++ return;
++ }
++
++ /* Initialize QoS States */
++ wmip->wmi_numQoSStream = 0;
++
++ for (i = 0; i < WMI_MAX_NUM_PRI_STREAMS; i++) {
++ wmip->wmi_priority[i].inUse = 0;
++ wmip->wmi_priority[i].mbox = WMI_BEST_EFFORT_MBOX;
++ }
++
++ for (i = 0; i < WMM_NUM_AC; i++) {
++ wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][i] = WMI_NOT_MAPPED;
++ wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][i] = WMI_NOT_MAPPED;
++ }
++ wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][WMM_AC_BE] = WMI_BEST_EFFORT_MBOX;
++ wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][WMM_AC_BE] = WMI_BEST_EFFORT_MBOX;
++
++ for (i = 0; i < WMI_MBOX_COUNT; i++) {
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][i].trafficClass = WMM_AC_BE;
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][i].priorityNum = WMI_NOT_MAPPED;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][i].trafficClass = WMM_AC_BE;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][i].priorityNum = WMI_NOT_MAPPED;
++ }
++
++ wmip->wmi_olderPriRxMbox = WMI_HIGH_PRIORITY_MBOX;
++ wmip->wmi_newerPriRxMbox = WMI_LOW_PRIORITY_MBOX;
++ ar6000_set_numdataendpts(wmip->wmi_devt, 1);
++}
++
++void
++wmi_shutdown(struct wmi_t *wmip)
++{
++ if (wmip != NULL) {
++ wlan_node_table_cleanup(&wmip->wmi_scan_table);
++ A_FREE(wmip);
++ }
++}
++
++/*
++ * performs DIX to 802.3 encapsulation for transmit packets.
++ * uses passed in buffer. Returns buffer or NULL if failed.
++ * Assumes the entire DIX header is contigous and that there is
++ * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
++ */
++A_STATUS
++wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
++{
++ A_UINT8 *datap;
++ A_UINT16 typeorlen;
++ ATH_MAC_HDR macHdr;
++ ATH_LLC_SNAP_HDR *llcHdr;
++
++ A_ASSERT(osbuf != NULL);
++
++ if (a_netbuf_headroom(osbuf) <
++ (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
++ {
++ return A_NO_MEMORY;
++ }
++
++ datap = a_netbuf_to_data(osbuf);
++
++ typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
++
++ if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
++ /*
++ * packet is already in 802.3 format - return success
++ */
++ WMI_DEBUG_PRINTF("packet already 802.3\n");
++ return (A_OK);
++ }
++
++ /*
++ * Save mac fields and length to be inserted later
++ */
++ A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
++ A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
++ macHdr.typeOrLen = A_CPU2BE16(a_netbuf_to_len(osbuf) - sizeof(ATH_MAC_HDR) +
++ sizeof(ATH_LLC_SNAP_HDR));
++
++ /*
++ * Make room for LLC+SNAP headers
++ */
++ if (a_netbuf_push(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ datap = a_netbuf_to_data(osbuf);
++
++ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
++
++ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
++ llcHdr->dsap = 0xAA;
++ llcHdr->ssap = 0xAA;
++ llcHdr->cntl = 0x03;
++ llcHdr->orgCode[0] = 0x0;
++ llcHdr->orgCode[1] = 0x0;
++ llcHdr->orgCode[2] = 0x0;
++ llcHdr->etherType = typeorlen;
++
++ return (A_OK);
++}
++
++/*
++ * Adds a WMI data header
++ * Assumes there is enough room in the buffer to add header.
++ */
++A_STATUS
++wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType)
++{
++ WMI_DATA_HDR *dtHdr;
++
++ A_ASSERT(osbuf != NULL);
++
++ if (a_netbuf_push(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ dtHdr = (WMI_DATA_HDR *)a_netbuf_to_data(osbuf);
++ dtHdr->info = msgType;
++ dtHdr->rssi = 0;
++
++ return (A_OK);
++}
++A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir)
++{
++ A_UINT8 *datap;
++ A_UINT8 trafficClass, userPriority = 0;
++ ATH_LLC_SNAP_HDR *llcHdr;
++ A_UINT16 ipType = IP_ETHERTYPE;
++ WMI_DATA_HDR *dtHdr;
++ WMI_CREATE_PSTREAM_CMD cmd;
++
++ A_ASSERT(osbuf != NULL);
++ A_ASSERT(dir == DNLINK_TRAFFIC || dir == UPLINK_TRAFFIC);
++ datap = a_netbuf_to_data(osbuf);
++ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) +
++ sizeof(ATH_MAC_HDR));
++
++ if (llcHdr->etherType == htons(ipType)) {
++ /* Extract the endpoint info from the TOS field in the IP header */
++ userPriority = ar6000_iptos_to_userPriority(((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR));
++ trafficClass = convert_userPriority_to_trafficClass(userPriority);
++ } else {
++ trafficClass = WMM_AC_BE;
++ }
++
++
++ dtHdr = (WMI_DATA_HDR *)datap;
++ if(dir==UPLINK_TRAFFIC)
++ dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */
++
++ /* Implicitly determine whether a create_pstream_cmd is needed for this trafficClass */
++ if (!((trafficClass == WMM_AC_BE) || (wmip->wmi_trafficClassMap[dir][trafficClass] != WMI_NOT_MAPPED))) {
++ A_UINT8 reqMbox;
++ /*
++ * If the data pkt is tagged with a priority that doesn't have a MBOX created,
++ * we must first call create_pstream_cmd
++ * Originally, assume traffic goes to BE MBox,
++ * until the driver receives the reply from the create_pstream cmd
++ */
++ wmip->wmi_trafficClassMap[dir][trafficClass] = WMI_BEST_EFFORT_MBOX;
++ if (dir == DNLINK_TRAFFIC) {
++ /* determine which mailbox to use */
++ reqMbox = wmip->wmi_olderPriRxMbox;
++ } else {
++ reqMbox = WMI_BEST_EFFORT_MBOX;
++ }
++
++ A_MEMZERO(&cmd, sizeof(cmd));
++ cmd.trafficClass = trafficClass;
++ cmd.rxQueueNum = reqMbox;
++ cmd.userPriority = userPriority;
++ cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
++
++ if (wmi_create_pstream_cmd(wmip, &cmd) != A_OK) {
++ wmip->wmi_trafficClassMap[dir][trafficClass] = WMI_NOT_MAPPED;
++ trafficClass = WMM_AC_BE;
++ }
++
++ }
++ return trafficClass;
++}
++
++HTC_ENDPOINT_ID
++wmi_get_endpoint(struct wmi_t *wmip, A_UINT8 trafficClass)
++{
++ WMI_DEBUG_PRINTF2("1 pkt of traffic class(%d) to mbox(%d)\n",
++ trafficClass, wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][trafficClass]);
++ return wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][trafficClass];
++}
++
++/*
++ * performs 802.3 to DIX encapsulation for received packets.
++ * Assumes the entire 802.3 header is contigous.
++ */
++A_STATUS
++wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf)
++{
++ A_UINT8 *datap;
++ ATH_MAC_HDR macHdr;
++ ATH_LLC_SNAP_HDR *llcHdr;
++
++ A_ASSERT(osbuf != NULL);
++ datap = a_netbuf_to_data(osbuf);
++
++ A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
++ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
++ macHdr.typeOrLen = llcHdr->etherType;
++
++ if (a_netbuf_pull(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ datap = a_netbuf_to_data(osbuf);
++
++ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
++
++ return (A_OK);
++}
++
++/*
++ * Removes a WMI data header
++ */
++A_STATUS
++wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
++{
++ A_ASSERT(osbuf != NULL);
++
++ return (a_netbuf_pull(osbuf, sizeof(WMI_DATA_HDR)));
++}
++
++void
++wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
++{
++ wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
++}
++
++/*
++ * WMI Extended Event received from Target.
++ */
++A_STATUS
++wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
++{
++ WMIX_CMD_HDR *cmd;
++ A_UINT16 id;
++ A_UINT8 *datap;
++ A_UINT32 len;
++ A_STATUS status = A_OK;
++
++ if (a_netbuf_to_len(osbuf) < sizeof(WMIX_CMD_HDR)) {
++ WMI_DEBUG_PRINTF("wmi extended event rx: bad packet\n");
++ wmip->wmi_stats.cmd_len_err++;
++ a_netbuf_free(osbuf);
++ return A_ERROR;
++ }
++
++ cmd = (WMIX_CMD_HDR *)a_netbuf_to_data(osbuf);
++ id = cmd->commandId;
++
++ if (a_netbuf_pull(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
++ WMI_DEBUG_PRINTF("wmi extended event rx: bad packet\n");
++ wmip->wmi_stats.cmd_len_err++;
++ a_netbuf_free(osbuf);
++ return A_ERROR;
++ }
++
++ datap = a_netbuf_to_data(osbuf);
++ len = a_netbuf_to_len(osbuf);
++
++ switch (id) {
++ case (WMIX_DSETOPENREQ_EVENTID):
++ status = wmi_dset_open_req_rx(wmip, datap, len);
++ break;
++#if CONFIG_HOST_DSET_SUPPORT
++ case (WMIX_DSETCLOSE_EVENTID):
++ status = wmi_dset_close_rx(wmip, datap, len);
++ break;
++ case (WMIX_DSETDATAREQ_EVENTID):
++ status = wmi_dset_data_req_rx(wmip, datap, len);
++ break;
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++#if CONFIG_HOST_GPIO_SUPPORT
++ case (WMIX_GPIO_INTR_EVENTID):
++ wmi_gpio_intr_rx(wmip, datap, len);
++ break;
++ case (WMIX_GPIO_DATA_EVENTID):
++ wmi_gpio_data_rx(wmip, datap, len);
++ break;
++ case (WMIX_GPIO_ACK_EVENTID):
++ wmi_gpio_ack_rx(wmip, datap, len);
++ break;
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++ default:
++ WMI_DEBUG_PRINTF("Host received unknown extended reply/event with id 0x%x\n",
++ id);
++ wmip->wmi_stats.cmd_id_err++;
++ status = A_ERROR;
++ break;
++ }
++
++ return status;
++}
++
++/*
++ * Control Path
++ */
++A_STATUS
++wmi_control_rx(struct wmi_t *wmip, void *osbuf)
++{
++ WMI_CMD_HDR *cmd;
++ A_UINT16 id;
++ A_UINT8 *datap;
++ A_UINT32 len;
++ A_STATUS status = A_OK;
++
++ A_ASSERT(osbuf != NULL);
++ if (a_netbuf_to_len(osbuf) < sizeof(WMI_CMD_HDR)) {
++ WMI_DEBUG_PRINTF("wmi event rx: bad packet\n");
++ wmip->wmi_stats.cmd_len_err++;
++ a_netbuf_free(osbuf);
++ return A_ERROR;
++ }
++
++ cmd = (WMI_CMD_HDR *)a_netbuf_to_data(osbuf);
++ id = cmd->commandId;
++
++ if (a_netbuf_pull(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
++ WMI_DEBUG_PRINTF("wmi event rx: bad packet\n");
++ wmip->wmi_stats.cmd_len_err++;
++ a_netbuf_free(osbuf);
++ return A_ERROR;
++ }
++
++ datap = a_netbuf_to_data(osbuf);
++ len = a_netbuf_to_len(osbuf);
++
++ switch (id) {
++ case (WMI_CREATE_PSTREAM_CMDID):
++ status = wmi_create_pstream_reply_rx(wmip, datap, len);
++ break;
++ case (WMI_DELETE_PSTREAM_CMDID):
++ status = wmi_delete_pstream_reply_rx(wmip, datap, len);
++ break;
++ case (WMI_GET_BITRATE_CMDID):
++ status = wmi_bitrate_reply_rx(wmip, datap, len);
++ break;
++ case (WMI_GET_CHANNEL_LIST_CMDID):
++ status = wmi_channelList_reply_rx(wmip, datap, len);
++ break;
++ case (WMI_GET_TX_PWR_CMDID):
++ status = wmi_txPwr_reply_rx(wmip, datap, len);
++ break;
++ case (WMI_READY_EVENTID):
++ status = wmi_ready_event_rx(wmip, datap, len);
++ break;
++ case (WMI_CONNECT_EVENTID):
++ status = wmi_connect_event_rx(wmip, datap, len);
++ break;
++ case (WMI_DISCONNECT_EVENTID):
++ status = wmi_disconnect_event_rx(wmip, datap, len);
++ break;
++ case (WMI_TKIP_MICERR_EVENTID):
++ status = wmi_tkip_micerr_event_rx(wmip, datap, len);
++ break;
++ case (WMI_BSSINFO_EVENTID):
++ status = wmi_bssInfo_event_rx(wmip, datap, len);
++ break;
++ case (WMI_REGDOMAIN_EVENTID):
++ status = wmi_regDomain_event_rx(wmip, datap, len);
++ break;
++ case (WMI_PSTREAM_TIMEOUT_EVENTID):
++ status = wmi_pstream_timeout_event_rx(wmip, datap, len);
++ break;
++ case (WMI_NEIGHBOR_REPORT_EVENTID):
++ status = wmi_neighborReport_event_rx(wmip, datap, len);
++ break;
++ case (WMI_SCAN_COMPLETE_EVENTID):
++ status = wmi_scanComplete_rx(wmip, datap, len);
++ break;
++ case (WMI_CMDERROR_EVENTID):
++ status = wmi_errorEvent_rx(wmip, datap, len);
++ break;
++ case (WMI_REPORT_STATISTICS_EVENTID):
++ status = wmi_statsEvent_rx(wmip, datap, len);
++ break;
++ case (WMI_RSSI_THRESHOLD_EVENTID):
++ status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
++ break;
++ case (WMI_ERROR_REPORT_EVENTID):
++ status = wmi_reportErrorEvent_rx(wmip, datap, len);
++ break;
++ case (WMI_OPT_RX_FRAME_EVENTID):
++ status = wmi_opt_frame_event_rx(wmip, datap, len);
++ break;
++ case (WMI_REPORT_ROAM_TBL_EVENTID):
++ status = wmi_roam_tbl_event_rx(wmip, datap, len);
++ break;
++ case (WMI_EXTENSION_EVENTID):
++ status = wmi_control_rx_xtnd(wmip, osbuf);
++ break;
++ case (WMI_CAC_EVENTID):
++ status = wmi_cac_event_rx(wmip, datap, len);
++ break;
++ case (WMI_REPORT_ROAM_DATA_EVENTID):
++ status = wmi_roam_data_event_rx(wmip, datap, len);
++ break;
++ default:
++ WMI_DEBUG_PRINTF("Host received unknown reply/event with id 0x%x\n",
++ id);
++ wmip->wmi_stats.cmd_id_err++;
++ status = A_ERROR;
++ break;
++ }
++
++ a_netbuf_free(osbuf);
++
++ return status;
++}
++
++static A_STATUS
++wmi_create_pstream_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_CRE_PRIORITY_STREAM_REPLY *reply;
++ A_INT8 priNum = 0, i;
++ A_UINT8 dir;
++
++ if (len < sizeof(WMI_CRE_PRIORITY_STREAM_REPLY)) {
++ WMI_DEBUG_PRINTF ("wmi: create pstream reply too short (%d)!!\n", len);
++ return A_EINVAL;
++ }
++
++ reply = (WMI_CRE_PRIORITY_STREAM_REPLY *)datap;
++ WMI_DEBUG_PRINTF("wmi: create pstream reply: status = %d, tx mbox = %d rx mbox %d\n",
++ reply->status, reply->txQueueNumber, reply->rxQueueNumber);
++
++ dir = reply->trafficDirection;
++ if (dir == BIDIR_TRAFFIC) {
++ wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][reply->trafficClass] = FALSE;
++ wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][reply->trafficClass] = FALSE;
++ } else {
++ wmip->wmi_pstreamCmdInProgress[dir][reply->trafficClass] = FALSE;
++ }
++ wmip->wmi_cpstreamCmdInProgress = FALSE;
++
++ if (reply->status == A_FAILED_CREATE_REMOVE_PSTREAM_FIRST) {
++ /* do nothing */
++ return A_OK;
++ }
++
++ if (reply->status == A_SUCCEEDED) {
++ if (reply->trafficDirection == DNLINK_TRAFFIC ||
++ reply->trafficDirection == BIDIR_TRAFFIC) {
++ wmip->wmi_olderPriRxMbox = wmip->wmi_newerPriRxMbox;
++ wmip->wmi_newerPriRxMbox = reply->rxQueueNumber;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][reply->rxQueueNumber].trafficClass = reply->trafficClass;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][reply->rxQueueNumber].priorityNum = 0;
++ wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][reply->trafficClass] = reply->rxQueueNumber;
++ }
++
++ if (reply->trafficDirection == UPLINK_TRAFFIC ||
++ reply->trafficDirection == BIDIR_TRAFFIC) {
++ wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][reply->trafficClass] = reply->txQueueNumber;
++ /* In case of 3rd pstreams being created, target automatically deletes the old pstream
++ * and accomodates the this one. Though, the host does not know of this implicit
++ * deletion,
++ */
++ if (wmip->wmi_numQoSStream < WMI_MAX_NUM_PRI_STREAMS)
++ wmip->wmi_numQoSStream++;
++ for (i = 0; i < WMI_MAX_NUM_PRI_STREAMS; i++) {
++ if (!wmip->wmi_priority[i].inUse) {
++ priNum = i;
++ wmip->wmi_priority[i].inUse = 1;
++ wmip->wmi_priority[i].mbox = reply->txQueueNumber;
++ break;
++ }
++ }
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][reply->txQueueNumber].trafficClass = reply->trafficClass;
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][reply->txQueueNumber].priorityNum = priNum;
++ ar6000_set_numdataendpts(wmip->wmi_devt, wmip->wmi_numQoSStream+1);
++ }
++ }
++
++ return reply->status;
++}
++
++static A_STATUS
++wmi_delete_pstream_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_DEL_PRIORITY_STREAM_REPLY *reply;
++ A_UINT8 dir;
++
++ if (len < sizeof(WMI_DEL_PRIORITY_STREAM_REPLY)) {
++ return A_EINVAL;
++ }
++
++ reply = (WMI_DEL_PRIORITY_STREAM_REPLY *)datap;
++ WMI_DEBUG_PRINTF("wmi: delete pstream reply: status = %d, rx mbox = %d tx mbox = %d\n", reply->status,
++ reply->rxQueueNumber, reply->txQueueNumber);
++
++ dir = reply->trafficDirection;
++ if (dir == BIDIR_TRAFFIC) {
++ wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][reply->trafficClass] = FALSE;
++ wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][reply->trafficClass] = FALSE;
++ } else {
++ wmip->wmi_pstreamCmdInProgress[dir][reply->trafficClass] = FALSE;
++ }
++
++ if (reply->status == A_OK) {
++ /* update internal states for Rx Path */
++ if (reply->trafficDirection == DNLINK_TRAFFIC || reply->trafficDirection == BIDIR_TRAFFIC) {
++ A_UINT8 qNum = reply->rxQueueNumber;
++ A_UINT8 class = wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].trafficClass;
++ wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][class] = WMI_NOT_MAPPED;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].priorityNum = WMI_NOT_MAPPED;
++ wmip->wmi_mboxMap[DNLINK_TRAFFIC][qNum].trafficClass = WMM_AC_BE;
++ if (wmip->wmi_newerPriRxMbox == qNum) {
++ wmip->wmi_newerPriRxMbox = wmip->wmi_olderPriRxMbox;
++ wmip->wmi_olderPriRxMbox = qNum;
++ }
++ }
++ }
++
++ return reply->status;
++}
++
++static A_STATUS
++wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
++
++ if (len < sizeof(WMI_READY_EVENT)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi: ready event\n");
++ wmip->wmi_ready = TRUE;
++ ar6000_ready_event(wmip->wmi_devt, ev->macaddr, ev->phyCapability);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_CONNECT_EVENT *ev;
++
++ if (len < sizeof(WMI_CONNECT_EVENT)) {
++ return A_EINVAL;
++ }
++ ev = (WMI_CONNECT_EVENT *)datap;
++#ifdef DEBUG
++ WMI_DEBUG_PRINTF("wmi: connected event at freq %d ", ev->channel);
++ WMI_DEBUG_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
++ ev->bssid[0], ev->bssid[1], ev->bssid[2],
++ ev->bssid[3], ev->bssid[4], ev->bssid[5]);
++#endif /* DEBUG */
++
++ A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
++
++ ar6000_connect_event(wmip->wmi_devt, ev->channel, ev->bssid,
++ ev->listenInterval, ev->beaconIeLen, ev->assocReqLen,
++ ev->assocRespLen, ev->assocInfo);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_REG_DOMAIN_EVENT *ev;
++
++ if (len < sizeof(*ev)) {
++ return A_EINVAL;
++ }
++ ev = (WMI_REG_DOMAIN_EVENT *)datap;
++
++ ar6000_regDomain_event(wmip->wmi_devt, ev->regDomain);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_NEIGHBOR_REPORT_EVENT *ev;
++ int numAps;
++
++ if (len < sizeof(*ev)) {
++ return A_EINVAL;
++ }
++ ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
++ numAps = ev->numberOfAps;
++
++ if (len < (sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
++ return A_EINVAL;
++ }
++
++ ar6000_neighborReport_event(wmip->wmi_devt, numAps, ev->neighbor);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_DISCONNECT_EVENT *ev;
++
++ if (len < sizeof(WMI_DISCONNECT_EVENT)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi: disconnected event\n");
++
++ ev = (WMI_DISCONNECT_EVENT *)datap;
++
++ A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
++
++ ar6000_disconnect_event(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
++ ev->assocRespLen, ev->assocInfo);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TKIP_MICERR_EVENT *ev;
++
++ if (len < sizeof(*ev)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi: tkip micerr event\n");
++
++ ev = (WMI_TKIP_MICERR_EVENT *)datap;
++ ar6000_tkip_micerr_event(wmip->wmi_devt, ev->keyid, ev->ismcast);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ bss_t *bss;
++ WMI_BSS_INFO_HDR *bih;
++ A_UINT8 *buf;
++
++ if (len <= sizeof(WMI_BSS_INFO_HDR)) {
++ return A_EINVAL;
++ }
++
++ bih = (WMI_BSS_INFO_HDR *)datap;
++ buf = datap + sizeof(WMI_BSS_INFO_HDR);
++ len -= sizeof(WMI_BSS_INFO_HDR);
++
++ WMI_DEBUG_PRINTF2("wmi: bssInfo event %2.2x:%2.2x\n",
++ bih->bssid[4], bih->bssid[5]);
++
++ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
++ if (bss != NULL) {
++ /*
++ * Free up the node. Not the most efficient process given
++ * we are about to allocate a new node but it is simple and should be
++ * adequate.
++ */
++ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
++ }
++
++ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
++ if (bss == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ bss->ni_rssi = bih->rssi;
++ A_ASSERT(bss->ni_buf != NULL);
++ A_MEMCPY(bss->ni_buf, buf, len);
++
++ if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
++ wlan_node_free(bss);
++ return A_EINVAL;
++ }
++
++ /*
++ * Update the frequency in ie_chan, overwriting of channel number
++ * which is done in wlan_parse_beacon
++ */
++ bss->ni_cie.ie_chan = bih->channel;
++ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ bss_t *bss;
++ WMI_OPT_RX_INFO_HDR *bih;
++ A_UINT8 *buf;
++
++ if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
++ return A_EINVAL;
++ }
++
++ bih = (WMI_OPT_RX_INFO_HDR *)datap;
++ buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
++ len -= sizeof(WMI_OPT_RX_INFO_HDR);
++
++ WMI_DEBUG_PRINTF2("wmi: opt frame event %2.2x:%2.2x\n",
++ bih->bssid[4], bih->bssid[5]);
++
++ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
++ if (bss != NULL) {
++ /*
++ * Free up the node. Not the most efficient process given
++ * we are about to allocate a new node but it is simple and should be
++ * adequate.
++ */
++ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
++ }
++
++ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
++ if (bss == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ bss->ni_rssi = bih->rssi;
++ bss->ni_cie.ie_chan = bih->channel;
++ A_ASSERT(bss->ni_buf != NULL);
++ A_MEMCPY(bss->ni_buf, buf, len);
++ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_PSTREAM_TIMEOUT_EVENT *ev;
++
++ if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
++ return A_EINVAL;
++ }
++
++ WMI_DEBUG_PRINTF("wmi: pstream timeout event\n");
++
++ ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
++
++ wmi_delete_pstream_cmd(wmip, ev->txQueueNumber, ev->rxQueueNumber, ev->trafficDirection);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_BIT_RATE_CMD *reply;
++ A_INT32 rate;
++
++ if (len < sizeof(WMI_BIT_RATE_CMD)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_BIT_RATE_CMD *)datap;
++ WMI_DEBUG_PRINTF("wmi: get bit rate reply %d\n", reply->rateIndex);
++
++ if (reply->rateIndex == RATE_AUTO) {
++ rate = RATE_AUTO;
++ } else {
++ rate = wmi_rateTable[reply->rateIndex];
++ }
++
++ ar6000_bitrate_rx(wmip->wmi_devt, rate);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_CHANNEL_LIST_REPLY *reply;
++
++ if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_CHANNEL_LIST_REPLY *)datap;
++ WMI_DEBUG_PRINTF("wmi: get channel list reply\n");
++
++ ar6000_channelList_rx(wmip->wmi_devt, reply->numChannels,
++ reply->channelList);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TX_PWR_REPLY *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_TX_PWR_REPLY *)datap;
++ WMI_DEBUG_PRINTF("wmi: get tx pwr reply\n");
++
++ ar6000_txPwr_rx(wmip->wmi_devt, reply->dbM);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMIX_DSETOPENREQ_EVENT *dsetopenreq;
++
++ if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi_dset_open_req_rx: DataSet Open Request event\n");
++
++ dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
++ WMI_DEBUG_PRINTF("wmi_dset_open_req_rx: dset_id=0x%x\n", dsetopenreq->dset_id);
++ ar6000_dset_open_req(wmip->wmi_devt,
++ dsetopenreq->dset_id,
++ dsetopenreq->targ_dset_handle,
++ dsetopenreq->targ_reply_fn,
++ dsetopenreq->targ_reply_arg);
++
++ return A_OK;
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++static A_STATUS
++wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMIX_DSETCLOSE_EVENT *dsetclose;
++
++ if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi: DataSet Close event\n");
++
++ dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
++ ar6000_dset_close(wmip->wmi_devt, dsetclose->access_cookie);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMIX_DSETDATAREQ_EVENT *dsetdatareq;
++
++ if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
++ return A_EINVAL;
++ }
++ WMI_DEBUG_PRINTF("wmi: DataSet Data Request event\n");
++
++ dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
++ ar6000_dset_data_req(wmip->wmi_devt,
++ dsetdatareq->access_cookie,
++ dsetdatareq->offset,
++ dsetdatareq->length,
++ dsetdatareq->targ_buf,
++ dsetdatareq->targ_reply_fn,
++ dsetdatareq->targ_reply_arg);
++
++ return A_OK;
++}
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++static A_STATUS
++wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ ar6000_scanComplete_event(wmip->wmi_devt);
++
++ return A_OK;
++}
++
++/*
++ * Target is reporting a programming error. This is for
++ * developer aid only. Target only checks a few common violations
++ * and it is responsibility of host to do all error checking.
++ * Behavior of target after wmi error event is undefined.
++ * A reset is recommended.
++ */
++static A_STATUS
++wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_CMD_ERROR_EVENT *ev;
++
++ ev = (WMI_CMD_ERROR_EVENT *)datap;
++ A_PRINTF("Programming Error: cmd=%d ", ev->commandId);
++ switch (ev->errorCode) {
++ case (INVALID_PARAM):
++ A_PRINTF("Illegal Parameter\n");
++ break;
++ case (ILLEGAL_STATE):
++ A_PRINTF("Illegal State\n");
++ break;
++ case (INTERNAL_ERROR):
++ A_PRINTF("Internal Error\n");
++ break;
++ }
++
++ return A_OK;
++}
++
++
++static A_STATUS
++wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TARGET_STATS *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_TARGET_STATS *)datap;
++ WMI_DEBUG_PRINTF("wmi: target stats event\n");
++
++ ar6000_targetStats_event(wmip->wmi_devt, reply);
++
++ return A_OK;
++}
++
++
++
++static A_STATUS
++wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_RSSI_THRESHOLD_EVENT *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
++ WMI_DEBUG_PRINTF("wmi: rssi threshold event\n");
++
++ ar6000_rssiThreshold_event(wmip->wmi_devt, reply->range);
++
++ return A_OK;
++}
++
++
++static A_STATUS
++wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TARGET_ERROR_REPORT_EVENT *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
++ WMI_DEBUG_PRINTF("wmi: report error event\n");
++
++ ar6000_reportError_event(wmip->wmi_devt, reply->errorVal);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_CAC_EVENT *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_CAC_EVENT *)datap;
++ WMI_DEBUG_PRINTF("wmi: report CAC event\n");
++
++ ar6000_cac_event(wmip->wmi_devt, reply->ac,
++ reply->cac_indication, reply->statusCode,
++ reply->tspecSuggestion);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TARGET_ROAM_TBL *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_TARGET_ROAM_TBL *)datap;
++ WMI_DEBUG_PRINTF("wmi: target ROAM TABLE event\n");
++
++ ar6000_roam_tbl_event(wmip->wmi_devt, reply);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_TARGET_ROAM_DATA *reply;
++
++ if (len < sizeof(*reply)) {
++ return A_EINVAL;
++ }
++ reply = (WMI_TARGET_ROAM_DATA *)datap;
++ WMI_DEBUG_PRINTF("wmi: target ROAM DATA event\n");
++
++ ar6000_roam_data_event(wmip->wmi_devt, reply);
++
++ return A_OK;
++}
++
++#if CONFIG_HOST_GPIO_SUPPORT
++static A_STATUS
++wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
++
++ WMI_DEBUG_PRINTF("wmi GPIO interrupt received intrmask=0x%x input=0x%x.\n",
++ gpio_intr->intr_mask, gpio_intr->input_values);
++
++ ar6000_gpio_intr_rx(gpio_intr->intr_mask, gpio_intr->input_values);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
++
++ WMI_DEBUG_PRINTF("wmi GPIO data received reg=%d value=0x%x.\n",
++ gpio_data->reg_id, gpio_data->value);
++
++ ar6000_gpio_data_rx(gpio_data->reg_id, gpio_data->value);
++
++ return A_OK;
++}
++
++static A_STATUS
++wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
++{
++ WMI_DEBUG_PRINTF("wmi GPIO ACK received.\n");
++
++ ar6000_gpio_ack_rx();
++
++ return A_OK;
++}
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++/*
++ * Called to send a wmi command. Command specific data is already built
++ * on osbuf and current osbuf->data points to it.
++ */
++A_STATUS
++wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
++ WMI_SYNC_FLAG syncflag)
++{
++#define IS_LONG_CMD(cmdId) (cmdId == WMI_OPT_TX_FRAME_CMDID)
++ WMI_CMD_HDR *cHdr;
++ A_UINT8 mbox = WMI_CONTROL_MBOX;
++
++ A_ASSERT(osbuf != NULL);
++
++ if (syncflag >= END_WMIFLAG) {
++ return A_EINVAL;
++ }
++
++ if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
++ /*
++ * We want to make sure all data currently queued is transmitted before
++ * the cmd execution. Establish a new sync point.
++ */
++ wmi_sync_point(wmip);
++ }
++
++ if (a_netbuf_push(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ cHdr = (WMI_CMD_HDR *)a_netbuf_to_data(osbuf);
++ cHdr->commandId = cmdId;
++
++ /*
++ * Send cmd, some via control pipe, others via data pipe
++ */
++ if (IS_LONG_CMD(cmdId)) {
++ wmi_data_hdr_add(wmip, osbuf, CNTL_MSGTYPE);
++ mbox = WMI_BEST_EFFORT_MBOX;
++ }
++ ar6000_control_tx(wmip->wmi_devt, osbuf, mbox);
++
++ if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
++ /*
++ * We want to make sure all new data queued waits for the command to
++ * execute. Establish a new sync point.
++ */
++ wmi_sync_point(wmip);
++ }
++
++ return (A_OK);
++#undef IS_LONG_CMD
++}
++
++A_STATUS
++wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
++ WMI_SYNC_FLAG syncflag)
++{
++ WMIX_CMD_HDR *cHdr;
++
++ if (a_netbuf_push(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ cHdr = (WMIX_CMD_HDR *)a_netbuf_to_data(osbuf);
++ cHdr->commandId = cmdId;
++
++ return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
++}
++
++A_STATUS
++wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
++ DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
++ CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
++ CRYPTO_TYPE groupCrypto,A_UINT8 groupCryptoLen,
++ int ssidLength, A_UCHAR *ssid,
++ A_UINT8 *bssid, A_UINT16 channel)
++{
++ void *osbuf;
++ WMI_CONNECT_CMD *cc;
++
++ if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
++ return A_EINVAL;
++ }
++ if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(WMI_CONNECT_CMD));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(WMI_CONNECT_CMD));
++
++ cc = (WMI_CONNECT_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cc, sizeof(*cc));
++
++ A_MEMCPY(cc->ssid, ssid, ssidLength);
++ cc->ssidLength = ssidLength;
++ cc->networkType = netType;
++ cc->dot11AuthMode = dot11AuthMode;
++ cc->authMode = authMode;
++ cc->pairwiseCryptoType = pairwiseCrypto;
++ cc->pairwiseCryptoLen = pairwiseCryptoLen;
++ cc->groupCryptoType = groupCrypto;
++ cc->groupCryptoLen = groupCryptoLen;
++ cc->channel = channel;
++
++ if (bssid != NULL) {
++ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
++{
++ void *osbuf;
++ WMI_RECONNECT_CMD *cc;
++
++ osbuf = a_netbuf_alloc(sizeof(WMI_RECONNECT_CMD));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(WMI_RECONNECT_CMD));
++
++ cc = (WMI_RECONNECT_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cc, sizeof(*cc));
++
++ cc->channel = channel;
++
++ if (bssid != NULL) {
++ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_disconnect_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++ A_STATUS status;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ status = (wmi_cmd_send(wmip, osbuf, WMI_DISCONNECT_CMDID,
++ SYNC_BEFORE_WMIFLAG));
++ wmi_qos_state_init(wmip);
++ return status;
++}
++
++A_STATUS
++wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType)
++{
++ void *osbuf;
++ WMI_START_SCAN_CMD *sc;
++
++ if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*sc));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*sc));
++
++ sc = (WMI_START_SCAN_CMD *)(a_netbuf_to_data(osbuf));
++ sc->scanType = scanType;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
++ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
++ A_UINT16 act_chdw_msec, A_UINT16 pas_chdw_msec,
++ A_UINT8 shScanRatio)
++{
++ void *osbuf;
++ WMI_SCAN_PARAMS_CMD *sc;
++
++ osbuf = a_netbuf_alloc(sizeof(*sc));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*sc));
++
++ sc = (WMI_SCAN_PARAMS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(sc, sizeof(*sc));
++ sc->fg_start_period = fg_start_sec;
++ sc->fg_end_period = fg_end_sec;
++ sc->bg_period = bg_sec;
++ sc->act_chdwell_time = act_chdw_msec;
++ sc->pas_chdwell_time = pas_chdw_msec;
++ sc->shortScanRatio = shScanRatio;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter)
++{
++ void *osbuf;
++ WMI_BSS_FILTER_CMD *cmd;
++
++ if (filter >= LAST_BSS_FILTER) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_BSS_FILTER_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->bssFilter = filter;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
++ A_UINT8 ssidLength, A_UCHAR *ssid)
++{
++ void *osbuf;
++ WMI_PROBED_SSID_CMD *cmd;
++
++ if (index > MAX_PROBED_SSID_INDEX) {
++ return A_EINVAL;
++ }
++ if (ssidLength > sizeof(cmd->ssid)) {
++ return A_EINVAL;
++ }
++ if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
++ return A_EINVAL;
++ }
++ if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_PROBED_SSID_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->entryIndex = index;
++ cmd->flag = flag;
++ cmd->ssidLength = ssidLength;
++ A_MEMCPY(cmd->ssid, ssid, ssidLength);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
++{
++ void *osbuf;
++ WMI_LISTEN_INT_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_LISTEN_INT_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->listenInterval = listenInterval;
++ cmd->numBeacons = listenBeacons;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
++{
++ void *osbuf;
++ WMI_BMISS_TIME_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_BMISS_TIME_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->bmissTime = bmissTime;
++ cmd->numBeacons = bmissBeacons;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
++ A_UINT8 ieLen, A_UINT8 *ieInfo)
++{
++ void *osbuf;
++ WMI_SET_ASSOC_INFO_CMD *cmd;
++ A_UINT16 cmdLen;
++
++ cmdLen = sizeof(*cmd) + ieLen - 1;
++ osbuf = a_netbuf_alloc(cmdLen);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, cmdLen);
++
++ cmd = (WMI_SET_ASSOC_INFO_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, cmdLen);
++ cmd->ieType = ieType;
++ cmd->bufferSize = ieLen;
++ A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
++{
++ void *osbuf;
++ WMI_POWER_MODE_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_POWER_MODE_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->powerMode = powerMode;
++ wmip->wmi_powerMode = powerMode;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
++ A_UINT16 atim_windows, A_UINT16 timeout_value)
++{
++ void *osbuf;
++ WMI_IBSS_PM_CAPS_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_IBSS_PM_CAPS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->power_saving = pmEnable;
++ cmd->ttl = ttl;
++ cmd->atim_windows = atim_windows;
++ cmd->timeout_value = timeout_value;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
++ A_UINT16 psPollNum, A_UINT16 dtimPolicy)
++{
++ void *osbuf;
++ WMI_POWER_PARAMS_CMD *pm;
++
++ osbuf = a_netbuf_alloc(sizeof(*pm));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*pm));
++
++ pm = (WMI_POWER_PARAMS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(pm, sizeof(*pm));
++ pm->idle_period = idlePeriod;
++ pm->pspoll_number = psPollNum;
++ pm->dtim_policy = dtimPolicy;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
++{
++ void *osbuf;
++ WMI_DISC_TIMEOUT_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_DISC_TIMEOUT_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->disconnectTimeout = timeout;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
++ A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
++ A_UINT8 *keyMaterial, WMI_SYNC_FLAG sync_flag)
++{
++ void *osbuf;
++ WMI_ADD_CIPHER_KEY_CMD *cmd;
++
++ if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
++ (keyMaterial == NULL))
++ {
++ return A_EINVAL;
++ }
++
++ if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_ADD_CIPHER_KEY_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->keyIndex = keyIndex;
++ cmd->keyType = keyType;
++ cmd->keyUsage = keyUsage;
++ cmd->keyLength = keyLength;
++ A_MEMCPY(cmd->key, keyMaterial, keyLength);
++ if (NULL != keyRSC) {
++ A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
++}
++
++A_STATUS
++wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
++{
++ void *osbuf;
++ WMI_ADD_KRK_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_ADD_KRK_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_delete_krk_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0);
++
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_KRK_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
++{
++ void *osbuf;
++ WMI_DELETE_CIPHER_KEY_CMD *cmd;
++
++ if (keyIndex > WMI_MAX_KEY_INDEX) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->keyIndex = keyIndex;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
++ A_BOOL set)
++{
++ void *osbuf;
++ WMI_SET_PMKID_CMD *cmd;
++
++ if (bssid == NULL) {
++ return A_EINVAL;
++ }
++
++ if ((set == TRUE) && (pmkId == NULL)) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_PMKID_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++ if (set == TRUE) {
++ A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
++ cmd->enable = PMKID_ENABLE;
++ } else {
++ A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
++ cmd->enable = PMKID_DISABLE;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
++{
++ void *osbuf;
++ WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, int endPoint)
++{
++ WMI_DATA_HDR *dtHdr;
++
++ A_ASSERT(endPoint != WMI_CONTROL_MBOX);
++ A_ASSERT(osbuf != NULL);
++
++ if (a_netbuf_push(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
++ return A_NO_MEMORY;
++ }
++
++ dtHdr = (WMI_DATA_HDR *)a_netbuf_to_data(osbuf);
++ dtHdr->info =
++ (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
++
++ WMI_DEBUG_PRINTF("wmi sync pkt sent on mbox %d\n", endPoint);
++
++ return (ar6000_control_tx(wmip->wmi_devt, osbuf, endPoint));
++}
++
++static A_STATUS
++wmi_sync_point(struct wmi_t *wmip)
++{
++ void *cmd_osbuf, *be_osbuf, *pri_osbuf[WMI_MAX_NUM_PRI_STREAMS];
++ A_UINT8 i;
++ A_STATUS status;
++
++ WMI_DEBUG_PRINTF("wmi_sync_point\n");
++ /*
++ * We allocate all network buffers needed so we will be able to
++ * send all required frames.
++ */
++ cmd_osbuf = a_netbuf_alloc(0); /* no payload */
++ if (cmd_osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ be_osbuf = a_netbuf_alloc(0); /* no payload */
++ if (be_osbuf == NULL) {
++ a_netbuf_free(cmd_osbuf);
++ return A_NO_MEMORY;
++ }
++
++ for (i = 0; i < wmip->wmi_numQoSStream; i++) {
++ pri_osbuf[i] = a_netbuf_alloc(0); /* no payload */
++ if (pri_osbuf[i] == NULL) {
++ A_UINT8 j;
++ a_netbuf_free(be_osbuf);
++ a_netbuf_free(cmd_osbuf);
++ /* free previously allocated bufs */
++ for (j = 0; j < i; j++) {
++ a_netbuf_free(pri_osbuf[j]);
++ }
++ return A_NO_MEMORY;
++ }
++ }
++
++ /*
++ * Send sync cmd followed by sync data messages on all endpoints being
++ * used
++ */
++ status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
++ NO_SYNC_WMIFLAG);
++
++ if (status == A_OK) {
++ status = wmi_dataSync_send(wmip, be_osbuf, WMI_BEST_EFFORT_MBOX);
++ }
++
++ if (status == A_OK) {
++ A_UINT8 priIndex = 0;
++ for (i = 0; i < wmip->wmi_numQoSStream; i++) {
++ while (priIndex < WMI_MAX_NUM_PRI_STREAMS &&
++ (!wmip->wmi_priority[priIndex].inUse)) {
++ priIndex++;
++ }
++ if (priIndex >= WMI_MAX_NUM_PRI_STREAMS) {
++ break;
++ }
++ status = wmi_dataSync_send(wmip, pri_osbuf[i], wmip->wmi_priority[priIndex].mbox);
++ if (status != A_OK) {
++ break;
++ }
++ priIndex++;
++ }
++ }
++
++ return (status);
++}
++
++A_STATUS
++wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
++{
++ void *osbuf;
++ WMI_CREATE_PSTREAM_CMD *cmd;
++
++ /* Validate all the parameters. */
++ if( !((params->userPriority < 8) &&
++ (params->trafficDirection == BIDIR_TRAFFIC ||
++ params->trafficDirection == UPLINK_TRAFFIC ||
++ params->trafficDirection == DNLINK_TRAFFIC ) &&
++ (params->userPriority <= 0x7) &&
++ (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) &&
++ (params->trafficClass != WMM_AC_BE) &&
++ (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
++ params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
++ (params->voicePSCapability == DISABLE_FOR_THIS_AC ||
++ params->voicePSCapability == ENABLE_FOR_THIS_AC ||
++ params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
++ (params->tsid < 15)) )
++ {
++ return A_EINVAL;
++ }
++
++
++ if (params->trafficDirection == BIDIR_TRAFFIC) {
++ if (wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][params->trafficClass]
++ || wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][params->trafficClass]
++ || wmip->wmi_cpstreamCmdInProgress) {
++ WMI_DEBUG_PRINTF("create %d too busy !\n",params->trafficClass);
++ return A_EBUSY;
++ }
++ wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][params->trafficClass] = TRUE;
++ wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][params->trafficClass] = TRUE;
++ } else {
++ if (wmip->wmi_pstreamCmdInProgress[params->trafficDirection][params->trafficClass]
++ || wmip->wmi_cpstreamCmdInProgress) {
++ WMI_DEBUG_PRINTF("create %d too busy !\n",params->trafficClass);
++ return A_EBUSY;
++ }
++ wmip->wmi_pstreamCmdInProgress[params->trafficDirection][params->trafficClass] = TRUE;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ wmip->wmi_cpstreamCmdInProgress = TRUE;
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ WMI_DEBUG_PRINTF("Sending create_pstream_cmd: ac=%d, rxQ=%d, dir=%d\n",
++ params->trafficClass, params->rxQueueNum, params->trafficDirection);
++ cmd = (WMI_CREATE_PSTREAM_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ A_MEMCPY(cmd, params, sizeof(*cmd));
++
++ if (params->rxQueueNum == 0xFF) {
++ if(wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][params->trafficClass] != WMI_NOT_MAPPED)
++ cmd->rxQueueNum = wmip->wmi_trafficClassMap[DNLINK_TRAFFIC][params->trafficClass];
++ else
++ cmd->rxQueueNum = wmip->wmi_olderPriRxMbox;
++ } else {
++ cmd->rxQueueNum = params->rxQueueNum;
++ }
++
++ /* mike: should be SYNC_BEFORE_WMIFLAG */
++ return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 txQueueNumber, A_UINT8 rxQueueNumber, A_UINT8 dir)
++{
++ void *osbuf;
++ WMI_DELETE_PSTREAM_CMD *cmd;
++ A_STATUS status;
++ A_UINT8 class;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ if (dir == BIDIR_TRAFFIC) {
++ class = wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].trafficClass;
++ if (wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][class]
++ || wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][class]) {
++ return A_EBUSY;
++ }
++ wmip->wmi_pstreamCmdInProgress[UPLINK_TRAFFIC][class] = TRUE;
++ wmip->wmi_pstreamCmdInProgress[DNLINK_TRAFFIC][class] = TRUE;
++ } else {
++ if (dir == UPLINK_TRAFFIC) {
++ class = wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].trafficClass;
++ } else {
++ class = wmip->wmi_mboxMap[DNLINK_TRAFFIC][rxQueueNumber].trafficClass;
++ }
++ if (wmip->wmi_pstreamCmdInProgress[dir][class]) {
++ return A_EBUSY;
++ }
++ wmip->wmi_pstreamCmdInProgress[dir][class] = TRUE;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_DELETE_PSTREAM_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->txQueueNumber = txQueueNumber;
++ cmd->rxQueueNumber = rxQueueNumber;
++ cmd->trafficDirection = dir;
++ cmd->trafficClass = class;
++ WMI_DEBUG_PRINTF("Sending delete_pstream_cmd: txQ=%d, rxQ=%d, dir=%d\n",
++ txQueueNumber, rxQueueNumber, dir);
++ status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
++ (dir == UPLINK_TRAFFIC || dir == BIDIR_TRAFFIC) ? SYNC_BEFORE_WMIFLAG : NO_SYNC_WMIFLAG));
++
++ if (class != WMM_AC_BE) {
++ /* Update internal states */
++ if (dir == UPLINK_TRAFFIC || dir == BIDIR_TRAFFIC) {
++ wmip->wmi_numQoSStream--;
++ ar6000_set_numdataendpts(wmip->wmi_devt, wmip->wmi_numQoSStream+1);
++ wmip->wmi_priority[wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].priorityNum].inUse = 0;
++ wmip->wmi_trafficClassMap[UPLINK_TRAFFIC][class] = WMI_NOT_MAPPED;
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].priorityNum = WMI_NOT_MAPPED;
++ wmip->wmi_mboxMap[UPLINK_TRAFFIC][txQueueNumber].trafficClass = WMM_AC_BE;
++ }
++ }
++
++ return status;
++}
++
++
++/*
++ * used to set the bit rate. rate is in Kbps. If rate == -1
++ * then auto selection is used.
++ */
++A_STATUS
++wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate)
++{
++ void *osbuf;
++ WMI_BIT_RATE_CMD *cmd;
++ A_INT8 index;
++
++ index = wmi_validate_bitrate(wmip, rate);
++ if(index == A_EINVAL){
++ return A_EINVAL;
++ }
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_BIT_RATE_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++
++ cmd->rateIndex = index;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_get_bitrate_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_INT8
++wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
++{
++ A_INT8 i;
++ if (rate != -1)
++ {
++ for (i=0;;i++)
++ {
++ if (wmi_rateTable[i] == 0) {
++ return A_EINVAL;
++ }
++ if (wmi_rateTable[i] == rate) {
++ break;
++ }
++ }
++ }
++ else{
++ i = -1;
++ }
++
++ if (wmip->wmi_phyMode == WMI_11A_MODE &&
++ (i < MODE_A_SUPPORT_RATE_START || i > MODE_A_SUPPORT_RATE_STOP))
++ {
++ return A_EINVAL;
++ } else if (wmip->wmi_phyMode == WMI_11B_MODE &&
++ (i < MODE_B_SUPPORT_RATE_START || i > MODE_B_SUPPORT_RATE_STOP))
++ {
++ return A_EINVAL;
++ } else if (wmip->wmi_phyMode == WMI_11GONLY_MODE &&
++ (i < MODE_GONLY_SUPPORT_RATE_START || i > MODE_GONLY_SUPPORT_RATE_STOP))
++ {
++ return A_EINVAL;
++ }
++
++ return i;
++ }
++
++A_STATUS
++wmi_get_channelList_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_CHANNEL_LIST_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++/*
++ * used to generate a wmi sey channel Parameters cmd.
++ * mode should always be specified and corresponds to the phy mode of the
++ * wlan.
++ * numChan should alway sbe specified. If zero indicates that all available
++ * channels should be used.
++ * channelList is an array of channel frequencies (in Mhz) which the radio
++ * should limit its operation to. It should be NULL if numChan == 0. Size of
++ * array should correspond to numChan entries.
++ */
++A_STATUS
++wmi_set_channelParams_cmd(struct wmi_t *wmip, WMI_PHY_MODE mode, A_INT8 numChan,
++ A_UINT16 *channelList)
++{
++ void *osbuf;
++ WMI_CHANNEL_PARAMS_CMD *cmd;
++ A_INT8 size;
++
++ size = sizeof (*cmd);
++
++ if (numChan) {
++ if (numChan > WMI_MAX_CHANNELS) {
++ return A_EINVAL;
++ }
++ size += sizeof(A_UINT16) * (numChan - 1);
++ }
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_CHANNEL_PARAMS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, size);
++
++ wmip->wmi_phyMode = mode;
++ cmd->phyMode = mode;
++ cmd->numChannels = numChan;
++ A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_link_threshold_params(struct wmi_t *wmip,
++ A_UINT8 highThreshold_upperVal,
++ A_UINT8 highThreshold_lowerVal,
++ A_UINT8 lowThreshold_upperVal,
++ A_UINT8 lowThreshold_lowerVal,
++ A_UINT32 pollTime)
++{
++ void *osbuf;
++ A_INT8 size;
++ WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
++
++ /* These values are in ascending order */
++ if( highThreshold_upperVal <= highThreshold_lowerVal ||
++ lowThreshold_upperVal <= lowThreshold_lowerVal ||
++ highThreshold_lowerVal <= lowThreshold_upperVal)
++ return A_EINVAL;
++
++ size = sizeof (*cmd);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, size);
++
++ cmd->highThreshold_upperVal = highThreshold_upperVal;
++ cmd->highThreshold_lowerVal = highThreshold_lowerVal;
++ cmd->lowThreshold_upperVal = lowThreshold_upperVal;
++ cmd->lowThreshold_lowerVal = lowThreshold_lowerVal;
++ cmd->pollTime = pollTime;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++
++A_STATUS
++wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
++{
++ void *osbuf;
++ A_INT8 size;
++ WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
++
++ size = sizeof (*cmd);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, size);
++
++ cmd->bitmask = mask;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++
++A_STATUS
++wmi_get_stats_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_STATISTICS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
++{
++ void *osbuf;
++ WMI_ADD_BAD_AP_CMD *cmd;
++
++ if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_ADD_BAD_AP_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->badApIndex = apIndex;
++ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
++{
++ void *osbuf;
++ WMI_DELETE_BAD_AP_CMD *cmd;
++
++ if (apIndex > WMI_MAX_BAD_AP_INDEX) {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_DELETE_BAD_AP_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->badApIndex = apIndex;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
++{
++ void *osbuf;
++ WMI_SET_TX_PWR_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_TX_PWR_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->dbM = dbM;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_get_txPwr_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
++}
++
++A_INT8
++wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 dir, A_UINT8 trafficClass)
++{
++ if ((dir == UPLINK_TRAFFIC || dir == DNLINK_TRAFFIC) &&
++ (trafficClass <= WMM_AC_VO)) {
++ return wmip->wmi_trafficClassMap[dir][trafficClass];
++ } else {
++ return WMI_NOT_MAPPED;
++ }
++}
++
++A_STATUS
++wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ osbuf = a_netbuf_alloc(0); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_TBL_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
++{
++ void *osbuf;
++ A_UINT32 size = sizeof(A_UINT8);
++ WMI_TARGET_ROAM_DATA *cmd;
++
++ osbuf = a_netbuf_alloc(size); /* no payload */
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_TARGET_ROAM_DATA *)(a_netbuf_to_data(osbuf));
++ cmd->roamDataType = roamDataType;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
++ A_UINT8 size)
++{
++ void *osbuf;
++ WMI_SET_ROAM_CTRL_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_SET_ROAM_CTRL_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, size);
++
++ A_MEMCPY(cmd, p, size);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
++ WMI_POWERSAVE_TIMERS_CMD *pCmd,
++ A_UINT8 size)
++{
++ void *osbuf;
++ WMI_POWERSAVE_TIMERS_CMD *cmd;
++
++ /* These timers can't be zero */
++ if(!pCmd->psPollTimeout || !pCmd->eospTimeout)
++ return A_EINVAL;
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, size);
++
++ cmd = (WMI_POWERSAVE_TIMERS_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, size);
++
++ A_MEMCPY(cmd, pCmd, size);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_dset_open_reply(struct wmi_t *wmip,
++ A_UINT32 status,
++ A_UINT32 access_cookie,
++ A_UINT32 dset_size,
++ A_UINT32 dset_version,
++ A_UINT32 targ_handle,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg)
++{
++ void *osbuf;
++ WMIX_DSETOPEN_REPLY_CMD *open_reply;
++
++ WMI_DEBUG_PRINTF("wmi_dset_open_reply: wmip=0x%x\n", (int)wmip);
++
++ osbuf = a_netbuf_alloc(sizeof(*open_reply));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*open_reply));
++ open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(a_netbuf_to_data(osbuf));
++
++ open_reply->status = status;
++ open_reply->targ_dset_handle = targ_handle;
++ open_reply->targ_reply_fn = targ_reply_fn;
++ open_reply->targ_reply_arg = targ_reply_arg;
++ open_reply->access_cookie = access_cookie;
++ open_reply->size = dset_size;
++ open_reply->version = dset_version;
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++A_STATUS
++wmi_dset_data_reply(struct wmi_t *wmip,
++ A_UINT32 status,
++ A_UINT8 *user_buf,
++ A_UINT32 length,
++ A_UINT32 targ_buf,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg)
++{
++ void *osbuf;
++ WMIX_DSETDATA_REPLY_CMD *data_reply;
++ int size;
++
++ size = sizeof(*data_reply) + length;
++
++ WMI_DEBUG_PRINTF("wmi_dset_data_reply: length=%d status=%d\n", length, status);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(osbuf, size);
++ data_reply = (WMIX_DSETDATA_REPLY_CMD *)(a_netbuf_to_data(osbuf));
++
++ data_reply->status = status;
++ data_reply->targ_buf = targ_buf;
++ data_reply->targ_reply_fn = targ_reply_fn;
++ data_reply->targ_reply_arg = targ_reply_arg;
++ data_reply->length = length;
++
++ if (status == A_OK) {
++ if (a_copy_from_user(data_reply->buf, user_buf, length)) {
++ return A_ERROR;
++ }
++ }
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++/* Send a command to Target to change GPIO output pins. */
++A_STATUS
++wmi_gpio_output_set(struct wmi_t *wmip,
++ A_UINT32 set_mask,
++ A_UINT32 clear_mask,
++ A_UINT32 enable_mask,
++ A_UINT32 disable_mask)
++{
++ void *osbuf;
++ WMIX_GPIO_OUTPUT_SET_CMD *output_set;
++ int size;
++
++ size = sizeof(*output_set);
++
++ WMI_DEBUG_PRINTF("wmi_gpio_output_set: set=0x%x clear=0x%x enb=0x%x dis=0x%x\n",
++ set_mask, clear_mask, enable_mask, disable_mask);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(osbuf, size);
++ output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(a_netbuf_to_data(osbuf));
++
++ output_set->set_mask = set_mask;
++ output_set->clear_mask = clear_mask;
++ output_set->enable_mask = enable_mask;
++ output_set->disable_mask = disable_mask;
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target requesting state of the GPIO input pins */
++A_STATUS
++wmi_gpio_input_get(struct wmi_t *wmip)
++{
++ void *osbuf;
++
++ WMI_DEBUG_PRINTF("wmi_gpio_input_get\n");
++
++ osbuf = a_netbuf_alloc(0);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INPUT_GET_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target that changes the value of a GPIO register. */
++A_STATUS
++wmi_gpio_register_set(struct wmi_t *wmip,
++ A_UINT32 gpioreg_id,
++ A_UINT32 value)
++{
++ void *osbuf;
++ WMIX_GPIO_REGISTER_SET_CMD *register_set;
++ int size;
++
++ size = sizeof(*register_set);
++
++ WMI_DEBUG_PRINTF("wmi_gpio_register_set: reg=%d value=0x%x\n",
++ gpioreg_id, value);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(osbuf, size);
++ register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(a_netbuf_to_data(osbuf));
++
++ register_set->gpioreg_id = gpioreg_id;
++ register_set->value = value;
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target to fetch the value of a GPIO register. */
++A_STATUS
++wmi_gpio_register_get(struct wmi_t *wmip,
++ A_UINT32 gpioreg_id)
++{
++ void *osbuf;
++ WMIX_GPIO_REGISTER_GET_CMD *register_get;
++ int size;
++
++ size = sizeof(*register_get);
++
++ WMI_DEBUG_PRINTF("wmi_gpio_register_get: reg=%d\n", gpioreg_id);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(osbuf, size);
++ register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(a_netbuf_to_data(osbuf));
++
++ register_get->gpioreg_id = gpioreg_id;
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++/* Send a command to the Target acknowledging some GPIO interrupts. */
++A_STATUS
++wmi_gpio_intr_ack(struct wmi_t *wmip,
++ A_UINT32 ack_mask)
++{
++ void *osbuf;
++ WMIX_GPIO_INTR_ACK_CMD *intr_ack;
++ int size;
++
++ size = sizeof(*intr_ack);
++
++ WMI_DEBUG_PRINTF("wmi_gpio_intr_ack: ack_mask=0x%x\n", ack_mask);
++
++ osbuf = a_netbuf_alloc(size);
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(osbuf, size);
++ intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(a_netbuf_to_data(osbuf));
++
++ intr_ack->ack_mask = ack_mask;
++
++ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++A_STATUS
++wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin,
++ A_UINT8 eCWmax, A_UINT8 aifsn)
++{
++ void *osbuf;
++ WMI_SET_ACCESS_PARAMS_CMD *cmd;
++
++ if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
++ (aifsn > WMI_MAX_AIFSN_ACPARAM))
++ {
++ return A_EINVAL;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->txop = txop;
++ cmd->eCWmin = eCWmin;
++ cmd->eCWmax = eCWmax;
++ cmd->aifsn = aifsn;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
++ A_UINT8 trafficClass, A_UINT8 maxRetries)
++{
++ void *osbuf;
++ WMI_SET_RETRY_LIMITS_CMD *cmd;
++
++ if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
++ (frameType != DATA_FRAMETYPE))
++ {
++ return A_EINVAL;
++ }
++
++ if (maxRetries > WMI_MAX_RETRIES) {
++ return A_EINVAL;
++ }
++
++ if (frameType != DATA_FRAMETYPE) {
++ trafficClass = 0;
++ }
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_RETRY_LIMITS_CMD *)(a_netbuf_to_data(osbuf));
++ cmd->frameType = frameType;
++ cmd->trafficClass = trafficClass;
++ cmd->maxRetries = maxRetries;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++void
++wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
++{
++ if (bssid != NULL) {
++ A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
++ }
++}
++
++A_STATUS
++wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
++{
++ void *osbuf;
++ WMI_SET_OPT_MODE_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_OPT_MODE_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->optMode = optMode;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
++ SYNC_BOTH_WMIFLAG));
++}
++
++A_STATUS
++wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
++ A_UINT8 frmType,
++ A_UINT8 *dstMacAddr,
++ A_UINT8 *bssid,
++ A_UINT16 optIEDataLen,
++ A_UINT8 *optIEData)
++{
++ void *osbuf;
++ WMI_OPT_TX_FRAME_CMD *cmd;
++ osbuf = a_netbuf_alloc(optIEDataLen + sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, (optIEDataLen + sizeof(*cmd)));
++
++ cmd = (WMI_OPT_TX_FRAME_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)));
++
++ cmd->frmType = frmType;
++ cmd->optIEDataLen = optIEDataLen;
++ cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd));
++ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
++ A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
++ A_MEMCPY(cmd->optIEData, optIEData, optIEDataLen);
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_STATUS
++wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
++{
++ void *osbuf;
++ WMI_BEACON_INT_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_BEACON_INT_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->beaconInterval = intvl;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++
++A_STATUS
++wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
++{
++ void *osbuf;
++ WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->voicePktSize = voicePktSize;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++
++A_STATUS
++wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
++{
++ void *osbuf;
++ WMI_SET_MAX_SP_LEN_CMD *cmd;
++
++ /* maxSPLen is a two-bit value. If user trys to set anything
++ * other than this, then its invalid
++ */
++ if(maxSPLen & ~0x03)
++ return A_EINVAL;
++
++ osbuf = a_netbuf_alloc(sizeof(*cmd));
++ if (osbuf == NULL) {
++ return A_NO_MEMORY;
++ }
++
++ a_netbuf_put(osbuf, sizeof(*cmd));
++
++ cmd = (WMI_SET_MAX_SP_LEN_CMD *)(a_netbuf_to_data(osbuf));
++ A_MEMZERO(cmd, sizeof(*cmd));
++ cmd->maxSPLen = maxSPLen;
++
++ return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
++ NO_SYNC_WMIFLAG));
++}
++
++A_UINT8
++convert_userPriority_to_trafficClass(A_UINT8 userPriority)
++{
++ return (up_to_ac[userPriority & 0x7]);
++}
++
++A_UINT8
++wmi_get_power_mode_cmd(struct wmi_t *wmip)
++{
++ return wmip->wmi_powerMode;
++}
++
++A_STATUS
++wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
++{
++ A_STATUS ret = A_OK;
++
++#define TSPEC_SUSPENSION_INTERVAL_CCXV4_DEF (~0)
++#define TSPEC_SERVICE_START_TIME_CCXV4_DEF 0
++#define TSPEC_MAX_BURST_SIZE_CCXV4_DEF 0
++#define TSPEC_DELAY_BOUND_CCXV4_DEF 0
++#define TSPEC_MEDIUM_TIME_CCXV4_DEF 0
++#define TSPEC_SBA_CCXV4_DEF 0x2000 /* factor is 1 */
++
++ /* Verify TSPEC params for CCX v4 compliance */
++ if(tspecCompliance == CCX_V4_COMPLIANCE) {
++ if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_CCXV4_DEF) ||
++ (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_CCXV4_DEF) ||
++ (pCmd->minDataRate != pCmd->meanDataRate) ||
++ (pCmd->minDataRate != pCmd->peakDataRate) ||
++ (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_CCXV4_DEF) ||
++ (pCmd->delayBound != TSPEC_DELAY_BOUND_CCXV4_DEF) ||
++ (pCmd->sba != TSPEC_SBA_CCXV4_DEF) ||
++ (pCmd->mediumTime != TSPEC_MEDIUM_TIME_CCXV4_DEF)) {
++
++ WMI_DEBUG_PRINTF("%s: Invalid TSPEC params\n", __FUNCTION__);
++ A_PRINTF("%s: Invalid TSPEC params\n", __FUNCTION__);
++ ret = A_EINVAL;
++ }
++ }
++
++ return ret;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/ar6000/ar6000_drv.c 2007-11-08 16:15:45.000000000 +0100
+@@ -0,0 +1,5752 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++/*
++ * This driver is a pseudo ethernet driver to access the Atheros AR6000
++ * WLAN Device
++ */
++static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/etnaGPL1.1/host/os/linux/ar6000_drv.c#2 $";
++
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/skbuff.h>
++#include <linux/if_ether.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <net/iw_handler.h>
++#include <linux/if_arp.h>
++#include <linux/ip.h>
++#include <linux/rtnetlink.h>
++#include <linux/netdevice.h>
++#include <asm/semaphore.h>
++#include <linux/wireless.h>
++
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/htc.h"
++#include "../include/wmi.h"
++#include "../include/athdrv.h"
++#include "ar6000_drv.h"
++#include "../include/bmi.h"
++#include "../include/ieee80211.h"
++#include "../include/ieee80211_ioctl.h"
++#include "../include/wlan_api.h"
++#include "../include/wmi_api.h"
++#include "../include/dset_api.h"
++#include "../include/app/dset.h"
++#include "../include/gpio_api.h"
++#include "../include/AR6000_gpio.h"
++#include "../include/host_version.h"
++#include "../include/hw/mbox_host_reg.h"
++#include "../include/hw/mc_reg.h"
++#include "../include/hw/mbox_reg.h"
++#include "../include/hw/rtc_reg.h"
++
++MODULE_LICENSE("Dual BSD/GPL");
++
++#if defined (SPI)
++#define CONTROL_PADCONF_AA12 0x00E8
++unsigned int awake_gpio = 17;
++unsigned int awake_gpio_pad_conf_offset = CONTROL_PADCONF_AA12;
++unsigned int awake_gpio_pad_conf_byte = 1;
++unsigned int awake_gpio_pad_mode_value = 0x3;
++#endif
++
++int bmienable = 0;
++unsigned int bypasswmi = 0;
++unsigned int debuglevel = 0;
++int tspecCompliance = CCX_V4_COMPLIANCE;
++unsigned int busspeedlow = 0;
++unsigned int onebitmode = 0;
++unsigned int skipflash = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++module_param(bmienable, int, 0644);
++module_param(bypasswmi, int, 0644);
++module_param(debuglevel, int, 0644);
++module_param(tspecCompliance, int, 0644);
++module_param(onebitmode, int, 0644);
++module_param(busspeedlow, int, 0644);
++module_param(skipflash, int, 0644);
++
++#else
++
++#define __user
++/* for linux 2.4 and lower */
++MODULE_PARM(bmienable,"i");
++MODULE_PARM(bypasswmi,"i");
++MODULE_PARM(debuglevel, "i");
++MODULE_PARM(onebitmode,"i");
++MODULE_PARM(busspeedlow, "i");
++MODULE_PARM(skipflash, "i");
++
++#if defined SPI
++MODULE_PARM(awake_gpio, "i");
++MODULE_PARM_DESC(awake_gpio, "Awake GPIO pin");
++MODULE_PARM(awake_gpio_pad_conf_offset, "i");
++MODULE_PARM_DESC(awake_gpio_pad_conf_offset,
++ "Awake GPIO pin pad config offset");
++MODULE_PARM(awake_gpio_pad_conf_byte, "i");
++MODULE_PARM_DESC(awake_gpio_pad_conf_byte,
++ "Awake GPIO pin pad byte number");
++MODULE_PARM(awake_gpio_pad_mode_value, "i");
++MODULE_PARM_DESC(awake_gpio_pad_mode_value,
++ "Awake GPIO pin mode value");
++#endif
++#endif
++
++#define MAX_ALLOWED_TXQ_DEPTH (HTC_DATA_REQUEST_RING_BUFFER_SIZE - 2)
++static int txFlowCtrlThresh[HTC_MAILBOX_NUM_MAX]
++ = {0 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++ 1 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++ 2 * (MAX_ALLOWED_TXQ_DEPTH - 1),
++ 3 * (MAX_ALLOWED_TXQ_DEPTH - 1)};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
++/* in 2.6.10 and later this is now a pointer to a uint */
++unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
++#define mboxnum &_mboxnum
++#else
++unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
++#endif
++
++#ifdef DEBUG
++int debugdriver = 1;
++unsigned int debughtc = 128;
++unsigned int debugbmi = 1;
++unsigned int debughif = 1;
++unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
++unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
++unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
++unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++module_param(debugdriver, int, 0644);
++module_param(debughtc, int, 0644);
++module_param(debugbmi, int, 0644);
++module_param(debughif, int, 0644);
++module_param_array(txcreditsavailable, int, mboxnum, 0644);
++module_param_array(txcreditsconsumed, int, mboxnum, 0644);
++module_param_array(txcreditintrenable, int, mboxnum, 0644);
++module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644);
++#else
++/* linux 2.4 and lower */
++MODULE_PARM(debugdriver, "i");
++MODULE_PARM(debughtc, "i");
++MODULE_PARM(debugbmi, "i");
++MODULE_PARM(debughif, "i");
++MODULE_PARM(txcreditsavailable, "0-3i");
++MODULE_PARM(txcreditsconsumed, "0-3i");
++MODULE_PARM(txcreditintrenable, "0-3i");
++MODULE_PARM(txcreditintrenableaggregate, "0-3i");
++#endif
++
++#endif /* DEBUG */
++
++unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
++unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
++unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++module_param_array(tx_attempt, int, mboxnum, 0644);
++module_param_array(tx_post, int, mboxnum, 0644);
++module_param_array(tx_complete, int, mboxnum, 0644);
++#else
++MODULE_PARM(tx_attempt, "0-3i");
++MODULE_PARM(tx_post, "0-3i");
++MODULE_PARM(tx_complete, "0-3i");
++#endif
++
++#ifdef BLOCK_TX_PATH_FLAG
++int blocktx = 0;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++module_param(blocktx, int, 0644);
++#else
++MODULE_PARM(blocktx, "i");
++#endif
++#endif /* BLOCK_TX_PATH_FLAG */
++
++#ifdef DEBUG
++#define AR_DEBUG_PRINTF(args...) if (debugdriver) printk(args);
++#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) printk(args);
++#else
++#define AR_DEBUG_PRINTF(args...)
++#define AR_DEBUG2_PRINTF(args...)
++#endif
++
++/* Function declarations */
++static int ar6000_init_module(void);
++static void ar6000_cleanup_module(void);
++
++static int ar6000_init(struct net_device *dev);
++static int ar6000_open(struct net_device *dev);
++static int ar6000_close(struct net_device *dev);
++static void ar6000_init_control_info(AR_SOFTC_T *ar);
++static void ar6000_init_profile_info(AR_SOFTC_T *ar);
++static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
++static int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++static void ar6000_destroy(struct net_device *dev);
++static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
++static struct iw_statistics * ar6000_get_iwstats(struct net_device *dev);
++static void ar6000_ioctl_iwsetup(struct iw_handler_def *def);
++static int ar6000_ioctl_set_channelParams(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_ioctl_set_probedSsid(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_set_link_threshold(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_set_access_params(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_ioctl_set_disconnect_timeout(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata);
++static int ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata);
++static int ar6000_ioctl_get_roam_tbl(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata);
++static int ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata);
++static int ar6000_ioctl_get_power_mode(struct net_device *dev,
++ struct ifreq *rq);
++
++#ifdef HTC_RAW_INTERFACE
++static void ar6000_htc_raw_read_cb(HTC_TARGET *htcTarget,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID evId,
++ HTC_EVENT_INFO *evInfo,
++ void *arg);
++static void ar6000_htc_raw_unread_cb(HTC_TARGET *htcTarget,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID evId,
++ HTC_EVENT_INFO *evInfo,
++ void *arg);
++static void ar6000_htc_raw_write_cb(HTC_TARGET *htcTarget,
++ HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID evId,
++ HTC_EVENT_INFO *evInfo,
++ void *arg);
++static int ar6000_htc_raw_open(HTC_TARGET *htcTarget);
++static int ar6000_htc_raw_close(HTC_TARGET *htcTarget);
++static ssize_t ar6000_htc_raw_read(HTC_TARGET *htcTarget,
++ HTC_ENDPOINT_ID endPointId,
++ char __user *buffer, size_t count);
++static ssize_t ar6000_htc_raw_write(HTC_TARGET *htcTarget,
++ HTC_ENDPOINT_ID endPointId,
++ char __user *buffer, size_t count);
++#endif /* HTC_RAW_INTERFACE */
++static void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
++static int ar6000_ioctl_addpmkid(struct net_device *dev,
++ struct iw_request_info *info, void *w, char *extra);
++
++#if CONFIG_HOST_DSET_SUPPORT
++static void ar6000_dset_init(void);
++static int ar6000_ioctl_wait_dset_req(struct net_device *dev, struct ifreq *rq);
++static int ar6000_ioctl_dset_open_reply(struct net_device *dev,
++ struct ifreq *rq);
++static int ar6000_ioctl_dset_data_reply(struct net_device *dev,
++ struct ifreq *rq);
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++static void ar6000_gpio_init(void);
++A_STATUS ar6000_gpio_output_set(struct net_device *dev,
++ A_UINT32 set_mask,
++ A_UINT32 clear_mask,
++ A_UINT32 enable_mask,
++ A_UINT32 disable_mask);
++static A_STATUS ar6000_gpio_input_get(struct net_device *dev);
++static A_STATUS ar6000_gpio_register_set(struct net_device *dev,
++ A_UINT32 gpioreg_id,
++ A_UINT32 value);
++static A_STATUS ar6000_gpio_register_get(struct net_device *dev,
++ A_UINT32 gpioreg_id);
++static A_STATUS ar6000_gpio_intr_ack(struct net_device *dev,
++ A_UINT32 ack_mask);
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++/*
++ * HTC event handlers
++ */
++static void ar6000_avail_ev(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID id, HTC_EVENT_INFO *evInfo, void *arg);
++
++static void ar6000_unavail_ev(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID id, HTC_EVENT_INFO *evInfo, void *arg);
++
++static void ar6000_rx(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID id, HTC_EVENT_INFO *evInfo, void *arg);
++
++static void ar6000_rx_refill(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID id, HTC_EVENT_INFO *evInfo, void *arg);
++
++static void ar6000_tx_complete(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID id, HTC_EVENT_INFO *evInfo, void *arg);
++
++/*
++ * Static variables
++ */
++static struct net_device *ar6000_devices[MAX_AR6000];
++static struct iw_handler_def ath_iw_handler_def;
++static DECLARE_WAIT_QUEUE_HEAD(arEvent);
++static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++#if CONFIG_HOST_GPIO_SUPPORT
++struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results;
++/* gpio_reg_results and gpio_data_available are protected by arSem */
++static struct ar6000_gpio_register_cmd_s gpio_reg_results;
++static A_BOOL gpio_data_available; /* Requested GPIO data available */
++static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
++static A_BOOL gpio_ack_received; /* GPIO ack was received */
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++/*
++ * adhoc PS support
++ */
++static void ar6000_cookie_init(AR_SOFTC_T *ar);
++static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
++static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
++static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
++
++static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
++
++static int __init
++ar6000_init_module(void)
++{
++ static int probed = 0;
++ A_STATUS status;
++
++ printk("######## %s() ############\n", __FUNCTION__);
++
++ if (probed) {
++ return -ENODEV;
++ }
++ probed++;
++
++#if CONFIG_HOST_DSET_SUPPORT
++ ar6000_dset_init();
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++ ar6000_gpio_init();
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++ status = HTCInit();
++ if(status != A_OK)
++ return -ENODEV;
++
++ HTCEventReg(NULL, ENDPOINT_UNUSED, HTC_TARGET_AVAILABLE,
++ ar6000_avail_ev, NULL);
++ HTCEventReg(NULL, ENDPOINT_UNUSED, HTC_TARGET_UNAVAILABLE,
++ ar6000_unavail_ev, NULL);
++
++ return 0;
++}
++
++static void __exit
++ar6000_cleanup_module(void)
++{
++ int i = 0;
++ struct net_device *ar6000_netdev;
++
++ for (i=0; i < MAX_AR6000; i++) {
++ if (ar6000_devices[i] != NULL) {
++ ar6000_netdev = ar6000_devices[i];
++ ar6000_devices[i] = NULL;
++ ar6000_destroy(ar6000_netdev);
++ }
++ }
++
++ /* This will unregister with the SDIO bus driver */
++ HTCShutDown(NULL);
++
++ AR_DEBUG_PRINTF("ar6000_cleanup: success\n");
++}
++
++/*
++ * Write to the AR6000 through its diagnostic window.
++ * No cooperation from the Target is required for this.
++ */
++A_STATUS
++ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
++{
++ HIF_REQUEST request;
++ A_STATUS status;
++
++ HIF_FRAME_REQUEST(&request,
++ HIF_WRITE,
++ HIF_EXTENDED_IO,
++ HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS,
++ HIF_INCREMENTAL_ADDRESS);
++
++ status = HIFReadWrite(hifDevice,
++ WINDOW_DATA_ADDRESS,
++ (A_UCHAR *)data,
++ sizeof(A_UINT32),
++ &request,
++ NULL);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data);
++ return status;
++ }
++
++ status = HIFReadWrite(hifDevice,
++ WINDOW_WRITE_ADDR_ADDRESS+1,
++ ((A_UCHAR *)(address))+1,
++ sizeof(A_UINT32)-1,
++ &request,
++ NULL);
++
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Cannot write initial bytes of 0x%x to WINDOW_WRITE_ADDR_ADDRESS\n", *address);
++ return status;
++ }
++
++ status = HIFReadWrite(hifDevice,
++ WINDOW_WRITE_ADDR_ADDRESS,
++ (A_UCHAR *)address,
++ sizeof(A_UINT8),
++ &request,
++ NULL);
++
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Cannot write 0x%x to WINDOW_WRITE_ADDR_ADDRESS\n", *address);
++ return status;
++ }
++
++ return status;
++}
++
++/*
++ * HTC Event handlers
++ */
++static void
++ar6000_avail_ev(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid, HTC_EVENT_ID event,
++ HTC_EVENT_INFO *evInfo,
++ void *arg)
++{
++ int i;
++ struct net_device *dev;
++ AR_SOFTC_T *ar;
++ int device_index = 0;
++
++ AR_DEBUG_PRINTF("ar6000_available\n");
++
++ for (i=0; i < MAX_AR6000; i++) {
++ if (ar6000_devices[i] == NULL) {
++ break;
++ }
++ }
++
++ if (i == MAX_AR6000) {
++ AR_DEBUG_PRINTF("ar6000_available: max devices reached\n");
++ return;
++ }
++
++ /* Save this. It gives a bit better readability especially since */
++ /* we use another local "i" variable below. */
++ device_index = i;
++
++ A_ASSERT(htcTarget != NULL);
++ A_ASSERT(event == HTC_TARGET_AVAILABLE);
++
++ dev = alloc_etherdev(sizeof(AR_SOFTC_T));
++ if (dev == NULL) {
++ AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n");
++ return;
++ }
++ SET_MODULE_OWNER(dev);
++
++ ether_setup(dev);
++
++ if (dev->priv == NULL) {
++ printk(KERN_CRIT "ar6000_available: Could not allocate memory\n");
++ return;
++ }
++
++ A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T));
++
++ ar = (AR_SOFTC_T *)dev->priv;
++ ar->arNetDev = dev;
++ ar->arHtcTarget = htcTarget;
++ ar->arHifDevice = evInfo->buffer;
++ ar->arWlanState = WLAN_ENABLED;
++
++ ar6000_init_control_info(ar);
++ init_waitqueue_head(&arEvent);
++ sema_init(&ar->arSem, 1);
++
++ /*
++ * If requested, perform some magic which requires no cooperation from
++ * the Target. It causes the Target to ignore flash and execute the
++ * OS from ROM.
++ *
++ * This code uses the Diagnostic Window to remap instructions at
++ * the start of ROM in such a way that on the next CPU reset, the
++ * ROM code avoids using flash. Then it uses the Diagnostic
++ * Window to force a CPU Warm Reset.
++ *
++ * This is intended to support recovery from a corrupted flash.
++ */
++ if (skipflash)
++ {
++ int i;
++
++ static struct {
++ A_UINT32 addr;
++ A_UINT32 data;
++ } ForceROM[] = {
++ /* NB: This is ROM-version dependent. */
++ {0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */
++ {0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */
++
++ {MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */
++ {MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */
++ {MC_REMAP_SIZE_ADDRESS, 0x00000000}, /* ...1 cache line */
++ {MC_REMAP_VALID_ADDRESS, 0x00000001}, /* ...remap is valid */
++
++ {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
++
++ {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
++ };
++
++ AR_DEBUG_PRINTF("Force Target to execute from ROM....\n");
++ for (i=0; i<sizeof(ForceROM)/sizeof(*ForceROM); i++) {
++ if (ar6000_WriteRegDiag(ar->arHifDevice,
++ &ForceROM[i].addr,
++ &ForceROM[i].data) != A_OK)
++ {
++ AR_DEBUG_PRINTF("Cannot force Target to execute ROM!\n");
++ break;
++ }
++ }
++ }
++
++ BMIInit();
++ if ((BMIGetTargetId(ar->arHifDevice, &ar->arVersion.target_ver)) != A_OK) {
++ return;
++ }
++
++ spin_lock_init(&ar->arLock);
++
++ /* Don't install the init function if BMI is requested */
++ if(!bmienable)
++ {
++ dev->init = ar6000_init;
++ }
++ dev->open = &ar6000_open;
++ dev->stop = &ar6000_close;
++ dev->hard_start_xmit = &ar6000_data_tx;
++ dev->get_stats = &ar6000_get_stats;
++ /* dev->tx_timeout = ar6000_tx_timeout; */
++ dev->do_ioctl = &ar6000_ioctl;
++ dev->watchdog_timeo = AR6000_TX_TIMEOUT;
++ ar6000_ioctl_iwsetup(&ath_iw_handler_def);
++ dev->wireless_handlers = &ath_iw_handler_def;
++
++ /*
++ * We need the OS to provide us with more headroom in order to
++ * perform dix to 802.3, WMI header encap, and the HTC header
++ */
++ dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
++ sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN;
++
++ /* This runs the init function */
++ if (register_netdev(dev)) {
++ AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n");
++ ar6000_destroy(dev);
++ return;
++ }
++
++ /* We only register the device in the global list if we succeed. */
++ /* If the device is in the global list, it will be destroyed */
++ /* when the module is unloaded. */
++ ar6000_devices[device_index] = dev;
++
++ AR_DEBUG_PRINTF("ar6000_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n",
++ dev->name, (A_UINT32)htcTarget, (A_UINT32)dev, device_index,
++ (A_UINT32)ar);
++}
++
++static void
++ar6000_unavail_ev(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID event, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ int i;
++ AR_SOFTC_T *ar;
++ struct net_device *ar6000_netdev;
++
++ for (i=0; i < MAX_AR6000; i++) {
++ if (ar6000_devices[i] != NULL) {
++ ar = (AR_SOFTC_T *)ar6000_devices[i]->priv;
++ if (ar && ar->arHtcTarget == htcTarget) {
++ ar6000_netdev = ar6000_devices[i];
++ ar6000_devices[i] = NULL;
++ ar6000_destroy(ar6000_netdev);
++ }
++ }
++ }
++}
++
++static void
++ar6000_destroy(struct net_device *dev)
++{
++ AR_SOFTC_T *ar;
++
++ if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL))
++ {
++ AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__);
++ return;
++ }
++
++ /* Stop the transmit queues */
++ netif_stop_queue(dev);
++
++ /* Disable the target and the interrupts associated with it */
++ if (ar->arWmiReady == TRUE)
++ {
++ if (!bypasswmi)
++ {
++ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
++ {
++ AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__);
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar6000_init_profile_info(ar);
++ wmi_disconnect_cmd(ar->arWmi);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++
++ /* It's necessary to wait for the tx pending cleaning */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX]==0);
++
++ ar->arWmiReady = FALSE;
++ ar->arConnected = FALSE;
++ ar->arConnectPending = FALSE;
++ wmi_shutdown(ar->arWmi);
++ ar->arWmiEnabled = FALSE;
++ ar->arWmi = NULL;
++ ar->arWlanState = WLAN_ENABLED;
++ }
++
++ /* It's necessary to wait for the tx pending cleaning */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX]==0);
++
++ HTCStop(ar->arHtcTarget);
++
++ /* It's necessary to wait for the tx pending cleaning */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX]==0);
++
++ AR_DEBUG_PRINTF("%s(): WMI and HTC stopped\n", __func__);
++ }
++ else
++ {
++ AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n",
++ __func__, (unsigned int) ar, (unsigned int) ar->arWmi);
++
++ /* Shut down WMI if we have started it */
++ if(ar->arWmiEnabled == TRUE)
++ {
++ AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__);
++ wmi_shutdown(ar->arWmi);
++ ar->arWmiEnabled = FALSE;
++ ar->arWmi = NULL;
++ }
++
++ /* It's necessary to wait for the tx pending cleaning */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX]==0);
++
++ HTCStop(ar->arHtcTarget);
++
++ /* It's necessary to wait for the tx pending cleaning */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX]==0);
++ }
++
++ BMIInit();
++
++ /* Done with cookies */
++ ar6000_cookie_cleanup(ar);
++
++ /* Free up the device data structure */
++ HTCShutDown(ar->arHtcTarget);
++
++ unregister_netdev(dev);
++#ifdef mvlcee31_2_4_20_omap2420_gsm_gprs
++ kfree(dev);
++#else
++ free_netdev(dev);
++#endif
++}
++
++static void
++ar6000_init_profile_info(AR_SOFTC_T *ar)
++{
++ ar->arSsidLen = 0;
++ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++ ar->arNetworkType = INFRA_NETWORK;
++ ar->arDot11AuthMode = OPEN_AUTH;
++ ar->arAuthMode = NONE_AUTH;
++ ar->arPairwiseCrypto = NONE_CRYPT;
++ ar->arPairwiseCryptoLen = 0;
++ ar->arGroupCrypto = NONE_CRYPT;
++ ar->arGroupCryptoLen = 0;
++ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
++ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
++ ar->arBssChannel = 0;
++}
++
++static void
++ar6000_init_control_info(AR_SOFTC_T *ar)
++{
++ ar->arWmiEnabled = FALSE;
++ ar6000_init_profile_info(ar);
++ ar->arDefTxKeyIndex = 0;
++ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
++ ar->arChannelHint = 0;
++ ar->arListenInterval = MAX_LISTEN_INTERVAL;
++ ar->arVersion.host_ver = AR6000_SW_VERSION;
++ ar->arRssi = 0;
++ ar->arTxPwr = 0;
++ ar->arTxPwrSet = FALSE;
++ ar->arBitRate = 0;
++ ar->arMaxRetries = 0;
++}
++
++static int
++ar6000_open(struct net_device *dev)
++{
++ /* Wake up the queues */
++ netif_wake_queue(dev);
++
++ return 0;
++}
++
++static int
++ar6000_close(struct net_device *dev)
++{
++ netif_stop_queue(dev);
++
++ return 0;
++}
++
++/* This function does one time initialization for the lifetime of the device */
++static int
++ar6000_init(struct net_device *dev)
++{
++ int i;
++ AR_SOFTC_T *ar;
++ int endpoint[] = { ENDPOINT1, ENDPOINT2, ENDPOINT3, ENDPOINT4 };
++ A_STATUS status;
++ A_INT32 timeleft;
++
++ if((ar = netdev_priv(dev)) == NULL)
++ {
++ return(-EIO);
++ }
++
++ /* Do we need to finish the BMI phase */
++ if(BMIDone(ar->arHifDevice) != A_OK)
++ {
++ return -EIO;
++ }
++
++ if (!bypasswmi)
++ {
++ if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
++ A_PRINTF("WARNING: Host version 0x%x does not match Target "
++ " version 0x%x!\n",
++ ar->arVersion.host_ver, ar->arVersion.target_ver);
++ }
++
++ /* Indicate that WMI is enabled (although not ready yet) */
++ ar->arWmiEnabled = TRUE;
++ if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
++ {
++ AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__);
++ return(-EIO);
++ }
++
++ AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__,
++ (unsigned int) ar->arWmi);
++ }
++
++ /* Install event handlers for each end point */
++ for(i = 0; i < (sizeof(endpoint) / sizeof(int)); i++)
++ {
++ if(HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_BUFFER_RECEIVED,
++ ar6000_rx, ar) != A_OK)
++ {
++ return(-EIO);
++ }
++
++ if(HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_DATA_AVAILABLE,
++ ar6000_rx_refill, ar) != A_OK)
++ {
++ return(-EIO);
++ }
++
++ if(HTCEventReg(ar->arHtcTarget, endpoint[i], HTC_BUFFER_SENT,
++ ar6000_tx_complete, ar) != A_OK)
++ {
++ return(-EIO);
++ }
++ }
++
++ /*
++ * Provide HTC with receive buffers
++ */
++ ar6000_rx_refill(ar->arHtcTarget, ENDPOINT1, HTC_DATA_AVAILABLE,
++ NULL, ar);
++
++ ar6000_rx_refill(ar->arHtcTarget, ENDPOINT2, HTC_DATA_AVAILABLE,
++ NULL, ar);
++
++ /*
++ * We will post the receive buffers only for SPE testing and so we are
++ * making it conditional on the 'bypasswmi' flag.
++ */
++ if (bypasswmi) {
++ ar6000_rx_refill(ar->arHtcTarget, ENDPOINT3, HTC_DATA_AVAILABLE,
++ NULL, ar);
++
++ ar6000_rx_refill(ar->arHtcTarget, ENDPOINT4, HTC_DATA_AVAILABLE,
++ NULL, ar);
++ }
++
++ /* Since cookies are used for HTC transports, they should be */
++ /* initialized prior to enabling HTC. */
++ ar6000_cookie_init(ar);
++
++ /* Enable the target and the interrupts associated with it */
++ status = HTCStart(ar->arHtcTarget);
++
++ if (status != A_OK) {
++ if (ar->arWmiEnabled == TRUE) {
++ wmi_shutdown(ar->arWmi);
++ ar->arWmiEnabled = FALSE;
++ ar->arWmi = NULL;
++ }
++ ar6000_cookie_cleanup(ar);
++ return -EIO;
++ }
++
++ if (!bypasswmi) {
++ /*Wait for Wmi event to be ready */
++ timeleft = wait_event_interruptible_timeout(arEvent,
++ (ar->arWmiReady == TRUE), 1 * HZ);
++
++ if(!timeleft || signal_pending(current))
++ {
++ AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n");
++ return -EIO;
++ }
++
++ AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__);
++ }
++
++ ar->arNumDataEndPts = 1;
++
++ return(0);
++}
++
++/* This would basically hold all the private ioctls that are not related to
++ WLAN operation */
++static int
++ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ HIF_DEVICE *hifDevice = ar->arHifDevice;
++ HTC_TARGET *htcTarget = ar->arHtcTarget;
++ int ret, param;
++ unsigned int address = 0;
++ unsigned int length = 0;
++ unsigned char *buffer;
++ char *userdata;
++#ifdef HTC_RAW_INTERFACE
++ HTC_ENDPOINT_ID endPointId = 0;
++ static A_BOOL rawIfInit = FALSE;
++#endif /* HTC_RAW_INTERFACE */
++ static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
++ WMI_SHORTSCANRATIO_DEFAULT };
++
++ if (cmd == AR6000_IOCTL_EXTENDED)
++ {
++ /*
++ * This allows for many more wireless ioctls than would otherwise
++ * be available. Applications embed the actual ioctl command in
++ * the first word of the parameter block, and use the command
++ * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
++ */
++ get_user(cmd, (int *)rq->ifr_data);
++ userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
++ }
++ else
++ {
++ userdata = (char *)rq->ifr_data;
++ }
++
++ if ((ar->arWlanState == WLAN_DISABLED) &&
++ (cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE))
++ {
++ return -EIO;
++ }
++
++ ret = 0;
++ switch(cmd)
++ {
++ case AR6000_XIOCTL_BMI_DONE:
++ if(bmienable)
++ {
++ ret = ar6000_init(dev);
++ }
++ else
++ {
++ ret = BMIDone(hifDevice);
++ }
++ break;
++
++ case AR6000_XIOCTL_BMI_READ_MEMORY:
++ get_user(address, (unsigned int *)userdata);
++ get_user(length, (unsigned int *)userdata + 1);
++ AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n",
++ address, length);
++ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
++ A_MEMZERO(buffer, length);
++ ret = BMIReadMemory(hifDevice, address, buffer, length);
++ if (copy_to_user(rq->ifr_data, buffer, length)) {
++ ret = -EFAULT;
++ }
++ A_FREE(buffer);
++ } else {
++ ret = -ENOMEM;
++ }
++ break;
++
++ case AR6000_XIOCTL_BMI_WRITE_MEMORY:
++ get_user(address, (unsigned int *)userdata);
++ get_user(length, (unsigned int *)userdata + 1);
++ AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n",
++ address, length);
++ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
++ A_MEMZERO(buffer, length);
++ if (copy_from_user(buffer, &userdata[sizeof(address) +
++ sizeof(length)], length))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = BMIWriteMemory(hifDevice, address, buffer, length);
++ }
++ A_FREE(buffer);
++ } else {
++ ret = -ENOMEM;
++ }
++ break;
++
++ case AR6000_XIOCTL_BMI_TEST:
++ AR_DEBUG_PRINTF("No longer supported\n");
++ ret = -EOPNOTSUPP;
++ break;
++
++ case AR6000_XIOCTL_BMI_EXECUTE:
++ get_user(address, (unsigned int *)userdata);
++ get_user(param, (unsigned int *)userdata + 1);
++ AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n",
++ address, param);
++ ret = BMIExecute(hifDevice, address, ¶m);
++ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
++ break;
++
++ case AR6000_XIOCTL_BMI_SET_APP_START:
++ get_user(address, (unsigned int *)userdata);
++ AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address);
++ ret = BMISetAppStart(hifDevice, address);
++ break;
++
++ case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
++ get_user(address, (unsigned int *)userdata);
++ ret = BMIReadSOCRegister(hifDevice, address, ¶m);
++ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
++ break;
++
++ case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
++ get_user(address, (unsigned int *)userdata);
++ get_user(param, (unsigned int *)userdata + 1);
++ ret = BMIWriteSOCRegister(hifDevice, address, param);
++ break;
++
++#ifdef HTC_RAW_INTERFACE
++ case AR6000_XIOCTL_HTC_RAW_OPEN:
++ ret = A_OK;
++ if (!rawIfInit) {
++ /* Terminate the BMI phase */
++ ret = BMIDone(hifDevice);
++ if (ret == A_OK) {
++ ret = ar6000_htc_raw_open(htcTarget);
++ }
++ if (ret == A_OK) {
++ rawIfInit = TRUE;
++ }
++ }
++ break;
++
++ case AR6000_XIOCTL_HTC_RAW_CLOSE:
++ if (rawIfInit) {
++ ret = ar6000_htc_raw_close(htcTarget);
++ rawIfInit = FALSE;
++ } else {
++ ret = A_ERROR;
++ }
++ break;
++
++ case AR6000_XIOCTL_HTC_RAW_READ:
++ if (rawIfInit) {
++ get_user(endPointId, (unsigned int *)userdata);
++ get_user(length, (unsigned int *)userdata + 1);
++ buffer = rq->ifr_data + sizeof(length);
++ ret = ar6000_htc_raw_read(htcTarget, endPointId,
++ buffer, length);
++ put_user(ret, (unsigned int *)rq->ifr_data);
++ } else {
++ ret = A_ERROR;
++ }
++ break;
++
++ case AR6000_XIOCTL_HTC_RAW_WRITE:
++ if (rawIfInit) {
++ get_user(endPointId, (unsigned int *)userdata);
++ get_user(length, (unsigned int *)userdata + 1);
++ buffer = userdata + sizeof(endPointId) + sizeof(length);
++ ret = ar6000_htc_raw_write(htcTarget, endPointId,
++ buffer, length);
++ put_user(ret, (unsigned int *)rq->ifr_data);
++ } else {
++ ret = A_ERROR;
++ }
++ break;
++#endif /* HTC_RAW_INTERFACE */
++
++ case AR6000_IOCTL_WMI_GETREV:
++ {
++ if (copy_to_user(rq->ifr_data, &ar->arVersion,
++ sizeof(ar->arVersion)))
++ {
++ ret = -EFAULT;
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SETPWR:
++ {
++ WMI_POWER_MODE_CMD pwrModeCmd;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&pwrModeCmd, userdata,
++ sizeof(pwrModeCmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
++ != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
++ {
++ WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&ibssPmCaps, userdata,
++ sizeof(ibssPmCaps)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
++ ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
++ {
++ ret = -EIO;
++ }
++ ar->arIbssPsEnable = ibssPmCaps.power_saving;
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_PMPARAMS:
++ {
++ WMI_POWER_PARAMS_CMD pmParams;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&pmParams, userdata,
++ sizeof(pmParams)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
++ pmParams.pspoll_number,
++ pmParams.dtim_policy) != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SETSCAN:
++ {
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&scParams, userdata,
++ sizeof(scParams)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
++ scParams.fg_end_period,
++ scParams.bg_period,
++ scParams.act_chdwell_time,
++ scParams.pas_chdwell_time,
++ scParams.shortScanRatio) != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SETLISTENINT:
++ {
++ WMI_LISTEN_INT_CMD listenCmd;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&listenCmd, userdata,
++ sizeof(listenCmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
++ ret = -EIO;
++ } else {
++ ar->arListenInterval = param;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_BMISS_TIME:
++ {
++ WMI_BMISS_TIME_CMD bmissCmd;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&bmissCmd, userdata,
++ sizeof(bmissCmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SETBSSFILTER:
++ {
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else {
++ get_user(param, (unsigned int *)userdata);
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_bssfilter_cmd(ar->arWmi, param) != A_OK) {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_LINKTHRESHOLD:
++ {
++ ret = ar6000_ioctl_set_link_threshold(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
++ {
++ ret = ar6000_ioctl_set_channelParams(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_PROBEDSSID:
++ {
++ ret = ar6000_ioctl_set_probedSsid(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_BADAP:
++ {
++ ret = ar6000_ioctl_set_badAp(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_CREATE_QOS:
++ {
++ ret = ar6000_ioctl_create_qos(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_DELETE_QOS:
++ {
++ ret = ar6000_ioctl_delete_qos(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
++ {
++ ret = ar6000_ioctl_get_qos_queue(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_GET_TARGET_STATS:
++ {
++ ret = ar6000_ioctl_get_target_stats(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
++ {
++ ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
++ {
++ WMI_SET_ASSOC_INFO_CMD cmd;
++ A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else {
++ get_user(cmd.ieType, userdata);
++ if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
++ ret = -EIO;
++ } else {
++ get_user(cmd.bufferSize, userdata + 1);
++ if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
++ ret = -EFAULT;
++ break;
++ }
++ if (copy_from_user(assocInfo, userdata + 2,
++ cmd.bufferSize))
++ {
++ ret = -EFAULT;
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
++ cmd.bufferSize,
++ assocInfo) != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ }
++ }
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
++ {
++ ret = ar6000_ioctl_set_access_params(dev, rq);
++ break;
++ }
++ case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
++ {
++ ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
++ break;
++ }
++#if CONFIG_HOST_DSET_SUPPORT
++ case AR6000_XIOCTL_WMI_DSET_WAIT_REQ:
++ {
++ ar6000_ioctl_wait_dset_req(dev, rq);
++ break;
++ }
++ case AR6000_XIOCTL_WMI_DSET_OPEN_REPLY:
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar6000_ioctl_dset_open_reply(dev, rq);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ break;
++ }
++ case AR6000_XIOCTL_WMI_DSET_DATA_REPLY:
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar6000_ioctl_dset_data_reply(dev, rq);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ break;
++ }
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++ case AR6000_XIOCTL_FORCE_TARGET_RESET:
++ {
++ if (htcTarget)
++ {
++// HTCForceReset(htcTarget);
++ }
++ else
++ {
++ AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n");
++ }
++ break;
++ }
++ case AR6000_XIOCTL_CHECK_TARGET_READY:
++ {
++ /* If we made it to here, then the Target exists and is ready. */
++ break;
++ }
++#if CONFIG_HOST_GPIO_SUPPORT
++ case AR6000_XIOCTL_GPIO_OUTPUT_SET:
++ {
++ struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ if (copy_from_user(&gpio_output_set_cmd, userdata,
++ sizeof(gpio_output_set_cmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = ar6000_gpio_output_set(dev,
++ gpio_output_set_cmd.set_mask,
++ gpio_output_set_cmd.clear_mask,
++ gpio_output_set_cmd.enable_mask,
++ gpio_output_set_cmd.disable_mask);
++ if (ret != A_OK) {
++ ret = EIO;
++ }
++ }
++ up(&ar->arSem);
++ break;
++ }
++ case AR6000_XIOCTL_GPIO_INPUT_GET:
++ {
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ ret = ar6000_gpio_input_get(dev);
++ if (ret != A_OK) {
++ up(&ar->arSem);
++ return -EIO;
++ }
++
++ /* Wait for Target to respond. */
++ wait_event_interruptible(arEvent, gpio_data_available);
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ } else {
++ A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
++
++ if (copy_to_user(userdata, &gpio_reg_results.value,
++ sizeof(gpio_reg_results.value)))
++ {
++ ret = -EFAULT;
++ }
++ }
++ up(&ar->arSem);
++ break;
++ }
++ case AR6000_XIOCTL_GPIO_REGISTER_SET:
++ {
++ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ if (copy_from_user(&gpio_register_cmd, userdata,
++ sizeof(gpio_register_cmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = ar6000_gpio_register_set(dev,
++ gpio_register_cmd.gpioreg_id,
++ gpio_register_cmd.value);
++ if (ret != A_OK) {
++ ret = EIO;
++ }
++
++ /* Wait for acknowledgement from Target */
++ wait_event_interruptible(arEvent, gpio_ack_received);
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ }
++ }
++ up(&ar->arSem);
++ break;
++ }
++ case AR6000_XIOCTL_GPIO_REGISTER_GET:
++ {
++ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ if (copy_from_user(&gpio_register_cmd, userdata,
++ sizeof(gpio_register_cmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
++ if (ret != A_OK) {
++ up(&ar->arSem);
++ return -EIO;
++ }
++
++ /* Wait for Target to respond. */
++ wait_event_interruptible(arEvent, gpio_data_available);
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ } else {
++ A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
++ if (copy_to_user(userdata, &gpio_reg_results,
++ sizeof(gpio_reg_results)))
++ {
++ ret = -EFAULT;
++ }
++ }
++ }
++ up(&ar->arSem);
++ break;
++ }
++ case AR6000_XIOCTL_GPIO_INTR_ACK:
++ {
++ struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ if (copy_from_user(&gpio_intr_ack_cmd, userdata,
++ sizeof(gpio_intr_ack_cmd)))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
++ if (ret != A_OK) {
++ ret = EIO;
++ }
++ }
++ up(&ar->arSem);
++ break;
++ }
++ case AR6000_XIOCTL_GPIO_INTR_WAIT:
++ {
++ /* Wait for Target to report an interrupt. */
++ dev_hold(dev);
++ rtnl_unlock();
++ wait_event_interruptible(arEvent, gpio_intr_available);
++ rtnl_lock();
++ dev_put(dev);
++
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ } else {
++ if (copy_to_user(userdata, &gpio_intr_results,
++ sizeof(gpio_intr_results)))
++ {
++ ret = -EFAULT;
++ }
++ }
++ break;
++ }
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++ case AR6000_XIOCTL_SET_ADHOC_BSSID:
++ {
++ WMI_SET_ADHOC_BSSID_CMD adhocBssid;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&adhocBssid, userdata,
++ sizeof(adhocBssid)))
++ {
++ ret = -EFAULT;
++ } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
++ AR6000_ETH_ADDR_LEN) == 0)
++ {
++ ret = -EFAULT;
++ } else {
++
++ A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
++ }
++ break;
++ }
++
++ case AR6000_XIOCTL_SET_OPT_MODE:
++ {
++ WMI_SET_OPT_MODE_CMD optModeCmd;
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&optModeCmd, userdata,
++ sizeof(optModeCmd)))
++ {
++ ret = -EFAULT;
++ } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
++ ret = -EFAULT;
++
++ } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
++ != A_OK)
++ {
++ ret = -EIO;
++ }
++ break;
++ }
++
++ case AR6000_XIOCTL_OPT_SEND_FRAME:
++ {
++ WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
++ A_UINT8 data[MAX_OPT_DATA_LEN];
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&optTxFrmCmd, userdata,
++ sizeof(optTxFrmCmd)))
++ {
++ ret = -EFAULT;
++ } else if (copy_from_user(data,
++ optTxFrmCmd.optIEData,
++ optTxFrmCmd.optIEDataLen))
++ {
++ ret = -EFAULT;
++ } else {
++ ret = wmi_opt_tx_frame_cmd(ar->arWmi,
++ optTxFrmCmd.frmType,
++ optTxFrmCmd.dstAddr,
++ optTxFrmCmd.bssid,
++ optTxFrmCmd.optIEDataLen,
++ data);
++ }
++
++ break;
++ }
++
++ case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL:
++ {
++ WMI_BEACON_INT_CMD bIntvlCmd;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&bIntvlCmd, userdata,
++ sizeof(bIntvlCmd)))
++ {
++ ret = -EFAULT;
++ } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
++ != A_OK)
++ {
++ ret = -EIO;
++ }
++ break;
++ }
++ case IEEE80211_IOCTL_SETAUTHALG:
++ {
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ieee80211req_authalg req;
++
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ } else if (copy_from_user(&req, userdata,
++ sizeof(struct ieee80211req_authalg)))
++ {
++ ret = -EFAULT;
++ } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) {
++ ar->arDot11AuthMode = OPEN_AUTH;
++ ar->arPairwiseCrypto = NONE_CRYPT;
++ ar->arGroupCrypto = NONE_CRYPT;
++ } else if (req.auth_alg == AUTH_ALG_LEAP) {
++ ar->arDot11AuthMode = LEAP_AUTH;
++ } else {
++ ret = -EIO;
++ }
++ break;
++ }
++
++ case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
++ ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
++ break;
++
++ case AR6000_XIOCTL_SET_MAX_SP:
++ ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
++ break;
++
++ case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
++ ret = ar6000_ioctl_get_roam_tbl(dev, rq);
++ break;
++ case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
++ ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
++ break;
++ case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
++ ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
++ break;
++ case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
++ ret = ar6000_ioctl_get_power_mode(dev, rq);
++ break;
++ case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
++ get_user(ar->arWlanState, (unsigned int *)userdata);
++ if (ar->arWmiReady == FALSE) {
++ ret = -EIO;
++ break;
++ }
++
++ if (ar->arWlanState == WLAN_ENABLED) {
++ /* Enable foreground scanning */
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
++ scParams.fg_end_period,
++ scParams.bg_period,
++ scParams.act_chdwell_time,
++ scParams.pas_chdwell_time,
++ scParams.shortScanRatio) != A_OK)
++ {
++ ret = -EIO;
++ }
++ if (ar->arSsidLen) {
++ if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
++ ar->arDot11AuthMode, ar->arAuthMode,
++ ar->arPairwiseCrypto,
++ ar->arPairwiseCryptoLen,
++ ar->arGroupCrypto, ar->arGroupCryptoLen,
++ ar->arSsidLen, ar->arSsid,
++ ar->arReqBssid, ar->arChannelHint) != A_OK)
++ {
++ ret = -EIO;
++ }
++ else
++ {
++ ar->arConnectPending = TRUE;
++ }
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ } else {
++ /* Disconnect from the AP and disable foreground scanning */
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
++ wmi_disconnect_cmd(ar->arWmi);
++ }
++ if (wmi_scanparams_cmd(ar->arWmi, 65535, 0, 0, 0, 0, 0) != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ break;
++ case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
++ ret = ar6000_ioctl_get_roam_data(dev, rq);
++ break;
++ default:
++ ret = -EOPNOTSUPP;
++ }
++ return ret;
++}
++
++void
++ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++
++ ar->arBitRate = rateKbps;
++ wake_up(&arEvent);
++}
++
++void
++ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++
++ ar->arTxPwr = txPwr;
++ wake_up(&arEvent);
++}
++
++static int
++ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ if (cmd.numChannels > 1) {
++ cmdp = A_MALLOC(128);
++ if (copy_from_user(cmdp, rq->ifr_data,
++ sizeof (*cmdp) +
++ ((cmd.numChannels - 1) * sizeof(A_UINT16))))
++ {
++ kfree(cmdp);
++ return -EFAULT;
++ }
++ } else {
++ cmdp = &cmd;
++ }
++
++ if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
++ ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
++ {
++ ret = -EINVAL;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (!ret &&
++ (wmi_set_channelParams_cmd(ar->arWmi, cmdp->phyMode, cmdp->numChannels,
++ cmdp->channelList) != A_OK))
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ if (cmd.numChannels > 1) {
++ kfree(cmdp);
++ }
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_set_link_threshold(struct net_device *dev, struct ifreq *rq)
++{
++
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if( wmi_set_link_threshold_params(ar->arWmi,
++ cmd.highThreshold_upperVal,
++ cmd.highThreshold_lowerVal,
++ cmd.lowThreshold_upperVal,
++ cmd.lowThreshold_lowerVal,
++ cmd.pollTime) != A_OK ) {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return ret;
++}
++
++void
++ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++
++ A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
++ ar->arNumChannels = numChan;
++
++ wake_up(&arEvent);
++}
++
++static int
++ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_PROBED_SSID_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
++ cmd.ssid) != A_OK)
++ {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_ADD_BAD_AP_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
++ /*
++ * This is a delete badAP.
++ */
++ if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
++ ret = -EIO;
++ }
++ } else {
++ if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
++ ret = -EIO;
++ }
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_CREATE_PSTREAM_CMD cmd;
++ A_STATUS ret;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ cmd.rxQueueNum = 0xFF;
++ ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
++ if (ret == A_OK)
++ ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ switch (ret) {
++ case A_OK:
++ return 0;
++ case A_EBUSY :
++ return -EBUSY;
++ case A_NO_MEMORY:
++ return -ENOMEM;
++ case A_EINVAL:
++ default:
++ return -EFAULT;
++ }
++}
++
++static int
++ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_DELETE_PSTREAM_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.txQueueNumber,
++ cmd.rxQueueNumber, cmd.trafficDirection);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ switch (ret) {
++ case A_OK:
++ return 0;
++ case A_EBUSY :
++ return -EBUSY;
++ case A_NO_MEMORY:
++ return -ENOMEM;
++ case A_EINVAL:
++ default:
++ return -EFAULT;
++ }
++}
++
++static int
++ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ar6000_queuereq qreq;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&qreq, rq->ifr_data,
++ sizeof(struct ar6000_queuereq)))
++ return -EFAULT;
++
++ qreq.queueNumber = wmi_get_mapped_qos_queue(ar->arWmi,
++ qreq.trafficDirection,
++ qreq.trafficClass);
++
++ if (copy_to_user(rq->ifr_data, &qreq,
++ sizeof(struct ar6000_queuereq)))
++ {
++ ret = -EFAULT;
++ }
++ return ret;
++}
++
++#ifdef HTC_RAW_INTERFACE
++#define RAW_HTC_READ_BUFFERS_NUM 16
++#define RAW_HTC_WRITE_BUFFERS_NUM 16
++typedef struct {
++ int currPtr;
++ int length;
++ unsigned char data[AR6000_BUFFER_SIZE];
++} raw_htc_buffer;
++
++static struct semaphore raw_htc_read_sem[HTC_MAILBOX_NUM_MAX];
++static struct semaphore raw_htc_write_sem[HTC_MAILBOX_NUM_MAX];
++static wait_queue_head_t raw_htc_read_queue[HTC_MAILBOX_NUM_MAX];
++static wait_queue_head_t raw_htc_write_queue[HTC_MAILBOX_NUM_MAX];
++static raw_htc_buffer raw_htc_read_buffer[HTC_MAILBOX_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
++static raw_htc_buffer raw_htc_write_buffer[HTC_MAILBOX_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
++static A_BOOL write_buffer_available[HTC_MAILBOX_NUM_MAX];
++static A_BOOL read_buffer_available[HTC_MAILBOX_NUM_MAX];
++
++static void
++ar6000_htc_raw_read_cb(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ HTC_TARGET *target;
++ raw_htc_buffer *busy;
++
++ target = (HTC_TARGET *)arg;
++ A_ASSERT(target != NULL);
++ busy = (raw_htc_buffer *)evInfo->cookie;
++ A_ASSERT(busy != NULL);
++
++ if (evInfo->status == A_ECANCELED) {
++ /*
++ * HTC provides A_ECANCELED status when it doesn't want to be refilled
++ * (probably due to a shutdown)
++ */
++ memset(busy, 0, sizeof(raw_htc_buffer));
++ return;
++ }
++
++#ifdef CF
++ if (down_trylock(&raw_htc_read_sem[endPointId])) {
++#else
++ if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++#endif /* CF */
++ AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
++ }
++
++ A_ASSERT(evId == HTC_BUFFER_RECEIVED);
++ A_ASSERT((evInfo->status != A_OK) ||
++ (evInfo->buffer == (busy->data + HTC_HEADER_LEN)));
++
++ busy->length = evInfo->actualLength + HTC_HEADER_LEN;
++ busy->currPtr = HTC_HEADER_LEN;
++ read_buffer_available[endPointId] = TRUE;
++ up(&raw_htc_read_sem[endPointId]);
++
++ /* Signal the waiting process */
++ AR_DEBUG2_PRINTF("Waking up the endpoint(%d) read process\n", endPointId);
++ wake_up_interruptible(&raw_htc_read_queue[endPointId]);
++}
++
++static void
++ar6000_htc_raw_write_cb(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID endPointId,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ HTC_TARGET *target;
++ raw_htc_buffer *free;
++
++ target = (HTC_TARGET *)arg;
++ A_ASSERT(target != NULL);
++ free = (raw_htc_buffer *)evInfo->cookie;
++ A_ASSERT(free != NULL);
++
++ if (evInfo->status == A_ECANCELED) {
++ /*
++ * HTC provides A_ECANCELED status when it doesn't want to be refilled
++ * (probably due to a shutdown)
++ */
++ memset(free, 0, sizeof(raw_htc_buffer));
++ return;
++ }
++
++#ifdef CF
++ if (down_trylock(&raw_htc_write_sem[endPointId])) {
++#else
++ if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++#endif /* CF */
++ AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
++ }
++
++ A_ASSERT(evId == HTC_BUFFER_SENT);
++ A_ASSERT(evInfo->buffer == (free->data + HTC_HEADER_LEN));
++
++ free->length = 0;
++ write_buffer_available[endPointId] = TRUE;
++ up(&raw_htc_write_sem[endPointId]);
++
++ /* Signal the waiting process */
++ AR_DEBUG2_PRINTF("Waking up the endpoint(%d) write process\n", endPointId);
++ wake_up_interruptible(&raw_htc_write_queue[endPointId]);
++}
++
++static void
++ar6000_htc_raw_unread_cb(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ HTC_TARGET *target;
++
++ target = (HTC_TARGET *)arg;
++ A_ASSERT(target != NULL);
++
++ AR_DEBUG_PRINTF("Not implemented\n");
++}
++
++static int
++ar6000_htc_raw_open(HTC_TARGET *htcTarget)
++{
++ A_STATUS status;
++ int count1, count2;
++ raw_htc_buffer *buffer;
++
++ for (count1 = 0; count1 < HTC_MAILBOX_NUM_MAX; count1 ++) {
++ /* Initialize the data structures */
++ init_MUTEX(&raw_htc_read_sem[count1]);
++ init_MUTEX(&raw_htc_write_sem[count1]);
++ init_waitqueue_head(&raw_htc_read_queue[count1]);
++ init_waitqueue_head(&raw_htc_write_queue[count1]);
++
++ /* Register the event handlers */
++ if ((status = HTCEventReg(htcTarget, count1, HTC_BUFFER_RECEIVED,
++ ar6000_htc_raw_read_cb, htcTarget)) != A_OK)
++ {
++ BMIInit();
++ return -EIO;
++ }
++ if ((status = HTCEventReg(htcTarget, count1, HTC_DATA_AVAILABLE,
++ ar6000_htc_raw_unread_cb, htcTarget)) != A_OK)
++ {
++ BMIInit();
++ return -EIO;
++ }
++ if ((status = HTCEventReg(htcTarget, count1, HTC_BUFFER_SENT,
++ ar6000_htc_raw_write_cb, htcTarget)) != A_OK)
++ {
++ BMIInit();
++ return -EIO;
++ }
++
++ for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
++ /* Initialize the receive buffers */
++ buffer = &raw_htc_write_buffer[count1][count2];
++ memset(buffer, 0, sizeof(raw_htc_buffer));
++ buffer = &raw_htc_read_buffer[count1][count2];
++ memset(buffer, 0, sizeof(raw_htc_buffer));
++
++ /* Queue buffers to HTC for receive */
++ if ((status = HTCBufferReceive(htcTarget, count1, buffer->data,
++ AR6000_BUFFER_SIZE, buffer)) != A_OK)
++ {
++ BMIInit();
++ return -EIO;
++ }
++ }
++
++ for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
++ /* Initialize the receive buffers */
++ buffer = &raw_htc_write_buffer[count1][count2];
++ memset(buffer, 0, sizeof(raw_htc_buffer));
++ }
++
++ read_buffer_available[count1] = FALSE;
++ write_buffer_available[count1] = TRUE;
++ }
++
++ /* Start the HTC component */
++ if ((status = HTCStart(htcTarget)) != A_OK) {
++ BMIInit();
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int
++ar6000_htc_raw_close(HTC_TARGET *htcTarget)
++{
++ int count;
++ A_STATUS status;
++
++ /* Stop the HTC */
++ HTCStop(htcTarget);
++
++ /* Unregister the event handlers */
++ for (count = 0; count < HTC_MAILBOX_NUM_MAX; count ++) {
++ status = HTCEventReg(htcTarget, count, HTC_BUFFER_RECEIVED,
++ NULL, htcTarget);
++
++ status = HTCEventReg(htcTarget, count, HTC_DATA_AVAILABLE,
++ NULL, htcTarget);
++
++ status = HTCEventReg(htcTarget, count, HTC_BUFFER_SENT,
++ NULL, htcTarget);
++ }
++
++ /* Initialize the BMI component */
++ BMIInit();
++
++ return 0;
++}
++
++raw_htc_buffer *
++get_filled_buffer(HTC_ENDPOINT_ID endPointId)
++{
++ int count;
++ raw_htc_buffer *busy;
++
++ /* Check for data */
++ for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
++ busy = &raw_htc_read_buffer[endPointId][count];
++ if (busy->length) {
++ break;
++ }
++ }
++ if (busy->length) {
++ read_buffer_available[endPointId] = TRUE;
++ } else {
++ read_buffer_available[endPointId] = FALSE;
++ }
++
++ return busy;
++}
++
++static ssize_t
++ar6000_htc_raw_read(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID endPointId,
++ char __user *buffer, size_t length)
++{
++ int readPtr;
++ raw_htc_buffer *busy;
++
++ if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++ return -ERESTARTSYS;
++ }
++
++ busy = get_filled_buffer(endPointId);
++ while (!read_buffer_available[endPointId]) {
++ up(&raw_htc_read_sem[endPointId]);
++
++ /* Wait for the data */
++ AR_DEBUG2_PRINTF("Sleeping endpoint(%d) read process\n", endPointId);
++ if (wait_event_interruptible(raw_htc_read_queue[endPointId],
++ read_buffer_available[endPointId]))
++ {
++ return -EINTR;
++ }
++ if (down_interruptible(&raw_htc_read_sem[endPointId])) {
++ return -ERESTARTSYS;
++ }
++ busy = get_filled_buffer(endPointId);
++ }
++
++ /* Read the data */
++ readPtr = busy->currPtr;
++ if (length > busy->length - HTC_HEADER_LEN) {
++ length = busy->length - HTC_HEADER_LEN;
++ }
++ if (copy_to_user(buffer, &busy->data[readPtr], length)) {
++ up(&raw_htc_read_sem[endPointId]);
++ return -EFAULT;
++ }
++
++ busy->currPtr += length;
++ if (busy->currPtr == busy->length)
++ {
++ /* Packet has been completely read. Queue it with HTC */
++ memset(busy, 0, sizeof(raw_htc_buffer));
++ HTCBufferReceive(htcTarget, endPointId, busy->data,
++ AR6000_BUFFER_SIZE, busy);
++ }
++ read_buffer_available[endPointId] = FALSE;
++ up(&raw_htc_read_sem[endPointId]);
++
++ return length;
++}
++
++raw_htc_buffer *
++get_free_buffer(HTC_ENDPOINT_ID endPointId)
++{
++ int count;
++ raw_htc_buffer *free;
++
++ free = NULL;
++ for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
++ free = &raw_htc_write_buffer[endPointId][count];
++ if (free->length == 0) {
++ break;
++ }
++ }
++ if (!free->length) {
++ write_buffer_available[endPointId] = TRUE;
++ } else {
++ write_buffer_available[endPointId] = FALSE;
++ }
++
++ return free;
++}
++
++static ssize_t
++ar6000_htc_raw_write(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID endPointId,
++ char __user *buffer, size_t length)
++{
++ int writePtr;
++ raw_htc_buffer *free;
++
++ if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++ return -ERESTARTSYS;
++ }
++
++ /* Search for a free buffer */
++ free = get_free_buffer(endPointId);
++
++ /* Check if there is space to write else wait */
++ while (!write_buffer_available[endPointId]) {
++ up(&raw_htc_write_sem[endPointId]);
++
++ /* Wait for buffer to become free */
++ AR_DEBUG2_PRINTF("Sleeping endpoint(%d) write process\n", endPointId);
++ if (wait_event_interruptible(raw_htc_write_queue[endPointId],
++ write_buffer_available[endPointId]))
++ {
++ return -EINTR;
++ }
++ if (down_interruptible(&raw_htc_write_sem[endPointId])) {
++ return -ERESTARTSYS;
++ }
++ free = get_free_buffer(endPointId);
++ }
++
++ /* Send the data */
++ writePtr = HTC_HEADER_LEN;
++ if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) {
++ length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN;
++ }
++
++ if (copy_from_user(&free->data[writePtr], buffer, length)) {
++ up(&raw_htc_read_sem[endPointId]);
++ return -EFAULT;
++ }
++
++ free->length = length;
++ HTCBufferSend(htcTarget, endPointId, &free->data[writePtr], length, free);
++ write_buffer_available[endPointId] = FALSE;
++ up(&raw_htc_write_sem[endPointId]);
++
++ return length;
++}
++#endif /* HTC_RAW_INTERFACE */
++
++/*
++ * As soon as the DataSet Server application waits for a request,
++ * we know that the server is operational, and we try to process
++ * requests. If the Target sends any requests before the server
++ * has started, we reject the request. The model we use is that
++ * once started, the server must continue to service requests as
++ * long as they may arrive, and the server ought to be started
++ * before WMI is started (before the network interface is brought
++ * up.
++ */
++static A_BOOL dset_server_alive;
++
++#if CONFIG_HOST_DSET_SUPPORT
++/*
++ * For now, we allow for just one outstanding (unhandled) request
++ * at a time. The current Target doesn't need any more than that.
++ * If we ever need to handle many simultaneous requests, this
++ * pending_dset_request and pending_dset_request_valid mechanism
++ * can get more complicated. The use of dset_request_lock is
++ * also very simple; it assumes that a single well-behaved thread
++ * serves all requests.
++ */
++static A_BOOL pending_dset_request_valid;
++static dset_request_t pending_dset_request;
++
++static spinlock_t dset_request_lock;
++static DECLARE_WAIT_QUEUE_HEAD(dset_request);
++
++static int
++ar6000_ioctl_wait_dset_req(struct net_device *dev, struct ifreq *rq)
++{
++ int ret = 0;
++
++ dset_server_alive = TRUE;
++
++ /* Wait for a DataSet Request to arrive. */
++ dev_hold(dev);
++ rtnl_unlock();
++ wait_event_interruptible(dset_request, pending_dset_request_valid);
++ rtnl_lock();
++ dev_put(dev);
++
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ } else {
++ if (copy_to_user(rq->ifr_data,
++ &pending_dset_request,
++ sizeof(pending_dset_request))) {
++ ret = -EFAULT;
++ }
++
++ /* pending_dset_request is now available for use */
++ pending_dset_request_valid = FALSE;
++ spin_unlock(&dset_request_lock);
++ }
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_dset_open_reply(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int ret = 0;
++ dset_open_reply_t dset_reply;
++
++ if (copy_from_user(&dset_reply, rq->ifr_data, sizeof(dset_reply))) {
++ ret = -EFAULT;
++ } else {
++ A_ASSERT(dset_reply.cmd == AR6000_XIOCTL_WMI_DSET_OPEN_REPLY);
++ ret = wmi_dset_open_reply(ar->arWmi,
++ dset_reply.status,
++ dset_reply.access_cookie,
++ dset_reply.size,
++ dset_reply.version,
++ dset_reply.targ_handle,
++ dset_reply.targ_reply_fn,
++ dset_reply.targ_reply_arg);
++
++ if (ret == A_NO_MEMORY) {
++ ret = -ENOMEM;
++ } else if (ret == A_ERROR) {
++ ret = -EFAULT;
++ }
++ }
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_dset_data_reply(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int ret = 0;
++ dset_data_reply_t dset_reply;
++
++ if (copy_from_user(&dset_reply, rq->ifr_data, sizeof(dset_reply))) {
++ ret = -EFAULT;
++ } else {
++ A_ASSERT(dset_reply.cmd == AR6000_XIOCTL_WMI_DSET_DATA_REPLY);
++ ret = wmi_dset_data_reply(ar->arWmi,
++ dset_reply.status,
++ dset_reply.buf,
++ dset_reply.length,
++ dset_reply.targ_buf,
++ dset_reply.targ_reply_fn,
++ dset_reply.targ_reply_arg);
++
++ if (ret == A_NO_MEMORY) {
++ ret = -ENOMEM;
++ } else if (ret == A_ERROR) {
++ ret = -EFAULT;
++ }
++ }
++
++ return ret;
++}
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++A_UINT8 ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ A_UINT8 *datap;
++ ATH_MAC_HDR *macHdr;
++ A_UINT32 i, emptMap;
++
++ (*mapNo) = 0;
++ datap = a_netbuf_to_data(skb);
++ macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
++ if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
++ return ENDPOINT3;
++ }
++
++ emptMap = -1;
++ for (i = 0; i < ar->arNodeNum; i ++) {
++ if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
++ (*mapNo) = i + 1;
++ ar->arNodeMap[i].txPending ++;
++ return ar->arNodeMap[i].epId;
++ }
++
++ if ((emptMap == -1) && !ar->arNodeMap[i].txPending) {
++ emptMap = i;
++ }
++ }
++
++ if (emptMap == -1) {
++ emptMap = ar->arNodeNum;
++ ar->arNodeNum ++;
++ A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
++ }
++
++ A_MEMCPY(ar->arNodeMap[emptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
++
++ for (i = ENDPOINT2; i <= ENDPOINT4; i ++) {
++ if (!ar->arTxPending[i]) {
++ ar->arNodeMap[emptMap].epId = i;
++ break;
++ }
++ }
++
++ if (i > ENDPOINT4) {
++ ar->arNodeMap[emptMap].epId = ar->arNexEpId;
++ ar->arNexEpId ++;
++ if (ar->arNexEpId > ENDPOINT4) {
++ ar->arNexEpId = ENDPOINT2;
++ }
++ }
++
++ (*mapNo) = emptMap + 1;
++ ar->arNodeMap[emptMap].txPending ++;
++
++ return ar->arNodeMap[ar->arNodeNum - 1].epId;
++}
++
++static int
++ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ HTC_ENDPOINT_ID endPointId;
++ A_UINT32 mapNo = 0;
++ struct iphdr *ipHdr;
++ struct sk_buff *newbuf;
++ int len;
++ struct ar_cookie *cookie;
++
++ if (ar->arWmiReady == FALSE && bypasswmi == 0) {
++ a_netbuf_free(skb);
++ return 0;
++ }
++
++#ifdef BLOCK_TX_PATH_FLAG
++ if (blocktx) {
++ a_netbuf_free(skb);
++ return 0;
++ }
++#endif /* BLOCK_TX_PATH_FLAG */
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ /* If all data queues are full, notify upper layer to stop. */
++ if (ar->arTotalTxDataPending >= (txFlowCtrlThresh[ar->arNumDataEndPts])) {
++ netif_stop_queue(ar->arNetDev);
++ }
++
++ AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
++ (A_UINT32)skb, (A_UINT32)a_netbuf_to_data(skb),
++ a_netbuf_to_len(skb));
++
++ if (ar->arWmiEnabled == TRUE) {
++ if (a_netbuf_headroom(skb) < dev->hard_header_len) {
++ /*
++ * We really should have gotten enough headroom but sometimes
++ * we still get packets with not enough headroom. Copy the packet.
++ */
++ len = a_netbuf_to_len(skb);
++ newbuf = a_netbuf_alloc(len);
++ if (newbuf == NULL) {
++ a_netbuf_free(skb);
++ AR6000_STAT_INC(ar, tx_dropped);
++ AR6000_STAT_INC(ar, tx_aborted_errors);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return A_NO_MEMORY;
++ }
++ a_netbuf_put(newbuf, len);
++ A_MEMCPY(a_netbuf_to_data(newbuf), a_netbuf_to_data(skb), len);
++ a_netbuf_free(skb);
++ skb = newbuf;
++ }
++ if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
++ AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n");
++ AR6000_STAT_INC(ar, tx_dropped);
++ AR6000_STAT_INC(ar, tx_aborted_errors);
++ a_netbuf_free(skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return 0;
++ }
++
++ if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) {
++ AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n");
++ AR6000_STAT_INC(ar, tx_dropped);
++ AR6000_STAT_INC(ar, tx_aborted_errors);
++ a_netbuf_free(skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return 0;
++ }
++
++ if ((ar->arNetworkType == ADHOC_NETWORK) &&
++ ar->arIbssPsEnable && ar->arConnected)
++ {
++ endPointId = ar6000_ibss_map_epid(skb, dev, &mapNo);
++ } else {
++ /* Extract the end point information */
++ endPointId = wmi_get_endpoint(ar->arWmi,
++ wmi_implicit_create_pstream(ar->arWmi, skb, UPLINK_TRAFFIC));
++ }
++ } else {
++ /*
++ * the endpoint is directly based on the TOS field in the IP
++ * header
++ */
++ ipHdr = a_netbuf_to_data(skb) + sizeof(ATH_MAC_HDR);
++ endPointId = ((ipHdr->tos >> 1) & 0x03);
++ }
++
++ AR_DEBUG2_PRINTF("ar6000_data_tx - ep=%d skb=0x%x, data=0x%x, len=0x%x\n",
++ endPointId, (A_UINT32)skb, (A_UINT32)a_netbuf_to_data(skb),
++ a_netbuf_to_len(skb));
++
++#ifdef DEBUG
++ if (debugdriver >= 3) {
++ u_char *ch;
++
++ for (ch = a_netbuf_to_data(skb);
++ (A_UINT32)ch < ((A_UINT32)a_netbuf_to_data(skb) +
++ a_netbuf_to_len(skb)); ch++)
++ {
++ AR_DEBUG_PRINTF("%2.2x ", *ch);
++ }
++ AR_DEBUG_PRINTF("\n");
++ }
++#endif /* DEBUG */
++ ar->arTxPending[endPointId]++;
++ ar->arTotalTxDataPending++;
++
++ /* If the particular data queue is full, silently drop the pkt. */
++ if (ar->arTxPending[endPointId] > MAX_ALLOWED_TXQ_DEPTH) {
++ ar->arTxPending[endPointId]--;
++ ar->arTotalTxDataPending--;
++ a_netbuf_free(skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return 0;
++ }
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ cookie = ar6000_alloc_cookie(ar);
++ if (cookie == NULL) {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar->arTxPending[endPointId]--;
++ ar->arTotalTxDataPending--;
++ a_netbuf_free(skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return 0;
++ }
++
++ cookie->arc_bp[0] = (A_UINT32)skb;
++ cookie->arc_bp[1] = mapNo;
++
++ if (HTCBufferSend(ar->arHtcTarget, endPointId, a_netbuf_to_data(skb),
++ a_netbuf_to_len(skb), cookie) != A_OK)
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar->arTxPending[endPointId]--;
++ ar->arTotalTxDataPending--;
++ AR_DEBUG_PRINTF("Dropping the frame\n");
++ ar6000_free_cookie(ar, cookie);
++ a_netbuf_free(skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++
++ return 0;
++}
++
++static void
++ar6000_tx_complete(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)arg;
++ void *cookie = (void *)evInfo->cookie;
++ struct sk_buff *skb = NULL;
++ A_UINT32 mapNo = 0;
++
++ if (ar->arWmiReady == TRUE || bypasswmi != 0)
++ {
++ struct ar_cookie * ar_cookie = (struct ar_cookie *)cookie;
++ skb = (struct sk_buff *)ar_cookie->arc_bp[0];
++ mapNo = ar_cookie->arc_bp[1];
++ } else {
++ skb = (struct sk_buff *)cookie;
++ AR_DEBUG_PRINTF("%s() WARNING Wierd cookie\n", __func__);
++ }
++
++ A_ASSERT(skb);
++ A_ASSERT(evId == HTC_BUFFER_SENT);
++ A_ASSERT(evInfo->buffer == a_netbuf_to_data(skb));
++ if (evInfo->status != A_ECANCELED) {
++ A_ASSERT(evInfo->actualLength == a_netbuf_to_len(skb));
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ ar->arTxPending[eid]--;
++ if (eid != WMI_CONTROL_MBOX || bypasswmi) {
++ ar->arTotalTxDataPending--;
++ }
++ AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x mbox=%d ",
++ (A_UINT32)skb, (A_UINT32)evInfo->buffer,
++ evInfo->actualLength,
++ eid);
++
++ if ((eid == WMI_CONTROL_MBOX) &&
++ (ar->arTxPending[WMI_CONTROL_MBOX] == 0))
++ {
++ wake_up(&arEvent);
++ }
++
++
++ if (evInfo->status != A_OK) {
++ AR_DEBUG_PRINTF("%s() -TX ERROR\n", __func__);
++ AR6000_STAT_INC(ar, tx_errors);
++ } else {
++ AR_DEBUG2_PRINTF("OK\n");
++ AR6000_STAT_INC(ar, tx_packets);
++ ar->arNetStats.tx_bytes += a_netbuf_to_len(skb);
++ }
++
++ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
++ && (eid != WMI_CONTROL_MBOX) && mapNo)
++ {
++ mapNo --;
++ ar->arNodeMap[mapNo].txPending --;
++
++ if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
++ A_UINT32 i;
++ for (i = ar->arNodeNum; i > 0; i --) {
++ if (!ar->arNodeMap[i - 1].txPending) {
++ A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
++ ar->arNodeNum --;
++ } else {
++ break;
++ }
++ }
++ }
++ }
++
++ /* Freeing a cookie should not be contingent on either of */
++ /* these flags, just if we have a cookie or not. */
++ /* Can we even get here without a cookie? Fix later. */
++ if (ar->arWmiReady == TRUE || (bypasswmi))
++ {
++ ar6000_free_cookie(ar, cookie);
++ }
++
++ a_netbuf_free(skb);
++
++ if ((ar->arConnected == TRUE) || (bypasswmi)) {
++ netif_wake_queue(ar->arNetDev);
++ }
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++}
++
++/*
++ * Receive event handler. This is called by HTC when a packet is received
++ */
++int pktcount;
++static void
++ar6000_rx(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)arg;
++ struct sk_buff *skb = (struct sk_buff *)evInfo->cookie;
++ int minHdrLen;
++
++ A_ASSERT(evId == HTC_BUFFER_RECEIVED);
++ A_ASSERT((evInfo->status != A_OK) || (evInfo->buffer == (a_netbuf_to_data(skb) + HTC_HEADER_LEN)));
++
++#ifdef DEBUG
++ AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x ep=%d, skb=0x%x, data=0x%x, len=0x%x ",
++ (A_UINT32)ar, eid, (A_UINT32)skb, (A_UINT32)evInfo->buffer,
++ evInfo->actualLength);
++ if (evInfo->status != A_OK) {
++ AR_DEBUG2_PRINTF("ERR\n");
++ } else {
++ AR_DEBUG2_PRINTF("OK\n");
++ }
++#endif /* DEBUG */
++
++ ar->arRxBuffers[eid]--;
++ AR6000_STAT_INC(ar, rx_packets);
++ ar->arNetStats.rx_bytes += evInfo->actualLength;
++
++ a_netbuf_put(skb, evInfo->actualLength + HTC_HEADER_LEN);
++
++ a_netbuf_pull(skb, HTC_HEADER_LEN);
++
++#ifdef DEBUG
++ if (debugdriver >= 2) {
++ u_char *ch;
++
++ for (ch = a_netbuf_to_data(skb);
++ (A_UINT32)ch < ((A_UINT32)a_netbuf_to_data(skb) +
++ a_netbuf_to_len(skb)); ch++)
++ {
++ AR_DEBUG_PRINTF("%2.2x ", *ch);
++ }
++ AR_DEBUG_PRINTF("\n");
++ }
++#endif /* DEBUG */
++
++ if (evInfo->status != A_OK) {
++ AR6000_STAT_INC(ar, rx_errors);
++ a_netbuf_free(skb);
++ } else if (ar->arWmiEnabled == TRUE) {
++ if (eid == WMI_CONTROL_MBOX) {
++ /*
++ * this is a wmi control msg
++ */
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ wmi_control_rx(ar->arWmi, skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ } else {
++ WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)a_netbuf_to_data(skb);
++ if (WMI_DATA_HDR_IS_MSG_TYPE(dhdr, CNTL_MSGTYPE)) {
++ /*
++ * this is a wmi control msg
++ */
++ /* strip off WMI hdr */
++ wmi_data_hdr_remove(ar->arWmi, skb);
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ wmi_control_rx(ar->arWmi, skb);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ } else {
++ /*
++ * this is a wmi data packet
++ */
++ minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
++ sizeof(ATH_LLC_SNAP_HDR);
++
++ if ((evInfo->actualLength < minHdrLen) ||
++ (evInfo->actualLength > AR6000_BUFFER_SIZE))
++ {
++ /*
++ * packet is too short or too long
++ */
++ AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n");
++ AR6000_STAT_INC(ar, rx_errors);
++ AR6000_STAT_INC(ar, rx_length_errors);
++ a_netbuf_free(skb);
++ } else {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ wmi_implicit_create_pstream(ar->arWmi, skb, DNLINK_TRAFFIC);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++#if 0
++ /* Access RSSI values here */
++ AR_DEBUG_PRINTF("RSSI %d\n",
++ ((WMI_DATA_HDR *) a_netbuf_to_data(skb))->rssi);
++#endif
++ wmi_data_hdr_remove(ar->arWmi, skb);
++ wmi_dot3_2_dix(ar->arWmi, skb);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++ /*
++ * extra push and memcpy, for eth_type_trans() of 2.4 kernel
++ * will pull out hard_header_len bytes of the skb.
++ */
++ a_netbuf_push(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
++ A_MEMCPY(a_netbuf_to_data(skb), a_netbuf_to_data(skb) + sizeof(WMI_DATA_HDR) +
++ sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
++#endif
++ if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
++ {
++ skb->dev = ar->arNetDev;
++ skb->protocol = eth_type_trans(skb, ar->arNetDev);
++ netif_rx(skb);
++ }
++ else
++ {
++ a_netbuf_free(skb);
++ }
++ }
++ }
++ }
++ } else {
++ if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
++ {
++ skb->dev = ar->arNetDev;
++ skb->protocol = eth_type_trans(skb, ar->arNetDev);
++ netif_rx(skb);
++ }
++ else
++ {
++ a_netbuf_free(skb);
++ }
++ }
++
++ if (evInfo->status != A_ECANCELED) {
++ /*
++ * HTC provides A_ECANCELED status when it doesn't want to be refilled
++ * (probably due to a shutdown)
++ */
++ ar6000_rx_refill(htcTarget, eid, HTC_DATA_AVAILABLE, NULL, ar);
++ }
++}
++
++static void
++ar6000_rx_refill(HTC_TARGET *htcTarget, HTC_ENDPOINT_ID eid,
++ HTC_EVENT_ID evId, HTC_EVENT_INFO *evInfo, void *arg)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)arg;
++ void *osBuf;
++ int arRxBuffers;
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ arRxBuffers = ar->arRxBuffers[eid];
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
++ AR6000_MAX_RX_BUFFERS - arRxBuffers, eid);
++ while (arRxBuffers < AR6000_MAX_RX_BUFFERS) {
++ osBuf = a_netbuf_alloc(AR6000_BUFFER_SIZE);
++ HTCBufferReceive(htcTarget, eid, a_netbuf_to_data(osBuf),
++ AR6000_BUFFER_SIZE, osBuf);
++ arRxBuffers++;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ar->arRxBuffers[eid] = arRxBuffers;
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++}
++
++static struct net_device_stats *
++ar6000_get_stats(struct net_device *dev)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ return &ar->arNetStats;
++}
++static struct iw_statistics *
++ar6000_get_iwstats(struct net_device * dev)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ TARGET_STATS *pStats = &ar->arTargetStats;
++ struct iw_statistics * pIwStats = &ar->arIwStats;
++
++ if (ar->arWmiReady == FALSE) {
++ pIwStats->status = 0;
++ pIwStats->qual.qual = 0;
++ pIwStats->qual.level =0;
++ pIwStats->qual.noise = 0;
++ pIwStats->discard.code =0;
++ pIwStats->discard.retries=0;
++ pIwStats->miss.beacon =0;
++ return pIwStats;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ pIwStats->status = 0;
++ return pIwStats;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ ar->statsUpdatePending = TRUE;
++
++ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ pIwStats->status = 0;
++ return pIwStats;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ wait_event_interruptible(arEvent, ar->statsUpdatePending == FALSE);
++
++ if (signal_pending(current)) {
++ pIwStats->status = 0;
++ return pIwStats;
++ }
++ pIwStats->status = 1 ;
++ pIwStats->qual.qual = pStats->cs_aveBeacon_rssi;
++ pIwStats->qual.level =pStats->cs_aveBeacon_rssi + 161; /* noise is -95 dBm */
++ pIwStats->qual.noise = pStats->noise_floor_calibation;
++ pIwStats->discard.code = pStats->rx_decrypt_err;
++ pIwStats->discard.retries = pStats->tx_retry_cnt;
++ pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
++ up(&ar->arSem);
++ return pIwStats;
++}
++void
++ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++ struct net_device *dev = ar->arNetDev;
++
++ ar->arWmiReady = TRUE;
++ wake_up(&arEvent);
++ A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
++ AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
++ dev->dev_addr[0], dev->dev_addr[1],
++ dev->dev_addr[2], dev->dev_addr[3],
++ dev->dev_addr[4], dev->dev_addr[5]);
++
++ ar->arPhyCapability = phyCap;
++}
++
++A_UINT8
++ar6000_iptos_to_userPriority(A_UINT8 *pkt)
++{
++ struct iphdr *ipHdr = (struct iphdr *)pkt;
++ A_UINT8 userPriority;
++
++ /*
++ * IP Tos format :
++ * (Refer Pg 57 WMM-test-plan-v1.2)
++ * IP-TOS - 8bits
++ * : DSCP(6-bits) ECN(2-bits)
++ * : DSCP - P2 P1 P0 X X X
++ * where (P2 P1 P0) form 802.1D
++ */
++ userPriority = ipHdr->tos >> 5;
++ return (userPriority & 0x7);
++}
++
++void
++ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
++ A_UINT16 listenInterval, A_UINT8 beaconIeLen,
++ A_UINT8 assocReqLen, A_UINT8 assocRespLen,
++ A_UINT8 *assocInfo)
++{
++ union iwreq_data wrqu;
++ int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
++ static const char *tag1 = "ASSOCINFO(ReqIEs=";
++ static const char *tag2 = "ASSOCRESPIE=";
++ static const char *beaconIetag = "BEACONIE=";
++ char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + sizeof(tag1)];
++ char *pos;
++
++ A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
++ ar->arBssChannel = channel;
++
++ A_PRINTF("AR6000 connected event on freq %d ", channel);
++ A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
++ " listenInterval=%d, beaconIeLen = %d assocReqLen=%d"
++ " assocRespLen =%d\n",
++ bssid[0], bssid[1], bssid[2],
++ bssid[3], bssid[4], bssid[5],
++ listenInterval,
++ beaconIeLen, assocReqLen, assocRespLen);
++
++ if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
++ AR_DEBUG_PRINTF("\nBeaconIEs= ");
++
++ beacon_ie_pos = 0;
++ A_MEMZERO(buf, sizeof(buf));
++ sprintf(buf, "%s", beaconIetag);
++ pos = buf + 9;
++ for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
++ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++ sprintf(pos, "%2.2x", assocInfo[i]);
++ pos += 2;
++ }
++ AR_DEBUG_PRINTF("\n");
++
++ A_MEMZERO(&wrqu, sizeof(wrqu));
++ wrqu.data.length = strlen(buf);
++ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++ }
++
++ if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
++ {
++ assoc_resp_ie_pos = beaconIeLen + assocReqLen +
++ sizeof(A_UINT16) + /* capinfo*/
++ sizeof(A_UINT16) + /* status Code */
++ sizeof(A_UINT16) ; /* associd */
++ A_MEMZERO(buf, sizeof(buf));
++ sprintf(buf, "%s", tag2);
++ pos = buf + 12;
++ AR_DEBUG_PRINTF("\nAssocRespIEs= ");
++ /*
++ * The Association Response Frame w.o. the WLAN header is delivered to
++ * the host, so skip over to the IEs
++ */
++ for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen; i++)
++ {
++ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++ sprintf(pos, "%2.2x", assocInfo[i]);
++ pos += 2;
++ }
++ AR_DEBUG_PRINTF("\n");
++
++ A_MEMZERO(&wrqu, sizeof(wrqu));
++ wrqu.data.length = strlen(buf);
++ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++ }
++
++ if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
++ /*
++ * assoc Request includes capability and listen interval. Skip these.
++ */
++ assoc_req_ie_pos = beaconIeLen +
++ sizeof(A_UINT16) + /* capinfo*/
++ sizeof(A_UINT16); /* listen interval */
++
++ A_MEMZERO(buf, sizeof(buf));
++ sprintf(buf, "%s", tag1);
++ pos = buf + 17;
++ AR_DEBUG_PRINTF("AssocReqIEs= ");
++ for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen; i++) {
++ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++ sprintf(pos, "%2.2x", assocInfo[i]);
++ pos += 2;;
++ }
++ AR_DEBUG_PRINTF("\n");
++
++ A_MEMZERO(&wrqu, sizeof(wrqu));
++ wrqu.data.length = strlen(buf);
++ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++ }
++
++ if (ar->arTotalTxDataPending < txFlowCtrlThresh[ar->arNumDataEndPts]) {
++ netif_wake_queue(ar->arNetDev);
++ }
++
++ if ((OPEN_AUTH == ar->arDot11AuthMode) &&
++ (NONE_AUTH == ar->arAuthMode) &&
++ (WEP_CRYPT == ar->arPairwiseCrypto))
++ {
++ if (!ar->arConnected) {
++ ar6000_install_static_wep_keys(ar);
++ }
++ }
++
++ ar->arConnected = TRUE;
++ ar->arConnectPending = FALSE;
++
++ A_MEMZERO(&wrqu, sizeof(wrqu));
++ A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
++ wrqu.addr.sa_family = ARPHRD_ETHER;
++ wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
++
++ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
++ A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
++ ar->arNodeNum = 0;
++ ar->arNexEpId = ENDPOINT2;
++ }
++}
++
++void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
++{
++ A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
++ ar->arNumDataEndPts = num;
++}
++
++void
++ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
++ A_UINT8 assocRespLen, A_UINT8 *assocInfo)
++{
++ A_UINT8 i;
++
++ A_PRINTF("AR6000 disconnected");
++ if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
++ A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
++ bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
++ }
++
++ AR_DEBUG_PRINTF("\nAssocResp Frame = %s",
++ assocRespLen ? " " : "NULL");
++ for (i = 0; i < assocRespLen; i++) {
++ if (!(i % 0x10)) {
++ AR_DEBUG_PRINTF("\n");
++ }
++ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
++ }
++ AR_DEBUG_PRINTF("\n");
++ /*
++ * If the event is due to disconnect cmd from the host, only they the target
++ * would stop trying to connect. Under any other condition, target would
++ * keep trying to connect.
++ *
++ */
++ if( reason == DISCONNECT_CMD)
++ {
++ ar->arConnectPending = FALSE;
++ }
++ ar->arConnected = FALSE;
++
++ netif_stop_queue(ar->arNetDev);
++ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
++ ar->arBssChannel = 0;
++}
++
++void
++ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
++{
++ A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
++ ar->arRegCode = regCode;
++}
++
++void
++ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
++{
++ static const char *tag = "PRE-AUTH";
++ char buf[128];
++ union iwreq_data wrqu;
++ int i;
++
++ A_PRINTF("AR6000 Neighbor Report Event\n");
++ for (i=0; i < numAps; info++, i++) {
++ A_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
++ info->bssid[0], info->bssid[1], info->bssid[2],
++ info->bssid[3], info->bssid[4], info->bssid[5]);
++ if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
++ A_PRINTF("preauth-cap");
++ }
++ if (info->bssFlags & WMI_PMKID_VALID_BSS) {
++ A_PRINTF(" pmkid-valid\n");
++ continue; /* we skip bss if the pmkid is already valid */
++ }
++ A_PRINTF("\n");
++ snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
++ tag,
++ info->bssid[0], info->bssid[1], info->bssid[2],
++ info->bssid[3], info->bssid[4], info->bssid[5],
++ i, info->bssFlags);
++ A_MEMZERO(&wrqu, sizeof(wrqu));
++ wrqu.data.length = strlen(buf);
++ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++ }
++}
++
++void
++ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
++{
++ static const char *tag = "MLME-MICHAELMICFAILURE.indication";
++ char buf[128];
++ union iwreq_data wrqu;
++
++ A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
++ keyid, ismcast ? "multi": "uni");
++ snprintf(buf, sizeof(buf), "%s(keyid=%d %scat)", tag, keyid,
++ ismcast ? "multi" : "uni");
++ memset(&wrqu, 0, sizeof(wrqu));
++ wrqu.data.length = strlen(buf);
++ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
++}
++
++void
++ar6000_scanComplete_event(AR_SOFTC_T *ar)
++{
++ A_PRINTF("AR6000 scan complete\n");
++}
++
++void
++ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget)
++{
++ TARGET_STATS *pStats = &ar->arTargetStats;
++ A_UINT8 ac;
++
++ A_PRINTF("AR6000 updating target stats\n");
++ pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets;
++ pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes;
++ pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
++ pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
++ pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
++ pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
++ pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
++ pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
++ pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
++ for(ac = 0; ac < WMM_NUM_AC; ac++)
++ pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
++ pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors;
++ pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt;
++ pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt;
++ pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
++
++ pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets;
++ pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes;
++ pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
++ pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
++ pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
++ pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
++ pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
++ pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
++ pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
++ pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors;
++ pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr;
++ pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
++ pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err;
++ pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
++
++
++ pStats->tkip_local_mic_failure
++ += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
++ pStats->tkip_counter_measures_invoked
++ += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
++ pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
++ pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
++ pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
++ pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
++
++
++ pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
++ pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
++
++ pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt;
++ pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt;
++ pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt;
++ pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt;
++ pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
++ pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec;
++
++ ar->statsUpdatePending = FALSE;
++ wake_up(&arEvent);
++}
++
++
++void
++ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold)
++{
++ A_PRINTF("AR6000 Threshold val = %d \n", newThreshold);
++}
++
++void
++ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
++{
++ char *errString[] = {
++ [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL",
++ [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND",
++ [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
++ [WMI_TARGET_BMISS] "WMI_TARGET_BMISS",
++ [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN"
++ };
++
++ A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
++
++ /* One error is reported at a time, and errorval is a bitmask */
++ if(errorVal & (errorVal - 1))
++ return;
++
++ A_PRINTF("AR6000 Error type = ");
++ switch(errorVal)
++ {
++ case WMI_TARGET_PM_ERR_FAIL:
++ case WMI_TARGET_KEY_NOT_FOUND:
++ case WMI_TARGET_DECRYPTION_ERR:
++ case WMI_TARGET_BMISS:
++ case WMI_PSDISABLE_NODE_JOIN:
++ A_PRINTF("%s\n", errString[errorVal]);
++ break;
++ default:
++ A_PRINTF("INVALID\n");
++ break;
++ }
++
++}
++
++
++void
++ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
++ A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
++{
++ WMM_TSPEC_IE *tspecIe;
++
++ /*
++ * This is the TSPEC IE suggestion from AP.
++ * Suggestion provided by AP under some error
++ * cases, could be helpful for the host app.
++ * Check documentation.
++ */
++ tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
++
++ /*
++ * What do we do, if we get TSPEC rejection? One thought
++ * that comes to mind is implictly delete the pstream...
++ */
++ A_PRINTF("AR6000 CAC notification. "
++ "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
++ ac, cacIndication, statusCode);
++}
++
++#define AR6000_PRINT_BSSID(_pBss) do { \
++ A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
++ (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
++ (_pBss)[4],(_pBss)[5]); \
++} while(0)
++
++void
++ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
++{
++ A_UINT8 i;
++
++ A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
++ pTbl->numEntries, pTbl->roamMode);
++ for (i= 0; i < pTbl->numEntries; i++) {
++ A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
++ pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
++ pTbl->bssRoamInfo[i].bssid[2],
++ pTbl->bssRoamInfo[i].bssid[3],
++ pTbl->bssRoamInfo[i].bssid[4],
++ pTbl->bssRoamInfo[i].bssid[5]);
++ A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
++ " BIAS %d\n",
++ pTbl->bssRoamInfo[i].rssi,
++ pTbl->bssRoamInfo[i].rssidt,
++ pTbl->bssRoamInfo[i].last_rssi,
++ pTbl->bssRoamInfo[i].util,
++ pTbl->bssRoamInfo[i].roam_util,
++ pTbl->bssRoamInfo[i].bias);
++ }
++}
++
++/*
++ * Report the Roaming related data collected on the target
++ */
++void
++ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
++{
++ A_PRINTF("Disconnect Data : BSSID: ");
++ AR6000_PRINT_BSSID(p->disassoc_bssid);
++ A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
++ p->disassoc_bss_rssi,p->disassoc_time,
++ p->no_txrx_time);
++ A_PRINTF("Connect Data: BSSID: ");
++ AR6000_PRINT_BSSID(p->assoc_bssid);
++ A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
++ p->assoc_bss_rssi,p->assoc_time,
++ p->allow_txrx_time);
++ A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\
++ "First Data Tx Time (after Assoc) %d\n",
++ p->last_data_txrx_time, p->first_data_txrx_time);
++}
++
++void
++ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
++{
++ switch (p->roamDataType) {
++ case ROAM_DATA_TIME:
++ ar6000_display_roam_time(&p->u.roamTime);
++ break;
++ default:
++ break;
++ }
++}
++
++static int
++ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_TARGET_ERROR_REPORT_BITMASK cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return (ret==0 ? ret : -EINVAL);
++}
++
++
++static int
++ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ TARGET_STATS *pStats = &ar->arTargetStats;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ ar->statsUpdatePending = TRUE;
++
++ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ wait_event_interruptible(arEvent, ar->statsUpdatePending == FALSE);
++
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ }
++
++ if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
++ ret = -EFAULT;
++ }
++
++ up(&ar->arSem);
++
++ return ret;
++}
++
++static int
++ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_SET_ACCESS_PARAMS_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax,
++ cmd.aifsn) == A_OK)
++ {
++ ret = 0;
++ } else {
++ ret = -EINVAL;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return (ret);
++}
++
++static int
++ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_DISC_TIMEOUT_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
++ {
++ ret = 0;
++ } else {
++ ret = -EINVAL;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return (ret);
++}
++
++static int
++ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_SET_VOICE_PKT_SIZE_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
++ {
++ ret = 0;
++ } else {
++ ret = -EINVAL;
++ }
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return (ret);
++}
++
++static int
++ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_SET_MAX_SP_LEN_CMD cmd;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
++ {
++ ret = 0;
++ } else {
++ ret = -EINVAL;
++ }
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return (ret);
++}
++
++A_STATUS
++ar6000_control_tx(void *devt, void *osbuf, int endPt)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++ A_STATUS status;
++ struct ar_cookie *cookie;
++ WMI_DATA_HDR *dhdr;
++
++ A_ASSERT((endPt == WMI_CONTROL_MBOX) || (endPt == WMI_LOW_PRIORITY_MBOX) ||
++ (endPt == WMI_HIGH_PRIORITY_MBOX) || (endPt == WMI_BEST_EFFORT_MBOX));
++
++ ar->arTxPending[endPt]++;
++ if (endPt != WMI_CONTROL_MBOX) {
++ ar->arTotalTxDataPending++;
++ }
++
++ AR_DEBUG2_PRINTF("ar_control_tx: skb=0x%x, len=0x%x, mbox=%d\n",
++ (A_UINT32)osbuf, a_netbuf_to_len(osbuf), endPt);
++
++ cookie = ar6000_alloc_cookie(ar);
++
++ /* If the particular data queue is full, silently drop the pkt. */
++ dhdr = (WMI_DATA_HDR *)a_netbuf_to_data(osbuf);
++ if ((cookie == NULL) ||
++ ((ar->arTxPending[endPt] > MAX_ALLOWED_TXQ_DEPTH) &&
++ (!WMI_DATA_HDR_IS_MSG_TYPE(dhdr, SYNC_MSGTYPE))))
++ {
++ ar->arTxPending[endPt]--;
++ if (endPt != WMI_CONTROL_MBOX) {
++ ar->arTotalTxDataPending--;
++ }
++ a_netbuf_free(osbuf);
++ if (cookie != NULL) {
++ ar6000_free_cookie(ar, cookie);
++ }
++ return A_NO_MEMORY;
++ }
++
++ cookie->arc_bp[0] = (A_UINT32)osbuf;
++ cookie->arc_bp[1] = 0;
++ status = HTCBufferSend(ar->arHtcTarget, endPt, a_netbuf_to_data(osbuf),
++ a_netbuf_to_len(osbuf), cookie);
++ if (status != A_OK) {
++ /*
++ * XXX This is an error that requires us to reset chip
++ */
++ ar->arTxPending[endPt]--;
++ if (endPt != WMI_CONTROL_MBOX) {
++ ar->arTotalTxDataPending--;
++ }
++ AR_DEBUG_PRINTF("Dropping control frame!!\n");
++ ar6000_free_cookie(ar, cookie);
++ a_netbuf_free(osbuf);
++ return (status);
++ }
++
++ return A_OK;
++}
++
++module_init(ar6000_init_module);
++module_exit(ar6000_cleanup_module);
++
++/*
++ * SIOCGIWNAME
++ */
++int
++ar6000_ioctl_giwname(struct net_device *dev,
++ struct iw_request_info *info,
++ char *name, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ switch (ar->arPhyCapability) {
++ case (WMI_11A_CAPABILITY):
++ strncpy(name, "AR6000 802.11a", IFNAMSIZ);
++ break;
++ case (WMI_11G_CAPABILITY):
++ strncpy(name, "AR6000 802.11g", IFNAMSIZ);
++ break;
++ case (WMI_11AG_CAPABILITY):
++ strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
++ break;
++ default:
++ strncpy(name, "AR6000 802.11", IFNAMSIZ);
++ break;
++ }
++
++ return 0;
++}
++
++/*
++ * SIOCSIWFREQ
++ */
++int
++ar6000_ioctl_siwfreq(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_freq *freq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ /*
++ * We support limiting the channels via wmiconfig.
++ *
++ * We use this command to configure the channel hint for the connect cmd
++ * so it is possible the target will end up connecting to a different
++ * channel.
++ */
++ if (freq->e > 1) {
++ return -EINVAL;
++ } else if (freq->e == 1) {
++ ar->arChannelHint = freq->m / 100000;
++ } else {
++ ar->arChannelHint = wlan_ieee2freq(freq->m);
++ }
++
++ A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
++ return 0;
++}
++
++/*
++ * SIOCGIWFREQ
++ */
++int
++ar6000_ioctl_giwfreq(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_freq *freq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ar->arConnected != TRUE) {
++ return -EINVAL;
++ }
++
++ freq->m = ar->arBssChannel * 100000;
++ freq->e = 1;
++
++ return 0;
++}
++
++/*
++ * SIOCSIWMODE
++ */
++int
++ar6000_ioctl_siwmode(struct net_device *dev,
++ struct iw_request_info *info,
++ __u32 *mode, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ switch (*mode) {
++ case IW_MODE_INFRA:
++ ar->arNetworkType = INFRA_NETWORK;
++ break;
++ case IW_MODE_ADHOC:
++ ar->arNetworkType = ADHOC_NETWORK;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * SIOCGIWMODE
++ */
++int
++ar6000_ioctl_giwmode(struct net_device *dev,
++ struct iw_request_info *info,
++ __u32 *mode, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ switch (ar->arNetworkType) {
++ case INFRA_NETWORK:
++ *mode = IW_MODE_INFRA;
++ break;
++ case ADHOC_NETWORK:
++ *mode = IW_MODE_ADHOC;
++ break;
++ default:
++ return -EIO;
++ }
++ return 0;
++}
++
++/*
++ * SIOCSIWSENS
++ */
++int
++ar6000_ioctl_siwsens(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *sens, char *extra)
++{
++ return 0;
++}
++
++/*
++ * SIOCGIWSENS
++ */
++int
++ar6000_ioctl_giwsens(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *sens, char *extra)
++{
++ sens->value = 0;
++ sens->fixed = 1;
++
++ return 0;
++}
++
++/*
++ * SIOCGIWRANGE
++ */
++int
++ar6000_ioctl_giwrange(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct iw_range *range = (struct iw_range *) extra;
++ int i, ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++ ar->arNumChannels = -1;
++ A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ wait_event_interruptible(arEvent, ar->arNumChannels != -1);
++
++ if (signal_pending(current)) {
++ up(&ar->arSem);
++ return -EINTR;
++ }
++
++ data->length = sizeof(struct iw_range);
++ A_MEMZERO(range, sizeof(struct iw_range));
++
++ range->txpower_capa = 0;
++
++ range->min_pmp = 1 * 1024;
++ range->max_pmp = 65535 * 1024;
++ range->min_pmt = 1 * 1024;
++ range->max_pmt = 1000 * 1024;
++ range->pmp_flags = IW_POWER_PERIOD;
++ range->pmt_flags = IW_POWER_TIMEOUT;
++ range->pm_capa = 0;
++
++ range->we_version_compiled = WIRELESS_EXT;
++ range->we_version_source = 13;
++
++ range->retry_capa = IW_RETRY_LIMIT;
++ range->retry_flags = IW_RETRY_LIMIT;
++ range->min_retry = 0;
++ range->max_retry = 255;
++
++ range->num_frequency = range->num_channels = ar->arNumChannels;
++ for (i = 0; i < ar->arNumChannels; i++) {
++ range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
++ range->freq[i].m = ar->arChannelList[i] * 100000;
++ range->freq[i].e = 1;
++ }
++
++ /* Max quality is max field value minus noise floor */
++ range->max_qual.qual = 0xff - 161;
++
++ /*
++ * In order to use dBm measurements, 'level' must be lower
++ * than any possible measurement (see iw_print_stats() in
++ * wireless tools). It's unclear how this is meant to be
++ * done, but setting zero in these values forces dBm and
++ * the actual numbers are not used.
++ */
++ range->max_qual.level = 0;
++ range->max_qual.noise = 0;
++
++ range->sensitivity = 3;
++
++ range->max_encoding_tokens = 4;
++ /* XXX query driver to find out supported key sizes */
++ range->num_encoding_sizes = 3;
++ range->encoding_size[0] = 5; /* 40-bit */
++ range->encoding_size[1] = 13; /* 104-bit */
++ range->encoding_size[2] = 16; /* 128-bit */
++
++ range->num_bitrates = 0;
++
++ /* estimated maximum TCP throughput values (bps) */
++ range->throughput = 22000000;
++
++ range->min_rts = 0;
++ range->max_rts = 2347;
++ range->min_frag = 256;
++ range->max_frag = 2346;
++
++ up(&ar->arSem);
++
++ return ret;
++}
++
++/*
++ * SIOCSIWAP
++ * This ioctl is used to set the desired bssid for the connect command.
++ */
++int
++ar6000_ioctl_siwap(struct net_device *dev,
++ struct iw_request_info *info,
++ struct sockaddr *ap_addr, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ap_addr->sa_family != ARPHRD_ETHER) {
++ return -EIO;
++ }
++
++ if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
++ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++ } else {
++ A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid));
++ }
++
++ return 0;
++}
++
++/*
++ * SIOCGIWAP
++ */
++int
++ar6000_ioctl_giwap(struct net_device *dev,
++ struct iw_request_info *info,
++ struct sockaddr *ap_addr, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ar->arConnected != TRUE) {
++ return -EINVAL;
++ }
++
++ A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
++ ap_addr->sa_family = ARPHRD_ETHER;
++
++ return 0;
++}
++
++/*
++ * SIOCGIWAPLIST
++ */
++int
++ar6000_ioctl_iwaplist(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *extra)
++{
++ return -EIO; /* for now */
++}
++
++/*
++ * SIOCGIWSCAN
++ */
++int
++ar6000_ioctl_siwscan(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN) != A_OK) {
++ ret = -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return ret;
++}
++
++#if WIRELESS_EXT > 14
++/*
++ * Encode a WPA or RSN information element as a custom
++ * element using the hostap format.
++ */
++static u_int
++encode_ie(void *buf, size_t bufsize,
++ const u_int8_t *ie, size_t ielen,
++ const char *leader, size_t leader_len)
++{
++ u_int8_t *p;
++ int i;
++
++ if (bufsize < leader_len)
++ return 0;
++ p = buf;
++ memcpy(p, leader, leader_len);
++ bufsize -= leader_len;
++ p += leader_len;
++ for (i = 0; i < ielen && bufsize > 2; i++)
++ p += sprintf(p, "%02x", ie[i]);
++ return (i == ielen ? p - (u_int8_t *)buf : 0);
++}
++#endif /* WIRELESS_EXT > 14 */
++/*
++ * Units are in db above the noise floor. That means the
++ * rssi values reported in the tx/rx descriptors in the
++ * driver are the SNR expressed in db.
++ *
++ * If you assume that the noise floor is -95, which is an
++ * excellent assumption 99.5 % of the time, then you can
++ * derive the absolute signal level (i.e. -95 + rssi).
++ * There are some other slight factors to take into account
++ * depending on whether the rssi measurement is from 11b,
++ * 11g, or 11a. These differences are at most 2db and
++ * can be documented.
++ *
++ * NB: various calculations are based on the orinoco/wavelan
++ * drivers for compatibility
++ */
++static void
++ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
++{
++ if (rssi < 0) {
++ iq->qual = 0;
++ } else {
++ iq->qual = rssi;
++ }
++
++ /* NB: max is 94 because noise is hardcoded to 161 */
++ if (iq->qual > 94)
++ iq->qual = 94;
++
++ iq->noise = 161; /* -95dBm */
++ iq->level = iq->noise + iq->qual;
++ iq->updated = 7;
++}
++
++void
++ar6000_scan_node(void *arg, bss_t *ni)
++{
++ struct iw_event iwe;
++#if WIRELESS_EXT > 14
++ char buf[64*2 + 30];
++#endif
++ struct ar_giwscan_param *param;
++ A_CHAR *current_ev;
++ A_CHAR *end_buf;
++ struct ieee80211_common_ie *cie;
++
++ param = (struct ar_giwscan_param *)arg;
++
++ if (param->current_ev >= param->end_buf) {
++ return;
++ }
++ if ((param->firstPass == TRUE) && (ni->ni_cie.ie_wpa == NULL)) {
++ /*
++ * Only forward wpa bss's in first pass
++ */
++ return;
++ }
++ if ((param->firstPass == FALSE) && (ni->ni_cie.ie_wpa != NULL)) {
++ /*
++ * Only forward non-wpa bss's in 2nd pass
++ */
++ return;
++ }
++
++ current_ev = param->current_ev;
++ end_buf = param->end_buf;
++
++ cie = &ni->ni_cie;
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWAP;
++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++ A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++ IW_EV_ADDR_LEN);
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWESSID;
++ iwe.u.data.flags = 1;
++ iwe.u.data.length = cie->ie_ssid[1];
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe,
++ &cie->ie_ssid[2]);
++
++ if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWMODE;
++ iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
++ IW_MODE_MASTER : IW_MODE_ADHOC;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++ IW_EV_UINT_LEN);
++ }
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWFREQ;
++ iwe.u.freq.m = cie->ie_chan * 100000;
++ iwe.u.freq.e = 1;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++ IW_EV_FREQ_LEN);
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = IWEVQUAL;
++ ar6000_set_quality(&iwe.u.qual, ni->ni_rssi);
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe,
++ IW_EV_QUAL_LEN);
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWENCODE;
++ if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++ } else {
++ iwe.u.data.flags = IW_ENCODE_DISABLED;
++ }
++ iwe.u.data.length = 0;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, "");
++
++#ifdef NOTYET
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = SIOCGIWRATE;
++ current_val = current_ev + IW_EV_LCP_LEN;
++ for (j = 0; j < ni->ni_rates.rs_nrates; j++) {
++ if (ni->ni_rates.rs_rates[j]) {
++ iwe.u.bitrate.value = ((ni->ni_rates.rs_rates[j] &
++ IEEE80211_RATE_VAL) / 2) * 1000000;
++ current_val = iwe_stream_add_value(current_ev,
++ current_val, end_buf, &iwe,
++ IW_EV_PARAM_LEN);
++ }
++ }
++ /* remove fixed header if no rates were added */
++ if ((current_val - current_ev) > IW_EV_LCP_LEN)
++ current_ev = current_val;
++#endif /* NOTYET */
++
++#if WIRELESS_EXT > 14
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
++ iwe.u.data.length = strlen(buf);
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++
++ if (cie->ie_wpa != NULL) {
++ static const char rsn_leader[] = "rsn_ie=";
++ static const char wpa_leader[] = "wpa_ie=";
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ if (cie->ie_wpa[0] == IEEE80211_ELEMID_RSN) {
++ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
++ cie->ie_wpa[1]+2,
++ rsn_leader, sizeof(rsn_leader)-1);
++ } else {
++ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
++ cie->ie_wpa[1]+2,
++ wpa_leader, sizeof(wpa_leader)-1);
++ }
++ if (iwe.u.data.length != 0) {
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++ }
++
++ if (cie->ie_wmm != NULL) {
++ static const char wmm_leader[] = "wmm_ie=";
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
++ cie->ie_wmm[1]+2,
++ wmm_leader, sizeof(wmm_leader)-1);
++ if (iwe.u.data.length != 0) {
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++ }
++
++ if (cie->ie_ath != NULL) {
++ static const char ath_leader[] = "ath_ie=";
++
++ A_MEMZERO(&iwe, sizeof(iwe));
++ iwe.cmd = IWEVCUSTOM;
++ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
++ cie->ie_ath[1]+2,
++ ath_leader, sizeof(ath_leader)-1);
++ if (iwe.u.data.length != 0) {
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++ }
++#endif /* WIRELESS_EXT > 14 */
++
++ param->current_ev = current_ev;
++}
++
++int
++ar6000_ioctl_giwscan(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ar_giwscan_param param;
++ int i;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ param.current_ev = extra;
++ param.end_buf = extra + IW_SCAN_MAX_DATA;
++ param.firstPass = TRUE;
++
++ /*
++ * Do two passes to insure WPA scan candidates
++ * are sorted to the front. This is a hack to deal with
++ * the wireless extensions capping scan results at
++ * IW_SCAN_MAX_DATA bytes. In densely populated environments
++ * it's easy to overflow this buffer (especially with WPA/RSN
++ * information elements). Note this sorting hack does not
++ * guarantee we won't overflow anyway.
++ */
++ for (i = 0; i < 2; i++) {
++ /*
++ * Translate data to WE format.
++ */
++ wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m);
++ param.firstPass = FALSE;
++ if (param.current_ev >= param.end_buf) {
++ break;
++ }
++ }
++
++ data->length = param.current_ev - extra;
++ return 0;
++}
++
++/* SIOCSIWESSID */
++static int
++ar6000_ioctl_siwessid(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *ssid)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ A_STATUS status;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ /*
++ * iwconfig passes a null terminated string with length including this
++ * so we need to account for this
++ */
++ if (data->flags && (!data->length || (data->length == 1) ||
++ ((data->length - 1) > sizeof(ar->arSsid))))
++ {
++ /*
++ * ssid is invalid
++ */
++ return -EINVAL;
++ }
++
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++
++ if (ar->arTxPending[WMI_CONTROL_MBOX]) {
++ /*
++ * sleep until the command queue drains
++ */
++ wait_event_interruptible(arEvent,
++ ar->arTxPending[WMI_CONTROL_MBOX] == 0);
++ if (signal_pending(current)) {
++ return -EINTR;
++ }
++ }
++
++ if ((ar->arSsidLen) || (!data->flags))
++ {
++ if ((!data->flags) ||
++ (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
++ (ar->arSsidLen != (data->length - 1)))
++ {
++ /*
++ * SSID set previously or essid off has been issued.
++ *
++ * Disconnect Command is issued in two cases after wmi is ready
++ * (1) ssid is different from the previous setting
++ * (2) essid off has been issued
++ *
++ */
++ if (ar->arWmiReady == TRUE) {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ status = wmi_disconnect_cmd(ar->arWmi);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++ ar->arSsidLen = 0;
++ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
++ if (!data->flags) {
++ up(&ar->arSem);
++ return 0;
++ }
++ } else {
++ up(&ar->arSem);
++ }
++ }
++ else
++ {
++ /*
++ * SSID is same, so we assume profile hasn't changed.
++ * If the interface is up and wmi is ready, we issue
++ * a reconnect cmd.
++ */
++ if((ar->arConnected == TRUE || ar->arConnectPending == TRUE) && (ar->arWmiReady == TRUE))
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
++ ar->arChannelHint);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ if (status != A_OK) {
++ return -EIO;
++ }
++ return 0;
++ }
++ else{
++ up(&ar->arSem);
++ return 0;
++ }
++ }
++ }
++
++ ar->arSsidLen = data->length - 1;
++ A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
++
++ /* The ssid length check prevents second "essid off" from the user,
++ to be treated as a connect cmd. The second "essid off" is ignored.
++ */
++ if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) )
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (SHARED_AUTH == ar->arDot11AuthMode) {
++ ar6000_install_static_wep_keys(ar);
++ }
++ AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\
++ " PW crypto %d PW crypto Len %d GRP crypto %d"\
++ " GRP crypto Len %d\n",
++ ar->arAuthMode, ar->arDot11AuthMode,
++ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
++ ar->arGroupCrypto, ar->arGroupCryptoLen);
++
++ status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
++ ar->arDot11AuthMode, ar->arAuthMode,
++ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
++ ar->arGroupCrypto,ar->arGroupCryptoLen,
++ ar->arSsidLen, ar->arSsid,
++ ar->arReqBssid, ar->arChannelHint);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ up(&ar->arSem);
++
++ if (status != A_OK) {
++ return -EIO;
++ }
++ ar->arConnectPending = TRUE;
++ }else{
++ up(&ar->arSem);
++ }
++ return 0;
++}
++
++/* SIOCGIWESSID */
++static int
++ar6000_ioctl_giwessid(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *data, char *essid)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (!ar->arSsidLen) {
++ return -EINVAL;
++ }
++
++ data->flags = 1;
++ data->length = ar->arSsidLen;
++ A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
++
++ return 0;
++}
++
++/*
++ * SIOCSIWRATE
++ */
++int
++ar6000_ioctl_siwrate(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ A_UINT32 kbps;
++
++ if (rrq->fixed) {
++ kbps = rrq->value / 1000; /* rrq->value is in bps */
++ } else {
++ kbps = -1; /* -1 indicates auto rate */
++ }
++ if(wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
++ {
++ AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps);
++ return -EINVAL;
++ }
++ ar->arBitRate = kbps;
++ if(ar->arWmiReady == TRUE)
++ {
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return -EINVAL;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ return 0;
++}
++
++/*
++ * SIOCGIWRATE
++ */
++int
++ar6000_ioctl_giwrate(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int ret = 0;
++
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++ if(ar->arWmiReady == TRUE)
++ {
++ ar->arBitRate = 0xFFFF;
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ wait_event_interruptible(arEvent, ar->arBitRate != 0xFFFF);
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ }
++ }
++ /* If the interface is down or wmi is not ready or the target is not
++ connected - return the value stored in the device structure */
++ if (!ret) {
++ if (ar->arBitRate == -1) {
++ rrq->fixed = TRUE;
++ rrq->value = 0;
++ } else {
++ rrq->value = ar->arBitRate * 1000;
++ }
++ }
++
++ up(&ar->arSem);
++
++ return ret;
++}
++
++/*
++ * SIOCSIWTXPOW
++ */
++static int
++ar6000_ioctl_siwtxpow(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ A_UINT8 dbM;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (rrq->disabled) {
++ return -EOPNOTSUPP;
++ }
++
++ if (rrq->fixed) {
++ if (rrq->flags != IW_TXPOW_DBM) {
++ return -EOPNOTSUPP;
++ }
++ ar->arTxPwr= dbM = rrq->value;
++ ar->arTxPwrSet = TRUE;
++ } else {
++ ar->arTxPwr = dbM = 0;
++ ar->arTxPwrSet = FALSE;
++ }
++ if(ar->arWmiReady == TRUE)
++ {
++ AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM);
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ wmi_set_txPwr_cmd(ar->arWmi, dbM);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ }
++ return 0;
++}
++
++/*
++ * SIOCGIWTXPOW
++ */
++int
++ar6000_ioctl_giwtxpow(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int ret = 0;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (down_interruptible(&ar->arSem)) {
++ return -ERESTARTSYS;
++ }
++ if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
++ {
++ ar->arTxPwr = 0;
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ up(&ar->arSem);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ wait_event_interruptible(arEvent, ar->arTxPwr != 0);
++
++ if (signal_pending(current)) {
++ ret = -EINTR;
++ }
++ }
++ /* If the interace is down or wmi is not ready or target is not connected
++ then return value stored in the device structure */
++
++ if (!ret) {
++ if (ar->arTxPwrSet == TRUE) {
++ rrq->fixed = TRUE;
++ }
++ rrq->value = ar->arTxPwr;
++ rrq->flags = IW_TXPOW_DBM;
++ }
++
++ up(&ar->arSem);
++
++ return ret;
++}
++
++/*
++ * SIOCSIWRETRY
++ * since iwconfig only provides us with one max retry value, we use it
++ * to apply to data frames of the BE traffic class.
++ */
++static int
++ar6000_ioctl_siwretry(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (rrq->disabled) {
++ return -EOPNOTSUPP;
++ }
++
++ if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
++ return -EOPNOTSUPP;
++ }
++
++ if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
++ return - EINVAL;
++ }
++ if(ar->arWmiReady == TRUE)
++ {
++ if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
++ rrq->value) == A_OK){
++ return -EINVAL;
++ }
++ }
++ ar->arMaxRetries = rrq->value;
++ return 0;
++}
++
++/*
++ * SIOCGIWRETRY
++ */
++static int
++ar6000_ioctl_giwretry(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *rrq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ rrq->disabled = 0;
++ switch (rrq->flags & IW_RETRY_TYPE) {
++ case IW_RETRY_LIFETIME:
++ return -EOPNOTSUPP;
++ break;
++ case IW_RETRY_LIMIT:
++ rrq->flags = IW_RETRY_LIMIT;
++ switch (rrq->flags & IW_RETRY_MODIFIER) {
++ case IW_RETRY_MIN:
++ rrq->flags |= IW_RETRY_MIN;
++ rrq->value = WMI_MIN_RETRIES;
++ break;
++ case IW_RETRY_MAX:
++ rrq->flags |= IW_RETRY_MAX;
++ rrq->value = ar->arMaxRetries;
++ break;
++ }
++ break;
++ }
++ return 0;
++}
++
++/*
++ * SIOCSIWENCODE
++ */
++static int
++ar6000_ioctl_siwencode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *erq, char *keybuf)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int index;
++ DOT11_AUTH_MODE auth = ar->arDot11AuthMode;
++ /*
++ * Static WEP Keys should be configured before setting the SSID
++ */
++ if (ar->arSsidLen) {
++ return -EIO;
++ }
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ index = erq->flags & IW_ENCODE_INDEX;
++
++ if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
++ ((index - 1) > WMI_MAX_KEY_INDEX)))
++ {
++ return -EIO;
++ }
++
++ if (erq->flags & IW_ENCODE_DISABLED) {
++ /*
++ * Encryption disabled
++ */
++ if (index) {
++ /*
++ * If key index was specified then clear the specified key
++ */
++ index--;
++ A_MEMZERO(ar->arWepKeyList[index].arKey,
++ sizeof(ar->arWepKeyList[index].arKey));
++ ar->arWepKeyList[index].arKeyLen = 0;
++ }
++ ar->arDot11AuthMode = OPEN_AUTH;
++ ar->arPairwiseCrypto = NONE_CRYPT;
++ ar->arGroupCrypto = NONE_CRYPT;
++ ar->arAuthMode = NONE_AUTH;
++ } else {
++ /*
++ * Enabling WEP encryption
++ */
++ if (index) {
++ index--; /* keyindex is off base 1 in iwconfig */
++ }
++
++ if (erq->flags & IW_ENCODE_OPEN) {
++ auth = OPEN_AUTH;
++ } else if (erq->flags & IW_ENCODE_RESTRICTED) {
++ auth = SHARED_AUTH;
++ }
++
++ if (erq->length) {
++ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
++ return -EIO;
++ }
++
++ A_MEMZERO(ar->arWepKeyList[index].arKey,
++ sizeof(ar->arWepKeyList[index].arKey));
++ A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
++ ar->arWepKeyList[index].arKeyLen = erq->length;
++ } else {
++ if (ar->arWepKeyList[index].arKeyLen == 0) {
++ return -EIO;
++ }
++ ar->arDefTxKeyIndex = index;
++ }
++
++ ar->arPairwiseCrypto = WEP_CRYPT;
++ ar->arGroupCrypto = WEP_CRYPT;
++ ar->arDot11AuthMode = auth;
++ ar->arAuthMode = NONE_AUTH;
++ }
++
++ /*
++ * profile has changed. Erase ssid to signal change
++ */
++ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_giwencode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *erq, char *key)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ A_UINT8 keyIndex;
++ struct ar_wep_key *wk;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if (ar->arPairwiseCrypto == NONE_CRYPT) {
++ erq->length = 0;
++ erq->flags = IW_ENCODE_DISABLED;
++ } else {
++ /* get the keyIndex */
++ keyIndex = erq->flags & IW_ENCODE_INDEX;
++ if (0 == keyIndex) {
++ keyIndex = ar->arDefTxKeyIndex;
++ } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
++ (keyIndex - 1 > WMI_MAX_KEY_INDEX))
++ {
++ keyIndex = WMI_MIN_KEY_INDEX;
++ } else {
++ keyIndex--;
++ }
++ erq->flags = keyIndex + 1;
++ erq->flags |= IW_ENCODE_ENABLED;
++ wk = &ar->arWepKeyList[keyIndex];
++ if (erq->length > wk->arKeyLen) {
++ erq->length = wk->arKeyLen;
++ }
++ if (wk->arKeyLen) {
++ A_MEMCPY(key, wk->arKey, erq->length);
++ }
++ if (ar->arDot11AuthMode == OPEN_AUTH) {
++ erq->flags |= IW_ENCODE_OPEN;
++ } else if (ar->arDot11AuthMode == SHARED_AUTH) {
++ erq->flags |= IW_ENCODE_RESTRICTED;
++ }
++ }
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_setparam(struct net_device *dev,
++ struct iw_request_info *info,
++ void *erq, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ int *i = (int *)extra;
++ int param = i[0];
++ int value = i[1];
++ int ret = 0;
++ A_BOOL profChanged = FALSE;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ switch (param) {
++ case IEEE80211_PARAM_WPA:
++ switch (value) {
++ case WPA_MODE_WPA1:
++ ar->arAuthMode = WPA_AUTH;
++ profChanged = TRUE;
++ break;
++ case WPA_MODE_WPA2:
++ ar->arAuthMode = WPA2_AUTH;
++ profChanged = TRUE;
++ break;
++ case WPA_MODE_NONE:
++ ar->arAuthMode = NONE_AUTH;
++ profChanged = TRUE;
++ break;
++ }
++ break;
++ case IEEE80211_PARAM_AUTHMODE:
++ switch(value) {
++ case IEEE80211_AUTH_WPA_PSK:
++ if (WPA_AUTH == ar->arAuthMode) {
++ ar->arAuthMode = WPA_PSK_AUTH;
++ profChanged = TRUE;
++ } else if (WPA2_AUTH == ar->arAuthMode) {
++ ar->arAuthMode = WPA2_PSK_AUTH;
++ profChanged = TRUE;
++ } else {
++ AR_DEBUG_PRINTF("Error - Setting PSK mode when WPA "\
++ "param was set to %d\n",
++ ar->arAuthMode);
++ ret = -1;
++ }
++ break;
++ case IEEE80211_AUTH_WPA_CCKM:
++ if (WPA2_AUTH == ar->arAuthMode) {
++ ar->arAuthMode = WPA2_AUTH_CCKM;
++ } else {
++ ar->arAuthMode = WPA_AUTH_CCKM;
++ }
++ break;
++ default:
++ break;
++ }
++ break;
++ case IEEE80211_PARAM_UCASTCIPHER:
++ switch (value) {
++ case IEEE80211_CIPHER_AES_CCM:
++ ar->arPairwiseCrypto = AES_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_TKIP:
++ ar->arPairwiseCrypto = TKIP_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_WEP:
++ ar->arPairwiseCrypto = WEP_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_NONE:
++ ar->arPairwiseCrypto = NONE_CRYPT;
++ profChanged = TRUE;
++ break;
++ }
++ break;
++ case IEEE80211_PARAM_UCASTKEYLEN:
++ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
++ ret = -EIO;
++ } else {
++ ar->arPairwiseCryptoLen = value;
++ }
++ break;
++ case IEEE80211_PARAM_MCASTCIPHER:
++ switch (value) {
++ case IEEE80211_CIPHER_AES_CCM:
++ ar->arGroupCrypto = AES_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_TKIP:
++ ar->arGroupCrypto = TKIP_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_WEP:
++ ar->arGroupCrypto = WEP_CRYPT;
++ profChanged = TRUE;
++ break;
++ case IEEE80211_CIPHER_NONE:
++ ar->arGroupCrypto = NONE_CRYPT;
++ profChanged = TRUE;
++ break;
++ }
++ break;
++ case IEEE80211_PARAM_MCASTKEYLEN:
++ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
++ ret = -EIO;
++ } else {
++ ar->arGroupCryptoLen = value;
++ }
++ break;
++ case IEEE80211_PARAM_COUNTERMEASURES:
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ break;
++ default:
++ break;
++ }
++
++ if (profChanged == TRUE) {
++ /*
++ * profile has changed. Erase ssid to signal change
++ */
++ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
++ }
++
++ return ret;
++}
++
++int
++ar6000_ioctl_getparam(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ return -EIO; /* for now */
++}
++
++int
++ar6000_ioctl_setkey(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ieee80211req_key *ik = (struct ieee80211req_key *)extra;
++ KEY_USAGE keyUsage;
++ A_STATUS status;
++ CRYPTO_TYPE keyType = NONE_CRYPT;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ if ( 0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00",
++ IEEE80211_ADDR_LEN)) {
++ keyUsage = GROUP_USAGE;
++ } else {
++ keyUsage = PAIRWISE_USAGE;
++ }
++
++ switch (ik->ik_type) {
++ case IEEE80211_CIPHER_WEP:
++ keyType = WEP_CRYPT;
++ break;
++ case IEEE80211_CIPHER_TKIP:
++ keyType = TKIP_CRYPT;
++ break;
++ case IEEE80211_CIPHER_AES_CCM:
++ keyType = AES_CRYPT;
++ break;
++ default:
++ break;
++ }
++
++ if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
++ if (NONE_CRYPT == keyType) {
++ return -EIO;
++ }
++
++ status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
++ ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
++ ik->ik_keydata, SYNC_BEFORE_WMIFLAG);
++
++ if (status != A_OK) {
++ return -EIO;
++ }
++ } else {
++ status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
++ }
++
++ return 0;
++}
++
++void
++ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
++{
++ A_UINT8 index;
++ A_UINT8 keyUsage;
++
++ for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
++ if (ar->arWepKeyList[index].arKeyLen) {
++ keyUsage = GROUP_USAGE;
++ if (index == ar->arDefTxKeyIndex) {
++ keyUsage |= TX_USAGE;
++ }
++ wmi_addKey_cmd(ar->arWmi,
++ index,
++ WEP_CRYPT,
++ keyUsage,
++ ar->arWepKeyList[index].arKeyLen,
++ NULL,
++ ar->arWepKeyList[index].arKey, NO_SYNC_WMIFLAG);
++ }
++ }
++}
++
++int
++ar6000_ioctl_delkey(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ return 0;
++}
++
++int
++ar6000_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *)extra;
++
++ if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE)) {
++ return -EIO;
++ }
++
++ switch (mlme->im_op) {
++ case IEEE80211_MLME_DISASSOC:
++ case IEEE80211_MLME_DEAUTH:
++ /* Not Supported */
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++int
++ar6000_ioctl_setwmmparams(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ return -EIO; /* for now */
++}
++
++int
++ar6000_ioctl_getwmmparams(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ return -EIO; /* for now */
++}
++
++int
++ar6000_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ return 0;
++}
++
++int
++ar6000_ioctl_setauthalg(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ieee80211req_authalg *req = (struct ieee80211req_authalg *)extra;
++ int ret = 0;
++
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) {
++ ar->arDot11AuthMode = OPEN_AUTH;
++ } else if (req->auth_alg == AUTH_ALG_LEAP) {
++ ar->arDot11AuthMode = LEAP_AUTH;
++ ar->arPairwiseCrypto = WEP_CRYPT;
++ ar->arGroupCrypto = WEP_CRYPT;
++ } else {
++ ret = -EIO;
++ }
++
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return ret;
++}
++static int
++ar6000_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info,
++ void *w, char *extra)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ struct ieee80211req_addpmkid *req = (struct ieee80211req_addpmkid *)extra;
++ A_STATUS status;
++
++ if (ar->arWlanState == WLAN_DISABLED) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++ AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
++ req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2],
++ req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5],
++ req->pi_enable);
++
++ status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid,
++ req->pi_enable);
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ if (status != A_OK) {
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ /* currently assume only roam times are required */
++ if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_SET_ROAM_CTRL_CMD cmd;
++ A_UINT8 size = sizeof(cmd);
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++
++ if (copy_from_user(&cmd, userdata, size)) {
++ return -EFAULT;
++ }
++
++ if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
++ if (cmd.info.bssBiasInfo.numBss > 1) {
++ size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
++ }
++ }
++
++ if (copy_from_user(&cmd, userdata, size)) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return 0;
++}
++
++static int
++ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_POWERSAVE_TIMERS_CMD cmd;
++ A_UINT8 size = sizeof(cmd);
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ if (copy_from_user(&cmd, userdata, size)) {
++ return -EFAULT;
++ }
++
++ if (copy_from_user(&cmd, userdata, size)) {
++ return -EFAULT;
++ }
++
++ AR6000_SPIN_LOCK(&ar->arLock, 0);
++
++ if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++ return -EIO;
++ }
++ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
++
++ return 0;
++}
++
++
++#if defined(DEBUG)
++int dset_debug = 0;
++#define DSET_DEBUG_PRINTF(args...) if (dset_debug) printk(args);
++#else
++#define DSET_DEBUG_PRINTF(args...)
++#endif
++
++/* Called when a DataSet Open request is received from the Target. */
++void
++ar6000_dset_open_req(void *devt,
++ A_UINT32 id,
++ A_UINT32 targ_handle,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++
++ DSET_DEBUG_PRINTF("ar6000_dset_open_req id=0x%x\n", id);
++
++ if (!dset_server_alive) {
++ /*
++ * An attempt to open a Host DataSet before the DataSet Server
++ * has started. (Or this Host chooses not to serve DataSets.)
++ */
++ DSET_DEBUG_PRINTF("DataSet Server not running. Unable to handle open request for id=0x%x\n", id);
++ wmi_dset_open_reply(ar->arWmi, A_ENOTSUP, 0, 0, 0,
++ targ_handle, targ_reply_fn, targ_reply_arg);
++ return;
++ }
++
++#if CONFIG_HOST_DSET_SUPPORT
++ if (spin_trylock(&dset_request_lock)) {
++ pending_dset_request.cmd = AR6000_OPEN_REQ;
++ pending_dset_request.u.open_req.id = id;
++ pending_dset_request.u.open_req.targ_handle = targ_handle;
++ pending_dset_request.u.open_req.targ_reply_fn = targ_reply_fn;
++ pending_dset_request.u.open_req.targ_reply_arg = targ_reply_arg;
++ /* Wakeup waiting thread */
++ pending_dset_request_valid = TRUE;
++ wake_up(&dset_request);
++ } else {
++ wmi_dset_open_reply(ar->arWmi, A_EBUSY, 0, 0, 0,
++ targ_handle, targ_reply_fn, targ_reply_arg);
++ }
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++}
++
++#if CONFIG_HOST_DSET_SUPPORT
++/* Called when a DataSet Close is received from the Target. */
++void
++ar6000_dset_close(void *devt,
++ A_UINT32 access_cookie)
++{
++ DSET_DEBUG_PRINTF("ar6000_dset_close access_cookie=0x%x\n", access_cookie);
++}
++
++/* Called when a DataSet Data Request is received from the Target. */
++void
++ar6000_dset_data_req(void *devt,
++ A_UINT32 access_cookie,
++ A_UINT32 offset,
++ A_UINT32 length,
++ A_UINT32 targ_buf,
++ A_UINT32 targ_reply_fn,
++ A_UINT32 targ_reply_arg)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
++
++ DSET_DEBUG_PRINTF("ar6000_dset_data_req: Cookie=0x%x offset=%d length=%d\n",
++ access_cookie, offset, length);
++
++ if (spin_trylock(&dset_request_lock)) {
++ pending_dset_request.cmd = AR6000_DATA_REQ;
++ pending_dset_request.u.data_req.access_cookie = access_cookie;
++ pending_dset_request.u.data_req.offset = offset;
++ pending_dset_request.u.data_req.length = length;
++ pending_dset_request.u.data_req.targ_buf = targ_buf;
++ pending_dset_request.u.data_req.targ_reply_fn = targ_reply_fn;
++ pending_dset_request.u.data_req.targ_reply_arg = targ_reply_arg;
++
++ /* Wakeup waiting thread */
++ pending_dset_request_valid = TRUE;
++ wake_up(&dset_request);
++ } else {
++ wmi_dset_data_reply(ar->arWmi, A_EBUSY, NULL, length,
++ targ_buf, targ_reply_fn, targ_reply_arg);
++ }
++}
++
++/* Init cookie queue */
++static void
++ar6000_cookie_init(AR_SOFTC_T *ar)
++{
++ A_UINT32 i;
++
++ ar->arCookieList = NULL;
++ A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
++
++ for (i = 0; i < MAX_COOKIE_NUM; i++) {
++ ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
++ }
++}
++
++/* cleanup cookie queue */
++static void
++ar6000_cookie_cleanup(AR_SOFTC_T *ar)
++{
++ /* It is gone .... */
++ ar->arCookieList = NULL;
++}
++
++/* Init cookie queue */
++static void
++ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
++{
++ /* Insert first */
++ cookie->arc_list_next = ar->arCookieList;
++ ar->arCookieList = cookie;
++}
++
++/* cleanup cookie queue */
++static struct ar_cookie *
++ar6000_alloc_cookie(AR_SOFTC_T *ar)
++{
++ struct ar_cookie *cookie;
++
++ cookie = ar->arCookieList;
++ if(cookie != NULL)
++ {
++ ar->arCookieList = cookie->arc_list_next;
++ }
++
++ return cookie;
++}
++
++/* Host-side initialization for DataSets */
++static void
++ar6000_dset_init(void)
++{
++ spin_lock_init(&dset_request_lock);
++ pending_dset_request_valid = FALSE;
++}
++#endif /* CONFIG_HOST_DSET_SUPPORT */
++
++#if CONFIG_HOST_GPIO_SUPPORT
++/* Host-side initialization for General Purpose I/O support */
++static void
++ar6000_gpio_init(void)
++{
++ gpio_intr_available = FALSE;
++ gpio_data_available = FALSE;
++ gpio_ack_received = FALSE;
++}
++
++/*
++ * Called when a GPIO interrupt is received from the Target.
++ * intr_values shows which GPIO pins have interrupted.
++ * input_values shows a recent value of GPIO pins.
++ */
++void
++ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
++{
++ gpio_intr_results.intr_mask = intr_mask;
++ gpio_intr_results.input_values = input_values;
++ *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
++ wake_up(&arEvent);
++}
++
++/*
++ * This is called when a response is received from the Target
++ * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
++ * call.
++ */
++void
++ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
++{
++ gpio_reg_results.gpioreg_id = reg_id;
++ gpio_reg_results.value = value;
++ *((volatile A_BOOL *)&gpio_data_available) = TRUE;
++ wake_up(&arEvent);
++}
++
++/*
++ * This is called when an acknowledgement is received from the Target
++ * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
++ * call.
++ */
++void
++ar6000_gpio_ack_rx(void)
++{
++ gpio_ack_received = TRUE;
++ wake_up(&arEvent);
++}
++
++A_STATUS
++ar6000_gpio_output_set(struct net_device *dev,
++ A_UINT32 set_mask,
++ A_UINT32 clear_mask,
++ A_UINT32 enable_mask,
++ A_UINT32 disable_mask)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ gpio_ack_received = FALSE;
++ return wmi_gpio_output_set(ar->arWmi,
++ set_mask, clear_mask, enable_mask, disable_mask);
++}
++
++static A_STATUS
++ar6000_gpio_input_get(struct net_device *dev)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
++ return wmi_gpio_input_get(ar->arWmi);
++}
++
++static A_STATUS
++ar6000_gpio_register_set(struct net_device *dev,
++ A_UINT32 gpioreg_id,
++ A_UINT32 value)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ gpio_ack_received = FALSE;
++ return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
++}
++
++static A_STATUS
++ar6000_gpio_register_get(struct net_device *dev,
++ A_UINT32 gpioreg_id)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
++ return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
++}
++
++static A_STATUS
++ar6000_gpio_intr_ack(struct net_device *dev,
++ A_UINT32 ack_mask)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++
++ gpio_intr_available = FALSE;
++ return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
++}
++#endif /* CONFIG_HOST_GPIO_SUPPORT */
++
++/* Structures to export the Wireless Handlers */
++static const iw_handler ath_handlers[] = {
++ (iw_handler) NULL, /* SIOCSIWCOMMIT */
++ (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */
++ (iw_handler) NULL, /* SIOCSIWNWID */
++ (iw_handler) NULL, /* SIOCGIWNWID */
++ (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */
++ (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */
++ (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */
++ (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */
++ (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */
++ (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */
++ (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */
++ (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */
++ (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */
++ (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */
++ (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */
++ (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */
++ (iw_handler) NULL, /* SIOCSIWSPY */
++ (iw_handler) NULL, /* SIOCGIWSPY */
++ (iw_handler) NULL, /* SIOCSIWTHRSPY */
++ (iw_handler) NULL, /* SIOCGIWTHRSPY */
++ (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */
++ (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */
++ (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */
++ (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */
++ (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */
++ (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */
++ (iw_handler) NULL, /* SIOCSIWNICKN */
++ (iw_handler) NULL, /* SIOCGIWNICKN */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */
++ (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */
++#ifdef NOTYET
++ (iw_handler) ar6000_ioctl_siwrts, /* SIOCSIWRTS */
++ (iw_handler) ar6000_ioctl_giwrts, /* SIOCGIWRTS */
++ (iw_handler) ar6000_ioctl_siwfrag, /* SIOCSIWFRAG */
++ (iw_handler) ar6000_ioctl_giwfrag, /* SIOCGIWFRAG */
++ (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */
++ (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */
++ (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */
++ (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */
++ (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */
++ (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */
++ (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */
++ (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */
++#else
++ (iw_handler) NULL, /* SIOCSIWRTS */
++ (iw_handler) NULL, /* SIOCGIWRTS */
++ (iw_handler) NULL, /* SIOCSIWFRAG */
++ (iw_handler) NULL, /* SIOCGIWFRAG */
++ (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */
++ (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */
++ (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */
++ (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */
++ (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */
++ (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */
++ (iw_handler) NULL, /* SIOCSIWPOWER */
++ (iw_handler) NULL, /* SIOCGIWPOWER */
++#endif /* NOTYET */
++};
++
++static const iw_handler ath_priv_handlers[] = {
++ (iw_handler) ar6000_ioctl_setparam, /* SIOCWFIRSTPRIV+0 */
++ (iw_handler) ar6000_ioctl_getparam, /* SIOCWFIRSTPRIV+1 */
++ (iw_handler) ar6000_ioctl_setkey, /* SIOCWFIRSTPRIV+2 */
++ (iw_handler) ar6000_ioctl_setwmmparams, /* SIOCWFIRSTPRIV+3 */
++ (iw_handler) ar6000_ioctl_delkey, /* SIOCWFIRSTPRIV+4 */
++ (iw_handler) ar6000_ioctl_getwmmparams, /* SIOCWFIRSTPRIV+5 */
++ (iw_handler) NULL, /* SIOCWFIRSTPRIV+6 */
++ (iw_handler) NULL, /* SIOCWFIRSTPRIV+7 */
++ (iw_handler) ar6000_ioctl_addpmkid, /* SIOCWFIRSTPRIV+8 */
++ (iw_handler) NULL, /* SIOCWFIRSTPRIV+9 */
++#ifdef NOT_YET
++ (iw_handler) ar6000_ioctl_setauthalg, /* SIOCWFIRSTPRIV+10 */
++#endif
++};
++
++#define IW_PRIV_TYPE_KEY \
++ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key))
++#define IW_PRIV_TYPE_DELKEY \
++ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key))
++#define IW_PRIV_TYPE_MLME \
++ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme))
++#define IW_PRIV_TYPE_ADDPMKID \
++ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid))
++
++static const struct iw_priv_args ar6000_priv_args[] = {
++ { IEEE80211_IOCTL_SETKEY,
++ IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0, "setkey"},
++ { IEEE80211_IOCTL_DELKEY,
++ IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0, "delkey"},
++ { IEEE80211_IOCTL_SETPARAM,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setparam"},
++ { IEEE80211_IOCTL_GETPARAM,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getparam"},
++ { IEEE80211_IOCTL_SETWMMPARAMS,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0, "setwmmparams"},
++ { IEEE80211_IOCTL_GETWMMPARAMS,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getwmmparams"},
++ { IEEE80211_IOCTL_ADDPMKID,
++ IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0, "addpmkid"},
++};
++
++static void
++ar6000_ioctl_iwsetup(struct iw_handler_def *def)
++{
++#define N(a) (sizeof(a) / sizeof(a[0]))
++ def->private_args = (struct iw_priv_args *)ar6000_priv_args;
++ def->num_private_args = N(ar6000_priv_args);
++#undef N
++}
++
++static struct iw_handler_def ath_iw_handler_def = {
++#define N(a) (sizeof (a) / sizeof (a[0]))
++ .standard = (iw_handler *)ath_handlers,
++ .num_standard = N(ath_handlers),
++ .private = (iw_handler *)ath_priv_handlers,
++ .num_private = N(ath_priv_handlers),
++ .get_wireless_stats = ar6000_get_iwstats,
++#undef N
++};
++
++void *
++a_netbuf_alloc(int size)
++{
++ struct sk_buff *skb;
++
++ skb = dev_alloc_skb(AR6000_DATA_OFFSET + size);
++ skb_reserve(skb, AR6000_DATA_OFFSET);
++
++ return ((void *)skb);
++}
++
++void
++a_netbuf_free(void *bufPtr)
++{
++ struct sk_buff *skb = (struct sk_buff *)bufPtr;
++
++ dev_kfree_skb(skb);
++}
++
++A_UINT32
++a_netbuf_to_len(void *bufPtr)
++{
++ return (((struct sk_buff *)bufPtr)->len);
++}
++
++void *
++a_netbuf_to_data(void *bufPtr)
++{
++ return (((struct sk_buff *)bufPtr)->data);
++}
++
++/*
++ * Add len # of bytes to the beginning of the network buffer
++ * pointed to by bufPtr
++ */
++A_STATUS
++a_netbuf_push(void *bufPtr, A_INT32 len)
++{
++ skb_push((struct sk_buff *)bufPtr, len);
++
++ return A_OK;
++}
++
++/*
++ * Add len # of bytes to the end of the network buffer
++ * pointed to by bufPtr
++ */
++A_STATUS
++a_netbuf_put(void *bufPtr, A_INT32 len)
++{
++ skb_put((struct sk_buff *)bufPtr, len);
++
++ return A_OK;
++}
++
++/*
++ * Trim the network buffer pointed to by bufPtr to len # of bytes
++ */
++A_STATUS
++a_netbuf_trim(void *bufPtr, A_INT32 len)
++{
++ skb_trim((struct sk_buff *)bufPtr, len);
++
++ return A_OK;
++}
++
++/*
++ * Returns the number of bytes available to a a_netbuf_push()
++ */
++A_INT32
++a_netbuf_headroom(void *bufPtr)
++{
++ return (skb_headroom((struct sk_buff *)bufPtr));
++}
++
++/*
++ * Removes specified number of bytes from the beginning of the buffer
++ */
++A_STATUS
++a_netbuf_pull(void *bufPtr, A_INT32 len)
++{
++ skb_pull((struct sk_buff *)bufPtr, len);
++
++ return A_OK;
++}
++
++A_UINT32
++a_copy_to_user(void *to, const void *from, A_UINT32 n)
++{
++ return(copy_to_user(to, from, n));
++}
++
++A_UINT32
++a_copy_from_user(void *to, const void *from, A_UINT32 n)
++{
++ return(copy_from_user(to, from, n));
++}
++
++/* Get power mode command */
++static int
++ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
++{
++ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
++ WMI_POWER_MODE_CMD power_mode;
++ int ret = 0;
++
++ if (ar->arWmiReady == FALSE) {
++ return -EIO;
++ }
++
++ power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
++ if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
++ ret = -EFAULT;
++ }
++
++ return ret;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/bmi.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/bmi.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,473 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines that implement the Boot loader messaging
++ * interface
++ */
++
++#include "../include/hif.h"
++#include "../include/bmi.h"
++#include "../include/htc.h"
++#include "bmi_internal.h"
++
++/*
++Although we had envisioned BMI to run on top of HTC, this is not what the
++final implementation boiled down to on dragon. Its a part of BSP and does
++not use the HTC protocol either. On the host side, however, we were still
++living with the original idea. I think the time has come to accept the truth
++and separate it from HTC which has been carrying BMI's burden all this while.
++It shall make HTC state machine relatively simpler
++*/
++
++/* ------ Static Variables ------ */
++
++/* ------ Global Variable Declarations ------- */
++A_BOOL bmiDone;
++extern A_UINT32 debugbmi;
++
++#ifdef DEBUG
++#define AR_DEBUG_PRINTF(...) if (debugbmi) A_PRINTF(__VA_ARGS__);
++#else
++#define AR_DEBUG_PRINTF(...)
++#endif
++
++/* APIs visible to the driver */
++void
++BMIInit(void)
++{
++ bmiDone = FALSE;
++}
++
++A_STATUS
++BMIDone(HIF_DEVICE *device)
++{
++ A_STATUS status;
++ A_UINT32 cid;
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF("BMI Done: Enter (device: 0x%p)\n", device);
++ bmiDone = TRUE;
++ cid = BMI_DONE;
++
++ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++ AR_DEBUG_PRINTF("BMI Done: Exit\n");
++
++ return A_OK;
++}
++
++A_STATUS
++BMIGetTargetId(HIF_DEVICE *device, A_UINT32 *id)
++{
++ A_STATUS status;
++ A_UINT32 cid;
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF("BMI Get Target ID: Enter (device: 0x%p)\n", device);
++ cid = BMI_GET_TARGET_ID;
++
++ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++
++ status = bmiBufferReceive(device, (A_UCHAR *)id, sizeof(*id));
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to read from the device\n");
++ return A_ERROR;
++ }
++ AR_DEBUG_PRINTF("BMI Get Target ID: Exit (ID: 0x%x)\n", *id);
++
++ return A_OK;
++}
++
++A_STATUS
++BMIReadMemory(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ A_UINT32 remaining, rxlen;
++ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
++ A_UCHAR data[BMI_DATASZ_MAX + header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
++ device, address, length);
++
++ cid = BMI_READ_MEMORY;
++
++ remaining = length;
++ while (remaining)
++ {
++ rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen));
++ offset += sizeof(length);
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++ status = bmiBufferReceive(device, data, rxlen);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to read from the device\n");
++ return A_ERROR;
++ }
++ A_MEMCPY(&buffer[length - remaining], data, rxlen);
++ remaining -= rxlen; address += rxlen;
++ }
++
++ AR_DEBUG_PRINTF("BMI Read Memory: Exit\n");
++ return A_OK;
++}
++
++A_STATUS
++BMIWriteMemory(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ A_UINT32 remaining, txlen;
++ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
++ A_UCHAR data[BMI_DATASZ_MAX + header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
++ device, address, length);
++
++ cid = BMI_WRITE_MEMORY;
++
++ remaining = length;
++ while (remaining)
++ {
++ txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
++ remaining : (BMI_DATASZ_MAX - header);
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ A_MEMCPY(&data[offset], &txlen, sizeof(txlen));
++ offset += sizeof(txlen);
++ A_MEMCPY(&data[offset], &buffer[length - remaining], txlen);
++ offset += txlen;
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++ remaining -= txlen; address += txlen;
++ }
++
++ AR_DEBUG_PRINTF("BMI Write Memory: Exit\n");
++
++ return A_OK;
++}
++
++A_STATUS
++BMIExecute(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 *param)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(*param);
++ A_UCHAR data[header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
++ device, address, *param);
++
++ cid = BMI_EXECUTE;
++
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ A_MEMCPY(&data[offset], param, sizeof(*param));
++ offset += sizeof(*param);
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++
++ status = bmiBufferReceive(device, data, sizeof(*param));
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to read from the device\n");
++ return A_ERROR;
++ }
++
++ A_MEMCPY(param, data, sizeof(*param));
++
++ AR_DEBUG_PRINTF("BMI Execute: Exit (param: %d)\n", *param);
++ return A_OK;
++}
++
++A_STATUS
++BMISetAppStart(HIF_DEVICE *device,
++ A_UINT32 address)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ const A_UINT32 header = sizeof(cid) + sizeof(address);
++ A_UCHAR data[header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
++ device, address);
++
++ cid = BMI_SET_APP_START;
++
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF("BMI Set App Start: Exit\n");
++ return A_OK;
++}
++
++A_STATUS
++BMIReadSOCRegister(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 *param)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ const A_UINT32 header = sizeof(cid) + sizeof(address);
++ A_UCHAR data[header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
++ device, address);
++
++ cid = BMI_READ_SOC_REGISTER;
++
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++
++ status = bmiBufferReceive(device, data, sizeof(*param));
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to read from the device\n");
++ return A_ERROR;
++ }
++ A_MEMCPY(param, data, sizeof(*param));
++
++ AR_DEBUG_PRINTF("BMI Read SOC Register: Exit (value: %d)\n", *param);
++ return A_OK;
++}
++
++A_STATUS
++BMIWriteSOCRegister(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UINT32 param)
++{
++ A_UINT32 cid;
++ A_STATUS status;
++ A_UINT32 offset;
++ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(param);
++ A_UCHAR data[header];
++
++ if (bmiDone) {
++ AR_DEBUG_PRINTF("Command disallowed\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF(
++ "BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
++ device, address, param);
++
++ cid = BMI_WRITE_SOC_REGISTER;
++
++ offset = 0;
++ A_MEMCPY(&data[offset], &cid, sizeof(cid));
++ offset += sizeof(cid);
++ A_MEMCPY(&data[offset], &address, sizeof(address));
++ offset += sizeof(address);
++ A_MEMCPY(&data[offset], ¶m, sizeof(param));
++ offset += sizeof(param);
++ status = bmiBufferSend(device, data, offset);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to write to the device\n");
++ return A_ERROR;
++ }
++
++ AR_DEBUG_PRINTF("BMI Read SOC Register: Exit\n");
++ return A_OK;
++}
++
++/* BMI Access routines */
++A_STATUS
++bmiBufferSend(HIF_DEVICE *device,
++ A_UCHAR *buffer,
++ A_UINT32 length)
++{
++ A_STATUS status;
++ A_UINT32 timeout;
++ A_UINT32 address;
++ A_UCHAR cmdCredits;
++ HIF_REQUEST request;
++ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
++
++ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
++ &mboxAddress, sizeof(mboxAddress));
++
++ cmdCredits = 0;
++ timeout = BMI_COMMUNICATION_TIMEOUT;
++ while(timeout-- && !cmdCredits) {
++ /* Read the counter register to get the command credits */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
++ status = HIFReadWrite(device, address, &cmdCredits, 1,
++ &request, NULL);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to decrement the command credit count register\n");
++ return A_ERROR;
++ }
++ }
++
++ if (cmdCredits) {
++ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
++ HIF_SYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_INCREMENTAL_ADDRESS);
++ address = mboxAddress[ENDPOINT1];
++ status = HIFReadWrite(device, address, buffer, length, &request, NULL);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to send the BMI data to the device\n");
++ return A_ERROR;
++ }
++ } else {
++ AR_DEBUG_PRINTF("BMI Communication timeout\n");
++ return A_ERROR;
++ }
++
++ return status;
++}
++
++A_STATUS
++bmiBufferReceive(HIF_DEVICE *device,
++ A_UCHAR *buffer,
++ A_UINT32 length)
++{
++ A_STATUS status;
++ A_UINT32 address;
++ A_UINT32 timeout;
++ A_UCHAR cmdCredits;
++ HIF_REQUEST request;
++ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
++
++ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
++ &mboxAddress, sizeof(mboxAddress));
++
++ cmdCredits = 0;
++ timeout = BMI_COMMUNICATION_TIMEOUT;
++ while(timeout-- && !cmdCredits) {
++ /* Read the counter register to get the command credits */
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
++ HIF_BYTE_BASIS, HIF_FIXED_ADDRESS);
++ address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
++ status = HIFReadWrite(device, address, &cmdCredits, sizeof(cmdCredits),
++ &request, NULL);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to decrement the command credit count register\n");
++ return A_ERROR;
++ }
++ status = A_ERROR;
++ }
++
++ if (cmdCredits) {
++ HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO,
++ HIF_SYNCHRONOUS, HIF_BYTE_BASIS,
++ HIF_INCREMENTAL_ADDRESS);
++ address = mboxAddress[ENDPOINT1];
++ status = HIFReadWrite(device, address, buffer, length, &request, NULL);
++ if (status != A_OK) {
++ AR_DEBUG_PRINTF("Unable to read the BMI data from the device\n");
++ return A_ERROR;
++ }
++ } else {
++ AR_DEBUG_PRINTF("BMI Communication timeout\n");
++ return A_ERROR;
++ }
++
++ return status;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_SDIO_AR6000_WLAN) += hif.o
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,11 @@
++#
++# hif for compact flash
++#
++#EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/include
++#EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/../include
++#EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/os/linux/include
++#
++#EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/hif/cf/linux/include \
++# -DEXPORT_SYMTAB -D__KERNEL__ -DLINUX -DDEBUG
++
++obj-m := ar6000_cs.o
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1001 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * It also includes code from the Linux PCMCIA package, (C) David Hinds.
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++#include <linux/config.h>
++#ifdef __IN_PCMCIA_PACKAGE__
++#include <pcmcia/k_compat.h>
++#endif /* __IN_PCMCIA_PACKAGE__ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/ptrace.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/ioport.h>
++#include <linux/wireless.h>
++#include <linux/interrupt.h>
++
++#include <pcmcia/version.h>
++#include <pcmcia/cs_types.h>
++#include <pcmcia/cs.h>
++#include <pcmcia/cistpl.h>
++#include <pcmcia/cisreg.h>
++#include <pcmcia/ds.h>
++
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/system.h>
++
++#include "ar6000_cs_internal.h"
++
++/********************************************************************/
++/* Module stuff */
++/********************************************************************/
++
++MODULE_DESCRIPTION("Driver for Atheros PCMCIA WLAN Card");
++
++#define CS_CHECK(fn, ret) \
++do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
++
++/*
++ * The dev_info variable is the "key" that is used to match up this
++ * device driver with appropriate cards, through the card
++ * configuration database.
++ */
++static dev_info_t dev_info = "ar6000_cs";
++
++/*
++ * A linked list of "instances" of the device. Each actual PCMCIA
++ * card corresponds to one device instance, and is described by one
++ * dev_link_t structure (defined in ds.h).
++ */
++static dev_link_t *dev_list;
++
++/* List of upper driver instances */
++static CFFUNCTION *drv_list;
++
++static struct rw_semaphore dev_lock;
++static struct rw_semaphore drv_lock;
++
++static struct work_struct hotPlugTask;
++
++#ifdef DEBUG
++A_UINT32 debugbusdrv=0;
++enum {
++ ATH_LOG_SEND = 0x0001,
++ ATH_LOG_RECV = 0x0002,
++ ATH_LOG_SYNC = 0x0004,
++ ATH_LOG_DUMP = 0x0008,
++ ATH_LOG_INF = 0x0010,
++ ATH_LOG_TRC = 0x0020,
++ ATH_LOG_WARN = 0x0040,
++ ATH_LOG_ERR = 0x0080,
++ ATH_LOG_ANY = 0xFFFF,
++};
++
++#define BUSDRV_DEBUG_PRINTF(flag, args...) do { \
++ if (debugbusdrv) { \
++ printk(KERN_ALERT args); \
++ } \
++} while (0)
++#endif //DEBUG
++
++/********************************************************************/
++/* Function prototypes */
++/********************************************************************/
++
++static void ar6000_cs_config(dev_link_t * link);
++static void ar6000_cs_release(dev_link_t * link);
++static int ar6000_cs_event(event_t event, int priority,
++ event_callback_args_t * args);
++
++static dev_link_t *ar6000_cs_attach(void);
++static void ar6000_cs_detach(dev_link_t *);
++
++/********************************************************************
++* API exposed to Upper layer.
++********************************************************************/
++/* Go thru the list of devices maintained in this layer and if it
++* matches the upper layer module, call the module's probe function.
++* Also pass a device's instance as an opaque reference to the upper
++* layer module.
++*/
++CF_STATUS CF_RegisterFunction(PCFFUNCTION pFunction) {
++ struct dev_link_t *ptr = NULL;
++ CF_DEVICE *pCfDevice = NULL;
++ PCF_PNP_INFO pnpPtr = NULL;
++ CF_STATUS status = CF_STATUS_SUCCESS;
++
++ //Insert the upper layer driver ctx in the list maintained in this layer.
++ insert_drv_list(pFunction);
++
++ // Acquire Lock
++ down_read(&dev_lock);
++
++ //traverse the dev_link_t list
++ for ( ptr=dev_list; (ptr); ptr=ptr->next ) {
++
++ /* check if ptr->priv->pCfDevice.pId matches that provided by the
++ * upper layer If so insert the pFunction ctx into that devices
++ * function list. and call that devices probe function & return.
++ */
++ pCfDevice = (CF_DEVICE *)&(((struct ar6000_pccard *)(ptr->priv))->CfDevice);
++ // Go thru the list of PNP Ids & if any of them match, call probe().
++ /* Check for NULL Manf-Code to traverse the Pnp List that is
++ * null terminated.
++ */
++
++ for ( pnpPtr = pFunction->pIds; pnpPtr->CF_ManufacturerCode != 0 ; \
++ pnpPtr++ ) {
++
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "CFRegisterFunc b4 manfid comp %04x, %04x\n", pCfDevice->pId.CF_ManufacturerID, pnpPtr->CF_ManufacturerID);
++
++ if( pCfDevice->pId.CF_ManufacturerID == pnpPtr->CF_ManufacturerID )
++ {
++ pCfDevice->pFunction = pFunction;
++ if ( !((*pFunction->pProbe)(pFunction, pCfDevice)) ) {
++ /* The device is not successfuly probed by this
++ * fuction driver. disassociate them.
++ */
++ pCfDevice->pFunction = NULL;
++ status = CF_STATUS_ERROR;
++ }
++ status = CF_STATUS_SUCCESS;
++ break;
++ }
++ }
++ }
++ up_read(&dev_lock);
++ return status;
++}
++
++CF_STATUS CF_UnregisterFunction(PCFFUNCTION pFunction) {
++
++ /* Release the device structure if a card is present or else
++ * remove the function instance from the FuncList
++ */
++ struct dev_link_t *ptr = NULL;
++ CF_DEVICE *pCfDevice = NULL;
++ PCF_PNP_INFO pnpPtr = NULL;
++
++ down_read(&dev_lock);
++
++ //traverse the dev_link_t list
++ for ( ptr=dev_list; (ptr); ptr=ptr->next ) {
++
++ /* check if ptr->priv->pCfDevice.pId matches that provided by the
++ * upper layer If so remove the association between the device and the
++ * upper layer driver.
++ */
++ pCfDevice = (CF_DEVICE *)&(((struct ar6000_pccard *)(ptr->priv))->CfDevice);
++ for ( pnpPtr = pFunction->pIds; pnpPtr->CF_ManufacturerCode != 0 ; \
++ pnpPtr++ ) {
++
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "CF_UnRegisterFunc manfid comp %04x, %04x\n", pCfDevice->pId.CF_ManufacturerID, pFunction->pIds->CF_ManufacturerID);
++
++ if( pCfDevice->pId.CF_ManufacturerID == pnpPtr->CF_ManufacturerID)
++ {
++ pCfDevice->pFunction = NULL;
++ break;
++ }
++ }
++ }
++ up_read(&dev_lock);
++ remove_drv_list(pFunction);
++ return CF_STATUS_SUCCESS;
++}
++
++static CF_STATUS ar6000_cs_read_byte(CF_DEVICE *pDev, PCFREQUEST pReq) {
++
++ A_UINT32 len = pReq->length;
++ A_UCHAR *buff = pReq->pDataBuffer;
++ A_UINT32 ctr=0;
++ A_UCHAR *port = ((A_UCHAR *)pDev->mem_start) + pReq->address;
++
++ for (ctr=0;ctr<len;ctr++) {
++ *buff = readb(port);
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP, "R: data: %x, address: %p\n",*buff,port);
++ buff++;
++ if (!(pReq->Flags & CFREQ_FLAGS_FIXED_ADDRESS))
++ port += 1;
++ }
++
++ return CF_STATUS_SUCCESS;
++}
++
++static CF_STATUS ar6000_cs_write_byte(CF_DEVICE *pDev, PCFREQUEST pReq) {
++
++ A_UINT32 ctr = 0;
++ A_UINT32 len = pReq->length;
++ A_UCHAR *buff = pReq->pDataBuffer;
++ A_UCHAR *port = ((A_UCHAR *)pDev->mem_start) + pReq->address;
++
++ for (ctr=0;ctr<len;ctr++) {
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP, "W: data: %x, address: %p\n",*buff,port);
++ writeb(*buff, port);
++ buff++;
++ if (!(pReq->Flags & CFREQ_FLAGS_FIXED_ADDRESS))
++ port += 1;
++ }
++
++ return CF_STATUS_SUCCESS;
++}
++
++static CF_STATUS ar6000_cs_read_word(CF_DEVICE *pDev, PCFREQUEST pReq) {
++
++ A_UINT32 len = pReq->length;
++ A_UINT16 *buff = pReq->pDataBuffer;
++ A_UINT32 ctr=0;
++ A_UCHAR *port = ((A_UCHAR *)pDev->mem_start) + pReq->address;
++
++ for (ctr=0;(ctr+1)<len;) {
++ *buff = readw(port);
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP,"R: data: %x, address: %p\n",*buff,port);
++ buff++;
++ if (!(pReq->Flags & CFREQ_FLAGS_FIXED_ADDRESS))
++ port += 2;
++ ctr += 2;
++ }
++
++ //Read the last byte
++ if ( ctr < len ) {
++ *((unsigned char *)buff) = readb(port);
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP,"R: data: %x, address: %p\n",*((unsigned char *)buff),port);
++ }
++
++ return CF_STATUS_SUCCESS;
++}
++
++static CF_STATUS ar6000_cs_write_word(CF_DEVICE *pDev, PCFREQUEST pReq) {
++
++ A_UINT32 ctr = 0;
++ A_UINT32 len = pReq->length;
++ A_UINT16 *buff = pReq->pDataBuffer;
++ A_UCHAR *port = ((A_UCHAR *)pDev->mem_start) + pReq->address;
++
++ for (ctr=0;(ctr+1)<len;) {
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP,"W: data: %x, address: %p\n",*buff,port);
++ writew(*buff, port);
++ buff++;
++ if (!(pReq->Flags & CFREQ_FLAGS_FIXED_ADDRESS))
++ port += 2;
++ ctr += 2;
++ }
++
++ // Write the last byte
++ if ( ctr < len ) {
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_DUMP,"W: data: %x, address: %p\n",*((unsigned char *)buff),port);
++ writeb(*((unsigned char *)buff), port);
++ }
++
++ return CF_STATUS_SUCCESS;
++}
++
++
++CF_STATUS CF_BusRequest_Word(PCFDEVICE pDev, PCFREQUEST pReq)
++{
++ CF_STATUS status;
++
++ if ( pReq->Flags & CFREQ_FLAGS_DATA_WRITE ) {
++ status = ar6000_cs_write_word((CF_DEVICE *)pDev, pReq);
++ } else {
++ status = ar6000_cs_read_word((CF_DEVICE *)pDev, pReq);
++ }
++
++ return status;
++}
++
++CF_STATUS CF_BusRequest_Byte(PCFDEVICE pDev, PCFREQUEST pReq)
++{
++ CF_STATUS status;
++
++ if ( pReq->Flags & CFREQ_FLAGS_DATA_WRITE ) {
++ status = ar6000_cs_write_byte((CF_DEVICE *)pDev, pReq);
++ } else {
++ status = ar6000_cs_read_byte((CF_DEVICE *)pDev, pReq);
++ }
++
++ return status;
++}
++
++void CF_SetIrqHandler(PCFDEVICE pDev, pIsrHandler pFn1, pDsrHandler pFn2, void * pContext) {
++ ((CF_DEVICE *)pDev)->pIrqFunction = (pFn1);
++ ((CF_DEVICE *)pDev)->IrqContext = (void *)(pContext);
++ if (pFn2) {
++ tasklet_init(&(((CF_DEVICE *)pDev)->tasklet),pFn2,(unsigned long)pContext);
++ }
++}
++
++/********************************************************************/
++/* PCMCIA stuff */
++/********************************************************************/
++
++/* For 2.4 kernels, cs_error is not exported. providing our own...*/
++static void
++ar6000_cs_error(client_handle_t handle, int func, int ret)
++{
++ error_info_t err = { func, ret };
++ pcmcia_report_error(handle, &err);
++}
++
++/* Device List manipulation routines */
++static void insert_dev_list(struct ar6000_pccard *dev)
++{
++ dev_link_t *temp=NULL;
++
++ down_write(&dev_lock);
++
++ //Check for empty dev list.
++ if(!dev_list) {
++ dev_list = &dev->link;
++ } else {
++ //traverse to the end of the list.
++ for(temp=dev_list;(temp->next);temp=temp->next);
++ temp->next = &dev->link;
++ }
++ up_write(&dev_lock);
++ return;
++}
++
++static struct dev_link_t * remove_dev_list(struct ar6000_pccard *dev)
++{
++ struct dev_link_t *curr,*prev;
++ curr = prev = NULL;
++
++ down_write(&dev_lock);
++
++ for(curr=prev=dev_list;(curr);prev=curr,curr=curr->next) {
++ if(curr->priv == dev) {
++ if(curr!=prev)
++ prev->next = curr->next;
++ else
++ dev_list = curr->next;
++ break;
++ }
++ }
++ up_write(&dev_lock);
++ return curr;
++}
++
++/* Upper driver instance list manipulation routines
++*/
++static void insert_drv_list(PCFFUNCTION pFunction) {
++
++ CFFUNCTION *temp=NULL;
++
++ down_write(&drv_lock);
++
++ //Check for empty dev list.
++ if(!drv_list) {
++ drv_list = pFunction;
++ } else {
++ //traverse to the end of the list.
++ for(temp=drv_list;(temp->next);temp=temp->next);
++ temp->next = pFunction;
++ }
++ pFunction->next = NULL;
++ up_write(&drv_lock);
++ return;
++}
++
++static PCFFUNCTION remove_drv_list(PCFFUNCTION pFunction)
++{
++ CFFUNCTION *curr,*prev;
++ curr = prev = NULL;
++
++ down_write(&drv_lock);
++
++ for(curr=prev=drv_list;(curr);prev=curr,curr=curr->next) {
++ if(curr == pFunction) {
++ if(curr!=prev)
++ prev->next = curr->next;
++ else
++ drv_list = curr->next;
++ break;
++ }
++ }
++ up_write(&drv_lock);
++ return curr;
++}
++
++/*
++ * Create an instance of the card and register with Card Services.
++ */
++static dev_link_t *
++ar6000_cs_attach(void)
++{
++ struct ar6000_pccard *info;
++ dev_link_t *link;
++ client_reg_t client_reg;
++ A_UINT32 ret;
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Enter - ar6000_cs_attach\n");
++
++ /* Create new device */
++ info = A_MALLOC(sizeof(struct ar6000_pccard));
++ if (!info) return NULL;
++ A_MEMZERO(info, sizeof(*info));
++ link = &info->link; link->priv = info;
++
++ /* Initialize the CF device structure */
++ info->CfDevice.backPtr = link;
++
++ /* Interrupt setup */
++ link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
++ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
++ link->irq.Handler = NULL;
++
++ link->conf.Attributes = 0;
++ link->conf.IntType = INT_MEMORY_AND_IO;
++
++ /* Insert into the global devlist */
++ insert_dev_list(info);
++
++ /* Register with Card Services */
++ client_reg.dev_info = &dev_info;
++ client_reg.Attributes = INFO_IO_CLIENT | INFO_CARD_SHARE;
++ client_reg.EventMask =
++ CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
++ CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
++ CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
++ client_reg.event_handler = &ar6000_cs_event;
++ client_reg.Version = 0x0210; /* FIXME: what does this mean? */
++ client_reg.event_callback_args.client_data = link;
++
++ ret = pcmcia_register_client(&link->handle, &client_reg);
++ if (ret != CS_SUCCESS) {
++ ar6000_cs_error(link->handle, RegisterClient, ret);
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_ERR, "pcmcia register failed\n");
++ ar6000_cs_detach(link);
++ return NULL;
++ }
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Exit - ar6000_cs_attach\n");
++
++ return link;
++} /* ar6000_cs_attach */
++
++/*
++ * Deregister with card services & free the device structure.
++ */
++static void
++ar6000_cs_detach(dev_link_t * link)
++{
++ CF_DEVICE *pCfDevice = NULL;
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Enter - ar6000_cs_detach\n");
++
++ /* Call the pRemove function of the top level driver */
++ pCfDevice = (CF_DEVICE *)&(((struct ar6000_pccard *)(link->priv))->CfDevice);
++ if (pCfDevice->pFunction) {
++ (*pCfDevice->pFunction->pRemove)(pCfDevice->pFunction, pCfDevice);
++ pCfDevice->pFunction = NULL;
++ }
++
++ if (link->state & DEV_CONFIG)
++ ar6000_cs_release(link);
++
++ /* Unregister with Card Services */
++ if (link->handle)
++ pcmcia_deregister_client(link->handle);
++
++ /* Unlink device structure, and free it */
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "ar6000_cs: detach: link=%p link->dev=%p\n", link, link->dev);
++
++ remove_dev_list(link->priv);
++ A_FREE(link->priv);
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Exit - ar6000_cs_detach\n");
++} /* ar6000_cs_detach */
++
++static irqreturn_t ar6000_interrupt(A_UINT32 irq, void *dev_id, struct pt_regs *regs)
++{
++ struct ar6000_pccard *card = (struct ar6000_pccard *)dev_id;
++ A_BOOL callDSR;
++
++ //Call the Interrupt handler registered by the upper layer
++ if (card->CfDevice.pFunction && card->CfDevice.pIrqFunction)
++ (*(card->CfDevice.pIrqFunction))(card->CfDevice.IrqContext, &callDSR);
++
++ /* Schedule a tasklet & return */
++ if (card->CfDevice.pFunction && card->CfDevice.pIrqFunction && callDSR)
++ tasklet_hi_schedule(&card->CfDevice.tasklet);
++
++ return IRQ_HANDLED;
++}
++
++#ifdef POLLED_MODE
++static void ar6000_interrupt_wrapper(unsigned long dev_id)
++{
++ struct ar6000_pccard *card = (struct ar6000_pccard *)dev_id;
++
++ //Call the Interrupt handler registered by the upper layer
++ if (card->CfDevice.pIrqFunction)
++ (*(card->CfDevice.pIrqFunction))(card->CfDevice.IrqContext);
++
++ card->poll_timer.expires = jiffies + HZ;
++ add_timer(&card->poll_timer);
++}
++#endif
++
++static A_UINT32 mem_speed = 0;
++
++/*
++ * ar6000_cs_config() is scheduled to run after a CARD_INSERTION
++ * event is received, to configure the PCMCIA socket, and to make the
++ * device available to the system.
++ */
++
++static void
++ar6000_cs_config(dev_link_t *link)
++{
++ client_handle_t handle = link->handle;
++ struct ar6000_pccard *card = link->priv;
++ A_UINT32 last_fn, last_ret;
++ A_UCHAR buf[64];
++ config_info_t conf;
++ cisinfo_t info;
++ tuple_t tuple;
++ cisparse_t parse;
++ win_req_t req;
++ memreq_t mem;
++ A_UINT32 status;
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Enter ar6000_cs_config\n");
++
++ CS_CHECK(ValidateCIS, pcmcia_validate_cis(handle, &info));
++
++ /*
++ * This reads the card's CONFIG tuple to find its
++ * configuration registers.
++ */
++ tuple.DesiredTuple = CISTPL_CONFIG;
++ tuple.Attributes = 0;
++ tuple.TupleData = buf;
++ tuple.TupleDataMax = sizeof(buf);
++ tuple.TupleOffset = 0;
++ CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
++ CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
++ CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
++ link->conf.ConfigBase = parse.config.base;
++ link->conf.Present = parse.config.rmask[0];
++
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "link->conf.ConfigBase: %04x, \
++ link->conf.Present: %0x\n", link->conf.ConfigBase,
++ link->conf.Present);
++
++ /*Read the card's manf-id, manf-code, func no & func class
++ * and initialize the device structure
++ */
++ tuple.DesiredTuple = CISTPL_MANFID;
++ CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
++ CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
++ CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
++
++ card->CfDevice.pId.CF_ManufacturerID = parse.manfid.card;
++ card->CfDevice.pId.CF_ManufacturerCode = parse.manfid.manf;
++
++ /*TODO: change this tuple.DesiredTuple = CISTPL_FUNCNO;
++ CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
++ CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
++ CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
++
++ card->CfDevice.pId.CF_FunctionNo = parse.manfid.manf;
++ */
++
++ /* Configure card */
++ link->state |= DEV_CONFIG;
++
++ /* Look up the current Vcc */
++ CS_CHECK(GetConfigurationInfo, pcmcia_get_configuration_info(handle, &conf));
++ link->conf.Vcc = conf.Vcc;
++
++ /*
++ * In this loop, we scan the CIS for configuration table
++ * entries, each of which describes a valid card
++ * configuration, including voltage, IO window, memory window,
++ * and interrupt settings.
++ *
++ * We make no assumptions about the card to be configured: we
++ * use just the information available in the CIS. In an ideal
++ * world, this would work for any PCMCIA card, but it requires
++ * a complete and accurate CIS. In practice, a driver usually
++ * "knows" most of these things without consulting the CIS,
++ * and most client drivers will only use the CIS to fill in
++ * implementation-defined details.
++ */
++ tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
++ CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
++ while (1) {
++ cistpl_cftable_entry_t *cfg = &(parse.cftable_entry);
++ cistpl_cftable_entry_t dflt = { .index = 0 };
++
++ if (pcmcia_get_tuple_data(handle, &tuple) != 0 ||
++ pcmcia_parse_tuple(handle, &tuple, &parse) != 0)
++ goto next_entry;
++
++ if (cfg->flags & CISTPL_CFTABLE_DEFAULT)
++ dflt = *cfg;
++ if (cfg->index == 0)
++ goto next_entry;
++ link->conf.ConfigIndex = cfg->index;
++
++ /* Does this card need audio output? */
++ if (cfg->flags & CISTPL_CFTABLE_AUDIO) {
++ link->conf.Attributes |= CONF_ENABLE_SPKR;
++ link->conf.Status = CCSR_AUDIO_ENA;
++ }
++
++ /* Use power settings for Vcc and Vpp if present */
++ /* Note that the CIS values need to be rescaled */
++ /*
++ if (cfg->vcc.present & (1 << CISTPL_POWER_VNOM)) {
++ if (conf.Vcc != cfg->vcc.param[CISTPL_POWER_VNOM] / 10000) {
++ if (!ignore_cis_vcc)
++ goto next_entry;
++ }
++ } else if (dflt.vcc.present & (1 << CISTPL_POWER_VNOM)) {
++ if (conf.Vcc != dflt.vcc.param[CISTPL_POWER_VNOM] / 10000) {
++ if(!ignore_cis_vcc)
++ goto next_entry;
++ }
++ }
++
++ if (cfg->vpp1.present & (1 << CISTPL_POWER_VNOM))
++ link->conf.Vpp1 = link->conf.Vpp2 =
++ cfg->vpp1.param[CISTPL_POWER_VNOM] / 10000;
++ else if (dflt.vpp1.present & (1 << CISTPL_POWER_VNOM))
++ link->conf.Vpp1 = link->conf.Vpp2 =
++ dflt.vpp1.param[CISTPL_POWER_VNOM] / 10000;
++ */
++
++ /* Do we need to allocate an interrupt? */
++ if (cfg->irq.IRQInfo1 || dflt.irq.IRQInfo1)
++ link->conf.Attributes |= CONF_ENABLE_IRQ;
++
++ /* IO window settings */
++ link->io.NumPorts1 = link->io.NumPorts2 = 0;
++ if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
++ cistpl_io_t *io =
++ (cfg->io.nwin) ? &cfg->io : &dflt.io;
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "io->nwin: %d, io->win[0].base: %d, io->win[0].len: %d\n", io->nwin, io->win[0].base, io->win[0].len);
++
++ link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
++ if (!(io->flags & CISTPL_IO_8BIT))
++ link->io.Attributes1 =
++ IO_DATA_PATH_WIDTH_16;
++ if (!(io->flags & CISTPL_IO_16BIT))
++ link->io.Attributes1 =
++ IO_DATA_PATH_WIDTH_8;
++ link->io.IOAddrLines =
++ io->flags & CISTPL_IO_LINES_MASK;
++ link->io.BasePort1 = io->win[0].base;
++ link->io.NumPorts1 = io->win[0].len;
++ if (io->nwin > 1) {
++ link->io.Attributes2 =
++ link->io.Attributes1;
++ link->io.BasePort2 = io->win[1].base;
++ link->io.NumPorts2 = io->win[1].len;
++ }
++ /* This reserves IO space but doesn't actually enable it */
++ if (pcmcia_request_io(link->handle, &link->io) != 0)
++ goto next_entry;
++ }
++
++ break;
++
++ next_entry:
++ if (link->io.NumPorts1)
++ pcmcia_release_io(link->handle, &link->io);
++ last_ret = pcmcia_get_next_tuple(handle, &tuple);
++ if (last_ret == CS_NO_MORE_ITEMS) {
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "GetNextTuple(). No matching CIS configuration, "
++ "maybe you need the ignore_cis_vcc=1 parameter.\n");
++ goto cs_failed;
++ }
++ }
++
++ /*
++ * Allocate an interrupt line. Note that this does not assign
++ * a handler to the interrupt, unless the 'Handler' member of
++ * the irq structure is initialized.
++ */
++
++ if (link->conf.Attributes & CONF_ENABLE_IRQ) {
++
++ link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
++ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
++
++ link->irq.Handler = ar6000_interrupt;
++ link->irq.Instance = card;
++
++#ifdef POLLED_MODE
++ init_timer(&card->poll_timer);
++ card->poll_timer.function = ar6000_interrupt_wrapper;
++ card->poll_timer.data = (unsigned long)card;
++ card->poll_timer.expires = jiffies + HZ;
++ add_timer(&card->poll_timer);
++#else
++ CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
++ card->CfDevice.irq = link->irq.AssignedIRQ;
++#endif
++ }
++
++ CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
++
++ /*
++ * Allocate a small memory window. Note that the dev_link_t
++ * structure provides space for one window handle -- if your
++ * device needs several windows, you'll need to keep track of
++ * the handles in your private data structure, link->priv.
++ */
++ req.Attributes = WIN_DATA_WIDTH_16|WIN_MEMORY_TYPE_CM|WIN_ENABLE;
++ req.Base = req.Size = 0;
++ req.AccessSpeed = mem_speed;
++ status = pcmcia_request_window(&link->handle, &req, &link->win);
++ if(status != CS_SUCCESS)
++ {
++#ifdef KERNEL_2_4
++ ar6000_cs_error(link->handle, RequestWindow, status);
++#else
++ cs_error(link->handle, RequestWindow, status);
++#endif
++ goto cs_failed;
++ }
++
++ card->CfDevice.mem_start = (u_long)ioremap(req.Base, req.Size);
++ card->CfDevice.mem_end = card->CfDevice.mem_start + req.Size;
++
++ mem.CardOffset = 0; mem.Page = 0;
++ status = pcmcia_map_mem_page(link->win, &mem);
++ if(status != CS_SUCCESS)
++ {
++#ifdef KERNEL_2_4
++ ar6000_cs_error(link->handle, MapMemPage, status);
++#else
++ cs_error(link->handle, MapMemPage, status);
++ goto cs_failed;
++#endif
++ }
++
++ card->node.major = card->node.minor = 0;
++
++ /* At this point, the dev_node_t structure(s) needs to be
++ * initialized and arranged in a linked list at link->dev. */
++ link->dev = &card->node;
++ /* link->dev being non-NULL is also
++ used to indicate that the
++ net_device has been registered */
++ link->state &= ~DEV_CONFIG_PENDING;
++
++ /* Finally, report what we've done */
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "%s: index 0x%02x: Vcc %d.%d",
++ card->node.dev_name, link->conf.ConfigIndex,
++ link->conf.Vcc / 10, link->conf.Vcc % 10);
++ if (link->conf.Vpp1)
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, ", Vpp %d.%d", link->conf.Vpp1 / 10,
++ link->conf.Vpp1 % 10);
++ if (link->conf.Attributes & CONF_ENABLE_IRQ)
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, ", irq %d", link->irq.AssignedIRQ);
++ if (link->io.NumPorts1)
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, ", io 0x%04x-0x%04x", link->io.BasePort1,
++ link->io.BasePort1 + link->io.NumPorts1 - 1);
++ if (link->io.NumPorts2)
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, " & 0x%04x-0x%04x", link->io.BasePort2,
++ link->io.BasePort2 + link->io.NumPorts2 - 1);
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "\n");
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Exiting ar6000_cs_config\n");
++
++ return;
++
++ cs_failed:
++ ar6000_cs_error(link->handle, last_fn, last_ret);
++
++ ar6000_cs_release(link);
++} /* ar6000_cs_config */
++
++/*
++ * Release the IO/irq resources assigned to this device.
++ */
++static void
++ar6000_cs_release(dev_link_t *link)
++{
++ pcmcia_release_configuration(link->handle);
++ if (link->io.NumPorts1)
++ pcmcia_release_io(link->handle, &link->io);
++ if (link->irq.AssignedIRQ)
++ pcmcia_release_irq(link->handle, &link->irq);
++ link->state &= ~DEV_CONFIG;
++} /* ar6000_cs_release */
++
++static void HotPlugHdlr(void *data)
++{
++ struct ar6000_pccard *card = dev_list->priv;
++ PCF_PNP_INFO pnpPtr = NULL;
++ CF_DEVICE *pCfDevice = &card->CfDevice;
++ A_BOOL isProbed = FALSE;
++ PCFFUNCTION pFunction = NULL;
++
++ /* The above code assumes only 1 card is present. In the case of
++ * multiple cards, we need to get the data ptr to a Queue and from that
++ * Queue get the dev link.
++ */
++ /* Hotplug */
++ for (pFunction = drv_list;(pFunction);pFunction = pFunction->next) {
++
++ /*Determine the CfFunction that has the same PNP info
++ * & call its probe function.
++ */
++ for ( pnpPtr = pFunction->pIds; pnpPtr->CF_ManufacturerCode != 0 ; \
++ pnpPtr++ ) {
++
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "ar6000_cs_event manfid comp %04x, %04x\n", pCfDevice->pId.CF_ManufacturerID, pnpPtr->CF_ManufacturerID);
++
++ if( pCfDevice->pId.CF_ManufacturerID == pnpPtr->CF_ManufacturerID )
++ {
++ pCfDevice->pFunction = pFunction;
++
++ /* delay here for the card to stabilize. BMI Comm.
++ * times out otherwise.
++ */
++ A_MDELAY(1000);
++ if ( !((*pFunction->pProbe)(pFunction, pCfDevice)) ) {
++ /* The device is not successfuly probed by this
++ * fuction driver. disassociate them.
++ */
++ pCfDevice->pFunction = NULL;
++ }
++ isProbed = TRUE;
++ break;
++ }
++ }
++ if (isProbed)
++ break;
++ }
++}
++
++/*
++ * The card status event handler. Mostly, this schedules other stuff
++ * to run after an event is received.
++ */
++static int
++ar6000_cs_event(event_t event, int priority,
++ event_callback_args_t * args)
++{
++ dev_link_t *link = args->client_data;
++ A_UINT32 err = 0;
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "AR6000_CS Event Handler Enter\n");
++
++ switch (event) {
++ case CS_EVENT_CARD_REMOVAL:
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Card Removal Event\n");
++ link->state &= ~DEV_PRESENT;
++ break;
++
++ case CS_EVENT_CARD_INSERTION:
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Card Insertion Event\n");
++
++ link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
++ ar6000_cs_config(link);
++
++ /* Indicate device available to upper drv in a work task Asynchronously
++ */
++ if (drv_list)
++ schedule_work(&hotPlugTask);
++ break;
++
++ case CS_EVENT_PM_SUSPEND:
++ link->state |= DEV_SUSPEND;
++ /* Fall through... */
++ case CS_EVENT_RESET_PHYSICAL:
++ break;
++
++ case CS_EVENT_PM_RESUME:
++ link->state &= ~DEV_SUSPEND;
++ /* Fall through... */
++ case CS_EVENT_CARD_RESET:
++ break;
++ }
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "AR6000_CS Event Handler Exit\n");
++
++ return err;
++} /* ar6000_cs_event */
++
++/********************************************************************/
++/* Module initialization */
++/********************************************************************/
++
++/* Can't be declared "const" or the whole __initdata section will
++ * become const */
++static char version[] __initdata = "ar6000_cs.c 1.0";
++
++#ifndef KERNEL_2_4
++static struct pcmcia_driver ar6000_driver = {
++ .owner = THIS_MODULE,
++ .drv = {
++ .name = "ar6000_cs",
++ },
++ .attach = ar6000_cs_attach,
++ .detach = ar6000_cs_detach,
++};
++#endif
++
++static int __init
++init_ar6000_cs(void)
++{
++ BUSDRV_DEBUG_PRINTF(ATH_LOG_INF, "%s\n", version);
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Enter - init_ar6000_cs");
++
++ /* Init Mutex's */
++ init_rwsem(&dev_lock);
++ init_rwsem(&drv_lock);
++
++ /* We dont pass the data ptr now. Will be useful when multiple
++ * devices are supported to pass a Queue to this
++ */
++ INIT_WORK(&hotPlugTask, HotPlugHdlr, NULL);
++#ifdef KERNEL_2_4
++ return register_pccard_driver("ar6000_cs", &ar6000_cs_attach, &ar6000_cs_detach);
++#else
++ return pcmcia_register_driver(&ar6000_driver);
++#endif
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Exit - init_ar6000_cs");
++}
++
++static void __exit
++exit_ar6000_cs(void)
++{
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Enter - exit_ar6000_cs");
++#ifdef KERNEL_2_4
++ unregister_pccard_driver("ar6000_cs");
++#else
++ pcmcia_unregister_driver(&ar6000_driver);
++#endif
++ //down_read(&dev_lock);
++ while (dev_list != NULL) {
++ if (dev_list->state & DEV_CONFIG)
++ ar6000_cs_release(dev_list);
++ ar6000_cs_detach(dev_list);
++ }
++ //up_read(&dev_lock);
++
++
++
++ BUSDRV_DEBUG_PRINTF(ATH_DEBUG_TRC, "Exit - exit_ar6000_cs");
++}
++
++module_init(init_ar6000_cs);
++module_exit(exit_ar6000_cs);
++
++#ifdef KERNEL_2_4
++MODULE_PARM(debugbusdrv, "i");
++#else
++module_param(debugbusdrv, int, 0644);
++#endif
++EXPORT_SYMBOL(CF_RegisterFunction);
++EXPORT_SYMBOL(CF_UnregisterFunction);
++EXPORT_SYMBOL(CF_SetIrqHandler);
++EXPORT_SYMBOL(CF_BusRequest_Word);
++EXPORT_SYMBOL(CF_BusRequest_Byte);
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,110 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _AR6000_CS_H_
++#define _AR6000_CS_H_
++
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++
++typedef struct _CF_PNP_INFO_ {
++ A_UINT16 CF_ManufacturerCode; /* JEDEC Code */
++ A_UINT16 CF_ManufacturerID; /* manf-specific ID */
++ A_UINT8 CF_FunctionNo; /* function number 1-7 */
++ A_UINT8 CF_FunctionClass; /* function class */
++
++} CF_PNP_INFO, *PCF_PNP_INFO;
++
++//Forward decl
++typedef struct _CFFUNCTION_ *PCFFUNCTION;
++typedef struct _CFREQUEST_ *PCFREQUEST;
++typedef void * PCFDEVICE;
++
++typedef A_INT32 CF_STATUS;
++
++#define CF_SUCCESS(status) ((CF_STATUS)(status) >= 0)
++#define CF_STATUS_SUCCESS 0
++#define CF_STATUS_ERROR -1
++
++/* Structure used by the upper layer to register itself with the
++* device driver.
++*/
++typedef struct _CFFUNCTION_ {
++
++ A_UCHAR *pName; /* name of registering driver */
++ A_UINT8 MaxDevices; /* maximum number of devices supported by this function */
++ A_UINT8 NumDevices; /* number of devices supported by this function */
++
++ /* callback functions provided by the Upper layer module to the driver.
++ */
++ A_BOOL (*pProbe)(struct _CFFUNCTION_ *pFunction, PCFDEVICE pDevice);
++ void (*pRemove)(struct _CFFUNCTION_ *pFunction, PCFDEVICE pDevice);
++
++ /* Currently Unused
++ CF_STATUS (*pSuspend)(struct _CFFUNCTION *pFunction, CFPOWER_STATE state);
++ CF_STATUS (*pResume)(struct _CFFUNCTION *pFunction);
++ CF_STATUS (*pWake) (struct _CFFUNCTION *pFunction, CFPOWER_STATE state, BOOL enable);
++ */
++
++ /* Cookie for the upper layer.
++ */
++ void * pContext;
++ PCF_PNP_INFO pIds; //NULL terminated list of PNP info.
++ struct _CFFUNCTION_ *next; //hanger for the Func ctx list maintained by bus drv.
++
++} CFFUNCTION;
++
++/* CFREQUEST request flags */
++typedef A_UINT8 CFREQUEST_FLAGS;
++
++/* write operation */
++#define CFREQ_FLAGS_DATA_WRITE 0x01
++#define CFREQ_FLAGS_FIXED_ADDRESS 0x02
++
++typedef struct _CFREQUEST_ {
++ void * pDataBuffer; /* starting address of buffer */
++ A_UINT32 address; /* address to which data has to be written */
++ A_UINT32 length; /* length of data to be written */
++ CFREQUEST_FLAGS Flags;
++ void * pCompleteContext; /* completion context */
++ CF_STATUS Status; /* completion status */
++ struct _CFFUNCTION* pFunction; /* function driver that generated request (internal use)*/
++}CFREQUEST;
++
++typedef void (*pIsrHandler)(void *, A_BOOL *);
++typedef void (*pDsrHandler)(unsigned long);
++
++/* API function prototypes
++ */
++CF_STATUS CF_RegisterFunction(PCFFUNCTION pFunction);
++CF_STATUS CF_UnregisterFunction(PCFFUNCTION pFunction);
++CF_STATUS CF_BusRequest_Word(PCFDEVICE, PCFREQUEST);
++CF_STATUS CF_BusRequest_Byte(PCFDEVICE, PCFREQUEST);
++void CF_SetIrqHandler(PCFDEVICE, pIsrHandler, pDsrHandler, void *);
++void CF_MaskIrqHandler(PCFDEVICE);
++void CF_UnMaskIrqHandler(PCFDEVICE);
++
++#define CFDEVICE_SET_IRQ_HANDLER(pDev,pFn1,pFn2,pContext) \
++ CF_SetIrqHandler(pDev,pFn1,pFn2,pContext);
++
++#define CFDEVICE_CALL_REQUESTW_FUNC(pDev, pReq) \
++ CF_BusRequest_Word(pDev, pReq)
++
++#define CFDEVICE_CALL_REQUESTB_FUNC(pDev, pReq) \
++ CF_BusRequest_Byte(pDev, pReq)
++
++#endif
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs_internal.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/ar6000_cs_internal.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,62 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _AR6000_CS_INTERNAL_H_
++#define _AR6000_CS_INTERNAL_H_
++
++#include "ar6000_cs.h"
++
++/* Device structure maintained for each instance of the device
++* in the driver.
++*/
++typedef struct _CFDEVICE_ {
++
++ PCFFUNCTION pFunction; //Upper layer driver supporting this device.
++ CF_PNP_INFO pId; // PNP Info for this device.
++ void (*pIrqFunction)(void * pContext, A_BOOL *callDSR);/* interrupt routine, synchronous calls allowed */
++ void * IrqContext; /* irq context */
++ struct tasklet_struct tasklet;
++
++ A_UINT32 mem_start;
++ A_UINT32 mem_end;
++ A_UINT8 irq;
++
++ void * backPtr; /* backptr to dev_link_t struct */
++
++} CF_DEVICE;
++
++struct ar6000_pccard {
++ dev_link_t link;
++ dev_node_t node;
++
++ CF_DEVICE CfDevice;//ref. to the CFDevice structure for this device.
++#ifdef POLLED_MODE
++ struct timer_list poll_timer;
++#endif
++};
++
++#ifdef KERNEL_2_4
++typedef void irqreturn_t;
++#define IRQ_NONE
++#define IRQ_HANDLED
++#endif
++
++static void insert_dev_list(struct ar6000_pccard *);
++static struct dev_link_t * remove_dev_list(struct ar6000_pccard *);
++static void insert_drv_list(PCFFUNCTION);
++static PCFFUNCTION remove_drv_list(PCFFUNCTION);
++
++#endif //_AR6000_CS_INTERNAL_H_
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/hif.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/hif.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,390 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ * This file contains the routines handling the interaction with the SDIO
++ * driver
++ */
++
++#include "hif_internal.h"
++
++/* ------ Static Variables ------ */
++
++/* ------ Global Variable Declarations ------- */
++CF_PNP_INFO Ids[] = {
++ {
++ .CF_ManufacturerID = MANUFACTURER_ID_BASE | 0xB,
++ .CF_ManufacturerCode = MANUFACTURER_CODE,
++ .CF_FunctionClass = FUNCTION_CLASS,
++ .CF_FunctionNo = 1
++ },
++ {
++ .CF_ManufacturerID = MANUFACTURER_ID_BASE | 0xA,
++ .CF_ManufacturerCode = MANUFACTURER_CODE,
++ .CF_FunctionClass = FUNCTION_CLASS,
++ .CF_FunctionNo = 1
++ },
++ {
++ .CF_ManufacturerID = MANUFACTURER_ID_BASE | 0x9,
++ .CF_ManufacturerCode = MANUFACTURER_CODE,
++ .CF_FunctionClass = FUNCTION_CLASS,
++ .CF_FunctionNo = 1
++ },
++ {
++ .CF_ManufacturerID = MANUFACTURER_ID_BASE | 0x8,
++ .CF_ManufacturerCode = MANUFACTURER_CODE,
++ .CF_FunctionClass = FUNCTION_CLASS,
++ .CF_FunctionNo = 1
++ },
++ {
++ } //list is null termintaed
++};
++
++TARGET_FUNCTION_CONTEXT FunctionContext = {
++ .function.pName = "cf_wlan",
++ .function.MaxDevices = 1,
++ .function.NumDevices = 0,
++ .function.pIds = Ids,
++ .function.pProbe = hifDeviceInserted,
++ .function.pRemove = hifDeviceRemoved,
++/*
++ .function.pSuspend = NULL,
++ .function.pResume = NULL,
++ .function.pWake = NULL,
++*/
++ .function.pContext = &FunctionContext,
++};
++
++HIF_DEVICE hifDevice[HIF_MAX_DEVICES];
++HTC_CALLBACKS htcCallbacks;
++BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM];
++A_MUTEX_T lock;
++#ifdef DEBUG
++extern A_UINT32 debughif;
++extern A_UINT32 debugzonelevel;
++#define ATH_DEBUG_ERROR 1
++#define ATH_DEBUG_WARN 2
++#define ATH_DEBUG_TRACE 3
++#define _AR_DEBUG_PRINTX_ARG(arg...) arg
++#define AR_DEBUG_PRINTF(lvl, args)\
++ {if (lvl <= debughif)\
++ A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\
++ }
++#else
++#define AR_DEBUG_PRINTF(lvl, args)
++#endif
++
++
++/* ------ Functions ------ */
++
++void
++HIFRegisterCallbacks(HTC_CALLBACKS *callbacks)
++{
++ CF_STATUS status;
++
++ /* Store the callback and event handlers */
++ htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
++ htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
++ htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
++ htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
++ htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
++ htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
++ htcCallbacks.deviceInterruptDisabler = callbacks->deviceInterruptDisabler;
++ htcCallbacks.deviceInterruptEnabler = callbacks->deviceInterruptEnabler;
++ htcCallbacks.dsrHandler = callbacks->dsrHandler;
++
++ A_MUTEX_INIT(&lock);
++
++ /* Register with bus driver core */
++ status = CF_RegisterFunction(&FunctionContext.function);
++ A_ASSERT(CF_SUCCESS(status));
++}
++
++/*
++Parameters:
++type - can be of the basic or extended. For SDIO it maps to using a CMD52 or CMD53. For wince SDIO it maps to SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED. For CF this paramter is unused.
++dmode - byte or block basis. For wince SDIO driver, it maps to SD_IO_BYTE_MODE and SD_IO_BLOCK_MODE. This mode is unused for CF.
++amode - type of addressing on the target (fixed/incremental). This maps to writing to a REGISTER or a FIFO for CF.
++*/
++A_STATUS
++HIFReadWrite(HIF_DEVICE *device,
++ A_UINT32 address,
++ A_UCHAR *buffer,
++ A_UINT32 length,
++ HIF_REQUEST *request,
++ void *context)
++{
++ CFREQUEST cfrequest;
++ CF_STATUS status;
++ A_UINT32 remainingLen;
++ A_UINT32 curPos;
++
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++
++ A_MEMZERO(&cfrequest, sizeof(CFREQUEST));
++
++ cfrequest.pDataBuffer = buffer;
++ cfrequest.length = length;
++
++ /* Changes made to compensate for the changes in htc. For all the mbox
++ reads we are now passing the beginning of the address of the mailbox
++ and the addressing mode is incremental - TODO */
++ if ((request->direction == HIF_READ) && HIF_IS_MBOX_ADDR(address)) {
++ address += (HIF_MBOX_WIDTH - 1);
++ request->amode = HIF_FIXED_ADDRESS;
++ }
++
++ if (request->emode == HIF_SYNCHRONOUS) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Synchronous\n"));
++ } else if (request->emode == HIF_ASYNCHRONOUS) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode:Asynchronous\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid execution mode: %d\n", request->emode));
++ return A_ERROR;
++ }
++
++ if (request->direction == HIF_WRITE) {
++ cfrequest.Flags |= CFREQ_FLAGS_DATA_WRITE;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Write\n"));
++ } else if (request->direction == HIF_READ) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Read\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid direction: %d\n", request->direction));
++ return A_ERROR;
++ }
++
++ if (request->amode == HIF_FIXED_ADDRESS) {
++ cfrequest.Flags |= CFREQ_FLAGS_FIXED_ADDRESS;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Fixed\n"));
++ } else if (request->amode == HIF_INCREMENTAL_ADDRESS) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Incremental\n"));
++ } else {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid address mode: %d\n", request->amode));
++ return A_ERROR;
++ }
++
++ /* We need to do multiple writes in the case of CF interface
++ * as the MBOX size is limited to 256 bytes
++ */
++ if ( request->direction == HIF_WRITE && HIF_IS_MBOX_ADDR(address) ) {
++
++ remainingLen = length;
++#define BLK_SZ (HIF_MBOX_WIDTH - 2)
++
++ curPos = 0;
++
++ while (remainingLen > BLK_SZ) {
++ cfrequest.address = address;
++ cfrequest.length = BLK_SZ;
++ cfrequest.pDataBuffer = &buffer[curPos];
++
++ status = CFDEVICE_CALL_REQUESTW_FUNC(device->handle, &cfrequest);
++
++ if (status != CF_STATUS_SUCCESS) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF Write failed\n"));
++ return status;
++ }
++
++ curPos += BLK_SZ;
++ remainingLen -= BLK_SZ;
++ }
++
++ cfrequest.pDataBuffer = &buffer[curPos];
++ cfrequest.address = address + HIF_MBOX_WIDTH - remainingLen;
++ cfrequest.length = remainingLen;
++
++ status = CFDEVICE_CALL_REQUESTW_FUNC(device->handle, &cfrequest);
++
++ if (status != CF_STATUS_SUCCESS) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF Write failed\n"));
++ return status;
++ }
++ }
++ else if ( request->direction == HIF_READ && HIF_IS_MBOX_ADDR(address) ) {
++ // Read from an even address
++ cfrequest.address = address - 1;
++ status = CFDEVICE_CALL_REQUESTW_FUNC(device->handle, &cfrequest);
++ }
++ else {
++ cfrequest.address = address;
++ status = CFDEVICE_CALL_REQUESTB_FUNC(device->handle, &cfrequest);
++ }
++
++ if (status == CF_STATUS_SUCCESS) {
++ status = A_OK;
++ } else {
++ status = A_ERROR;
++ }
++
++ return status;
++}
++
++A_STATUS
++HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
++ void *config, A_UINT32 configLen)
++{
++ A_UINT32 count;
++
++ switch(opcode) {
++ case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
++ ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
++ ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
++ ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
++ ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
++ break;
++
++ case HIF_DEVICE_GET_MBOX_ADDR:
++ for (count = 0; count < 4; count ++) {
++ ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
++ }
++ break;
++
++ default:
++ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
++ ("Invalid configuration opcode: %d\n", opcode));
++ return A_ERROR;
++ }
++
++ return A_OK;
++}
++
++void
++HIFShutDownDevice(HIF_DEVICE *device)
++{
++ A_UINT32 count;
++ CF_STATUS status = CF_STATUS_SUCCESS;
++
++ /* Free the bus requests */
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
++ busRequest[count].free = TRUE;
++ }
++
++ /* Unregister with bus driver core */
++ if (device == NULL) {
++ status = CF_UnregisterFunction(&FunctionContext.function);
++ }
++
++ A_ASSERT(CF_SUCCESS(status));
++}
++
++void
++hifISRHandler(void *context, A_BOOL *callDSR)
++{
++ A_STATUS status;
++ HIF_DEVICE *device;
++
++ device = (HIF_DEVICE *)context;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ status = htcCallbacks.deviceInterruptDisabler(device, callDSR);
++ A_ASSERT(status == A_OK);
++}
++
++void
++hifDSRHandler(unsigned long context)
++{
++ A_STATUS status;
++ HIF_DEVICE *device;
++
++ device = (HIF_DEVICE *)context;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ status = htcCallbacks.dsrHandler(device);
++ A_ASSERT(status == A_OK);
++}
++
++
++static A_BOOL
++hifDeviceInserted(CFFUNCTION *function, PCFDEVICE handle)
++{
++ A_UINT32 count;
++ HIF_DEVICE *device;
++ TARGET_FUNCTION_CONTEXT *functionContext;
++
++ device = addHifDevice(handle);
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
++ functionContext = (TARGET_FUNCTION_CONTEXT *)function->pContext;
++
++ /* Allocate the bus requests to be used later */
++ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
++ busRequest[count].free = TRUE;
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
++ ("busRequest[%d].request = 0x%p, busRequest[%d].free = %d\n", count, &busRequest[count].request, count, busRequest[count].free));
++ }
++
++ /* Inform HTC */
++ if ((htcCallbacks.deviceInsertedHandler(device)) != A_OK) {
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
++ return FALSE;
++ }
++
++ return TRUE;
++}
++
++void
++HIFAckInterrupt(HIF_DEVICE *device)
++{
++ htcCallbacks.deviceInterruptEnabler(device);
++ return;
++ /* enable interrupts */
++ //enable_irq(device->handle->irq);
++}
++
++void
++HIFUnMaskInterrupt(HIF_DEVICE *device)
++{
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("HIFUnMaskInterrupt"));
++
++ CFDEVICE_SET_IRQ_HANDLER(device->handle, hifISRHandler, hifDSRHandler, device);
++}
++
++void HIFMaskInterrupt(HIF_DEVICE *device)
++{
++ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("HIFMaskInterrupt"));
++
++ CFDEVICE_SET_IRQ_HANDLER(device->handle, NULL, NULL, device);
++}
++
++static void
++hifDeviceRemoved(CFFUNCTION *function, PCFDEVICE handle)
++{
++ A_STATUS status;
++ HIF_DEVICE *device;
++
++ device = getHifDevice(handle);
++ status = htcCallbacks.deviceRemovedHandler(device);
++ delHifDevice(handle);
++ A_ASSERT(status == A_OK);
++}
++
++static HIF_DEVICE *
++addHifDevice(PCFDEVICE handle)
++{
++ hifDevice[0].handle = handle;
++ return &hifDevice[0];
++}
++
++static HIF_DEVICE *
++getHifDevice(PCFDEVICE handle)
++{
++ return &hifDevice[0];
++}
++
++static void
++delHifDevice(PCFDEVICE handle)
++{
++ hifDevice[0].handle = NULL;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/hif_internal.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/cf/hif_internal.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,78 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++#ifndef _HIF_INTERNAL_H
++#define _HIF_INTERNAL_H
++
++#include "ar6000_cs.h"
++#include "../../include/hif.h"
++
++#define MANUFACTURER_ID_BASE 0x100
++#define FUNCTION_CLASS 0x0
++#define MANUFACTURER_CODE 0x271
++
++#define HIF_MBOX_BLOCK_SIZE 2
++#define HIF_MBOX_BASE_ADDR 0x0
++#define HIF_MBOX_WIDTH 0x100
++#define HIF_MBOX0_BLOCK_SIZE 1
++#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++
++#define BUS_REQUEST_MAX_NUM 32
++
++#define HIF_MBOX_START_ADDR(mbox) \
++ HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
++
++#define HIF_MBOX_END_ADDR(mbox) \
++ HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
++
++#define HIF_IS_MBOX_ADDR(addr) (addr >= HIF_MBOX_START_ADDR(0) && addr <= HIF_MBOX_END_ADDR(3)) ? 1:0
++
++struct hif_device {
++ PCFDEVICE handle;
++};
++
++typedef struct target_function_context {
++ CFFUNCTION function; /* function description of the bus driver */
++
++// OS_SEMAPHORE instanceSem; /* instance lock. Unused */
++// SDLIST instanceList; /* list of instances. Unused */
++
++} TARGET_FUNCTION_CONTEXT;
++
++typedef struct bus_request {
++ A_BOOL free;
++ CFREQUEST request;
++} BUS_REQUEST;
++
++static A_BOOL
++hifDeviceInserted(CFFUNCTION *function, PCFDEVICE device);
++
++static void
++hifDeviceRemoved(CFFUNCTION *function, PCFDEVICE device);
++
++static HIF_DEVICE *
++addHifDevice(PCFDEVICE handle);
++
++static HIF_DEVICE *
++getHifDevice(PCFDEVICE handle);
++
++static void
++delHifDevice(PCFDEVICE handle);
++
++#endif //_HIF_INTERNAL_H
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/bmi/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1 @@
++obj-$(CONFIG_SDIO_AR6000_WLAN) += bmi.o
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/hif_internal.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/hif/hif_internal.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,85 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ $ATH_LICENSE_AR6K0$
++ *
++ */
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/hif.h"
++
++#define MANUFACTURER_ID_BASE 0x100
++#define FUNCTION_CLASS 0x0
++#define MANUFACTURER_CODE 0x271
++
++#define BUS_REQUEST_MAX_NUM 32
++
++#define SDIO_CLOCK_FREQUENCY_DEFAULT 24000000
++#define SDIO_CLOCK_FREQUENCY_REDUCED 12000000
++
++#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
++#define FLAGS_CARD_ENAB 0x02
++#define FLAGS_CARD_IRQ_UNMSK 0x04
++
++#define HIF_MBOX_BLOCK_SIZE 128
++#define HIF_MBOX_BASE_ADDR 0x800
++#define HIF_MBOX_WIDTH 0x800
++#define HIF_MBOX0_BLOCK_SIZE 1
++#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
++
++#define HIF_MBOX_START_ADDR(mbox) \
++ HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
++
++#define HIF_MBOX_END_ADDR(mbox) \
++ HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
++
++struct hif_device {
++ SDDEVICE *handle;
++};
++
++typedef struct target_function_context {
++ SDFUNCTION function; /* function description of the bus driver */
++ OS_SEMAPHORE instanceSem; /* instance lock. Unused */
++ SDLIST instanceList; /* list of instances. Unused */
++} TARGET_FUNCTION_CONTEXT;
++
++typedef struct bus_request {
++ A_BOOL free;
++ SDREQUEST *request;
++} BUS_REQUEST;
++
++BOOL
++hifDeviceInserted(SDFUNCTION *function, SDDEVICE *device);
++
++void
++hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *device);
++
++SDREQUEST *
++hifAllocateDeviceRequest(SDDEVICE *device);
++
++void
++hifFreeDeviceRequest(SDREQUEST *request);
++
++void
++hifRWCompletionHandler(SDREQUEST *request);
++
++void
++hifIRQHandler(void *context);
++
++HIF_DEVICE *
++addHifDevice(SDDEVICE *handle);
++
++HIF_DEVICE *
++getHifDevice(SDDEVICE *handle);
++
++void
++delHifDevice(SDDEVICE *handle);
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/htc/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO ar6000 wlan htc function driver
++#
++obj-$(CONFIG_SDIO_AR6000_WLAN) += htc.o htc_events.o htc_recv.o htc_send.o htc_utils.o
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_SDIO_AR6000_WLAN) += wlan_node.o wlan_recv_beacon.o wlan_utils.o
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_recv_beacon.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/wlan/wlan_recv_beacon.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,169 @@
++/*
++ * Copyright (c) 2001 Atsushi Onoe
++ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ */
++/*
++ * IEEE 802.11 input handling.
++ */
++
++#include "../include/athdefs.h"
++#include "../include/athtypes.h"
++#include "../include/osapi.h"
++#include "../include/wmi.h"
++#include "../include/ieee80211.h"
++#include "../include/wlan_api.h"
++
++#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \
++ if ((_len) < (_minlen)) { \
++ return A_EINVAL; \
++ } \
++} while (0)
++
++#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \
++ if ((__elem) == NULL) { \
++ return A_EINVAL; \
++ } \
++ if ((__elem)[1] > (__maxlen)) { \
++ return A_EINVAL; \
++ } \
++} while (0)
++
++
++/* unaligned little endian access */
++#define LE_READ_2(p) \
++ ((A_UINT16) \
++ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8)))
++
++#define LE_READ_4(p) \
++ ((A_UINT32) \
++ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
++ (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
++
++
++static int __inline
++iswpaoui(const A_UINT8 *frm)
++{
++ return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
++}
++
++static int __inline
++iswmmoui(const A_UINT8 *frm)
++{
++ return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
++}
++
++static int __inline
++iswmmparam(const A_UINT8 *frm)
++{
++ return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
++}
++
++static int __inline
++iswmminfo(const A_UINT8 *frm)
++{
++ return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
++}
++
++static int __inline
++isatherosoui(const A_UINT8 *frm)
++{
++ return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
++}
++
++A_STATUS
++wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
++{
++ A_UINT8 *frm, *efrm;
++
++ frm = buf;
++ efrm = (A_UINT8 *) (frm + framelen);
++
++ /*
++ * beacon/probe response frame format
++ * [8] time stamp
++ * [2] beacon interval
++ * [2] capability information
++ * [tlv] ssid
++ * [tlv] supported rates
++ * [tlv] country information
++ * [tlv] parameter set (FH/DS)
++ * [tlv] erp information
++ * [tlv] extended supported rates
++ * [tlv] WMM
++ * [tlv] WPA or RSN
++ * [tlv] Atheros Advanced Capabilities
++ */
++ IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
++ A_MEMZERO(cie, sizeof(*cie));
++
++ cie->ie_tstamp = frm; frm += 8;
++ cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
++ cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
++ cie->ie_chan = 0;
++
++ while (frm < efrm) {
++ switch (*frm) {
++ case IEEE80211_ELEMID_SSID:
++ cie->ie_ssid = frm;
++ break;
++ case IEEE80211_ELEMID_RATES:
++ cie->ie_rates = frm;
++ break;
++ case IEEE80211_ELEMID_COUNTRY:
++ cie->ie_country = frm;
++ break;
++ case IEEE80211_ELEMID_FHPARMS:
++ break;
++ case IEEE80211_ELEMID_DSPARMS:
++ cie->ie_chan = frm[2];
++ break;
++ case IEEE80211_ELEMID_TIM:
++ cie->ie_tim = frm;
++ break;
++ case IEEE80211_ELEMID_IBSSPARMS:
++ break;
++ case IEEE80211_ELEMID_XRATES:
++ cie->ie_xrates = frm;
++ break;
++ case IEEE80211_ELEMID_ERP:
++ if (frm[1] != 1) {
++ A_PRINTF("Discarding ERP Element - Bad Len\n");
++ return A_EINVAL;
++ }
++ cie->ie_erp = frm[2];
++ break;
++ case IEEE80211_ELEMID_RSN:
++ cie->ie_wpa = frm;
++ break;
++ case IEEE80211_ELEMID_VENDOR:
++ if (iswpaoui(frm)) {
++ cie->ie_wpa = frm;
++ } else if (iswmmoui(frm)) {
++ cie->ie_wmm = frm;
++ } else if (isatherosoui(frm)) {
++ cie->ie_ath = frm;
++ }
++ break;
++ default:
++ break;
++ }
++ frm += frm[1] + 2;
++ }
++ IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
++ IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
++
++ return A_OK;
++}
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mbox_reg.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mbox_reg.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,550 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _MBOX_REG_H_
++#define _MBOX_REG_H_
++
++#define MBOX_FIFO_ADDRESS 0x0c014000
++#define MBOX_FIFO_OFFSET 0x00000000
++#define MBOX_FIFO_DATA_MSB 19
++#define MBOX_FIFO_DATA_LSB 0
++#define MBOX_FIFO_DATA_MASK 0x000fffff
++#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
++#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
++
++#define MBOX_FIFO_STATUS_ADDRESS 0x0c014010
++#define MBOX_FIFO_STATUS_OFFSET 0x00000010
++#define MBOX_FIFO_STATUS_EMPTY_MSB 19
++#define MBOX_FIFO_STATUS_EMPTY_LSB 16
++#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
++#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
++#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
++#define MBOX_FIFO_STATUS_FULL_MSB 15
++#define MBOX_FIFO_STATUS_FULL_LSB 12
++#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
++#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
++#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
++
++#define MBOX_DMA_POLICY_ADDRESS 0x0c014014
++#define MBOX_DMA_POLICY_OFFSET 0x00000014
++#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
++#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
++#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
++#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
++#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
++#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
++#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
++#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
++#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
++#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
++#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
++#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
++#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
++#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
++#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
++#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
++#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
++#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
++#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
++#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
++
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x0c014018
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0c01401c
++#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
++#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
++#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
++#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX0_DMA_RX_CONTROL_START_MSB 1
++#define MBOX0_DMA_RX_CONTROL_START_LSB 1
++#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
++#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
++#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
++#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
++#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
++#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
++#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0c014020
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x0c014024
++#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
++#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
++#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
++#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX0_DMA_TX_CONTROL_START_MSB 1
++#define MBOX0_DMA_TX_CONTROL_START_LSB 1
++#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
++#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
++#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
++#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
++#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
++#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
++#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x0c014028
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0c01402c
++#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
++#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
++#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
++#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX1_DMA_RX_CONTROL_START_MSB 1
++#define MBOX1_DMA_RX_CONTROL_START_LSB 1
++#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
++#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
++#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
++#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
++#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
++#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
++#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0c014030
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x0c014034
++#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
++#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
++#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
++#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX1_DMA_TX_CONTROL_START_MSB 1
++#define MBOX1_DMA_TX_CONTROL_START_LSB 1
++#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
++#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
++#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
++#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
++#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
++#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
++#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x0c014038
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0c01403c
++#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
++#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
++#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
++#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX2_DMA_RX_CONTROL_START_MSB 1
++#define MBOX2_DMA_RX_CONTROL_START_LSB 1
++#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
++#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
++#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
++#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
++#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
++#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
++#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0c014040
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x0c014044
++#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
++#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
++#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
++#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX2_DMA_TX_CONTROL_START_MSB 1
++#define MBOX2_DMA_TX_CONTROL_START_LSB 1
++#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
++#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
++#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
++#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
++#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
++#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
++#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x0c014048
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0c01404c
++#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
++#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
++#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
++#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
++#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
++#define MBOX3_DMA_RX_CONTROL_START_MSB 1
++#define MBOX3_DMA_RX_CONTROL_START_LSB 1
++#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
++#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
++#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
++#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
++#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
++#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
++#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
++#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
++
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0c014050
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
++#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
++
++#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x0c014054
++#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
++#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
++#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
++#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
++#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
++#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
++#define MBOX3_DMA_TX_CONTROL_START_MSB 1
++#define MBOX3_DMA_TX_CONTROL_START_LSB 1
++#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
++#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
++#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
++#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
++#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
++#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
++#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
++#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
++
++#define MBOX_INT_STATUS_ADDRESS 0x0c014058
++#define MBOX_INT_STATUS_OFFSET 0x00000058
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
++#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
++#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
++#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
++#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
++#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
++#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
++#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
++#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
++#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
++#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
++#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
++#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
++#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
++#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
++#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
++#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
++#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
++#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
++#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
++#define MBOX_INT_STATUS_HOST_MSB 7
++#define MBOX_INT_STATUS_HOST_LSB 0
++#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
++#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
++#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
++
++#define MBOX_INT_ENABLE_ADDRESS 0x0c01405c
++#define MBOX_INT_ENABLE_OFFSET 0x0000005c
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
++#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
++#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
++#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
++#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
++#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
++#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
++#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
++#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
++#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
++#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
++#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
++#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
++#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
++#define MBOX_INT_ENABLE_HOST_MSB 7
++#define MBOX_INT_ENABLE_HOST_LSB 0
++#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
++#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
++#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
++
++#define INT_HOST_ADDRESS 0x0c014060
++#define INT_HOST_OFFSET 0x00000060
++#define INT_HOST_VECTOR_MSB 7
++#define INT_HOST_VECTOR_LSB 0
++#define INT_HOST_VECTOR_MASK 0x000000ff
++#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
++#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
++
++#define LOCAL_COUNT_ADDRESS 0x0c014080
++#define LOCAL_COUNT_OFFSET 0x00000080
++#define LOCAL_COUNT_VALUE_MSB 7
++#define LOCAL_COUNT_VALUE_LSB 0
++#define LOCAL_COUNT_VALUE_MASK 0x000000ff
++#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
++#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
++
++#define COUNT_INC_ADDRESS 0x0c0140a0
++#define COUNT_INC_OFFSET 0x000000a0
++#define COUNT_INC_VALUE_MSB 7
++#define COUNT_INC_VALUE_LSB 0
++#define COUNT_INC_VALUE_MASK 0x000000ff
++#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
++#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
++
++#define LOCAL_SCRATCH_ADDRESS 0x0c0140c0
++#define LOCAL_SCRATCH_OFFSET 0x000000c0
++#define LOCAL_SCRATCH_VALUE_MSB 7
++#define LOCAL_SCRATCH_VALUE_LSB 0
++#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
++#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
++#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
++
++#define USE_LOCAL_BUS_ADDRESS 0x0c0140e0
++#define USE_LOCAL_BUS_OFFSET 0x000000e0
++#define USE_LOCAL_BUS_PIN_INIT_MSB 0
++#define USE_LOCAL_BUS_PIN_INIT_LSB 0
++#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
++#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
++#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
++
++#define SDIO_CONFIG_ADDRESS 0x0c0140e4
++#define SDIO_CONFIG_OFFSET 0x000000e4
++#define SDIO_CONFIG_CCCR_IOR1_MSB 0
++#define SDIO_CONFIG_CCCR_IOR1_LSB 0
++#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
++#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
++#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
++
++#define MBOX_DEBUG_ADDRESS 0x0c0140e8
++#define MBOX_DEBUG_OFFSET 0x000000e8
++#define MBOX_DEBUG_SEL_MSB 2
++#define MBOX_DEBUG_SEL_LSB 0
++#define MBOX_DEBUG_SEL_MASK 0x00000007
++#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
++#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
++
++#define MBOX_FIFO_RESET_ADDRESS 0x0c0140ec
++#define MBOX_FIFO_RESET_OFFSET 0x000000ec
++#define MBOX_FIFO_RESET_INIT_MSB 0
++#define MBOX_FIFO_RESET_INIT_LSB 0
++#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
++#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
++#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
++
++#define STEREO_CONFIG_ADDRESS 0x0c0140f0
++#define STEREO_CONFIG_OFFSET 0x000000f0
++#define STEREO_CONFIG_ENABLE_MSB 24
++#define STEREO_CONFIG_ENABLE_LSB 24
++#define STEREO_CONFIG_ENABLE_MASK 0x01000000
++#define STEREO_CONFIG_ENABLE_GET(x) (((x) & STEREO_CONFIG_ENABLE_MASK) >> STEREO_CONFIG_ENABLE_LSB)
++#define STEREO_CONFIG_ENABLE_SET(x) (((x) << STEREO_CONFIG_ENABLE_LSB) & STEREO_CONFIG_ENABLE_MASK)
++#define STEREO_CONFIG_RESET_MSB 23
++#define STEREO_CONFIG_RESET_LSB 23
++#define STEREO_CONFIG_RESET_MASK 0x00800000
++#define STEREO_CONFIG_RESET_GET(x) (((x) & STEREO_CONFIG_RESET_MASK) >> STEREO_CONFIG_RESET_LSB)
++#define STEREO_CONFIG_RESET_SET(x) (((x) << STEREO_CONFIG_RESET_LSB) & STEREO_CONFIG_RESET_MASK)
++#define STEREO_CONFIG_I2S_DELAY_MSB 22
++#define STEREO_CONFIG_I2S_DELAY_LSB 22
++#define STEREO_CONFIG_I2S_DELAY_MASK 0x00400000
++#define STEREO_CONFIG_I2S_DELAY_GET(x) (((x) & STEREO_CONFIG_I2S_DELAY_MASK) >> STEREO_CONFIG_I2S_DELAY_LSB)
++#define STEREO_CONFIG_I2S_DELAY_SET(x) (((x) << STEREO_CONFIG_I2S_DELAY_LSB) & STEREO_CONFIG_I2S_DELAY_MASK)
++#define STEREO_CONFIG_MIC_MASTER_MSB 21
++#define STEREO_CONFIG_MIC_MASTER_LSB 21
++#define STEREO_CONFIG_MIC_MASTER_MASK 0x00200000
++#define STEREO_CONFIG_MIC_MASTER_GET(x) (((x) & STEREO_CONFIG_MIC_MASTER_MASK) >> STEREO_CONFIG_MIC_MASTER_LSB)
++#define STEREO_CONFIG_MIC_MASTER_SET(x) (((x) << STEREO_CONFIG_MIC_MASTER_LSB) & STEREO_CONFIG_MIC_MASTER_MASK)
++#define STEREO_CONFIG_MIC_WORD_SIZE_MSB 20
++#define STEREO_CONFIG_MIC_WORD_SIZE_LSB 20
++#define STEREO_CONFIG_MIC_WORD_SIZE_MASK 0x00100000
++#define STEREO_CONFIG_MIC_WORD_SIZE_GET(x) (((x) & STEREO_CONFIG_MIC_WORD_SIZE_MASK) >> STEREO_CONFIG_MIC_WORD_SIZE_LSB)
++#define STEREO_CONFIG_MIC_WORD_SIZE_SET(x) (((x) << STEREO_CONFIG_MIC_WORD_SIZE_LSB) & STEREO_CONFIG_MIC_WORD_SIZE_MASK)
++#define STEREO_CONFIG_STEREO_MONO_MSB 19
++#define STEREO_CONFIG_STEREO_MONO_LSB 18
++#define STEREO_CONFIG_STEREO_MONO_MASK 0x000c0000
++#define STEREO_CONFIG_STEREO_MONO_GET(x) (((x) & STEREO_CONFIG_STEREO_MONO_MASK) >> STEREO_CONFIG_STEREO_MONO_LSB)
++#define STEREO_CONFIG_STEREO_MONO_SET(x) (((x) << STEREO_CONFIG_STEREO_MONO_LSB) & STEREO_CONFIG_STEREO_MONO_MASK)
++#define STEREO_CONFIG_DATA_WORD_SIZE_MSB 17
++#define STEREO_CONFIG_DATA_WORD_SIZE_LSB 16
++#define STEREO_CONFIG_DATA_WORD_SIZE_MASK 0x00030000
++#define STEREO_CONFIG_DATA_WORD_SIZE_GET(x) (((x) & STEREO_CONFIG_DATA_WORD_SIZE_MASK) >> STEREO_CONFIG_DATA_WORD_SIZE_LSB)
++#define STEREO_CONFIG_DATA_WORD_SIZE_SET(x) (((x) << STEREO_CONFIG_DATA_WORD_SIZE_LSB) & STEREO_CONFIG_DATA_WORD_SIZE_MASK)
++#define STEREO_CONFIG_I2S_WORD_SIZE_MSB 15
++#define STEREO_CONFIG_I2S_WORD_SIZE_LSB 15
++#define STEREO_CONFIG_I2S_WORD_SIZE_MASK 0x00008000
++#define STEREO_CONFIG_I2S_WORD_SIZE_GET(x) (((x) & STEREO_CONFIG_I2S_WORD_SIZE_MASK) >> STEREO_CONFIG_I2S_WORD_SIZE_LSB)
++#define STEREO_CONFIG_I2S_WORD_SIZE_SET(x) (((x) << STEREO_CONFIG_I2S_WORD_SIZE_LSB) & STEREO_CONFIG_I2S_WORD_SIZE_MASK)
++#define STEREO_CONFIG_MCK_SEL_MSB 14
++#define STEREO_CONFIG_MCK_SEL_LSB 14
++#define STEREO_CONFIG_MCK_SEL_MASK 0x00004000
++#define STEREO_CONFIG_MCK_SEL_GET(x) (((x) & STEREO_CONFIG_MCK_SEL_MASK) >> STEREO_CONFIG_MCK_SEL_LSB)
++#define STEREO_CONFIG_MCK_SEL_SET(x) (((x) << STEREO_CONFIG_MCK_SEL_LSB) & STEREO_CONFIG_MCK_SEL_MASK)
++#define STEREO_CONFIG_MCK_CNT_MSB 13
++#define STEREO_CONFIG_MCK_CNT_LSB 10
++#define STEREO_CONFIG_MCK_CNT_MASK 0x00003c00
++#define STEREO_CONFIG_MCK_CNT_GET(x) (((x) & STEREO_CONFIG_MCK_CNT_MASK) >> STEREO_CONFIG_MCK_CNT_LSB)
++#define STEREO_CONFIG_MCK_CNT_SET(x) (((x) << STEREO_CONFIG_MCK_CNT_LSB) & STEREO_CONFIG_MCK_CNT_MASK)
++#define STEREO_CONFIG_MCK_RAW_MSB 9
++#define STEREO_CONFIG_MCK_RAW_LSB 9
++#define STEREO_CONFIG_MCK_RAW_MASK 0x00000200
++#define STEREO_CONFIG_MCK_RAW_GET(x) (((x) & STEREO_CONFIG_MCK_RAW_MASK) >> STEREO_CONFIG_MCK_RAW_LSB)
++#define STEREO_CONFIG_MCK_RAW_SET(x) (((x) << STEREO_CONFIG_MCK_RAW_LSB) & STEREO_CONFIG_MCK_RAW_MASK)
++#define STEREO_CONFIG_MASTER_MSB 8
++#define STEREO_CONFIG_MASTER_LSB 8
++#define STEREO_CONFIG_MASTER_MASK 0x00000100
++#define STEREO_CONFIG_MASTER_GET(x) (((x) & STEREO_CONFIG_MASTER_MASK) >> STEREO_CONFIG_MASTER_LSB)
++#define STEREO_CONFIG_MASTER_SET(x) (((x) << STEREO_CONFIG_MASTER_LSB) & STEREO_CONFIG_MASTER_MASK)
++#define STEREO_CONFIG_POSEDGE_MSB 7
++#define STEREO_CONFIG_POSEDGE_LSB 0
++#define STEREO_CONFIG_POSEDGE_MASK 0x000000ff
++#define STEREO_CONFIG_POSEDGE_GET(x) (((x) & STEREO_CONFIG_POSEDGE_MASK) >> STEREO_CONFIG_POSEDGE_LSB)
++#define STEREO_CONFIG_POSEDGE_SET(x) (((x) << STEREO_CONFIG_POSEDGE_LSB) & STEREO_CONFIG_POSEDGE_MASK)
++
++#define STEREO_VOLUME_ADDRESS 0x0c0140f4
++#define STEREO_VOLUME_OFFSET 0x000000f4
++#define STEREO_VOLUME_CHANNEL1_MSB 12
++#define STEREO_VOLUME_CHANNEL1_LSB 8
++#define STEREO_VOLUME_CHANNEL1_MASK 0x00001f00
++#define STEREO_VOLUME_CHANNEL1_GET(x) (((x) & STEREO_VOLUME_CHANNEL1_MASK) >> STEREO_VOLUME_CHANNEL1_LSB)
++#define STEREO_VOLUME_CHANNEL1_SET(x) (((x) << STEREO_VOLUME_CHANNEL1_LSB) & STEREO_VOLUME_CHANNEL1_MASK)
++#define STEREO_VOLUME_CHANNEL0_MSB 4
++#define STEREO_VOLUME_CHANNEL0_LSB 0
++#define STEREO_VOLUME_CHANNEL0_MASK 0x0000001f
++#define STEREO_VOLUME_CHANNEL0_GET(x) (((x) & STEREO_VOLUME_CHANNEL0_MASK) >> STEREO_VOLUME_CHANNEL0_LSB)
++#define STEREO_VOLUME_CHANNEL0_SET(x) (((x) << STEREO_VOLUME_CHANNEL0_LSB) & STEREO_VOLUME_CHANNEL0_MASK)
++
++#define HOST_IF_WINDOW_ADDRESS 0x0c016000
++#define HOST_IF_WINDOW_OFFSET 0x00002000
++#define HOST_IF_WINDOW_DATA_MSB 7
++#define HOST_IF_WINDOW_DATA_LSB 0
++#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
++#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
++#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mbox_reg_s {
++ volatile unsigned int mbox_fifo[4];
++ volatile unsigned int mbox_fifo_status;
++ volatile unsigned int mbox_dma_policy;
++ volatile unsigned int mbox0_dma_rx_descriptor_base;
++ volatile unsigned int mbox0_dma_rx_control;
++ volatile unsigned int mbox0_dma_tx_descriptor_base;
++ volatile unsigned int mbox0_dma_tx_control;
++ volatile unsigned int mbox1_dma_rx_descriptor_base;
++ volatile unsigned int mbox1_dma_rx_control;
++ volatile unsigned int mbox1_dma_tx_descriptor_base;
++ volatile unsigned int mbox1_dma_tx_control;
++ volatile unsigned int mbox2_dma_rx_descriptor_base;
++ volatile unsigned int mbox2_dma_rx_control;
++ volatile unsigned int mbox2_dma_tx_descriptor_base;
++ volatile unsigned int mbox2_dma_tx_control;
++ volatile unsigned int mbox3_dma_rx_descriptor_base;
++ volatile unsigned int mbox3_dma_rx_control;
++ volatile unsigned int mbox3_dma_tx_descriptor_base;
++ volatile unsigned int mbox3_dma_tx_control;
++ volatile unsigned int mbox_int_status;
++ volatile unsigned int mbox_int_enable;
++ volatile unsigned int int_host;
++ unsigned char pad0[28]; /* pad to 0x80 */
++ volatile unsigned int local_count[8];
++ volatile unsigned int count_inc[8];
++ volatile unsigned int local_scratch[8];
++ volatile unsigned int use_local_bus;
++ volatile unsigned int sdio_config;
++ volatile unsigned int mbox_debug;
++ volatile unsigned int mbox_fifo_reset;
++ volatile unsigned int stereo_config;
++ volatile unsigned int stereo_volume;
++ unsigned char pad1[7944]; /* pad to 0x2000 */
++ volatile unsigned int host_if_window[2048];
++} mbox_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MBOX_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mc_reg.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mc_reg.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1129 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _MC_REG_H_
++#define _MC_REG_H_
++
++#define BANK0_ADDR_ADDRESS 0x0c004000
++#define BANK0_ADDR_OFFSET 0x00000000
++#define BANK0_ADDR_SIZE_MSB 31
++#define BANK0_ADDR_SIZE_LSB 28
++#define BANK0_ADDR_SIZE_MASK 0xf0000000
++#define BANK0_ADDR_SIZE_GET(x) (((x) & BANK0_ADDR_SIZE_MASK) >> BANK0_ADDR_SIZE_LSB)
++#define BANK0_ADDR_SIZE_SET(x) (((x) << BANK0_ADDR_SIZE_LSB) & BANK0_ADDR_SIZE_MASK)
++#define BANK0_ADDR_BASE_MSB 27
++#define BANK0_ADDR_BASE_LSB 10
++#define BANK0_ADDR_BASE_MASK 0x0ffffc00
++#define BANK0_ADDR_BASE_GET(x) (((x) & BANK0_ADDR_BASE_MASK) >> BANK0_ADDR_BASE_LSB)
++#define BANK0_ADDR_BASE_SET(x) (((x) << BANK0_ADDR_BASE_LSB) & BANK0_ADDR_BASE_MASK)
++
++#define BANK0_CONFIG_ADDRESS 0x0c004004
++#define BANK0_CONFIG_OFFSET 0x00000004
++#define BANK0_CONFIG_ENABLE_MSB 31
++#define BANK0_CONFIG_ENABLE_LSB 31
++#define BANK0_CONFIG_ENABLE_MASK 0x80000000
++#define BANK0_CONFIG_ENABLE_GET(x) (((x) & BANK0_CONFIG_ENABLE_MASK) >> BANK0_CONFIG_ENABLE_LSB)
++#define BANK0_CONFIG_ENABLE_SET(x) (((x) << BANK0_CONFIG_ENABLE_LSB) & BANK0_CONFIG_ENABLE_MASK)
++#define BANK0_CONFIG_WIDTH_MSB 28
++#define BANK0_CONFIG_WIDTH_LSB 28
++#define BANK0_CONFIG_WIDTH_MASK 0x10000000
++#define BANK0_CONFIG_WIDTH_GET(x) (((x) & BANK0_CONFIG_WIDTH_MASK) >> BANK0_CONFIG_WIDTH_LSB)
++#define BANK0_CONFIG_WIDTH_SET(x) (((x) << BANK0_CONFIG_WIDTH_LSB) & BANK0_CONFIG_WIDTH_MASK)
++#define BANK0_CONFIG_PROTECT_MSB 26
++#define BANK0_CONFIG_PROTECT_LSB 26
++#define BANK0_CONFIG_PROTECT_MASK 0x04000000
++#define BANK0_CONFIG_PROTECT_GET(x) (((x) & BANK0_CONFIG_PROTECT_MASK) >> BANK0_CONFIG_PROTECT_LSB)
++#define BANK0_CONFIG_PROTECT_SET(x) (((x) << BANK0_CONFIG_PROTECT_LSB) & BANK0_CONFIG_PROTECT_MASK)
++#define BANK0_CONFIG_WB_ENABLE_MSB 25
++#define BANK0_CONFIG_WB_ENABLE_LSB 25
++#define BANK0_CONFIG_WB_ENABLE_MASK 0x02000000
++#define BANK0_CONFIG_WB_ENABLE_GET(x) (((x) & BANK0_CONFIG_WB_ENABLE_MASK) >> BANK0_CONFIG_WB_ENABLE_LSB)
++#define BANK0_CONFIG_WB_ENABLE_SET(x) (((x) << BANK0_CONFIG_WB_ENABLE_LSB) & BANK0_CONFIG_WB_ENABLE_MASK)
++#define BANK0_CONFIG_WB_FLUSH_MSB 24
++#define BANK0_CONFIG_WB_FLUSH_LSB 24
++#define BANK0_CONFIG_WB_FLUSH_MASK 0x01000000
++#define BANK0_CONFIG_WB_FLUSH_GET(x) (((x) & BANK0_CONFIG_WB_FLUSH_MASK) >> BANK0_CONFIG_WB_FLUSH_LSB)
++#define BANK0_CONFIG_WB_FLUSH_SET(x) (((x) << BANK0_CONFIG_WB_FLUSH_LSB) & BANK0_CONFIG_WB_FLUSH_MASK)
++#define BANK0_CONFIG_SCALE_MSB 21
++#define BANK0_CONFIG_SCALE_LSB 20
++#define BANK0_CONFIG_SCALE_MASK 0x00300000
++#define BANK0_CONFIG_SCALE_GET(x) (((x) & BANK0_CONFIG_SCALE_MASK) >> BANK0_CONFIG_SCALE_LSB)
++#define BANK0_CONFIG_SCALE_SET(x) (((x) << BANK0_CONFIG_SCALE_LSB) & BANK0_CONFIG_SCALE_MASK)
++#define BANK0_CONFIG_HOLDOFF_MSB 19
++#define BANK0_CONFIG_HOLDOFF_LSB 16
++#define BANK0_CONFIG_HOLDOFF_MASK 0x000f0000
++#define BANK0_CONFIG_HOLDOFF_GET(x) (((x) & BANK0_CONFIG_HOLDOFF_MASK) >> BANK0_CONFIG_HOLDOFF_LSB)
++#define BANK0_CONFIG_HOLDOFF_SET(x) (((x) << BANK0_CONFIG_HOLDOFF_LSB) & BANK0_CONFIG_HOLDOFF_MASK)
++#define BANK0_CONFIG_TIMER3_MSB 15
++#define BANK0_CONFIG_TIMER3_LSB 12
++#define BANK0_CONFIG_TIMER3_MASK 0x0000f000
++#define BANK0_CONFIG_TIMER3_GET(x) (((x) & BANK0_CONFIG_TIMER3_MASK) >> BANK0_CONFIG_TIMER3_LSB)
++#define BANK0_CONFIG_TIMER3_SET(x) (((x) << BANK0_CONFIG_TIMER3_LSB) & BANK0_CONFIG_TIMER3_MASK)
++#define BANK0_CONFIG_TIMER2_MSB 11
++#define BANK0_CONFIG_TIMER2_LSB 8
++#define BANK0_CONFIG_TIMER2_MASK 0x00000f00
++#define BANK0_CONFIG_TIMER2_GET(x) (((x) & BANK0_CONFIG_TIMER2_MASK) >> BANK0_CONFIG_TIMER2_LSB)
++#define BANK0_CONFIG_TIMER2_SET(x) (((x) << BANK0_CONFIG_TIMER2_LSB) & BANK0_CONFIG_TIMER2_MASK)
++#define BANK0_CONFIG_TIMER1_MSB 7
++#define BANK0_CONFIG_TIMER1_LSB 4
++#define BANK0_CONFIG_TIMER1_MASK 0x000000f0
++#define BANK0_CONFIG_TIMER1_GET(x) (((x) & BANK0_CONFIG_TIMER1_MASK) >> BANK0_CONFIG_TIMER1_LSB)
++#define BANK0_CONFIG_TIMER1_SET(x) (((x) << BANK0_CONFIG_TIMER1_LSB) & BANK0_CONFIG_TIMER1_MASK)
++#define BANK0_CONFIG_TIMER0_MSB 3
++#define BANK0_CONFIG_TIMER0_LSB 0
++#define BANK0_CONFIG_TIMER0_MASK 0x0000000f
++#define BANK0_CONFIG_TIMER0_GET(x) (((x) & BANK0_CONFIG_TIMER0_MASK) >> BANK0_CONFIG_TIMER0_LSB)
++#define BANK0_CONFIG_TIMER0_SET(x) (((x) << BANK0_CONFIG_TIMER0_LSB) & BANK0_CONFIG_TIMER0_MASK)
++
++#define BANK0_READ_ADDRESS 0x0c004008
++#define BANK0_READ_OFFSET 0x00000008
++#define BANK0_READ_ENABLE_WAIT_MSB 31
++#define BANK0_READ_ENABLE_WAIT_LSB 31
++#define BANK0_READ_ENABLE_WAIT_MASK 0x80000000
++#define BANK0_READ_ENABLE_WAIT_GET(x) (((x) & BANK0_READ_ENABLE_WAIT_MASK) >> BANK0_READ_ENABLE_WAIT_LSB)
++#define BANK0_READ_ENABLE_WAIT_SET(x) (((x) << BANK0_READ_ENABLE_WAIT_LSB) & BANK0_READ_ENABLE_WAIT_MASK)
++#define BANK0_READ_WAIT_EVENT_MSB 30
++#define BANK0_READ_WAIT_EVENT_LSB 28
++#define BANK0_READ_WAIT_EVENT_MASK 0x70000000
++#define BANK0_READ_WAIT_EVENT_GET(x) (((x) & BANK0_READ_WAIT_EVENT_MASK) >> BANK0_READ_WAIT_EVENT_LSB)
++#define BANK0_READ_WAIT_EVENT_SET(x) (((x) << BANK0_READ_WAIT_EVENT_LSB) & BANK0_READ_WAIT_EVENT_MASK)
++#define BANK0_READ_END_EVENT_MSB 26
++#define BANK0_READ_END_EVENT_LSB 24
++#define BANK0_READ_END_EVENT_MASK 0x07000000
++#define BANK0_READ_END_EVENT_GET(x) (((x) & BANK0_READ_END_EVENT_MASK) >> BANK0_READ_END_EVENT_LSB)
++#define BANK0_READ_END_EVENT_SET(x) (((x) << BANK0_READ_END_EVENT_LSB) & BANK0_READ_END_EVENT_MASK)
++#define BANK0_READ_BURST_END_EVENT_MSB 22
++#define BANK0_READ_BURST_END_EVENT_LSB 20
++#define BANK0_READ_BURST_END_EVENT_MASK 0x00700000
++#define BANK0_READ_BURST_END_EVENT_GET(x) (((x) & BANK0_READ_BURST_END_EVENT_MASK) >> BANK0_READ_BURST_END_EVENT_LSB)
++#define BANK0_READ_BURST_END_EVENT_SET(x) (((x) << BANK0_READ_BURST_END_EVENT_LSB) & BANK0_READ_BURST_END_EVENT_MASK)
++#define BANK0_READ_BURST_START_EVENT_MSB 18
++#define BANK0_READ_BURST_START_EVENT_LSB 16
++#define BANK0_READ_BURST_START_EVENT_MASK 0x00070000
++#define BANK0_READ_BURST_START_EVENT_GET(x) (((x) & BANK0_READ_BURST_START_EVENT_MASK) >> BANK0_READ_BURST_START_EVENT_LSB)
++#define BANK0_READ_BURST_START_EVENT_SET(x) (((x) << BANK0_READ_BURST_START_EVENT_LSB) & BANK0_READ_BURST_START_EVENT_MASK)
++#define BANK0_READ_EVENT3_DC_MSB 15
++#define BANK0_READ_EVENT3_DC_LSB 15
++#define BANK0_READ_EVENT3_DC_MASK 0x00008000
++#define BANK0_READ_EVENT3_DC_GET(x) (((x) & BANK0_READ_EVENT3_DC_MASK) >> BANK0_READ_EVENT3_DC_LSB)
++#define BANK0_READ_EVENT3_DC_SET(x) (((x) << BANK0_READ_EVENT3_DC_LSB) & BANK0_READ_EVENT3_DC_MASK)
++#define BANK0_READ_EVENT3_BE_MSB 14
++#define BANK0_READ_EVENT3_BE_LSB 14
++#define BANK0_READ_EVENT3_BE_MASK 0x00004000
++#define BANK0_READ_EVENT3_BE_GET(x) (((x) & BANK0_READ_EVENT3_BE_MASK) >> BANK0_READ_EVENT3_BE_LSB)
++#define BANK0_READ_EVENT3_BE_SET(x) (((x) << BANK0_READ_EVENT3_BE_LSB) & BANK0_READ_EVENT3_BE_MASK)
++#define BANK0_READ_EVENT3_OE_MSB 13
++#define BANK0_READ_EVENT3_OE_LSB 13
++#define BANK0_READ_EVENT3_OE_MASK 0x00002000
++#define BANK0_READ_EVENT3_OE_GET(x) (((x) & BANK0_READ_EVENT3_OE_MASK) >> BANK0_READ_EVENT3_OE_LSB)
++#define BANK0_READ_EVENT3_OE_SET(x) (((x) << BANK0_READ_EVENT3_OE_LSB) & BANK0_READ_EVENT3_OE_MASK)
++#define BANK0_READ_EVENT3_CS_MSB 12
++#define BANK0_READ_EVENT3_CS_LSB 12
++#define BANK0_READ_EVENT3_CS_MASK 0x00001000
++#define BANK0_READ_EVENT3_CS_GET(x) (((x) & BANK0_READ_EVENT3_CS_MASK) >> BANK0_READ_EVENT3_CS_LSB)
++#define BANK0_READ_EVENT3_CS_SET(x) (((x) << BANK0_READ_EVENT3_CS_LSB) & BANK0_READ_EVENT3_CS_MASK)
++#define BANK0_READ_EVENT2_DC_MSB 11
++#define BANK0_READ_EVENT2_DC_LSB 11
++#define BANK0_READ_EVENT2_DC_MASK 0x00000800
++#define BANK0_READ_EVENT2_DC_GET(x) (((x) & BANK0_READ_EVENT2_DC_MASK) >> BANK0_READ_EVENT2_DC_LSB)
++#define BANK0_READ_EVENT2_DC_SET(x) (((x) << BANK0_READ_EVENT2_DC_LSB) & BANK0_READ_EVENT2_DC_MASK)
++#define BANK0_READ_EVENT2_BE_MSB 10
++#define BANK0_READ_EVENT2_BE_LSB 10
++#define BANK0_READ_EVENT2_BE_MASK 0x00000400
++#define BANK0_READ_EVENT2_BE_GET(x) (((x) & BANK0_READ_EVENT2_BE_MASK) >> BANK0_READ_EVENT2_BE_LSB)
++#define BANK0_READ_EVENT2_BE_SET(x) (((x) << BANK0_READ_EVENT2_BE_LSB) & BANK0_READ_EVENT2_BE_MASK)
++#define BANK0_READ_EVENT2_OE_MSB 9
++#define BANK0_READ_EVENT2_OE_LSB 9
++#define BANK0_READ_EVENT2_OE_MASK 0x00000200
++#define BANK0_READ_EVENT2_OE_GET(x) (((x) & BANK0_READ_EVENT2_OE_MASK) >> BANK0_READ_EVENT2_OE_LSB)
++#define BANK0_READ_EVENT2_OE_SET(x) (((x) << BANK0_READ_EVENT2_OE_LSB) & BANK0_READ_EVENT2_OE_MASK)
++#define BANK0_READ_EVENT2_CS_MSB 8
++#define BANK0_READ_EVENT2_CS_LSB 8
++#define BANK0_READ_EVENT2_CS_MASK 0x00000100
++#define BANK0_READ_EVENT2_CS_GET(x) (((x) & BANK0_READ_EVENT2_CS_MASK) >> BANK0_READ_EVENT2_CS_LSB)
++#define BANK0_READ_EVENT2_CS_SET(x) (((x) << BANK0_READ_EVENT2_CS_LSB) & BANK0_READ_EVENT2_CS_MASK)
++#define BANK0_READ_EVENT1_DC_MSB 7
++#define BANK0_READ_EVENT1_DC_LSB 7
++#define BANK0_READ_EVENT1_DC_MASK 0x00000080
++#define BANK0_READ_EVENT1_DC_GET(x) (((x) & BANK0_READ_EVENT1_DC_MASK) >> BANK0_READ_EVENT1_DC_LSB)
++#define BANK0_READ_EVENT1_DC_SET(x) (((x) << BANK0_READ_EVENT1_DC_LSB) & BANK0_READ_EVENT1_DC_MASK)
++#define BANK0_READ_EVENT1_BE_MSB 6
++#define BANK0_READ_EVENT1_BE_LSB 6
++#define BANK0_READ_EVENT1_BE_MASK 0x00000040
++#define BANK0_READ_EVENT1_BE_GET(x) (((x) & BANK0_READ_EVENT1_BE_MASK) >> BANK0_READ_EVENT1_BE_LSB)
++#define BANK0_READ_EVENT1_BE_SET(x) (((x) << BANK0_READ_EVENT1_BE_LSB) & BANK0_READ_EVENT1_BE_MASK)
++#define BANK0_READ_EVENT1_OE_MSB 5
++#define BANK0_READ_EVENT1_OE_LSB 5
++#define BANK0_READ_EVENT1_OE_MASK 0x00000020
++#define BANK0_READ_EVENT1_OE_GET(x) (((x) & BANK0_READ_EVENT1_OE_MASK) >> BANK0_READ_EVENT1_OE_LSB)
++#define BANK0_READ_EVENT1_OE_SET(x) (((x) << BANK0_READ_EVENT1_OE_LSB) & BANK0_READ_EVENT1_OE_MASK)
++#define BANK0_READ_EVENT1_CS_MSB 4
++#define BANK0_READ_EVENT1_CS_LSB 4
++#define BANK0_READ_EVENT1_CS_MASK 0x00000010
++#define BANK0_READ_EVENT1_CS_GET(x) (((x) & BANK0_READ_EVENT1_CS_MASK) >> BANK0_READ_EVENT1_CS_LSB)
++#define BANK0_READ_EVENT1_CS_SET(x) (((x) << BANK0_READ_EVENT1_CS_LSB) & BANK0_READ_EVENT1_CS_MASK)
++#define BANK0_READ_EVENT0_DC_MSB 3
++#define BANK0_READ_EVENT0_DC_LSB 3
++#define BANK0_READ_EVENT0_DC_MASK 0x00000008
++#define BANK0_READ_EVENT0_DC_GET(x) (((x) & BANK0_READ_EVENT0_DC_MASK) >> BANK0_READ_EVENT0_DC_LSB)
++#define BANK0_READ_EVENT0_DC_SET(x) (((x) << BANK0_READ_EVENT0_DC_LSB) & BANK0_READ_EVENT0_DC_MASK)
++#define BANK0_READ_EVENT0_BE_MSB 2
++#define BANK0_READ_EVENT0_BE_LSB 2
++#define BANK0_READ_EVENT0_BE_MASK 0x00000004
++#define BANK0_READ_EVENT0_BE_GET(x) (((x) & BANK0_READ_EVENT0_BE_MASK) >> BANK0_READ_EVENT0_BE_LSB)
++#define BANK0_READ_EVENT0_BE_SET(x) (((x) << BANK0_READ_EVENT0_BE_LSB) & BANK0_READ_EVENT0_BE_MASK)
++#define BANK0_READ_EVENT0_OE_MSB 1
++#define BANK0_READ_EVENT0_OE_LSB 1
++#define BANK0_READ_EVENT0_OE_MASK 0x00000002
++#define BANK0_READ_EVENT0_OE_GET(x) (((x) & BANK0_READ_EVENT0_OE_MASK) >> BANK0_READ_EVENT0_OE_LSB)
++#define BANK0_READ_EVENT0_OE_SET(x) (((x) << BANK0_READ_EVENT0_OE_LSB) & BANK0_READ_EVENT0_OE_MASK)
++#define BANK0_READ_EVENT0_CS_MSB 0
++#define BANK0_READ_EVENT0_CS_LSB 0
++#define BANK0_READ_EVENT0_CS_MASK 0x00000001
++#define BANK0_READ_EVENT0_CS_GET(x) (((x) & BANK0_READ_EVENT0_CS_MASK) >> BANK0_READ_EVENT0_CS_LSB)
++#define BANK0_READ_EVENT0_CS_SET(x) (((x) << BANK0_READ_EVENT0_CS_LSB) & BANK0_READ_EVENT0_CS_MASK)
++
++#define BANK0_WRITE_ADDRESS 0x0c00400c
++#define BANK0_WRITE_OFFSET 0x0000000c
++#define BANK0_WRITE_ENABLE_WAIT_MSB 31
++#define BANK0_WRITE_ENABLE_WAIT_LSB 31
++#define BANK0_WRITE_ENABLE_WAIT_MASK 0x80000000
++#define BANK0_WRITE_ENABLE_WAIT_GET(x) (((x) & BANK0_WRITE_ENABLE_WAIT_MASK) >> BANK0_WRITE_ENABLE_WAIT_LSB)
++#define BANK0_WRITE_ENABLE_WAIT_SET(x) (((x) << BANK0_WRITE_ENABLE_WAIT_LSB) & BANK0_WRITE_ENABLE_WAIT_MASK)
++#define BANK0_WRITE_WAIT_EVENT_MSB 30
++#define BANK0_WRITE_WAIT_EVENT_LSB 28
++#define BANK0_WRITE_WAIT_EVENT_MASK 0x70000000
++#define BANK0_WRITE_WAIT_EVENT_GET(x) (((x) & BANK0_WRITE_WAIT_EVENT_MASK) >> BANK0_WRITE_WAIT_EVENT_LSB)
++#define BANK0_WRITE_WAIT_EVENT_SET(x) (((x) << BANK0_WRITE_WAIT_EVENT_LSB) & BANK0_WRITE_WAIT_EVENT_MASK)
++#define BANK0_WRITE_END_EVENT_MSB 26
++#define BANK0_WRITE_END_EVENT_LSB 24
++#define BANK0_WRITE_END_EVENT_MASK 0x07000000
++#define BANK0_WRITE_END_EVENT_GET(x) (((x) & BANK0_WRITE_END_EVENT_MASK) >> BANK0_WRITE_END_EVENT_LSB)
++#define BANK0_WRITE_END_EVENT_SET(x) (((x) << BANK0_WRITE_END_EVENT_LSB) & BANK0_WRITE_END_EVENT_MASK)
++#define BANK0_WRITE_BURST_END_EVENT_MSB 22
++#define BANK0_WRITE_BURST_END_EVENT_LSB 20
++#define BANK0_WRITE_BURST_END_EVENT_MASK 0x00700000
++#define BANK0_WRITE_BURST_END_EVENT_GET(x) (((x) & BANK0_WRITE_BURST_END_EVENT_MASK) >> BANK0_WRITE_BURST_END_EVENT_LSB)
++#define BANK0_WRITE_BURST_END_EVENT_SET(x) (((x) << BANK0_WRITE_BURST_END_EVENT_LSB) & BANK0_WRITE_BURST_END_EVENT_MASK)
++#define BANK0_WRITE_BURST_START_EVENT_MSB 18
++#define BANK0_WRITE_BURST_START_EVENT_LSB 16
++#define BANK0_WRITE_BURST_START_EVENT_MASK 0x00070000
++#define BANK0_WRITE_BURST_START_EVENT_GET(x) (((x) & BANK0_WRITE_BURST_START_EVENT_MASK) >> BANK0_WRITE_BURST_START_EVENT_LSB)
++#define BANK0_WRITE_BURST_START_EVENT_SET(x) (((x) << BANK0_WRITE_BURST_START_EVENT_LSB) & BANK0_WRITE_BURST_START_EVENT_MASK)
++#define BANK0_WRITE_EVENT3_BE_MSB 14
++#define BANK0_WRITE_EVENT3_BE_LSB 14
++#define BANK0_WRITE_EVENT3_BE_MASK 0x00004000
++#define BANK0_WRITE_EVENT3_BE_GET(x) (((x) & BANK0_WRITE_EVENT3_BE_MASK) >> BANK0_WRITE_EVENT3_BE_LSB)
++#define BANK0_WRITE_EVENT3_BE_SET(x) (((x) << BANK0_WRITE_EVENT3_BE_LSB) & BANK0_WRITE_EVENT3_BE_MASK)
++#define BANK0_WRITE_EVENT3_WE_MSB 13
++#define BANK0_WRITE_EVENT3_WE_LSB 13
++#define BANK0_WRITE_EVENT3_WE_MASK 0x00002000
++#define BANK0_WRITE_EVENT3_WE_GET(x) (((x) & BANK0_WRITE_EVENT3_WE_MASK) >> BANK0_WRITE_EVENT3_WE_LSB)
++#define BANK0_WRITE_EVENT3_WE_SET(x) (((x) << BANK0_WRITE_EVENT3_WE_LSB) & BANK0_WRITE_EVENT3_WE_MASK)
++#define BANK0_WRITE_EVENT3_CS_MSB 12
++#define BANK0_WRITE_EVENT3_CS_LSB 12
++#define BANK0_WRITE_EVENT3_CS_MASK 0x00001000
++#define BANK0_WRITE_EVENT3_CS_GET(x) (((x) & BANK0_WRITE_EVENT3_CS_MASK) >> BANK0_WRITE_EVENT3_CS_LSB)
++#define BANK0_WRITE_EVENT3_CS_SET(x) (((x) << BANK0_WRITE_EVENT3_CS_LSB) & BANK0_WRITE_EVENT3_CS_MASK)
++#define BANK0_WRITE_EVENT2_BE_MSB 10
++#define BANK0_WRITE_EVENT2_BE_LSB 10
++#define BANK0_WRITE_EVENT2_BE_MASK 0x00000400
++#define BANK0_WRITE_EVENT2_BE_GET(x) (((x) & BANK0_WRITE_EVENT2_BE_MASK) >> BANK0_WRITE_EVENT2_BE_LSB)
++#define BANK0_WRITE_EVENT2_BE_SET(x) (((x) << BANK0_WRITE_EVENT2_BE_LSB) & BANK0_WRITE_EVENT2_BE_MASK)
++#define BANK0_WRITE_EVENT2_WE_MSB 9
++#define BANK0_WRITE_EVENT2_WE_LSB 9
++#define BANK0_WRITE_EVENT2_WE_MASK 0x00000200
++#define BANK0_WRITE_EVENT2_WE_GET(x) (((x) & BANK0_WRITE_EVENT2_WE_MASK) >> BANK0_WRITE_EVENT2_WE_LSB)
++#define BANK0_WRITE_EVENT2_WE_SET(x) (((x) << BANK0_WRITE_EVENT2_WE_LSB) & BANK0_WRITE_EVENT2_WE_MASK)
++#define BANK0_WRITE_EVENT2_CS_MSB 8
++#define BANK0_WRITE_EVENT2_CS_LSB 8
++#define BANK0_WRITE_EVENT2_CS_MASK 0x00000100
++#define BANK0_WRITE_EVENT2_CS_GET(x) (((x) & BANK0_WRITE_EVENT2_CS_MASK) >> BANK0_WRITE_EVENT2_CS_LSB)
++#define BANK0_WRITE_EVENT2_CS_SET(x) (((x) << BANK0_WRITE_EVENT2_CS_LSB) & BANK0_WRITE_EVENT2_CS_MASK)
++#define BANK0_WRITE_EVENT1_BE_MSB 6
++#define BANK0_WRITE_EVENT1_BE_LSB 6
++#define BANK0_WRITE_EVENT1_BE_MASK 0x00000040
++#define BANK0_WRITE_EVENT1_BE_GET(x) (((x) & BANK0_WRITE_EVENT1_BE_MASK) >> BANK0_WRITE_EVENT1_BE_LSB)
++#define BANK0_WRITE_EVENT1_BE_SET(x) (((x) << BANK0_WRITE_EVENT1_BE_LSB) & BANK0_WRITE_EVENT1_BE_MASK)
++#define BANK0_WRITE_EVENT1_WE_MSB 5
++#define BANK0_WRITE_EVENT1_WE_LSB 5
++#define BANK0_WRITE_EVENT1_WE_MASK 0x00000020
++#define BANK0_WRITE_EVENT1_WE_GET(x) (((x) & BANK0_WRITE_EVENT1_WE_MASK) >> BANK0_WRITE_EVENT1_WE_LSB)
++#define BANK0_WRITE_EVENT1_WE_SET(x) (((x) << BANK0_WRITE_EVENT1_WE_LSB) & BANK0_WRITE_EVENT1_WE_MASK)
++#define BANK0_WRITE_EVENT1_CS_MSB 4
++#define BANK0_WRITE_EVENT1_CS_LSB 4
++#define BANK0_WRITE_EVENT1_CS_MASK 0x00000010
++#define BANK0_WRITE_EVENT1_CS_GET(x) (((x) & BANK0_WRITE_EVENT1_CS_MASK) >> BANK0_WRITE_EVENT1_CS_LSB)
++#define BANK0_WRITE_EVENT1_CS_SET(x) (((x) << BANK0_WRITE_EVENT1_CS_LSB) & BANK0_WRITE_EVENT1_CS_MASK)
++#define BANK0_WRITE_EVENT0_BE_MSB 2
++#define BANK0_WRITE_EVENT0_BE_LSB 2
++#define BANK0_WRITE_EVENT0_BE_MASK 0x00000004
++#define BANK0_WRITE_EVENT0_BE_GET(x) (((x) & BANK0_WRITE_EVENT0_BE_MASK) >> BANK0_WRITE_EVENT0_BE_LSB)
++#define BANK0_WRITE_EVENT0_BE_SET(x) (((x) << BANK0_WRITE_EVENT0_BE_LSB) & BANK0_WRITE_EVENT0_BE_MASK)
++#define BANK0_WRITE_EVENT0_WE_MSB 1
++#define BANK0_WRITE_EVENT0_WE_LSB 1
++#define BANK0_WRITE_EVENT0_WE_MASK 0x00000002
++#define BANK0_WRITE_EVENT0_WE_GET(x) (((x) & BANK0_WRITE_EVENT0_WE_MASK) >> BANK0_WRITE_EVENT0_WE_LSB)
++#define BANK0_WRITE_EVENT0_WE_SET(x) (((x) << BANK0_WRITE_EVENT0_WE_LSB) & BANK0_WRITE_EVENT0_WE_MASK)
++#define BANK0_WRITE_EVENT0_CS_MSB 0
++#define BANK0_WRITE_EVENT0_CS_LSB 0
++#define BANK0_WRITE_EVENT0_CS_MASK 0x00000001
++#define BANK0_WRITE_EVENT0_CS_GET(x) (((x) & BANK0_WRITE_EVENT0_CS_MASK) >> BANK0_WRITE_EVENT0_CS_LSB)
++#define BANK0_WRITE_EVENT0_CS_SET(x) (((x) << BANK0_WRITE_EVENT0_CS_LSB) & BANK0_WRITE_EVENT0_CS_MASK)
++
++#define BANK1_ADDR_ADDRESS 0x0c004010
++#define BANK1_ADDR_OFFSET 0x00000010
++#define BANK1_ADDR_SIZE_MSB 31
++#define BANK1_ADDR_SIZE_LSB 28
++#define BANK1_ADDR_SIZE_MASK 0xf0000000
++#define BANK1_ADDR_SIZE_GET(x) (((x) & BANK1_ADDR_SIZE_MASK) >> BANK1_ADDR_SIZE_LSB)
++#define BANK1_ADDR_SIZE_SET(x) (((x) << BANK1_ADDR_SIZE_LSB) & BANK1_ADDR_SIZE_MASK)
++#define BANK1_ADDR_BASE_MSB 27
++#define BANK1_ADDR_BASE_LSB 10
++#define BANK1_ADDR_BASE_MASK 0x0ffffc00
++#define BANK1_ADDR_BASE_GET(x) (((x) & BANK1_ADDR_BASE_MASK) >> BANK1_ADDR_BASE_LSB)
++#define BANK1_ADDR_BASE_SET(x) (((x) << BANK1_ADDR_BASE_LSB) & BANK1_ADDR_BASE_MASK)
++
++#define BANK1_CONFIG_ADDRESS 0x0c004014
++#define BANK1_CONFIG_OFFSET 0x00000014
++#define BANK1_CONFIG_ENABLE_MSB 31
++#define BANK1_CONFIG_ENABLE_LSB 31
++#define BANK1_CONFIG_ENABLE_MASK 0x80000000
++#define BANK1_CONFIG_ENABLE_GET(x) (((x) & BANK1_CONFIG_ENABLE_MASK) >> BANK1_CONFIG_ENABLE_LSB)
++#define BANK1_CONFIG_ENABLE_SET(x) (((x) << BANK1_CONFIG_ENABLE_LSB) & BANK1_CONFIG_ENABLE_MASK)
++#define BANK1_CONFIG_WIDTH_MSB 28
++#define BANK1_CONFIG_WIDTH_LSB 28
++#define BANK1_CONFIG_WIDTH_MASK 0x10000000
++#define BANK1_CONFIG_WIDTH_GET(x) (((x) & BANK1_CONFIG_WIDTH_MASK) >> BANK1_CONFIG_WIDTH_LSB)
++#define BANK1_CONFIG_WIDTH_SET(x) (((x) << BANK1_CONFIG_WIDTH_LSB) & BANK1_CONFIG_WIDTH_MASK)
++#define BANK1_CONFIG_PROTECT_MSB 26
++#define BANK1_CONFIG_PROTECT_LSB 26
++#define BANK1_CONFIG_PROTECT_MASK 0x04000000
++#define BANK1_CONFIG_PROTECT_GET(x) (((x) & BANK1_CONFIG_PROTECT_MASK) >> BANK1_CONFIG_PROTECT_LSB)
++#define BANK1_CONFIG_PROTECT_SET(x) (((x) << BANK1_CONFIG_PROTECT_LSB) & BANK1_CONFIG_PROTECT_MASK)
++#define BANK1_CONFIG_WB_ENABLE_MSB 25
++#define BANK1_CONFIG_WB_ENABLE_LSB 25
++#define BANK1_CONFIG_WB_ENABLE_MASK 0x02000000
++#define BANK1_CONFIG_WB_ENABLE_GET(x) (((x) & BANK1_CONFIG_WB_ENABLE_MASK) >> BANK1_CONFIG_WB_ENABLE_LSB)
++#define BANK1_CONFIG_WB_ENABLE_SET(x) (((x) << BANK1_CONFIG_WB_ENABLE_LSB) & BANK1_CONFIG_WB_ENABLE_MASK)
++#define BANK1_CONFIG_WB_FLUSH_MSB 24
++#define BANK1_CONFIG_WB_FLUSH_LSB 24
++#define BANK1_CONFIG_WB_FLUSH_MASK 0x01000000
++#define BANK1_CONFIG_WB_FLUSH_GET(x) (((x) & BANK1_CONFIG_WB_FLUSH_MASK) >> BANK1_CONFIG_WB_FLUSH_LSB)
++#define BANK1_CONFIG_WB_FLUSH_SET(x) (((x) << BANK1_CONFIG_WB_FLUSH_LSB) & BANK1_CONFIG_WB_FLUSH_MASK)
++#define BANK1_CONFIG_SCALE_MSB 21
++#define BANK1_CONFIG_SCALE_LSB 20
++#define BANK1_CONFIG_SCALE_MASK 0x00300000
++#define BANK1_CONFIG_SCALE_GET(x) (((x) & BANK1_CONFIG_SCALE_MASK) >> BANK1_CONFIG_SCALE_LSB)
++#define BANK1_CONFIG_SCALE_SET(x) (((x) << BANK1_CONFIG_SCALE_LSB) & BANK1_CONFIG_SCALE_MASK)
++#define BANK1_CONFIG_HOLDOFF_MSB 19
++#define BANK1_CONFIG_HOLDOFF_LSB 16
++#define BANK1_CONFIG_HOLDOFF_MASK 0x000f0000
++#define BANK1_CONFIG_HOLDOFF_GET(x) (((x) & BANK1_CONFIG_HOLDOFF_MASK) >> BANK1_CONFIG_HOLDOFF_LSB)
++#define BANK1_CONFIG_HOLDOFF_SET(x) (((x) << BANK1_CONFIG_HOLDOFF_LSB) & BANK1_CONFIG_HOLDOFF_MASK)
++#define BANK1_CONFIG_TIMER3_MSB 15
++#define BANK1_CONFIG_TIMER3_LSB 12
++#define BANK1_CONFIG_TIMER3_MASK 0x0000f000
++#define BANK1_CONFIG_TIMER3_GET(x) (((x) & BANK1_CONFIG_TIMER3_MASK) >> BANK1_CONFIG_TIMER3_LSB)
++#define BANK1_CONFIG_TIMER3_SET(x) (((x) << BANK1_CONFIG_TIMER3_LSB) & BANK1_CONFIG_TIMER3_MASK)
++#define BANK1_CONFIG_TIMER2_MSB 11
++#define BANK1_CONFIG_TIMER2_LSB 8
++#define BANK1_CONFIG_TIMER2_MASK 0x00000f00
++#define BANK1_CONFIG_TIMER2_GET(x) (((x) & BANK1_CONFIG_TIMER2_MASK) >> BANK1_CONFIG_TIMER2_LSB)
++#define BANK1_CONFIG_TIMER2_SET(x) (((x) << BANK1_CONFIG_TIMER2_LSB) & BANK1_CONFIG_TIMER2_MASK)
++#define BANK1_CONFIG_TIMER1_MSB 7
++#define BANK1_CONFIG_TIMER1_LSB 4
++#define BANK1_CONFIG_TIMER1_MASK 0x000000f0
++#define BANK1_CONFIG_TIMER1_GET(x) (((x) & BANK1_CONFIG_TIMER1_MASK) >> BANK1_CONFIG_TIMER1_LSB)
++#define BANK1_CONFIG_TIMER1_SET(x) (((x) << BANK1_CONFIG_TIMER1_LSB) & BANK1_CONFIG_TIMER1_MASK)
++#define BANK1_CONFIG_TIMER0_MSB 3
++#define BANK1_CONFIG_TIMER0_LSB 0
++#define BANK1_CONFIG_TIMER0_MASK 0x0000000f
++#define BANK1_CONFIG_TIMER0_GET(x) (((x) & BANK1_CONFIG_TIMER0_MASK) >> BANK1_CONFIG_TIMER0_LSB)
++#define BANK1_CONFIG_TIMER0_SET(x) (((x) << BANK1_CONFIG_TIMER0_LSB) & BANK1_CONFIG_TIMER0_MASK)
++
++#define BANK1_READ_ADDRESS 0x0c004018
++#define BANK1_READ_OFFSET 0x00000018
++#define BANK1_READ_ENABLE_WAIT_MSB 31
++#define BANK1_READ_ENABLE_WAIT_LSB 31
++#define BANK1_READ_ENABLE_WAIT_MASK 0x80000000
++#define BANK1_READ_ENABLE_WAIT_GET(x) (((x) & BANK1_READ_ENABLE_WAIT_MASK) >> BANK1_READ_ENABLE_WAIT_LSB)
++#define BANK1_READ_ENABLE_WAIT_SET(x) (((x) << BANK1_READ_ENABLE_WAIT_LSB) & BANK1_READ_ENABLE_WAIT_MASK)
++#define BANK1_READ_WAIT_EVENT_MSB 30
++#define BANK1_READ_WAIT_EVENT_LSB 28
++#define BANK1_READ_WAIT_EVENT_MASK 0x70000000
++#define BANK1_READ_WAIT_EVENT_GET(x) (((x) & BANK1_READ_WAIT_EVENT_MASK) >> BANK1_READ_WAIT_EVENT_LSB)
++#define BANK1_READ_WAIT_EVENT_SET(x) (((x) << BANK1_READ_WAIT_EVENT_LSB) & BANK1_READ_WAIT_EVENT_MASK)
++#define BANK1_READ_END_EVENT_MSB 26
++#define BANK1_READ_END_EVENT_LSB 24
++#define BANK1_READ_END_EVENT_MASK 0x07000000
++#define BANK1_READ_END_EVENT_GET(x) (((x) & BANK1_READ_END_EVENT_MASK) >> BANK1_READ_END_EVENT_LSB)
++#define BANK1_READ_END_EVENT_SET(x) (((x) << BANK1_READ_END_EVENT_LSB) & BANK1_READ_END_EVENT_MASK)
++#define BANK1_READ_BURST_END_EVENT_MSB 22
++#define BANK1_READ_BURST_END_EVENT_LSB 20
++#define BANK1_READ_BURST_END_EVENT_MASK 0x00700000
++#define BANK1_READ_BURST_END_EVENT_GET(x) (((x) & BANK1_READ_BURST_END_EVENT_MASK) >> BANK1_READ_BURST_END_EVENT_LSB)
++#define BANK1_READ_BURST_END_EVENT_SET(x) (((x) << BANK1_READ_BURST_END_EVENT_LSB) & BANK1_READ_BURST_END_EVENT_MASK)
++#define BANK1_READ_BURST_START_EVENT_MSB 18
++#define BANK1_READ_BURST_START_EVENT_LSB 16
++#define BANK1_READ_BURST_START_EVENT_MASK 0x00070000
++#define BANK1_READ_BURST_START_EVENT_GET(x) (((x) & BANK1_READ_BURST_START_EVENT_MASK) >> BANK1_READ_BURST_START_EVENT_LSB)
++#define BANK1_READ_BURST_START_EVENT_SET(x) (((x) << BANK1_READ_BURST_START_EVENT_LSB) & BANK1_READ_BURST_START_EVENT_MASK)
++#define BANK1_READ_EVENT3_DC_MSB 15
++#define BANK1_READ_EVENT3_DC_LSB 15
++#define BANK1_READ_EVENT3_DC_MASK 0x00008000
++#define BANK1_READ_EVENT3_DC_GET(x) (((x) & BANK1_READ_EVENT3_DC_MASK) >> BANK1_READ_EVENT3_DC_LSB)
++#define BANK1_READ_EVENT3_DC_SET(x) (((x) << BANK1_READ_EVENT3_DC_LSB) & BANK1_READ_EVENT3_DC_MASK)
++#define BANK1_READ_EVENT3_BE_MSB 14
++#define BANK1_READ_EVENT3_BE_LSB 14
++#define BANK1_READ_EVENT3_BE_MASK 0x00004000
++#define BANK1_READ_EVENT3_BE_GET(x) (((x) & BANK1_READ_EVENT3_BE_MASK) >> BANK1_READ_EVENT3_BE_LSB)
++#define BANK1_READ_EVENT3_BE_SET(x) (((x) << BANK1_READ_EVENT3_BE_LSB) & BANK1_READ_EVENT3_BE_MASK)
++#define BANK1_READ_EVENT3_OE_MSB 13
++#define BANK1_READ_EVENT3_OE_LSB 13
++#define BANK1_READ_EVENT3_OE_MASK 0x00002000
++#define BANK1_READ_EVENT3_OE_GET(x) (((x) & BANK1_READ_EVENT3_OE_MASK) >> BANK1_READ_EVENT3_OE_LSB)
++#define BANK1_READ_EVENT3_OE_SET(x) (((x) << BANK1_READ_EVENT3_OE_LSB) & BANK1_READ_EVENT3_OE_MASK)
++#define BANK1_READ_EVENT3_CS_MSB 12
++#define BANK1_READ_EVENT3_CS_LSB 12
++#define BANK1_READ_EVENT3_CS_MASK 0x00001000
++#define BANK1_READ_EVENT3_CS_GET(x) (((x) & BANK1_READ_EVENT3_CS_MASK) >> BANK1_READ_EVENT3_CS_LSB)
++#define BANK1_READ_EVENT3_CS_SET(x) (((x) << BANK1_READ_EVENT3_CS_LSB) & BANK1_READ_EVENT3_CS_MASK)
++#define BANK1_READ_EVENT2_DC_MSB 11
++#define BANK1_READ_EVENT2_DC_LSB 11
++#define BANK1_READ_EVENT2_DC_MASK 0x00000800
++#define BANK1_READ_EVENT2_DC_GET(x) (((x) & BANK1_READ_EVENT2_DC_MASK) >> BANK1_READ_EVENT2_DC_LSB)
++#define BANK1_READ_EVENT2_DC_SET(x) (((x) << BANK1_READ_EVENT2_DC_LSB) & BANK1_READ_EVENT2_DC_MASK)
++#define BANK1_READ_EVENT2_BE_MSB 10
++#define BANK1_READ_EVENT2_BE_LSB 10
++#define BANK1_READ_EVENT2_BE_MASK 0x00000400
++#define BANK1_READ_EVENT2_BE_GET(x) (((x) & BANK1_READ_EVENT2_BE_MASK) >> BANK1_READ_EVENT2_BE_LSB)
++#define BANK1_READ_EVENT2_BE_SET(x) (((x) << BANK1_READ_EVENT2_BE_LSB) & BANK1_READ_EVENT2_BE_MASK)
++#define BANK1_READ_EVENT2_OE_MSB 9
++#define BANK1_READ_EVENT2_OE_LSB 9
++#define BANK1_READ_EVENT2_OE_MASK 0x00000200
++#define BANK1_READ_EVENT2_OE_GET(x) (((x) & BANK1_READ_EVENT2_OE_MASK) >> BANK1_READ_EVENT2_OE_LSB)
++#define BANK1_READ_EVENT2_OE_SET(x) (((x) << BANK1_READ_EVENT2_OE_LSB) & BANK1_READ_EVENT2_OE_MASK)
++#define BANK1_READ_EVENT2_CS_MSB 8
++#define BANK1_READ_EVENT2_CS_LSB 8
++#define BANK1_READ_EVENT2_CS_MASK 0x00000100
++#define BANK1_READ_EVENT2_CS_GET(x) (((x) & BANK1_READ_EVENT2_CS_MASK) >> BANK1_READ_EVENT2_CS_LSB)
++#define BANK1_READ_EVENT2_CS_SET(x) (((x) << BANK1_READ_EVENT2_CS_LSB) & BANK1_READ_EVENT2_CS_MASK)
++#define BANK1_READ_EVENT1_DC_MSB 7
++#define BANK1_READ_EVENT1_DC_LSB 7
++#define BANK1_READ_EVENT1_DC_MASK 0x00000080
++#define BANK1_READ_EVENT1_DC_GET(x) (((x) & BANK1_READ_EVENT1_DC_MASK) >> BANK1_READ_EVENT1_DC_LSB)
++#define BANK1_READ_EVENT1_DC_SET(x) (((x) << BANK1_READ_EVENT1_DC_LSB) & BANK1_READ_EVENT1_DC_MASK)
++#define BANK1_READ_EVENT1_BE_MSB 6
++#define BANK1_READ_EVENT1_BE_LSB 6
++#define BANK1_READ_EVENT1_BE_MASK 0x00000040
++#define BANK1_READ_EVENT1_BE_GET(x) (((x) & BANK1_READ_EVENT1_BE_MASK) >> BANK1_READ_EVENT1_BE_LSB)
++#define BANK1_READ_EVENT1_BE_SET(x) (((x) << BANK1_READ_EVENT1_BE_LSB) & BANK1_READ_EVENT1_BE_MASK)
++#define BANK1_READ_EVENT1_OE_MSB 5
++#define BANK1_READ_EVENT1_OE_LSB 5
++#define BANK1_READ_EVENT1_OE_MASK 0x00000020
++#define BANK1_READ_EVENT1_OE_GET(x) (((x) & BANK1_READ_EVENT1_OE_MASK) >> BANK1_READ_EVENT1_OE_LSB)
++#define BANK1_READ_EVENT1_OE_SET(x) (((x) << BANK1_READ_EVENT1_OE_LSB) & BANK1_READ_EVENT1_OE_MASK)
++#define BANK1_READ_EVENT1_CS_MSB 4
++#define BANK1_READ_EVENT1_CS_LSB 4
++#define BANK1_READ_EVENT1_CS_MASK 0x00000010
++#define BANK1_READ_EVENT1_CS_GET(x) (((x) & BANK1_READ_EVENT1_CS_MASK) >> BANK1_READ_EVENT1_CS_LSB)
++#define BANK1_READ_EVENT1_CS_SET(x) (((x) << BANK1_READ_EVENT1_CS_LSB) & BANK1_READ_EVENT1_CS_MASK)
++#define BANK1_READ_EVENT0_DC_MSB 3
++#define BANK1_READ_EVENT0_DC_LSB 3
++#define BANK1_READ_EVENT0_DC_MASK 0x00000008
++#define BANK1_READ_EVENT0_DC_GET(x) (((x) & BANK1_READ_EVENT0_DC_MASK) >> BANK1_READ_EVENT0_DC_LSB)
++#define BANK1_READ_EVENT0_DC_SET(x) (((x) << BANK1_READ_EVENT0_DC_LSB) & BANK1_READ_EVENT0_DC_MASK)
++#define BANK1_READ_EVENT0_BE_MSB 2
++#define BANK1_READ_EVENT0_BE_LSB 2
++#define BANK1_READ_EVENT0_BE_MASK 0x00000004
++#define BANK1_READ_EVENT0_BE_GET(x) (((x) & BANK1_READ_EVENT0_BE_MASK) >> BANK1_READ_EVENT0_BE_LSB)
++#define BANK1_READ_EVENT0_BE_SET(x) (((x) << BANK1_READ_EVENT0_BE_LSB) & BANK1_READ_EVENT0_BE_MASK)
++#define BANK1_READ_EVENT0_OE_MSB 1
++#define BANK1_READ_EVENT0_OE_LSB 1
++#define BANK1_READ_EVENT0_OE_MASK 0x00000002
++#define BANK1_READ_EVENT0_OE_GET(x) (((x) & BANK1_READ_EVENT0_OE_MASK) >> BANK1_READ_EVENT0_OE_LSB)
++#define BANK1_READ_EVENT0_OE_SET(x) (((x) << BANK1_READ_EVENT0_OE_LSB) & BANK1_READ_EVENT0_OE_MASK)
++#define BANK1_READ_EVENT0_CS_MSB 0
++#define BANK1_READ_EVENT0_CS_LSB 0
++#define BANK1_READ_EVENT0_CS_MASK 0x00000001
++#define BANK1_READ_EVENT0_CS_GET(x) (((x) & BANK1_READ_EVENT0_CS_MASK) >> BANK1_READ_EVENT0_CS_LSB)
++#define BANK1_READ_EVENT0_CS_SET(x) (((x) << BANK1_READ_EVENT0_CS_LSB) & BANK1_READ_EVENT0_CS_MASK)
++
++#define BANK1_WRITE_ADDRESS 0x0c00401c
++#define BANK1_WRITE_OFFSET 0x0000001c
++#define BANK1_WRITE_ENABLE_WAIT_MSB 31
++#define BANK1_WRITE_ENABLE_WAIT_LSB 31
++#define BANK1_WRITE_ENABLE_WAIT_MASK 0x80000000
++#define BANK1_WRITE_ENABLE_WAIT_GET(x) (((x) & BANK1_WRITE_ENABLE_WAIT_MASK) >> BANK1_WRITE_ENABLE_WAIT_LSB)
++#define BANK1_WRITE_ENABLE_WAIT_SET(x) (((x) << BANK1_WRITE_ENABLE_WAIT_LSB) & BANK1_WRITE_ENABLE_WAIT_MASK)
++#define BANK1_WRITE_WAIT_EVENT_MSB 30
++#define BANK1_WRITE_WAIT_EVENT_LSB 28
++#define BANK1_WRITE_WAIT_EVENT_MASK 0x70000000
++#define BANK1_WRITE_WAIT_EVENT_GET(x) (((x) & BANK1_WRITE_WAIT_EVENT_MASK) >> BANK1_WRITE_WAIT_EVENT_LSB)
++#define BANK1_WRITE_WAIT_EVENT_SET(x) (((x) << BANK1_WRITE_WAIT_EVENT_LSB) & BANK1_WRITE_WAIT_EVENT_MASK)
++#define BANK1_WRITE_END_EVENT_MSB 26
++#define BANK1_WRITE_END_EVENT_LSB 24
++#define BANK1_WRITE_END_EVENT_MASK 0x07000000
++#define BANK1_WRITE_END_EVENT_GET(x) (((x) & BANK1_WRITE_END_EVENT_MASK) >> BANK1_WRITE_END_EVENT_LSB)
++#define BANK1_WRITE_END_EVENT_SET(x) (((x) << BANK1_WRITE_END_EVENT_LSB) & BANK1_WRITE_END_EVENT_MASK)
++#define BANK1_WRITE_BURST_END_EVENT_MSB 22
++#define BANK1_WRITE_BURST_END_EVENT_LSB 20
++#define BANK1_WRITE_BURST_END_EVENT_MASK 0x00700000
++#define BANK1_WRITE_BURST_END_EVENT_GET(x) (((x) & BANK1_WRITE_BURST_END_EVENT_MASK) >> BANK1_WRITE_BURST_END_EVENT_LSB)
++#define BANK1_WRITE_BURST_END_EVENT_SET(x) (((x) << BANK1_WRITE_BURST_END_EVENT_LSB) & BANK1_WRITE_BURST_END_EVENT_MASK)
++#define BANK1_WRITE_BURST_START_EVENT_MSB 18
++#define BANK1_WRITE_BURST_START_EVENT_LSB 16
++#define BANK1_WRITE_BURST_START_EVENT_MASK 0x00070000
++#define BANK1_WRITE_BURST_START_EVENT_GET(x) (((x) & BANK1_WRITE_BURST_START_EVENT_MASK) >> BANK1_WRITE_BURST_START_EVENT_LSB)
++#define BANK1_WRITE_BURST_START_EVENT_SET(x) (((x) << BANK1_WRITE_BURST_START_EVENT_LSB) & BANK1_WRITE_BURST_START_EVENT_MASK)
++#define BANK1_WRITE_EVENT3_BE_MSB 14
++#define BANK1_WRITE_EVENT3_BE_LSB 14
++#define BANK1_WRITE_EVENT3_BE_MASK 0x00004000
++#define BANK1_WRITE_EVENT3_BE_GET(x) (((x) & BANK1_WRITE_EVENT3_BE_MASK) >> BANK1_WRITE_EVENT3_BE_LSB)
++#define BANK1_WRITE_EVENT3_BE_SET(x) (((x) << BANK1_WRITE_EVENT3_BE_LSB) & BANK1_WRITE_EVENT3_BE_MASK)
++#define BANK1_WRITE_EVENT3_WE_MSB 13
++#define BANK1_WRITE_EVENT3_WE_LSB 13
++#define BANK1_WRITE_EVENT3_WE_MASK 0x00002000
++#define BANK1_WRITE_EVENT3_WE_GET(x) (((x) & BANK1_WRITE_EVENT3_WE_MASK) >> BANK1_WRITE_EVENT3_WE_LSB)
++#define BANK1_WRITE_EVENT3_WE_SET(x) (((x) << BANK1_WRITE_EVENT3_WE_LSB) & BANK1_WRITE_EVENT3_WE_MASK)
++#define BANK1_WRITE_EVENT3_CS_MSB 12
++#define BANK1_WRITE_EVENT3_CS_LSB 12
++#define BANK1_WRITE_EVENT3_CS_MASK 0x00001000
++#define BANK1_WRITE_EVENT3_CS_GET(x) (((x) & BANK1_WRITE_EVENT3_CS_MASK) >> BANK1_WRITE_EVENT3_CS_LSB)
++#define BANK1_WRITE_EVENT3_CS_SET(x) (((x) << BANK1_WRITE_EVENT3_CS_LSB) & BANK1_WRITE_EVENT3_CS_MASK)
++#define BANK1_WRITE_EVENT2_BE_MSB 10
++#define BANK1_WRITE_EVENT2_BE_LSB 10
++#define BANK1_WRITE_EVENT2_BE_MASK 0x00000400
++#define BANK1_WRITE_EVENT2_BE_GET(x) (((x) & BANK1_WRITE_EVENT2_BE_MASK) >> BANK1_WRITE_EVENT2_BE_LSB)
++#define BANK1_WRITE_EVENT2_BE_SET(x) (((x) << BANK1_WRITE_EVENT2_BE_LSB) & BANK1_WRITE_EVENT2_BE_MASK)
++#define BANK1_WRITE_EVENT2_WE_MSB 9
++#define BANK1_WRITE_EVENT2_WE_LSB 9
++#define BANK1_WRITE_EVENT2_WE_MASK 0x00000200
++#define BANK1_WRITE_EVENT2_WE_GET(x) (((x) & BANK1_WRITE_EVENT2_WE_MASK) >> BANK1_WRITE_EVENT2_WE_LSB)
++#define BANK1_WRITE_EVENT2_WE_SET(x) (((x) << BANK1_WRITE_EVENT2_WE_LSB) & BANK1_WRITE_EVENT2_WE_MASK)
++#define BANK1_WRITE_EVENT2_CS_MSB 8
++#define BANK1_WRITE_EVENT2_CS_LSB 8
++#define BANK1_WRITE_EVENT2_CS_MASK 0x00000100
++#define BANK1_WRITE_EVENT2_CS_GET(x) (((x) & BANK1_WRITE_EVENT2_CS_MASK) >> BANK1_WRITE_EVENT2_CS_LSB)
++#define BANK1_WRITE_EVENT2_CS_SET(x) (((x) << BANK1_WRITE_EVENT2_CS_LSB) & BANK1_WRITE_EVENT2_CS_MASK)
++#define BANK1_WRITE_EVENT1_BE_MSB 6
++#define BANK1_WRITE_EVENT1_BE_LSB 6
++#define BANK1_WRITE_EVENT1_BE_MASK 0x00000040
++#define BANK1_WRITE_EVENT1_BE_GET(x) (((x) & BANK1_WRITE_EVENT1_BE_MASK) >> BANK1_WRITE_EVENT1_BE_LSB)
++#define BANK1_WRITE_EVENT1_BE_SET(x) (((x) << BANK1_WRITE_EVENT1_BE_LSB) & BANK1_WRITE_EVENT1_BE_MASK)
++#define BANK1_WRITE_EVENT1_WE_MSB 5
++#define BANK1_WRITE_EVENT1_WE_LSB 5
++#define BANK1_WRITE_EVENT1_WE_MASK 0x00000020
++#define BANK1_WRITE_EVENT1_WE_GET(x) (((x) & BANK1_WRITE_EVENT1_WE_MASK) >> BANK1_WRITE_EVENT1_WE_LSB)
++#define BANK1_WRITE_EVENT1_WE_SET(x) (((x) << BANK1_WRITE_EVENT1_WE_LSB) & BANK1_WRITE_EVENT1_WE_MASK)
++#define BANK1_WRITE_EVENT1_CS_MSB 4
++#define BANK1_WRITE_EVENT1_CS_LSB 4
++#define BANK1_WRITE_EVENT1_CS_MASK 0x00000010
++#define BANK1_WRITE_EVENT1_CS_GET(x) (((x) & BANK1_WRITE_EVENT1_CS_MASK) >> BANK1_WRITE_EVENT1_CS_LSB)
++#define BANK1_WRITE_EVENT1_CS_SET(x) (((x) << BANK1_WRITE_EVENT1_CS_LSB) & BANK1_WRITE_EVENT1_CS_MASK)
++#define BANK1_WRITE_EVENT0_BE_MSB 2
++#define BANK1_WRITE_EVENT0_BE_LSB 2
++#define BANK1_WRITE_EVENT0_BE_MASK 0x00000004
++#define BANK1_WRITE_EVENT0_BE_GET(x) (((x) & BANK1_WRITE_EVENT0_BE_MASK) >> BANK1_WRITE_EVENT0_BE_LSB)
++#define BANK1_WRITE_EVENT0_BE_SET(x) (((x) << BANK1_WRITE_EVENT0_BE_LSB) & BANK1_WRITE_EVENT0_BE_MASK)
++#define BANK1_WRITE_EVENT0_WE_MSB 1
++#define BANK1_WRITE_EVENT0_WE_LSB 1
++#define BANK1_WRITE_EVENT0_WE_MASK 0x00000002
++#define BANK1_WRITE_EVENT0_WE_GET(x) (((x) & BANK1_WRITE_EVENT0_WE_MASK) >> BANK1_WRITE_EVENT0_WE_LSB)
++#define BANK1_WRITE_EVENT0_WE_SET(x) (((x) << BANK1_WRITE_EVENT0_WE_LSB) & BANK1_WRITE_EVENT0_WE_MASK)
++#define BANK1_WRITE_EVENT0_CS_MSB 0
++#define BANK1_WRITE_EVENT0_CS_LSB 0
++#define BANK1_WRITE_EVENT0_CS_MASK 0x00000001
++#define BANK1_WRITE_EVENT0_CS_GET(x) (((x) & BANK1_WRITE_EVENT0_CS_MASK) >> BANK1_WRITE_EVENT0_CS_LSB)
++#define BANK1_WRITE_EVENT0_CS_SET(x) (((x) << BANK1_WRITE_EVENT0_CS_LSB) & BANK1_WRITE_EVENT0_CS_MASK)
++
++#define BANK2_ADDR_ADDRESS 0x0c004020
++#define BANK2_ADDR_OFFSET 0x00000020
++#define BANK2_ADDR_SIZE_MSB 31
++#define BANK2_ADDR_SIZE_LSB 28
++#define BANK2_ADDR_SIZE_MASK 0xf0000000
++#define BANK2_ADDR_SIZE_GET(x) (((x) & BANK2_ADDR_SIZE_MASK) >> BANK2_ADDR_SIZE_LSB)
++#define BANK2_ADDR_SIZE_SET(x) (((x) << BANK2_ADDR_SIZE_LSB) & BANK2_ADDR_SIZE_MASK)
++#define BANK2_ADDR_BASE_MSB 27
++#define BANK2_ADDR_BASE_LSB 10
++#define BANK2_ADDR_BASE_MASK 0x0ffffc00
++#define BANK2_ADDR_BASE_GET(x) (((x) & BANK2_ADDR_BASE_MASK) >> BANK2_ADDR_BASE_LSB)
++#define BANK2_ADDR_BASE_SET(x) (((x) << BANK2_ADDR_BASE_LSB) & BANK2_ADDR_BASE_MASK)
++
++#define BANK2_CONFIG_ADDRESS 0x0c004024
++#define BANK2_CONFIG_OFFSET 0x00000024
++#define BANK2_CONFIG_ENABLE_MSB 31
++#define BANK2_CONFIG_ENABLE_LSB 31
++#define BANK2_CONFIG_ENABLE_MASK 0x80000000
++#define BANK2_CONFIG_ENABLE_GET(x) (((x) & BANK2_CONFIG_ENABLE_MASK) >> BANK2_CONFIG_ENABLE_LSB)
++#define BANK2_CONFIG_ENABLE_SET(x) (((x) << BANK2_CONFIG_ENABLE_LSB) & BANK2_CONFIG_ENABLE_MASK)
++#define BANK2_CONFIG_WIDTH_MSB 28
++#define BANK2_CONFIG_WIDTH_LSB 28
++#define BANK2_CONFIG_WIDTH_MASK 0x10000000
++#define BANK2_CONFIG_WIDTH_GET(x) (((x) & BANK2_CONFIG_WIDTH_MASK) >> BANK2_CONFIG_WIDTH_LSB)
++#define BANK2_CONFIG_WIDTH_SET(x) (((x) << BANK2_CONFIG_WIDTH_LSB) & BANK2_CONFIG_WIDTH_MASK)
++#define BANK2_CONFIG_PROTECT_MSB 26
++#define BANK2_CONFIG_PROTECT_LSB 26
++#define BANK2_CONFIG_PROTECT_MASK 0x04000000
++#define BANK2_CONFIG_PROTECT_GET(x) (((x) & BANK2_CONFIG_PROTECT_MASK) >> BANK2_CONFIG_PROTECT_LSB)
++#define BANK2_CONFIG_PROTECT_SET(x) (((x) << BANK2_CONFIG_PROTECT_LSB) & BANK2_CONFIG_PROTECT_MASK)
++#define BANK2_CONFIG_WB_ENABLE_MSB 25
++#define BANK2_CONFIG_WB_ENABLE_LSB 25
++#define BANK2_CONFIG_WB_ENABLE_MASK 0x02000000
++#define BANK2_CONFIG_WB_ENABLE_GET(x) (((x) & BANK2_CONFIG_WB_ENABLE_MASK) >> BANK2_CONFIG_WB_ENABLE_LSB)
++#define BANK2_CONFIG_WB_ENABLE_SET(x) (((x) << BANK2_CONFIG_WB_ENABLE_LSB) & BANK2_CONFIG_WB_ENABLE_MASK)
++#define BANK2_CONFIG_WB_FLUSH_MSB 24
++#define BANK2_CONFIG_WB_FLUSH_LSB 24
++#define BANK2_CONFIG_WB_FLUSH_MASK 0x01000000
++#define BANK2_CONFIG_WB_FLUSH_GET(x) (((x) & BANK2_CONFIG_WB_FLUSH_MASK) >> BANK2_CONFIG_WB_FLUSH_LSB)
++#define BANK2_CONFIG_WB_FLUSH_SET(x) (((x) << BANK2_CONFIG_WB_FLUSH_LSB) & BANK2_CONFIG_WB_FLUSH_MASK)
++#define BANK2_CONFIG_SCALE_MSB 21
++#define BANK2_CONFIG_SCALE_LSB 20
++#define BANK2_CONFIG_SCALE_MASK 0x00300000
++#define BANK2_CONFIG_SCALE_GET(x) (((x) & BANK2_CONFIG_SCALE_MASK) >> BANK2_CONFIG_SCALE_LSB)
++#define BANK2_CONFIG_SCALE_SET(x) (((x) << BANK2_CONFIG_SCALE_LSB) & BANK2_CONFIG_SCALE_MASK)
++#define BANK2_CONFIG_HOLDOFF_MSB 19
++#define BANK2_CONFIG_HOLDOFF_LSB 16
++#define BANK2_CONFIG_HOLDOFF_MASK 0x000f0000
++#define BANK2_CONFIG_HOLDOFF_GET(x) (((x) & BANK2_CONFIG_HOLDOFF_MASK) >> BANK2_CONFIG_HOLDOFF_LSB)
++#define BANK2_CONFIG_HOLDOFF_SET(x) (((x) << BANK2_CONFIG_HOLDOFF_LSB) & BANK2_CONFIG_HOLDOFF_MASK)
++#define BANK2_CONFIG_TIMER3_MSB 15
++#define BANK2_CONFIG_TIMER3_LSB 12
++#define BANK2_CONFIG_TIMER3_MASK 0x0000f000
++#define BANK2_CONFIG_TIMER3_GET(x) (((x) & BANK2_CONFIG_TIMER3_MASK) >> BANK2_CONFIG_TIMER3_LSB)
++#define BANK2_CONFIG_TIMER3_SET(x) (((x) << BANK2_CONFIG_TIMER3_LSB) & BANK2_CONFIG_TIMER3_MASK)
++#define BANK2_CONFIG_TIMER2_MSB 11
++#define BANK2_CONFIG_TIMER2_LSB 8
++#define BANK2_CONFIG_TIMER2_MASK 0x00000f00
++#define BANK2_CONFIG_TIMER2_GET(x) (((x) & BANK2_CONFIG_TIMER2_MASK) >> BANK2_CONFIG_TIMER2_LSB)
++#define BANK2_CONFIG_TIMER2_SET(x) (((x) << BANK2_CONFIG_TIMER2_LSB) & BANK2_CONFIG_TIMER2_MASK)
++#define BANK2_CONFIG_TIMER1_MSB 7
++#define BANK2_CONFIG_TIMER1_LSB 4
++#define BANK2_CONFIG_TIMER1_MASK 0x000000f0
++#define BANK2_CONFIG_TIMER1_GET(x) (((x) & BANK2_CONFIG_TIMER1_MASK) >> BANK2_CONFIG_TIMER1_LSB)
++#define BANK2_CONFIG_TIMER1_SET(x) (((x) << BANK2_CONFIG_TIMER1_LSB) & BANK2_CONFIG_TIMER1_MASK)
++#define BANK2_CONFIG_TIMER0_MSB 3
++#define BANK2_CONFIG_TIMER0_LSB 0
++#define BANK2_CONFIG_TIMER0_MASK 0x0000000f
++#define BANK2_CONFIG_TIMER0_GET(x) (((x) & BANK2_CONFIG_TIMER0_MASK) >> BANK2_CONFIG_TIMER0_LSB)
++#define BANK2_CONFIG_TIMER0_SET(x) (((x) << BANK2_CONFIG_TIMER0_LSB) & BANK2_CONFIG_TIMER0_MASK)
++
++#define BANK2_READ_ADDRESS 0x0c004028
++#define BANK2_READ_OFFSET 0x00000028
++#define BANK2_READ_ENABLE_WAIT_MSB 31
++#define BANK2_READ_ENABLE_WAIT_LSB 31
++#define BANK2_READ_ENABLE_WAIT_MASK 0x80000000
++#define BANK2_READ_ENABLE_WAIT_GET(x) (((x) & BANK2_READ_ENABLE_WAIT_MASK) >> BANK2_READ_ENABLE_WAIT_LSB)
++#define BANK2_READ_ENABLE_WAIT_SET(x) (((x) << BANK2_READ_ENABLE_WAIT_LSB) & BANK2_READ_ENABLE_WAIT_MASK)
++#define BANK2_READ_WAIT_EVENT_MSB 30
++#define BANK2_READ_WAIT_EVENT_LSB 28
++#define BANK2_READ_WAIT_EVENT_MASK 0x70000000
++#define BANK2_READ_WAIT_EVENT_GET(x) (((x) & BANK2_READ_WAIT_EVENT_MASK) >> BANK2_READ_WAIT_EVENT_LSB)
++#define BANK2_READ_WAIT_EVENT_SET(x) (((x) << BANK2_READ_WAIT_EVENT_LSB) & BANK2_READ_WAIT_EVENT_MASK)
++#define BANK2_READ_END_EVENT_MSB 26
++#define BANK2_READ_END_EVENT_LSB 24
++#define BANK2_READ_END_EVENT_MASK 0x07000000
++#define BANK2_READ_END_EVENT_GET(x) (((x) & BANK2_READ_END_EVENT_MASK) >> BANK2_READ_END_EVENT_LSB)
++#define BANK2_READ_END_EVENT_SET(x) (((x) << BANK2_READ_END_EVENT_LSB) & BANK2_READ_END_EVENT_MASK)
++#define BANK2_READ_BURST_END_EVENT_MSB 22
++#define BANK2_READ_BURST_END_EVENT_LSB 20
++#define BANK2_READ_BURST_END_EVENT_MASK 0x00700000
++#define BANK2_READ_BURST_END_EVENT_GET(x) (((x) & BANK2_READ_BURST_END_EVENT_MASK) >> BANK2_READ_BURST_END_EVENT_LSB)
++#define BANK2_READ_BURST_END_EVENT_SET(x) (((x) << BANK2_READ_BURST_END_EVENT_LSB) & BANK2_READ_BURST_END_EVENT_MASK)
++#define BANK2_READ_BURST_START_EVENT_MSB 18
++#define BANK2_READ_BURST_START_EVENT_LSB 16
++#define BANK2_READ_BURST_START_EVENT_MASK 0x00070000
++#define BANK2_READ_BURST_START_EVENT_GET(x) (((x) & BANK2_READ_BURST_START_EVENT_MASK) >> BANK2_READ_BURST_START_EVENT_LSB)
++#define BANK2_READ_BURST_START_EVENT_SET(x) (((x) << BANK2_READ_BURST_START_EVENT_LSB) & BANK2_READ_BURST_START_EVENT_MASK)
++#define BANK2_READ_EVENT3_DC_MSB 15
++#define BANK2_READ_EVENT3_DC_LSB 15
++#define BANK2_READ_EVENT3_DC_MASK 0x00008000
++#define BANK2_READ_EVENT3_DC_GET(x) (((x) & BANK2_READ_EVENT3_DC_MASK) >> BANK2_READ_EVENT3_DC_LSB)
++#define BANK2_READ_EVENT3_DC_SET(x) (((x) << BANK2_READ_EVENT3_DC_LSB) & BANK2_READ_EVENT3_DC_MASK)
++#define BANK2_READ_EVENT3_BE_MSB 14
++#define BANK2_READ_EVENT3_BE_LSB 14
++#define BANK2_READ_EVENT3_BE_MASK 0x00004000
++#define BANK2_READ_EVENT3_BE_GET(x) (((x) & BANK2_READ_EVENT3_BE_MASK) >> BANK2_READ_EVENT3_BE_LSB)
++#define BANK2_READ_EVENT3_BE_SET(x) (((x) << BANK2_READ_EVENT3_BE_LSB) & BANK2_READ_EVENT3_BE_MASK)
++#define BANK2_READ_EVENT3_OE_MSB 13
++#define BANK2_READ_EVENT3_OE_LSB 13
++#define BANK2_READ_EVENT3_OE_MASK 0x00002000
++#define BANK2_READ_EVENT3_OE_GET(x) (((x) & BANK2_READ_EVENT3_OE_MASK) >> BANK2_READ_EVENT3_OE_LSB)
++#define BANK2_READ_EVENT3_OE_SET(x) (((x) << BANK2_READ_EVENT3_OE_LSB) & BANK2_READ_EVENT3_OE_MASK)
++#define BANK2_READ_EVENT3_CS_MSB 12
++#define BANK2_READ_EVENT3_CS_LSB 12
++#define BANK2_READ_EVENT3_CS_MASK 0x00001000
++#define BANK2_READ_EVENT3_CS_GET(x) (((x) & BANK2_READ_EVENT3_CS_MASK) >> BANK2_READ_EVENT3_CS_LSB)
++#define BANK2_READ_EVENT3_CS_SET(x) (((x) << BANK2_READ_EVENT3_CS_LSB) & BANK2_READ_EVENT3_CS_MASK)
++#define BANK2_READ_EVENT2_DC_MSB 11
++#define BANK2_READ_EVENT2_DC_LSB 11
++#define BANK2_READ_EVENT2_DC_MASK 0x00000800
++#define BANK2_READ_EVENT2_DC_GET(x) (((x) & BANK2_READ_EVENT2_DC_MASK) >> BANK2_READ_EVENT2_DC_LSB)
++#define BANK2_READ_EVENT2_DC_SET(x) (((x) << BANK2_READ_EVENT2_DC_LSB) & BANK2_READ_EVENT2_DC_MASK)
++#define BANK2_READ_EVENT2_BE_MSB 10
++#define BANK2_READ_EVENT2_BE_LSB 10
++#define BANK2_READ_EVENT2_BE_MASK 0x00000400
++#define BANK2_READ_EVENT2_BE_GET(x) (((x) & BANK2_READ_EVENT2_BE_MASK) >> BANK2_READ_EVENT2_BE_LSB)
++#define BANK2_READ_EVENT2_BE_SET(x) (((x) << BANK2_READ_EVENT2_BE_LSB) & BANK2_READ_EVENT2_BE_MASK)
++#define BANK2_READ_EVENT2_OE_MSB 9
++#define BANK2_READ_EVENT2_OE_LSB 9
++#define BANK2_READ_EVENT2_OE_MASK 0x00000200
++#define BANK2_READ_EVENT2_OE_GET(x) (((x) & BANK2_READ_EVENT2_OE_MASK) >> BANK2_READ_EVENT2_OE_LSB)
++#define BANK2_READ_EVENT2_OE_SET(x) (((x) << BANK2_READ_EVENT2_OE_LSB) & BANK2_READ_EVENT2_OE_MASK)
++#define BANK2_READ_EVENT2_CS_MSB 8
++#define BANK2_READ_EVENT2_CS_LSB 8
++#define BANK2_READ_EVENT2_CS_MASK 0x00000100
++#define BANK2_READ_EVENT2_CS_GET(x) (((x) & BANK2_READ_EVENT2_CS_MASK) >> BANK2_READ_EVENT2_CS_LSB)
++#define BANK2_READ_EVENT2_CS_SET(x) (((x) << BANK2_READ_EVENT2_CS_LSB) & BANK2_READ_EVENT2_CS_MASK)
++#define BANK2_READ_EVENT1_DC_MSB 7
++#define BANK2_READ_EVENT1_DC_LSB 7
++#define BANK2_READ_EVENT1_DC_MASK 0x00000080
++#define BANK2_READ_EVENT1_DC_GET(x) (((x) & BANK2_READ_EVENT1_DC_MASK) >> BANK2_READ_EVENT1_DC_LSB)
++#define BANK2_READ_EVENT1_DC_SET(x) (((x) << BANK2_READ_EVENT1_DC_LSB) & BANK2_READ_EVENT1_DC_MASK)
++#define BANK2_READ_EVENT1_BE_MSB 6
++#define BANK2_READ_EVENT1_BE_LSB 6
++#define BANK2_READ_EVENT1_BE_MASK 0x00000040
++#define BANK2_READ_EVENT1_BE_GET(x) (((x) & BANK2_READ_EVENT1_BE_MASK) >> BANK2_READ_EVENT1_BE_LSB)
++#define BANK2_READ_EVENT1_BE_SET(x) (((x) << BANK2_READ_EVENT1_BE_LSB) & BANK2_READ_EVENT1_BE_MASK)
++#define BANK2_READ_EVENT1_OE_MSB 5
++#define BANK2_READ_EVENT1_OE_LSB 5
++#define BANK2_READ_EVENT1_OE_MASK 0x00000020
++#define BANK2_READ_EVENT1_OE_GET(x) (((x) & BANK2_READ_EVENT1_OE_MASK) >> BANK2_READ_EVENT1_OE_LSB)
++#define BANK2_READ_EVENT1_OE_SET(x) (((x) << BANK2_READ_EVENT1_OE_LSB) & BANK2_READ_EVENT1_OE_MASK)
++#define BANK2_READ_EVENT1_CS_MSB 4
++#define BANK2_READ_EVENT1_CS_LSB 4
++#define BANK2_READ_EVENT1_CS_MASK 0x00000010
++#define BANK2_READ_EVENT1_CS_GET(x) (((x) & BANK2_READ_EVENT1_CS_MASK) >> BANK2_READ_EVENT1_CS_LSB)
++#define BANK2_READ_EVENT1_CS_SET(x) (((x) << BANK2_READ_EVENT1_CS_LSB) & BANK2_READ_EVENT1_CS_MASK)
++#define BANK2_READ_EVENT0_DC_MSB 3
++#define BANK2_READ_EVENT0_DC_LSB 3
++#define BANK2_READ_EVENT0_DC_MASK 0x00000008
++#define BANK2_READ_EVENT0_DC_GET(x) (((x) & BANK2_READ_EVENT0_DC_MASK) >> BANK2_READ_EVENT0_DC_LSB)
++#define BANK2_READ_EVENT0_DC_SET(x) (((x) << BANK2_READ_EVENT0_DC_LSB) & BANK2_READ_EVENT0_DC_MASK)
++#define BANK2_READ_EVENT0_BE_MSB 2
++#define BANK2_READ_EVENT0_BE_LSB 2
++#define BANK2_READ_EVENT0_BE_MASK 0x00000004
++#define BANK2_READ_EVENT0_BE_GET(x) (((x) & BANK2_READ_EVENT0_BE_MASK) >> BANK2_READ_EVENT0_BE_LSB)
++#define BANK2_READ_EVENT0_BE_SET(x) (((x) << BANK2_READ_EVENT0_BE_LSB) & BANK2_READ_EVENT0_BE_MASK)
++#define BANK2_READ_EVENT0_OE_MSB 1
++#define BANK2_READ_EVENT0_OE_LSB 1
++#define BANK2_READ_EVENT0_OE_MASK 0x00000002
++#define BANK2_READ_EVENT0_OE_GET(x) (((x) & BANK2_READ_EVENT0_OE_MASK) >> BANK2_READ_EVENT0_OE_LSB)
++#define BANK2_READ_EVENT0_OE_SET(x) (((x) << BANK2_READ_EVENT0_OE_LSB) & BANK2_READ_EVENT0_OE_MASK)
++#define BANK2_READ_EVENT0_CS_MSB 0
++#define BANK2_READ_EVENT0_CS_LSB 0
++#define BANK2_READ_EVENT0_CS_MASK 0x00000001
++#define BANK2_READ_EVENT0_CS_GET(x) (((x) & BANK2_READ_EVENT0_CS_MASK) >> BANK2_READ_EVENT0_CS_LSB)
++#define BANK2_READ_EVENT0_CS_SET(x) (((x) << BANK2_READ_EVENT0_CS_LSB) & BANK2_READ_EVENT0_CS_MASK)
++
++#define BANK2_WRITE_ADDRESS 0x0c00402c
++#define BANK2_WRITE_OFFSET 0x0000002c
++#define BANK2_WRITE_ENABLE_WAIT_MSB 31
++#define BANK2_WRITE_ENABLE_WAIT_LSB 31
++#define BANK2_WRITE_ENABLE_WAIT_MASK 0x80000000
++#define BANK2_WRITE_ENABLE_WAIT_GET(x) (((x) & BANK2_WRITE_ENABLE_WAIT_MASK) >> BANK2_WRITE_ENABLE_WAIT_LSB)
++#define BANK2_WRITE_ENABLE_WAIT_SET(x) (((x) << BANK2_WRITE_ENABLE_WAIT_LSB) & BANK2_WRITE_ENABLE_WAIT_MASK)
++#define BANK2_WRITE_WAIT_EVENT_MSB 30
++#define BANK2_WRITE_WAIT_EVENT_LSB 28
++#define BANK2_WRITE_WAIT_EVENT_MASK 0x70000000
++#define BANK2_WRITE_WAIT_EVENT_GET(x) (((x) & BANK2_WRITE_WAIT_EVENT_MASK) >> BANK2_WRITE_WAIT_EVENT_LSB)
++#define BANK2_WRITE_WAIT_EVENT_SET(x) (((x) << BANK2_WRITE_WAIT_EVENT_LSB) & BANK2_WRITE_WAIT_EVENT_MASK)
++#define BANK2_WRITE_END_EVENT_MSB 26
++#define BANK2_WRITE_END_EVENT_LSB 24
++#define BANK2_WRITE_END_EVENT_MASK 0x07000000
++#define BANK2_WRITE_END_EVENT_GET(x) (((x) & BANK2_WRITE_END_EVENT_MASK) >> BANK2_WRITE_END_EVENT_LSB)
++#define BANK2_WRITE_END_EVENT_SET(x) (((x) << BANK2_WRITE_END_EVENT_LSB) & BANK2_WRITE_END_EVENT_MASK)
++#define BANK2_WRITE_BURST_END_EVENT_MSB 22
++#define BANK2_WRITE_BURST_END_EVENT_LSB 20
++#define BANK2_WRITE_BURST_END_EVENT_MASK 0x00700000
++#define BANK2_WRITE_BURST_END_EVENT_GET(x) (((x) & BANK2_WRITE_BURST_END_EVENT_MASK) >> BANK2_WRITE_BURST_END_EVENT_LSB)
++#define BANK2_WRITE_BURST_END_EVENT_SET(x) (((x) << BANK2_WRITE_BURST_END_EVENT_LSB) & BANK2_WRITE_BURST_END_EVENT_MASK)
++#define BANK2_WRITE_BURST_START_EVENT_MSB 18
++#define BANK2_WRITE_BURST_START_EVENT_LSB 16
++#define BANK2_WRITE_BURST_START_EVENT_MASK 0x00070000
++#define BANK2_WRITE_BURST_START_EVENT_GET(x) (((x) & BANK2_WRITE_BURST_START_EVENT_MASK) >> BANK2_WRITE_BURST_START_EVENT_LSB)
++#define BANK2_WRITE_BURST_START_EVENT_SET(x) (((x) << BANK2_WRITE_BURST_START_EVENT_LSB) & BANK2_WRITE_BURST_START_EVENT_MASK)
++#define BANK2_WRITE_EVENT3_BE_MSB 14
++#define BANK2_WRITE_EVENT3_BE_LSB 14
++#define BANK2_WRITE_EVENT3_BE_MASK 0x00004000
++#define BANK2_WRITE_EVENT3_BE_GET(x) (((x) & BANK2_WRITE_EVENT3_BE_MASK) >> BANK2_WRITE_EVENT3_BE_LSB)
++#define BANK2_WRITE_EVENT3_BE_SET(x) (((x) << BANK2_WRITE_EVENT3_BE_LSB) & BANK2_WRITE_EVENT3_BE_MASK)
++#define BANK2_WRITE_EVENT3_WE_MSB 13
++#define BANK2_WRITE_EVENT3_WE_LSB 13
++#define BANK2_WRITE_EVENT3_WE_MASK 0x00002000
++#define BANK2_WRITE_EVENT3_WE_GET(x) (((x) & BANK2_WRITE_EVENT3_WE_MASK) >> BANK2_WRITE_EVENT3_WE_LSB)
++#define BANK2_WRITE_EVENT3_WE_SET(x) (((x) << BANK2_WRITE_EVENT3_WE_LSB) & BANK2_WRITE_EVENT3_WE_MASK)
++#define BANK2_WRITE_EVENT3_CS_MSB 12
++#define BANK2_WRITE_EVENT3_CS_LSB 12
++#define BANK2_WRITE_EVENT3_CS_MASK 0x00001000
++#define BANK2_WRITE_EVENT3_CS_GET(x) (((x) & BANK2_WRITE_EVENT3_CS_MASK) >> BANK2_WRITE_EVENT3_CS_LSB)
++#define BANK2_WRITE_EVENT3_CS_SET(x) (((x) << BANK2_WRITE_EVENT3_CS_LSB) & BANK2_WRITE_EVENT3_CS_MASK)
++#define BANK2_WRITE_EVENT2_BE_MSB 10
++#define BANK2_WRITE_EVENT2_BE_LSB 10
++#define BANK2_WRITE_EVENT2_BE_MASK 0x00000400
++#define BANK2_WRITE_EVENT2_BE_GET(x) (((x) & BANK2_WRITE_EVENT2_BE_MASK) >> BANK2_WRITE_EVENT2_BE_LSB)
++#define BANK2_WRITE_EVENT2_BE_SET(x) (((x) << BANK2_WRITE_EVENT2_BE_LSB) & BANK2_WRITE_EVENT2_BE_MASK)
++#define BANK2_WRITE_EVENT2_WE_MSB 9
++#define BANK2_WRITE_EVENT2_WE_LSB 9
++#define BANK2_WRITE_EVENT2_WE_MASK 0x00000200
++#define BANK2_WRITE_EVENT2_WE_GET(x) (((x) & BANK2_WRITE_EVENT2_WE_MASK) >> BANK2_WRITE_EVENT2_WE_LSB)
++#define BANK2_WRITE_EVENT2_WE_SET(x) (((x) << BANK2_WRITE_EVENT2_WE_LSB) & BANK2_WRITE_EVENT2_WE_MASK)
++#define BANK2_WRITE_EVENT2_CS_MSB 8
++#define BANK2_WRITE_EVENT2_CS_LSB 8
++#define BANK2_WRITE_EVENT2_CS_MASK 0x00000100
++#define BANK2_WRITE_EVENT2_CS_GET(x) (((x) & BANK2_WRITE_EVENT2_CS_MASK) >> BANK2_WRITE_EVENT2_CS_LSB)
++#define BANK2_WRITE_EVENT2_CS_SET(x) (((x) << BANK2_WRITE_EVENT2_CS_LSB) & BANK2_WRITE_EVENT2_CS_MASK)
++#define BANK2_WRITE_EVENT1_BE_MSB 6
++#define BANK2_WRITE_EVENT1_BE_LSB 6
++#define BANK2_WRITE_EVENT1_BE_MASK 0x00000040
++#define BANK2_WRITE_EVENT1_BE_GET(x) (((x) & BANK2_WRITE_EVENT1_BE_MASK) >> BANK2_WRITE_EVENT1_BE_LSB)
++#define BANK2_WRITE_EVENT1_BE_SET(x) (((x) << BANK2_WRITE_EVENT1_BE_LSB) & BANK2_WRITE_EVENT1_BE_MASK)
++#define BANK2_WRITE_EVENT1_WE_MSB 5
++#define BANK2_WRITE_EVENT1_WE_LSB 5
++#define BANK2_WRITE_EVENT1_WE_MASK 0x00000020
++#define BANK2_WRITE_EVENT1_WE_GET(x) (((x) & BANK2_WRITE_EVENT1_WE_MASK) >> BANK2_WRITE_EVENT1_WE_LSB)
++#define BANK2_WRITE_EVENT1_WE_SET(x) (((x) << BANK2_WRITE_EVENT1_WE_LSB) & BANK2_WRITE_EVENT1_WE_MASK)
++#define BANK2_WRITE_EVENT1_CS_MSB 4
++#define BANK2_WRITE_EVENT1_CS_LSB 4
++#define BANK2_WRITE_EVENT1_CS_MASK 0x00000010
++#define BANK2_WRITE_EVENT1_CS_GET(x) (((x) & BANK2_WRITE_EVENT1_CS_MASK) >> BANK2_WRITE_EVENT1_CS_LSB)
++#define BANK2_WRITE_EVENT1_CS_SET(x) (((x) << BANK2_WRITE_EVENT1_CS_LSB) & BANK2_WRITE_EVENT1_CS_MASK)
++#define BANK2_WRITE_EVENT0_BE_MSB 2
++#define BANK2_WRITE_EVENT0_BE_LSB 2
++#define BANK2_WRITE_EVENT0_BE_MASK 0x00000004
++#define BANK2_WRITE_EVENT0_BE_GET(x) (((x) & BANK2_WRITE_EVENT0_BE_MASK) >> BANK2_WRITE_EVENT0_BE_LSB)
++#define BANK2_WRITE_EVENT0_BE_SET(x) (((x) << BANK2_WRITE_EVENT0_BE_LSB) & BANK2_WRITE_EVENT0_BE_MASK)
++#define BANK2_WRITE_EVENT0_WE_MSB 1
++#define BANK2_WRITE_EVENT0_WE_LSB 1
++#define BANK2_WRITE_EVENT0_WE_MASK 0x00000002
++#define BANK2_WRITE_EVENT0_WE_GET(x) (((x) & BANK2_WRITE_EVENT0_WE_MASK) >> BANK2_WRITE_EVENT0_WE_LSB)
++#define BANK2_WRITE_EVENT0_WE_SET(x) (((x) << BANK2_WRITE_EVENT0_WE_LSB) & BANK2_WRITE_EVENT0_WE_MASK)
++#define BANK2_WRITE_EVENT0_CS_MSB 0
++#define BANK2_WRITE_EVENT0_CS_LSB 0
++#define BANK2_WRITE_EVENT0_CS_MASK 0x00000001
++#define BANK2_WRITE_EVENT0_CS_GET(x) (((x) & BANK2_WRITE_EVENT0_CS_MASK) >> BANK2_WRITE_EVENT0_CS_LSB)
++#define BANK2_WRITE_EVENT0_CS_SET(x) (((x) << BANK2_WRITE_EVENT0_CS_LSB) & BANK2_WRITE_EVENT0_CS_MASK)
++
++#define MC_REMAP_VALID_ADDRESS 0x0c004080
++#define MC_REMAP_VALID_OFFSET 0x00000080
++#define MC_REMAP_VALID_BIT_MSB 0
++#define MC_REMAP_VALID_BIT_LSB 0
++#define MC_REMAP_VALID_BIT_MASK 0x00000001
++#define MC_REMAP_VALID_BIT_GET(x) (((x) & MC_REMAP_VALID_BIT_MASK) >> MC_REMAP_VALID_BIT_LSB)
++#define MC_REMAP_VALID_BIT_SET(x) (((x) << MC_REMAP_VALID_BIT_LSB) & MC_REMAP_VALID_BIT_MASK)
++
++#define MC_REMAP_SIZE_ADDRESS 0x0c004100
++#define MC_REMAP_SIZE_OFFSET 0x00000100
++#define MC_REMAP_SIZE_VALUE_MSB 2
++#define MC_REMAP_SIZE_VALUE_LSB 0
++#define MC_REMAP_SIZE_VALUE_MASK 0x00000007
++#define MC_REMAP_SIZE_VALUE_GET(x) (((x) & MC_REMAP_SIZE_VALUE_MASK) >> MC_REMAP_SIZE_VALUE_LSB)
++#define MC_REMAP_SIZE_VALUE_SET(x) (((x) << MC_REMAP_SIZE_VALUE_LSB) & MC_REMAP_SIZE_VALUE_MASK)
++
++#define MC_REMAP_COMPARE_ADDRESS 0x0c004180
++#define MC_REMAP_COMPARE_OFFSET 0x00000180
++#define MC_REMAP_COMPARE_ADDRESS_MSB 17
++#define MC_REMAP_COMPARE_ADDRESS_LSB 4
++#define MC_REMAP_COMPARE_ADDRESS_MASK 0x0003fff0
++#define MC_REMAP_COMPARE_ADDRESS_GET(x) (((x) & MC_REMAP_COMPARE_ADDRESS_MASK) >> MC_REMAP_COMPARE_ADDRESS_LSB)
++#define MC_REMAP_COMPARE_ADDRESS_SET(x) (((x) << MC_REMAP_COMPARE_ADDRESS_LSB) & MC_REMAP_COMPARE_ADDRESS_MASK)
++
++#define MC_REMAP_TARGET_ADDRESS 0x0c004200
++#define MC_REMAP_TARGET_OFFSET 0x00000200
++#define MC_REMAP_TARGET_ADDRESS_MSB 16
++#define MC_REMAP_TARGET_ADDRESS_LSB 4
++#define MC_REMAP_TARGET_ADDRESS_MASK 0x0001fff0
++#define MC_REMAP_TARGET_ADDRESS_GET(x) (((x) & MC_REMAP_TARGET_ADDRESS_MASK) >> MC_REMAP_TARGET_ADDRESS_LSB)
++#define MC_REMAP_TARGET_ADDRESS_SET(x) (((x) << MC_REMAP_TARGET_ADDRESS_LSB) & MC_REMAP_TARGET_ADDRESS_MASK)
++
++#define G729_ROM_ADDRESS 0x0c004280
++#define G729_ROM_OFFSET 0x00000280
++#define G729_ROM_ENABLE_MSB 0
++#define G729_ROM_ENABLE_LSB 0
++#define G729_ROM_ENABLE_MASK 0x00000001
++#define G729_ROM_ENABLE_GET(x) (((x) & G729_ROM_ENABLE_MASK) >> G729_ROM_ENABLE_LSB)
++#define G729_ROM_ENABLE_SET(x) (((x) << G729_ROM_ENABLE_LSB) & G729_ROM_ENABLE_MASK)
++
++#define ERROR_VALID_ADDRESS 0x0c004284
++#define ERROR_VALID_OFFSET 0x00000284
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MSB 8
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB 8
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK 0x00000100
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_GET(x) (((x) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK) >> ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB)
++#define ERROR_VALID_ERROR_CAPTURE_ENABLE_SET(x) (((x) << ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK)
++#define ERROR_VALID_APB_ERROR_OVERFLOW_MSB 5
++#define ERROR_VALID_APB_ERROR_OVERFLOW_LSB 5
++#define ERROR_VALID_APB_ERROR_OVERFLOW_MASK 0x00000020
++#define ERROR_VALID_APB_ERROR_OVERFLOW_GET(x) (((x) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK) >> ERROR_VALID_APB_ERROR_OVERFLOW_LSB)
++#define ERROR_VALID_APB_ERROR_OVERFLOW_SET(x) (((x) << ERROR_VALID_APB_ERROR_OVERFLOW_LSB) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK)
++#define ERROR_VALID_APB_ERROR_VALID_MSB 4
++#define ERROR_VALID_APB_ERROR_VALID_LSB 4
++#define ERROR_VALID_APB_ERROR_VALID_MASK 0x00000010
++#define ERROR_VALID_APB_ERROR_VALID_GET(x) (((x) & ERROR_VALID_APB_ERROR_VALID_MASK) >> ERROR_VALID_APB_ERROR_VALID_LSB)
++#define ERROR_VALID_APB_ERROR_VALID_SET(x) (((x) << ERROR_VALID_APB_ERROR_VALID_LSB) & ERROR_VALID_APB_ERROR_VALID_MASK)
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_MSB 1
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_LSB 1
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_MASK 0x00000002
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_GET(x) (((x) & ERROR_VALID_AHB_ERROR_OVERFLOW_MASK) >> ERROR_VALID_AHB_ERROR_OVERFLOW_LSB)
++#define ERROR_VALID_AHB_ERROR_OVERFLOW_SET(x) (((x) << ERROR_VALID_AHB_ERROR_OVERFLOW_LSB) & ERROR_VALID_AHB_ERROR_OVERFLOW_MASK)
++#define ERROR_VALID_AHB_ERROR_VALID_MSB 0
++#define ERROR_VALID_AHB_ERROR_VALID_LSB 0
++#define ERROR_VALID_AHB_ERROR_VALID_MASK 0x00000001
++#define ERROR_VALID_AHB_ERROR_VALID_GET(x) (((x) & ERROR_VALID_AHB_ERROR_VALID_MASK) >> ERROR_VALID_AHB_ERROR_VALID_LSB)
++#define ERROR_VALID_AHB_ERROR_VALID_SET(x) (((x) << ERROR_VALID_AHB_ERROR_VALID_LSB) & ERROR_VALID_AHB_ERROR_VALID_MASK)
++
++#define AHB_ERROR_ADDRESS 0x0c004288
++#define AHB_ERROR_OFFSET 0x00000288
++#define AHB_ERROR_HMASTER_MSB 31
++#define AHB_ERROR_HMASTER_LSB 30
++#define AHB_ERROR_HMASTER_MASK 0xc0000000
++#define AHB_ERROR_HMASTER_GET(x) (((x) & AHB_ERROR_HMASTER_MASK) >> AHB_ERROR_HMASTER_LSB)
++#define AHB_ERROR_HMASTER_SET(x) (((x) << AHB_ERROR_HMASTER_LSB) & AHB_ERROR_HMASTER_MASK)
++#define AHB_ERROR_HTRANS_MSB 29
++#define AHB_ERROR_HTRANS_LSB 28
++#define AHB_ERROR_HTRANS_MASK 0x30000000
++#define AHB_ERROR_HTRANS_GET(x) (((x) & AHB_ERROR_HTRANS_MASK) >> AHB_ERROR_HTRANS_LSB)
++#define AHB_ERROR_HTRANS_SET(x) (((x) << AHB_ERROR_HTRANS_LSB) & AHB_ERROR_HTRANS_MASK)
++#define AHB_ERROR_HWRITE_MSB 27
++#define AHB_ERROR_HWRITE_LSB 27
++#define AHB_ERROR_HWRITE_MASK 0x08000000
++#define AHB_ERROR_HWRITE_GET(x) (((x) & AHB_ERROR_HWRITE_MASK) >> AHB_ERROR_HWRITE_LSB)
++#define AHB_ERROR_HWRITE_SET(x) (((x) << AHB_ERROR_HWRITE_LSB) & AHB_ERROR_HWRITE_MASK)
++#define AHB_ERROR_HBURST_MSB 26
++#define AHB_ERROR_HBURST_LSB 24
++#define AHB_ERROR_HBURST_MASK 0x07000000
++#define AHB_ERROR_HBURST_GET(x) (((x) & AHB_ERROR_HBURST_MASK) >> AHB_ERROR_HBURST_LSB)
++#define AHB_ERROR_HBURST_SET(x) (((x) << AHB_ERROR_HBURST_LSB) & AHB_ERROR_HBURST_MASK)
++#define AHB_ERROR_HADDR_MSB 23
++#define AHB_ERROR_HADDR_LSB 0
++#define AHB_ERROR_HADDR_MASK 0x00ffffff
++#define AHB_ERROR_HADDR_GET(x) (((x) & AHB_ERROR_HADDR_MASK) >> AHB_ERROR_HADDR_LSB)
++#define AHB_ERROR_HADDR_SET(x) (((x) << AHB_ERROR_HADDR_LSB) & AHB_ERROR_HADDR_MASK)
++
++#define APB_ERROR_ADDRESS 0x0c00428c
++#define APB_ERROR_OFFSET 0x0000028c
++#define APB_ERROR_PADDR_MSB 31
++#define APB_ERROR_PADDR_LSB 2
++#define APB_ERROR_PADDR_MASK 0xfffffffc
++#define APB_ERROR_PADDR_GET(x) (((x) & APB_ERROR_PADDR_MASK) >> APB_ERROR_PADDR_LSB)
++#define APB_ERROR_PADDR_SET(x) (((x) << APB_ERROR_PADDR_LSB) & APB_ERROR_PADDR_MASK)
++#define APB_ERROR_PVALID_MSB 1
++#define APB_ERROR_PVALID_LSB 1
++#define APB_ERROR_PVALID_MASK 0x00000002
++#define APB_ERROR_PVALID_GET(x) (((x) & APB_ERROR_PVALID_MASK) >> APB_ERROR_PVALID_LSB)
++#define APB_ERROR_PVALID_SET(x) (((x) << APB_ERROR_PVALID_LSB) & APB_ERROR_PVALID_MASK)
++#define APB_ERROR_PWRITE_MSB 0
++#define APB_ERROR_PWRITE_LSB 0
++#define APB_ERROR_PWRITE_MASK 0x00000001
++#define APB_ERROR_PWRITE_GET(x) (((x) & APB_ERROR_PWRITE_MASK) >> APB_ERROR_PWRITE_LSB)
++#define APB_ERROR_PWRITE_SET(x) (((x) << APB_ERROR_PWRITE_LSB) & APB_ERROR_PWRITE_MASK)
++
++#define PERF_CONFIG_ADDRESS 0x0c004290
++#define PERF_CONFIG_OFFSET 0x00000290
++#define PERF_CONFIG_ENABLE_MSB 20
++#define PERF_CONFIG_ENABLE_LSB 20
++#define PERF_CONFIG_ENABLE_MASK 0x00100000
++#define PERF_CONFIG_ENABLE_GET(x) (((x) & PERF_CONFIG_ENABLE_MASK) >> PERF_CONFIG_ENABLE_LSB)
++#define PERF_CONFIG_ENABLE_SET(x) (((x) << PERF_CONFIG_ENABLE_LSB) & PERF_CONFIG_ENABLE_MASK)
++#define PERF_CONFIG_RESET_MSB 19
++#define PERF_CONFIG_RESET_LSB 16
++#define PERF_CONFIG_RESET_MASK 0x000f0000
++#define PERF_CONFIG_RESET_GET(x) (((x) & PERF_CONFIG_RESET_MASK) >> PERF_CONFIG_RESET_LSB)
++#define PERF_CONFIG_RESET_SET(x) (((x) << PERF_CONFIG_RESET_LSB) & PERF_CONFIG_RESET_MASK)
++#define PERF_CONFIG_COUNTER3_MSB 15
++#define PERF_CONFIG_COUNTER3_LSB 12
++#define PERF_CONFIG_COUNTER3_MASK 0x0000f000
++#define PERF_CONFIG_COUNTER3_GET(x) (((x) & PERF_CONFIG_COUNTER3_MASK) >> PERF_CONFIG_COUNTER3_LSB)
++#define PERF_CONFIG_COUNTER3_SET(x) (((x) << PERF_CONFIG_COUNTER3_LSB) & PERF_CONFIG_COUNTER3_MASK)
++#define PERF_CONFIG_COUNTER2_MSB 11
++#define PERF_CONFIG_COUNTER2_LSB 8
++#define PERF_CONFIG_COUNTER2_MASK 0x00000f00
++#define PERF_CONFIG_COUNTER2_GET(x) (((x) & PERF_CONFIG_COUNTER2_MASK) >> PERF_CONFIG_COUNTER2_LSB)
++#define PERF_CONFIG_COUNTER2_SET(x) (((x) << PERF_CONFIG_COUNTER2_LSB) & PERF_CONFIG_COUNTER2_MASK)
++#define PERF_CONFIG_COUNTER1_MSB 7
++#define PERF_CONFIG_COUNTER1_LSB 4
++#define PERF_CONFIG_COUNTER1_MASK 0x000000f0
++#define PERF_CONFIG_COUNTER1_GET(x) (((x) & PERF_CONFIG_COUNTER1_MASK) >> PERF_CONFIG_COUNTER1_LSB)
++#define PERF_CONFIG_COUNTER1_SET(x) (((x) << PERF_CONFIG_COUNTER1_LSB) & PERF_CONFIG_COUNTER1_MASK)
++#define PERF_CONFIG_COUNTER0_MSB 3
++#define PERF_CONFIG_COUNTER0_LSB 0
++#define PERF_CONFIG_COUNTER0_MASK 0x0000000f
++#define PERF_CONFIG_COUNTER0_GET(x) (((x) & PERF_CONFIG_COUNTER0_MASK) >> PERF_CONFIG_COUNTER0_LSB)
++#define PERF_CONFIG_COUNTER0_SET(x) (((x) << PERF_CONFIG_COUNTER0_LSB) & PERF_CONFIG_COUNTER0_MASK)
++
++#define PERF_COUNTER_ADDRESS 0x0c0042a0
++#define PERF_COUNTER_OFFSET 0x000002a0
++#define PERF_COUNTER_VALUE_MSB 19
++#define PERF_COUNTER_VALUE_LSB 0
++#define PERF_COUNTER_VALUE_MASK 0x000fffff
++#define PERF_COUNTER_VALUE_GET(x) (((x) & PERF_COUNTER_VALUE_MASK) >> PERF_COUNTER_VALUE_LSB)
++#define PERF_COUNTER_VALUE_SET(x) (((x) << PERF_COUNTER_VALUE_LSB) & PERF_COUNTER_VALUE_MASK)
++
++#define CPU_SETUP_CONFIG_ADDRESS 0x0c0042b0
++#define CPU_SETUP_CONFIG_OFFSET 0x000002b0
++#define CPU_SETUP_CONFIG_ENABLE_MSB 1
++#define CPU_SETUP_CONFIG_ENABLE_LSB 1
++#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002
++#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
++#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
++#define CPU_SETUP_CONFIG_CLEAR_MSB 0
++#define CPU_SETUP_CONFIG_CLEAR_LSB 0
++#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001
++#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
++#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
++
++#define MC_SETUP_CONFIG_ADDRESS 0x0c0042b4
++#define MC_SETUP_CONFIG_OFFSET 0x000002b4
++#define MC_SETUP_CONFIG_ENABLE_MSB 1
++#define MC_SETUP_CONFIG_ENABLE_LSB 1
++#define MC_SETUP_CONFIG_ENABLE_MASK 0x00000002
++#define MC_SETUP_CONFIG_ENABLE_GET(x) (((x) & MC_SETUP_CONFIG_ENABLE_MASK) >> MC_SETUP_CONFIG_ENABLE_LSB)
++#define MC_SETUP_CONFIG_ENABLE_SET(x) (((x) << MC_SETUP_CONFIG_ENABLE_LSB) & MC_SETUP_CONFIG_ENABLE_MASK)
++#define MC_SETUP_CONFIG_CLEAR_MSB 0
++#define MC_SETUP_CONFIG_CLEAR_LSB 0
++#define MC_SETUP_CONFIG_CLEAR_MASK 0x00000001
++#define MC_SETUP_CONFIG_CLEAR_GET(x) (((x) & MC_SETUP_CONFIG_CLEAR_MASK) >> MC_SETUP_CONFIG_CLEAR_LSB)
++#define MC_SETUP_CONFIG_CLEAR_SET(x) (((x) << MC_SETUP_CONFIG_CLEAR_LSB) & MC_SETUP_CONFIG_CLEAR_MASK)
++
++#define BB_SETUP_CONFIG_ADDRESS 0x0c0042b8
++#define BB_SETUP_CONFIG_OFFSET 0x000002b8
++#define BB_SETUP_CONFIG_ENABLE_MSB 1
++#define BB_SETUP_CONFIG_ENABLE_LSB 1
++#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002
++#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
++#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
++#define BB_SETUP_CONFIG_CLEAR_MSB 0
++#define BB_SETUP_CONFIG_CLEAR_LSB 0
++#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001
++#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
++#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
++
++#define SDIO_SETUP_CONFIG_ADDRESS 0x0c0042bc
++#define SDIO_SETUP_CONFIG_OFFSET 0x000002bc
++#define SDIO_SETUP_CONFIG_ENABLE_MSB 1
++#define SDIO_SETUP_CONFIG_ENABLE_LSB 1
++#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002
++#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
++#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
++#define SDIO_SETUP_CONFIG_CLEAR_MSB 0
++#define SDIO_SETUP_CONFIG_CLEAR_LSB 0
++#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001
++#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
++#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
++
++#define CPU_SETUP_CIRCUIT_ADDRESS 0x0c0042c0
++#define CPU_SETUP_CIRCUIT_OFFSET 0x000002c0
++#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7
++#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0
++#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
++#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
++#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define MC_SETUP_CIRCUIT_ADDRESS 0x0c0042e0
++#define MC_SETUP_CIRCUIT_OFFSET 0x000002e0
++#define MC_SETUP_CIRCUIT_VECTOR_MSB 7
++#define MC_SETUP_CIRCUIT_VECTOR_LSB 0
++#define MC_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
++#define MC_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & MC_SETUP_CIRCUIT_VECTOR_MASK) >> MC_SETUP_CIRCUIT_VECTOR_LSB)
++#define MC_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << MC_SETUP_CIRCUIT_VECTOR_LSB) & MC_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define BB_SETUP_CIRCUIT_ADDRESS 0x0c004300
++#define BB_SETUP_CIRCUIT_OFFSET 0x00000300
++#define BB_SETUP_CIRCUIT_VECTOR_MSB 7
++#define BB_SETUP_CIRCUIT_VECTOR_LSB 0
++#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
++#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
++#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define SDIO_SETUP_CIRCUIT_ADDRESS 0x0c004320
++#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000320
++#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7
++#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0
++#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
++#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
++#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
++
++#define TIMING_SUMMARY_ADDRESS 0x0c004340
++#define TIMING_SUMMARY_OFFSET 0x00000340
++#define TIMING_SUMMARY_VECTOR_MSB 7
++#define TIMING_SUMMARY_VECTOR_LSB 0
++#define TIMING_SUMMARY_VECTOR_MASK 0x000000ff
++#define TIMING_SUMMARY_VECTOR_GET(x) (((x) & TIMING_SUMMARY_VECTOR_MASK) >> TIMING_SUMMARY_VECTOR_LSB)
++#define TIMING_SUMMARY_VECTOR_SET(x) (((x) << TIMING_SUMMARY_VECTOR_LSB) & TIMING_SUMMARY_VECTOR_MASK)
++
++#define TIMING_INT_ENABLE_ADDRESS 0x0c004344
++#define TIMING_INT_ENABLE_OFFSET 0x00000344
++#define TIMING_INT_ENABLE_VECTOR_MSB 7
++#define TIMING_INT_ENABLE_VECTOR_LSB 0
++#define TIMING_INT_ENABLE_VECTOR_MASK 0x000000ff
++#define TIMING_INT_ENABLE_VECTOR_GET(x) (((x) & TIMING_INT_ENABLE_VECTOR_MASK) >> TIMING_INT_ENABLE_VECTOR_LSB)
++#define TIMING_INT_ENABLE_VECTOR_SET(x) (((x) << TIMING_INT_ENABLE_VECTOR_LSB) & TIMING_INT_ENABLE_VECTOR_MASK)
++
++#define MC_ERROR_STATUS_ADDRESS 0x0c004348
++#define MC_ERROR_STATUS_OFFSET 0x00000348
++#define MC_ERROR_STATUS_AHB_MSB 1
++#define MC_ERROR_STATUS_AHB_LSB 1
++#define MC_ERROR_STATUS_AHB_MASK 0x00000002
++#define MC_ERROR_STATUS_AHB_GET(x) (((x) & MC_ERROR_STATUS_AHB_MASK) >> MC_ERROR_STATUS_AHB_LSB)
++#define MC_ERROR_STATUS_AHB_SET(x) (((x) << MC_ERROR_STATUS_AHB_LSB) & MC_ERROR_STATUS_AHB_MASK)
++#define MC_ERROR_STATUS_TIMING_MSB 0
++#define MC_ERROR_STATUS_TIMING_LSB 0
++#define MC_ERROR_STATUS_TIMING_MASK 0x00000001
++#define MC_ERROR_STATUS_TIMING_GET(x) (((x) & MC_ERROR_STATUS_TIMING_MASK) >> MC_ERROR_STATUS_TIMING_LSB)
++#define MC_ERROR_STATUS_TIMING_SET(x) (((x) << MC_ERROR_STATUS_TIMING_LSB) & MC_ERROR_STATUS_TIMING_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mc_reg_s {
++ volatile unsigned int bank0_addr;
++ volatile unsigned int bank0_config;
++ volatile unsigned int bank0_read;
++ volatile unsigned int bank0_write;
++ volatile unsigned int bank1_addr;
++ volatile unsigned int bank1_config;
++ volatile unsigned int bank1_read;
++ volatile unsigned int bank1_write;
++ volatile unsigned int bank2_addr;
++ volatile unsigned int bank2_config;
++ volatile unsigned int bank2_read;
++ volatile unsigned int bank2_write;
++ unsigned char pad0[80]; /* pad to 0x80 */
++ volatile unsigned int mc_remap_valid[32];
++ volatile unsigned int mc_remap_size[32];
++ volatile unsigned int mc_remap_compare[32];
++ volatile unsigned int mc_remap_target[32];
++ volatile unsigned int g729_rom;
++ volatile unsigned int error_valid;
++ volatile unsigned int ahb_error;
++ volatile unsigned int apb_error;
++ volatile unsigned int perf_config;
++ unsigned char pad1[12]; /* pad to 0x2a0 */
++ volatile unsigned int perf_counter[4];
++ volatile unsigned int cpu_setup_config;
++ volatile unsigned int mc_setup_config;
++ volatile unsigned int bb_setup_config;
++ volatile unsigned int sdio_setup_config;
++ volatile unsigned int cpu_setup_circuit[8];
++ volatile unsigned int mc_setup_circuit[8];
++ volatile unsigned int bb_setup_circuit[8];
++ volatile unsigned int sdio_setup_circuit[8];
++ volatile unsigned int timing_summary;
++ volatile unsigned int timing_int_enable;
++ volatile unsigned int mc_error_status;
++} mc_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MC_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/rtc_reg.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/rtc_reg.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1204 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef _RTC_REG_H_
++#define _RTC_REG_H_
++
++#define RESET_CONTROL_ADDRESS 0x0c000000
++#define RESET_CONTROL_OFFSET 0x00000000
++#define RESET_CONTROL_RST_OUT_MSB 9
++#define RESET_CONTROL_RST_OUT_LSB 9
++#define RESET_CONTROL_RST_OUT_MASK 0x00000200
++#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
++#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
++#define RESET_CONTROL_COLD_RST_MSB 8
++#define RESET_CONTROL_COLD_RST_LSB 8
++#define RESET_CONTROL_COLD_RST_MASK 0x00000100
++#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
++#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
++#define RESET_CONTROL_WARM_RST_MSB 7
++#define RESET_CONTROL_WARM_RST_LSB 7
++#define RESET_CONTROL_WARM_RST_MASK 0x00000080
++#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
++#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
++#define RESET_CONTROL_CPU_WARM_RST_MSB 6
++#define RESET_CONTROL_CPU_WARM_RST_LSB 6
++#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
++#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
++#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
++#define RESET_CONTROL_MAC_COLD_RST_MSB 5
++#define RESET_CONTROL_MAC_COLD_RST_LSB 5
++#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
++#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
++#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
++#define RESET_CONTROL_MAC_WARM_RST_MSB 4
++#define RESET_CONTROL_MAC_WARM_RST_LSB 4
++#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
++#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
++#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
++#define RESET_CONTROL_MBOX_RST_MSB 2
++#define RESET_CONTROL_MBOX_RST_LSB 2
++#define RESET_CONTROL_MBOX_RST_MASK 0x00000004
++#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
++#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
++#define RESET_CONTROL_UART_RST_MSB 1
++#define RESET_CONTROL_UART_RST_LSB 1
++#define RESET_CONTROL_UART_RST_MASK 0x00000002
++#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
++#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
++#define RESET_CONTROL_SI0_RST_MSB 0
++#define RESET_CONTROL_SI0_RST_LSB 0
++#define RESET_CONTROL_SI0_RST_MASK 0x00000001
++#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
++#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
++
++#define XTAL_CONTROL_ADDRESS 0x0c000004
++#define XTAL_CONTROL_OFFSET 0x00000004
++#define XTAL_CONTROL_TCXO_MSB 0
++#define XTAL_CONTROL_TCXO_LSB 0
++#define XTAL_CONTROL_TCXO_MASK 0x00000001
++#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
++#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
++
++#define TCXO_DETECT_ADDRESS 0x0c000008
++#define TCXO_DETECT_OFFSET 0x00000008
++#define TCXO_DETECT_PRESENT_MSB 0
++#define TCXO_DETECT_PRESENT_LSB 0
++#define TCXO_DETECT_PRESENT_MASK 0x00000001
++#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
++#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
++
++#define XTAL_TEST_ADDRESS 0x0c00000c
++#define XTAL_TEST_OFFSET 0x0000000c
++#define XTAL_TEST_NOTCXODET_MSB 0
++#define XTAL_TEST_NOTCXODET_LSB 0
++#define XTAL_TEST_NOTCXODET_MASK 0x00000001
++#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
++#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
++
++#define QUADRATURE_ADDRESS 0x0c000010
++#define QUADRATURE_OFFSET 0x00000010
++#define QUADRATURE_ADC_MSB 5
++#define QUADRATURE_ADC_LSB 4
++#define QUADRATURE_ADC_MASK 0x00000030
++#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
++#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
++#define QUADRATURE_SEL_MSB 2
++#define QUADRATURE_SEL_LSB 2
++#define QUADRATURE_SEL_MASK 0x00000004
++#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
++#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
++#define QUADRATURE_DAC_MSB 1
++#define QUADRATURE_DAC_LSB 0
++#define QUADRATURE_DAC_MASK 0x00000003
++#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
++#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
++
++#define PLL_CONTROL_ADDRESS 0x0c000014
++#define PLL_CONTROL_OFFSET 0x00000014
++#define PLL_CONTROL_DIG_TEST_CLK_MSB 20
++#define PLL_CONTROL_DIG_TEST_CLK_LSB 20
++#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
++#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
++#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
++#define PLL_CONTROL_MAC_OVERRIDE_MSB 19
++#define PLL_CONTROL_MAC_OVERRIDE_LSB 19
++#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
++#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
++#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
++#define PLL_CONTROL_NOPWD_MSB 18
++#define PLL_CONTROL_NOPWD_LSB 18
++#define PLL_CONTROL_NOPWD_MASK 0x00040000
++#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
++#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
++#define PLL_CONTROL_UPDATING_MSB 17
++#define PLL_CONTROL_UPDATING_LSB 17
++#define PLL_CONTROL_UPDATING_MASK 0x00020000
++#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
++#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
++#define PLL_CONTROL_BYPASS_MSB 16
++#define PLL_CONTROL_BYPASS_LSB 16
++#define PLL_CONTROL_BYPASS_MASK 0x00010000
++#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
++#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
++#define PLL_CONTROL_REFDIV_MSB 15
++#define PLL_CONTROL_REFDIV_LSB 12
++#define PLL_CONTROL_REFDIV_MASK 0x0000f000
++#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
++#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
++#define PLL_CONTROL_DIV_MSB 9
++#define PLL_CONTROL_DIV_LSB 0
++#define PLL_CONTROL_DIV_MASK 0x000003ff
++#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
++#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
++
++#define PLL_SETTLE_ADDRESS 0x0c000018
++#define PLL_SETTLE_OFFSET 0x00000018
++#define PLL_SETTLE_TIME_MSB 10
++#define PLL_SETTLE_TIME_LSB 0
++#define PLL_SETTLE_TIME_MASK 0x000007ff
++#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
++#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
++
++#define XTAL_SETTLE_ADDRESS 0x0c00001c
++#define XTAL_SETTLE_OFFSET 0x0000001c
++#define XTAL_SETTLE_TIME_MSB 6
++#define XTAL_SETTLE_TIME_LSB 0
++#define XTAL_SETTLE_TIME_MASK 0x0000007f
++#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
++#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
++
++#define CORE_CLOCK_ADDRESS 0x0c000020
++#define CORE_CLOCK_OFFSET 0x00000020
++#define CORE_CLOCK_DIG_TEST_MSB 12
++#define CORE_CLOCK_DIG_TEST_LSB 12
++#define CORE_CLOCK_DIG_TEST_MASK 0x00001000
++#define CORE_CLOCK_DIG_TEST_GET(x) (((x) & CORE_CLOCK_DIG_TEST_MASK) >> CORE_CLOCK_DIG_TEST_LSB)
++#define CORE_CLOCK_DIG_TEST_SET(x) (((x) << CORE_CLOCK_DIG_TEST_LSB) & CORE_CLOCK_DIG_TEST_MASK)
++#define CORE_CLOCK_STANDARD_MSB 9
++#define CORE_CLOCK_STANDARD_LSB 8
++#define CORE_CLOCK_STANDARD_MASK 0x00000300
++#define CORE_CLOCK_STANDARD_GET(x) (((x) & CORE_CLOCK_STANDARD_MASK) >> CORE_CLOCK_STANDARD_LSB)
++#define CORE_CLOCK_STANDARD_SET(x) (((x) << CORE_CLOCK_STANDARD_LSB) & CORE_CLOCK_STANDARD_MASK)
++#define CORE_CLOCK_REDUCED_MSB 1
++#define CORE_CLOCK_REDUCED_LSB 0
++#define CORE_CLOCK_REDUCED_MASK 0x00000003
++#define CORE_CLOCK_REDUCED_GET(x) (((x) & CORE_CLOCK_REDUCED_MASK) >> CORE_CLOCK_REDUCED_LSB)
++#define CORE_CLOCK_REDUCED_SET(x) (((x) << CORE_CLOCK_REDUCED_LSB) & CORE_CLOCK_REDUCED_MASK)
++
++#define CPU_CLOCK_ADDRESS 0x0c000024
++#define CPU_CLOCK_OFFSET 0x00000024
++#define CPU_CLOCK_DISABLE_SYNC_MSB 12
++#define CPU_CLOCK_DISABLE_SYNC_LSB 12
++#define CPU_CLOCK_DISABLE_SYNC_MASK 0x00001000
++#define CPU_CLOCK_DISABLE_SYNC_GET(x) (((x) & CPU_CLOCK_DISABLE_SYNC_MASK) >> CPU_CLOCK_DISABLE_SYNC_LSB)
++#define CPU_CLOCK_DISABLE_SYNC_SET(x) (((x) << CPU_CLOCK_DISABLE_SYNC_LSB) & CPU_CLOCK_DISABLE_SYNC_MASK)
++#define CPU_CLOCK_STANDARD_MSB 9
++#define CPU_CLOCK_STANDARD_LSB 8
++#define CPU_CLOCK_STANDARD_MASK 0x00000300
++#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
++#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
++#define CPU_CLOCK_REDUCED_MSB 1
++#define CPU_CLOCK_REDUCED_LSB 0
++#define CPU_CLOCK_REDUCED_MASK 0x00000003
++#define CPU_CLOCK_REDUCED_GET(x) (((x) & CPU_CLOCK_REDUCED_MASK) >> CPU_CLOCK_REDUCED_LSB)
++#define CPU_CLOCK_REDUCED_SET(x) (((x) << CPU_CLOCK_REDUCED_LSB) & CPU_CLOCK_REDUCED_MASK)
++
++#define CLOCK_OUT_ADDRESS 0x0c000028
++#define CLOCK_OUT_OFFSET 0x00000028
++#define CLOCK_OUT_SELECT_MSB 3
++#define CLOCK_OUT_SELECT_LSB 0
++#define CLOCK_OUT_SELECT_MASK 0x0000000f
++#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
++#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
++
++#define CLOCK_CONTROL_ADDRESS 0x0c00002c
++#define CLOCK_CONTROL_OFFSET 0x0000002c
++#define CLOCK_CONTROL_UART_CLK_MSB 1
++#define CLOCK_CONTROL_UART_CLK_LSB 1
++#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002
++#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
++#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
++#define CLOCK_CONTROL_SI0_CLK_MSB 0
++#define CLOCK_CONTROL_SI0_CLK_LSB 0
++#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
++#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
++#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
++
++#define BIAS_OVERRIDE_ADDRESS 0x0c000030
++#define BIAS_OVERRIDE_OFFSET 0x00000030
++#define BIAS_OVERRIDE_ON_MSB 0
++#define BIAS_OVERRIDE_ON_LSB 0
++#define BIAS_OVERRIDE_ON_MASK 0x00000001
++#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
++#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
++
++#define REF_VOLTAGE_TRIM_ADDRESS 0x0c000034
++#define REF_VOLTAGE_TRIM_OFFSET 0x00000034
++#define REF_VOLTAGE_TRIM_REFSEL_MSB 3
++#define REF_VOLTAGE_TRIM_REFSEL_LSB 0
++#define REF_VOLTAGE_TRIM_REFSEL_MASK 0x0000000f
++#define REF_VOLTAGE_TRIM_REFSEL_GET(x) (((x) & REF_VOLTAGE_TRIM_REFSEL_MASK) >> REF_VOLTAGE_TRIM_REFSEL_LSB)
++#define REF_VOLTAGE_TRIM_REFSEL_SET(x) (((x) << REF_VOLTAGE_TRIM_REFSEL_LSB) & REF_VOLTAGE_TRIM_REFSEL_MASK)
++
++#define LDO_CONTROL_ADDRESS 0x0c000038
++#define LDO_CONTROL_OFFSET 0x00000038
++#define LDO_CONTROL_CORE_LIMIT_OFF_MSB 14
++#define LDO_CONTROL_CORE_LIMIT_OFF_LSB 14
++#define LDO_CONTROL_CORE_LIMIT_OFF_MASK 0x00004000
++#define LDO_CONTROL_CORE_LIMIT_OFF_GET(x) (((x) & LDO_CONTROL_CORE_LIMIT_OFF_MASK) >> LDO_CONTROL_CORE_LIMIT_OFF_LSB)
++#define LDO_CONTROL_CORE_LIMIT_OFF_SET(x) (((x) << LDO_CONTROL_CORE_LIMIT_OFF_LSB) & LDO_CONTROL_CORE_LIMIT_OFF_MASK)
++#define LDO_CONTROL_CORE_LIMIT_MSB 13
++#define LDO_CONTROL_CORE_LIMIT_LSB 11
++#define LDO_CONTROL_CORE_LIMIT_MASK 0x00003800
++#define LDO_CONTROL_CORE_LIMIT_GET(x) (((x) & LDO_CONTROL_CORE_LIMIT_MASK) >> LDO_CONTROL_CORE_LIMIT_LSB)
++#define LDO_CONTROL_CORE_LIMIT_SET(x) (((x) << LDO_CONTROL_CORE_LIMIT_LSB) & LDO_CONTROL_CORE_LIMIT_MASK)
++#define LDO_CONTROL_CORE_REG_Z_MSB 10
++#define LDO_CONTROL_CORE_REG_Z_LSB 8
++#define LDO_CONTROL_CORE_REG_Z_MASK 0x00000700
++#define LDO_CONTROL_CORE_REG_Z_GET(x) (((x) & LDO_CONTROL_CORE_REG_Z_MASK) >> LDO_CONTROL_CORE_REG_Z_LSB)
++#define LDO_CONTROL_CORE_REG_Z_SET(x) (((x) << LDO_CONTROL_CORE_REG_Z_LSB) & LDO_CONTROL_CORE_REG_Z_MASK)
++#define LDO_CONTROL_RADIO_LIMIT_OFF_MSB 6
++#define LDO_CONTROL_RADIO_LIMIT_OFF_LSB 6
++#define LDO_CONTROL_RADIO_LIMIT_OFF_MASK 0x00000040
++#define LDO_CONTROL_RADIO_LIMIT_OFF_GET(x) (((x) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK) >> LDO_CONTROL_RADIO_LIMIT_OFF_LSB)
++#define LDO_CONTROL_RADIO_LIMIT_OFF_SET(x) (((x) << LDO_CONTROL_RADIO_LIMIT_OFF_LSB) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK)
++#define LDO_CONTROL_RADIO_LIMIT_MSB 5
++#define LDO_CONTROL_RADIO_LIMIT_LSB 3
++#define LDO_CONTROL_RADIO_LIMIT_MASK 0x00000038
++#define LDO_CONTROL_RADIO_LIMIT_GET(x) (((x) & LDO_CONTROL_RADIO_LIMIT_MASK) >> LDO_CONTROL_RADIO_LIMIT_LSB)
++#define LDO_CONTROL_RADIO_LIMIT_SET(x) (((x) << LDO_CONTROL_RADIO_LIMIT_LSB) & LDO_CONTROL_RADIO_LIMIT_MASK)
++#define LDO_CONTROL_RADIO_REG_Z_MSB 2
++#define LDO_CONTROL_RADIO_REG_Z_LSB 0
++#define LDO_CONTROL_RADIO_REG_Z_MASK 0x00000007
++#define LDO_CONTROL_RADIO_REG_Z_GET(x) (((x) & LDO_CONTROL_RADIO_REG_Z_MASK) >> LDO_CONTROL_RADIO_REG_Z_LSB)
++#define LDO_CONTROL_RADIO_REG_Z_SET(x) (((x) << LDO_CONTROL_RADIO_REG_Z_LSB) & LDO_CONTROL_RADIO_REG_Z_MASK)
++
++#define WDT_CONTROL_ADDRESS 0x0c00003c
++#define WDT_CONTROL_OFFSET 0x0000003c
++#define WDT_CONTROL_ACTION_MSB 2
++#define WDT_CONTROL_ACTION_LSB 0
++#define WDT_CONTROL_ACTION_MASK 0x00000007
++#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
++#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
++
++#define WDT_STATUS_ADDRESS 0x0c000040
++#define WDT_STATUS_OFFSET 0x00000040
++#define WDT_STATUS_INTERRUPT_MSB 0
++#define WDT_STATUS_INTERRUPT_LSB 0
++#define WDT_STATUS_INTERRUPT_MASK 0x00000001
++#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
++#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
++
++#define WDT_ADDRESS 0x0c000044
++#define WDT_OFFSET 0x00000044
++#define WDT_TARGET_MSB 21
++#define WDT_TARGET_LSB 0
++#define WDT_TARGET_MASK 0x003fffff
++#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
++#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
++
++#define WDT_COUNT_ADDRESS 0x0c000048
++#define WDT_COUNT_OFFSET 0x00000048
++#define WDT_COUNT_VALUE_MSB 21
++#define WDT_COUNT_VALUE_LSB 0
++#define WDT_COUNT_VALUE_MASK 0x003fffff
++#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
++#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
++
++#define WDT_RESET_ADDRESS 0x0c00004c
++#define WDT_RESET_OFFSET 0x0000004c
++#define WDT_RESET_VALUE_MSB 0
++#define WDT_RESET_VALUE_LSB 0
++#define WDT_RESET_VALUE_MASK 0x00000001
++#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
++#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
++
++#define INT_STATUS_ADDRESS 0x0c000050
++#define INT_STATUS_OFFSET 0x00000050
++#define INT_STATUS_TIMER_MSB 14
++#define INT_STATUS_TIMER_LSB 14
++#define INT_STATUS_TIMER_MASK 0x00004000
++#define INT_STATUS_TIMER_GET(x) (((x) & INT_STATUS_TIMER_MASK) >> INT_STATUS_TIMER_LSB)
++#define INT_STATUS_TIMER_SET(x) (((x) << INT_STATUS_TIMER_LSB) & INT_STATUS_TIMER_MASK)
++#define INT_STATUS_MAC_MSB 13
++#define INT_STATUS_MAC_LSB 13
++#define INT_STATUS_MAC_MASK 0x00002000
++#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
++#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
++#define INT_STATUS_MAILBOX_MSB 12
++#define INT_STATUS_MAILBOX_LSB 12
++#define INT_STATUS_MAILBOX_MASK 0x00001000
++#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
++#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
++#define INT_STATUS_RTC_ALARM_MSB 11
++#define INT_STATUS_RTC_ALARM_LSB 11
++#define INT_STATUS_RTC_ALARM_MASK 0x00000800
++#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
++#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
++#define INT_STATUS_HF_TIMER_MSB 10
++#define INT_STATUS_HF_TIMER_LSB 10
++#define INT_STATUS_HF_TIMER_MASK 0x00000400
++#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
++#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
++#define INT_STATUS_LF_TIMER3_MSB 9
++#define INT_STATUS_LF_TIMER3_LSB 9
++#define INT_STATUS_LF_TIMER3_MASK 0x00000200
++#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
++#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
++#define INT_STATUS_LF_TIMER2_MSB 8
++#define INT_STATUS_LF_TIMER2_LSB 8
++#define INT_STATUS_LF_TIMER2_MASK 0x00000100
++#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
++#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
++#define INT_STATUS_LF_TIMER1_MSB 7
++#define INT_STATUS_LF_TIMER1_LSB 7
++#define INT_STATUS_LF_TIMER1_MASK 0x00000080
++#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
++#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
++#define INT_STATUS_LF_TIMER0_MSB 6
++#define INT_STATUS_LF_TIMER0_LSB 6
++#define INT_STATUS_LF_TIMER0_MASK 0x00000040
++#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
++#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
++#define INT_STATUS_KEYPAD_MSB 5
++#define INT_STATUS_KEYPAD_LSB 5
++#define INT_STATUS_KEYPAD_MASK 0x00000020
++#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
++#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
++#define INT_STATUS_SI_MSB 4
++#define INT_STATUS_SI_LSB 4
++#define INT_STATUS_SI_MASK 0x00000010
++#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
++#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
++#define INT_STATUS_GPIO_MSB 3
++#define INT_STATUS_GPIO_LSB 3
++#define INT_STATUS_GPIO_MASK 0x00000008
++#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
++#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
++#define INT_STATUS_UART_MSB 2
++#define INT_STATUS_UART_LSB 2
++#define INT_STATUS_UART_MASK 0x00000004
++#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
++#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
++#define INT_STATUS_ERROR_MSB 1
++#define INT_STATUS_ERROR_LSB 1
++#define INT_STATUS_ERROR_MASK 0x00000002
++#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
++#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
++#define INT_STATUS_WDT_INT_MSB 0
++#define INT_STATUS_WDT_INT_LSB 0
++#define INT_STATUS_WDT_INT_MASK 0x00000001
++#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
++#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
++
++#define LF_TIMER0_ADDRESS 0x0c000054
++#define LF_TIMER0_OFFSET 0x00000054
++#define LF_TIMER0_TARGET_MSB 31
++#define LF_TIMER0_TARGET_LSB 0
++#define LF_TIMER0_TARGET_MASK 0xffffffff
++#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
++#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
++
++#define LF_TIMER_COUNT0_ADDRESS 0x0c000058
++#define LF_TIMER_COUNT0_OFFSET 0x00000058
++#define LF_TIMER_COUNT0_VALUE_MSB 31
++#define LF_TIMER_COUNT0_VALUE_LSB 0
++#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
++#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
++#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
++
++#define LF_TIMER_CONTROL0_ADDRESS 0x0c00005c
++#define LF_TIMER_CONTROL0_OFFSET 0x0000005c
++#define LF_TIMER_CONTROL0_ENABLE_MSB 2
++#define LF_TIMER_CONTROL0_ENABLE_LSB 2
++#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
++#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
++#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
++#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
++#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
++#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
++#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL0_RESET_MSB 0
++#define LF_TIMER_CONTROL0_RESET_LSB 0
++#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001
++#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
++#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
++
++#define LF_TIMER_STATUS0_ADDRESS 0x0c000060
++#define LF_TIMER_STATUS0_OFFSET 0x00000060
++#define LF_TIMER_STATUS0_INTERRUPT_MSB 0
++#define LF_TIMER_STATUS0_INTERRUPT_LSB 0
++#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
++#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
++#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
++
++#define LF_TIMER1_ADDRESS 0x0c000064
++#define LF_TIMER1_OFFSET 0x00000064
++#define LF_TIMER1_TARGET_MSB 31
++#define LF_TIMER1_TARGET_LSB 0
++#define LF_TIMER1_TARGET_MASK 0xffffffff
++#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
++#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
++
++#define LF_TIMER_COUNT1_ADDRESS 0x0c000068
++#define LF_TIMER_COUNT1_OFFSET 0x00000068
++#define LF_TIMER_COUNT1_VALUE_MSB 31
++#define LF_TIMER_COUNT1_VALUE_LSB 0
++#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
++#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
++#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
++
++#define LF_TIMER_CONTROL1_ADDRESS 0x0c00006c
++#define LF_TIMER_CONTROL1_OFFSET 0x0000006c
++#define LF_TIMER_CONTROL1_ENABLE_MSB 2
++#define LF_TIMER_CONTROL1_ENABLE_LSB 2
++#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
++#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
++#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
++#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
++#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
++#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
++#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL1_RESET_MSB 0
++#define LF_TIMER_CONTROL1_RESET_LSB 0
++#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001
++#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
++#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
++
++#define LF_TIMER_STATUS1_ADDRESS 0x0c000070
++#define LF_TIMER_STATUS1_OFFSET 0x00000070
++#define LF_TIMER_STATUS1_INTERRUPT_MSB 0
++#define LF_TIMER_STATUS1_INTERRUPT_LSB 0
++#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
++#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
++#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
++
++#define LF_TIMER2_ADDRESS 0x0c000074
++#define LF_TIMER2_OFFSET 0x00000074
++#define LF_TIMER2_TARGET_MSB 31
++#define LF_TIMER2_TARGET_LSB 0
++#define LF_TIMER2_TARGET_MASK 0xffffffff
++#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
++#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
++
++#define LF_TIMER_COUNT2_ADDRESS 0x0c000078
++#define LF_TIMER_COUNT2_OFFSET 0x00000078
++#define LF_TIMER_COUNT2_VALUE_MSB 31
++#define LF_TIMER_COUNT2_VALUE_LSB 0
++#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
++#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
++#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
++
++#define LF_TIMER_CONTROL2_ADDRESS 0x0c00007c
++#define LF_TIMER_CONTROL2_OFFSET 0x0000007c
++#define LF_TIMER_CONTROL2_ENABLE_MSB 2
++#define LF_TIMER_CONTROL2_ENABLE_LSB 2
++#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
++#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
++#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
++#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
++#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
++#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
++#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL2_RESET_MSB 0
++#define LF_TIMER_CONTROL2_RESET_LSB 0
++#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001
++#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
++#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
++
++#define LF_TIMER_STATUS2_ADDRESS 0x0c000080
++#define LF_TIMER_STATUS2_OFFSET 0x00000080
++#define LF_TIMER_STATUS2_INTERRUPT_MSB 0
++#define LF_TIMER_STATUS2_INTERRUPT_LSB 0
++#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
++#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
++#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
++
++#define LF_TIMER3_ADDRESS 0x0c000084
++#define LF_TIMER3_OFFSET 0x00000084
++#define LF_TIMER3_TARGET_MSB 31
++#define LF_TIMER3_TARGET_LSB 0
++#define LF_TIMER3_TARGET_MASK 0xffffffff
++#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
++#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
++
++#define LF_TIMER_COUNT3_ADDRESS 0x0c000088
++#define LF_TIMER_COUNT3_OFFSET 0x00000088
++#define LF_TIMER_COUNT3_VALUE_MSB 31
++#define LF_TIMER_COUNT3_VALUE_LSB 0
++#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
++#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
++#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
++
++#define LF_TIMER_CONTROL3_ADDRESS 0x0c00008c
++#define LF_TIMER_CONTROL3_OFFSET 0x0000008c
++#define LF_TIMER_CONTROL3_ENABLE_MSB 2
++#define LF_TIMER_CONTROL3_ENABLE_LSB 2
++#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
++#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
++#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
++#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
++#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
++#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
++#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
++#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
++#define LF_TIMER_CONTROL3_RESET_MSB 0
++#define LF_TIMER_CONTROL3_RESET_LSB 0
++#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001
++#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
++#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
++
++#define LF_TIMER_STATUS3_ADDRESS 0x0c000090
++#define LF_TIMER_STATUS3_OFFSET 0x00000090
++#define LF_TIMER_STATUS3_INTERRUPT_MSB 0
++#define LF_TIMER_STATUS3_INTERRUPT_LSB 0
++#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
++#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
++#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
++
++#define HF_TIMER_ADDRESS 0x0c000094
++#define HF_TIMER_OFFSET 0x00000094
++#define HF_TIMER_TARGET_MSB 31
++#define HF_TIMER_TARGET_LSB 12
++#define HF_TIMER_TARGET_MASK 0xfffff000
++#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
++#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
++
++#define HF_TIMER_COUNT_ADDRESS 0x0c000098
++#define HF_TIMER_COUNT_OFFSET 0x00000098
++#define HF_TIMER_COUNT_VALUE_MSB 31
++#define HF_TIMER_COUNT_VALUE_LSB 12
++#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000
++#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
++#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
++
++#define HF_LF_COUNT_ADDRESS 0x0c00009c
++#define HF_LF_COUNT_OFFSET 0x0000009c
++#define HF_LF_COUNT_VALUE_MSB 31
++#define HF_LF_COUNT_VALUE_LSB 0
++#define HF_LF_COUNT_VALUE_MASK 0xffffffff
++#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
++#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
++
++#define HF_TIMER_CONTROL_ADDRESS 0x0c0000a0
++#define HF_TIMER_CONTROL_OFFSET 0x000000a0
++#define HF_TIMER_CONTROL_ENABLE_MSB 3
++#define HF_TIMER_CONTROL_ENABLE_LSB 3
++#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
++#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
++#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
++#define HF_TIMER_CONTROL_ON_MSB 2
++#define HF_TIMER_CONTROL_ON_LSB 2
++#define HF_TIMER_CONTROL_ON_MASK 0x00000004
++#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
++#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
++#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
++#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
++#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
++#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
++#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
++#define HF_TIMER_CONTROL_RESET_MSB 0
++#define HF_TIMER_CONTROL_RESET_LSB 0
++#define HF_TIMER_CONTROL_RESET_MASK 0x00000001
++#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
++#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
++
++#define HF_TIMER_STATUS_ADDRESS 0x0c0000a4
++#define HF_TIMER_STATUS_OFFSET 0x000000a4
++#define HF_TIMER_STATUS_INTERRUPT_MSB 0
++#define HF_TIMER_STATUS_INTERRUPT_LSB 0
++#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
++#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
++#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
++
++#define RTC_CONTROL_ADDRESS 0x0c0000a8
++#define RTC_CONTROL_OFFSET 0x000000a8
++#define RTC_CONTROL_ENABLE_MSB 2
++#define RTC_CONTROL_ENABLE_LSB 2
++#define RTC_CONTROL_ENABLE_MASK 0x00000004
++#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
++#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
++#define RTC_CONTROL_LOAD_RTC_MSB 1
++#define RTC_CONTROL_LOAD_RTC_LSB 1
++#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002
++#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
++#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
++#define RTC_CONTROL_LOAD_ALARM_MSB 0
++#define RTC_CONTROL_LOAD_ALARM_LSB 0
++#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
++#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
++#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
++
++#define RTC_TIME_ADDRESS 0x0c0000ac
++#define RTC_TIME_OFFSET 0x000000ac
++#define RTC_TIME_WEEK_DAY_MSB 26
++#define RTC_TIME_WEEK_DAY_LSB 24
++#define RTC_TIME_WEEK_DAY_MASK 0x07000000
++#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
++#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
++#define RTC_TIME_HOUR_MSB 21
++#define RTC_TIME_HOUR_LSB 16
++#define RTC_TIME_HOUR_MASK 0x003f0000
++#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
++#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
++#define RTC_TIME_MINUTE_MSB 14
++#define RTC_TIME_MINUTE_LSB 8
++#define RTC_TIME_MINUTE_MASK 0x00007f00
++#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
++#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
++#define RTC_TIME_SECOND_MSB 6
++#define RTC_TIME_SECOND_LSB 0
++#define RTC_TIME_SECOND_MASK 0x0000007f
++#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
++#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
++
++#define RTC_DATE_ADDRESS 0x0c0000b0
++#define RTC_DATE_OFFSET 0x000000b0
++#define RTC_DATE_YEAR_MSB 23
++#define RTC_DATE_YEAR_LSB 16
++#define RTC_DATE_YEAR_MASK 0x00ff0000
++#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
++#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
++#define RTC_DATE_MONTH_MSB 12
++#define RTC_DATE_MONTH_LSB 8
++#define RTC_DATE_MONTH_MASK 0x00001f00
++#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
++#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
++#define RTC_DATE_MONTH_DAY_MSB 5
++#define RTC_DATE_MONTH_DAY_LSB 0
++#define RTC_DATE_MONTH_DAY_MASK 0x0000003f
++#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
++#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
++
++#define RTC_SET_TIME_ADDRESS 0x0c0000b4
++#define RTC_SET_TIME_OFFSET 0x000000b4
++#define RTC_SET_TIME_WEEK_DAY_MSB 26
++#define RTC_SET_TIME_WEEK_DAY_LSB 24
++#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
++#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
++#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
++#define RTC_SET_TIME_HOUR_MSB 21
++#define RTC_SET_TIME_HOUR_LSB 16
++#define RTC_SET_TIME_HOUR_MASK 0x003f0000
++#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
++#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
++#define RTC_SET_TIME_MINUTE_MSB 14
++#define RTC_SET_TIME_MINUTE_LSB 8
++#define RTC_SET_TIME_MINUTE_MASK 0x00007f00
++#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
++#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
++#define RTC_SET_TIME_SECOND_MSB 6
++#define RTC_SET_TIME_SECOND_LSB 0
++#define RTC_SET_TIME_SECOND_MASK 0x0000007f
++#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
++#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
++
++#define RTC_SET_DATE_ADDRESS 0x0c0000b8
++#define RTC_SET_DATE_OFFSET 0x000000b8
++#define RTC_SET_DATE_YEAR_MSB 23
++#define RTC_SET_DATE_YEAR_LSB 16
++#define RTC_SET_DATE_YEAR_MASK 0x00ff0000
++#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
++#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
++#define RTC_SET_DATE_MONTH_MSB 12
++#define RTC_SET_DATE_MONTH_LSB 8
++#define RTC_SET_DATE_MONTH_MASK 0x00001f00
++#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
++#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
++#define RTC_SET_DATE_MONTH_DAY_MSB 5
++#define RTC_SET_DATE_MONTH_DAY_LSB 0
++#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
++#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
++#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
++
++#define RTC_SET_ALARM_ADDRESS 0x0c0000bc
++#define RTC_SET_ALARM_OFFSET 0x000000bc
++#define RTC_SET_ALARM_HOUR_MSB 21
++#define RTC_SET_ALARM_HOUR_LSB 16
++#define RTC_SET_ALARM_HOUR_MASK 0x003f0000
++#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
++#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
++#define RTC_SET_ALARM_MINUTE_MSB 14
++#define RTC_SET_ALARM_MINUTE_LSB 8
++#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00
++#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
++#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
++#define RTC_SET_ALARM_SECOND_MSB 6
++#define RTC_SET_ALARM_SECOND_LSB 0
++#define RTC_SET_ALARM_SECOND_MASK 0x0000007f
++#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
++#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
++
++#define RTC_CONFIG_ADDRESS 0x0c0000c0
++#define RTC_CONFIG_OFFSET 0x000000c0
++#define RTC_CONFIG_BCD_MSB 2
++#define RTC_CONFIG_BCD_LSB 2
++#define RTC_CONFIG_BCD_MASK 0x00000004
++#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
++#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
++#define RTC_CONFIG_TWELVE_HOUR_MSB 1
++#define RTC_CONFIG_TWELVE_HOUR_LSB 1
++#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
++#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
++#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
++#define RTC_CONFIG_DSE_MSB 0
++#define RTC_CONFIG_DSE_LSB 0
++#define RTC_CONFIG_DSE_MASK 0x00000001
++#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
++#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
++
++#define RTC_ALARM_STATUS_ADDRESS 0x0c0000c4
++#define RTC_ALARM_STATUS_OFFSET 0x000000c4
++#define RTC_ALARM_STATUS_ENABLE_MSB 1
++#define RTC_ALARM_STATUS_ENABLE_LSB 1
++#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
++#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
++#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
++#define RTC_ALARM_STATUS_INTERRUPT_MSB 0
++#define RTC_ALARM_STATUS_INTERRUPT_LSB 0
++#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
++#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
++#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
++
++#define UART_WAKEUP_ADDRESS 0x0c0000c8
++#define UART_WAKEUP_OFFSET 0x000000c8
++#define UART_WAKEUP_ENABLE_MSB 0
++#define UART_WAKEUP_ENABLE_LSB 0
++#define UART_WAKEUP_ENABLE_MASK 0x00000001
++#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
++#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
++
++#define RESET_CAUSE_ADDRESS 0x0c0000cc
++#define RESET_CAUSE_OFFSET 0x000000cc
++#define RESET_CAUSE_LAST_MSB 2
++#define RESET_CAUSE_LAST_LSB 0
++#define RESET_CAUSE_LAST_MASK 0x00000007
++#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
++#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
++
++#define SYSTEM_SLEEP_ADDRESS 0x0c0000d0
++#define SYSTEM_SLEEP_OFFSET 0x000000d0
++#define SYSTEM_SLEEP_HOST_IF_MSB 4
++#define SYSTEM_SLEEP_HOST_IF_LSB 4
++#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
++#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
++#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
++#define SYSTEM_SLEEP_MBOX_MSB 3
++#define SYSTEM_SLEEP_MBOX_LSB 3
++#define SYSTEM_SLEEP_MBOX_MASK 0x00000008
++#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
++#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
++#define SYSTEM_SLEEP_MAC_IF_MSB 2
++#define SYSTEM_SLEEP_MAC_IF_LSB 2
++#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
++#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
++#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
++#define SYSTEM_SLEEP_LIGHT_MSB 1
++#define SYSTEM_SLEEP_LIGHT_LSB 1
++#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002
++#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
++#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
++#define SYSTEM_SLEEP_DISABLE_MSB 0
++#define SYSTEM_SLEEP_DISABLE_LSB 0
++#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001
++#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
++#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
++
++#define LDO_VOLTAGE_ADDRESS 0x0c0000d4
++#define LDO_VOLTAGE_OFFSET 0x000000d4
++#define LDO_VOLTAGE_SLEEP_MSB 14
++#define LDO_VOLTAGE_SLEEP_LSB 12
++#define LDO_VOLTAGE_SLEEP_MASK 0x00007000
++#define LDO_VOLTAGE_SLEEP_GET(x) (((x) & LDO_VOLTAGE_SLEEP_MASK) >> LDO_VOLTAGE_SLEEP_LSB)
++#define LDO_VOLTAGE_SLEEP_SET(x) (((x) << LDO_VOLTAGE_SLEEP_LSB) & LDO_VOLTAGE_SLEEP_MASK)
++#define LDO_VOLTAGE_WAKEUP_MSB 10
++#define LDO_VOLTAGE_WAKEUP_LSB 8
++#define LDO_VOLTAGE_WAKEUP_MASK 0x00000700
++#define LDO_VOLTAGE_WAKEUP_GET(x) (((x) & LDO_VOLTAGE_WAKEUP_MASK) >> LDO_VOLTAGE_WAKEUP_LSB)
++#define LDO_VOLTAGE_WAKEUP_SET(x) (((x) << LDO_VOLTAGE_WAKEUP_LSB) & LDO_VOLTAGE_WAKEUP_MASK)
++#define LDO_VOLTAGE_SOC_ON_MSB 6
++#define LDO_VOLTAGE_SOC_ON_LSB 4
++#define LDO_VOLTAGE_SOC_ON_MASK 0x00000070
++#define LDO_VOLTAGE_SOC_ON_GET(x) (((x) & LDO_VOLTAGE_SOC_ON_MASK) >> LDO_VOLTAGE_SOC_ON_LSB)
++#define LDO_VOLTAGE_SOC_ON_SET(x) (((x) << LDO_VOLTAGE_SOC_ON_LSB) & LDO_VOLTAGE_SOC_ON_MASK)
++#define LDO_VOLTAGE_ON_MSB 2
++#define LDO_VOLTAGE_ON_LSB 0
++#define LDO_VOLTAGE_ON_MASK 0x00000007
++#define LDO_VOLTAGE_ON_GET(x) (((x) & LDO_VOLTAGE_ON_MASK) >> LDO_VOLTAGE_ON_LSB)
++#define LDO_VOLTAGE_ON_SET(x) (((x) << LDO_VOLTAGE_ON_LSB) & LDO_VOLTAGE_ON_MASK)
++
++#define LDO_A_VOLTAGE_ADDRESS 0x0c0000d8
++#define LDO_A_VOLTAGE_OFFSET 0x000000d8
++#define LDO_A_VOLTAGE_SLEEP_MSB 14
++#define LDO_A_VOLTAGE_SLEEP_LSB 12
++#define LDO_A_VOLTAGE_SLEEP_MASK 0x00007000
++#define LDO_A_VOLTAGE_SLEEP_GET(x) (((x) & LDO_A_VOLTAGE_SLEEP_MASK) >> LDO_A_VOLTAGE_SLEEP_LSB)
++#define LDO_A_VOLTAGE_SLEEP_SET(x) (((x) << LDO_A_VOLTAGE_SLEEP_LSB) & LDO_A_VOLTAGE_SLEEP_MASK)
++#define LDO_A_VOLTAGE_WAKEUP_MSB 10
++#define LDO_A_VOLTAGE_WAKEUP_LSB 8
++#define LDO_A_VOLTAGE_WAKEUP_MASK 0x00000700
++#define LDO_A_VOLTAGE_WAKEUP_GET(x) (((x) & LDO_A_VOLTAGE_WAKEUP_MASK) >> LDO_A_VOLTAGE_WAKEUP_LSB)
++#define LDO_A_VOLTAGE_WAKEUP_SET(x) (((x) << LDO_A_VOLTAGE_WAKEUP_LSB) & LDO_A_VOLTAGE_WAKEUP_MASK)
++#define LDO_A_VOLTAGE_SOC_ON_MSB 6
++#define LDO_A_VOLTAGE_SOC_ON_LSB 4
++#define LDO_A_VOLTAGE_SOC_ON_MASK 0x00000070
++#define LDO_A_VOLTAGE_SOC_ON_GET(x) (((x) & LDO_A_VOLTAGE_SOC_ON_MASK) >> LDO_A_VOLTAGE_SOC_ON_LSB)
++#define LDO_A_VOLTAGE_SOC_ON_SET(x) (((x) << LDO_A_VOLTAGE_SOC_ON_LSB) & LDO_A_VOLTAGE_SOC_ON_MASK)
++#define LDO_A_VOLTAGE_ON_MSB 2
++#define LDO_A_VOLTAGE_ON_LSB 0
++#define LDO_A_VOLTAGE_ON_MASK 0x00000007
++#define LDO_A_VOLTAGE_ON_GET(x) (((x) & LDO_A_VOLTAGE_ON_MASK) >> LDO_A_VOLTAGE_ON_LSB)
++#define LDO_A_VOLTAGE_ON_SET(x) (((x) << LDO_A_VOLTAGE_ON_LSB) & LDO_A_VOLTAGE_ON_MASK)
++
++#define SDIO_LDO_VOLTAGE_ADDRESS 0x0c0000dc
++#define SDIO_LDO_VOLTAGE_OFFSET 0x000000dc
++#define SDIO_LDO_VOLTAGE_OFF_MSB 18
++#define SDIO_LDO_VOLTAGE_OFF_LSB 16
++#define SDIO_LDO_VOLTAGE_OFF_MASK 0x00070000
++#define SDIO_LDO_VOLTAGE_OFF_GET(x) (((x) & SDIO_LDO_VOLTAGE_OFF_MASK) >> SDIO_LDO_VOLTAGE_OFF_LSB)
++#define SDIO_LDO_VOLTAGE_OFF_SET(x) (((x) << SDIO_LDO_VOLTAGE_OFF_LSB) & SDIO_LDO_VOLTAGE_OFF_MASK)
++#define SDIO_LDO_VOLTAGE_SLEEP_MSB 14
++#define SDIO_LDO_VOLTAGE_SLEEP_LSB 12
++#define SDIO_LDO_VOLTAGE_SLEEP_MASK 0x00007000
++#define SDIO_LDO_VOLTAGE_SLEEP_GET(x) (((x) & SDIO_LDO_VOLTAGE_SLEEP_MASK) >> SDIO_LDO_VOLTAGE_SLEEP_LSB)
++#define SDIO_LDO_VOLTAGE_SLEEP_SET(x) (((x) << SDIO_LDO_VOLTAGE_SLEEP_LSB) & SDIO_LDO_VOLTAGE_SLEEP_MASK)
++#define SDIO_LDO_VOLTAGE_WAKEUP_MSB 10
++#define SDIO_LDO_VOLTAGE_WAKEUP_LSB 8
++#define SDIO_LDO_VOLTAGE_WAKEUP_MASK 0x00000700
++#define SDIO_LDO_VOLTAGE_WAKEUP_GET(x) (((x) & SDIO_LDO_VOLTAGE_WAKEUP_MASK) >> SDIO_LDO_VOLTAGE_WAKEUP_LSB)
++#define SDIO_LDO_VOLTAGE_WAKEUP_SET(x) (((x) << SDIO_LDO_VOLTAGE_WAKEUP_LSB) & SDIO_LDO_VOLTAGE_WAKEUP_MASK)
++#define SDIO_LDO_VOLTAGE_SOC_ON_MSB 6
++#define SDIO_LDO_VOLTAGE_SOC_ON_LSB 4
++#define SDIO_LDO_VOLTAGE_SOC_ON_MASK 0x00000070
++#define SDIO_LDO_VOLTAGE_SOC_ON_GET(x) (((x) & SDIO_LDO_VOLTAGE_SOC_ON_MASK) >> SDIO_LDO_VOLTAGE_SOC_ON_LSB)
++#define SDIO_LDO_VOLTAGE_SOC_ON_SET(x) (((x) << SDIO_LDO_VOLTAGE_SOC_ON_LSB) & SDIO_LDO_VOLTAGE_SOC_ON_MASK)
++#define SDIO_LDO_VOLTAGE_ON_MSB 2
++#define SDIO_LDO_VOLTAGE_ON_LSB 0
++#define SDIO_LDO_VOLTAGE_ON_MASK 0x00000007
++#define SDIO_LDO_VOLTAGE_ON_GET(x) (((x) & SDIO_LDO_VOLTAGE_ON_MASK) >> SDIO_LDO_VOLTAGE_ON_LSB)
++#define SDIO_LDO_VOLTAGE_ON_SET(x) (((x) << SDIO_LDO_VOLTAGE_ON_LSB) & SDIO_LDO_VOLTAGE_ON_MASK)
++
++#define CORE_PAD_ENABLE_ADDRESS 0x0c0000e0
++#define CORE_PAD_ENABLE_OFFSET 0x000000e0
++#define CORE_PAD_ENABLE_SLEEP_MSB 3
++#define CORE_PAD_ENABLE_SLEEP_LSB 3
++#define CORE_PAD_ENABLE_SLEEP_MASK 0x00000008
++#define CORE_PAD_ENABLE_SLEEP_GET(x) (((x) & CORE_PAD_ENABLE_SLEEP_MASK) >> CORE_PAD_ENABLE_SLEEP_LSB)
++#define CORE_PAD_ENABLE_SLEEP_SET(x) (((x) << CORE_PAD_ENABLE_SLEEP_LSB) & CORE_PAD_ENABLE_SLEEP_MASK)
++#define CORE_PAD_ENABLE_WAKEUP_MSB 2
++#define CORE_PAD_ENABLE_WAKEUP_LSB 2
++#define CORE_PAD_ENABLE_WAKEUP_MASK 0x00000004
++#define CORE_PAD_ENABLE_WAKEUP_GET(x) (((x) & CORE_PAD_ENABLE_WAKEUP_MASK) >> CORE_PAD_ENABLE_WAKEUP_LSB)
++#define CORE_PAD_ENABLE_WAKEUP_SET(x) (((x) << CORE_PAD_ENABLE_WAKEUP_LSB) & CORE_PAD_ENABLE_WAKEUP_MASK)
++#define CORE_PAD_ENABLE_SOC_ON_MSB 1
++#define CORE_PAD_ENABLE_SOC_ON_LSB 1
++#define CORE_PAD_ENABLE_SOC_ON_MASK 0x00000002
++#define CORE_PAD_ENABLE_SOC_ON_GET(x) (((x) & CORE_PAD_ENABLE_SOC_ON_MASK) >> CORE_PAD_ENABLE_SOC_ON_LSB)
++#define CORE_PAD_ENABLE_SOC_ON_SET(x) (((x) << CORE_PAD_ENABLE_SOC_ON_LSB) & CORE_PAD_ENABLE_SOC_ON_MASK)
++#define CORE_PAD_ENABLE_ON_MSB 0
++#define CORE_PAD_ENABLE_ON_LSB 0
++#define CORE_PAD_ENABLE_ON_MASK 0x00000001
++#define CORE_PAD_ENABLE_ON_GET(x) (((x) & CORE_PAD_ENABLE_ON_MASK) >> CORE_PAD_ENABLE_ON_LSB)
++#define CORE_PAD_ENABLE_ON_SET(x) (((x) << CORE_PAD_ENABLE_ON_LSB) & CORE_PAD_ENABLE_ON_MASK)
++
++#define SDIO_WRAPPER_ADDRESS 0x0c0000e4
++#define SDIO_WRAPPER_OFFSET 0x000000e4
++#define SDIO_WRAPPER_SLEEP_MSB 3
++#define SDIO_WRAPPER_SLEEP_LSB 3
++#define SDIO_WRAPPER_SLEEP_MASK 0x00000008
++#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
++#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
++#define SDIO_WRAPPER_WAKEUP_MSB 2
++#define SDIO_WRAPPER_WAKEUP_LSB 2
++#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004
++#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
++#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
++#define SDIO_WRAPPER_SOC_ON_MSB 1
++#define SDIO_WRAPPER_SOC_ON_LSB 1
++#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002
++#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
++#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
++#define SDIO_WRAPPER_ON_MSB 0
++#define SDIO_WRAPPER_ON_LSB 0
++#define SDIO_WRAPPER_ON_MASK 0x00000001
++#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
++#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
++
++#define MAC_SLEEP_CONTROL_ADDRESS 0x0c0000e8
++#define MAC_SLEEP_CONTROL_OFFSET 0x000000e8
++#define MAC_SLEEP_CONTROL_ENABLE_MSB 1
++#define MAC_SLEEP_CONTROL_ENABLE_LSB 0
++#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
++#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
++#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
++
++#define KEEP_AWAKE_ADDRESS 0x0c0000ec
++#define KEEP_AWAKE_OFFSET 0x000000ec
++#define KEEP_AWAKE_COUNT_MSB 7
++#define KEEP_AWAKE_COUNT_LSB 0
++#define KEEP_AWAKE_COUNT_MASK 0x000000ff
++#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
++#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
++
++#define CHIP_REV_ADDRESS 0x0c0000f0
++#define CHIP_REV_OFFSET 0x000000f0
++#define CHIP_REV_ID_MSB 7
++#define CHIP_REV_ID_LSB 0
++#define CHIP_REV_ID_MASK 0x000000ff
++#define CHIP_REV_ID_GET(x) (((x) & CHIP_REV_ID_MASK) >> CHIP_REV_ID_LSB)
++#define CHIP_REV_ID_SET(x) (((x) << CHIP_REV_ID_LSB) & CHIP_REV_ID_MASK)
++
++#define DERIVED_RTC_CLK_ADDRESS 0x0c0000f4
++#define DERIVED_RTC_CLK_OFFSET 0x000000f4
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
++#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
++#define DERIVED_RTC_CLK_FORCE_MSB 17
++#define DERIVED_RTC_CLK_FORCE_LSB 16
++#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000
++#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
++#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
++#define DERIVED_RTC_CLK_PERIOD_MSB 15
++#define DERIVED_RTC_CLK_PERIOD_LSB 1
++#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
++#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
++#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
++
++#define ACG_DISABLE_ADDRESS 0x0c0000f8
++#define ACG_DISABLE_OFFSET 0x000000f8
++#define ACG_DISABLE_CPU_MSB 3
++#define ACG_DISABLE_CPU_LSB 3
++#define ACG_DISABLE_CPU_MASK 0x00000008
++#define ACG_DISABLE_CPU_GET(x) (((x) & ACG_DISABLE_CPU_MASK) >> ACG_DISABLE_CPU_LSB)
++#define ACG_DISABLE_CPU_SET(x) (((x) << ACG_DISABLE_CPU_LSB) & ACG_DISABLE_CPU_MASK)
++#define ACG_DISABLE_SDIO_MSB 2
++#define ACG_DISABLE_SDIO_LSB 2
++#define ACG_DISABLE_SDIO_MASK 0x00000004
++#define ACG_DISABLE_SDIO_GET(x) (((x) & ACG_DISABLE_SDIO_MASK) >> ACG_DISABLE_SDIO_LSB)
++#define ACG_DISABLE_SDIO_SET(x) (((x) << ACG_DISABLE_SDIO_LSB) & ACG_DISABLE_SDIO_MASK)
++#define ACG_DISABLE_BB_AND_BBB_MSB 1
++#define ACG_DISABLE_BB_AND_BBB_LSB 1
++#define ACG_DISABLE_BB_AND_BBB_MASK 0x00000002
++#define ACG_DISABLE_BB_AND_BBB_GET(x) (((x) & ACG_DISABLE_BB_AND_BBB_MASK) >> ACG_DISABLE_BB_AND_BBB_LSB)
++#define ACG_DISABLE_BB_AND_BBB_SET(x) (((x) << ACG_DISABLE_BB_AND_BBB_LSB) & ACG_DISABLE_BB_AND_BBB_MASK)
++#define ACG_DISABLE_AMBA_MAC_MSB 0
++#define ACG_DISABLE_AMBA_MAC_LSB 0
++#define ACG_DISABLE_AMBA_MAC_MASK 0x00000001
++#define ACG_DISABLE_AMBA_MAC_GET(x) (((x) & ACG_DISABLE_AMBA_MAC_MASK) >> ACG_DISABLE_AMBA_MAC_LSB)
++#define ACG_DISABLE_AMBA_MAC_SET(x) (((x) << ACG_DISABLE_AMBA_MAC_LSB) & ACG_DISABLE_AMBA_MAC_MASK)
++
++#define KEY_ENABLE_ADDRESS 0x0c0000fc
++#define KEY_ENABLE_OFFSET 0x000000fc
++#define KEY_ENABLE_ON_MSB 0
++#define KEY_ENABLE_ON_LSB 0
++#define KEY_ENABLE_ON_MASK 0x00000001
++#define KEY_ENABLE_ON_GET(x) (((x) & KEY_ENABLE_ON_MASK) >> KEY_ENABLE_ON_LSB)
++#define KEY_ENABLE_ON_SET(x) (((x) << KEY_ENABLE_ON_LSB) & KEY_ENABLE_ON_MASK)
++
++#define KEY_DEBOUNCE_ADDRESS 0x0c000100
++#define KEY_DEBOUNCE_OFFSET 0x00000100
++#define KEY_DEBOUNCE_TIME_MSB 3
++#define KEY_DEBOUNCE_TIME_LSB 0
++#define KEY_DEBOUNCE_TIME_MASK 0x0000000f
++#define KEY_DEBOUNCE_TIME_GET(x) (((x) & KEY_DEBOUNCE_TIME_MASK) >> KEY_DEBOUNCE_TIME_LSB)
++#define KEY_DEBOUNCE_TIME_SET(x) (((x) << KEY_DEBOUNCE_TIME_LSB) & KEY_DEBOUNCE_TIME_MASK)
++
++#define KEY_LONG_PRESS_ADDRESS 0x0c000104
++#define KEY_LONG_PRESS_OFFSET 0x00000104
++#define KEY_LONG_PRESS_TIME_MSB 5
++#define KEY_LONG_PRESS_TIME_LSB 0
++#define KEY_LONG_PRESS_TIME_MASK 0x0000003f
++#define KEY_LONG_PRESS_TIME_GET(x) (((x) & KEY_LONG_PRESS_TIME_MASK) >> KEY_LONG_PRESS_TIME_LSB)
++#define KEY_LONG_PRESS_TIME_SET(x) (((x) << KEY_LONG_PRESS_TIME_LSB) & KEY_LONG_PRESS_TIME_MASK)
++
++#define KEY_REPEAT_ADDRESS 0x0c000108
++#define KEY_REPEAT_OFFSET 0x00000108
++#define KEY_REPEAT_TIME_MSB 5
++#define KEY_REPEAT_TIME_LSB 0
++#define KEY_REPEAT_TIME_MASK 0x0000003f
++#define KEY_REPEAT_TIME_GET(x) (((x) & KEY_REPEAT_TIME_MASK) >> KEY_REPEAT_TIME_LSB)
++#define KEY_REPEAT_TIME_SET(x) (((x) << KEY_REPEAT_TIME_LSB) & KEY_REPEAT_TIME_MASK)
++
++#define KEY_MATRIX_LO_ADDRESS 0x0c00010c
++#define KEY_MATRIX_LO_OFFSET 0x0000010c
++#define KEY_MATRIX_LO_ROW0_MSB 31
++#define KEY_MATRIX_LO_ROW0_LSB 24
++#define KEY_MATRIX_LO_ROW0_MASK 0xff000000
++#define KEY_MATRIX_LO_ROW0_GET(x) (((x) & KEY_MATRIX_LO_ROW0_MASK) >> KEY_MATRIX_LO_ROW0_LSB)
++#define KEY_MATRIX_LO_ROW0_SET(x) (((x) << KEY_MATRIX_LO_ROW0_LSB) & KEY_MATRIX_LO_ROW0_MASK)
++#define KEY_MATRIX_LO_ROW1_MSB 23
++#define KEY_MATRIX_LO_ROW1_LSB 16
++#define KEY_MATRIX_LO_ROW1_MASK 0x00ff0000
++#define KEY_MATRIX_LO_ROW1_GET(x) (((x) & KEY_MATRIX_LO_ROW1_MASK) >> KEY_MATRIX_LO_ROW1_LSB)
++#define KEY_MATRIX_LO_ROW1_SET(x) (((x) << KEY_MATRIX_LO_ROW1_LSB) & KEY_MATRIX_LO_ROW1_MASK)
++#define KEY_MATRIX_LO_ROW2_MSB 15
++#define KEY_MATRIX_LO_ROW2_LSB 8
++#define KEY_MATRIX_LO_ROW2_MASK 0x0000ff00
++#define KEY_MATRIX_LO_ROW2_GET(x) (((x) & KEY_MATRIX_LO_ROW2_MASK) >> KEY_MATRIX_LO_ROW2_LSB)
++#define KEY_MATRIX_LO_ROW2_SET(x) (((x) << KEY_MATRIX_LO_ROW2_LSB) & KEY_MATRIX_LO_ROW2_MASK)
++#define KEY_MATRIX_LO_ROW3_MSB 7
++#define KEY_MATRIX_LO_ROW3_LSB 0
++#define KEY_MATRIX_LO_ROW3_MASK 0x000000ff
++#define KEY_MATRIX_LO_ROW3_GET(x) (((x) & KEY_MATRIX_LO_ROW3_MASK) >> KEY_MATRIX_LO_ROW3_LSB)
++#define KEY_MATRIX_LO_ROW3_SET(x) (((x) << KEY_MATRIX_LO_ROW3_LSB) & KEY_MATRIX_LO_ROW3_MASK)
++
++#define KEY_MATRIX_HI_ADDRESS 0x0c000110
++#define KEY_MATRIX_HI_OFFSET 0x00000110
++#define KEY_MATRIX_HI_ROW4_MSB 31
++#define KEY_MATRIX_HI_ROW4_LSB 24
++#define KEY_MATRIX_HI_ROW4_MASK 0xff000000
++#define KEY_MATRIX_HI_ROW4_GET(x) (((x) & KEY_MATRIX_HI_ROW4_MASK) >> KEY_MATRIX_HI_ROW4_LSB)
++#define KEY_MATRIX_HI_ROW4_SET(x) (((x) << KEY_MATRIX_HI_ROW4_LSB) & KEY_MATRIX_HI_ROW4_MASK)
++#define KEY_MATRIX_HI_ROW5_MSB 23
++#define KEY_MATRIX_HI_ROW5_LSB 16
++#define KEY_MATRIX_HI_ROW5_MASK 0x00ff0000
++#define KEY_MATRIX_HI_ROW5_GET(x) (((x) & KEY_MATRIX_HI_ROW5_MASK) >> KEY_MATRIX_HI_ROW5_LSB)
++#define KEY_MATRIX_HI_ROW5_SET(x) (((x) << KEY_MATRIX_HI_ROW5_LSB) & KEY_MATRIX_HI_ROW5_MASK)
++#define KEY_MATRIX_HI_ROW6_MSB 15
++#define KEY_MATRIX_HI_ROW6_LSB 8
++#define KEY_MATRIX_HI_ROW6_MASK 0x0000ff00
++#define KEY_MATRIX_HI_ROW6_GET(x) (((x) & KEY_MATRIX_HI_ROW6_MASK) >> KEY_MATRIX_HI_ROW6_LSB)
++#define KEY_MATRIX_HI_ROW6_SET(x) (((x) << KEY_MATRIX_HI_ROW6_LSB) & KEY_MATRIX_HI_ROW6_MASK)
++#define KEY_MATRIX_HI_ROW7_MSB 7
++#define KEY_MATRIX_HI_ROW7_LSB 0
++#define KEY_MATRIX_HI_ROW7_MASK 0x000000ff
++#define KEY_MATRIX_HI_ROW7_GET(x) (((x) & KEY_MATRIX_HI_ROW7_MASK) >> KEY_MATRIX_HI_ROW7_LSB)
++#define KEY_MATRIX_HI_ROW7_SET(x) (((x) << KEY_MATRIX_HI_ROW7_LSB) & KEY_MATRIX_HI_ROW7_MASK)
++
++#define KEY_CODE_ADDRESS 0x0c000114
++#define KEY_CODE_OFFSET 0x00000114
++#define KEY_CODE_MULTIPRESS_MSB 7
++#define KEY_CODE_MULTIPRESS_LSB 7
++#define KEY_CODE_MULTIPRESS_MASK 0x00000080
++#define KEY_CODE_MULTIPRESS_GET(x) (((x) & KEY_CODE_MULTIPRESS_MASK) >> KEY_CODE_MULTIPRESS_LSB)
++#define KEY_CODE_MULTIPRESS_SET(x) (((x) << KEY_CODE_MULTIPRESS_LSB) & KEY_CODE_MULTIPRESS_MASK)
++#define KEY_CODE_ROW_MSB 6
++#define KEY_CODE_ROW_LSB 4
++#define KEY_CODE_ROW_MASK 0x00000070
++#define KEY_CODE_ROW_GET(x) (((x) & KEY_CODE_ROW_MASK) >> KEY_CODE_ROW_LSB)
++#define KEY_CODE_ROW_SET(x) (((x) << KEY_CODE_ROW_LSB) & KEY_CODE_ROW_MASK)
++#define KEY_CODE_COL_MSB 2
++#define KEY_CODE_COL_LSB 0
++#define KEY_CODE_COL_MASK 0x00000007
++#define KEY_CODE_COL_GET(x) (((x) & KEY_CODE_COL_MASK) >> KEY_CODE_COL_LSB)
++#define KEY_CODE_COL_SET(x) (((x) << KEY_CODE_COL_LSB) & KEY_CODE_COL_MASK)
++
++#define KEY_STATUS_ADDRESS 0x0c000118
++#define KEY_STATUS_OFFSET 0x00000118
++#define KEY_STATUS_KEY_RELEASE_ENABLE_MSB 7
++#define KEY_STATUS_KEY_RELEASE_ENABLE_LSB 7
++#define KEY_STATUS_KEY_RELEASE_ENABLE_MASK 0x00000080
++#define KEY_STATUS_KEY_RELEASE_ENABLE_GET(x) (((x) & KEY_STATUS_KEY_RELEASE_ENABLE_MASK) >> KEY_STATUS_KEY_RELEASE_ENABLE_LSB)
++#define KEY_STATUS_KEY_RELEASE_ENABLE_SET(x) (((x) << KEY_STATUS_KEY_RELEASE_ENABLE_LSB) & KEY_STATUS_KEY_RELEASE_ENABLE_MASK)
++#define KEY_STATUS_FIRST_PRESS_ENABLE_MSB 6
++#define KEY_STATUS_FIRST_PRESS_ENABLE_LSB 6
++#define KEY_STATUS_FIRST_PRESS_ENABLE_MASK 0x00000040
++#define KEY_STATUS_FIRST_PRESS_ENABLE_GET(x) (((x) & KEY_STATUS_FIRST_PRESS_ENABLE_MASK) >> KEY_STATUS_FIRST_PRESS_ENABLE_LSB)
++#define KEY_STATUS_FIRST_PRESS_ENABLE_SET(x) (((x) << KEY_STATUS_FIRST_PRESS_ENABLE_LSB) & KEY_STATUS_FIRST_PRESS_ENABLE_MASK)
++#define KEY_STATUS_LONG_PRESS_ENABLE_MSB 5
++#define KEY_STATUS_LONG_PRESS_ENABLE_LSB 5
++#define KEY_STATUS_LONG_PRESS_ENABLE_MASK 0x00000020
++#define KEY_STATUS_LONG_PRESS_ENABLE_GET(x) (((x) & KEY_STATUS_LONG_PRESS_ENABLE_MASK) >> KEY_STATUS_LONG_PRESS_ENABLE_LSB)
++#define KEY_STATUS_LONG_PRESS_ENABLE_SET(x) (((x) << KEY_STATUS_LONG_PRESS_ENABLE_LSB) & KEY_STATUS_LONG_PRESS_ENABLE_MASK)
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_MSB 4
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_LSB 4
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_MASK 0x00000010
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_GET(x) (((x) & KEY_STATUS_REPEAT_PRESS_ENABLE_MASK) >> KEY_STATUS_REPEAT_PRESS_ENABLE_LSB)
++#define KEY_STATUS_REPEAT_PRESS_ENABLE_SET(x) (((x) << KEY_STATUS_REPEAT_PRESS_ENABLE_LSB) & KEY_STATUS_REPEAT_PRESS_ENABLE_MASK)
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_MSB 3
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB 3
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK 0x00000008
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_GET(x) (((x) & KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK) >> KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB)
++#define KEY_STATUS_KEY_RELEASE_INTERRUPT_SET(x) (((x) << KEY_STATUS_KEY_RELEASE_INTERRUPT_LSB) & KEY_STATUS_KEY_RELEASE_INTERRUPT_MASK)
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_MSB 2
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB 2
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK 0x00000004
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_GET(x) (((x) & KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK) >> KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_FIRST_PRESS_INTERRUPT_SET(x) (((x) << KEY_STATUS_FIRST_PRESS_INTERRUPT_LSB) & KEY_STATUS_FIRST_PRESS_INTERRUPT_MASK)
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_MSB 1
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_LSB 1
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_MASK 0x00000002
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_GET(x) (((x) & KEY_STATUS_LONG_PRESS_INTERRUPT_MASK) >> KEY_STATUS_LONG_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_LONG_PRESS_INTERRUPT_SET(x) (((x) << KEY_STATUS_LONG_PRESS_INTERRUPT_LSB) & KEY_STATUS_LONG_PRESS_INTERRUPT_MASK)
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_MSB 0
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB 0
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK 0x00000001
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_GET(x) (((x) & KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK) >> KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB)
++#define KEY_STATUS_REPEAT_PRESS_INTERRUPT_SET(x) (((x) << KEY_STATUS_REPEAT_PRESS_INTERRUPT_LSB) & KEY_STATUS_REPEAT_PRESS_INTERRUPT_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct rtc_reg_s {
++ volatile unsigned int reset_control;
++ volatile unsigned int xtal_control;
++ volatile unsigned int tcxo_detect;
++ volatile unsigned int xtal_test;
++ volatile unsigned int quadrature;
++ volatile unsigned int pll_control;
++ volatile unsigned int pll_settle;
++ volatile unsigned int xtal_settle;
++ volatile unsigned int core_clock;
++ volatile unsigned int cpu_clock;
++ volatile unsigned int clock_out;
++ volatile unsigned int clock_control;
++ volatile unsigned int bias_override;
++ volatile unsigned int ref_voltage_trim;
++ volatile unsigned int ldo_control;
++ volatile unsigned int wdt_control;
++ volatile unsigned int wdt_status;
++ volatile unsigned int wdt;
++ volatile unsigned int wdt_count;
++ volatile unsigned int wdt_reset;
++ volatile unsigned int int_status;
++ volatile unsigned int lf_timer0;
++ volatile unsigned int lf_timer_count0;
++ volatile unsigned int lf_timer_control0;
++ volatile unsigned int lf_timer_status0;
++ volatile unsigned int lf_timer1;
++ volatile unsigned int lf_timer_count1;
++ volatile unsigned int lf_timer_control1;
++ volatile unsigned int lf_timer_status1;
++ volatile unsigned int lf_timer2;
++ volatile unsigned int lf_timer_count2;
++ volatile unsigned int lf_timer_control2;
++ volatile unsigned int lf_timer_status2;
++ volatile unsigned int lf_timer3;
++ volatile unsigned int lf_timer_count3;
++ volatile unsigned int lf_timer_control3;
++ volatile unsigned int lf_timer_status3;
++ volatile unsigned int hf_timer;
++ volatile unsigned int hf_timer_count;
++ volatile unsigned int hf_lf_count;
++ volatile unsigned int hf_timer_control;
++ volatile unsigned int hf_timer_status;
++ volatile unsigned int rtc_control;
++ volatile unsigned int rtc_time;
++ volatile unsigned int rtc_date;
++ volatile unsigned int rtc_set_time;
++ volatile unsigned int rtc_set_date;
++ volatile unsigned int rtc_set_alarm;
++ volatile unsigned int rtc_config;
++ volatile unsigned int rtc_alarm_status;
++ volatile unsigned int uart_wakeup;
++ volatile unsigned int reset_cause;
++ volatile unsigned int system_sleep;
++ volatile unsigned int ldo_voltage;
++ volatile unsigned int ldo_a_voltage;
++ volatile unsigned int sdio_ldo_voltage;
++ volatile unsigned int core_pad_enable;
++ volatile unsigned int sdio_wrapper;
++ volatile unsigned int mac_sleep_control;
++ volatile unsigned int keep_awake;
++ volatile unsigned int chip_rev;
++ volatile unsigned int derived_rtc_clk;
++ volatile unsigned int acg_disable;
++ volatile unsigned int key_enable;
++ volatile unsigned int key_debounce;
++ volatile unsigned int key_long_press;
++ volatile unsigned int key_repeat;
++ volatile unsigned int key_matrix_lo;
++ volatile unsigned int key_matrix_hi;
++ volatile unsigned int key_code;
++ volatile unsigned int key_status;
++} rtc_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _RTC_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athdefs.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/athdefs.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,82 @@
++
++#ifndef __ATHDEFS_H__
++#define __ATHDEFS_H__
++
++/*
++ * This file contains definitions that may be used across both
++ * Host and Target software. Nothing here is module-dependent
++ * or platform-dependent.
++ */
++
++/*
++ * Generic error codes that can be used by hw, sta, ap, sim, dk
++ * and any other environments. Since these are enums, feel free to
++ * add any more codes that you need.
++ */
++
++typedef enum {
++ A_ERROR = -1, /* Generic error return */
++ A_OK = 0, /* success */
++ /* Following values start at 1 */
++ A_DEVICE_NOT_FOUND, /* not able to find PCI device */
++ A_NO_MEMORY, /* not able to allocate memory, not available */
++ A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
++ A_NO_FREE_DESC, /* no free descriptors available */
++ A_BAD_ADDRESS, /* address does not match descriptor */
++ A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
++ A_REGS_NOT_MAPPED, /* registers not correctly mapped */
++ A_EPERM, /* Not superuser */
++ A_EACCES, /* Access denied */
++ A_ENOENT, /* No such entry, search failed, etc. */
++ A_EEXIST, /* The object already exists (can't create) */
++ A_EFAULT, /* Bad address fault */
++ A_EBUSY, /* Object is busy */
++ A_EINVAL, /* Invalid parameter */
++ A_EMSGSIZE, /* Inappropriate message buffer length */
++ A_ECANCELED, /* Operation canceled */
++ A_ENOTSUP, /* Operation not supported */
++ A_ECOMM, /* Communication error on send */
++ A_EPROTO, /* Protocol error */
++ A_ENODEV, /* No such device */
++ A_EDEVNOTUP, /* device is not UP */
++ A_NO_RESOURCE, /* No resources for requested operation */
++ A_HARDWARE, /* Hardware failure */
++ A_PENDING, /* Asynchronous routine; will send up results la
++ter (typically in callback) */
++ A_EBADCHANNEL, /* The channel cannot be used */
++ A_DECRYPT_ERROR, /* Decryption error */
++ A_PHY_ERROR, /* RX PHY error */
++ A_CONSUMED /* Object was consumed */
++} A_STATUS;
++
++#define A_SUCCESS(x) (x == A_OK)
++#define A_FAILED(x) (!A_SUCCESS(x))
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++/*
++ * The following definition is WLAN specific definition
++ */
++typedef enum {
++ MODE_11A = 0, /* 11a Mode */
++ MODE_11G = 1, /* 11g + 11b Mode */
++ MODE_11B = 2, /* 11b Mode */
++ MODE_11GONLY = 3, /* 11g only Mode */
++ MODE_UNKNOWN = 4,
++
++ MODE_MAX = 4
++} WLAN_PHY_MODE;
++
++typedef enum {
++ WLAN_11A_CAPABILITY = 1,
++ WLAN_11G_CAPABILITY = 2,
++ WLAN_11AG_CAPABILITY = 3,
++}WALN_CAPABILITY;
++
++#endif /* __ATHDEFS_H__ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mbox_host_reg.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/hw/mbox_host_reg.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,416 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++#ifndef _MBOX_HOST_REG_REG_H_
++#define _MBOX_HOST_REG_REG_H_
++
++#define HOST_INT_STATUS_ADDRESS 0x00000400
++#define HOST_INT_STATUS_OFFSET 0x00000400
++#define HOST_INT_STATUS_ERROR_MSB 7
++#define HOST_INT_STATUS_ERROR_LSB 7
++#define HOST_INT_STATUS_ERROR_MASK 0x00000080
++#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
++#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
++#define HOST_INT_STATUS_CPU_MSB 6
++#define HOST_INT_STATUS_CPU_LSB 6
++#define HOST_INT_STATUS_CPU_MASK 0x00000040
++#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
++#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
++#define HOST_INT_STATUS_DRAGON_INT_MSB 5
++#define HOST_INT_STATUS_DRAGON_INT_LSB 5
++#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
++#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
++#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
++#define HOST_INT_STATUS_COUNTER_MSB 4
++#define HOST_INT_STATUS_COUNTER_LSB 4
++#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
++#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
++#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
++#define HOST_INT_STATUS_MBOX_DATA_MSB 3
++#define HOST_INT_STATUS_MBOX_DATA_LSB 0
++#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
++#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
++#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ADDRESS 0x00000401
++#define CPU_INT_STATUS_OFFSET 0x00000401
++#define CPU_INT_STATUS_BIT_MSB 7
++#define CPU_INT_STATUS_BIT_LSB 0
++#define CPU_INT_STATUS_BIT_MASK 0x000000ff
++#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
++#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
++
++#define ERROR_INT_STATUS_ADDRESS 0x00000402
++#define ERROR_INT_STATUS_OFFSET 0x00000402
++#define ERROR_INT_STATUS_SPI_MSB 3
++#define ERROR_INT_STATUS_SPI_LSB 3
++#define ERROR_INT_STATUS_SPI_MASK 0x00000008
++#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
++#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
++#define ERROR_INT_STATUS_WAKEUP_MSB 2
++#define ERROR_INT_STATUS_WAKEUP_LSB 2
++#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
++#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
++#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
++#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
++#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
++#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
++#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
++#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
++#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
++#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
++#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ADDRESS 0x00000403
++#define COUNTER_INT_STATUS_OFFSET 0x00000403
++#define COUNTER_INT_STATUS_COUNTER_MSB 7
++#define COUNTER_INT_STATUS_COUNTER_LSB 0
++#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
++#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
++#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
++
++#define MBOX_FRAME_ADDRESS 0x00000404
++#define MBOX_FRAME_OFFSET 0x00000404
++#define MBOX_FRAME_RX_EOM_MSB 7
++#define MBOX_FRAME_RX_EOM_LSB 4
++#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
++#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
++#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
++#define MBOX_FRAME_RX_SOM_MSB 3
++#define MBOX_FRAME_RX_SOM_LSB 0
++#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
++#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
++#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
++
++#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
++#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
++#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
++#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
++#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
++#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
++#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
++
++#define RX_LOOKAHEAD0_ADDRESS 0x00000408
++#define RX_LOOKAHEAD0_OFFSET 0x00000408
++#define RX_LOOKAHEAD0_DATA_MSB 7
++#define RX_LOOKAHEAD0_DATA_LSB 0
++#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
++#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
++#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
++
++#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
++#define RX_LOOKAHEAD1_OFFSET 0x0000040c
++#define RX_LOOKAHEAD1_DATA_MSB 7
++#define RX_LOOKAHEAD1_DATA_LSB 0
++#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
++#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
++#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
++
++#define RX_LOOKAHEAD2_ADDRESS 0x00000410
++#define RX_LOOKAHEAD2_OFFSET 0x00000410
++#define RX_LOOKAHEAD2_DATA_MSB 7
++#define RX_LOOKAHEAD2_DATA_LSB 0
++#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
++#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
++#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
++
++#define RX_LOOKAHEAD3_ADDRESS 0x00000414
++#define RX_LOOKAHEAD3_OFFSET 0x00000414
++#define RX_LOOKAHEAD3_DATA_MSB 7
++#define RX_LOOKAHEAD3_DATA_LSB 0
++#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
++#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
++#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
++
++#define INT_STATUS_ENABLE_ADDRESS 0x00000418
++#define INT_STATUS_ENABLE_OFFSET 0x00000418
++#define INT_STATUS_ENABLE_ERROR_MSB 7
++#define INT_STATUS_ENABLE_ERROR_LSB 7
++#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
++#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
++#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
++#define INT_STATUS_ENABLE_CPU_MSB 6
++#define INT_STATUS_ENABLE_CPU_LSB 6
++#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
++#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
++#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
++#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
++#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
++#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
++#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
++#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
++#define INT_STATUS_ENABLE_COUNTER_MSB 4
++#define INT_STATUS_ENABLE_COUNTER_LSB 4
++#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
++#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
++#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
++#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
++#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
++#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
++#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
++#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
++
++#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
++#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
++#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
++#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
++#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
++#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
++#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
++
++#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
++#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
++#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
++#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
++#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
++#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
++#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
++#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
++
++#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
++#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
++#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
++#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
++#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
++#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
++
++#define COUNT_ADDRESS 0x00000420
++#define COUNT_OFFSET 0x00000420
++#define COUNT_VALUE_MSB 7
++#define COUNT_VALUE_LSB 0
++#define COUNT_VALUE_MASK 0x000000ff
++#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
++#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
++
++#define COUNT_DEC_ADDRESS 0x00000440
++#define COUNT_DEC_OFFSET 0x00000440
++#define COUNT_DEC_VALUE_MSB 7
++#define COUNT_DEC_VALUE_LSB 0
++#define COUNT_DEC_VALUE_MASK 0x000000ff
++#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
++#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
++
++#define SCRATCH_ADDRESS 0x00000460
++#define SCRATCH_OFFSET 0x00000460
++#define SCRATCH_VALUE_MSB 7
++#define SCRATCH_VALUE_LSB 0
++#define SCRATCH_VALUE_MASK 0x000000ff
++#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
++#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ADDRESS 0x00000468
++#define FIFO_TIMEOUT_OFFSET 0x00000468
++#define FIFO_TIMEOUT_VALUE_MSB 7
++#define FIFO_TIMEOUT_VALUE_LSB 0
++#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
++#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
++#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
++
++#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
++#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
++#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
++#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
++#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
++#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
++#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
++
++#define DISABLE_SLEEP_ADDRESS 0x0000046a
++#define DISABLE_SLEEP_OFFSET 0x0000046a
++#define DISABLE_SLEEP_FOR_INT_MSB 1
++#define DISABLE_SLEEP_FOR_INT_LSB 1
++#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
++#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
++#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
++#define DISABLE_SLEEP_ON_MSB 0
++#define DISABLE_SLEEP_ON_LSB 0
++#define DISABLE_SLEEP_ON_MASK 0x00000001
++#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
++#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
++
++#define LOCAL_BUS_ENDIAN_ADDRESS 0x0000046e
++#define LOCAL_BUS_ENDIAN_OFFSET 0x0000046e
++#define LOCAL_BUS_ENDIAN_BIG_MSB 0
++#define LOCAL_BUS_ENDIAN_BIG_LSB 0
++#define LOCAL_BUS_ENDIAN_BIG_MASK 0x00000001
++#define LOCAL_BUS_ENDIAN_BIG_GET(x) (((x) & LOCAL_BUS_ENDIAN_BIG_MASK) >> LOCAL_BUS_ENDIAN_BIG_LSB)
++#define LOCAL_BUS_ENDIAN_BIG_SET(x) (((x) << LOCAL_BUS_ENDIAN_BIG_LSB) & LOCAL_BUS_ENDIAN_BIG_MASK)
++
++#define LOCAL_BUS_ADDRESS 0x00000470
++#define LOCAL_BUS_OFFSET 0x00000470
++#define LOCAL_BUS_SOFT_RESET_MSB 4
++#define LOCAL_BUS_SOFT_RESET_LSB 4
++#define LOCAL_BUS_SOFT_RESET_MASK 0x00000010
++#define LOCAL_BUS_SOFT_RESET_GET(x) (((x) & LOCAL_BUS_SOFT_RESET_MASK) >> LOCAL_BUS_SOFT_RESET_LSB)
++#define LOCAL_BUS_SOFT_RESET_SET(x) (((x) << LOCAL_BUS_SOFT_RESET_LSB) & LOCAL_BUS_SOFT_RESET_MASK)
++#define LOCAL_BUS_IO_ENABLE_MSB 3
++#define LOCAL_BUS_IO_ENABLE_LSB 3
++#define LOCAL_BUS_IO_ENABLE_MASK 0x00000008
++#define LOCAL_BUS_IO_ENABLE_GET(x) (((x) & LOCAL_BUS_IO_ENABLE_MASK) >> LOCAL_BUS_IO_ENABLE_LSB)
++#define LOCAL_BUS_IO_ENABLE_SET(x) (((x) << LOCAL_BUS_IO_ENABLE_LSB) & LOCAL_BUS_IO_ENABLE_MASK)
++#define LOCAL_BUS_KEEP_AWAKE_MSB 2
++#define LOCAL_BUS_KEEP_AWAKE_LSB 2
++#define LOCAL_BUS_KEEP_AWAKE_MASK 0x00000004
++#define LOCAL_BUS_KEEP_AWAKE_GET(x) (((x) & LOCAL_BUS_KEEP_AWAKE_MASK) >> LOCAL_BUS_KEEP_AWAKE_LSB)
++#define LOCAL_BUS_KEEP_AWAKE_SET(x) (((x) << LOCAL_BUS_KEEP_AWAKE_LSB) & LOCAL_BUS_KEEP_AWAKE_MASK)
++#define LOCAL_BUS_STATE_MSB 1
++#define LOCAL_BUS_STATE_LSB 0
++#define LOCAL_BUS_STATE_MASK 0x00000003
++#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
++#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
++
++#define INT_WLAN_ADDRESS 0x00000472
++#define INT_WLAN_OFFSET 0x00000472
++#define INT_WLAN_VECTOR_MSB 7
++#define INT_WLAN_VECTOR_LSB 0
++#define INT_WLAN_VECTOR_MASK 0x000000ff
++#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
++#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
++
++#define WINDOW_DATA_ADDRESS 0x00000474
++#define WINDOW_DATA_OFFSET 0x00000474
++#define WINDOW_DATA_DATA_MSB 7
++#define WINDOW_DATA_DATA_LSB 0
++#define WINDOW_DATA_DATA_MASK 0x000000ff
++#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
++#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
++
++#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
++#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
++#define WINDOW_WRITE_ADDR_ADDR_MSB 7
++#define WINDOW_WRITE_ADDR_ADDR_LSB 0
++#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
++#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
++#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
++
++#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
++#define WINDOW_READ_ADDR_OFFSET 0x0000047c
++#define WINDOW_READ_ADDR_ADDR_MSB 7
++#define WINDOW_READ_ADDR_ADDR_LSB 0
++#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
++#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
++#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
++
++#define SPI_CONFIG_ADDRESS 0x00000480
++#define SPI_CONFIG_OFFSET 0x00000480
++#define SPI_CONFIG_SPI_RESET_MSB 4
++#define SPI_CONFIG_SPI_RESET_LSB 4
++#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
++#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
++#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
++#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
++#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
++#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
++#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
++#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
++#define SPI_CONFIG_TEST_MODE_MSB 2
++#define SPI_CONFIG_TEST_MODE_LSB 2
++#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
++#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
++#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
++#define SPI_CONFIG_DATA_SIZE_MSB 1
++#define SPI_CONFIG_DATA_SIZE_LSB 0
++#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
++#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
++#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
++
++#define SPI_STATUS_ADDRESS 0x00000481
++#define SPI_STATUS_OFFSET 0x00000481
++#define SPI_STATUS_ADDR_ERR_MSB 3
++#define SPI_STATUS_ADDR_ERR_LSB 3
++#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
++#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
++#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
++#define SPI_STATUS_RD_ERR_MSB 2
++#define SPI_STATUS_RD_ERR_LSB 2
++#define SPI_STATUS_RD_ERR_MASK 0x00000004
++#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
++#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
++#define SPI_STATUS_WR_ERR_MSB 1
++#define SPI_STATUS_WR_ERR_LSB 1
++#define SPI_STATUS_WR_ERR_MASK 0x00000002
++#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
++#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
++#define SPI_STATUS_READY_MSB 0
++#define SPI_STATUS_READY_LSB 0
++#define SPI_STATUS_READY_MASK 0x00000001
++#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
++#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
++
++#define CIS_WINDOW_ADDRESS 0x00000600
++#define CIS_WINDOW_OFFSET 0x00000600
++#define CIS_WINDOW_DATA_MSB 7
++#define CIS_WINDOW_DATA_LSB 0
++#define CIS_WINDOW_DATA_MASK 0x000000ff
++#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
++#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
++
++#ifndef __ASSEMBLER__
++typedef struct mbox_host_reg_reg_s {
++ unsigned char pad0[1024]; /* pad to 0x400 */
++ volatile unsigned char host_int_status;
++ volatile unsigned char cpu_int_status;
++ volatile unsigned char error_int_status;
++ volatile unsigned char counter_int_status;
++ volatile unsigned char mbox_frame;
++ volatile unsigned char rx_lookahead_valid;
++ unsigned char pad1[2]; /* pad to 0x408 */
++ volatile unsigned char rx_lookahead0[4];
++ volatile unsigned char rx_lookahead1[4];
++ volatile unsigned char rx_lookahead2[4];
++ volatile unsigned char rx_lookahead3[4];
++ volatile unsigned char int_status_enable;
++ volatile unsigned char cpu_int_status_enable;
++ volatile unsigned char error_status_enable;
++ volatile unsigned char counter_int_status_enable;
++ unsigned char pad2[4]; /* pad to 0x420 */
++ volatile unsigned char count[8];
++ unsigned char pad3[24]; /* pad to 0x440 */
++ volatile unsigned char count_dec[32];
++ volatile unsigned char scratch[8];
++ volatile unsigned char fifo_timeout;
++ volatile unsigned char fifo_timeout_enable;
++ volatile unsigned char disable_sleep;
++ unsigned char pad4[3]; /* pad to 0x46e */
++ volatile unsigned char local_bus_endian;
++ unsigned char pad5[1]; /* pad to 0x470 */
++ volatile unsigned char local_bus;
++ unsigned char pad6[1]; /* pad to 0x472 */
++ volatile unsigned char int_wlan;
++ unsigned char pad7[1]; /* pad to 0x474 */
++ volatile unsigned char window_data[4];
++ volatile unsigned char window_write_addr[4];
++ volatile unsigned char window_read_addr[4];
++ volatile unsigned char spi_config;
++ volatile unsigned char spi_status;
++ unsigned char pad8[382]; /* pad to 0x600 */
++ volatile unsigned char cis_window[512];
++} mbox_host_reg_reg_t;
++#endif /* __ASSEMBLER__ */
++
++#endif /* _MBOX_HOST_REG_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_bmi.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_bmi.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,136 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++#ifndef __AR6000_BMI_H__
++#define __AR6000_BMI_H__
++
++/*
++ * Bootloader Messaging Interface (BMI)
++ *
++ * BMI is a very simple messaging interface used during initialization
++ * to read memory, write memory, execute code, and to define an
++ * application entry PC.
++ *
++ * It is used to download an application to AR6000, to provide
++ * patches to code that is already resident on AR6000, and generally
++ * to examine and modify state. The Host has an opportunity to use
++ * BMI only once during bootup. Once the Host issues a BMI_DONE
++ * command, this opportunity ends.
++ *
++ * The Host writes BMI requests to mailbox0, and reads BMI responses
++ * from mailbox0. BMI requests all begin with a command
++ * (see below for specific commands), and are followed by
++ * command-specific data.
++ *
++ * Flow control:
++ * The Host can only issue a command once the Target gives it a
++ * "BMI Command Credit", using AR6000 Counter #4. As soon as the
++ * Target has completed a command, it issues another BMI Command
++ * Credit (so the Host can issue the next command).
++ *
++ * BMI handles all required Target-side cache flushing.
++ */
++
++
++/* Maximum data size used for BMI transfers */
++#define BMI_DATASZ_MAX 32
++
++/* BMI Commands */
++
++#define BMI_NO_COMMAND 0
++
++#define BMI_DONE 1
++ /*
++ * Semantics: Host is done using BMI
++ * Request format:
++ * A_UINT32 command (BMI_DONE)
++ * Response format: none
++ */
++
++#define BMI_READ_MEMORY 2
++ /*
++ * Semantics: Host reads AR6000 memory
++ * Request format:
++ * A_UINT32 command (BMI_READ_MEMORY)
++ * A_UINT32 address
++ * A_UINT32 length, at most BMI_DATASZ_MAX
++ * Response format:
++ * A_UINT8 data[length]
++ */
++
++#define BMI_WRITE_MEMORY 3
++ /*
++ * Semantics: Host writes AR6000 memory
++ * Request format:
++ * A_UINT32 command (BMI_WRITE_MEMORY)
++ * A_UINT32 address
++ * A_UINT32 length, at most BMI_DATASZ_MAX
++ * A_UINT8 data[length]
++ * Response format: none
++ */
++
++#define BMI_EXECUTE 4
++ /*
++ * Semantics: Causes AR6000 to execute code
++ * Request format:
++ * A_UINT32 command (BMI_EXECUTE)
++ * A_UINT32 address
++ * A_UINT32 parameter
++ * Response format:
++ * A_UINT32 return value
++ */
++
++#define BMI_SET_APP_START 5
++ /*
++ * Semantics: Set Target application starting address
++ * Request format:
++ * A_UINT32 command (BMI_SET_APP_START)
++ * A_UINT32 address
++ * Response format: none
++ */
++
++#define BMI_READ_SOC_REGISTER 6
++ /*
++ * Semantics: Read a 32-bit Target SOC register.
++ * Request format:
++ * A_UINT32 command (BMI_READ_REGISTER)
++ * A_UINT32 address
++ * Response format:
++ * A_UINT32 value
++ */
++
++#define BMI_WRITE_SOC_REGISTER 7
++ /*
++ * Semantics: Write a 32-bit Target SOC register.
++ * Request format:
++ * A_UINT32 command (BMI_WRITE_REGISTER)
++ * A_UINT32 address
++ * A_UINT32 value
++ *
++ * Response format: none
++ */
++
++#define BMI_GET_TARGET_ID 8
++ /*
++ * Semantics: Fetch the 4-byte Target ID.
++ * Request format:
++ * A_UINT32 command (BMI_GET_TARGET_ID)
++ *
++ * Response format:
++ * A_UINT32 TargetID
++ */
++
++#endif /* __AR6000_BMI_H__ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_version.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_version.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,46 @@
++/*
++ * Copyright 2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++#define __VER_MAJOR_ 1
++#define __VER_MINOR_ 1
++#define __VER_PATCH_ 0
++
++
++/* The makear6ksdk script (used for release builds) modifies the following line. */
++#define __BUILD_NUMBER_ 2
++
++
++/* Format of the version number. */
++#define VER_MAJOR_BIT_OFFSET 28
++#define VER_MINOR_BIT_OFFSET 24
++#define VER_PATCH_BIT_OFFSET 16
++#define VER_BUILD_NUM_BIT_OFFSET 0
++
++
++/*
++ * The version has the following format:
++ * Bits 28-31: Major version
++ * Bits 24-27: Minor version
++ * Bits 16-23: Patch version
++ * Bits 0-15: Build number (automatically generated during build process )
++ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
++ *
++ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
++ */
++#define AR6000_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
++
++
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_gpio.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/AR6000_gpio.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,39 @@
++/*
++ * Copyright 2005-2006 Atheros Communications, Inc.
++ *
++ * Wireless Network driver for Atheros AR6001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ *
++ */
++
++#define GPIO_PIN_COUNT 18
++
++/*
++ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
++ * NB: These match hardware order, so that addresses can
++ * easily be computed.
++ */
++#define GPIO_ID_OUT 0x00000000
++#define GPIO_ID_OUT_W1TS 0x00000001
++#define GPIO_ID_OUT_W1TC 0x00000002
++#define GPIO_ID_ENABLE 0x00000003
++#define GPIO_ID_ENABLE_W1TS 0x00000004
++#define GPIO_ID_ENABLE_W1TC 0x00000005
++#define GPIO_ID_IN 0x00000006
++#define GPIO_ID_STATUS 0x00000007
++#define GPIO_ID_STATUS_W1TS 0x00000008
++#define GPIO_ID_STATUS_W1TC 0x00000009
++#define GPIO_ID_PIN0 0x0000000a
++#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
++
++#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
++#define GPIO_ID_NONE 0xffffffff
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/app/dset.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/app/dset.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,77 @@
++#ifndef _DSET_H_
++#define _DSET_H_
++
++/*
++ * Structures used to communicate between an application and the kernel for
++ * DataSet ioctls.
++ *
++ * Pass a dset_request_t with cmd=AR6000_XIOCTL_WMI_WAITDSETREQ in order to
++ * wait for the next DataSet Request to arrive. Once a request is received
++ * from the Target, the kernel fills in information about the Request and
++ * returns from the ioctl to the application. When the ioctl returns,
++ * cmd is set to either AR6000_OPEN_REQ or AR6000_DATA_REQ.
++ *
++ * Pass a dset_open_reply_t with cmd=AR6000_IOCTL_WMI_DSET_OPEN_REPLY in order
++ * to send a DataSet Open reply to the Target. The targ_* fields should simply
++ * be copied from the original Open Request. The status field should be set
++ * to 0 for success or non-zero for failure.
++ *
++ * Pass a dset_data_reply_t with cmd=AR6000_IOCTL_WMI_DSET_DATA_REPLY in order
++ * to send a DataSet Data reply to the Target. The targ_* fields should simply
++ * be copied from the original Data Request. The status field should be set
++ * to 0 for success or non-zero for failure. The buf field is a pointer
++ * to a buffer that contains the requested data.
++ */
++
++/* A DataSet Request, either Open Request or Data Request */
++typedef struct dset_request_s {
++ unsigned int cmd;
++ union {
++ struct open_req_s {
++ unsigned int id;
++ unsigned int targ_handle;
++ unsigned int targ_reply_fn;
++ unsigned int targ_reply_arg;
++ } open_req;
++ struct data_req_s {
++ unsigned int access_cookie;
++ unsigned int offset;
++ unsigned int length;
++ unsigned int targ_buf;
++ unsigned int targ_reply_fn;
++ unsigned int targ_reply_arg;
++ } data_req;
++ } u;
++} dset_request_t;
++
++/*
++ * Values in cmd on return from an AR6000_IOCTL_EXTENDED ioctl that had
++ * cmd=AR6000_XIOCTL_WMI_WAITDSETREQ.
++ */
++#define AR6000_OPEN_REQ 1
++#define AR6000_DATA_REQ 2
++
++/* Open Reply from Application to Kernel (to be sent to Target) */
++typedef struct dset_open_reply {
++ unsigned int cmd;
++ unsigned int status;
++ unsigned int targ_handle;
++ unsigned int targ_reply_fn;
++ unsigned int targ_reply_arg;
++ unsigned int access_cookie;
++ unsigned int size;
++ unsigned int version;
++} dset_open_reply_t;
++
++/* Data Reply from Application to Kernel (to be sent to Target) */
++typedef struct dset_data_reply {
++ unsigned int cmd;
++ unsigned int status;
++ char *buf;
++ unsigned int length;
++ unsigned int targ_buf;
++ unsigned int targ_reply_fn;
++ unsigned int targ_reply_arg;
++} dset_data_reply_t;
++
++#endif /* _DSET_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmi.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1141 @@
++/*
++ * Copyright (c) 2004-2006 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * This file contains the definitions of the WMI protocol specified in the
++ * Wireless Module Interface (WMI). It includes definitions of all the
++ * commands and events. Commands are messages from the host to the WM.
++ * Events and Replies are messages from the WM to the host.
++ *
++ * Ownership of correctness in regards to WMI commands
++ * belongs to the host driver and the WM is not required to validate
++ * parameters for value, proper range, or any other checking.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/include/wmi.h#1 $
++ *
++ */
++
++#ifndef _WMI_H_
++#define _WMI_H_
++
++#include "wmix.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define WMI_PROTOCOL_VERSION 0x0001
++#define WMI_PROTOCOL_REVISION 0x0000
++
++#define ATH_MAC_LEN 6 /* length of mac in bytes */
++#define WMI_CMD_MAX_LEN 100
++#define WMI_CONTROL_MSG_MAX_LEN 256
++#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
++#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
++#define RFC1042OUI {0x00, 0x00, 0x00}
++
++#define IP_ETHERTYPE 0x0800
++
++/*
++ * Data Path
++ */
++typedef struct {
++ A_UINT8 dstMac[ATH_MAC_LEN];
++ A_UINT8 srcMac[ATH_MAC_LEN];
++ A_UINT16 typeOrLen;
++} __ATTRIB_PACK ATH_MAC_HDR;
++
++typedef struct {
++ A_UINT8 dsap;
++ A_UINT8 ssap;
++ A_UINT8 cntl;
++ A_UINT8 orgCode[3];
++ A_UINT16 etherType;
++} __ATTRIB_PACK ATH_LLC_SNAP_HDR;
++
++typedef enum {
++ DATA_MSGTYPE = 0x0,
++ CNTL_MSGTYPE,
++ SYNC_MSGTYPE
++} WMI_MSG_TYPE;
++
++
++typedef struct {
++ A_INT8 rssi;
++ A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */
++ /* UP in next 3 bits - b4b3b2 */
++#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03
++#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
++#define WMI_DATA_HDR_UP_MASK 0x07
++#define WMI_DATA_HDR_UP_SHIFT 2
++#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
++} __ATTRIB_PACK WMI_DATA_HDR;
++
++/*
++ * Control Path
++ */
++typedef struct {
++ A_UINT16 commandId;
++} __ATTRIB_PACK WMI_CMD_HDR; /* used for commands and events */
++
++/*
++ * List of Commnands
++ */
++typedef enum {
++ WMI_CONNECT_CMDID = 0x0001,
++ WMI_RECONNECT_CMDID,
++ WMI_DISCONNECT_CMDID,
++ WMI_SYNCHRONIZE_CMDID,
++ WMI_CREATE_PSTREAM_CMDID,
++ WMI_DELETE_PSTREAM_CMDID,
++ WMI_START_SCAN_CMDID,
++ WMI_SET_SCAN_PARAMS_CMDID,
++ WMI_SET_BSS_FILTER_CMDID,
++ WMI_SET_PROBED_SSID_CMDID,
++ WMI_SET_LISTEN_INT_CMDID,
++ WMI_SET_BMISS_TIME_CMDID,
++ WMI_SET_DISC_TIMEOUT_CMDID,
++ WMI_GET_CHANNEL_LIST_CMDID,
++ WMI_SET_BEACON_INT_CMDID,
++ WMI_GET_STATISTICS_CMDID,
++ WMI_SET_CHANNEL_PARAMS_CMDID,
++ WMI_SET_POWER_MODE_CMDID,
++ WMI_SET_IBSS_PM_CAPS_CMDID,
++ WMI_SET_POWER_PARAMS_CMDID,
++ WMI_SET_POWERSAVE_TIMERS_CMDID,
++ WMI_ADD_CIPHER_KEY_CMDID,
++ WMI_DELETE_CIPHER_KEY_CMDID,
++ WMI_ADD_KRK_CMDID,
++ WMI_DELETE_KRK_CMDID,
++ WMI_SET_PMKID_CMDID,
++ WMI_SET_TX_PWR_CMDID,
++ WMI_GET_TX_PWR_CMDID,
++ WMI_SET_ASSOC_INFO_CMDID,
++ WMI_ADD_BAD_AP_CMDID,
++ WMI_DELETE_BAD_AP_CMDID,
++ WMI_SET_TKIP_COUNTERMEASURES_CMDID,
++ WMI_RSSI_THRESHOLD_PARAMS_CMDID,
++ WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
++ WMI_SET_ACCESS_PARAMS_CMDID,
++ WMI_SET_RETRY_LIMITS_CMDID,
++ WMI_SET_OPT_MODE_CMDID,
++ WMI_OPT_TX_FRAME_CMDID,
++ WMI_SET_VOICE_PKT_SIZE_CMDID,
++ WMI_SET_MAX_SP_LEN_CMDID,
++ WMI_SET_ROAM_CTRL_CMDID,
++ WMI_GET_ROAM_TBL_CMDID,
++ WMI_GET_ROAM_DATA_CMDID,
++ WMI_ENABLE_RM_CMDID,
++ WMI_SET_MAX_OFFHOME_DURATION_CMDID,
++ WMI_EXTENSION_CMDID, /* Non-wireless extensions */
++ WMI_SNR_THRESHOLD_PARAMS_CMDID,
++ WMI_LQ_THRESHOLD_PARAMS_CMDID,
++ WMI_SET_LPREAMBLE_CMDID,
++ WMI_SET_RTS_CMDID,
++ WMI_CLR_RSSI_SNR_CMDID,
++ WMI_SET_FIXRATES_CMDID,
++ WMI_GET_FIXRATES_CMDID,
++ WMI_SET_AUTH_MODE_CMDID,
++ /*
++ * Developer commands starts at 0xF000
++ */
++ WMI_SET_BITRATE_CMDID = 0xF000,
++ WMI_GET_BITRATE_CMDID,
++} WMI_COMMAND_ID;
++
++/*
++ * Connect Command
++ */
++typedef enum {
++ INFRA_NETWORK = 0x01,
++ ADHOC_NETWORK = 0x02,
++} NETWORK_TYPE;
++
++typedef enum {
++ OPEN_AUTH = 0x01,
++ SHARED_AUTH = 0x02,
++ LEAP_AUTH = 0x04,
++} DOT11_AUTH_MODE;
++
++typedef enum {
++ NONE_AUTH = 0x01,
++ WPA_AUTH = 0x02,
++ WPA_PSK_AUTH = 0x03,
++ WPA2_AUTH = 0x04,
++ WPA2_PSK_AUTH = 0x05,
++ WPA_AUTH_CCKM = 0x06,
++ WPA2_AUTH_CCKM = 0x07,
++} AUTH_MODE;
++
++typedef enum {
++ NONE_CRYPT = 0x01,
++ WEP_CRYPT = 0x02,
++ TKIP_CRYPT = 0x03,
++ AES_CRYPT = 0x04,
++} CRYPTO_TYPE;
++
++#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
++#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
++
++#define WMI_MIN_KEY_INDEX 0
++#define WMI_MAX_KEY_INDEX 3
++
++#define WMI_MAX_KEY_LEN 32
++
++#define WMI_MAX_SSID_LEN 32
++
++typedef struct {
++ A_UINT8 networkType;
++ A_UINT8 dot11AuthMode;
++ A_UINT8 authMode;
++ A_UINT8 pairwiseCryptoType;
++ A_UINT8 pairwiseCryptoLen;
++ A_UINT8 groupCryptoType;
++ A_UINT8 groupCryptoLen;
++ A_UINT8 ssidLength;
++ A_UCHAR ssid[WMI_MAX_SSID_LEN];
++ A_UINT16 channel;
++ A_UINT8 bssid[ATH_MAC_LEN];
++} __ATTRIB_PACK WMI_CONNECT_CMD;
++
++/*
++ * WMI_RECONNECT_CMDID
++ */
++typedef struct {
++ A_UINT16 channel; /* hint */
++ A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */
++} __ATTRIB_PACK WMI_RECONNECT_CMD;
++
++/*
++ * WMI_ADD_CIPHER_KEY_CMDID
++ */
++typedef enum {
++ PAIRWISE_USAGE = 0x00,
++ GROUP_USAGE = 0x01,
++ TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
++} KEY_USAGE;
++
++typedef struct {
++ A_UINT8 keyIndex;
++ A_UINT8 keyType;
++ A_UINT8 keyUsage; /* KEY_USAGE */
++ A_UINT8 keyLength;
++ A_UINT8 keyRSC[8]; /* key replay sequence counter */
++ A_UINT8 key[WMI_MAX_KEY_LEN];
++} __ATTRIB_PACK WMI_ADD_CIPHER_KEY_CMD;
++
++/*
++ * WMI_DELETE_CIPHER_KEY_CMDID
++ */
++typedef struct {
++ A_UINT8 keyIndex;
++} __ATTRIB_PACK WMI_DELETE_CIPHER_KEY_CMD;
++
++#define WMI_KRK_LEN 16
++/*
++ * WMI_ADD_KRK_CMDID
++ */
++typedef struct {
++ A_UINT8 krk[WMI_KRK_LEN];
++} __ATTRIB_PACK WMI_ADD_KRK_CMD;
++
++/*
++ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
++ */
++typedef enum {
++ WMI_TKIP_CM_DISABLE = 0x0,
++ WMI_TKIP_CM_ENABLE = 0x1,
++} WMI_TKIP_CM_CONTROL;
++
++typedef struct {
++ A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */
++} __ATTRIB_PACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
++
++/*
++ * WMI_SET_PMKID_CMDID
++ */
++typedef enum {
++ PMKID_DISABLE = 0,
++ PMKID_ENABLE = 1,
++} PMKID_ENABLE_FLG;
++
++typedef struct {
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_UINT8 enable; /* PMKID_ENABLE_FLG */
++ A_UINT8 pmkid[16];
++} __ATTRIB_PACK WMI_SET_PMKID_CMD;
++
++/*
++ * WMI_START_SCAN_CMD
++ */
++typedef enum {
++ WMI_LONG_SCAN = 0,
++ WMI_SHORT_SCAN = 1,
++} WMI_SCAN_TYPE;
++
++typedef struct {
++ A_UINT8 scanType; /* WMI_SCAN_TYPE */
++} __ATTRIB_PACK WMI_START_SCAN_CMD;
++
++/*
++ * WMI_SET_SCAN_PARAMS_CMDID
++ */
++#define WMI_SHORTSCANRATIO_DEFAULT 3
++
++typedef struct {
++ A_UINT16 fg_start_period; /* seconds */
++ A_UINT16 fg_end_period; /* seconds */
++ A_UINT16 bg_period; /* seconds */
++ A_UINT16 act_chdwell_time; /* msec */
++ A_UINT16 pas_chdwell_time; /* msec */
++ A_UINT8 shortScanRatio; /* how many shorts scan for one long */
++} __ATTRIB_PACK WMI_SCAN_PARAMS_CMD;
++
++/*
++ * WMI_SET_BSS_FILTER_CMDID
++ */
++typedef enum {
++ NONE_BSS_FILTER = 0x0, /* no beacons forwarded */
++ ALL_BSS_FILTER, /* all beacons forwarded */
++ PROFILE_FILTER, /* only beacons matching profile */
++ ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */
++ CURRENT_BSS_FILTER, /* only beacons matching current BSS */
++ ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */
++ PROBED_SSID_FILTER, /* beacons matching probed ssid */
++ LAST_BSS_FILTER, /* marker only */
++} WMI_BSS_FILTER;
++
++typedef struct {
++ A_UINT8 bssFilter; /* see WMI_BSS_FILTER */
++} __ATTRIB_PACK WMI_BSS_FILTER_CMD;
++
++/*
++ * WMI_SET_PROBED_SSID_CMDID
++ */
++#define MAX_PROBED_SSID_INDEX 5
++
++typedef enum {
++ DISABLE_SSID_FLAG = 0, /* disables entry */
++ SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */
++ ANY_SSID_FLAG = 0x02, /* probes for any ssid */
++} WMI_SSID_FLAG;
++
++typedef struct {
++ A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */
++ A_UINT8 flag; /* WMI_SSID_FLG */
++ A_UINT8 ssidLength;
++ A_UINT8 ssid[32];
++} __ATTRIB_PACK WMI_PROBED_SSID_CMD;
++
++/*
++ * WMI_SET_LISTEN_INT_CMDID
++ * The Listen interval is between 100 and 1000 TUs
++ */
++#define MIN_LISTEN_INTERVAL 100
++#define MAX_LISTEN_INTERVAL 1000
++#define MIN_LISTEN_BEACONS 1
++#define MAX_LISTEN_BEACONS 50
++
++typedef struct {
++ A_UINT16 listenInterval;
++ A_UINT16 numBeacons;
++} __ATTRIB_PACK WMI_LISTEN_INT_CMD;
++
++/*
++ * WMI_SET_BEACON_INT_CMDID
++ */
++typedef struct {
++ A_UINT16 beaconInterval;
++} __ATTRIB_PACK WMI_BEACON_INT_CMD;
++
++/*
++ * WMI_SET_BMISS_TIME_CMDID
++ * valid values are between 1000 and 5000 TUs
++ */
++
++#define MIN_BMISS_TIME 1000
++#define MAX_BMISS_TIME 5000
++#define MIN_BMISS_BEACONS 5
++#define MAX_BMISS_BEACONS 50
++
++typedef struct {
++ A_UINT16 bmissTime;
++ A_UINT16 numBeacons;
++} __ATTRIB_PACK WMI_BMISS_TIME_CMD;
++
++/*
++ * WMI_SET_POWER_MODE_CMDID
++ */
++typedef enum {
++ REC_POWER = 0x01,
++ MAX_PERF_POWER,
++} WMI_POWER_MODE;
++
++typedef struct {
++ A_UINT8 powerMode; /* WMI_POWER_MODE */
++} __ATTRIB_PACK WMI_POWER_MODE_CMD;
++
++/*
++ * WMI_SET_POWER_PARAMS_CMDID
++ */
++typedef enum {
++ IGNORE_DTIM = 0x01,
++ NORMAL_DTIM = 0x02,
++ STICK_DTIM = 0x03,
++} WMI_DTIM_POLICY;
++
++typedef struct {
++ A_UINT16 idle_period; /* msec */
++ A_UINT16 pspoll_number;
++ A_UINT16 dtim_policy;
++} __ATTRIB_PACK WMI_POWER_PARAMS_CMD;
++
++typedef struct {
++ A_UINT8 power_saving;
++ A_UINT8 ttl; /* number of beacon periods */
++ A_UINT16 atim_windows; /* msec */
++ A_UINT16 timeout_value; /* msec */
++} __ATTRIB_PACK WMI_IBSS_PM_CAPS_CMD;
++
++/*
++ * WMI_SET_POWERSAVE_TIMERS_CMDID
++ */
++typedef struct {
++ A_UINT16 psPollTimeout; /* msec */
++ A_UINT16 eospTimeout; /* msec */
++} __ATTRIB_PACK WMI_POWERSAVE_TIMERS_CMD;
++
++/*
++ * WMI_SET_VOICE_PKT_SIZE_CMDID
++ */
++typedef struct {
++ A_UINT16 voicePktSize;
++} __ATTRIB_PACK WMI_SET_VOICE_PKT_SIZE_CMD;
++
++/*
++ * WMI_SET_MAX_SP_LEN_CMDID
++ */
++typedef enum {
++ DELIVER_ALL_PKT = 0x0,
++ DELIVER_2_PKT = 0x1,
++ DELIVER_4_PKT = 0x2,
++ DELIVER_6_PKT = 0x3,
++} APSD_SP_LEN_TYPE;
++
++typedef struct {
++ A_UINT8 maxSPLen;
++} __ATTRIB_PACK WMI_SET_MAX_SP_LEN_CMD;
++
++/*
++ * WMI_SET_DISC_TIMEOUT_CMDID
++ */
++typedef struct {
++ A_UINT8 disconnectTimeout; /* seconds */
++} __ATTRIB_PACK WMI_DISC_TIMEOUT_CMD;
++
++typedef enum {
++ UPLINK_TRAFFIC = 0,
++ DNLINK_TRAFFIC = 1,
++ BIDIR_TRAFFIC = 2,
++} DIR_TYPE;
++/*
++ * WMI_CREATE_PSTREAM_CMDID
++ */
++typedef enum {
++ DISABLE_FOR_THIS_AC = 0,
++ ENABLE_FOR_THIS_AC = 1,
++ ENABLE_FOR_ALL_AC = 2,
++} VOICEPS_CAP_TYPE;
++
++typedef enum {
++ TRAFFIC_TYPE_APERIODIC = 0,
++ TRAFFIC_TYPE_PERIODIC = 1,
++}TRAFFIC_TYPE;
++
++typedef struct {
++ A_UINT8 trafficClass;
++ A_UINT8 trafficDirection; /* DIR_TYPE */
++ A_UINT8 rxQueueNum;
++ A_UINT8 trafficType; /* TRAFFIC_TYPE */
++ A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */
++ A_UINT8 tsid;
++ A_UINT8 userPriority; /* 802.1D user priority */
++ A_UINT16 nominalMSDU; /* in octects */
++ A_UINT16 maxMSDU; /* in octects */
++ A_UINT32 minServiceInt; /* in milli-sec */
++ A_UINT32 maxServiceInt; /* in milli-sec */
++ A_UINT32 inactivityInt; /* in milli-sec */
++ A_UINT32 suspensionInt; /* in milli-sec */
++ A_UINT32 serviceStartTime;
++ A_UINT32 minDataRate; /* in bps */
++ A_UINT32 meanDataRate; /* in bps */
++ A_UINT32 peakDataRate; /* in bps */
++ A_UINT32 maxBurstSize;
++ A_UINT32 delayBound;
++ A_UINT32 minPhyRate; /* in bps */
++ A_UINT32 sba;
++ A_UINT32 mediumTime;
++} __ATTRIB_PACK WMI_CREATE_PSTREAM_CMD;
++
++/*
++ * WMI_DELETE_PSTREAM_CMDID
++ */
++typedef struct {
++ A_UINT8 txQueueNumber;
++ A_UINT8 rxQueueNumber;
++ A_UINT8 trafficDirection;
++ A_UINT8 trafficClass;
++} __ATTRIB_PACK WMI_DELETE_PSTREAM_CMD;
++
++/*
++ * WMI_SET_CHANNEL_PARAMS_CMDID
++ */
++typedef enum {
++ WMI_11A_MODE = 0x1,
++ WMI_11G_MODE = 0x2,
++ WMI_11AG_MODE = 0x3,
++ WMI_11B_MODE = 0x4,
++ WMI_11GONLY_MODE = 0x5,
++} WMI_PHY_MODE;
++
++#define WMI_MAX_CHANNELS 32
++
++typedef struct {
++ A_UINT8 phyMode; /* see WMI_PHY_MODE */
++ A_UINT8 numChannels; /* how many channels follow */
++ A_UINT16 channelList[1]; /* channels in Mhz */
++} __ATTRIB_PACK WMI_CHANNEL_PARAMS_CMD;
++
++
++/*
++ * WMI_RSSI_THRESHOLD_PARAMS_CMDID
++ * Setting the polltime to 0 would disable polling.
++ * Threshold values are in the ascending order, and should agree to:
++ * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
++ * < highThreshold_upperVal)
++ */
++
++typedef struct WMI_RSSI_THRESHOLD_PARAMS{
++ A_UINT8 highThreshold_upperVal;
++ A_UINT8 highThreshold_lowerVal;
++ A_UINT8 lowThreshold_upperVal;
++ A_UINT8 lowThreshold_lowerVal;
++ A_UINT32 pollTime; /* Polling time in seconds */
++} __ATTRIB_PACK WMI_RSSI_THRESHOLD_PARAMS_CMD;
++
++/*
++ * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
++ * Sets the error reporting event bitmask in target. Target clears it
++ * upon an error. Subsequent errors are counted, but not reported
++ * via event, unless the bitmask is set again.
++ */
++typedef struct {
++ A_UINT32 bitmask;
++} __ATTRIB_PACK WMI_TARGET_ERROR_REPORT_BITMASK;
++
++/*
++ * WMI_SET_TX_PWR_CMDID
++ */
++typedef struct {
++ A_UINT8 dbM; /* in dbM units */
++} __ATTRIB_PACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
++
++/*
++ * WMI_SET_ASSOC_INFO_CMDID
++ *
++ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
++ * A 3rd one, the CCX version IE can also be set from the host.
++ */
++#define WMI_MAX_ASSOC_INFO_TYPE 2
++#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */
++
++#define WMI_MAX_ASSOC_INFO_LEN 240
++
++typedef struct {
++ A_UINT8 ieType;
++ A_UINT8 bufferSize;
++ A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */
++} __ATTRIB_PACK WMI_SET_ASSOC_INFO_CMD;
++
++
++/*
++ * WMI_GET_TX_PWR_CMDID does not take any parameters
++ */
++
++/*
++ * WMI_ADD_BAD_AP_CMDID
++ */
++#define WMI_MAX_BAD_AP_INDEX 1
++
++typedef struct {
++ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
++ A_UINT8 bssid[ATH_MAC_LEN];
++} __ATTRIB_PACK WMI_ADD_BAD_AP_CMD;
++
++/*
++ * WMI_DELETE_BAD_AP_CMDID
++ */
++typedef struct {
++ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
++} __ATTRIB_PACK WMI_DELETE_BAD_AP_CMD;
++
++/*
++ * WMI_SET_ACCESS_PARAMS_CMDID
++ */
++#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */
++#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */
++#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */
++#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */
++#define WMI_DEFAULT_AIFSN_ACPARAM 2
++#define WMI_MAX_AIFSN_ACPARAM 15
++typedef struct {
++ A_UINT16 txop; /* in units of 32 usec */
++ A_UINT8 eCWmin;
++ A_UINT8 eCWmax;
++ A_UINT8 aifsn;
++} __ATTRIB_PACK WMI_SET_ACCESS_PARAMS_CMD;
++
++
++/*
++ * WMI_SET_RETRY_LIMITS_CMDID
++ *
++ * This command is used to customize the number of retries the
++ * wlan device will perform on a given frame.
++ */
++#define WMI_MIN_RETRIES 2
++#define WMI_MAX_RETRIES 13
++typedef enum {
++ MGMT_FRAMETYPE = 0,
++ CONTROL_FRAMETYPE = 1,
++ DATA_FRAMETYPE = 2
++} WMI_FRAMETYPE;
++
++typedef struct {
++ A_UINT8 frameType; /* WMI_FRAMETYPE */
++ A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */
++ A_UINT8 maxRetries;
++} __ATTRIB_PACK WMI_SET_RETRY_LIMITS_CMD;
++/*
++ * WMI_SET_ROAM_CTRL_CMDID
++ *
++ * This command is used to influence the Roaming behaviour
++ * Set the host biases of the BSSs before setting the roam mode as bias
++ * based.
++ */
++
++/*
++ * Different types of Roam Control
++ */
++
++typedef enum {
++ WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */
++ WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */
++ WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */
++} WMI_ROAM_CTRL_TYPE;
++
++#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
++#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_HOST_BIAS
++
++/*
++ * ROAM MODES
++ */
++
++typedef enum {
++ WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */
++ WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
++ WMI_LOCK_BSS_MODE = 3, /* Lock to the Current BSS - no Roam */
++ WMI_DISABLE_ROAM = 4 /* disables all auto-nomous roaming
++ behaviour */
++} WMI_ROAM_MODE;
++
++/*
++ * BSS HOST BIAS INFO
++ */
++
++typedef struct {
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_INT8 bias;
++} __ATTRIB_PACK WMI_BSS_BIAS;
++
++typedef struct {
++ A_UINT8 numBss;
++ WMI_BSS_BIAS bssBias[1];
++} __ATTRIB_PACK WMI_BSS_BIAS_INFO;
++
++typedef struct {
++ A_UINT8 roamCtrlType;
++ union {
++ A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
++ A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */
++ WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
++ } __ATTRIB_PACK info;
++} __ATTRIB_PACK WMI_SET_ROAM_CTRL_CMD;
++
++/*
++ * WMI_ENABLE_RM_CMDID
++ */
++typedef struct {
++ A_BOOL enable_radio_measurements;
++} __ATTRIB_PACK WMI_ENABLE_RM_CMD;
++
++/*
++ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
++ */
++typedef struct {
++ A_UINT8 max_offhome_duration;
++} __ATTRIB_PACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
++
++
++
++/*
++ * Command Replies
++ */
++
++/*
++ * WMI_GET_CHANNEL_LIST_CMDID reply
++ */
++typedef struct {
++ A_UINT8 reserved1;
++ A_UINT8 numChannels; /* number of channels in reply */
++ A_UINT16 channelList[1]; /* channel in Mhz */
++} __ATTRIB_PACK WMI_CHANNEL_LIST_REPLY;
++
++typedef enum {
++ A_SUCCEEDED = A_OK,
++ A_MBOX1_OK = 1,
++ A_MBOX2_OK = 2,
++ A_MBOX3_OK = 3,
++ A_FAILED_DELETE_INVALID_MBOX = 253,
++ A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
++} PSTREAM_REPLY_STATUS;
++
++typedef struct {
++ A_UINT8 status; /* PSTREAM_REPLY_STATUS */
++ A_UINT8 txQueueNumber;
++ A_UINT8 rxQueueNumber;
++ A_UINT8 trafficClass;
++ A_UINT8 trafficDirection; /* DIR_TYPE */
++} __ATTRIB_PACK WMI_CRE_PRIORITY_STREAM_REPLY;
++
++typedef struct {
++ A_UINT8 status; /* PSTREAM_REPLY_STATUS */
++ A_UINT8 txQueueNumber;
++ A_UINT8 rxQueueNumber;
++ A_UINT8 trafficDirection; /* DIR_TYPE */
++ A_UINT8 trafficClass;
++} __ATTRIB_PACK WMI_DEL_PRIORITY_STREAM_REPLY;
++
++
++/*
++ * List of Events (target to host)
++ */
++typedef enum {
++ WMI_READY_EVENTID = 0x1001,
++ WMI_CONNECT_EVENTID,
++ WMI_DISCONNECT_EVENTID,
++ WMI_BSSINFO_EVENTID,
++ WMI_CMDERROR_EVENTID,
++ WMI_REGDOMAIN_EVENTID,
++ WMI_PSTREAM_TIMEOUT_EVENTID,
++ WMI_NEIGHBOR_REPORT_EVENTID,
++ WMI_TKIP_MICERR_EVENTID,
++ WMI_SCAN_COMPLETE_EVENTID,
++ WMI_REPORT_STATISTICS_EVENTID,
++ WMI_RSSI_THRESHOLD_EVENTID,
++ WMI_ERROR_REPORT_EVENTID,
++ WMI_OPT_RX_FRAME_EVENTID,
++ WMI_REPORT_ROAM_TBL_EVENTID,
++ WMI_EXTENSION_EVENTID,
++ WMI_CAC_EVENTID,
++ WMI_SNR_THRESHOLD_EVENTID,
++ WMI_LQ_THRESHOLD_EVENTID,
++ WMI_TX_RETRY_ERR_EVENTID,
++ WMI_REPORT_ROAM_DATA_EVENTID,
++} WMI_EVENT_ID;
++
++typedef enum {
++ WMI_11A_CAPABILITY = 1,
++ WMI_11G_CAPABILITY = 2,
++ WMI_11AG_CAPABILITY = 3,
++} WMI_PHY_CAPABILITY;
++
++typedef struct {
++ A_UINT8 macaddr[ATH_MAC_LEN];
++ A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */
++} __ATTRIB_PACK WMI_READY_EVENT;
++
++/*
++ * Connect Event
++ */
++typedef struct {
++ A_UINT16 channel;
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_UINT16 listenInterval;
++ A_UINT8 beaconIeLen;
++ A_UINT8 assocReqLen;
++ A_UINT8 assocRespLen;
++ A_UINT8 assocInfo[1];
++} __ATTRIB_PACK WMI_CONNECT_EVENT;
++
++/*
++ * Disconnect Event
++ */
++typedef enum {
++ NO_NETWORK_AVAIL = 0x01,
++ LOST_LINK = 0x02, /* bmiss */
++ DISCONNECT_CMD = 0x03,
++ BSS_DISCONNECTED = 0x04,
++ AUTH_FAILED = 0x05,
++ ASSOC_FAILED = 0x06,
++ NO_RESOURCES_AVAIL = 0x07,
++ CSERV_DISCONNECT = 0x08,
++ INVALID_PROFILE = 0x0a,
++} WMI_DISCONNECT_REASON;
++
++typedef struct {
++ A_UINT8 disconnectReason; /* see WMI_DISCONNECT_REASON */
++ A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */
++ A_UINT8 assocRespLen;
++ A_UINT8 assocInfo[1];
++} __ATTRIB_PACK WMI_DISCONNECT_EVENT;
++
++/*
++ * BSS Info Event.
++ * Mechanism used to inform host of the presence and characteristic of
++ * wireless networks present. Consists of bss info header followed by
++ * the beacon or probe-response frame body. The 802.11 header is not included.
++ */
++typedef enum {
++ BEACON_FTYPE = 0x1,
++ PROBERESP_FTYPE,
++} WMI_BI_FTYPE;
++
++typedef struct {
++ A_UINT16 channel;
++ A_UINT8 frameType; /* see WMI_BI_FTYPE */
++ A_INT8 rssi;
++ A_UINT8 bssid[ATH_MAC_LEN];
++} __ATTRIB_PACK WMI_BSS_INFO_HDR;
++
++/*
++ * Command Error Event
++ */
++typedef enum {
++ INVALID_PARAM = 0x01,
++ ILLEGAL_STATE = 0x02,
++ INTERNAL_ERROR = 0x03,
++} WMI_ERROR_CODE;
++
++typedef struct {
++ A_UINT16 commandId;
++ A_UINT8 errorCode;
++} __ATTRIB_PACK WMI_CMD_ERROR_EVENT;
++
++/*
++ * New Regulatory Domain Event
++ */
++typedef struct {
++ A_UINT32 regDomain;
++} __ATTRIB_PACK WMI_REG_DOMAIN_EVENT;
++
++typedef struct {
++ A_UINT8 txQueueNumber;
++ A_UINT8 rxQueueNumber;
++ A_UINT8 trafficDirection;
++} __ATTRIB_PACK WMI_PSTREAM_TIMEOUT_EVENT;
++
++/*
++ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
++ * the host of BSS's it has found that matches the current profile.
++ * It can be used by the host to cache PMKs and/to initiate pre-authentication
++ * if the BSS supports it. The first bssid is always the current associated
++ * BSS.
++ * The bssid and bssFlags information repeats according to the number
++ * or APs reported.
++ */
++typedef enum {
++ WMI_DEFAULT_BSS_FLAGS = 0x00,
++ WMI_PREAUTH_CAPABLE_BSS = 0x01,
++ WMI_PMKID_VALID_BSS = 0x02,
++} WMI_BSS_FLAGS;
++
++typedef struct {
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */
++} __ATTRIB_PACK WMI_NEIGHBOR_INFO;
++
++typedef struct {
++ A_INT8 numberOfAps;
++ WMI_NEIGHBOR_INFO neighbor[1];
++} __ATTRIB_PACK WMI_NEIGHBOR_REPORT_EVENT;
++
++/*
++ * TKIP MIC Error Event
++ */
++typedef struct {
++ A_UINT8 keyid;
++ A_UINT8 ismcast;
++} __ATTRIB_PACK WMI_TKIP_MICERR_EVENT;
++
++/*
++ * WMI_SCAN_COMPLETE_EVENTID - no parameters
++ */
++
++#define MAX_OPT_DATA_LEN 1400
++
++/*
++ * WMI_SET_ADHOC_BSSID_CMDID
++ */
++typedef struct {
++ A_UINT8 bssid[ATH_MAC_LEN];
++} __ATTRIB_PACK WMI_SET_ADHOC_BSSID_CMD;
++
++/*
++ * WMI_SET_OPT_MODE_CMDID
++ */
++typedef enum {
++ SPECIAL_OFF,
++ SPECIAL_ON,
++} OPT_MODE_TYPE;
++
++typedef struct {
++ A_UINT8 optMode;
++} __ATTRIB_PACK WMI_SET_OPT_MODE_CMD;
++
++/*
++ * WMI_TX_OPT_FRAME_CMDID
++ */
++typedef enum {
++ OPT_PROBE_REQ = 0x01,
++ OPT_PROBE_RESP = 0x02,
++ OPT_CPPP_START = 0x03,
++ OPT_CPPP_STOP = 0x04,
++} __ATTRIB_PACK WMI_OPT_FTYPE;
++
++typedef struct {
++ A_UINT8 frmType;
++ A_UINT8 dstAddr[ATH_MAC_LEN];
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_UINT16 optIEDataLen;
++ A_UINT8 *optIEData;
++} __ATTRIB_PACK WMI_OPT_TX_FRAME_CMD;
++
++/*
++ * Special frame receive Event.
++ * Mechanism used to inform host of the receiption of the special frames.
++ * Consists of special frame info header followed by special frame body.
++ * The 802.11 header is not included.
++ */
++typedef struct {
++ A_UINT16 channel;
++ A_UINT8 frameType; /* see WMI_OPT_FTYPE */
++ A_INT8 rssi;
++ A_UINT8 srcAddr[ATH_MAC_LEN];
++ A_UINT8 bssid[ATH_MAC_LEN];
++} __ATTRIB_PACK WMI_OPT_RX_INFO_HDR;
++
++/*
++ * Reporting statistics.
++ */
++typedef struct {
++ A_UINT32 tx_packets;
++ A_UINT32 tx_bytes;
++ A_UINT32 tx_unicast_pkts;
++ A_UINT32 tx_unicast_bytes;
++ A_UINT32 tx_multicast_pkts;
++ A_UINT32 tx_multicast_bytes;
++ A_UINT32 tx_broadcast_pkts;
++ A_UINT32 tx_broadcast_bytes;
++ A_UINT32 tx_rts_success_cnt;
++ A_UINT32 tx_packet_per_ac[4];
++
++ A_UINT32 tx_errors;
++ A_UINT32 tx_failed_cnt;
++ A_UINT32 tx_retry_cnt;
++ A_UINT32 tx_rts_fail_cnt;
++}__ATTRIB_PACK tx_stats_t;
++
++typedef struct {
++ A_UINT32 rx_packets;
++ A_UINT32 rx_bytes;
++ A_UINT32 rx_unicast_pkts;
++ A_UINT32 rx_unicast_bytes;
++ A_UINT32 rx_multicast_pkts;
++ A_UINT32 rx_multicast_bytes;
++ A_UINT32 rx_broadcast_pkts;
++ A_UINT32 rx_broadcast_bytes;
++ A_UINT32 rx_fragment_pkt;
++
++ A_UINT32 rx_errors;
++ A_UINT32 rx_crcerr;
++ A_UINT32 rx_key_cache_miss;
++ A_UINT32 rx_decrypt_err;
++ A_UINT32 rx_duplicate_frames;
++}__ATTRIB_PACK rx_stats_t;
++
++typedef struct {
++ A_UINT32 tkip_local_mic_failure;
++ A_UINT32 tkip_counter_measures_invoked;
++ A_UINT32 tkip_replays;
++ A_UINT32 tkip_format_errors;
++ A_UINT32 ccmp_format_errors;
++ A_UINT32 ccmp_replays;
++}__ATTRIB_PACK tkip_ccmp_stats_t;
++
++typedef struct {
++ A_UINT32 power_save_failure_cnt;
++}__ATTRIB_PACK pm_stats_t;
++
++typedef struct {
++ A_UINT32 cs_bmiss_cnt;
++ A_UINT32 cs_lowRssi_cnt;
++ A_UINT16 cs_connect_cnt;
++ A_UINT16 cs_disconnect_cnt;
++ A_UINT8 cs_aveBeacon_rssi;
++ A_UINT8 cs_lastRoam_msec;
++}__ATTRIB_PACK cserv_stats_t;
++
++typedef struct {
++ tx_stats_t tx_stats;
++ rx_stats_t rx_stats;
++ tkip_ccmp_stats_t tkipCcmpStats;
++}__ATTRIB_PACK wlan_net_stats_t;
++
++typedef struct {
++ wlan_net_stats_t txrxStats;
++ cserv_stats_t cservStats;
++ pm_stats_t pmStats;
++ A_INT16 noise_floor_calibation;
++}__ATTRIB_PACK WMI_TARGET_STATS;
++
++/*
++ * WMI_RSSI_THRESHOLD_EVENTID.
++ * Indicate the RSSI events to host. Events are indicated when we breach a
++ * thresold value.
++ */
++typedef enum{
++ WMI_RSSI_LOWTHRESHOLD_BELOW_LOWERVAL=1,
++ WMI_RSSI_LOWTHRESHOLD_LOWERVAL,
++ WMI_RSSI_LOWTHRESHOLD_UPPERVAL,
++ WMI_RSSI_HIGHTHRESHOLD_LOWERVAL,
++ WMI_RSSI_HIGHTHRESHOLD_HIGHERVAL
++}WMI_RSSI_THRESHOLD_VAL;
++
++typedef struct {
++ A_UINT8 range;
++}__ATTRIB_PACK WMI_RSSI_THRESHOLD_EVENT;
++
++/*
++ * WMI_ERROR_REPORT_EVENTID
++ */
++typedef enum{
++ WMI_TARGET_PM_ERR_FAIL = 0x00000001,
++ WMI_TARGET_KEY_NOT_FOUND = 0x00000002,
++ WMI_TARGET_DECRYPTION_ERR = 0x00000004,
++ WMI_TARGET_BMISS = 0x00000008,
++ WMI_PSDISABLE_NODE_JOIN = 0x00000010
++}__ATTRIB_PACK WMI_TARGET_ERROR_VAL;
++
++typedef struct {
++ A_UINT32 errorVal;
++}__ATTRIB_PACK WMI_TARGET_ERROR_REPORT_EVENT;
++
++/*
++ * WMI_REPORT_ROAM_TBL_EVENTID
++ */
++#define MAX_ROAM_TBL_CAND 5
++
++typedef struct {
++ A_UINT8 bssid[ATH_MAC_LEN];
++ A_INT8 rssi;
++ A_INT8 rssidt;
++ A_INT8 last_rssi;
++ A_INT32 roam_util;
++ A_INT8 util;
++ A_INT8 bias;
++} __ATTRIB_PACK WMI_BSS_ROAM_INFO;
++
++
++typedef struct {
++ A_UINT8 roamMode;
++ A_UINT8 numEntries;
++ WMI_BSS_ROAM_INFO bssRoamInfo[1];
++} __ATTRIB_PACK WMI_TARGET_ROAM_TBL;
++
++/*
++ * WMI_CAC_EVENTID
++ */
++typedef enum {
++ CAC_INDICATION_ADMISSION = 0x00,
++ CAC_INDICATION_ADMISSION_RESP = 0x01,
++ CAC_INDICATION_DELETE = 0x02,
++ CAC_INDICATION_NO_RESP = 0x03,
++}CAC_INDICATION;
++
++#define WMM_TSPEC_IE_LEN 63
++
++typedef struct {
++ A_UINT8 ac;
++ A_UINT8 cac_indication;
++ A_UINT8 statusCode;
++ A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
++}__ATTRIB_PACK WMI_CAC_EVENT;
++
++/*
++ * developer commands
++ */
++
++/*
++ * WMI_SET_BITRATE_CMDID
++ *
++ * Get bit rate cmd uses same definition as set bit rate cmd
++ */
++typedef enum {
++ RATE_AUTO = -1,
++ RATE_1Mb = 0,
++ RATE_2Mb = 1,
++ RATE_5_5Mb = 2,
++ RATE_11Mb = 3,
++ RATE_6Mb = 4,
++ RATE_9Mb = 5,
++ RATE_12Mb = 6,
++ RATE_18Mb = 7,
++ RATE_24Mb = 8,
++ RATE_36Mb = 9,
++ RATE_48Mb = 10,
++ RATE_54Mb = 11,
++} WMI_BIT_RATE;
++
++typedef struct {
++ A_INT8 rateIndex; /* see WMI_BIT_RATE */
++} __ATTRIB_PACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY;
++
++typedef enum {
++ ROAM_DATA_TIME = 1, /* Get The Roam Time Data */
++} ROAM_DATA_TYPE;
++
++typedef struct {
++ A_UINT32 disassoc_time;
++ A_UINT8 disassoc_bssid[ATH_MAC_LEN];
++ A_INT8 disassoc_bss_rssi;
++ A_UINT32 no_txrx_time;
++ A_UINT32 assoc_time;
++ A_UINT8 assoc_bssid[ATH_MAC_LEN];
++ A_INT8 assoc_bss_rssi;
++ A_UINT32 allow_txrx_time;
++ A_UINT32 last_data_txrx_time;
++ A_UINT32 first_data_txrx_time;
++} __ATTRIB_PACK WMI_TARGET_ROAM_TIME;
++
++typedef struct {
++ A_UINT8 roamDataType;
++ union {
++ WMI_TARGET_ROAM_TIME roamTime;
++ } u;
++} __ATTRIB_PACK WMI_TARGET_ROAM_DATA;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _WMI_H_ */
+Index: linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmix.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/wlan/ar6000/include/wmix.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,197 @@
++/*
++ * Copyright (c) 2004-2005 Atheros Communications Inc.
++ * All rights reserved.
++ *
++ * This file contains extensions of the WMI protocol specified in the
++ * Wireless Module Interface (WMI). It includes definitions of all
++ * extended commands and events. Extensions include useful commands
++ * that are not directly related to wireless activities. They may
++ * be hardware-specific, and they might not be supported on all
++ * implementations.
++ *
++ * Extended WMIX commands are encapsulated in a WMI message with
++ * cmd=WMI_EXTENSION_CMD.
++ *
++ * $Id: //depot/sw/releases/etnaGPL1.1/include/wmix.h#1 $
++ *
++ */
++
++#ifndef _WMIX_H_
++#define _WMIX_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++ * Extended WMI commands are those that are needed during wireless
++ * operation, but which are not really wireless commands. This allows,
++ * for instance, platform-specific commands. Extended WMI commands are
++ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
++ * Extended WMI events are similarly embedded in a WMI event message with
++ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
++ */
++typedef struct {
++ A_UINT16 commandId;
++} __ATTRIB_PACK WMIX_CMD_HDR;
++
++typedef enum {
++ WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
++ WMIX_DSETDATA_REPLY_CMDID,
++ WMIX_GPIO_OUTPUT_SET_CMDID,
++ WMIX_GPIO_INPUT_GET_CMDID,
++ WMIX_GPIO_REGISTER_SET_CMDID,
++ WMIX_GPIO_REGISTER_GET_CMDID,
++ WMIX_GPIO_INTR_ACK_CMDID,
++} WMIX_COMMAND_ID;
++
++typedef enum {
++ WMIX_DSETOPENREQ_EVENTID = 0x3001,
++ WMIX_DSETCLOSE_EVENTID,
++ WMIX_DSETDATAREQ_EVENTID,
++ WMIX_GPIO_INTR_EVENTID,
++ WMIX_GPIO_DATA_EVENTID,
++ WMIX_GPIO_ACK_EVENTID,
++} WMIX_EVENT_ID;
++
++/*
++ * =============DataSet support=================
++ */
++
++/*
++ * WMIX_DSETOPENREQ_EVENTID
++ * DataSet Open Request Event
++ */
++typedef struct {
++ A_UINT32 dset_id;
++ A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
++ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
++ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
++} __ATTRIB_PACK WMIX_DSETOPENREQ_EVENT;
++
++/*
++ * WMIX_DSETCLOSE_EVENTID
++ * DataSet Close Event
++ */
++typedef struct {
++ A_UINT32 access_cookie;
++} __ATTRIB_PACK WMIX_DSETCLOSE_EVENT;
++
++/*
++ * WMIX_DSETDATAREQ_EVENTID
++ * DataSet Data Request Event
++ */
++typedef struct {
++ A_UINT32 access_cookie;
++ A_UINT32 offset;
++ A_UINT32 length;
++ A_UINT32 targ_buf; /* echo'ed, not used by Host, */
++ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
++ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
++} __ATTRIB_PACK WMIX_DSETDATAREQ_EVENT;
++
++typedef struct {
++ A_UINT32 status;
++ A_UINT32 targ_dset_handle;
++ A_UINT32 targ_reply_fn;
++ A_UINT32 targ_reply_arg;
++ A_UINT32 access_cookie;
++ A_UINT32 size;
++ A_UINT32 version;
++} __ATTRIB_PACK WMIX_DSETOPEN_REPLY_CMD;
++
++typedef struct {
++ A_UINT32 status;
++ A_UINT32 targ_buf;
++ A_UINT32 targ_reply_fn;
++ A_UINT32 targ_reply_arg;
++ A_UINT32 length;
++ A_UINT8 buf[1];
++} __ATTRIB_PACK WMIX_DSETDATA_REPLY_CMD;
++
++
++/*
++ * =============GPIO support=================
++ * All masks are 18-bit masks with bit N operating on GPIO pin N.
++ */
++
++#if defined(AR6000)
++#include "AR6000/AR6000_gpio.h"
++#endif /* AR6000 */
++
++/*
++ * Set GPIO pin output state.
++ * In order for output to be driven, a pin must be enabled for output.
++ * This can be done during initialization through the GPIO Configuration
++ * DataSet, or during operation with the enable_mask.
++ *
++ * If a request is made to simultaneously set/clear or set/disable or
++ * clear/disable or disable/enable, results are undefined.
++ */
++typedef struct {
++ A_UINT32 set_mask; /* pins to set */
++ A_UINT32 clear_mask; /* pins to clear */
++ A_UINT32 enable_mask; /* pins to enable for output */
++ A_UINT32 disable_mask; /* pins to disable/tristate */
++} __ATTRIB_PACK WMIX_GPIO_OUTPUT_SET_CMD;
++
++/*
++ * Set a GPIO register. For debug/exceptional cases.
++ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
++ * platform-dependent header.
++ */
++typedef struct {
++ A_UINT32 gpioreg_id; /* GPIO register ID */
++ A_UINT32 value; /* value to write */
++} __ATTRIB_PACK WMIX_GPIO_REGISTER_SET_CMD;
++
++/* Get a GPIO register. For debug/exceptional cases. */
++typedef struct {
++ A_UINT32 gpioreg_id; /* GPIO register to read */
++} __ATTRIB_PACK WMIX_GPIO_REGISTER_GET_CMD;
++
++/*
++ * Host acknowledges and re-arms GPIO interrupts. A single
++ * message should be used to acknowledge all interrupts that
++ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
++ */
++typedef struct {
++ A_UINT32 ack_mask; /* interrupts to acknowledge */
++} __ATTRIB_PACK WMIX_GPIO_INTR_ACK_CMD;
++
++/*
++ * Target informs Host of GPIO interrupts that have ocurred since the
++ * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information --
++ * the current GPIO input values is provided -- in order to support
++ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
++ */
++typedef struct {
++ A_UINT32 intr_mask; /* pending GPIO interrupts */
++ A_UINT32 input_values; /* recent GPIO input values */
++} __ATTRIB_PACK WMIX_GPIO_INTR_EVENT;
++
++/*
++ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
++ * using a GPIO_DATA_EVENT with
++ * value set to the mask of GPIO pin inputs and
++ * reg_id set to GPIO_ID_NONE
++ *
++ *
++ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
++ * using a GPIO_DATA_EVENT with
++ * value set to the value of the requested register and
++ * reg_id identifying the register (reflects the original request)
++ * NB: reg_id supports the future possibility of unsolicited
++ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
++ * simplify Host GPIO support.
++ */
++typedef struct {
++ A_UINT32 value;
++ A_UINT32 reg_id;
++} __ATTRIB_PACK WMIX_GPIO_DATA_EVENT;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _WMIX_H_ */
+Index: linux-2.6.22/drivers/pnp/core.c
+===================================================================
+--- linux-2.6.22.orig/drivers/pnp/core.c 2007-11-08 15:47:27.000000000 +0100
++++ linux-2.6.22/drivers/pnp/core.c 2007-11-08 15:47:58.000000000 +0100
+@@ -169,14 +169,12 @@
+ *
+ * this function will free all mem used by dev
+ */
+-#if 0
+ void pnp_remove_device(struct pnp_dev *dev)
+ {
+ if (!dev || dev->card)
+ return;
+ __pnp_remove_device(dev);
+ }
+-#endif /* 0 */
+
+ static int __init pnp_init(void)
+ {
+@@ -186,9 +184,7 @@
+
+ subsys_initcall(pnp_init);
+
+-#if 0
+ EXPORT_SYMBOL(pnp_register_protocol);
+ EXPORT_SYMBOL(pnp_unregister_protocol);
+ EXPORT_SYMBOL(pnp_add_device);
+ EXPORT_SYMBOL(pnp_remove_device);
+-#endif /* 0 */
+Index: linux-2.6.22/drivers/pnp/driver.c
+===================================================================
+--- linux-2.6.22.orig/drivers/pnp/driver.c 2007-11-08 15:47:27.000000000 +0100
++++ linux-2.6.22/drivers/pnp/driver.c 2007-11-08 15:47:58.000000000 +0100
+@@ -243,8 +243,6 @@
+
+ EXPORT_SYMBOL(pnp_register_driver);
+ EXPORT_SYMBOL(pnp_unregister_driver);
+-#if 0
+ EXPORT_SYMBOL(pnp_add_id);
+-#endif
+ EXPORT_SYMBOL(pnp_device_attach);
+ EXPORT_SYMBOL(pnp_device_detach);
+Index: linux-2.6.22/drivers/pnp/Kconfig
+===================================================================
+--- linux-2.6.22.orig/drivers/pnp/Kconfig 2007-11-08 15:47:27.000000000 +0100
++++ linux-2.6.22/drivers/pnp/Kconfig 2007-11-08 15:47:58.000000000 +0100
+@@ -7,7 +7,7 @@
+
+ config PNP
+ bool "Plug and Play support"
+- depends on ISA || ACPI
++ depends on ISA || ACPI || SDIO
+ ---help---
+ Plug and Play (PnP) is a standard for peripherals which allows those
+ peripherals to be configured by software, e.g. assign IRQ's or other
Added: developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_functions.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_functions.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_functions.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,5181 @@
+---
+ drivers/sdio/function/Kconfig | 32
+ drivers/sdio/function/Makefile | 7
+ drivers/sdio/function/bluetooth/Makefile | 5
+ drivers/sdio/function/bluetooth/sdio_bt.c | 769 +++++++++++++++++
+ drivers/sdio/function/bluetooth/sdio_bt.h | 176 +++
+ drivers/sdio/function/bluetooth/sdio_bt_linux.h | 70 +
+ drivers/sdio/function/bluetooth/sdio_bt_os.c | 584 ++++++++++++
+ drivers/sdio/function/gps/Makefile | 5
+ drivers/sdio/function/gps/gps.c | 392 ++++++++
+ drivers/sdio/function/gps/gps.h | 194 ++++
+ drivers/sdio/function/gps/gps_linux.h | 63 +
+ drivers/sdio/function/gps/gps_os.c | 633 ++++++++++++++
+ drivers/sdio/function/memory/Makefile | 5
+ drivers/sdio/function/memory/sdio_memory.c | 926 ++++++++++++++++++++
+ drivers/sdio/function/memory/sdio_memory.h | 98 ++
+ drivers/sdio/function/memory/sdio_memory_linux.h | 80 +
+ drivers/sdio/function/memory/sdio_memory_os.c | 1036 +++++++++++++++++++++++
+ 17 files changed, 5075 insertions(+)
+
+Index: linux-2.6.22/drivers/sdio/function/gps/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/gps/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO GPS function driver
++#
++obj-m += sdio_gps_fd.o
++sdio_gps_fd-objs := gps.o gps_os.o
+Index: linux-2.6.22/drivers/sdio/function/gps/gps.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/gps/gps.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,392 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: gps.c
++
++ at abstract: OS independent GPS class SDIO function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SD_GPS_FD
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include "gps.h"
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++
++void GpsIRQHandler(PVOID pContext);
++static void TxCompletion(PSDREQUEST pReq);
++
++
++/*
++ * GpsInitialize - initialize new device
++*/
++SDIO_STATUS GpsInitialize(PSDGPS_DEVICE pDevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++ struct SDIO_GPS_TPL gpsTpl;
++ UINT32 nextTpl;
++ UINT8 tplLength;
++ UINT8 temp;
++ SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
++
++ ZERO_OBJECT(fData);
++ ZERO_OBJECT(slotCurrent);
++
++ do {
++ status = SemaphoreInitialize(&pDevice->DeviceSem, 0);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ status = SDLIB_GetDefaultOpCurrent(pDevice->pSDDevice,&slotCurrent.SlotCurrent);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Gps Function: Allocating Slot current: %d mA\n", slotCurrent.SlotCurrent));
++ status = SDLIB_IssueConfig(pDevice->pSDDevice,
++ SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
++ &slotCurrent,
++ sizeof(slotCurrent));
++
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Gps Function: failed to allocate slot current %d\n",
++ status));
++ if (status == SDIO_STATUS_NO_RESOURCES) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Gps Function: Remaining Slot Current: %d mA\n",
++ slotCurrent.SlotCurrent));
++ }
++ break;
++ }
++
++ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
++ fData.TimeOut = 500;
++ status = SDLIB_IssueConfig(pDevice->pSDDevice,
++ SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData,
++ sizeof(fData));
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: GpsInitialize, failed to enable function %d\n",
++ status));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function Ready!\n"));
++ pDevice->HwReady = TRUE;
++ /* setup starting CIS scan */
++ nextTpl = SDDEVICE_GET_SDIO_FUNC_CISPTR(pDevice->pSDDevice);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Function CIS starts at :0x%X \n",
++ SDDEVICE_GET_SDIO_FUNC_CISPTR(pDevice->pSDDevice)));
++ /* look for the GPS TPL */
++ while (1) {
++ /* reset max buffer length */
++ tplLength = sizeof(gpsTpl);
++ /* go get the GPS tuple */
++ status = SDLIB_FindTuple(pDevice->pSDDevice,
++ GPS_TUPLE,
++ &nextTpl,
++ (PUINT8)&gpsTpl,
++ &tplLength);
++
++ if (!SDIO_SUCCESS(status)){
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: Failed to get GPS Tuple: %d \n",status));
++ break;
++ }
++
++ if (gpsTpl.StdTupleNumber == STD_GPS_TUPLE_SIOREG) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Found SDIOREG Tuple \n"));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: RegisterID:%d,RegisterExtID:%d \n",
++ gpsTpl.Tpd.AsSIOReg.RegisterID, gpsTpl.Tpd.AsSIOReg.RegisterExpID));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: MaxBaudCode:%d, DRL:%d , DRM:%d\n",
++ gpsTpl.Tpd.AsSIOReg.MaxBaudRateCode,
++ gpsTpl.Tpd.AsSIOReg.DRL_4800,gpsTpl.Tpd.AsSIOReg.DRM_4800));
++ pDevice->UartRegOffset = gpsTpl.Tpd.AsSIOReg.RegisterOffset[0];
++ pDevice->UartRegOffset |= gpsTpl.Tpd.AsSIOReg.RegisterOffset[1] << 8;
++ pDevice->UartRegOffset |= gpsTpl.Tpd.AsSIOReg.RegisterOffset[2] << 16;
++ pDevice->UartMaxBaud = (gpsTpl.Tpd.AsSIOReg.MaxBaudRateCode > 0) ?
++ gpsTpl.Tpd.AsSIOReg.MaxBaudRateCode * 115200 : 115200;
++ pDevice->UartDivisor = 4 *(gpsTpl.Tpd.AsSIOReg.DRL_4800 |
++ (gpsTpl.Tpd.AsSIOReg.DRM_4800 << 8) );
++ /* if zero, its not setup, guess */
++ if (pDevice->UartDivisor == 0) {
++ pDevice->UartDivisor = 6666;
++ DBG_PRINT(SDDBG_WARN, ("SDIO GPS Function: no UART divisor, using 1\n"));
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: RegisterOffset:0x%X \n",
++ pDevice->UartRegOffset));
++ break;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Found Sub-Tuple %d .. continuing search\n",
++ gpsTpl.StdTupleNumber));
++ continue;
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ /* allocate a single request for asynch call usage */
++ pDevice->pRequest = SDDeviceAllocRequest(pDevice->pSDDevice);
++
++ if (NULL == pDevice->pRequest) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ /* make sure interrupts are off and this also tests to see if we can see the
++ * hardware */
++ pDevice->InterruptEnable = 0;
++ status = WriteRegister(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable);
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: GpsInitialize, failed register write, %d\n",
++ status));
++ break;
++ }
++ /* read registers to clear status */
++ ReadRegister(pDevice, UART_LINE_STATUS_REG, &temp);
++ ReadRegister(pDevice, UART_RECEIVE_REG, &temp);
++ ReadRegister(pDevice, UART_INT_IDENT_REG, &temp);
++ ReadRegister(pDevice, UART_MODEM_STATUS_REG, &temp);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE | UART_FIFO_RCV_RESET);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE);
++ SetBaudRate(pDevice, 4800);
++ WriteRegister(pDevice, UART_LINE_CNTRL_REG, (UART_ONE_STOP | UART_NO_PARITY | UART_DATA_8_BITS));
++
++ /* set our IRQ handler */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Registering GpsIrqHandler \n"));
++ SDDEVICE_SET_IRQ_HANDLER(pDevice->pSDDevice,GpsIRQHandler,pDevice);
++ /* unmask our interrupt on the card */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: unmasking IRQ \n"));
++ status = SDLIB_IssueConfig(pDevice->pSDDevice,SDCONFIG_FUNC_UNMASK_IRQ,NULL,0);
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: GpsInitialize, failed to unmask IRQ %d\n",
++ status));
++ break;
++ }
++
++//?? DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: enabling InterruptEnable \n"));
++//?? pDevice->InterruptEnable = UART_ERBFI | UART_ELSI;
++//?? WriteRegister(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable);
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ GpsDeinitialize(pDevice);
++ }
++ SemaphorePost(&pDevice->DeviceSem);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: exiting \n"));
++
++ return status;
++}
++
++/*
++ * GpsDeinitialize - initialize new device
++*/
++void GpsDeinitialize(PSDGPS_DEVICE pDevice)
++{
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++
++ if (!(SDDEVICE_IS_CARD_REMOVED(pDevice->pSDDevice))) {
++ if (pDevice->HwReady) {
++ /* try masking our IRQ */
++ SDLIB_IssueConfig(pDevice->pSDDevice,SDCONFIG_FUNC_MASK_IRQ,NULL,0);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Unregistering GpsIrqHandler \n"));
++ SDDEVICE_SET_IRQ_HANDLER(pDevice->pSDDevice, NULL, NULL);
++
++ /* power down the hardware */
++ ZERO_OBJECT(fData);
++ fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
++ fData.TimeOut = 500;
++ SDLIB_IssueConfig(pDevice->pSDDevice,
++ SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData,
++ sizeof(fData));
++ }
++ }
++ pDevice->HwReady = FALSE;
++
++ SDLIB_IssueConfig(pDevice->pSDDevice,
++ SDCONFIG_FUNC_FREE_SLOT_CURRENT,
++ NULL,
++ 0);
++
++ if (pDevice->pRequest != NULL) {
++ SDDeviceFreeRequest(pDevice->pSDDevice, pDevice->pRequest);
++ pDevice->pRequest = NULL;
++ }
++ SemaphoreDelete(&pDevice->DeviceSem);
++}
++/*
++ * SetBaudRate - set the requested baud rate
++ */
++SDIO_STATUS SetBaudRate(PSDGPS_DEVICE pDevice, UINT32 BaudRate)
++{
++ UINT8 lineControl;
++ UINT8 saveInterrupt;
++ UINT32 divisor;
++
++ /* disable device interrupts */
++ ReadRegister(pDevice, UART_INT_ENABLE_REG, &saveInterrupt);
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, 0);
++ /* check for a valid baud rate */
++ if ((BaudRate % 1200) || (BaudRate > pDevice->UartMaxBaud)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: SetBaudRate, invalid rate %d\n", BaudRate));
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, saveInterrupt);
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ /* calculate new divisor based on 1200 baud divisor */
++ divisor = pDevice->UartDivisor / (BaudRate / 1200);
++
++ ReadRegister(pDevice, UART_LINE_CNTRL_REG, &lineControl);
++
++ WriteRegister(pDevice, UART_LINE_CNTRL_REG, lineControl | UART_CLOCK_ENABLE);
++ WriteRegister(pDevice, UART_BAUD_HIGH_REG, (UINT8)((divisor >> 8) & 0xFF));
++ WriteRegister(pDevice, UART_BAUD_LOW_REG, (UINT8)(divisor & 0xFF));
++ WriteRegister(pDevice, UART_LINE_CNTRL_REG, lineControl);
++
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, saveInterrupt);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: SetBaudRate, rate %d, divisor %d\n",
++ BaudRate, divisor));
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * GpsIRQHandler - hamdle interrupts
++*/
++void GpsIRQHandler(PVOID pContext)
++{
++ PSDGPS_DEVICE pDevice;
++ SDIO_STATUS status = SDIO_STATUS_DEVICE_ERROR;
++ UINT8 temp;
++ int max = 4;
++ pDevice = (PSDGPS_DEVICE)pContext;
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("+I\n"));
++
++ while(1) {
++ if (max-- < 0) break;
++ /* read the ident register */
++ status = ReadRegister(pDevice, UART_INT_IDENT_REG, &temp);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* INTPEND bit is zero indicates a pending interrupt */
++ if (!(temp & UART_INTPEND)) {
++ /* get the encoded interrupt value */
++ switch (temp & UART_IID_MASK) {
++ case UART_IID_RLS:
++ /* line status changed */
++ ReadRegister(pDevice, UART_LINE_STATUS_REG, &temp);
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("+LS 0x%X\n", (UINT)temp));
++ if (temp & UART_LSR_DR) {
++ GpsReceive(pDevice);
++ }
++ break;
++ case UART_IID_RDA:
++ /* handle receive */
++ GpsReceive(pDevice);
++ break;
++ case UART_IID_CTI:
++ /* receiver timeout? */
++ GpsReceive(pDevice);
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("+CTI\n"));
++ break;
++ case UART_IID_THRE:
++ /* transmitter empty */
++ GpsTransmit(pDevice);
++ break;
++ case UART_IID_MS:
++ /* modem status */
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("SDIO GPS Function: modem status change int \n"));
++ break;
++ default:
++ break;
++ }
++ } else {
++ /* no interrupts pending */
++ break;
++ }
++ }
++
++ /* ack the interrupt */
++ status = SDLIB_IssueConfig(pDevice->pSDDevice,SDCONFIG_FUNC_ACK_IRQ,NULL,0);
++
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("-I\n"));
++
++}
++
++/*
++ * WriteRegister - write an 8-bit register
++*/
++SDIO_STATUS WriteRegister(PSDGPS_DEVICE pDevice, UINT reg, UINT8 Data) {
++ return SDLIB_IssueCMD52(pDevice->pSDDevice,SDDEVICE_GET_SDIO_FUNCNO(pDevice->pSDDevice),
++ ((pDevice)->UartRegOffset + (reg)),&Data,1,TRUE);
++}
++
++/*
++ * WriteRegister - write an 8-bit register aysnchronously
++*/
++SDIO_STATUS WriteRegisterAsynch(PSDGPS_DEVICE pDevice, UINT reg, UINT8 Data, PSDREQUEST pReq)
++{
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ SDLIB_SetupCMD52Request(SDDEVICE_GET_SDIO_FUNCNO(pDevice->pSDDevice),
++ ((pDevice)->UartRegOffset + (reg)),
++ TRUE,
++ Data,
++ pReq);
++ pReq->Flags |= SDREQ_FLAGS_TRANS_ASYNC;
++ pReq->pCompletion = TxCompletion;
++ pReq->pCompleteContext = (PVOID)pDevice;
++
++ return SDDEVICE_CALL_REQUEST_FUNC(pDevice->pSDDevice, pReq);
++}
++
++/*
++ * TxCompletion - completion routine for WriteAsynch
++*/
++static void TxCompletion(PSDREQUEST pReq)
++{
++ /* nothing to do
++ PSDGPS_DEVICE pDevice;
++ pDevice = (PSDGPS_DEVICE)pReq->pCompleteContext;
++ */
++}
+Index: linux-2.6.22/drivers/sdio/function/gps/gps.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/gps/gps.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,194 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: gps.h
++
++ at abstract: OS independent include for GPS SDIO function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __GPS_H___
++#define __GPS_H___
++
++#include "gps_linux.h"
++
++typedef struct _SDGPS_DRIVER_CONTEXT {
++ SDFUNCTION Function; /* function description for bus driver */
++ PSDDEVICE pSDDevice; /* bus driver's device we are supporting (only 1) */
++ SDGPS_DEVICE GpsDevice; /* per device info, we only support one device right now */
++}SDGPS_DRIVER_CONTEXT, *PSDGPS_DRIVER_CONTEXT;
++
++#define SDIO_GPS_TRACE_INT (SDDBG_TRACE+1)
++
++#define GPS_CMD_52 52
++#define GPS_MAX_BAUD_RATE 115200
++#define GPS_FIFO_SIZE 16
++#define GPS_TYPE "SDIO GPS 16650"
++#define GPS_TUPLE 0x91
++
++struct SDIO_GPS_SUBTPL_SIOREG {
++ UINT8 RegisterID;
++ UINT8 RegisterExpID;
++ UINT8 RegisterOffset[3];
++ UINT8 MaxBaudRateCode;
++ UINT8 DRL_4800;
++ UINT8 DRM_4800;
++}__attribute__ ((packed));
++
++struct SDIO_GPS_SUBTPL_RCVCAPS {
++ UINT8 Junk; /* defined in some other doc */
++}__attribute__ ((packed));
++
++union GPS_TPL_DATA {
++ struct SDIO_GPS_SUBTPL_SIOREG AsSIOReg;
++ struct SDIO_GPS_SUBTPL_RCVCAPS AsRcvCaps;
++};
++
++ /* GPS tuple */
++struct SDIO_GPS_TPL {
++ UINT8 InterfaceCode;
++ UINT8 StdTupleNumber;
++#define STD_GPS_TUPLE_SIOREG 0x00
++#define STD_GPS_TUPLE_RCVCAP 0x01
++ union GPS_TPL_DATA Tpd;
++}__attribute__ ((packed));
++
++ /* 166550 UART register offsets */
++#define UART_RECEIVE_REG 0x00
++#define UART_SEND_REG 0x00
++#define UART_BAUD_LOW_REG 0x00
++#define UART_BAUD_HIGH_REG 0x01
++#define UART_INT_ENABLE_REG 0x01
++#define UART_INT_IDENT_REG 0x02
++#define UART_FIFO_CNTRL_REG 0x02
++#define UART_LINE_CNTRL_REG 0x03
++#define UART_MODEM_CONTROL_REG 0x04
++#define UART_LINE_STATUS_REG 0x05
++#define UART_MODEM_STATUS_REG 0x06
++#define UART_SCRATCH_REG 0x07
++
++ //INTERRUPT_STATUS_REG
++#define UART_UARTINT 0x80
++#define UART_RXWKINT 0x02
++
++ //INT_ENABLE_REG
++#define UART_EDSSI 0x08 /* enable modem status interrupt */
++#define UART_ELSI 0x04 /* enable receiver line status interrupt */
++#define UART_ETBEI 0x02 /* enable transmitter holding register empty int. */
++#define UART_ERBFI 0x01 /* enable received data available interrupt */
++
++ //INT_IDENT_REG
++#define UART_FIFO_ENABLED 0xC0
++#define UART_IID_RLS 0x06
++#define UART_IID_RDA 0x04
++#define UART_IID_CTI 0x0C
++#define UART_IID_THRE 0x02
++#define UART_IID_MS 0x00
++#define UART_INTPEND 0x01
++#define UART_IID_MASK 0x0F
++
++ //FIFO_CNTRL_REG
++#define UART_FIFO_ENABLE 0x01
++#define UART_FIFO_TRIGGER_1 0x00
++#define UART_FIFO_TRIGGER_4 0x40
++#define UART_FIFO_TRIGGER_8 0x80
++#define UART_FIFO_TRIGGER_14 0xC0
++#define UART_FIFO_XMIT_RESET 0x04
++#define UART_FIFO_RCV_RESET 0x02
++
++ //LINE_CNTRL_REG
++#define UART_CLOCK_ENABLE 0x80
++#define UART_SET_BREAK 0x40
++#define UART_EVEN_PARITY_SELECT 0x10
++#define UART_PARITY_ENABLE 0x08
++#define UART_NO_PARITY 0x00
++#define UART_NUM_STOP_BITS 0x04
++#define UART_ONE_STOP 0x00
++#define UART_DATA_8_BITS 0x03
++
++
++ //MODEM_CONTROL_REG
++#define UART_RTS_AUTO_FLOW 0x40
++#define UART_CTS_AUTO_FLOW 0x20
++#define UART_LOOP 0x10
++#define UART_TOUT2 0x08
++#define UART_TOUT1 0x04
++#define UART_RTS_ON 0x02
++#define UART_DTR_ON 0x01
++
++ //LINE_STATUS_REG
++#define UART_LSR_EIRF 0x80 /* error receive fifo */
++#define UART_LSR_TEMT 0x40
++#define UART_LSR_THRE 0x20 /* transmitter holding register empty */
++#define UART_LSR_BI 0x10
++#define UART_LSR_FE 0x08
++#define UART_LSR_PE 0x04
++#define UART_LSR_OE 0x02
++#define UART_LSR_DR 0x01
++
++ //MODEM_STATUS_REG
++#define UART_MSR_DCD 0x80
++#define UART_MSR_RI 0x40
++#define UART_MSR_DSR 0x20
++#define UART_MSR_CTS 0x10
++#define UART_MSR_DCTS 0x01
++
++ //UART_INIT_REG
++#define UART_UART_INIT 0xC7
++
++#define GPS_FIFO_SIZE 16
++
++/* prototypes */
++SDIO_STATUS IssueCMD52(PSDDEVICE pDevice,
++ UINT8 FuncNo,
++ UINT32 Address,
++ PUCHAR pData,
++ INT ByteCount,
++ BOOL Write);
++#define ReadRegister(pDev,reg,pData) \
++ SDLIB_IssueCMD52((pDev)->pSDDevice,SDDEVICE_GET_SDIO_FUNCNO((pDev)->pSDDevice),\
++ ((pDev)->UartRegOffset + (reg)),(pData),1,FALSE)
++SDIO_STATUS WriteRegister(PSDGPS_DEVICE pDevice, UINT reg, UINT8 Data);
++SDIO_STATUS WriteRegisterAsynch(PSDGPS_DEVICE pDevice, UINT reg, UINT8 Data, PSDREQUEST pReq);
++SDIO_STATUS GpsInitialize(PSDGPS_DEVICE pDevice);
++void GpsDeinitialize(PSDGPS_DEVICE pDevice);
++SDIO_STATUS GpsReceive(PSDGPS_DEVICE pDevice);
++SDIO_STATUS GpsTransmit(PSDGPS_DEVICE pDevice);
++SDIO_STATUS SetBaudRate(PSDGPS_DEVICE pDevice, UINT32 BaudRate);
++
++
++#endif /* __GPS_H___*/
++
+Index: linux-2.6.22/drivers/sdio/function/gps/gps_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/gps/gps_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,63 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: gps_linux.h
++
++ at abstract: OS dedependent include for GPS SDIO function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __GPS_LINUX_H___
++#define __GPS_LINUX_H___
++#include <linux/serial_reg.h>
++#include <linux/tty.h>
++#include <linux/serial.h>
++#include <linux/serial_core.h>
++
++typedef struct _SDGPS_DEVICE {
++ PSDDEVICE pSDDevice; /* the devices we are supporting */
++ BOOL HwReady; /* hardware is setup and ready */
++ struct uart_port Port; /* uart port support */
++ UINT32 UartRegOffset; /* UART register offset */
++ UINT32 UartMaxBaud; /* maximum allowable baud rate */
++ UINT16 UartDivisor; /* base divisor at 1200 baud*/
++ UINT8 InterruptEnable; /* state of IER register */
++ OS_SEMAPHORE DeviceSem; /* semaphore to protect the shadow registers and interrupts */
++ PSDREQUEST pRequest; /* allocate a request for asynch use */
++}SDGPS_DEVICE, *PSDGPS_DEVICE;
++
++
++#endif /* __GPS_LINUX_H___*/
+Index: linux-2.6.22/drivers/sdio/function/gps/gps_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/gps/gps_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,633 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: gps_os.c
++
++ at abstract: OS dependent GPS class SDIO function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++#define DBG_DECLARE 3;
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "gps.h"
++
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <linux/workqueue.h>
++
++#define DESCRIPTION "SDIO GPS Function Driver"
++#define AUTHOR "Atheros Communications, Inc."
++
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++int fixedbaud = 1;
++module_param(fixedbaud, int, 0644);
++MODULE_PARM_DESC(fixedbaud, "fixedbaud, if non-zero then no baud rate changes will be processed");
++
++
++static BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++static void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++static unsigned int gps_tx_empty(struct uart_port *port);
++static void gps_set_mctrl(struct uart_port *port, unsigned int mctrl);
++static unsigned int gps_get_mctrl(struct uart_port *port);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
++static void gps_stop_tx(struct uart_port *port);
++static void gps_start_tx(struct uart_port *port);
++#else
++static void gps_stop_tx(struct uart_port *port, unsigned int tty_stop);
++static void gps_start_tx(struct uart_port *port, unsigned int tty_start);
++#endif
++
++static void gps_stop_rx(struct uart_port *port);
++static void gps_enable_ms(struct uart_port *port);
++static void gps_break_ctl(struct uart_port *port, int break_state);
++static int gps_startup(struct uart_port *port);
++static void gps_shutdown(struct uart_port *port);
++static void gps_set_termios(struct uart_port *port, struct termios *termios,
++ struct termios *old);
++static void gps_pm(struct uart_port *port, unsigned int state, unsigned int oldstate);
++static const char *gps_type(struct uart_port *port);
++static void gps_release_port(struct uart_port *port);
++static int gps_request_port(struct uart_port *port);
++static void gps_config_port(struct uart_port *port, int flags);
++static int gps_verify_port(struct uart_port *port, struct serial_struct *ser);
++
++
++/* devices we support, null terminated */
++#define SDIO_GPS_CLASS 0x04
++static SD_PNP_INFO Ids[] = {
++ {.SDIO_FunctionClass = SDIO_GPS_CLASS}, /* SDIO-GPS SDIO standard interface code */
++ {}
++};
++
++static struct uart_ops sops = {
++ .tx_empty = gps_tx_empty,
++ .set_mctrl = gps_set_mctrl,
++ .get_mctrl = gps_get_mctrl,
++ .stop_tx = gps_stop_tx,
++ .start_tx = gps_start_tx,
++ .stop_rx = gps_stop_rx,
++ .enable_ms = gps_enable_ms,
++ .break_ctl = gps_break_ctl,
++ .startup = gps_startup,
++ .shutdown = gps_shutdown,
++ .set_termios = gps_set_termios,
++ .pm = gps_pm,
++ .type = gps_type,
++ .release_port = gps_release_port,
++ .request_port = gps_request_port,
++ .config_port = gps_config_port,
++ .verify_port = gps_verify_port,
++};
++
++/* the driver context data */
++static SDGPS_DRIVER_CONTEXT GpsContext = {
++ .Function.pName = "sdio_gps",
++ .Function.Version = CT_SDIO_STACK_VERSION_CODE,
++ .Function.MaxDevices = 1,
++ .Function.NumDevices = 0,
++ .Function.pIds = Ids,
++ .Function.pProbe = Probe,
++ .Function.pRemove = Remove,
++ .Function.pSuspend = NULL,
++ .Function.pResume = NULL,
++ .Function.pWake = NULL,
++ .Function.pContext = &GpsContext,
++ .GpsDevice.Port.type = PORT_16550,
++ .GpsDevice.Port.uartclk = GPS_MAX_BAUD_RATE*16,
++ .GpsDevice.Port.fifosize = GPS_FIFO_SIZE,
++ .GpsDevice.Port.line = 0,
++ .GpsDevice.Port.ops = &sops,
++};
++
++static struct uart_driver gps_uart = {
++ .owner = THIS_MODULE,
++ .driver_name = "ttyGPS", /* not sure if this is proper naming convention */
++ .dev_name = "ttyGPS",
++#ifdef CONFIG_DEVFS
++ .devfs_name = "ttygps",
++#endif
++ .major = 0, /*TTY_MAJOR,*/
++ .minor = 0, /*64,*/
++ .nr = 1,
++
++
++};
++
++
++
++/*
++ * Probe - a device potentially for us
++*/
++static BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice) {
++ PSDGPS_DRIVER_CONTEXT pFunctionContext =
++ (PSDGPS_DRIVER_CONTEXT)pFunction->pContext;
++ SYSTEM_STATUS err = 0;
++ SDIO_STATUS status;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Probe - enter\n"));
++
++ /* make sure this is a device we can handle */
++ if (pDevice->pId[0].SDIO_FunctionClass == pFunctionContext->Function.pIds[0].SDIO_FunctionClass) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Probe - card matched (0x%X/0x%X/0x%X)\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode,
++ pDevice->pId[0].SDIO_FunctionNo));
++ /* connect to the serial port driver */
++ pFunctionContext->pSDDevice = pDevice;
++ pFunctionContext->GpsDevice.pSDDevice = pDevice;
++ pFunctionContext->GpsDevice.HwReady = FALSE;
++
++ if (!SDIO_SUCCESS((status = GpsInitialize(&pFunctionContext->GpsDevice)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: Probe - could not initialize, %d\n", status));
++ return FALSE;
++ }
++ /* the port structure must be reset each time it is re-used */
++ ZERO_OBJECT(pFunctionContext->GpsDevice.Port);
++ pFunctionContext->GpsDevice.Port.type = PORT_16550;
++ pFunctionContext->GpsDevice.Port.uartclk = GPS_MAX_BAUD_RATE*16;
++ pFunctionContext->GpsDevice.Port.fifosize = GPS_FIFO_SIZE;
++ pFunctionContext->GpsDevice.Port.line = 0;
++ pFunctionContext->GpsDevice.Port.ops = &sops;
++ pFunctionContext->GpsDevice.Port.dev = SD_GET_OS_DEVICE(pDevice);
++ pFunctionContext->GpsDevice.Port.uartclk = pFunctionContext->GpsDevice.UartMaxBaud * 16;
++//?? snprintf(gps_uart->tty_driver.devfs_name,sizeof(gps_uart->tty_driver.devfs_name), "sdgps_%s",
++//?? (pFunctionContext->GpsDevice.Port.dev->bus_id);
++//?? /* remove any colons */
++//?? ReplaceChar(gps_uart->devfs_name, ':', '_');
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Probe - adding bus_id: %s, driver name: %s\n",
++ pFunctionContext->GpsDevice.Port.dev->bus_id, pFunctionContext->GpsDevice.Port.dev->driver->name));
++ err = uart_add_one_port(&gps_uart, &pFunctionContext->GpsDevice.Port);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: Probe - could not add uart port, %d\n", err));
++ return FALSE;
++ }
++ return TRUE;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Probe - not our card (0x%X/0x%X/0x%X)\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode,
++ pDevice->pId[0].SDIO_FunctionNo));
++ return FALSE;
++ }
++}
++
++/*
++ * Remove - our device is being removed
++*/
++void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice) {
++ PSDGPS_DRIVER_CONTEXT pFunctionContext =
++ (PSDGPS_DRIVER_CONTEXT)pFunction->pContext;
++ SYSTEM_STATUS err;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO GPS Function: Remove - enter\n"));
++
++ GpsDeinitialize(&pFunctionContext->GpsDevice);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: Remove - calling uart_remove_one_port\n"));
++ err = uart_remove_one_port(&gps_uart, &pFunctionContext->GpsDevice.Port);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: Remove - could not remove uart port, %d\n", err));
++ }
++ pFunctionContext->pSDDevice = NULL;
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO GPS Function: Remove - exit\n"));
++}
++
++/*
++ * gps_tx_empty - transmitter fifo and shifter is empty
++*/
++static unsigned int gps_tx_empty(struct uart_port *port)
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ UINT8 data;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_tx_empty - enter\n"));
++ ReadRegister(pDevice, UART_LINE_STATUS_REG, &data);
++ return (data & UART_LSR_TEMT)? TIOCSER_TEMT : 0;
++}
++
++/*
++ * gps_set_mctrl - set modem control line
++*/
++static void gps_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_set_mctrl - enter\n"));
++ return; /* fixed values */
++}
++
++/*
++ * gps_get_mctrl - get modem control line
++*/
++static unsigned int gps_get_mctrl(struct uart_port *port)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_get_mctrl - enter\n"));
++ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; /* fixed */
++}
++
++/*
++ * gps_stop_tx - stop output
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
++static void gps_stop_tx(struct uart_port *port)
++#else
++static void gps_stop_tx(struct uart_port *port, unsigned int tty_stop)
++#endif
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_stop_tx - enter\n"));
++ if (pDevice->InterruptEnable & UART_ETBEI) {
++ /* called with local ints disabled if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ return;
++ } */
++ pDevice->InterruptEnable &= ~UART_ETBEI;
++ WriteRegisterAsynch(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable, pDevice->pRequest);
++ /*SemaphorePost(&pDevice->DeviceSem);*/
++ }
++}
++
++/*
++ * gps_start_tx - start output
++*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
++static void gps_start_tx(struct uart_port *port)
++#else
++static void gps_start_tx(struct uart_port *port, unsigned int tty_start)
++#endif
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO GPS Function: gps_start_tx - enter\n"));
++ if (!(pDevice->InterruptEnable & UART_ETBEI)) {
++ /* called with local ints disabledif (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ return;
++ } */
++ pDevice->InterruptEnable |= UART_ETBEI;
++ WriteRegisterAsynch(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable, pDevice->pRequest);
++ /*SemaphorePost(&pDevice->DeviceSem);*/
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO GPS Function: gps_start_tx\n"));
++}
++
++/*
++ * gps_stop_rx - stop output
++*/
++static void gps_stop_rx(struct uart_port *port)
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_stop_rx - enter\n"));
++ /* called with local ints disabled if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ return;
++ } */
++ pDevice->InterruptEnable &= ~UART_ELSI;
++ WriteRegisterAsynch(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable, pDevice->pRequest);
++ /*SemaphorePost(&pDevice->DeviceSem);*/
++}
++
++/*
++ * gps_enable_ms - enable modem status interrupts
++*/
++static void gps_enable_ms(struct uart_port *port)
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_enable_ms - enter\n"));
++ /* called with local ints disabledif (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ return;
++ } */
++ pDevice->InterruptEnable |= UART_EDSSI;
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable);
++ /*SemaphorePost(&pDevice->DeviceSem);*/
++}
++
++/*
++ * gps_break_ctl - enable/disable breaks
++*/
++static void gps_break_ctl(struct uart_port *port, int break_state)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_break_ctl - enter\n"));
++}
++
++/*
++ * gps_startup - initialization
++*/
++static int gps_startup(struct uart_port *port)
++{
++ UINT8 temp;
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_startup - enter\n"));
++//?? if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++//?? return -EINTR;
++//?? }
++ /* read registers to clear status */
++ ReadRegister(pDevice, UART_LINE_STATUS_REG, &temp);
++ ReadRegister(pDevice, UART_RECEIVE_REG, &temp);
++ ReadRegister(pDevice, UART_INT_IDENT_REG, &temp);
++ ReadRegister(pDevice, UART_MODEM_STATUS_REG, &temp);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE | UART_FIFO_RCV_RESET);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE);
++ WriteRegister(pDevice, UART_LINE_CNTRL_REG, (UART_ONE_STOP | UART_NO_PARITY | UART_DATA_8_BITS));
++
++ pDevice->InterruptEnable = UART_ERBFI | UART_ELSI;
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable);
++//?? SemaphorePost(&pDevice->DeviceSem);
++ return 0;
++}
++
++/*
++ * gps_shutdown -
++*/
++static void gps_shutdown(struct uart_port *port)
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO GPS Function: gps_shutdown - enter\n"));
++ //??if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ //?? return;
++ //??}
++ pDevice->InterruptEnable = 0;
++ WriteRegister(pDevice, UART_INT_ENABLE_REG, pDevice->InterruptEnable);
++ //??SemaphorePost(&pDevice->DeviceSem);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO GPS Function: gps_shutdown\n"));
++}
++
++/*
++ * gps_set_termios - set data parameters
++*/
++static void gps_set_termios(struct uart_port *port, struct termios *termios,
++ struct termios *old)
++{
++ PSDGPS_DEVICE pDevice = CONTAINING_STRUCT(port, SDGPS_DEVICE, Port);
++ unsigned char cval = 0;
++ unsigned int baudrate;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_set_termios - enter\n"));
++
++ port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;//???
++
++ switch (termios->c_cflag & CSIZE) {
++ case CS5:
++ cval = 0x00;
++ break;
++ case CS6:
++ cval = 0x01;
++ break;
++ case CS7:
++ cval = 0x02;
++ break;
++ default:
++ case CS8:
++ cval = 0x03;
++ break;
++ }
++
++ cval |= (termios->c_cflag & PARENB)? UART_PARITY_ENABLE : 0;
++ cval |= (termios->c_cflag & CSTOPB)? UART_NUM_STOP_BITS : 0;
++ cval |= (!(termios->c_cflag & PARODD))? UART_EVEN_PARITY_SELECT : 0;
++ //?? WriteRegister(pDevice, UART_LINE_CNTRL_REG, cval);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: LCR 0x%X\n", cval));
++
++ /* get serial port to figure out the baud rate */
++ baudrate = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
++ DBG_ASSERT(baudrate != 0);
++ if (fixedbaud == 0) {
++ SetBaudRate(pDevice, baudrate);
++ uart_update_timeout(port, termios->c_cflag, baudrate);
++ }
++
++
++ //??do something about this locking
++ /* maybe called with local ints disabledif (!SDIO_SUCCESS(SemaphorePendInterruptable(&pDevice->DeviceSem))) {
++ return;
++ } */
++//?? pDevice->InterruptEnable &= ~UART_EDSSI;
++//?? if (UART_ENABLE_MS(&port, termios->c_cflag)) {
++//?? pDevice->InterruptEnable |= UART_EDSSI;
++//?? }
++ gps_set_mctrl(&pDevice->Port, pDevice->Port.mctrl);
++
++ /* SemaphorePost(&pDevice->DeviceSem);*/
++}
++
++/*
++ * gps_pm - power management
++*/
++static void gps_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_pm - state: %d\n", state));
++ return;
++}
++
++/*
++ * gps_type - retrieve type string
++*/
++static const char *gps_type(struct uart_port *port)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_type - enter\n"));
++ return GPS_TYPE;
++}
++
++/*
++ * gps_release_port - release resources
++*/
++static void gps_release_port(struct uart_port *port)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_release_port - enter\n"));
++ return;
++}
++
++/*
++ * gps_request_port - request resources
++*/
++static int gps_request_port(struct uart_port *port)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_request_port - enter\n"));
++ return 0;
++}
++
++/*
++ * gps_config_port - auto configuration
++*/
++static void gps_config_port(struct uart_port *port, int flags)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_config_port - enter\n"));
++ return;
++}
++
++/*
++ * gps_verify_port - verify configuration of port
++*/
++static int gps_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: gps_verify_port - enter\n"));
++ return 0;
++}
++
++/*
++ * GpsReceive
++*/
++SDIO_STATUS GpsReceive(PSDGPS_DEVICE pDevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 statusReg;
++ UINT8 inChar;
++ UINT maxCount = 64;
++ struct uart_port *port = &pDevice->Port;
++ struct tty_struct *tty;
++
++ tty = ((port == NULL) || (port->info == NULL)) ? NULL : port->info->tty;
++ /* if we aren't ready, just clear out the incoming char */
++ if ((port == NULL) || (tty == NULL)) {
++ ReadRegister(pDevice, UART_RECEIVE_REG, &inChar);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE | UART_FIFO_RCV_RESET);
++ WriteRegister(pDevice, UART_FIFO_CNTRL_REG, UART_DATA_8_BITS | UART_FIFO_ENABLE);
++ DBG_PRINT(SDIO_GPS_TRACE_INT, ("+RX%X\n", (UINT)inChar));
++ return status;
++ }
++
++ for (status = ReadRegister(pDevice, UART_LINE_STATUS_REG, &statusReg);
++ SDIO_SUCCESS(status) && (statusReg & UART_LSR_DR) &&
++ (maxCount-- > 0);
++ status = ReadRegister(pDevice, UART_LINE_STATUS_REG, &statusReg))
++ {
++
++ ReadRegister(pDevice, UART_RECEIVE_REG, &inChar);
++
++ if (status & UART_LSR_OE) {
++ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
++ DBG_PRINT(SDDBG_WARN, ("SDIO GPS Function: GpsReceive overrun\n"));
++ break;
++ }
++
++ tty_insert_flip_char(tty, inChar, 0);
++ udelay(1);
++ }
++ tty_flip_buffer_push(tty);
++
++ return status;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
++#define GPS_STOP_TX(p) gps_stop_tx((p))
++#else
++#define GPS_STOP_TX(p) gps_stop_tx((p),0)
++#endif
++
++/*
++ * GpsTransmit
++*/
++SDIO_STATUS GpsTransmit(PSDGPS_DEVICE pDevice)
++{
++ UINT ii;
++ struct uart_port *port = &pDevice->Port;
++ struct circ_buf *xmit;
++
++ xmit = ((port == NULL) || (port->info == NULL)) ? NULL : &port->info->xmit;
++ /* if we aren't ready, just clear interrupt */
++ if (xmit == NULL) {
++ GPS_STOP_TX(port);
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
++ GPS_STOP_TX(port);
++ return SDIO_STATUS_SUCCESS;
++ }
++
++ for(ii = 0; ii < GPS_FIFO_SIZE; ii++) {
++ WriteRegister(pDevice, UART_TX, xmit->buf[xmit->tail]);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ port->icount.tx++;
++ if (uart_circ_empty(xmit)) {
++ break;
++ }
++
++ }
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
++ uart_write_wakeup(port);
++ }
++ if (uart_circ_empty(xmit)) {
++ GPS_STOP_TX(port);
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * module init
++*/
++static int __init sdio_gps_init(void) {
++ SDIO_STATUS status;
++ SYSTEM_STATUS err;
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO GPS Function: init\n"));
++ /* register with the serial driver core */
++ err = uart_register_driver(&gps_uart);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: failed to register with uart driver, %d\n", err));
++ return err;
++ }
++ /* register with bus driver core */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterFunction(&GpsContext.Function)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO GPS Function: failed to register with bus driver, %d\n", status));
++ uart_unregister_driver(&gps_uart);
++ return SDIOErrorToOSError(status);
++ }
++ return err;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_gps_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO GPS Function: : cleanup\n"));
++ SDIO_UnregisterFunction(&GpsContext.Function);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: SDIO unregistered\n"));
++ /* unregister with the serial driver core */
++ uart_unregister_driver(&gps_uart);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO GPS Function: UART unregistered\n"));
++}
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++module_init(sdio_gps_init);
++module_exit(sdio_gps_cleanup);
+Index: linux-2.6.22/drivers/sdio/function/bluetooth/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/bluetooth/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO bluetooth functiondriver
++#
++obj-m += sdio_bluetooth_fd.o
++sdio_bluetooth_fd-objs := sdio_bt.o sdio_bt_os.o
+Index: linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,769 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bt.c
++
++ at abstract: Bluetooth SDIO driver
++
++#notes: includes OS independent portions
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_bt.h"
++
++static void BTIRQHandler(PVOID pContext);
++#define BLOCK_WRITE TRUE
++#define BLOCK_READ FALSE
++static SDIO_STATUS ReceiveHciPacket(PBT_HCI_INSTANCE pHci);
++static void BtTxCompletion(PSDREQUEST pReq);
++
++UINT32 SetRequestParam(PBT_HCI_INSTANCE pHci,
++ UINT32 BytesToSend,
++ PSDREQUEST pReq,
++ BOOL Write);
++
++/* delete an instance */
++void DeleteHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PBT_HCI_INSTANCE pHci)
++{
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++ SDIO_STATUS status;
++
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pFuncContext->InstanceSem))) {
++ return;
++ }
++ /* pull it out of the list */
++ SDListRemove(&pHci->SDList);
++ SemaphorePost(&pFuncContext->InstanceSem);
++
++ if (!(SDDEVICE_IS_CARD_REMOVED(pHci->pDevice))) {
++ if (pHci->Flags & FLAGS_CARD_IRQ_UNMSK) {
++ SDDEVICE_SET_IRQ_HANDLER(pHci->pDevice, NULL, NULL);
++ /* mask our IRQ */
++ status = SDLIB_IssueConfig(pHci->pDevice,SDCONFIG_FUNC_MASK_IRQ,NULL,0);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to unmask IRQ err:%d \n", status));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: IRQ disabled \n"));
++ }
++ }
++ /* disable the card */
++ if (pHci->Flags & FLAGS_CARD_ENAB) {
++ ZERO_OBJECT(fData);
++ fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
++ fData.TimeOut = SDBT_ENABLE_DISABLE_TIMEOUT;
++ status = SDLIB_IssueConfig(pHci->pDevice,
++ SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData,
++ sizeof(fData));
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to disable card: %d\n", status));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Card Disabled \n"));
++ }
++ }
++
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Card removed \n"));
++ }
++
++ SDLIB_IssueConfig(pHci->pDevice,
++ SDCONFIG_FUNC_FREE_SLOT_CURRENT,
++ NULL,
++ 0);
++
++ KernelFree(pHci);
++}
++
++/* create a Hci instance */
++PBT_HCI_INSTANCE CreateHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PSDDEVICE pDevice)
++{
++ PBT_HCI_INSTANCE pHci = NULL;
++ UINT32 nextTpl;
++ UINT8 tplLength;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ struct PKT_RETRY_CONTROL_TUPLE rtcTuple;
++ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
++ SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
++
++ ZERO_OBJECT(slotCurrent);
++ ZERO_OBJECT(fData);
++
++ do {
++ pHci = (PBT_HCI_INSTANCE)KernelAlloc(sizeof(BT_HCI_INSTANCE));
++ if (NULL == pHci) {
++ break;
++ }
++ ZERO_POBJECT(pHci);
++ SDLIST_INIT(&pHci->SDList);
++ pHci->pDevice = pDevice;
++
++ pHci->FuncNo = SDDEVICE_GET_SDIO_FUNCNO(pHci->pDevice);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT HCI Function Instance: 0x%Xn Fn:%d \n",(INT)pHci,
++ pHci->FuncNo));
++
++ if (SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(pHci->pDevice) == 0) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Function does not support Block Mode! \n"));
++ status = SDIO_STATUS_ERROR;
++ break;
++ }
++ /* limit block size to operational block limit or card function capability*/
++ pHci->MaxBlockSize = min(SDDEVICE_GET_OPER_BLOCK_LEN(pHci->pDevice),
++ SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(pHci->pDevice));
++
++ /* check if the card support multi-block transfers */
++ if (!(SDDEVICE_GET_SDIOCARD_CAPS(pHci->pDevice) & SDIO_CAPS_MULTI_BLOCK)) {
++ pHci->Flags |= FLAGS_BYTE_BASIS;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Byte basis only \n"));
++ /* limit block size to max byte basis */
++ pHci->MaxBlockSize = min(pHci->MaxBlockSize,
++ (UINT16)SDIO_MAX_LENGTH_BYTE_BASIS);
++ pHci->MaxBlocks = 1;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Multi-block capable \n"));
++ pHci->MaxBlocks = SDDEVICE_GET_OPER_BLOCKS(pHci->pDevice);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Bytes Per Block: %d bytes, Block Count:%d \n",
++ pHci->MaxBlockSize,
++ pHci->MaxBlocks));
++
++ status = SDLIB_GetDefaultOpCurrent(pDevice, &slotCurrent.SlotCurrent);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Allocating Slot current: %d mA\n", slotCurrent.SlotCurrent));
++ status = SDLIB_IssueConfig(pDevice,
++ SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
++ &slotCurrent,
++ sizeof(slotCurrent));
++
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: failed to allocate slot current %d\n",
++ status));
++ if (status == SDIO_STATUS_NO_RESOURCES) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Remaining Slot Current: %d mA\n",
++ slotCurrent.SlotCurrent));
++ }
++ break;
++ }
++
++ nextTpl = SDDEVICE_GET_SDIO_FUNC_CISPTR(pHci->pDevice);
++ tplLength = sizeof(rtcTuple);
++ status = SDLIB_FindTuple(pHci->pDevice,
++ CISTPL_VENDOR,
++ &nextTpl,
++ (PUINT8)&rtcTuple,
++ &tplLength);
++ if (SDIO_SUCCESS(status)) {
++ pHci->Flags |= FLAGS_RTC_SUPPORTED;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Retry protocol supported \n"));
++ if (!(rtcTuple.SDIO_RetryControl & RTC_READ_ACK_NOT_REQUIRED)) {
++ pHci->Flags |= FLAGS_READ_ACK;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Read Acknowledgements required \n"));
++ }
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO BT Function: No RTC Tuple, retry not supported \n"));
++ status = SDIO_STATUS_SUCCESS;
++ }
++
++ /* now enable the card */
++ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
++ fData.TimeOut = SDBT_ENABLE_DISABLE_TIMEOUT;
++ status = SDLIB_IssueConfig(pHci->pDevice,
++ SDCONFIG_FUNC_ENABLE_DISABLE,
++ &fData,
++ sizeof(fData));
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: failed to enable function Err:%d\n", status));
++ break;
++ }
++ pHci->Flags |= FLAGS_CARD_ENAB;
++
++ if (!(pHci->Flags & FLAGS_BYTE_BASIS)) {
++ /* for cards that support multi-block transfers, set the block size */
++ status = SDLIB_SetFunctionBlockSize(pHci->pDevice,
++ pHci->MaxBlockSize);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to set block size. Err:%d\n", status));
++ break;
++ }
++ }
++ /* if it was Type-B card, put it in Type-A mode */
++ if (SDDEVICE_GET_SDIO_FUNC_CLASS(pHci->pDevice) == 0x03) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Type B card detected, switch to type A mode \n"));
++ status = WriteRegister(pHci,MODE_STATUS_REG,MODE_STATUS_TYPE_A);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to switch to type A mode \n"));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: TYPE A Mode switched \n"));
++ }
++
++ if (pHci->Flags & FLAGS_READ_ACK) {
++ status = WriteRegister(pHci,RETRY_CONTROL_STATUS_REG,RETRY_CONTROL_STATUS_USE_ACKS);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to set retry control to use acks \n"));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Read acks enabled \n"));
++ status = WriteRegister(pHci,RECV_PACKET_CONTROL_REG,RECV_PACKET_CONTROL_ACK);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to set issue read ack \n"));
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: Read ack issued \n"));
++ }
++
++ SDDEVICE_SET_IRQ_HANDLER(pHci->pDevice,BTIRQHandler,pHci);
++ /* unmask our function IRQ */
++ status = SDLIB_IssueConfig(pHci->pDevice,SDCONFIG_FUNC_UNMASK_IRQ,NULL,0);
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: failed to unmask IRQ Err:%d\n", status));
++ break;
++ }
++ pHci->Flags |= FLAGS_CARD_IRQ_UNMSK;
++
++ /* enable packet ready interrupt */
++ status = WriteRegister(pHci,INTERRUPT_ENABLE_REG,RCV_PKT_PENDING_ENABLE);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO BT Function: IRQ enabled - ready \n"));
++#if 0 // test command
++ {
++ UCHAR data[7] = {0x07,0x00,0x00,0x01,0x03,0x10,0x00};
++ PSDREQUEST pReq = NULL;
++
++ /* allocate request to send to host controller */
++ pReq = SDDeviceAllocRequest(pHci->pDevice);
++ if (NULL == pReq) {
++ break;
++ }
++
++ SetRequestParam(pHci,
++ 7,
++ pReq,
++ TRUE);
++
++ pReq->Flags &= ~SDREQ_FLAGS_TRANS_ASYNC;
++ pReq->pCompletion =NULL;
++ pReq->pCompleteContext = NULL;
++ pReq->pDataBuffer = data;
++
++ SDLIB_PrintBuffer(data,7,
++ "Sending first BT command...");
++ status = SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO BT - TEST: Synch CMD53 write failed %d \n",
++ status));
++ }
++
++ SDDeviceFreeRequest(pHci->pDevice,pReq);
++ }
++#endif
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status) && (pHci != NULL)) {
++ DeleteHciInstance(pFuncContext, pHci);
++ pHci = NULL;
++ }
++
++ return pHci;
++}
++
++/* find an instance associated with the SD device */
++PBT_HCI_INSTANCE FindHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PSDDEVICE pDevice)
++{
++ SDIO_STATUS status;
++ PSDLIST pItem;
++ PBT_HCI_INSTANCE pHci = NULL;
++
++ status = SemaphorePendInterruptable(&pFuncContext->InstanceSem);
++ if (!SDIO_SUCCESS(status)) {
++ return NULL;
++ }
++ /* walk the list and find our instance */
++ SDITERATE_OVER_LIST(&pFuncContext->InstanceList, pItem) {
++ pHci = CONTAINING_STRUCT(pItem, BT_HCI_INSTANCE, SDList);
++ if (pHci->pDevice == pDevice) {
++ /* found it */
++ break;
++ }
++ pHci = NULL;
++ }
++
++ SemaphorePost(&pFuncContext->InstanceSem);
++ return pHci;
++}
++
++/* add an instance to our list */
++SDIO_STATUS AddHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PBT_HCI_INSTANCE pHci)
++{
++ SDIO_STATUS status;
++
++ status = SemaphorePendInterruptable(&pFuncContext->InstanceSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ SDListAdd(&pFuncContext->InstanceList,&pHci->SDList);
++ SemaphorePost(&pFuncContext->InstanceSem);
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++static void BTIRQHandler(PVOID pContext)
++{
++ PBT_HCI_INSTANCE pHci;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT8 temp;
++
++ DBG_PRINT(SDBT_DBG_RECEIVE, ("SDIO BT IRQ \n"));
++
++ pHci = (PBT_HCI_INSTANCE)pContext;
++
++ while (1) {
++
++ status = ReadRegister(pHci,INTERRUPT_STATUS_CLEAR_REG,&temp);
++ if (!SDIO_SUCCESS(status)) {
++ /* can't read it for some reason */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to read int status, err:%d\n", status));
++ break;
++ }
++
++ if (!(temp & RCV_PKT_PENDING)) {
++ break;
++ }
++ /* clear the status */
++ status = WriteRegister(pHci,INTERRUPT_STATUS_CLEAR_REG,RCV_PKT_PENDING);
++
++ if (!SDIO_SUCCESS(status)) {
++ /* can't clear it for some reason */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Failed to clear int status, err:%d\n", status));
++ break;
++ }
++
++ status = ReceiveHciPacket(pHci);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ /* mask the interrupt if we can't handle them */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: FATAL Error detected in IRQ processing , err:%d\n", status));
++ WriteRegister(pHci,INTERRUPT_ENABLE_REG,0);
++ }
++ /* ack the interrupt */
++ SDLIB_IssueConfig(pHci->pDevice,SDCONFIG_FUNC_ACK_IRQ,NULL,0);
++}
++
++/* set the request parameters in a request
++ * This does not set the pDataBuffer field */
++UINT32 SetRequestParam(PBT_HCI_INSTANCE pHci,
++ UINT32 BytesToSend,
++ PSDREQUEST pReq,
++ BOOL Write)
++{
++ UINT32 bytesToTransfer;
++
++ pReq->Command = CMD53;
++ pReq->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS;
++ if (Write) {
++ /* do write in non-blocking fashion */
++ /* note, that read-operations are performed in our normal IRQ handler which
++ * allows synchronous operations */
++ pReq->Flags |= (SDREQ_FLAGS_DATA_WRITE | SDREQ_FLAGS_TRANS_ASYNC);
++ pReq->pCompletion = BtTxCompletion;
++ pReq->pCompleteContext = (PVOID)pHci;
++ }
++
++ if ((pHci->Flags & FLAGS_BYTE_BASIS) || (BytesToSend < pHci->MaxBlockSize)) {
++ /* byte basis */
++ bytesToTransfer = min((UINT32)pHci->MaxBlockSize, BytesToSend);
++ SDIO_SET_CMD53_ARG(pReq->Argument,
++ (Write ? CMD53_WRITE : CMD53_READ),
++ pHci->FuncNo,
++ CMD53_BYTE_BASIS,
++ CMD53_FIXED_ADDRESS,
++ (Write ? XMIT_DATA_REG : RECV_DATA_REG),
++ CMD53_CONVERT_BYTE_BASIS_BLK_LENGTH_PARAM(bytesToTransfer));
++ pReq->BlockCount = 1;
++ pReq->BlockLen = bytesToTransfer;
++ if (pReq->BlockLen < 8) {
++ pReq->Flags |= SDREQ_FLAGS_DATA_SHORT_TRANSFER;
++ }
++ } else {
++ /* block mode */
++ pReq->BlockLen = pHci->MaxBlockSize;
++ /* get block counts (whole blocks, no partials allowed) */
++ pReq->BlockCount = min(BytesToSend / (UINT32)pHci->MaxBlockSize, (UINT32)pHci->MaxBlocks);
++ DBG_ASSERT(pReq->BlockCount != 0);
++ /* calculate total transfer to return */
++ bytesToTransfer = pReq->BlockCount * pReq->BlockLen;
++ /* set argument */
++ SDIO_SET_CMD53_ARG(pReq->Argument,
++ (Write ? CMD53_WRITE : CMD53_READ),
++ pHci->FuncNo,
++ CMD53_BLOCK_BASIS,
++ CMD53_FIXED_ADDRESS,
++ (Write ? XMIT_DATA_REG : RECV_DATA_REG),
++ CMD53_CONVERT_BLOCK_BASIS_BLK_COUNT_PARAM(pReq->BlockCount));
++ }
++
++ return bytesToTransfer;
++}
++
++static INLINE UINT32 AdjustBytesForHC(PBT_HCI_INSTANCE pHci, UINT32 RemainingBytes) {
++
++ if (pHci->BlockTransferFix) {
++ /* some host controllers (like the PXA25x) do not support 1 and 3 byte transfers
++ * we are trying to avert a 1 or 3 byte block transfer
++ * unfortunately not all SDIO BT cards allow CMD52 operations on the data port
++ * so we have to "look ahead" and prevent a small block transfer by dividing the
++ * current chunk */
++ if (((RemainingBytes % pHci->MaxBlockSize) == 1) ||
++ ((RemainingBytes % pHci->MaxBlockSize) == 3)) {
++ /* divide by two, this should split the remaining bytes into something
++ * manageable */
++ DBG_PRINT(SDDBG_WARN, ("SDIO BT - adjusting %d bytes (max blocks: %d) \n",
++ RemainingBytes,pHci->MaxBlockSize));
++ return (RemainingBytes >> 1);
++ }
++ return RemainingBytes;
++ }
++ /* no adjustment required */
++ return RemainingBytes;
++}
++
++static INLINE void SetUpNextTxBlocTransfer(PBT_HCI_INSTANCE pHci,
++ PSDREQUEST pReq) {
++ pHci->pTxBufferPosition += pHci->TxBytesToTransfer;
++ pHci->TxRemaining -= pHci->TxBytesToTransfer;
++ if (pHci->TxRemaining) {
++ /* set where we are */
++ pReq->pDataBuffer = pHci->pTxBufferPosition;
++ /* set up parameters for the request */
++ pHci->TxBytesToTransfer = SetRequestParam(pHci,
++ AdjustBytesForHC(pHci,pHci->TxRemaining),
++ pReq,
++ BLOCK_WRITE);
++ }
++}
++
++static INLINE void ResetCurrentTxPacketTransfer(PBT_HCI_INSTANCE pHci) {
++ pHci->pTxBufferPosition = SDBTHCI_GET_PKT_BUFFER(pHci->pCurrentTxPacket);
++ pHci->TxRemaining = SDBTHCI_GET_PKT_LENGTH(pHci->pCurrentTxPacket);
++ pHci->TxBytesToTransfer = 0;
++}
++
++static void BtTxCompletion(PSDREQUEST pReq)
++{
++ PBT_HCI_INSTANCE pHci;
++ SDIO_STATUS status;
++ BOOL done = FALSE;
++
++ pHci = (PBT_HCI_INSTANCE)pReq->pCompleteContext;
++ DBG_ASSERT(pHci != NULL);
++ status = pReq->Status;
++
++ switch (pHci->TxState) {
++ case TX_BLOCK_PROCESSING:
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: XMIT Failed, Err:%d \n", status));
++ /* check for retry */
++ if (pHci->Flags & FLAGS_RTC_SUPPORTED) {
++ pHci->TxRetry--;
++ if (pHci->TxRetry) {
++ pHci->TxState = TX_PACKET_RETRY;
++ /* setup request for async CMD52 */
++ SDLIB_SetupCMD52RequestAsync((pHci)->FuncNo,
++ XMIT_PACKET_CONTROL_REG,
++ CMD52_DO_WRITE,
++ XMIT_PKT_CONTROL_RETRY,
++ pReq);
++ /* set completion routine */
++ pReq->pCompletion = BtTxCompletion;
++ pReq->pCompleteContext = (PVOID)pHci;
++ /* submit */
++ SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: XMIT retries exceeded \n"));
++ done = TRUE;
++ break;
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Card does not support retries! \n"));
++ done = TRUE;
++ }
++ } else {
++ /* set it up for the next transfer */
++ SetUpNextTxBlocTransfer(pHci,pReq);
++ /* are we done? */
++ if (pHci->TxRemaining) {
++ /* submit request asynchronously */
++ SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++ } else {
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO BT Function: TX Packet 0x%X sent \n",
++ (INT)pHci->pCurrentTxPacket));
++ done = TRUE;
++ }
++ }
++ break;
++ case TX_PACKET_RETRY:
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BT Function: Failed to set TX packet retry control, Err:%d \n", status));
++ done = TRUE;
++ break;
++ }
++ if (SD_R5_GET_RESP_FLAGS(pReq->Response) & SD_R5_ERRORS) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BT Function: CMD52 failed in TX retry control \n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ done = TRUE;
++ break;
++ }
++ ResetCurrentTxPacketTransfer(pHci);
++ pHci->TxState = TX_BLOCK_PROCESSING;
++ /* setup block transfer */
++ SetUpNextTxBlocTransfer(pHci,pReq);
++ /* submit request asynchronously */
++ SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ if (done) {
++ OSIndicateHCIPacketTransmitDone(pHci,status);
++ OSFreeSDRequest(pHci, pReq);
++ }
++}
++
++
++
++/* send the hci packet asynchronously the caller handles the header and packet queues and sets the
++ * pCurrentPacket field for the packet ready to go out */
++SDIO_STATUS SendHciPacket(PBT_HCI_INSTANCE pHci)
++{
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ PSDREQUEST pReq;
++
++ do {
++ DBG_ASSERT(pHci->pCurrentTxPacket != NULL);
++ pReq = OSAllocSDRequest(pHci);
++
++ if (NULL == pReq) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: No SD requests remaining \n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ pHci->TxRetry = SDBT_PKT_RETRIES;
++ ResetCurrentTxPacketTransfer(pHci);
++ pHci->TxState = TX_BLOCK_PROCESSING;
++ /* setup block transfer */
++ SetUpNextTxBlocTransfer(pHci,pReq);
++
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO BT Function: BlockLen:%d,BlockCount:%d, Arg:0x%X \n",
++ pReq->BlockLen, pReq->BlockCount,pReq->Argument));
++ /* submit request asynchronously */
++ SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ OSIndicateHCIPacketTransmitDone(pHci,status);
++ }
++
++ return status;
++}
++
++static SDIO_STATUS ReceiveHciPacket(PBT_HCI_INSTANCE pHci)
++{
++ SDIO_STATUS status;
++ PSDBT_HCI_PACKET pPacket = NULL;
++ UINT8 header[SDIO_BT_TRANSPORT_HEADER_LENGTH];
++ PSDREQUEST pReq;
++ UINT32 bytesToTransfer;
++ UINT32 remaining;
++ PUINT8 pBufferLoc;
++
++ pReq = OSAllocSDRequest(pHci);
++
++ if (NULL == pReq) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: No SD requests remaining \n"));
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ do{
++ pReq->pDataBuffer = header;
++ SetRequestParam(pHci,AdjustBytesForHC(pHci,sizeof(header)),pReq,BLOCK_READ);
++ /* go get the header */
++ status = SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: failed to get header, Err:%d\n", status));
++ break;
++ }
++
++ remaining = SDIO_BT_GET_LENGTH(header);
++ if (remaining <= SDIO_BT_TRANSPORT_HEADER_LENGTH) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Invalid Length:%d \n", remaining));
++ break;
++ }
++
++ if (DBG_GET_DEBUG_LEVEL() >= SDBT_DBG_RECEIVE) {
++ SDLIB_PrintBuffer(header,sizeof(header),"SDIO BT, header dump \n");
++ }
++ switch (SDIO_BT_GET_SERVICEID(header)) {
++ case SDIO_BT_TYPE_A_HCI_EVT:
++ case SDIO_BT_TYPE_A_HCI_ACL:
++ case SDIO_BT_TYPE_A_HCI_SCO:
++ break;
++ default:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Invalid packet type:%d \n",
++ SDIO_BT_GET_SERVICEID(header)));
++ status = SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* subtract off header */
++ remaining -= SDIO_BT_TRANSPORT_HEADER_LENGTH;
++ /* get a buffer for this HCI packet */
++ pPacket = OSAllocHCIRcvPacket(pHci,
++ remaining,
++ SDIO_BT_GET_SERVICEID(header));
++ if (NULL == pPacket) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: failed to allocate packet \n"));
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ DBG_PRINT(SDBT_DBG_RECEIVE, ("SDIO BT Function: Getting HCI Packet (type:%d, Length:%d) \n",
++ SDIO_BT_GET_SERVICEID(header),remaining));
++
++ pBufferLoc = SDBTHCI_GET_PKT_BUFFER(pPacket);
++
++ while (remaining) {
++ /* set where we are */
++ pReq->pDataBuffer = pBufferLoc;
++ /* set up parameters for the request */
++ bytesToTransfer = SetRequestParam(pHci,AdjustBytesForHC(pHci,remaining),pReq,BLOCK_READ);
++ /* submit request synchronously */
++ status = SDDEVICE_CALL_REQUEST_FUNC(pHci->pDevice,pReq);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Rcv Failed, Err:%d \n", status));
++ break;
++ }
++
++ pBufferLoc += bytesToTransfer;
++ remaining -= bytesToTransfer;
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ /* free this packet */
++ OSFreeHciRcvPacket(pHci, pPacket);
++ if (pHci->Flags & FLAGS_RTC_SUPPORTED) {
++ pHci->RxRetry++;
++ if (pHci->RxRetry > MAX_RX_RETRY) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BT Function: RX Retry Exceeded \n"));
++ break;
++ }
++ /* set bit to discard this packet, we need to start over */
++ status = WriteRegister(pHci,RECV_PACKET_CONTROL_REG,RCV_PKT_CONTROL_RETRY);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BT Function: failed to set RCV PKT RETRY, err:%d \n", status));
++ }
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO BT Function: Card does not support retries! \n"));
++ }
++ break;
++ } else {
++ /* reset retry on good packets */
++ pHci->RxRetry = 0;
++ DBG_PRINT(SDBT_DBG_RECEIVE, ("SDIO BT Function: Packet received --\n"));
++ if (DBG_GET_DEBUG_LEVEL() >= SDBT_DBG_RECEIVE) {
++ SDLIB_PrintBuffer(SDBTHCI_GET_PKT_BUFFER(pPacket),
++ (SDIO_BT_GET_LENGTH(header) - SDIO_BT_TRANSPORT_HEADER_LENGTH),
++ "Received HCI Packet Dump");
++ }
++ /* indicate the packet */
++ OSIndicateHCIPacketReceived(pHci,
++ pPacket,
++ (SDIO_BT_GET_LENGTH(header) - SDIO_BT_TRANSPORT_HEADER_LENGTH),
++ SDIO_BT_GET_SERVICEID(header));
++ /* we no longer own this packet */
++ pPacket = NULL;
++ if (pHci->Flags & FLAGS_READ_ACK) {
++ /* ack the hardware indicating we pulled the packet out */
++ status = WriteRegister(pHci,RECV_PACKET_CONTROL_REG,RECV_PACKET_CONTROL_ACK);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO BT Function: failed to set ACK Packet, err:%d \n", status));
++ break;
++ } else {
++ DBG_PRINT(SDBT_DBG_RECEIVE, ("SDIO BT Function: RCV Packet Ack'd \n"));
++ }
++ }
++ }
++ }while(FALSE);
++
++
++ OSFreeSDRequest(pHci, pReq);
++
++ return status;
++}
++
+Index: linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,176 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bt.h
++
++ at abstract: OS independent include Bluetooth function driver
++
++#notes:
++
++ at notice: Copyright (c), 2005-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_BT_H___
++#define __SDIO_BT_H___
++
++#include "sdio_bt_linux.h"
++
++#define SDBT_DBG_TRANSMIT (SDDBG_TRACE + 1)
++#define SDBT_DBG_RECEIVE (SDDBG_TRACE + 2)
++
++#define FLAGS_RTC_SUPPORTED 0x01 /* re-try control protocol supported */
++#define FLAGS_BYTE_BASIS 0x02 /* byte basis transfer of packets */
++#define FLAGS_READ_ACK 0x04 /* requires read acknowledgements */
++#define FLAGS_CARD_ENAB 0x08
++#define FLAGS_CARD_IRQ_UNMSK 0x10
++
++#define SDBT_ENABLE_DISABLE_TIMEOUT 2000
++#define SDBT_PKT_RETRIES 3
++
++typedef enum _BTHCI_TX_STATES {
++ TX_BLOCK_PROCESSING = 0,
++ TX_PACKET_RETRY = 1
++}BTHCI_TX_STATES, *PBTHCI_TX_STATES;
++
++typedef struct _BT_HCI_INSTANCE {
++ SDLIST SDList; /* hcd list entry */
++ PSDDEVICE pDevice; /* bus driver's device we are supporting */
++ UINT8 FuncNo; /* function number we are on */
++ SDBT_CONFIG Config; /* devices local data */
++ UINT8 Flags; /* operational flags */
++ UINT16 MaxBlockSize; /* max block size for transfers */
++ UINT16 MaxBlocks; /* max blocks for transfers (multi-block) */
++ PSDBT_HCI_PACKET pCurrentTxPacket;
++ PUINT8 pTxBufferPosition;
++ UINT32 TxRemaining;
++ UINT32 RxRemaining;
++ UINT32 TxBytesToTransfer;
++ UINT8 TxRetry;
++ BTHCI_TX_STATES TxState;
++ UINT8 RxRetry;
++ BOOL BlockTransferFix;
++}BT_HCI_INSTANCE, *PBT_HCI_INSTANCE;
++
++typedef struct _BT_FUNCTION_CONTEXT {
++ SDFUNCTION Function; /* function description for bus driver */
++ OS_SEMAPHORE InstanceSem; /* instance lock */
++ SDLIST InstanceList; /* list of instances */
++}BT_FUNCTION_CONTEXT, *PBT_FUNCTION_CONTEXT;
++
++#define SDIO_BT_TYPE_A_HCI_CMD 0x01
++#define SDIO_BT_TYPE_A_HCI_ACL 0x02
++#define SDIO_BT_TYPE_A_HCI_SCO 0x03
++#define SDIO_BT_TYPE_A_HCI_EVT 0x04
++#define MAX_RX_RETRY 3
++#define SDIO_BT_TRANSPORT_HEADER_LENGTH 4
++#define SDIO_BT_SET_HEADER(pBuf,ServiceID,Length) \
++{ \
++ (pBuf)[0] = (UINT8)(Length); \
++ (pBuf)[1] = (UINT8)((Length) >> 8); \
++ (pBuf)[2] = (UINT8)((Length) >> 16); \
++ (pBuf)[3] = (UINT8)(ServiceID); \
++}
++
++#define SDIO_BT_GET_LENGTH(pHdr) \
++ ((UINT32)((pHdr)[0]) | ((UINT32)((pHdr)[1]) << 8) | ((UINT32)((pHdr)[2]) << 16))
++
++#define SDIO_BT_GET_SERVICEID(pHdr) (pHdr)[3]
++
++/* register offsets */
++#define RECV_DATA_REG 0x00
++#define XMIT_DATA_REG 0x00
++#define RECV_PACKET_CONTROL_REG 0x10
++#define XMIT_PACKET_CONTROL_REG 0x11
++#define RETRY_CONTROL_STATUS_REG 0x12
++#define INTERRUPT_STATUS_CLEAR_REG 0x13
++#define INTERRUPT_ENABLE_REG 0x14
++#define MODE_STATUS_REG 0x20
++/* bit masks */
++#define RCV_PKT_PENDING (1 << 0)
++#define RETRY_STATUS_BIT_MASK (1 << 0)
++#define RCV_PKT_PENDING_ENABLE (1 << 0)
++#define RCV_PKT_CONTROL_RETRY (1 << 0)
++#define XMIT_PKT_CONTROL_RETRY (1 << 0)
++#define MODE_STATUS_TYPE_A 0x00
++#define RECV_PACKET_CONTROL_ACK 0x00
++#define RETRY_CONTROL_STATUS_USE_ACKS 0x00
++
++struct PKT_RETRY_CONTROL_TUPLE {
++ UINT8 SDIO_Interface; /* interface code */
++ UINT8 Class; /* standard function class */
++#define RTC_READ_ACK_REQUIRED 0x00
++#define RTC_READ_ACK_NOT_REQUIRED 0x01
++ UINT8 SDIO_RetryControl; /* retry control */
++}CT_PACK_STRUCT;
++
++#define ReadRegister(pHci,reg,pData) \
++ SDLIB_IssueCMD52((pHci)->pDevice,(pHci)->FuncNo,\
++ (reg),(pData),1,CMD52_DO_READ)
++static INLINE SDIO_STATUS WriteRegister(PBT_HCI_INSTANCE pHci, UINT reg, UINT8 Data)
++{
++ return SDLIB_IssueCMD52((pHci)->pDevice,(pHci)->FuncNo,
++ (reg),&Data,1,CMD52_DO_WRITE);
++}
++
++PBT_HCI_INSTANCE CreateHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PSDDEVICE pDevice);
++void DeleteHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PBT_HCI_INSTANCE pHci);
++
++SDIO_STATUS AddHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PBT_HCI_INSTANCE pHci);
++
++PBT_HCI_INSTANCE FindHciInstance(PBT_FUNCTION_CONTEXT pFuncContext,
++ PSDDEVICE pDevice);
++
++SDIO_STATUS SendHciPacket(PBT_HCI_INSTANCE pHci);
++
++PSDBT_HCI_PACKET OSAllocHCIRcvPacket(PBT_HCI_INSTANCE pHci,
++ UINT32 HCIPacketLength,
++ UINT8 Type);
++
++void OSFreeHciRcvPacket(PBT_HCI_INSTANCE pHci, PSDBT_HCI_PACKET pPkt);
++
++SDIO_STATUS OSIndicateHCIPacketReceived(PBT_HCI_INSTANCE pHci,
++ PSDBT_HCI_PACKET pPacket,
++ UINT32 HCIPacketLength,
++ UINT8 ServiceID);
++void OSIndicateHCIPacketTransmitDone(PBT_HCI_INSTANCE pHci,
++ SDIO_STATUS status);
++
++void OSFreeSDRequest(PBT_HCI_INSTANCE pHci, PSDREQUEST pReq);
++
++PSDREQUEST OSAllocSDRequest(PBT_HCI_INSTANCE pHci);
++
++#endif /* __SDIO_BT_H___*/
++
+Index: linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,70 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bt_linux.h
++
++ at abstract: OS dependent include Bluetooth function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_BT_LINUX_H___
++#define __SDIO_BT_LINUX_H___
++
++
++#include <linux/skbuff.h>
++#include <net/bluetooth/bluetooth.h>
++#include <net/bluetooth/hci_core.h>
++
++#define SDIO_FUNCTION_BASE "sdiofn"
++#define SDIO_FUNCTION_MAX_DEVICES 1
++#define SDIO_FUNCTION_MAJOR 0
++
++typedef struct _SDBT_CONFIG {
++ struct hci_dev *pHciDev; /* the HCI device */
++ BOOL HciRegistered;
++ struct sk_buff_head TxList;
++ spinlock_t TxListLock;
++ BOOL PktFlush;
++ spinlock_t RequestListLock;
++ SDLIST RequestList;
++}SDBT_CONFIG, *PSBT_CONFIG;
++
++typedef struct sk_buff *PSDBT_HCI_PACKET;
++#define SDBTHCI_GET_PKT_BUFFER(p) (p)->data
++#define SDBTHCI_GET_PKT_LENGTH(p) (p)->len
++
++#endif /*__SDIO_BT_LINUX_H___*/
++
+Index: linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/bluetooth/sdio_bt_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,584 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_bt_os.c
++
++ at abstract: Linux implementation module for SDIO Bluetooth Function driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++#define DBG_DECLARE 3;
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_bt.h"
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++
++#define DESCRIPTION "SDIO Bluetooth Function Driver"
++#define AUTHOR "Atheros Communications, Inc."
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++static INT blockfix = 0;
++module_param(blockfix, int, 0644);
++MODULE_PARM_DESC(blockfix, "HCI packet block fix");
++
++static INT sdrequests = 8;
++module_param(sdrequests, int, 0644);
++MODULE_PARM_DESC(sdrequests, "HCI SDRequest list size");
++
++static int bt_open(struct hci_dev *hdev);
++static int bt_close(struct hci_dev *hdev);
++static int bt_send_frame(struct sk_buff *skb);
++static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg);
++static int bt_flush(struct hci_dev *hdev);
++static void bt_destruct(struct hci_dev *hdev);
++static BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++static void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++static void CleanupInstance(PBT_FUNCTION_CONTEXT pFunctionContext,
++ PBT_HCI_INSTANCE pHci);
++
++/* devices we support, null terminated */
++static SD_PNP_INFO Ids[] = {
++ {.SDIO_FunctionClass = 0x02}, /* SDIO-BLUETOOTH SDIO standard interface code */
++ {.SDIO_FunctionClass = 0x03},
++ {}
++};
++
++/* driver data */
++static BT_FUNCTION_CONTEXT FunctionContext = {
++ .Function.Version = CT_SDIO_STACK_VERSION_CODE,
++ .Function.pName = "sdio_bluetooth",
++ .Function.MaxDevices = 1,
++ .Function.NumDevices = 0,
++ .Function.pIds = Ids,
++ .Function.pProbe = Probe,
++ .Function.pRemove = Remove,
++ .Function.pSuspend = NULL,
++ .Function.pResume = NULL,
++ .Function.pWake = NULL,
++ .Function.pContext = &FunctionContext,
++};
++
++void OSFreeSDRequest(PBT_HCI_INSTANCE pHci, PSDREQUEST pReq)
++{
++ spin_lock(&pHci->Config.RequestListLock);
++ SDListAdd(&pHci->Config.RequestList, &pReq->SDList);
++ spin_unlock(&pHci->Config.RequestListLock);
++}
++
++PSDREQUEST OSAllocSDRequest(PBT_HCI_INSTANCE pHci)
++{
++ PSDREQUEST pReq = NULL;
++ PSDLIST pItem;
++
++ spin_lock(&pHci->Config.RequestListLock);
++ do {
++ /* check the list */
++ pItem = SDListRemoveItemFromHead(&pHci->Config.RequestList);
++ if (NULL == pItem) {
++ break;
++ }
++ pReq = CONTAINING_STRUCT(pItem, SDREQUEST, SDList);
++ } while (FALSE);
++
++ spin_unlock(&pHci->Config.RequestListLock);
++
++ return pReq;
++}
++
++/* allocate a receive packet */
++PSDBT_HCI_PACKET OSAllocHCIRcvPacket(PBT_HCI_INSTANCE pHci,
++ UINT32 HCIPacketLength,
++ UINT8 Type)
++{
++ PSDBT_HCI_PACKET pPacket;
++
++ /* allocate a buffer */
++ pPacket = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC);
++ if (pPacket != NULL) {
++ pPacket->dev = (PVOID)pHci->Config.pHciDev;
++ }
++ return pPacket;
++}
++
++void OSFreeHciRcvPacket(PBT_HCI_INSTANCE pHci, PSDBT_HCI_PACKET pPkt)
++{
++ kfree_skb(pPkt);
++}
++
++/*
++ * Indicate that a HCI packet was received
++*/
++SDIO_STATUS OSIndicateHCIPacketReceived(PBT_HCI_INSTANCE pHci,
++ PSDBT_HCI_PACKET pPacket,
++ UINT32 HCIPacketLength,
++ UINT8 ServiceID)
++{
++ UINT8 btType;
++
++ switch (ServiceID) {
++ case SDIO_BT_TYPE_A_HCI_ACL:
++ btType = HCI_ACLDATA_PKT;
++ break;
++ case SDIO_BT_TYPE_A_HCI_SCO:
++ btType = HCI_SCODATA_PKT;
++ break;
++ case SDIO_BT_TYPE_A_HCI_EVT:
++ btType = HCI_EVENT_PKT;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ }
++ /* set the final type */
++ pPacket->pkt_type = btType;
++ /* adjust packet length to what the caller copied to the buffer */
++ skb_put(pPacket,HCIPacketLength);
++ /* pass receive packet up the stack */
++ if (hci_recv_frame(pPacket) != 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth Function: hci_recv_frame failed \n"));
++ } else {
++ DBG_PRINT(SDBT_DBG_RECEIVE, ("SDIO Bluetooth Function: Indicated RCV of type:%d, Length:%d \n",
++ btType,HCIPacketLength));
++ }
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * bt_open - open a handle to the device
++*/
++static int bt_open(struct hci_dev *hdev)
++{
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_open - enter - x\n"));
++
++ set_bit(HCI_RUNNING, &hdev->flags);
++ set_bit(HCI_UP, &hdev->flags);
++ set_bit(HCI_INIT, &hdev->flags);
++ ((PBT_HCI_INSTANCE)hdev->driver_data)->Config.PktFlush = FALSE;
++
++ return 0;
++}
++
++/*
++ * bt_close - close handle to the device
++*/
++static int bt_close(struct hci_dev *hdev)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_close - enter\n"));
++
++ clear_bit(HCI_RUNNING, &hdev->flags);
++ return 0;
++}
++
++
++void OSIndicateHCIPacketTransmitDone(PBT_HCI_INSTANCE pHci,
++ SDIO_STATUS status)
++{
++ PSDBT_HCI_PACKET pPacket;
++
++ pPacket = pHci->pCurrentTxPacket;
++ DBG_ASSERT(pPacket != NULL);
++
++ spin_lock(&pHci->Config.TxListLock);
++ pHci->pCurrentTxPacket = NULL;
++ if (!pHci->Config.PktFlush) {
++ /* dequeue HCI packet */
++ pHci->pCurrentTxPacket = __skb_dequeue(&pHci->Config.TxList);
++ spin_unlock(&pHci->Config.TxListLock);
++ if (pHci->pCurrentTxPacket != NULL) {
++ /* start next */
++ SendHciPacket(pHci);
++ }
++ } else {
++ spin_unlock(&pHci->Config.TxListLock);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth, cleanup in progress \n"));
++ }
++ /* free the one that completed */
++ kfree_skb(pPacket);
++}
++
++
++
++/*
++ * bt_send_frame - send data frames
++*/
++static int bt_send_frame(struct sk_buff *skb)
++{
++ SDIO_STATUS status;
++ struct hci_dev *hdev = (struct hci_dev *) skb->dev;
++ PBT_HCI_INSTANCE pHci;
++ UINT8 serviceID;
++ UINT8 *pTemp;
++
++ if (!hdev) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Bluetooth Function: bt_send_frame - no device\n"));
++ return -ENODEV;
++ }
++
++ if (!test_bit(HCI_RUNNING, &hdev->flags)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_send_frame - not open\n"));
++ return -EBUSY;
++ }
++
++ pHci = (PBT_HCI_INSTANCE)hdev->driver_data;
++
++ if (pHci->Config.PktFlush) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_send_frame - flush in progress..\n"));
++ return -EBUSY;
++ }
++
++ switch (skb->pkt_type) {
++ case HCI_COMMAND_PKT:
++ serviceID = SDIO_BT_TYPE_A_HCI_CMD;
++ hdev->stat.cmd_tx++;
++ break;
++
++ case HCI_ACLDATA_PKT:
++ serviceID = SDIO_BT_TYPE_A_HCI_ACL;
++ hdev->stat.acl_tx++;
++ break;
++
++ case HCI_SCODATA_PKT:
++ serviceID = SDIO_BT_TYPE_A_HCI_SCO;
++ hdev->stat.sco_tx++;
++ break;
++ default:
++ kfree_skb(skb);
++ return 0;
++ }
++ if (DBG_GET_DEBUG_LEVEL() >= SDBT_DBG_TRANSMIT) {
++ SDLIB_PrintBuffer(SDBTHCI_GET_PKT_BUFFER(skb),SDBTHCI_GET_PKT_LENGTH(skb),
++ "Linux BT HCI Packet Dump");
++ if (skb->pkt_type == HCI_COMMAND_PKT) {
++ pTemp = SDBTHCI_GET_PKT_BUFFER(skb);
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO BT HCI Command: OCF:0x%4.4X, OGF:0x%2.2X \n",
++ (INT)pTemp[0] | (((INT)(pTemp[1] & 0x03)) << 8), pTemp[1] >> 2 ));
++ }
++ }
++
++ /* BT HCI packets have 8 bytes of header space, push on 4 bytes for the header
++ * this bumps up the "len" field */
++ pTemp = (PUINT8)skb_push(skb, SDIO_BT_TRANSPORT_HEADER_LENGTH);
++ /* set the header */
++ SDIO_BT_SET_HEADER(pTemp,
++ serviceID,
++ SDBTHCI_GET_PKT_LENGTH(skb));
++
++
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO Bluetooth Function: bt_send_frame (hci:0x%X) Packet:0x%X \n",
++ (INT)pHci, (INT)skb));
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO BT Send ServiceID:%d, Total Length:%d Bytes \n",
++ serviceID,SDBTHCI_GET_PKT_LENGTH(skb)));
++
++ spin_lock(&pHci->Config.TxListLock);
++ status = SDIO_STATUS_PENDING;
++ if (pHci->pCurrentTxPacket != NULL) {
++ /* queue HCI packet */
++ __skb_queue_tail(&pHci->Config.TxList,skb);
++ spin_unlock(&pHci->Config.TxListLock);
++ DBG_PRINT(SDBT_DBG_TRANSMIT, ("SDIO BT Send , Packet Queued \n"));
++ } else {
++ pHci->pCurrentTxPacket = skb;
++ spin_unlock(&pHci->Config.TxListLock);
++ status = SendHciPacket(pHci);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ return SDIOErrorToOSError(status);
++ }
++ return 0;
++}
++
++/*
++ * bt_ioctl - ioctl processing
++*/
++static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_ioctl - enter\n"));
++ return -ENOIOCTLCMD;
++}
++
++/*
++ * bt_flush - flush outstandingbpackets
++*/
++static int bt_flush(struct hci_dev *hdev)
++{
++ PSDBT_HCI_PACKET pPkt;
++ PBT_HCI_INSTANCE pHci;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_flush - enter\n"));
++
++ pHci = (PBT_HCI_INSTANCE)hdev->driver_data;
++ pHci->Config.PktFlush = TRUE;
++
++ spin_lock(&pHci->Config.TxListLock);
++ /* cleanup the queue */
++ while (1) {
++ pPkt = __skb_dequeue(&pHci->Config.TxList);
++ if (pPkt != NULL) {
++ kfree_skb(pPkt);
++ } else {
++ break;
++ }
++
++ }
++ if (pHci->pCurrentTxPacket != NULL) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Outstanding HCI packet:0x%X \n",
++ (INT)pHci->pCurrentTxPacket));
++ }
++ spin_unlock(&pHci->Config.TxListLock);
++
++ return 0;
++}
++
++
++/*
++ * bt_destruct -
++*/
++static void bt_destruct(struct hci_dev *hdev)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: bt_destruct - enter\n"));
++ /* currently only supporting a single statically assigned device, nothing to do here */
++}
++
++/*
++ * Probe - a device potentially for us
++*/
++static BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice) {
++ PBT_FUNCTION_CONTEXT pFunctionContext =
++ (PBT_FUNCTION_CONTEXT)pFunction->pContext;
++ SYSTEM_STATUS err = 0;
++ BOOL okay = FALSE;
++ struct hci_dev *pHciDev = NULL;
++ PBT_HCI_INSTANCE pNewHci = NULL;
++ INT i;
++ PSDREQUEST pReq;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Probe - enter\n"));
++
++ /* make sure this is a device we can handle */
++ if ((pDevice->pId[0].SDIO_FunctionClass == 0x02) ||
++ (pDevice->pId[0].SDIO_FunctionClass == 0x03)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Probe - card matched (0x%X/0x%X/0x%X)\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode,
++ pDevice->pId[0].SDIO_FunctionNo));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Probe - not our card (0x%X/0x%X/0x%X)\n",
++ pDevice->pId[0].SDIO_ManufacturerID,
++ pDevice->pId[0].SDIO_ManufacturerCode,
++ pDevice->pId[0].SDIO_FunctionNo));
++ return FALSE;
++ }
++
++ do {
++
++ pNewHci = CreateHciInstance(pFunctionContext, pDevice);
++ if (NULL == pNewHci) {
++ break;
++ }
++
++ if (blockfix) {
++ pNewHci->BlockTransferFix = TRUE;
++ } else {
++ pNewHci->BlockTransferFix = FALSE;
++ }
++
++ skb_queue_head_init(&pNewHci->Config.TxList);
++ spin_lock_init(&pNewHci->Config.TxListLock);
++ spin_lock_init(&pNewHci->Config.RequestListLock);
++ SDLIST_INIT(&pNewHci->Config.RequestList);
++
++ /* allocate bus requests for block transfers */
++ for (i = 0; i < sdrequests; i++) {
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ break;
++ }
++ /* add it to our list */
++ OSFreeSDRequest(pNewHci, pReq);
++ }
++
++ /* allocate a BT HCI struct for this device */
++ pHciDev = hci_alloc_dev();
++ if (NULL == pHciDev) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth Function: Probe - failed to allocate bt struct.\n"));
++ break;
++ }
++ SET_HCIDEV_DEV(pHciDev, SD_GET_OS_DEVICE(pDevice));
++
++ pNewHci->Config.pHciDev = pHciDev;
++ /* add this instance to our list */
++ if (!SDIO_SUCCESS(AddHciInstance(pFunctionContext,pNewHci))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth : failed to add instance to list \n"));
++ break;
++ }
++
++ pHciDev->type = HCI_VHCI; /* we don't really have a type assigned ????*/
++ pHciDev->driver_data = pNewHci;
++ pHciDev->open = bt_open;
++ pHciDev->close = bt_close;
++ pHciDev->send = bt_send_frame;
++ pHciDev->ioctl = bt_ioctl;
++ pHciDev->flush = bt_flush;
++ pHciDev->destruct = bt_destruct;
++ pHciDev->owner = THIS_MODULE;
++
++ /* mark that we are registered */
++ pNewHci->Config.HciRegistered = TRUE;
++ if ((err = hci_register_dev(pHciDev)) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth Function: Probe - can't register with bluetooth %d\n",
++ err));
++ pNewHci->Config.HciRegistered = FALSE;
++ break;
++ }
++
++ okay = TRUE;
++ } while (FALSE);
++
++ if (!okay) {
++ if (pNewHci != NULL) {
++ CleanupInstance(pFunctionContext, pNewHci);
++ }
++ }
++
++ return okay;
++}
++
++static void CleanupInstance(PBT_FUNCTION_CONTEXT pFunctionContext,
++ PBT_HCI_INSTANCE pHci)
++{
++ int err;
++ PSDREQUEST pReq;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Bluetooth CleanupInstance \n"));
++
++ if (pHci->Config.pHciDev != NULL) {
++ if (pHci->Config.HciRegistered) {
++ /* first unregister */
++ if ((err = hci_unregister_dev(pHci->Config.pHciDev)) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth Function: Remove - can't unregister with bluetooth %d\n",
++ err));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Remove - HCI Instance:0x%X, unregistered\n",
++ (INT)pHci));
++ }
++
++ if (pHci->pCurrentTxPacket != NULL) {
++ /* TODO fix this with polling or an event */
++ OSSleep(2000);
++ }
++ DBG_ASSERT(pHci->pCurrentTxPacket == NULL);
++ KernelFree(pHci->Config.pHciDev);
++ }
++ }
++
++ /* cleanup list */
++ while (1) {
++ pReq = OSAllocSDRequest(pHci);
++ if (NULL == pReq) {
++ break;
++ }
++ SDDeviceFreeRequest(pHci->pDevice,pReq);
++ }
++ /* remove this instance */
++ DeleteHciInstance(pFunctionContext, pHci);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Bluetooth CleanupInstance \n"));
++}
++
++/*
++ * Remove - our device is being removed
++*/
++static void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice)
++{
++ PBT_HCI_INSTANCE pHci;
++ PBT_FUNCTION_CONTEXT pFunctionContext =
++ (PBT_FUNCTION_CONTEXT)pFunction->pContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Remove - enter\n"));
++
++ pHci = FindHciInstance(pFunctionContext,pDevice);
++ if (pHci != NULL) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: Removing instance: 0x%X From Remove() \n",
++ (INT)pHci));
++ CleanupInstance(pFunctionContext, pHci);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Bluetooth Function: could not find matching instance! \n"));
++ }
++}
++
++
++/*
++ * module init
++*/
++static int __init sdio_bt_init(void) {
++ SDIO_STATUS status;
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: enter\n"));
++
++ SDLIST_INIT(&FunctionContext.InstanceList);
++ status = SemaphoreInitialize(&FunctionContext.InstanceSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ return SDIOErrorToOSError(status);
++ }
++ /* register with bus driver core */
++ return SDIOErrorToOSError(SDIO_RegisterFunction(&FunctionContext.Function));
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_bt_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("SDIO Bluetooth Function: exit\n"));
++ SDIO_UnregisterFunction(&FunctionContext.Function);
++ SemaphoreDelete(&FunctionContext.InstanceSem);
++}
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++module_init(sdio_bt_init);
++module_exit(sdio_bt_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/function/memory/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/memory/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,5 @@
++#
++# SDIO memory card function driver
++#
++obj-m += sdio_memory_fd.o
++sdio_memory_fd-objs := sdio_memory.o sdio_memory_os.o
+Index: linux-2.6.22/drivers/sdio/function/memory/sdio_memory.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/memory/sdio_memory.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,926 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_memory.c
++
++ at abstract: SDIO Memeory Function driver
++
++#notes: includes OS independent portions -
++
++ at notice: Copyright (c), 2004-2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#define MODULE_NAME SDMEMORYFD
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include <linux/sdio/_sdio_defs.h>
++#include <linux/sdio/mmc_defs.h>
++#include "sdio_memory.h"
++
++
++#define MMC_GET_START_BIT(pCsd) (pCsd[0] & 0x1)
++#define MMC_GET_FILE_FORMAT(pCsd) (pCsd[1] & 0xC)
++#define MMC_GET_PERM_WRITE_PROTECT(pCsd) (pCsd[1] & 0x20)
++#define MMC_GET_TEMP_WRITE_PROTECT(pCsd) (pCsd[1] & 0x10)
++#define MMC_GET_FILE_FORMAT_GROUP(pCsd) (pCsd[1] & 0x80)
++#define MMC_GET_PARTIAL_WRITE_DATA(pCsd) (pCsd[2] & 0x20)
++#define MMC_GET_MAX_WRITE_DATA_BLOCK(pCsd) (((pCsd[2] & 0xC0)>>6) | ((pCsd[3] & 0x3) << 2))
++#define MMC_GET_WRITE_SPEED_FACTOR(pCsd) (pCsd[3] & 0x1C)
++#define MMC_GET_MAX_READ_DATA_BLOCK(pCsd) (pCsd[10] & 0x0F)
++#define MMC_GET_PARTIAL_READ_DATA(pCsd) (pCsd[9] & 0x80)
++#define MMC_GET_C_SIZE_MULT(pCsd) (((pCsd[5] & 0x80)>>7) | ((pCsd[6] & 0x03)<<1))
++#define MMC_GET_C_SIZE(pCsd) (((pCsd[7] & 0xC0)>>6) | (pCsd[8]<<2) |((pCsd[9] & 0x03)<<10))
++#define MMC_GET_SPEC_VERSION(pCsd) ((pCsd[15] & 0x3C) >> 2) /* MMC Only */
++#define MMC_GET_CSD_VERSION(pCsd) ((pCsd[15] & 0xC0) >> 6)
++static const INT MMC_POWER_TABLE[12] = {
++ 1,2,4,8,16,32,64,128,256,512,1024,2048
++};
++
++#define MMC_GET_WRITE_CURR_MAX(pCsd) (((pCsd)[6] >> 2) & 0x07)
++#define MMC_GET_READ_CURR_MAX(pCsd) ((pCsd)[7] & 0x07)
++
++ /* VDD current table, mA */
++static const UINT8 VDDCurrentTable[8] = {
++ 1,5,10,25,35,45,80,200
++};
++
++#define MMC_CMD_SET_BLOCK_LENGTH CMD16
++#define MMC_CMD_READ_SINGLE_BLOCK CMD17
++#define MMC_CMD_READ_MULTIPLE_BLOCK CMD18
++#define MMC_CMD_WRITE_SINGLE_BLOCK CMD24
++#define MMC_CMD_WRITE_MULTIPLE_BLOCK CMD25
++
++
++const SD_SLOT_CURRENT MMC_PowerClass_3_6V_To_Current[MMC_EXT_MAX_PWR_CLASSES] =
++ /* in milliamps */
++{
++ 200, /* 0 */
++ 220, /* 1 */
++ 250, /* 2 */
++ 280, /* 3 */
++ 300, /* 4 */
++ 320, /* 5 */
++ 350, /* 6 */
++ 400, /* 7 */
++ 450, /* 8 */
++ 500, /* 9 */
++ 550, /* 10 */
++ 0,0,0,0,0 /* 11 - 15 are reserved */
++};
++
++const SD_SLOT_CURRENT MMC_PowerClass_1_95V_To_Current[MMC_EXT_MAX_PWR_CLASSES] =
++ /* in milliamps */
++{
++ 130, /* 0 */
++ 140, /* 1 */
++ 160, /* 2 */
++ 180, /* 3 */
++ 200, /* 4 */
++ 220, /* 5 */
++ 240, /* 6 */
++ 260, /* 7 */
++ 280, /* 8 */
++ 300, /* 9 */
++ 350, /* 10 */
++ 0,0,0,0,0 /* 11 - 15 are reserved */
++};
++
++
++
++static SDIO_STATUS IssueDeviceRequest(PSDDEVICE pDevice,
++ UINT8 Cmd,
++ UINT32 Argument,
++ SDREQUEST_FLAGS Flags,
++ PSDREQUEST pReqToUse,
++ PVOID pData,
++ INT Length);
++static SDIO_STATUS ReadBlocks(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ PVOID pData,
++ UINT32 Length);
++static SDIO_STATUS WriteBlocks(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ PVOID pData,
++ UINT32 Length);
++
++
++/* delete an instance */
++void DeleteInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDIO_MEMORY_INSTANCE pInstance)
++{
++
++ if (!SDIO_SUCCESS(SemaphorePendInterruptable(&pFuncContext->InstanceSem))) {
++ return;
++ }
++ /* pull it out of the list */
++ SDListRemove(&pInstance->SDList);
++ SemaphorePost(&pFuncContext->InstanceSem);
++
++
++ /* free slot current */
++ SDLIB_IssueConfig(pInstance->pDevice,
++ SDCONFIG_FUNC_FREE_SLOT_CURRENT,
++ NULL,
++ 0);
++
++ KernelFree(pInstance);
++}
++
++static void ReorderBuffer(UINT8 *pBuffer, INT Bytes)
++{
++ UINT8 *pEnd;
++ UINT8 temp;
++
++ DBG_ASSERT(!(Bytes & 1));
++ /* point to the end */
++ pEnd = &pBuffer[Bytes - 1];
++ /* divide in half */
++ Bytes = Bytes >> 1;
++
++ while (Bytes) {
++ temp = *pBuffer;
++ /* swap bytes */
++ *pBuffer = *pEnd;
++ *pEnd = temp;
++ pBuffer++;
++ pEnd--;
++ Bytes--;
++ }
++}
++
++SD_SLOT_CURRENT LookupCurrent(PSDDEVICE pDevice, PUINT8 pExtendedCSD)
++{
++ const SD_SLOT_CURRENT *pTable = NULL;
++ UINT8 powerClass = 0;
++
++ switch(SDDEVICE_GET_SLOT_VOLTAGE_MASK(pDevice)) {
++ case SLOT_POWER_3_3V:
++ case SLOT_POWER_3_0V:
++ case SLOT_POWER_2_8V:
++ pTable = MMC_PowerClass_3_6V_To_Current;
++ if (SDDEVICE_GET_OPER_CLOCK(pDevice) <= 26000000) {
++ DBG_PRINT(SDDBG_TRACE, (" Using MMC 3.6V and 26Mhz power table \n"));
++ powerClass = pExtendedCSD[MMC_EXT_PWR_CL_26_360_OFFSET];
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" Using MMC 3.6V and 52Mhz power table \n"));
++ powerClass = pExtendedCSD[MMC_EXT_PWR_CL_52_360_OFFSET];
++ }
++ break;
++ case SLOT_POWER_2_0V:
++ case SLOT_POWER_1_8V:
++ case SLOT_POWER_1_6V:
++ pTable = MMC_PowerClass_1_95V_To_Current;
++ if (SDDEVICE_GET_OPER_CLOCK(pDevice) <= 26000000) {
++ DBG_PRINT(SDDBG_TRACE, (" Using MMC 1.95V and 26Mhz power table \n"));
++ powerClass = pExtendedCSD[MMC_EXT_PWR_CL_26_195_OFFSET];
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" Using MMC 1.95V and 52Mhz power table \n"));
++ powerClass = pExtendedCSD[MMC_EXT_PWR_CL_52_195_OFFSET];
++ }
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ if (pTable != NULL) {
++ if (SDDEVICE_GET_BUSWIDTH(pDevice) == SDCONFIG_BUS_WIDTH_MMC8_BIT) {
++ /* use upper nibble for power class */
++ powerClass >>= 4;
++ }
++ powerClass &= 0xF;
++ DBG_PRINT(SDDBG_TRACE, (" MMC Power Class %d: \n",powerClass));
++ return pTable[powerClass];
++ }
++
++ return 0;
++}
++/* create a memory instance */
++PSDIO_MEMORY_INSTANCE CreateDeviceInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDDEVICE pDevice)
++{
++ PSDIO_MEMORY_INSTANCE pInstance = NULL;
++ SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
++ PUINT8 pCSD = SDDEVICE_GET_CARDCSD(pDevice);
++ SD_SLOT_CURRENT maxReadCurrent = 0;
++ SD_SLOT_CURRENT maxWriteCurrent = 0;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq = NULL;
++
++ ZERO_OBJECT(slotCurrent);
++
++ do {
++ pInstance = (PSDIO_MEMORY_INSTANCE)KernelAlloc(sizeof(SDIO_MEMORY_INSTANCE));
++ if (NULL == pInstance) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ ZERO_POBJECT(pInstance);
++ SDLIST_INIT(&pInstance->SDList);
++ pInstance->pDevice = pDevice;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function Instance: 0x%X \n",(INT)pInstance));
++ DBG_PRINT(SDDBG_TRACE, (" Card Flags: 0x%X \n",SDDEVICE_GET_CARD_FLAGS(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Card RCA: 0x%X \n",SDDEVICE_GET_CARD_RCA(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Oper Clock: %d Hz \n",SDDEVICE_GET_OPER_CLOCK(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Max Clock: %d Hz \n",SDDEVICE_GET_MAX_CLOCK(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Oper BlklenLim: %d bytes \n",SDDEVICE_GET_OPER_BLOCK_LEN(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Max BlkLen: %d bytes\n",SDDEVICE_GET_MAX_BLOCK_LEN(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Oper BlksLim: %d blocks per trans \n",SDDEVICE_GET_OPER_BLOCKS(pDevice)));
++ DBG_PRINT(SDDBG_TRACE, (" Max Blks: %d blocks per trans \n",SDDEVICE_GET_MAX_BLOCKS(pDevice)));
++
++
++ pReq = SDDeviceAllocRequest(pDevice);
++
++ if (NULL == pReq) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++
++ /* for SD cards in high speed mode, the power consumption is reported in the switch
++ * status block */
++ if ((SDDEVICE_GET_CARD_FLAGS(pDevice) & CARD_SD) &&
++ (SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_SD_HS)) {
++ /* fetch the switch status block */
++ pReq->Command = CMD6;
++ pReq->Argument = SD_SWITCH_FUNC_ARG_GROUP_CHECK(SD_SWITCH_HIGH_SPEED_GROUP,
++ SD_SWITCH_HIGH_SPEED_FUNC_NO);
++ pReq->Flags = SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS;
++ pReq->BlockCount = 1;
++ pReq->BlockLen = SD_SWITCH_FUNC_STATUS_BLOCK_BYTES;
++ pReq->pDataBuffer = pInstance->ExtendedData;
++
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice,pReq);
++
++ if (SDIO_SUCCESS(status)) {
++ /* need to reorder this since cards send this MSB first */
++ ReorderBuffer(pInstance->ExtendedData,SD_SWITCH_FUNC_STATUS_BLOCK_BYTES);
++ maxWriteCurrent = SD_SWITCH_FUNC_STATUS_GET_MAX_CURRENT(pInstance->ExtendedData);
++ if (maxWriteCurrent == 0) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory: SD Card Switch Status indicates 0 current!, using CSD instead\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory: SD High Speed card requires %d mA of current\n",
++ maxWriteCurrent));
++ }
++ maxReadCurrent = maxWriteCurrent;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory: Failed to get SD Card Switch Status \n"));
++ status = SDIO_STATUS_SUCCESS;
++ /* since we can't figure this out, use the largest value the SD spec says */
++ maxWriteCurrent = 200;
++ maxReadCurrent = 200;
++ }
++ }
++ /* for MMC cards in high speed mode the current consumption is in the extended CSD */
++ if ((SDDEVICE_GET_CARD_FLAGS(pDevice) & CARD_MMC) &&
++ (SDDEVICE_GET_BUSMODE_FLAGS(pDevice) & SDCONFIG_BUS_MODE_MMC_HS)) {
++
++ pReq->Command = MMC_CMD8;
++ pReq->Argument = 0;
++ pReq->Flags = SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_TRANS;
++ pReq->BlockCount = 1;
++ pReq->BlockLen = MMC_EXT_CSD_SIZE;
++ pReq->pDataBuffer = pInstance->ExtendedData;
++
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice,pReq);
++
++ if (SDIO_SUCCESS(status)) {
++ maxWriteCurrent = LookupCurrent(pDevice,pInstance->ExtendedData);
++ if (maxWriteCurrent == 0) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory: MMC card Extended CSD indicates 0 current!, using old CSD instead\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory: MMC High Speed card requires %d mA of current\n",
++ maxWriteCurrent));
++ }
++ maxReadCurrent = maxWriteCurrent;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory: Failed to get MMC Extended CSD \n"));
++ status = SDIO_STATUS_SUCCESS;
++ /* since we can't figure this out, pick a reasonable value */
++ maxWriteCurrent = 500;
++ maxReadCurrent = 500;
++ }
++ }
++
++ if (0 == maxWriteCurrent) {
++ /* get max currents for write from CSD */
++ maxWriteCurrent = VDDCurrentTable[MMC_GET_WRITE_CURR_MAX(pCSD)];
++ }
++
++ if (0 == maxReadCurrent) {
++ /* get max currents for read from CSD */
++ maxReadCurrent = VDDCurrentTable[MMC_GET_READ_CURR_MAX(pCSD)];
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory: Write Max Curr: %d mA, Read Max Curr: %d mA\n", maxWriteCurrent,
++ maxReadCurrent));
++
++ /* pick the highest of the read or write */
++ slotCurrent.SlotCurrent = max(maxWriteCurrent, maxReadCurrent);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory: Allocating Slot current: %d mA\n", slotCurrent.SlotCurrent));
++ status = SDLIB_IssueConfig(pDevice,
++ SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
++ &slotCurrent,
++ sizeof(slotCurrent));
++
++ if (!SDIO_SUCCESS((status))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory: failed to allocate slot current %d\n",
++ status));
++ if (status == SDIO_STATUS_NO_RESOURCES) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory: Remaining Slot Current: %d mA\n",
++ slotCurrent.SlotCurrent));
++ }
++ break;
++ }
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status) && (pInstance != NULL)) {
++ KernelFree(pInstance);
++ pInstance = NULL;
++ }
++
++ if (pReq != NULL) {
++ SDDeviceFreeRequest(pDevice,pReq);
++ }
++ return pInstance;
++}
++
++PSDIO_MEMORY_INSTANCE GetFirstInstance(PSDIO_MEMORY_CONTEXT pFuncContext)
++{
++ SDIO_STATUS status;
++ PSDIO_MEMORY_INSTANCE pInstance;
++
++ status = SemaphorePendInterruptable(&pFuncContext->InstanceSem);
++ if (!SDIO_SUCCESS(status)) {
++ return NULL;
++ }
++
++ if (SDLIST_IS_EMPTY(&pFuncContext->InstanceList)) {
++ /* no more left */
++ pInstance = NULL;
++ } else {
++ /* get the item at the head */
++ pInstance = CONTAINING_STRUCT(SDLIST_GET_ITEM_AT_HEAD(&pFuncContext->InstanceList),
++ SDIO_MEMORY_INSTANCE,
++ SDList);
++ }
++
++ SemaphorePost(&pFuncContext->InstanceSem);
++ return pInstance;
++}
++
++/* find an instance associated with the SD device */
++PSDIO_MEMORY_INSTANCE FindInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDDEVICE pDevice)
++{
++ SDIO_STATUS status;
++ PSDLIST pItem;
++ PSDIO_MEMORY_INSTANCE pInstance = NULL;
++
++ status = SemaphorePendInterruptable(&pFuncContext->InstanceSem);
++ if (!SDIO_SUCCESS(status)) {
++ return NULL;
++ }
++ /* walk the list and find our instance */
++ SDITERATE_OVER_LIST(&pFuncContext->InstanceList, pItem) {
++ pInstance = CONTAINING_STRUCT(pItem, SDIO_MEMORY_INSTANCE, SDList);
++ if (pInstance->pDevice == pDevice) {
++ /* found it */
++ break;
++ }
++ pInstance = NULL;
++ }
++
++ SemaphorePost(&pFuncContext->InstanceSem);
++ return pInstance;
++}
++
++/* add and instance to our list */
++SDIO_STATUS AddDeviceInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDIO_MEMORY_INSTANCE pInstance)
++{
++ SDIO_STATUS status;
++
++ status = SemaphorePendInterruptable(&pFuncContext->InstanceSem);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ SDListAdd(&pFuncContext->InstanceList,&pInstance->SDList);
++ SemaphorePost(&pFuncContext->InstanceSem);
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/* cleanup the function context */
++void CleanupFunctionContext(PSDIO_MEMORY_CONTEXT pFuncContext)
++{
++ SemaphoreDelete(&pFuncContext->InstanceSem);
++}
++
++/* initialize the function context */
++SDIO_STATUS InitFunctionContext(PSDIO_MEMORY_CONTEXT pFuncContext)
++{
++ SDIO_STATUS status;
++ SDLIST_INIT(&pFuncContext->InstanceList);
++
++ status = SemaphoreInitialize(&pFuncContext->InstanceSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ return status;
++ }
++
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * GetCardCSD - get the interesting part of Card CSD register
++*/
++SDIO_STATUS GetCardCSD(PSDDEVICE pDevice, PSDIO_MEMORY_INSTANCE pInstance, BOOL IsMmcCardType)
++{
++ PUINT8 pCSD = SDDEVICE_GET_CARDCSD(pDevice);
++ UINT32 size;
++ SDIO_STATUS status;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: ViewCardCSD\n"));
++ if (!MMC_GET_START_BIT(pCSD)) {
++ /* this bit is not really available to be read DBG_PRINT(SDDBG_ERROR, ("**ERROR, start bit not 1\n"));*/
++ }
++ if (MMC_GET_CSD_VERSION(pCSD) == 0) {
++ DBG_PRINT(SDDBG_TRACE, (" CSD version: 1.0\n")); /* all SD cards should be here */
++ } else if (MMC_GET_CSD_VERSION(pCSD) == 1) {
++ DBG_PRINT(SDDBG_TRACE, (" CSD version: 1.1\n"));
++ } else if (MMC_GET_CSD_VERSION(pCSD) == 2) {
++ DBG_PRINT(SDDBG_TRACE, (" CSD version: 1.2\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" CSD version: reserved %d\n", MMC_GET_SPEC_VERSION(pCSD)));
++ }
++ if (IsMmcCardType) {
++ if (MMC_GET_SPEC_VERSION(pCSD) == 0) {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: 1.0-1.2\n"));
++ } else if (MMC_GET_SPEC_VERSION(pCSD) == 1) {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: 1.4\n"));
++ } else if (MMC_GET_SPEC_VERSION(pCSD) == 2) {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: 2.0-2.2\n"));
++ } else if (MMC_GET_SPEC_VERSION(pCSD) == 3) {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: 3.1-3.31\n"));
++ } else if (MMC_GET_SPEC_VERSION(pCSD) == 4) {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: 4.0-4.1\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" spec version: reserved %d\n", MMC_GET_SPEC_VERSION(pCSD)));
++ }
++ }
++ if (MMC_GET_FILE_FORMAT_GROUP(pCSD)) {
++ DBG_PRINT(SDDBG_TRACE, (" File format reserved: %d\n", MMC_GET_FILE_FORMAT(pCSD)));
++ } else {
++ if (MMC_GET_FILE_FORMAT(pCSD) == 0) {
++ DBG_PRINT(SDDBG_TRACE, (" File format: Hard disk-like file system with partition table\n"));
++ } else if (MMC_GET_FILE_FORMAT(pCSD) == 1) {
++ DBG_PRINT(SDDBG_TRACE, (" File format: DOS FAT (floppy-like) with boot sector only (no partition table)\n"));
++ } else if (MMC_GET_FILE_FORMAT(pCSD) == 2) {
++ DBG_PRINT(SDDBG_TRACE, (" File format: Universal File Format\n"));
++ } else if (MMC_GET_FILE_FORMAT(pCSD) == 3) {
++ DBG_PRINT(SDDBG_TRACE, (" File format: Others - Unknown\n"));
++ }
++ }
++ if (MMC_GET_MAX_WRITE_DATA_BLOCK(pCSD) > 11) {
++ DBG_PRINT(SDDBG_WARN, (" Max write block *reserved* value: %d\n",
++ MMC_GET_MAX_WRITE_DATA_BLOCK(pCSD)));
++ /* use the max, as this size is in error */
++ pInstance->WriteBlockLength = MMC_POWER_TABLE[11];
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" Max write block: %d\n",
++ MMC_POWER_TABLE[MMC_GET_MAX_WRITE_DATA_BLOCK(pCSD)]));
++ pInstance->WriteBlockLength = MMC_POWER_TABLE[MMC_GET_MAX_WRITE_DATA_BLOCK(pCSD)];
++ }
++ pInstance->PartialWritesAllowed = MMC_GET_PARTIAL_WRITE_DATA(pCSD);
++ if (pInstance->PartialWritesAllowed) {
++ DBG_PRINT(SDDBG_TRACE, (" partial write allowed:\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" partial write not allowed:\n"));
++ }
++
++ DBG_PRINT(SDDBG_TRACE, (" write speed R2W_FACTOR: %d\n",
++ MMC_POWER_TABLE[MMC_GET_WRITE_SPEED_FACTOR(pCSD)]));
++
++ if (MMC_GET_MAX_READ_DATA_BLOCK(pCSD) > 11) {
++ DBG_PRINT(SDDBG_WARN, (" Max read block reserved value: %d\n",
++ MMC_GET_MAX_READ_DATA_BLOCK(pCSD)));
++ /* use the max, as this size is in error */
++ pInstance->ReadBlockLength = MMC_POWER_TABLE[11];
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" Max read block: %d\n",
++ MMC_POWER_TABLE[MMC_GET_MAX_READ_DATA_BLOCK(pCSD)]));
++ pInstance->ReadBlockLength = MMC_POWER_TABLE[MMC_GET_MAX_READ_DATA_BLOCK(pCSD)];
++ }
++ pInstance->PartialReadsAllowed = MMC_GET_PARTIAL_READ_DATA(pCSD);
++ if (pInstance->PartialReadsAllowed) {
++ DBG_PRINT(SDDBG_TRACE, (" partial read allowed:\n"));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, (" partial read not allowed:\n"));
++ }
++
++ DBG_PRINT(SDDBG_TRACE, (" C_SIZE/C_SIZE_MULT: %d/%d\n",
++ MMC_GET_C_SIZE(pCSD),MMC_GET_C_SIZE_MULT(pCSD) ));
++ /* calulate the size in 1k increments, handle 4GB as a special case to avoid overflow */
++ if ((MMC_POWER_TABLE[MMC_GET_C_SIZE_MULT(pCSD)+2] == 512) &&
++ ((MMC_GET_C_SIZE(pCSD) + 1) == 4096) &&
++ (MMC_POWER_TABLE[MMC_GET_MAX_READ_DATA_BLOCK(pCSD)] == 2048)) {
++ /* special case of 4GB card */
++ size = 0x400000;
++ } else {
++ size = (MMC_POWER_TABLE[MMC_GET_C_SIZE_MULT(pCSD)+2] * (MMC_GET_C_SIZE(pCSD) + 1) *
++ MMC_POWER_TABLE[MMC_GET_MAX_READ_DATA_BLOCK(pCSD)]) / 1024;
++ }
++ DBG_PRINT(SDDBG_TRACE, (" capacity: %dK\n", (UINT)size));
++ pInstance->Size = size;
++ /* set the block size to the smaller of the read/write block sizes */
++ /* use the smaller of two block sizes */
++//?? pInstance->BlockSize = (pInstance->ReadBlockLength < pInstance->WriteBlockLength)?
++//?? pInstance->ReadBlockLength : pInstance->WriteBlockLength;
++ /* MMC cards seem to want us to ignore the write block size and use the read block size,
++ SD cards have these equal to each other */
++ pInstance->BlockSize = pInstance->ReadBlockLength;
++ pInstance->MaxBlocksPerTransfer = pDevice->pHcd->CardProperties.OperBlockCountLimit;
++ /* tell the device this is the block size we'll use for reads and writes */
++ status = IssueDeviceRequest(pDevice, MMC_CMD_SET_BLOCK_LENGTH, pInstance->BlockSize,
++ SDREQ_FLAGS_RESP_R1, NULL, NULL, 0);
++
++ pInstance->WriteProtected =
++ (MMC_GET_PERM_WRITE_PROTECT(pCSD) || MMC_GET_TEMP_WRITE_PROTECT(pCSD)) ||
++ SDDEVICE_IS_CARD_WP_ON(pDevice);
++ DBG_PRINT(SDDBG_TRACE, (" %s media- perm:%d temp:%d\n",
++ (pInstance->WriteProtected)? "write protected" : "writable",
++ (UINT)MMC_GET_PERM_WRITE_PROTECT(pCSD), (UINT)MMC_GET_TEMP_WRITE_PROTECT(pCSD)));
++
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_DUMP) {
++ SDLIB_PrintBuffer((PUCHAR)pCSD, (INT)MAX_CARD_RESPONSE_BYTES, "SDIO Memory Function: CSD");
++ }
++
++ return status;
++}
++
++
++
++/*
++ * MemoryTransfer - read/write to device
++*/
++SDIO_STATUS MemoryTransfer(PSDIO_MEMORY_INSTANCE pInstance, SDSECTOR_SIZE sectorNumber,
++ ULONG sectorCount, PUCHAR pBuffer, BOOL WriteDirection)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ ULONG startOffset = sectorNumber * pInstance->FileSysBlockSize;
++ ULONG length = sectorCount * pInstance->FileSysBlockSize;
++
++ if (((SDSECTOR_SIZE)startOffset+(SDSECTOR_SIZE)length) >
++ ((SDSECTOR_SIZE)pInstance->Size * (SDSECTOR_SIZE)1024)) {
++ /* past end of disk */
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory Function: MemoryTransfer sector past end of disk, %d/%d size/blockSize %d/%d \n",
++ (INT)sectorNumber, (INT)sectorCount,
++ (INT)pInstance->Size, (INT)pInstance->FileSysBlockSize));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++ if (WriteDirection) {
++ /* write to device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: MemoryTransfer writing, %d/%d \n",
++ (UINT)startOffset, (UINT)length));
++ if ((length/pInstance->BlockSize) <= pInstance->MaxBlocksPerTransfer) {
++ status = WriteBlocks(pInstance->pDevice, pInstance, startOffset, pBuffer, length);
++ } else {
++ /* break into smaller chunks to transfer */
++ int tlen;
++ int offset = 0;
++ for(tlen = length; tlen > 0; tlen = length) {
++ tlen = (tlen/pInstance->MaxBlocksPerTransfer) * pInstance->BlockSize;
++ tlen = ((tlen/pInstance->MaxBlocksPerTransfer) > pInstance->MaxBlocksPerTransfer) ?
++ pInstance->MaxBlocksPerTransfer * pInstance->BlockSize: tlen;
++ length -= tlen;
++ status = WriteBlocks(pInstance->pDevice, pInstance, startOffset, &pBuffer[offset], tlen);
++ offset += tlen;
++ startOffset += tlen/pInstance->MaxBlocksPerTransfer;
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++ }
++ if (SDIO_SUCCESS(status)) {
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_DUMP) {
++ SDLIB_PrintBuffer(pBuffer, length, "SDIO Memory Function: Write buffer");
++ }
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory Function: MemoryTransfer error on WriteBlock, %d\n",
++ status ));
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_TRACE) {
++ SDLIB_PrintBuffer(pBuffer, (length > 16) ? 16 : length, "SDIO Memory Function: Write buffer, with error");
++ }
++ }
++ } else {
++ /* read from device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: MemoryTransfer reading, Offset:%d Length:%d \n",
++ (UINT)startOffset, (UINT)length));
++ if ((length/pInstance->BlockSize) <= pInstance->MaxBlocksPerTransfer) {
++ status = ReadBlocks(pInstance->pDevice, pInstance, startOffset, pBuffer, length);
++ } else {
++ /* break into smaller chunks to transfer */
++ int tlen;
++ int offset = 0;
++ for(tlen = length; tlen > 0; tlen = length) {
++ tlen = (tlen/pInstance->MaxBlocksPerTransfer) * pInstance->BlockSize;
++ tlen = ((tlen/pInstance->MaxBlocksPerTransfer) > pInstance->MaxBlocksPerTransfer) ?
++ pInstance->MaxBlocksPerTransfer * pInstance->BlockSize: tlen;
++ length -= tlen;
++ status = ReadBlocks(pInstance->pDevice, pInstance, startOffset, &pBuffer[offset], tlen);
++ offset += tlen;
++ startOffset += tlen/pInstance->MaxBlocksPerTransfer;
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++ }
++
++ if (SDIO_SUCCESS(status)) {
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_DUMP) {
++ SDLIB_PrintBuffer(pBuffer, length, "SDIO Memory Function: Read buffer");
++ }
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory Function: MemoryTransfer error on ReadBlock, %d\n",
++ status ));
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_TRACE) {
++ SDLIB_PrintBuffer(pBuffer, (length > 16) ? 16 : length, "SDIO Memory Function: Read buffer, with error");
++ }
++ }
++ }
++ return status;
++}
++
++/*
++ * ReadBlocks
++*/
++static SDIO_STATUS ReadBlocks(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ PVOID pData,
++ UINT32 Length)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq;
++
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ pReq->Argument = Address;
++ pReq->Flags = SDREQ_FLAGS_DATA_TRANS | SDREQ_FLAGS_RESP_R1;
++ pReq->Command = (Length > pInstance->BlockSize)?
++ MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK;
++ if (pReq->Command == MMC_CMD_READ_MULTIPLE_BLOCK) {
++ /* bus driver issues auto stop */
++ pReq->Flags |= SDREQ_FLAGS_AUTO_CMD12;
++ }
++ pReq->pDataBuffer = pData;
++ pReq->BlockCount = Length / pInstance->BlockSize;
++ pReq->BlockLen = pInstance->BlockSize;
++ if (SDDEVICE_IS_BUSMODE_SPI(pDevice)) {
++ pReq->RetryCount = 3;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: ReadBlocks reading, count/size length %d/%d %d cmd: %d \n",
++ (UINT)pReq->BlockCount, (UINT)pReq->BlockLen,
++ (UINT)(pReq->BlockLen*pReq->BlockCount), (UINT)pReq->Command));
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice, pReq);
++
++ SDDeviceFreeRequest(pDevice, pReq);
++
++ return status;
++}
++
++/*
++ * WriteBlocks
++*/
++static SDIO_STATUS WriteBlocks(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ PVOID pData,
++ UINT32 Length)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq;
++
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ pReq->Argument = Address;
++ pReq->Flags = SDREQ_FLAGS_DATA_TRANS | SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_WRITE |
++ SDREQ_FLAGS_AUTO_TRANSFER_STATUS;
++ pReq->Command = (Length > pInstance->BlockSize)?
++ MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_SINGLE_BLOCK;
++
++ if (pReq->Command == MMC_CMD_WRITE_MULTIPLE_BLOCK){
++ pReq->Flags |= SDREQ_FLAGS_AUTO_CMD12;
++ }
++ if (SDDEVICE_IS_BUSMODE_SPI(pDevice)) {
++ pReq->RetryCount = 3;
++ }
++
++ pReq->pDataBuffer = pData;
++ pReq->BlockCount = Length / pInstance->BlockSize;
++ pReq->BlockLen = pInstance->BlockSize;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: WriteBlocks reading, count/size length %d/%d %d cmd: %d \n",
++ (UINT)pReq->BlockCount, (UINT)pReq->BlockLen,
++ (UINT)(pReq->BlockLen*pReq->BlockCount), (UINT)pReq->Command));
++
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice, pReq);
++
++ SDDeviceFreeRequest(pDevice, pReq);
++ return status;
++}
++
++/*
++ * IssueAsyncTransfer
++*/
++SDIO_STATUS IssueAsyncTransfer(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ UINT32 Length,
++ BOOL Write,
++ PVOID pBufferOrSGList,
++ UINT SGcount,
++ void (*pCompletion)(struct _SDREQUEST *pRequest),
++ PVOID pContext)
++{
++ PSDREQUEST pReq;
++
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ pReq->Argument = Address;
++
++ /* set up default flags */
++ pReq->Flags = SDREQ_FLAGS_DATA_TRANS | SDREQ_FLAGS_RESP_R1 |
++ SDREQ_FLAGS_TRANS_ASYNC;
++
++ if (SGcount > 0) {
++ /* using DMA , pBufferOrSGList is a scatter gather list*/
++ pReq->Flags |= SDREQ_FLAGS_DATA_DMA;
++ }
++
++ if (Write) {
++ pReq->Flags |= SDREQ_FLAGS_DATA_WRITE | SDREQ_FLAGS_AUTO_TRANSFER_STATUS;
++ pReq->Command = (Length > pInstance->BlockSize)?
++ MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_SINGLE_BLOCK;
++ } else {
++ pReq->Command = (Length > pInstance->BlockSize)?
++ MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK;
++ }
++
++ if (Length > pInstance->BlockSize) {
++ /* multi-block transfer requires CMD12 to stop */
++ pReq->Flags |= SDREQ_FLAGS_AUTO_CMD12;
++ }
++
++ pReq->pDataBuffer = pBufferOrSGList;
++ pReq->DescriptorCount = SGcount;
++ pReq->BlockCount = Length / pInstance->BlockSize;
++ pReq->BlockLen = pInstance->BlockSize;
++ pReq->pCompletion = pCompletion;
++ pReq->pCompleteContext = pContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: IssueAsyncTransfer (%s), (count/blksize:%d/%d) (length:%d) cmd: %d \n",
++ Write ? "TX": "RX",
++ (UINT)pReq->BlockCount, (UINT)pReq->BlockLen,
++ (UINT)(pReq->BlockLen*pReq->BlockCount), (UINT)pReq->Command));
++ return SDDEVICE_CALL_REQUEST_FUNC(pDevice, pReq);
++}
++
++/*
++ * WriteBlocksAsync
++*/
++SDIO_STATUS WriteBlocksAsync(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ UINT32 Length,
++ PSDDMA_DESCRIPTOR pDmaList,
++ UINT SGcount,
++ void (*pCompletion)(struct _SDREQUEST *pRequest),
++ PVOID pContext)
++{
++ PSDREQUEST pReq;
++
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++
++ pReq->Argument = Address;
++ pReq->Flags = SDREQ_FLAGS_DATA_TRANS | SDREQ_FLAGS_RESP_R1 | SDREQ_FLAGS_DATA_WRITE |
++ SDREQ_FLAGS_TRANS_ASYNC | SDREQ_FLAGS_DATA_DMA | SDREQ_FLAGS_AUTO_TRANSFER_STATUS;
++
++ pReq->Command = (Length > pInstance->BlockSize)?
++ MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_SINGLE_BLOCK;
++ if (pReq->Command == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
++ /* bus driver issues auto stop */
++ pReq->Flags |= SDREQ_FLAGS_AUTO_CMD12;
++ }
++ pReq->pDataBuffer = (PVOID)pDmaList;
++ pReq->DescriptorCount = SGcount;
++ pReq->BlockCount = Length / pInstance->BlockSize;
++ pReq->BlockLen = pInstance->BlockSize;
++ pReq->pCompletion = pCompletion;
++ pReq->pCompleteContext = pContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: WriteBlocksAsync reading, count/size length %d/%d %d cmd: %d \n",
++ (UINT)pReq->BlockCount, (UINT)pReq->BlockLen,
++ (UINT)(pReq->BlockLen*pReq->BlockCount), (UINT)pReq->Command));
++ return SDDEVICE_CALL_REQUEST_FUNC(pDevice, pReq);
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ IssueDeviceRequest - issue a bus request
++ Input: pDevice - device to send to
++ Cmd - command to issue
++ Argument - command argument
++ Flags - request flags
++
++ Output: pReqToUse - request to use (if caller wants response data)
++ Return: SDIO Status
++ Notes: This function only issues 1 block data transfers
++ This function issues the request synchronously
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++static SDIO_STATUS IssueDeviceRequest(PSDDEVICE pDevice,
++ UINT8 Cmd,
++ UINT32 Argument,
++ SDREQUEST_FLAGS Flags,
++ PSDREQUEST pReqToUse,
++ PVOID pData,
++ INT Length)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDREQUEST pReq;
++
++ if (NULL == pReqToUse) {
++ /* caller doesn't care about the response data, allocate locally */
++ pReq = SDDeviceAllocRequest(pDevice);
++ if (NULL == pReq) {
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ } else {
++ /* use the caller's request buffer */
++ pReq = pReqToUse;
++ }
++
++ pReq->Argument = Argument;
++ pReq->Flags = Flags;
++ pReq->Command = Cmd;
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ pReq->pDataBuffer = pData;
++ pReq->BlockCount = 1;
++ pReq->BlockLen = Length;
++ }
++
++ status = SDDEVICE_CALL_REQUEST_FUNC(pDevice, pReq);
++
++ if (NULL == pReqToUse) {
++ DBG_ASSERT(pReq != NULL);
++ SDDeviceFreeRequest(pDevice, pReq);
++ }
++ return status;
++}
+Index: linux-2.6.22/drivers/sdio/function/memory/sdio_memory.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/memory/sdio_memory.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,98 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: function.h
++
++ at abstract: OS independent include memory card function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_MEMORY_H___
++#define __SDIO_MEMORY_H___
++
++#include "sdio_memory_linux.h"
++
++#define EXTENDED_DATA_SIZE 512
++typedef struct _SDIO_MEMORY_INSTANCE {
++ SDLIST SDList; /* link in the instance list */
++ PSDDEVICE pDevice; /* bus driver's device we are supporting */
++ SDMEMORY_CONFIG Config; /* OS specific config */
++ UINT32 Size; /* size of this card, in 1024 byte units*/
++ UINT FileSysBlockSize; /* block size used by file system */
++ BOOL WriteProtected; /* true if write protected */
++ UINT WriteBlockLength; /* length of writes */
++ BOOL PartialWritesAllowed; /* writes < WriteBlockLength OK */
++ UINT ReadBlockLength; /* length of reads */
++ BOOL PartialReadsAllowed; /* reads < ReadBlockLength OK */
++ UINT BlockSize; /* read/write size based on above 4 parameters */
++ UINT MaxBlocksPerTransfer; /* maximum number of blocks per individual transfer */
++ UINT8 ExtendedData[EXTENDED_DATA_SIZE]; /* store extended CSD and/or SD status block */
++}SDIO_MEMORY_INSTANCE, *PSDIO_MEMORY_INSTANCE;
++
++typedef struct _SDIO_MEMORY_CONTEXT {
++ SDFUNCTION Function; /* function description for bus driver */
++ SDMEMORY_DRIVER_CONFIG Driver; /* OS specific driver wide configuration */
++ OS_SEMAPHORE InstanceSem; /* instance lock */
++ SDLIST InstanceList; /* list of instances */
++}SDIO_MEMORY_CONTEXT, *PSDIO_MEMORY_CONTEXT;
++
++#define SDDBG_DUMP (SDDBG_TRACE + 1)
++
++void DeleteInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDIO_MEMORY_INSTANCE pInstance);
++PSDIO_MEMORY_INSTANCE CreateDeviceInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDDEVICE pDevice);
++PSDIO_MEMORY_INSTANCE GetFirstInstance(PSDIO_MEMORY_CONTEXT pFuncContext);
++PSDIO_MEMORY_INSTANCE FindInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDDEVICE pDevice);
++SDIO_STATUS AddDeviceInstance(PSDIO_MEMORY_CONTEXT pFuncContext,
++ PSDIO_MEMORY_INSTANCE pInstance);
++void CleanupFunctionContext(PSDIO_MEMORY_CONTEXT pFuncContext);
++SDIO_STATUS InitFunctionContext(PSDIO_MEMORY_CONTEXT pFuncContext);
++SDIO_STATUS MemoryTransfer(PSDIO_MEMORY_INSTANCE pInstance, SDSECTOR_SIZE sectorNumber,
++ ULONG sectorCount, PUCHAR pBuffer, BOOL WriteDirection);
++SDIO_STATUS GetCardCSD(PSDDEVICE pDevice, PSDIO_MEMORY_INSTANCE pInstance, BOOL IsMmcCardType);
++SDIO_STATUS IssueAsyncTransfer(PSDDEVICE pDevice,
++ PSDIO_MEMORY_INSTANCE pInstance,
++ UINT32 Address,
++ UINT32 Length,
++ BOOL Write,
++ PVOID pBufferOrSGList,
++ UINT SGcount,
++ void (*pCompletion)(struct _SDREQUEST *pRequest),
++ PVOID pContext);
++
++#endif /* __SDIO_MEMORY_H___*/
+Index: linux-2.6.22/drivers/sdio/function/memory/sdio_memory_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/memory/sdio_memory_linux.h 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,80 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_memory_linux.h
++
++ at abstract: OS dependent include memory card function driver
++
++#notes:
++
++ at notice: Copyright (c), 2004 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_MEMORY_LINUX_H___
++#define __SDIO_MEMORY_LINUX_H___
++
++
++
++#define SDIO_MEMORY_BASE "sdmem"
++#define SDIO_MEMORY_MAX_DEVICES 4
++#define SDIO_MEMORY_MAJOR 0
++//??#define SDIO_MEMORY_MAX_MINOR 4
++#define SDIO_MEMORY_MAX_PARTITIONS 8
++/* sector size is aribtary and matchs the Linux requests */
++//??#define SDIO_MEMORY_SECTOR_SIZE 512
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++typedef sector_t SDSECTOR_SIZE;
++#else
++/* 2.4 */
++typedef unsigned long SDSECTOR_SIZE;
++#endif
++/* driver configuration */
++typedef struct _SDMEMORY_DRIVER_CONFIG {
++ int Major; /* device's major number */
++ struct device *pDevice; /* the parent device we are on*/
++}SDMEMORY_DRIVER_CONFIG, *PSDMEMORY_DRIVER_CONFIG;
++
++/* per device configuration */
++typedef struct _SDMEMORY_CONFIG {
++ struct hci_dev *pHciDev; /* the HCI device */
++ struct gendisk *pGenDisk; /* the disk definition */
++ struct request_queue *pRequestQueue; /* request queue for disk requests*/
++ spinlock_t RequestLock; /* lock for the RequestQueue */
++ spinlock_t DeviceLock; /* lock for this device */
++ atomic_t OpenCount; /* how many opens are current */
++}SDMEMORY_CONFIG, *PSDMEMORY_CONFIG;
++
++
++#endif /*__SDIO_MEMORY_LINUX_H___*/
++
+Index: linux-2.6.22/drivers/sdio/function/memory/sdio_memory_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/memory/sdio_memory_os.c 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,1036 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_memory_os.c
++
++ at abstract: Linux implementation module for SDIO MMC and SD nenory cards driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2004-2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++/* debug level for this module*/
++#define DBG_DECLARE 3;
++#include <linux/sdio/ctsystem.h>
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/blkdev.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++#include <linux/blkpg.h>
++#endif
++#include <linux/genhd.h>
++#include <linux/hdreg.h>
++#include <asm/uaccess.h>
++
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_memory.h"
++#include "sdio_memory_linux.h"
++
++#define DESCRIPTION "SDIO MMC/SD memory card Driver"
++#define AUTHOR "Atheros Communications, Inc."
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++
++BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice);
++static SDIO_STATUS CreateDisk(PSDIO_MEMORY_CONTEXT pDriverContext, PSDIO_MEMORY_INSTANCE pInstance);
++static void DiskRequest(request_queue_t *pQueue);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static void DiskRequestDma(request_queue_t *pQueue);
++static char* ReplaceChar(char* pStr, char Find, char Replace);
++static int CheckDeviceChange(struct gendisk *disk);
++#else
++/* 2.4 */
++static int CheckDeviceChange(kdev_t kdev);
++static int Revalidate(kdev_t i_rdev);
++#endif
++static int DeviceIoctl(struct inode *inode, struct file *filp,
++ unsigned int cmd, unsigned long arg);
++static void DeleteDisk(PSDMEMORY_CONFIG pInstance);
++static int Open(struct inode *inode, struct file *filp);
++static int Release(struct inode *inode, struct file *filp);
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++/* 2.4, only support 1 device */
++#define MEM_SHIFT 3
++static int temp_major;
++#define MAJOR_NR temp_major
++#define DEVICE_NR(device) (MINOR(device) >> MEM_SHIFT)
++#define DEVICE_NAME SDIO_MEMORY_BASE
++#define DEVICE_NO_RANDOM
++#define DEVICE_REQUEST DiskRequest
++
++#include <linux/blk.h>
++
++//??static char GenDiskFlags = GENHD_FL_REMOVABLE;
++static char GenDiskFlags = 0;
++static char GenDiskMajorName[16];
++static int GenSize[SDIO_MEMORY_MAX_PARTITIONS];
++static int GenSize_size[SDIO_MEMORY_MAX_PARTITIONS];
++static int GenHardsects[SDIO_MEMORY_MAX_PARTITIONS];
++static int GenMaxsects[SDIO_MEMORY_MAX_PARTITIONS];
++#ifdef CONFIG_DEVFS
++static devfs_handle_t devfs_handle;
++#endif
++#endif
++
++
++/* devices we support, null terminated */
++static SD_PNP_INFO Ids[] = {
++ //??{.SDMMC_ManfacturerID = 0x00, /* specific MMC card */
++ //?? .SDMMC_OEMApplicationID = 0x0002},
++ {.CardFlags = CARD_SD}, /* all SD cards */
++ {.CardFlags = CARD_MMC}, /* all MMC cards */
++ {}
++};
++
++/* driver wide context data */
++SDIO_MEMORY_CONTEXT DriverContext = {
++ .Driver.Major = SDIO_MEMORY_MAJOR,
++ .Function.pName = "sdio_mem",
++ .Function.Version = CT_SDIO_STACK_VERSION_CODE,
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ .Function.MaxDevices = SDIO_MEMORY_MAX_DEVICES,
++#else
++ .Function.MaxDevices = 1,
++#endif
++ .Function.NumDevices = 0,
++ .Function.pIds = Ids,
++ .Function.pProbe = Probe,
++ .Function.pRemove = Remove,
++ .Function.pSuspend = NULL,
++ .Function.pResume = NULL,
++ .Function.pWake = NULL,
++ .Function.pContext = &DriverContext,
++};
++
++/* supported I/O operations*/
++static struct block_device_operations driver_ops = {
++ .owner = THIS_MODULE,
++ .open = Open,
++ .release = Release,
++ .ioctl = DeviceIoctl,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ .media_changed = CheckDeviceChange,
++#else
++ /* 2.4 */
++ .check_media_change = CheckDeviceChange,
++ .revalidate = Revalidate,
++#endif
++};
++
++
++
++/* per scatter-gather request */
++typedef struct _REQUEST_CONTEXT {
++ PSDIO_MEMORY_INSTANCE pInstance; /* this device */
++ struct request * pOSRequest; /* the request we are working on */
++ UINT SectorsToTransfer; /* the number of sectors transferred */
++ UINT SGcount; /* number of scatter-gather entries */
++ SDDMA_DESCRIPTOR SGlist[0]; /* variable length of scatter gather entries */
++}REQUEST_CONTEXT, *PREQUEST_CONTEXT;
++
++/*
++ * Probe - a device potentially for us
++*/
++BOOL Probe(PSDFUNCTION pFunction, PSDDEVICE pDevice)
++{
++ PSDIO_MEMORY_CONTEXT pDriverContext =
++ (PSDIO_MEMORY_CONTEXT)pFunction->pContext;
++
++ BOOL accept = FALSE;
++ PSDIO_MEMORY_INSTANCE pNewInstance = NULL;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - enter\n"));
++
++ /* make sure we can handle this device type */
++ if ((pDevice->pId[0].CardFlags & CARD_SD) && (pDevice->pId[0].SDIO_FunctionNo == 0)) {
++ /* we check against a zero SDIO function number to make sure this is not an SDIO function
++ * on a combo card which will also have CARD_SD set as well. SDIO functions start
++ * with 1*/
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - SD Card Type Match (MANF:0x%X, OEMID:0x%X) \n",
++ pDevice->pId[0].SDMMC_ManfacturerID, pDevice->pId[0].SDMMC_OEMApplicationID));
++ } else if (pDevice->pId[0].CardFlags & CARD_MMC) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - MMC Card Type Match (MANF:0x%X, OEMID:0x%X) \n",
++ pDevice->pId[0].SDMMC_ManfacturerID, pDevice->pId[0].SDMMC_OEMApplicationID));
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - not ours \n"));
++ return FALSE;
++ }
++
++ do {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - creating instance \n"));
++ pNewInstance = CreateDeviceInstance(pDriverContext, pDevice);
++ if (NULL == pNewInstance) {
++ break;
++ }
++ atomic_set(&pNewInstance->Config.OpenCount, 0);
++
++ /* add it to the list */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - adding instance \n"));
++ AddDeviceInstance(pDriverContext, pNewInstance);
++
++ /* get the card info */
++ GetCardCSD(pDevice, pNewInstance, (pDevice->pId[0].CardFlags & CARD_MMC));
++
++ /* create an OS disk for this device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - creating disk \n"));
++ if (!SDIO_SUCCESS(CreateDisk(pDriverContext, pNewInstance))) {
++ /* failed */
++ break;
++ }
++ accept = TRUE;
++ break;
++ } while (FALSE);
++
++ if (!accept && (pNewInstance != NULL)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Probe - deleting instance \n"));
++ DeleteInstance(pDriverContext, pNewInstance);
++ }
++
++ return accept;
++}
++
++/*
++ * Remove - our device is being removed
++*/
++void Remove(PSDFUNCTION pFunction, PSDDEVICE pDevice)
++{
++ PSDIO_MEMORY_CONTEXT pDriverContext =
++ (PSDIO_MEMORY_CONTEXT)pFunction->pContext;
++ PSDIO_MEMORY_INSTANCE pInstance;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: Remove\n"));
++
++
++ pInstance = FindInstance(pDriverContext, pDevice);
++
++ if (pInstance != NULL) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function:: Removing instance: 0x%X From Remove() \n",
++ (INT)pInstance));
++ DeleteDisk(&pInstance->Config);
++ DeleteInstance(pDriverContext, pInstance);
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function:: could not find matching instance! \n"));
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: Remove\n"));
++}
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++/* 2.4 */
++static struct gendisk* alloc_disk(int minor)
++{
++ struct gendisk* pDisk;
++ int len;
++
++ pDisk = kmalloc(sizeof(struct gendisk), GFP_KERNEL);
++ if (pDisk == NULL) {
++ return NULL;
++ }
++ memset(pDisk, 0, sizeof(struct gendisk));
++ len = (minor-1) * sizeof(struct hd_struct *);
++ pDisk->part = kmalloc(len, GFP_KERNEL);
++ if (pDisk->part == NULL) {
++ kfree(pDisk);
++ return NULL;
++ }
++ memset(pDisk->part, 0, len);
++ pDisk->max_p = minor;
++ pDisk->minor_shift = MEM_SHIFT;
++ //?????partition inits?
++ return pDisk;
++}
++static int add_disk(PSDIO_MEMORY_INSTANCE pInstance, struct gendisk *pDisk)
++{
++ struct hd_struct* pPartitions;
++ /* create the partitions */
++ pPartitions = kmalloc(SDIO_MEMORY_MAX_PARTITIONS * sizeof(struct hd_struct), GFP_KERNEL);
++ if (pPartitions == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: add_disk, no memory\n"));
++ return -ENOMEM;;
++ }
++ memset(pPartitions , 0, SDIO_MEMORY_MAX_PARTITIONS * sizeof(struct hd_struct));
++ pPartitions[0].nr_sects = (GenSize[0] * 1024) / pInstance->FileSysBlockSize;
++ pDisk->part = pPartitions;
++ pDisk->nr_real = 1;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: register_disk, nr_sects: %d, GenSize[0]: %d \n",
++ (UINT)pPartitions[0].nr_sects, (UINT)GenSize[0]));
++ register_disk(pDisk, 0, SDIO_MEMORY_MAX_PARTITIONS,
++ pDisk->fops, pPartitions[0].nr_sects);
++ return 0;
++}
++#endif
++/*
++ * CreateDisk - create the disk that represenst this device
++*/
++static SDIO_STATUS CreateDisk(PSDIO_MEMORY_CONTEXT pDriverContext, PSDIO_MEMORY_INSTANCE pInstance)
++{
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: CreateDisk\n"));
++ pInstance->Config.pGenDisk = alloc_disk(SDIO_MEMORY_MAX_PARTITIONS);
++ if (pInstance->Config.pGenDisk == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: CreateDisk - cannot allocate disk\n"));
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ spin_lock_init(&pInstance->Config.RequestLock);
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ if ((SDGET_DMA_DESCRIPTION(pInstance->pDevice) != NULL) &&
++ ((SDGET_DMA_DESCRIPTION(pInstance->pDevice)->Flags & SDDMA_DESCRIPTION_FLAG_DMA) ||
++ (SDGET_DMA_DESCRIPTION(pInstance->pDevice)->Flags & SDDMA_DESCRIPTION_FLAG_SGDMA))){
++ pInstance->Config.pRequestQueue = blk_init_queue(DiskRequestDma, &pInstance->Config.RequestLock);
++ } else {
++ pInstance->Config.pRequestQueue = blk_init_queue(DiskRequest, &pInstance->Config.RequestLock);
++ }
++#else
++ /* 2.4 */
++ pInstance->Config.pRequestQueue = BLK_DEFAULT_QUEUE(pDriverContext->Driver.Major);
++ blk_init_queue(pInstance->Config.pRequestQueue, DiskRequest);
++#endif
++ if (pInstance->Config.pRequestQueue == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: CreateDisk - cannot allocate queue\n"));
++ /* get rid of our reference from alloc_disk() */
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ put_disk(pInstance->Config.pGenDisk);
++#endif
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ /* not sure if we need to set this, limit the number of blocks per transfer */
++ blk_queue_max_sectors(pInstance->Config.pRequestQueue,
++ pInstance->pDevice->pHcd->CardProperties.OperBlockCountLimit);
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: block size %d\n", pInstance->BlockSize));
++ /* force the file system to use at least a 512 block, seems to break when smaller */
++ pInstance->FileSysBlockSize = (pInstance->BlockSize < 512) ? 512 : pInstance->BlockSize;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: setting block size %d\n",
++ pInstance->FileSysBlockSize));
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ blk_queue_hardsect_size(pInstance->Config.pRequestQueue, pInstance->FileSysBlockSize);
++
++ if (SDGET_DMA_DESCRIPTION(pInstance->pDevice) != NULL) {
++ PSDDMA_DESCRIPTION pDmaDescrp = SDGET_DMA_DESCRIPTION(pInstance->pDevice);
++ if ((pDmaDescrp->Flags & SDDMA_DESCRIPTION_FLAG_DMA) ||
++ (pDmaDescrp->Flags & SDDMA_DESCRIPTION_FLAG_SGDMA)){
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: setting up DMA\n"));
++ /* setup the DMA parameters */
++ blk_queue_dma_alignment(pInstance->Config.pRequestQueue,
++ pDmaDescrp->AddressAlignment);
++ blk_queue_bounce_limit(pInstance->Config.pRequestQueue,
++ pDmaDescrp->Mask);
++ blk_queue_max_segment_size(pInstance->Config.pRequestQueue,
++ pDmaDescrp->MaxBytesPerDescriptor);
++ /* setup the DMA scatter gather parameters */
++ blk_queue_max_phys_segments(pInstance->Config.pRequestQueue,
++ pDmaDescrp->MaxDescriptors);
++ blk_queue_max_hw_segments(pInstance->Config.pRequestQueue,
++ pDmaDescrp->MaxDescriptors);
++ }
++ }
++
++ pInstance->Config.pGenDisk->major = pDriverContext->Driver.Major;
++ /* minor number is incremented for each slot plus the max number of partitions on a disk */
++ pInstance->Config.pGenDisk->first_minor =
++ SDIO_MEMORY_MAX_PARTITIONS * pInstance->pDevice->pHcd->SlotNumber;
++ pInstance->Config.pGenDisk->fops = &driver_ops;
++ pInstance->Config.pGenDisk->private_data = pInstance;
++ pInstance->Config.pGenDisk->flags= GENHD_FL_REMOVABLE;
++ sprintf(pInstance->Config.pGenDisk->disk_name, SDIO_MEMORY_BASE "%d",
++ pDriverContext->Function.NumDevices);
++#ifdef CONFIG_DEVFS
++ snprintf(pInstance->Config.pGenDisk->devfs_name,sizeof(pInstance->Config.pGenDisk->devfs_name),
++ "sdmem_%s",
++ (SD_GET_OS_DEVICE(pInstance->pDevice))->bus_id);
++ /* remove any colons */
++ ReplaceChar(pInstance->Config.pGenDisk->devfs_name, ':', '_');
++
++ pInstance->Config.pGenDisk->driverfs_dev = SD_GET_OS_DEVICE(pInstance->pDevice);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: CreateDisk: devfs_name: %s, 0x%X\n",
++ pInstance->Config.pGenDisk->devfs_name,
++ (INT)pInstance->Config.pGenDisk->driverfs_dev));
++#endif
++
++ set_capacity(pInstance->Config.pGenDisk, pInstance->Size/pInstance->FileSysBlockSize * 1024);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: CreateDisk: size %d (Size %d, FileSysBlockSize %d)\n",
++ pInstance->Size/pInstance->FileSysBlockSize * 1024,
++ (INT)pInstance->Size, (INT)pInstance->FileSysBlockSize));
++ pInstance->Config.pGenDisk->queue = pInstance->Config.pRequestQueue ;
++ /* is it read only ? */
++ set_disk_ro(pInstance->Config.pGenDisk, pInstance->WriteProtected);
++ add_disk(pInstance->Config.pGenDisk);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: CreateDisk major: %d, minors: %d, first_minor: %d\n",
++ pInstance->Config.pGenDisk->major, pInstance->Config.pGenDisk->minors,
++ pInstance->Config.pGenDisk->first_minor));
++#else
++ /* 2.4 */
++ pInstance->Config.pGenDisk->major = pDriverContext->Driver.Major;
++ pInstance->Config.pGenDisk->fops = &driver_ops;
++ pInstance->Config.pGenDisk->flags= &GenDiskFlags;
++ sprintf(GenDiskMajorName, SDIO_MEMORY_BASE "%d",
++ pDriverContext->Function.NumDevices);
++ pInstance->Config.pGenDisk->major_name = GenDiskMajorName;
++
++ {
++ int ii;
++ for (ii = 0; ii < SDIO_MEMORY_MAX_PARTITIONS; ii++) {
++//?? GenSize[ii] = pInstance->Size; /* * 1024, already in kbytes*/
++ GenSize_size[ii] = pInstance->FileSysBlockSize;
++ GenHardsects[ii] = pInstance->FileSysBlockSize;
++ GenMaxsects[ii] = pInstance->pDevice->pHcd->CardProperties.OperBlockCountLimit;
++ }
++ memset(GenSize, 0, sizeof(GenSize));
++ GenSize[0] = pInstance->Size; /* * 1024, already in kbytes*/
++ pInstance->Config.pGenDisk->sizes = GenSize;
++ blk_size[pDriverContext->Driver.Major] = pInstance->Config.pGenDisk->sizes;
++ blksize_size[pDriverContext->Driver.Major] = GenSize_size;
++ hardsect_size[pDriverContext->Driver.Major] = GenHardsects;
++ max_sectors[pDriverContext->Driver.Major] = GenMaxsects;
++ }
++ read_ahead[pDriverContext->Driver.Major] = 2;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: CreateDisk: size %d (Size %d, FileSysBlockSize %d) GenSize[0]: %d\n",
++ pInstance->Size/pInstance->FileSysBlockSize * 1024,
++ (INT)pInstance->Size, (INT)pInstance->FileSysBlockSize, GenSize[0]));
++ /* is it read only ? */
++//?? set_disk_ro(pInstance->Config.pGenDisk, pInstance->WriteProtected);
++ add_disk(pInstance, pInstance->Config.pGenDisk);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: CreateDisk major: %d, max_p: %d\n",
++ pInstance->Config.pGenDisk->major, pInstance->Config.pGenDisk->max_p));
++#endif
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: CreateDisk\n"));
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*
++ * DeleteDisk - remove the disk
++*/
++static void DeleteDisk(PSDMEMORY_CONFIG pConfig)
++{
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DeleteDisk\n"));
++ del_gendisk(pConfig->pGenDisk);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ pConfig->pGenDisk->queue = NULL; //???
++ put_disk(pConfig->pGenDisk);
++ blk_cleanup_queue(pConfig->pRequestQueue);
++#else
++ /* 2.4 */
++ {
++ int ii;
++ int major = DriverContext.Driver.Major;
++ /* flush the devices */
++ for (ii = 0; ii < SDIO_MEMORY_MAX_PARTITIONS; ii++) {
++ fsync_dev(MKDEV(major, ii));
++ }
++
++#ifdef CONFIG_DEVFS
++ devfs_register_partitions(pConfig->pGenDisk, 0, 1);
++ if (devfs_handle) {
++ devfs_unregister(devfs_handle);
++ }
++ devfs_handle = NULL;
++#endif
++
++ invalidate_device (MKDEV(DriverContext.Driver.Major,0), 1);
++
++ blk_cleanup_queue(BLK_DEFAULT_QUEUE(major));
++ read_ahead[major] = 0;
++ blk_size[major] = NULL;
++ if (pConfig->pGenDisk->part != NULL) {
++ kfree(pConfig->pGenDisk->part);
++ }
++ blksize_size[major] = NULL;
++ del_gendisk(pConfig->pGenDisk);
++ }
++#endif
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++/* 2.4 */
++static int Revalidate(kdev_t i_rdev)
++{
++ int index;
++ int max_p;
++ int ii;
++ int start;
++ PSDIO_MEMORY_INSTANCE pInstance = GetFirstInstance(&DriverContext);
++
++ index = DEVICE_NR(i_rdev);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: Revalidate: %d \n", index));
++
++ max_p = pInstance->Config.pGenDisk->max_p;
++ start = index << MEM_SHIFT;
++
++ for (ii = max_p - 1 ; ii >= 0 ; ii--) {
++ int item = start + ii;
++ invalidate_device(MKDEV(DriverContext.Driver.Major, item),1);
++ pInstance->Config.pGenDisk->part[item].start_sect = 0;
++ pInstance->Config.pGenDisk->part[item].nr_sects = 0;
++ }
++
++ register_disk(pInstance->Config.pGenDisk, i_rdev, 1 << MEM_SHIFT, pInstance->Config.pGenDisk->fops,
++ (pInstance->Size * 1024) / pInstance->FileSysBlockSize);
++ return 0;
++}
++#endif
++
++/*
++ * Open - open the device
++*/
++static int Open(struct inode *inode, struct file *filp)
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ PSDIO_MEMORY_INSTANCE pInstance = (PSDIO_MEMORY_INSTANCE)inode->i_bdev->bd_disk->private_data;
++#else
++ /* 2.4 */
++ PSDIO_MEMORY_INSTANCE pInstance = GetFirstInstance(&DriverContext);
++#endif
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: Open\n"));
++ atomic_inc(&pInstance->Config.OpenCount);
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ check_disk_change(inode->i_bdev);
++#else
++ check_disk_change(inode->i_rdev);
++ /* 2.4 */
++#endif
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: Open\n"));
++ return 0;
++}
++
++/*
++ * Release - handle close
++*/
++static int Release(struct inode *inode, struct file *filp)
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ PSDIO_MEMORY_INSTANCE pInstance = (PSDIO_MEMORY_INSTANCE)inode->i_bdev->bd_disk->private_data;
++#else
++ /* 2.4 */
++ PSDIO_MEMORY_INSTANCE pInstance = GetFirstInstance(&DriverContext);
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: Release\n"));
++ atomic_dec(&pInstance->Config.OpenCount);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: Release\n"));
++ return 0;
++}
++
++/*
++ * DiskRequest - process a user request
++*/
++static void DiskRequest(request_queue_t *pQueue)
++{
++ struct request *pRequest;
++ PSDIO_MEMORY_INSTANCE pInstance;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: DiskRequest\n"));
++
++ /* for each request in queue */
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ while ((pRequest = elv_next_request(pQueue)) != NULL) {
++ if (!blk_fs_request(pRequest)) {
++ /* not a command we care about */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequest - unsupported command: flags 0x%X\n",
++ (UINT)pRequest->flags));
++ end_request(pRequest, 0);
++ continue;
++ }
++ pInstance = (PSDIO_MEMORY_INSTANCE)pRequest->rq_disk->private_data;
++ /* we don't need the queue spinlock while processing the head of the queue */
++ spin_unlock_irq(&pInstance->Config.RequestLock);
++ if (SDIO_SUCCESS(MemoryTransfer(pInstance,
++ pRequest->sector, pRequest->current_nr_sectors,
++ pRequest->buffer, rq_data_dir(pRequest)))) {
++#else
++ /* 2.4 */
++#define rq_data_dir(r) ((r)->cmd == WRITE)
++ spin_unlock_irq(&io_request_lock);
++ pInstance = GetFirstInstance(&DriverContext);
++ spin_lock_irq(&pInstance->Config.RequestLock);
++ while(TRUE) {
++ INIT_REQUEST;
++ pRequest = CURRENT;
++ /* we don't need the queue spinlock while processing the head of the queue */
++ spin_unlock_irq(&io_request_lock);
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Memory Function: DiskRequest -sector:%d, nr_sectors: %d, hard_sector: %d, hard_nr_sectors: %d, \n nr_segments: %d, nr_hw_segments: %d, current_nr_sectors: %d, hard_cur_sectors: %d, start_sect: %d, minor: %d\n",
++ (UINT)pRequest->sector, (UINT)pRequest->nr_sectors, (UINT)pRequest->hard_sector,
++ (UINT)pRequest->hard_nr_sectors, (UINT)pRequest->nr_segments, (UINT)pRequest->nr_hw_segments, (UINT)pRequest->current_nr_sectors, (UINT)pRequest->hard_cur_sectors,
++ (UINT)pInstance->Config.pGenDisk->part[MINOR(pRequest->rq_dev)].start_sect, MINOR(pRequest->rq_dev)));
++ if (SDIO_SUCCESS(MemoryTransfer(pInstance,
++ pRequest->sector+pInstance->Config.pGenDisk->part[MINOR(pRequest->rq_dev)].start_sect,
++ pRequest->current_nr_sectors,
++ pRequest->buffer, rq_data_dir(pRequest)))) {
++#endif
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ spin_lock_irq(&pInstance->Config.RequestLock);
++ end_request(pRequest, 1);
++#else
++ /* 2.4 */
++ spin_lock_irq(&io_request_lock);
++ end_request(1);
++#endif
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO Memory Function: DiskRequest - failing request\n"));
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++ spin_lock_irq(&pInstance->Config.RequestLock);
++ end_request(pRequest, 0);
++#else
++ /* 2.4 */
++ spin_lock_irq(&io_request_lock);
++ end_request(0);
++#endif
++ }
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: DiskRequest\n"));
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++/*
++ * AsyncCompletion - asynch I/O completion routine
++*/
++void AsyncCompletion(struct _SDREQUEST *pRequest)
++{
++ PREQUEST_CONTEXT pRegContext = (PREQUEST_CONTEXT)pRequest->pCompleteContext;
++ PSDIO_MEMORY_INSTANCE pInstance = pRegContext->pInstance;
++ struct request * pOSRequest = pRegContext->pOSRequest;
++ UINT sectorsTransferred = pRegContext->SectorsToTransfer;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: AsyncCompletion: status: %d\n",
++ pRequest->Status));
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_DUMP) {
++ SDLIB_PrintBuffer(pOSRequest->buffer,
++ sectorsTransferred* pInstance->BlockSize,
++ "SDIO Memory Function: AsyncCompletion");
++ }
++ KernelFree(pRegContext);
++ SDDeviceFreeRequest(pInstance->pDevice, pRequest);
++
++ /* now deal with the disk request */
++ spin_lock_irq(&pInstance->Config.RequestLock);
++
++ do {
++ if (SDIO_SUCCESS(pRequest->Status)) {
++ if (end_that_request_first(pOSRequest, 1, sectorsTransferred)) {
++ /* more to do */
++ DiskRequestDma(pInstance->Config.pRequestQueue);
++ break;
++ }
++ } else {
++ if (end_that_request_first(pOSRequest, 0, sectorsTransferred)) {
++ /* more to do */
++ DiskRequestDma(pInstance->Config.pRequestQueue);
++ break;
++ }
++ }
++ blkdev_dequeue_request(pOSRequest);
++ end_that_request_last(pOSRequest, 0);
++ } while (FALSE);
++
++ spin_unlock_irq(&pInstance->Config.RequestLock);
++}
++
++/*
++ * AsyncCompletionLast - asynch I/O completion routine, handles last of series of requests
++*/
++void AsyncCompletionLast(struct _SDREQUEST *pRequest)
++{
++ PREQUEST_CONTEXT pRegContext = (PREQUEST_CONTEXT)pRequest->pCompleteContext;
++ PSDIO_MEMORY_INSTANCE pInstance = pRegContext->pInstance;
++ struct request * pOSRequest = pRegContext->pOSRequest;
++ UINT sectorsTransferred = pRegContext->SectorsToTransfer;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: AsyncCompletionLast: status: %d\n",
++ pRequest->Status));
++ if (DBG_GET_DEBUG_LEVEL() >= SDDBG_DUMP) {
++ SDLIB_PrintBuffer(pOSRequest->buffer,
++ sectorsTransferred * pInstance->BlockSize,
++ "SDIO Memory Function: AsyncCompletion");
++ }
++ KernelFree(pRegContext);
++ SDDeviceFreeRequest(pInstance->pDevice, pRequest);
++
++ /* now deal with the disk request */
++ spin_lock_irq(&pInstance->Config.RequestLock);
++
++ do {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: completed sectors :%d nr_sectors: %d \n",
++ (UINT)sectorsTransferred, (UINT)pOSRequest->nr_sectors));
++
++ if (SDIO_SUCCESS(pRequest->Status)) {
++ if (end_that_request_first(pOSRequest, 1, sectorsTransferred)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: end_that_request_first not done!\n"));
++ /* more to do */
++ DiskRequestDma(pInstance->Config.pRequestQueue);
++ break;
++ }
++ } else {
++ if (end_that_request_first(pOSRequest, 0, sectorsTransferred)) {
++ /* more to do */
++ DiskRequestDma(pInstance->Config.pRequestQueue);
++ break;
++ }
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: current disk request done!\n"));
++
++ blkdev_dequeue_request(pOSRequest);
++ end_that_request_last(pOSRequest, 0);
++
++ /* look for more requests */
++ DiskRequestDma(pInstance->Config.pRequestQueue);
++
++ } while (FALSE);
++
++ spin_unlock_irq(&pInstance->Config.RequestLock);
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: AsyncCompletionLast\n"));
++}
++
++/*
++ * DiskRequest - process a user request via DMA
++*/
++static void DiskRequestDma(request_queue_t *pQueue)
++{
++ struct request *pRequest;
++ PSDIO_MEMORY_INSTANCE pInstance;
++ UINT MaxDescriptors;
++ SDIO_STATUS status;
++ INT outstandingReq = 1; /* for now, just queue one at a time */
++ UINT32 checkLength;
++ PREQUEST_CONTEXT pContext;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: DiskRequestDma\n"));
++
++ /* for each request in queue */
++ while ((outstandingReq-- > 0) && ((pRequest = elv_next_request(pQueue)) != NULL)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma : processing block request :0x%X\n",(UINT32)pRequest));
++ if (!blk_fs_request(pRequest)) {
++ /* not a command we care about */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - unsupported command: flags 0x%X\n",
++ (UINT)pRequest->flags));
++ end_request(pRequest, 0);
++ /* reset */
++ outstandingReq = 1;
++ continue;
++ }
++
++ pInstance = (PSDIO_MEMORY_INSTANCE)pRequest->rq_disk->private_data;
++ /* we don't need the queue spinlock while processing the head of the queue */
++ spin_unlock_irq(&pInstance->Config.RequestLock);
++
++ /* allocate a context for ASYNC requests */
++ pContext = KernelAlloc(sizeof(REQUEST_CONTEXT) + ((sizeof(SDDMA_DESCRIPTOR))*pRequest->nr_phys_segments));
++
++ if (pContext == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: DiskRequestDma - no memory, failing request\n"));
++ spin_lock_irq(&pInstance->Config.RequestLock);
++ end_request(pRequest, 0);
++ /* exit */
++ break;
++ }
++
++ pContext->pOSRequest = pRequest;
++ pContext->pInstance = pInstance;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - Phys Segments %d, HW Segments:%d, current_nr_sectors:%d, nr_sectors:%d , hard_nr_sectors:%d \n",
++ pRequest->nr_phys_segments, pRequest->nr_hw_segments, pRequest->current_nr_sectors, (UINT32)pRequest->nr_sectors, (UINT32)pRequest->hard_nr_sectors));
++
++ if (pInstance->FileSysBlockSize != pInstance->BlockSize) {
++ /* incompatible block size, use PIO mode, asynchronously */
++DO_DIO:
++ pContext->SectorsToTransfer = pRequest->current_nr_sectors;
++ status = IssueAsyncTransfer(pInstance->pDevice,
++ pInstance,
++ pRequest->sector * pInstance->FileSysBlockSize,
++ pContext->SectorsToTransfer*pInstance->FileSysBlockSize,
++ rq_data_dir(pRequest),
++ pRequest->buffer,
++ 0,
++ (outstandingReq > 0) ? AsyncCompletion : AsyncCompletionLast,
++ pContext);
++
++ } else {
++ /* try DMA */
++ int ii;
++ UINT32 align = SDGET_DMA_DESCRIPTION(pInstance->pDevice)->AddressAlignment;
++ UINT32 lenAlign = SDGET_DMA_DESCRIPTION(pInstance->pDevice)->LengthAlignment;
++
++ /* process as a DMA */
++ if (!((SDGET_DMA_DESCRIPTION(pInstance->pDevice)->Flags) & SDDMA_DESCRIPTION_FLAG_SGDMA)) {
++ /* single block DMA */
++ DBG_ASSERT_WITH_MSG((pRequest->nr_phys_segments == 1), "SDIO Memory Function: DiskRequestDma, invalid SG size")
++ }
++ /* transfer all sectors */
++ pContext->SectorsToTransfer = pRequest->nr_sectors;
++
++ /* get the scatter gather mapping */
++ MaxDescriptors = blk_rq_map_sg(pQueue, pRequest, pContext->SGlist);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - SG entries: %d, sector start: %d, seccnt: %d\n",
++ MaxDescriptors, (UINT)pRequest->sector, pContext->SectorsToTransfer));
++
++ DBG_ASSERT_WITH_MSG((MaxDescriptors > 0), "SDIO Memory Function: DiskRequestDma, zero descriptors in request")
++
++ checkLength = 0;
++ /* check DMA restrictions */
++ for (ii = 0; ii < MaxDescriptors; ii++) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - SG Index:%d, page: 0x%X, length: %d, offset: 0x%X\n",
++ ii, (UINT)pContext->SGlist[ii].page, pContext->SGlist[ii].length, pContext->SGlist[ii].offset));
++
++ /* check address alignment */
++ if (pContext->SGlist[ii].offset & align) {
++ /* we have some illegal bits here, not a supportable address boundary, go PIO*/
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - punting to direct IO, offset: 0x%X, alignment: 0x%X\n",
++ pContext->SGlist[ii].offset, align));
++ goto DO_DIO;
++ }
++ /* check length alignement */
++ if (pContext->SGlist[ii].length & lenAlign) {
++ /* we have some illegal bits here, not a supportable length go PIO*/
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - punting to direct IO, Length: 0x%X (%d bytes), Length Alignment: 0x%X\n",
++ pContext->SGlist[ii].length, pContext->SGlist[ii].length, lenAlign));
++ goto DO_DIO;
++ }
++ /* we are all good here, add the length */
++ checkLength += pContext->SGlist[ii].length;
++ }
++
++ if (checkLength != pContext->SectorsToTransfer*pInstance->FileSysBlockSize) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: DiskRequestDma - SG Data length and Sector Mismatch! SG Total Length %d, Sectors:%d, bytespersector:%d\n",
++ checkLength, pContext->SectorsToTransfer, pInstance->FileSysBlockSize));
++ goto DO_DIO;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DiskRequestDma - submitting %s using SG entries: %d,len: %d\n",
++ rq_data_dir(pRequest) ? "Write":"Read", MaxDescriptors, (UINT)(pContext->SectorsToTransfer * pInstance->BlockSize)));
++
++ /* issue async transfer */
++ status = IssueAsyncTransfer(pInstance->pDevice,
++ pInstance,
++ pRequest->sector * pInstance->FileSysBlockSize,
++ pContext->SectorsToTransfer*pInstance->FileSysBlockSize,
++ rq_data_dir(pRequest),
++ pContext->SGlist,
++ MaxDescriptors,
++ (outstandingReq > 0)?AsyncCompletion : AsyncCompletionLast, pContext);
++ }
++ /* reacquire the lock, the lock is held on entry of this function */
++ spin_lock_irq(&pInstance->Config.RequestLock);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: DiskRequestDma\n"));
++}
++
++/*
++ ReplaceChar - replace all Find with Replace
++*/
++static char* ReplaceChar(char* pStr, char Find, char Replace)
++{
++ int ii;
++ for(ii = 0; pStr[ii] != 0; ii++) {
++ if (pStr[ii] == Find) {
++ pStr[ii] = Replace;
++ }
++ }
++ return pStr;
++}
++#endif
++
++/*
++ * DeviceIoctl - handle IOCTL requests
++ */
++static int DeviceIoctl(struct inode *inode, struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ struct hd_geometry geometry;
++
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: DeviceIoctl - cmd: %d\n", cmd));
++ switch(cmd) {
++ case HDIO_GETGEO: {
++ /* get device geometry request. Return something reasonable,
++ our device doesn't care */
++ geometry.heads = 4;
++ geometry.sectors = 16;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ geometry.start = get_start_sect(inode->i_bdev);
++ geometry.cylinders = get_capacity(inode->i_bdev->bd_disk) / (4 * 16);
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Memory Function: DeviceIoctl - HDIO_GETGEO, size: %d heads: %d sectors: %d start: %d cylinders: %d\n",
++ (INT)get_capacity(inode->i_bdev->bd_disk),
++ (INT)geometry.heads,
++ (INT)geometry.sectors,
++ (INT)geometry.start,
++ (INT)geometry.cylinders));
++#else
++/* 2.4 */ {
++ PSDIO_MEMORY_INSTANCE pInstance = GetFirstInstance(&DriverContext);
++ geometry.start = 0;
++ geometry.cylinders = (pInstance->Size/pInstance->FileSysBlockSize * 1024) / (4 * 16);
++ DBG_PRINT(SDDBG_TRACE,
++ ("SDIO Memory Function: DeviceIoctl - HDIO_GETGEO, size: %d heads: %d sectors: %d start: %d cylinders: %d\n",
++ (INT)(pInstance->Size/pInstance->FileSysBlockSize * 1024),
++ (INT)geometry.heads,
++ (INT)geometry.sectors,
++ (INT)geometry.start,
++ (INT)geometry.cylinders));
++ }
++#endif
++ if (copy_to_user((void *) arg, &geometry, sizeof(geometry))) {
++ return -EFAULT;
++ }
++ return 0;
++ }
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++/* 2.4 */
++ case BLKGETSIZE: {
++ PSDIO_MEMORY_INSTANCE pInstance = GetFirstInstance(&DriverContext);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DeviceIoctl BLKGETSIZE\n"));
++ if (!access_ok(VERIFY_WRITE, arg, sizeof(long))) {
++ return -EFAULT;
++ }
++ return put_user(pInstance->Config.pGenDisk->part[MINOR(inode->i_rdev)].nr_sects, (long *)arg);
++ }
++ case BLKRRPART: /* re-read partition table */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DeviceIoctl BLKRRPART\n"));
++ if (!capable(CAP_SYS_ADMIN))
++ return -EACCES;
++ return Revalidate(inode->i_rdev);
++
++ default:
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: DeviceIoctl default\n"));
++ return blk_ioctl(inode->i_rdev, cmd, arg);
++
++#endif
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: DeviceIoctl - cmd: %d\n", cmd));
++ return -ENOTTY; /* unknown command */
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++static int CheckDeviceChange(struct gendisk *disk)
++#else
++/* 2.4 */
++static int CheckDeviceChange(kdev_t kdev)
++#endif
++{
++ return 0;
++}
++
++/*
++ * module init
++*/
++static int __init sdio_memory_init(void) {
++ SDIO_STATUS status;
++ SYSTEM_STATUS err;
++
++ REL_PRINT(SDDBG_TRACE, ("+SDIO Memory Function: enter sdio_memory_init\n"));
++
++ SDLIST_INIT(&DriverContext.InstanceList);
++
++ status = SemaphoreInitialize(&DriverContext.InstanceSem, 1);
++ if (!SDIO_SUCCESS(status)) {
++ return SDIOErrorToOSError(status);
++ }
++ /* register with the block core */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ err = register_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE);
++#else
++ /* 2.4 */
++ err = devfs_register_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE, &driver_ops);
++ devfs_handle = devfs_mk_dir(NULL, SDIO_MEMORY_BASE, NULL);
++#endif
++ if (err <= 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: unable to register with block driver, %d\n",
++ (INT)err));
++ return err;
++ }
++ if (DriverContext.Driver.Major == 0) {
++ /* save the assigned major number if it was a dynanmic assignment */
++ DriverContext.Driver.Major = err;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
++ /* 2.4 */
++ temp_major = DriverContext.Driver.Major;
++#endif
++ }
++
++ /* register with bus driver core */
++ if (!SDIO_SUCCESS((status = SDIO_RegisterFunction(&DriverContext.Function)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO Memory Function: failed to register with bus driver, %d\n",
++ status));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ unregister_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE);
++#else
++ devfs_unregister_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE);
++#endif
++ return SDIOErrorToOSError(status);
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO Memory Function: sdio_memory_init, major: %d\n",
++ DriverContext.Driver.Major));
++
++ return 0;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_memory_cleanup(void) {
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO Memory Function: enter sdio_memory_cleanup\n"));
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: sdio_memory_cleanup unregistering sdio device\n"));
++ SDIO_UnregisterFunction(&DriverContext.Function);
++ /* unregister with the block driver core */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: sdio_memory_cleanup unregistering block device, major: %d\n",
++ DriverContext.Driver.Major));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++ unregister_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE);
++#else
++ devfs_unregister_blkdev(DriverContext.Driver.Major, SDIO_MEMORY_BASE);
++#endif
++ DBG_PRINT(SDDBG_TRACE, ("SDIO Memory Function: sdio_memory_cleanup unregistering bus device\n"));
++}
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++module_init(sdio_memory_init);
++module_exit(sdio_memory_cleanup);
++
+Index: linux-2.6.22/drivers/sdio/function/Kconfig
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/Kconfig 2007-11-08 15:52:39.000000000 +0100
+@@ -0,0 +1,32 @@
++
++menu "SDIO function drivers"
++
++config SDIO_AR6000_WLAN
++ tristate "ar6000 wireless networking over sdio"
++ select WIRELESS_EXT
++ default m
++ help
++ good luck.
++
++config SDIO_BLUETOOTH
++ tristate "bluetooth over sdio"
++ default m
++ help
++ good luck.
++
++
++config SDIO_GPS
++ tristate "gps over sdio"
++ default m
++ help
++ good luck.
++
++config SDIO_MEMORY
++ tristate "memory card over sdio"
++ default m
++ help
++ good luck.
++
++
++
++endmenu
+Index: linux-2.6.22/drivers/sdio/function/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/function/Makefile 2007-11-08 15:47:58.000000000 +0100
+@@ -0,0 +1,7 @@
++#
++# SDIO function drivers Makefile
++#
++obj-$(CONFIG_SDIO_BLUETOOTH) += bluetooth/
++obj-$(CONFIG_SDIO_GPS) += gps/
++obj-$(CONFIG_SDIO_MEMORY) += memory/
++obj-$(CONFIG_SDIO_AR6000_WLAN) += wlan/
+\ No newline at end of file
Added: developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_shcd.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_shcd.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/common_atheros_sdiostack_shcd.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,3661 @@
+---
+ drivers/sdio/hcd/pci_std/Makefile | 4
+ drivers/sdio/hcd/pci_std/sdio_hcd_os.c | 569 +++++++
+ drivers/sdio/hcd/stdhost/Makefile | 7
+ drivers/sdio/hcd/stdhost/sdio_std_hcd.c | 1663 ++++++++++++++++++++++
+ drivers/sdio/hcd/stdhost/sdio_std_hcd.h | 330 ++++
+ drivers/sdio/hcd/stdhost/sdio_std_hcd_linux.h | 132 +
+ drivers/sdio/hcd/stdhost/sdio_std_hcd_linux_lib.h | 79 +
+ drivers/sdio/hcd/stdhost/sdio_std_hcd_os.c | 826 ++++++++++
+ 8 files changed, 3610 insertions(+)
+
+Index: linux-2.6.22.5/drivers/sdio/hcd/pci_std/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/pci_std/Makefile 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,4 @@
++obj-m += sdio_pcistd_hcd.o
++
++sdio_pcistd_hcd-objs := sdio_hcd_os.o ../stdhost/sdio_std_hcd.o ../stdhost/sdio_std_hcd_os.o
++
+Index: linux-2.6.22.5/drivers/sdio/hcd/pci_std/sdio_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/pci_std/sdio_hcd_os.c 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,569 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_hcd_os.c
++
++ at abstract: Standard PCI SDIO Host Controller Driver
++
++#notes: includes module load and unload functions
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include "../stdhost/sdio_std_hcd_linux.h"
++#include "../stdhost/sdio_std_hcd.h"
++#include "../stdhost/sdio_std_hcd_linux_lib.h"
++#include <linux/pci.h>
++
++#define DESCRIPTION "SDIO Standard PCI HCD"
++#define AUTHOR "Atheros Communications, Inc."
++
++static INT ForceSDMA = 0;
++module_param(ForceSDMA, int, 0444);
++MODULE_PARM_DESC(ForceSDMA, "Force Host controller to use simple DMA if available");
++
++#define PCI_CLASS_SYSTEM_SDIO 0x0805
++
++/* the config space slot number and start for SD host */
++#define PCI_CONFIG_SLOT 0x40
++#define GET_SLOT_COUNT(config)\
++ ((((config)>>4)& 0x7) +1)
++#define GET_SLOT_FIRST(config)\
++ ((config) & 0x7)
++#define PCI_CONFIG_CLASS 0x09
++#define PCI_SD_DMA_SUPPORTED 0x01
++
++#define SDIO_PCI_BAR_MAPPED 0x01
++
++typedef enum _SDHCD_TYPE {
++ TYPE_CLASS, /* standard class device */
++ TYPE_PCIELLEN, /* Tokyo Electron PCI Ellen card */
++}SDHCD_TYPE, *PSDHCD_TYPE;
++
++ /* PCI devices supported */
++static const struct pci_device_id pci_ids [] = {
++ /* Ellen I */
++ {
++ .vendor = 0x1679, .device = 0x3000,
++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
++ },
++ { /* Ellen II Standard Host */
++ .vendor = 0x10ee, .device = 0x0300,
++ .subvendor = 0x10b5, .subdevice = 0x9030,
++ },
++ { /* Standard Host */
++ PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDIO << 8, 0xFFFFFF00),
++ },
++ { /* end: all zeroes */ }
++};
++
++MODULE_DEVICE_TABLE (pci, pci_ids);
++
++#define SDHCD_PCI_IRQ_HOOKED 0x01
++
++static SYSTEM_STATUS Probe(struct pci_dev *pPCIdevice, const struct pci_device_id *pId);
++static void Remove(struct pci_dev *pPCIdevice);
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r);
++static SDIO_STATUS InitEllen(struct pci_dev *pPCIdevice);
++
++/* tell PCI bus driver about us */
++static struct pci_driver sdio_pci_driver = {
++ .name = "sdio_pcistd_hcd",
++ .id_table = pci_ids,
++
++ .probe = Probe,
++ .remove = Remove,
++
++#ifdef CONFIG_PM
++ .suspend = NULL,
++ .resume = NULL,
++#endif
++};
++
++
++ /* Advanced DMA description */
++SDDMA_DESCRIPTION HcdADMADefaults = {
++ .Flags = SDDMA_DESCRIPTION_FLAG_SGDMA,
++ .MaxDescriptors = SDHCD_MAX_ADMA_DESCRIPTOR,
++ .MaxBytesPerDescriptor = SDHCD_MAX_ADMA_LENGTH,
++ .Mask = SDHCD_ADMA_ADDRESS_MASK,
++ .AddressAlignment = SDHCD_ADMA_ALIGNMENT,
++ .LengthAlignment = SDHCD_ADMA_LENGTH_ALIGNMENT,
++};
++
++ /* simple DMA descriptions */
++SDDMA_DESCRIPTION HcdSDMADefaults = {
++ .Flags = SDDMA_DESCRIPTION_FLAG_DMA,
++ .MaxDescriptors = 1,
++ .MaxBytesPerDescriptor = SDHCD_MAX_SDMA_LENGTH,
++ .Mask = SDHCD_SDMA_ADDRESS_MASK,
++ .AddressAlignment = SDHCD_SDMA_ALIGNMENT,
++ .LengthAlignment = SDHCD_SDMA_LENGTH_ALIGNMENT,
++};
++
++/*
++ * MapAddress - sets up the address for a given BAR
++*/
++static int MapAddress(struct pci_dev *pPCIdevice, char *pName, UINT8 bar, PSDHCD_MEMORY pAddress)
++{
++ if (pci_resource_flags(pPCIdevice, bar) & PCI_BASE_ADDRESS_SPACE ) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO STDPCI HCD: MapAddress, port I/O not supported\n"));
++ return -ENOMEM;
++ }
++ pAddress->Raw = pci_resource_start(pPCIdevice, bar);
++ pAddress->Length = pci_resource_len(pPCIdevice, bar);
++ if (!request_mem_region (pAddress->Raw, pAddress->Length, pName)) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO STDPCI HCD: MapAddress - memory in use: 0x%X(0x%X)\n",
++ (UINT)pAddress->Raw, (UINT)pAddress->Length));
++ return -EBUSY;
++ }
++ pAddress->pMapped = ioremap_nocache(pAddress->Raw, pAddress->Length);
++ if (pAddress->pMapped == NULL) {
++ DBG_PRINT(SDDBG_WARN, ("SDIO STDPCI HCD: MapAddress - unable to map memory\n"));
++ /* cleanup region */
++ release_mem_region (pAddress->Raw, pAddress->Length);
++ return -EFAULT;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: MapAddress - mapped memory: 0x%X(0x%X) to 0x%X\n",
++ (UINT)pAddress->Raw, (UINT)pAddress->Length, (UINT)pAddress->pMapped));
++ return 0;
++}
++
++
++/*
++ * UnmapAddress - unmaps the address
++*/
++static void UnmapAddress(PSDHCD_MEMORY pAddress) {
++ iounmap(pAddress->pMapped);
++ release_mem_region(pAddress->Raw, pAddress->Length);
++ pAddress->pMapped = NULL;
++}
++
++/*
++ * CleanupPCIResources - cleanup PCI resources
++*/
++static void CleanupPCIResources(struct pci_dev *pPCIdevice,
++ PSDHCD_INSTANCE pHcInstance)
++{
++ if (pHcInstance->OsSpecific.InitMask & SDIO_PCI_BAR_MAPPED) {
++ UnmapAddress(&pHcInstance->OsSpecific.Address);
++ pHcInstance->OsSpecific.InitMask &= ~SDIO_PCI_BAR_MAPPED;
++ }
++}
++
++SDIO_STATUS SetUpOneSlotController(PSDHCD_CORE_CONTEXT pStdCore,
++ struct pci_dev *pPCIdevice,
++ UINT SlotNumber,
++ int BAR,
++ BOOL AllowDMA,
++ SDHCD_TYPE Type)
++{
++ SDIO_STATUS status = SDIO_STATUS_ERROR;
++ TEXT nameBuffer[SDHCD_MAX_DEVICE_NAME];
++ PSDHCD_INSTANCE pHcInstance = NULL;
++ UINT startFlags = 0;
++
++ do {
++ /* setup the name */
++ snprintf(nameBuffer, SDHCD_MAX_DEVICE_NAME, "pcistd_%X:%i",
++ (UINT)pPCIdevice,SlotNumber);
++
++ /* create the instance */
++ pHcInstance = CreateStdHcdInstance(&pPCIdevice->dev,
++ SlotNumber,
++ nameBuffer);
++
++ if (NULL == pHcInstance) {
++ status = SDIO_STATUS_NO_RESOURCES;
++ break;
++ }
++ /* map the memory BAR */
++ status = MapAddress(pPCIdevice,
++ pHcInstance->Hcd.pName,
++ (UINT8)BAR,
++ &pHcInstance->OsSpecific.Address);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR,
++ ("SDIO STDPCI HCD: Probe - failed to map device memory address %s 0x%X, status %d\n",
++ pHcInstance->Hcd.pName, (UINT)pci_resource_start(pPCIdevice, BAR),
++ status));
++ break;
++ }
++ pHcInstance->OsSpecific.InitMask |= SDIO_PCI_BAR_MAPPED;
++
++ pHcInstance->pRegs = pHcInstance->OsSpecific.Address.pMapped;
++
++ if (!AllowDMA) {
++ startFlags |= START_HCD_FLAGS_FORCE_NO_DMA;
++ }
++
++ if (ForceSDMA) {
++ startFlags |= START_HCD_FLAGS_FORCE_SDMA;
++ }
++
++ /* startup this instance */
++ status = AddStdHcdInstance(pStdCore,
++ pHcInstance,
++ startFlags,
++ NULL,
++ &HcdSDMADefaults,
++ &HcdADMADefaults);
++
++ } while (FALSE);
++
++ if (!SDIO_SUCCESS(status)) {
++ if (pHcInstance != NULL) {
++ CleanupPCIResources(pPCIdevice,pHcInstance);
++ DeleteStdHcdInstance(pHcInstance);
++ }
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI Probe - HCD:0x%X ready! \n",(UINT)pHcInstance));
++ }
++
++ return status;
++}
++
++
++static void CleanUpHcdCore(struct pci_dev *pPCIdevice, PSDHCD_CORE_CONTEXT pStdCore)
++{
++ PSDHCD_INSTANCE pHcInstance;
++
++ /* make sure interrupts are disabled */
++ if (pStdCore->CoreReserved1 & SDHCD_PCI_IRQ_HOOKED) {
++ pStdCore->CoreReserved1 &= ~SDHCD_PCI_IRQ_HOOKED;
++ free_irq(pPCIdevice->irq, pStdCore);
++ }
++
++ /* remove all hcd instances associated with this PCI device */
++ while (1) {
++ pHcInstance = RemoveStdHcdInstance(pStdCore);
++ if (NULL == pHcInstance) {
++ /* no more instances */
++ break;
++ }
++ DBG_PRINT(SDDBG_TRACE, (" SDIO STDPCI HCD: Remove - removed HC Instance:0x%X, HCD:0x%X\n",
++ (UINT)pHcInstance, (UINT)&pHcInstance->Hcd));
++ /* hcd is now removed, we can clean it up */
++ CleanupPCIResources(pPCIdevice,pHcInstance);
++ DeleteStdHcdInstance(pHcInstance);
++ }
++
++ DeleteStdHostCore(pStdCore);
++}
++
++/*
++ * Probe - probe to setup our device, if present
++*/
++static SYSTEM_STATUS Probe(struct pci_dev *pPCIdevice, const struct pci_device_id *pId)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ int ii;
++ int count;
++ int firstBar;
++ int controllers = 0;
++ UINT8 config;
++ SDHCD_TYPE type = TYPE_CLASS;
++ BOOL dmaSupported = FALSE;
++ PSDHCD_CORE_CONTEXT pStdCore = NULL;
++ SYSTEM_STATUS err = 0;
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: Probe - probing for new device\n"));
++ if (NULL == pId) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STDPCI HCD: Probe - no device\n"));
++ return -EINVAL;
++ }
++
++ if (pci_enable_device(pPCIdevice) < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STDPCI HCD: Probe - failed to enable device\n"));
++ return -ENODEV;
++ }
++
++ if ((pId->vendor == pci_ids[0].vendor) && (pId->device == pci_ids[0].device)) {
++ type = TYPE_PCIELLEN;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: Probe - found PCI Ellen type\n"));
++ }
++
++ do {
++
++ pStdCore = CreateStdHostCore(pPCIdevice);
++
++ if (NULL == pStdCore) {
++ err = -ENOMEM;
++ break;
++ }
++ /* get the number of slots supported and the initial BAR for it */
++ pci_read_config_byte(pPCIdevice, PCI_CONFIG_SLOT, &config);
++ count = GET_SLOT_COUNT(config);
++ firstBar = GET_SLOT_FIRST(config);
++
++ if (type == TYPE_PCIELLEN) {
++ /* move the first bar to the right start place, the original ellen card used a PLX
++ * bridge chip which uses the first BAR for control registers */
++ firstBar = 2;
++ status = InitEllen(pPCIdevice);
++ if (!SDIO_SUCCESS(status)) {
++ err = -ENODEV;
++ break;
++ }
++ }
++
++ if (count > 0) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI: Probe - slot count: %d, first BAR: %d\n", count, firstBar));
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STDPCI: Probe - no slots defined, first BAR: %d\n", firstBar));
++ //pci_disable_device(pPCIdevice);
++ err = -ENODEV;
++ break;
++ }
++ /* see if bus mastering DMA is supported */
++ pci_read_config_byte(pPCIdevice, PCI_CONFIG_CLASS, &config);
++ if (config & PCI_SD_DMA_SUPPORTED) {
++ dmaSupported = TRUE;
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI: Probe - DMA %s enabled in config space: %d\n",
++ (dmaSupported)? "is": "not", dmaSupported));
++
++
++ /* setup an hcd instance for each bar that we have */
++ for(ii = 0; ii < count; ii++, firstBar++) {
++ status = SetUpOneSlotController(pStdCore,
++ pPCIdevice, /* pci device instance */
++ ii, /* std host slot number */
++ firstBar, /* pci BAR for the registers */
++ dmaSupported, /* PCI enabled DMA */
++ type /* specific PCI card type */
++ );
++ if (SDIO_SUCCESS(status)) {
++ controllers++;
++ }
++ }
++
++ if (0 == controllers) {
++ /* if none were created, error */
++ err = -ENODEV;
++ break;
++ }
++
++ /* enable the single PCI controller interrupt
++ Interrupts can be called from this point on */
++ err = request_irq(pPCIdevice->irq, hcd_sdio_irq, SA_SHIRQ,
++ "stdhcdpci", pStdCore);
++
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STDPCI - probe, unable to map interrupt \n"));
++ break;
++ }
++
++ pStdCore->CoreReserved1 |= SDHCD_PCI_IRQ_HOOKED;
++
++ /* startup the hosts..., this will enable interrupts for card detect */
++ status = StartStdHostCore(pStdCore);
++
++ if (!SDIO_SUCCESS(status)) {
++ err = -ENODEV;
++ break;
++ }
++
++ } while (FALSE);
++
++ if (err < 0) {
++ if (pStdCore != NULL) {
++ CleanUpHcdCore(pPCIdevice,pStdCore);
++ }
++ }
++ return err;
++}
++
++/* Remove - remove device
++ * perform the undo of the Probe
++*/
++static void Remove(struct pci_dev *pPCIdevice)
++{
++ PSDHCD_CORE_CONTEXT pStdCore;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO STDPCI HCD: Remove - removing device\n"));
++
++ pStdCore = GetStdHostCore(pPCIdevice);
++
++ if (NULL == pStdCore) {
++ DBG_ASSERT(FALSE);
++ return;
++ }
++
++ CleanUpHcdCore(pPCIdevice, pStdCore);
++
++ /* DO NOT CALL : pci_disable_device(pPCIdevice); this destroys the bus mastering settings
++ * on the PCI device, on re-load DMA transfers will fail ***/
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STDPCI HCD: Remove\n"));
++ return;
++}
++
++/* SDIO interrupt request */
++static irqreturn_t hcd_sdio_irq(int irq, void *context, struct pt_regs * r)
++{
++ irqreturn_t retStat;
++
++ /* call shared handling ISR in case this is a mult-slot controller using 1 PCI IRQ.
++ * if this was not a mult-slot controller or each controller has it's own system
++ * interrupt, we could call HcdSDInterrupt((PSDHCD_INSTANCE)context)) instead */
++ if (HandleSharedStdHostInterrupt((PSDHCD_CORE_CONTEXT)context)) {
++ retStat = IRQ_HANDLED;
++ } else {
++ retStat = IRQ_NONE;
++ }
++
++ return retStat;
++}
++
++/*
++ * module init
++*/
++static int __init sdio_pci_hcd_init(void) {
++ SYSTEM_STATUS err;
++
++ REL_PRINT(SDDBG_TRACE, ("+SDIO STDPCI HCD: loading....\n"));
++ InitStdHostLib();
++
++ /* register with the PCI bus driver */
++ err = pci_module_init(&sdio_pci_driver);
++ if (err < 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STDPCI HCD: failed to register with system PCI bus driver, %d\n",
++ err));
++ }
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STDPCI HCD \n"));
++ return err;
++}
++
++/*
++ * module cleanup
++*/
++static void __exit sdio_pci_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO STDPCI HCD: unloaded\n"));
++ pci_unregister_driver(&sdio_pci_driver);
++ DeinitStdHostLib();
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STDPCI HCD: leave sdio_pci_hcd_cleanup\n"));
++}
++
++/* PLX 9030 control registers */
++#define INTCSR 0x4C
++#define INTCSR_LINTi1ENABLE (1 << 0)
++#define INTCSR_LINTi1STATUS (1 << 2)
++#define INTCSR_LINTi2ENABLE (1 << 3)
++#define INTCSR_LINTi2STATUS (1 << 5)
++#define INTCSR_PCIINTENABLE (1 << 6)
++
++#define GPIOCTRL 0x54
++#define GPIO8_PIN_DIRECTION (1 << 25)
++#define GPIO8_DATA_MASK (1 << 26)
++#define GPIO3_PIN_SELECT (1 << 9)
++#define GPIO3_PIN_DIRECTION (1 << 10)
++#define GPIO3_DATA_MASK (1 << 11)
++#define GPIO2_PIN_SELECT (1 << 6)
++#define GPIO2_PIN_DIRECTION (1 << 7)
++#define GPIO2_DATA_MASK (1 << 8)
++#define GPIO4_PIN_SELECT (1 << 12)
++#define GPIO4_PIN_DIRECTION (1 << 13)
++#define GPIO4_DATA_MASK (1 << 14)
++
++#define GPIO_CONTROL(pDevice, on, GpioMask) \
++{ \
++ UINT32 temp; \
++ temp = READ_CONTROL_REG32((pDevice),GPIOCTRL); \
++ if (on) temp |= (GpioMask); else temp &= ~(GpioMask); \
++ WRITE_CONTROL_REG32((pDevice),GPIOCTRL, temp); \
++}
++
++static SDIO_STATUS InitEllen(struct pci_dev *pPCIdevice)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ SDHCD_MEMORY controlRegs;
++ UINT32 temp;
++ BOOL mapped = FALSE;
++
++ do {
++ /* map the slots control register BAR */
++ status = MapAddress(pPCIdevice,
++ "EllenPCI",
++ (UINT8)0,
++ &controlRegs);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ mapped = TRUE;
++
++ temp = _READ_WORD_REG((((UINT32)controlRegs.pMapped) + INTCSR));
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: InitEllen Init:INTCSR - 0x%X\n", (UINT)temp));
++
++ temp |= INTCSR_LINTi1ENABLE | INTCSR_LINTi2ENABLE | INTCSR_PCIINTENABLE;
++
++ /* enable local to PCI interrupts */
++ _WRITE_WORD_REG((((UINT32)controlRegs.pMapped) + INTCSR), (UINT16)temp);
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: InitEllen Wrote:INTCSR - 0x%X\n", (UINT)temp));
++
++ /*
++ temp = READ_CONTROL_REG32((pHcInstance),GPIOCTRL);
++ temp &= ~(GPIO3_PIN_SELECT | GPIO2_PIN_SELECT | GPIO4_PIN_SELECT);
++ temp |= (GPIO8_PIN_DIRECTION | GPIO3_PIN_DIRECTION | GPIO2_PIN_DIRECTION | GPIO4_PIN_DIRECTION);
++ WRITE_CONTROL_REG32((pHcInstance),GPIOCTRL, temp);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STDPCI HCD: InitEllen GPIOCTRL - 0x%X\n", (UINT)temp));
++ */
++
++ TRACE_SIGNAL_DATA_WRITE(pHcInstance, FALSE);
++ TRACE_SIGNAL_DATA_READ(pHcInstance, FALSE);
++ TRACE_SIGNAL_DATA_ISR(pHcInstance, FALSE);
++ TRACE_SIGNAL_DATA_IOCOMP(pHcInstance, FALSE);
++
++ } while (FALSE);
++
++ if (mapped) {
++ UnmapAddress(&controlRegs);
++ }
++ return status;
++}
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(sdio_pci_hcd_init);
++module_exit(sdio_pci_hcd_cleanup);
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/Makefile 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,7 @@
++#
++# SDIO standard host controller makefile
++#
++obj-m += sdio_std_hcd.o
++
++sdio_std_hcd-objs := sdio_std_hcd.o sdio_std_hcd_os.o
++
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd.c 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,1663 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_std_hcd.c
++
++ at abstract: SDIO standard host controller implementation
++
++#notes: OS independent code
++
++ at notice: Copyright (c), 2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#include "sdio_std_hcd.h"
++
++#define CLOCK_ON TRUE
++#define CLOCK_OFF FALSE
++
++SDIO_STATUS SetPowerLevel(PSDHCD_INSTANCE pHcInstance, BOOL On, SLOT_VOLTAGE_MASK Level);
++SDIO_STATUS ProcessCommandDone(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq, BOOL FromIsr);
++
++ /* clock divisor table */
++SD_CLOCK_TBL_ENTRY SDClockDivisorTable[SD_CLOCK_MAX_ENTRIES] =
++{ /* clock rate divisor, divisor setting */
++ {1, 0x0000},
++ {2, 0x0100},
++ {4, 0x0200},
++ {8, 0x0400},
++ {16,0x0800},
++ {32,0x1000},
++ {64,0x2000},
++ {128,0x4000},
++ {256,0x8000},
++};
++
++ /* register polling change macro */
++#define WAIT_REGISTER32_CHANGE(pHcInstance, pStatus, reg,mask,cmp,timout) \
++ {\
++ if (!WaitRegisterBitsChange((pHcInstance), \
++ (pStatus), \
++ (reg), \
++ (mask), \
++ (cmp), \
++ (timout))) { \
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - Reg Change Timeout : 0x%X src:%s, line:%d \n",\
++ (reg),__FILE__, __LINE__)); \
++ } \
++ }
++
++#define WAIT_REGISTER32_CHANGE_OR(pHcInstance, pStatus, reg,mask,ormask,timout) \
++ {\
++ if (!WaitRegisterBitsChangeOR((pHcInstance), \
++ (pStatus), \
++ (reg), \
++ (mask), \
++ (ormask), \
++ (timout))) { \
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - Reg Change Timeout : 0x%X src:%s, line:%d \n",\
++ (reg),__FILE__, __LINE__)); \
++ } \
++ }
++
++
++ /* command data ready polling macro */
++#define WAIT_FOR_DAT_CMD_DAT_READY(pHcInstance, pStatus) \
++ WAIT_REGISTER32_CHANGE(pHcInstance, \
++ pStatus, \
++ HOST_REG_PRESENT_STATE,(HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_DAT | \
++ HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD), \
++ 0, pHcInstance->PresentStateWaitLimit)
++
++ /* function to wait for a register bit(s) change */
++static BOOL WaitRegisterBitsChange(PSDHCD_INSTANCE pHcInstance,
++ SDIO_STATUS *pStatus,
++ UINT32 Reg,
++ UINT32 Mask,
++ UINT32 CompareMask,
++ UINT32 Count)
++{
++ while (Count) {
++
++ if ((READ_HOST_REG32(pHcInstance, Reg) & Mask) == CompareMask) {
++ break;
++ }
++
++ Count--;
++ }
++
++ if (0 == Count) {
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_ERROR;
++ }
++ return FALSE;
++ }
++
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_SUCCESS;
++ }
++
++ return TRUE;
++}
++
++static BOOL WaitRegisterBitsChangeOR(PSDHCD_INSTANCE pHcInstance,
++ SDIO_STATUS *pStatus,
++ UINT32 Reg,
++ UINT32 Mask,
++ UINT32 OrMask,
++ UINT32 Count)
++{
++ while (Count) {
++
++ if ((READ_HOST_REG32(pHcInstance, Reg) & Mask) & OrMask) {
++ break;
++ }
++
++ Count--;
++ }
++
++ if (0 == Count) {
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_ERROR;
++ }
++ return FALSE;
++ }
++
++ if (pStatus != NULL) {
++ *pStatus = SDIO_STATUS_SUCCESS;
++ }
++
++ return TRUE;
++}
++
++ /* reset command data line state machines */
++void _DoResetCmdDatLine(PSDHCD_INSTANCE pHcInstance)
++{ /* issue reset */
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_SW_RESET,
++ (HOST_REG_SW_RST_CMD_LINE | HOST_REG_SW_RST_DAT_LINE));
++ /* wait for bits to clear */
++ WAIT_REGISTER32_CHANGE(pHcInstance,
++ NULL,
++ HOST_REG_SW_RESET,
++ HOST_REG_SW_RST_CMD_LINE | HOST_REG_SW_RST_DAT_LINE,
++ 0,
++ pHcInstance->ResetWaitLimit);
++}
++
++#define ResetCmdDatLine(pHc) \
++{ \
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST - **** reseting cmd data at line:%d \n",\
++ __LINE__)); \
++ _DoResetCmdDatLine((pHc)); \
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ GetResponseData - get the response data
++ Input: pHcInstance - device context
++ pReq - the request
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void GetResponseData(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq)
++{
++ INT dwordCount;
++ INT byteCount;
++ UINT32 readBuffer[4];
++ INT ii;
++
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_NO_RESP) {
++ return;
++ }
++
++
++ byteCount = SD_DEFAULT_RESPONSE_BYTES;
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = SD_R2_RESPONSE_BYTES;
++ }
++ dwordCount = (byteCount + 3) / 4;
++
++ /* move data into read buffer */
++ for (ii = 0; ii < dwordCount; ii++) {
++ readBuffer[ii] = READ_HOST_REG32(pHcInstance, HOST_REG_RESPONSE+(ii*4));
++ }
++
++ /* handle normal SD/MMC responses */
++
++ /* the standard host strips the CRC for all responses and puts them in
++ * a nice linear order */
++ memcpy(&pReq->Response[1],readBuffer,byteCount);
++
++ if (DBG_GET_DEBUG_LEVEL() >= STD_HOST_TRACE_REQUESTS) {
++ if (GET_SDREQ_RESP_TYPE(pReq->Flags) == SDREQ_FLAGS_RESP_R2) {
++ byteCount = 17;
++ }
++ SDLIB_PrintBuffer(pReq->Response,byteCount,"SDIO STD HOST - Response Dump");
++ }
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ DumpCurrentRequestInfo - debug dump
++ Input: pHcInstance - device context
++ Output:
++ Return:
++ Notes: This function debug prints the current request
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void DumpCurrentRequestInfo(PSDHCD_INSTANCE pHcInstance)
++{
++ PSDREQUEST pRequest = GET_CURRENT_REQUEST(&pHcInstance->Hcd);
++ if (pRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - Current Request Command:%d, ARG:0x%8.8X\n",
++ pRequest->Command, pRequest->Argument));
++ if (IS_SDREQ_DATA_TRANS(pRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(pRequest->Flags) ? "WRITE":"READ",
++ pRequest->BlockCount,
++ pRequest->BlockLen,
++ pRequest->DataRemaining));
++ }
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ TranslateSDError - check for an SD error
++ Input: pHcInstance - device context
++ Status - error interrupt status register value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS TranslateSDError(PSDHCD_INSTANCE pHcInstance, UINT16 ErrorMask)
++{
++ SDIO_STATUS status = SDIO_STATUS_DEVICE_ERROR;
++
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - TranslateSDError :0x%X \n",ErrorMask));
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - RESP CRC ERROR \n"));
++ status = SDIO_STATUS_BUS_RESP_CRC_ERR;
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - DATA TIMEOUT ERROR \n"));
++ status = SDIO_STATUS_BUS_READ_TIMEOUT;
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_DATACRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - READ or WRITE DATA CRC ERROR \n"));
++ status = SDIO_STATUS_BUS_READ_CRC_ERR;
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR) {
++ if (pHcInstance->CardInserted) {
++ /* hide error if we are polling an empty slot */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST - RESPONSE TIMEOUT \n"));
++ }
++ status = SDIO_STATUS_BUS_RESP_TIMEOUT;
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_VENDOR_MASK) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt vendor error 0x%X: \n",
++ (UINT)((ErrorMask & HOST_REG_ERROR_INT_STATUS_VENDOR_MASK) >>
++ HOST_REG_ERROR_INT_STATUS_VENDOR_SHIFT)));
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_AUTOCMD12ERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt auto cmd12 error\n"));
++ }
++
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CURRENTLIMITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt current limit error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_DATAENDBITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt data end bit error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt data timeout error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CMDINDEXERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt CMD index error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CMDENDBITERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt CMD end bit error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_CRCERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt CRC error\n"));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_SDMAERR) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt SDMA error (system address:0x%X\n",
++ READ_HOST_REG32(pHcInstance, HOST_REG_SYSTEM_ADDRESS)));
++ }
++ if (ErrorMask & HOST_REG_ERROR_INT_STATUS_ADMAERR) {
++ UINT32 dmaErrStatus;
++ dmaErrStatus = READ_HOST_REG32(pHcInstance, HOST_REG_ADMA_ERR_STATUS);
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST HcdSDInterrupt ADMA error status: 0x%X \n",
++ dmaErrStatus));
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST, ADMA Descriptor Start ADMA %s Address: 0x%X\n",
++ (dmaErrStatus & HOST_REG_ADMA_STATE_MASK) == HOST_REG_ADMA_STATE_FDS ? "Bad" : "Current",
++ READ_HOST_REG32(pHcInstance, HOST_REG_ADMA_ADDRESS)));
++ DumpDMADescriptorsInfo(pHcInstance);
++ }
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ ClockStartStop - SD clock control
++ Input: pHcInstance - device object
++ On - turn on or off (TRUE/FALSE)
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void ClockStartStop(PSDHCD_INSTANCE pHcInstance, BOOL On)
++{
++ /* beware, an unprotected read-modify-write */
++ UINT16 state;
++
++ DBG_PRINT(STD_HOST_TRACE_CLOCK, ("SDIO STD HOST - ClockStartStop, %d\n", (UINT)On));
++
++ state = READ_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL);
++
++ if (On) {
++ state |= HOST_REG_CLOCK_CONTROL_SD_ENABLE;
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL, state);
++ } else {
++ state &= ~HOST_REG_CLOCK_CONTROL_SD_ENABLE;
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL, state);
++ }
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetBusMode - Set Bus mode
++ Input: pHcInstance - device object
++ pMode - mode
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetBusMode(PSDHCD_INSTANCE pHcInstance, PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ int ii;
++ int clockIndex;
++ UINT32 rate;
++ UINT16 state;
++ UINT8 control;
++
++ DBG_PRINT(STD_HOST_TRACE_CONFIG , ("SDIO STD HOST - SetMode\n"));
++
++ /* set clock index to the end, the table is sorted this way */
++ clockIndex = SD_CLOCK_MAX_ENTRIES - 1;
++ pMode->ActualClockRate = (pHcInstance->BaseClock) / SDClockDivisorTable[clockIndex].ClockRateDivisor;
++ for (ii = 0; ii < SD_CLOCK_MAX_ENTRIES; ii++) {
++ rate = pHcInstance->BaseClock / SDClockDivisorTable[ii].ClockRateDivisor;
++ if (pMode->ClockRate >= rate) {
++ pMode->ActualClockRate = rate;
++ clockIndex = ii;
++ break;
++ }
++ }
++
++ control = READ_HOST_REG8(pHcInstance, HOST_REG_CONTROL);
++ control &= ~HOST_REG_CONTROL_BUSWIDTH_BITS;
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ control |= HOST_REG_CONTROL_1BIT_WIDTH;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ control |= HOST_REG_CONTROL_4BIT_WIDTH;
++ break;
++ case SDCONFIG_BUS_WIDTH_MMC8_BIT:
++ control |= HOST_REG_CONTROL_EXTENDED_DATA;
++ break;
++ default:
++ DBG_PRINT(SDDBG_TRACE , ("SDIO STD HOST - SetMode, unknown bus width requested 0x%X\n", pMode->BusModeFlags));
++ break;
++ }
++ if (pMode->BusModeFlags & SDCONFIG_BUS_MODE_SD_HS) {
++ control |= HOST_REG_CONTROL_HI_SPEED;
++ }
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_CONTROL, control);
++
++ /* set the clock divisor, unprotected read modify write */
++ state = SDClockDivisorTable[clockIndex].RegisterValue |
++ (UINT16)HOST_REG_CLOCK_CONTROL_CLOCK_ENABLE;
++
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL, state);
++
++ /* wait for stable */
++ while(!(READ_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL) &
++ (UINT16)HOST_REG_CLOCK_CONTROL_CLOCK_STABLE)) {
++ ;
++ }
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL, state |
++ (UINT16)HOST_REG_CLOCK_CONTROL_SD_ENABLE);
++
++ state = READ_HOST_REG16(pHcInstance, HOST_REG_CLOCK_CONTROL);
++ DBG_PRINT(STD_HOST_TRACE_CONFIG , ("SDIO STD HOST - Clock: %d Hz, ClockRate %d (%d) state:0x%X control:0x%X\n",
++ pMode->ActualClockRate, pMode->ClockRate, clockIndex, (UINT)state, (UINT)control));
++
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdTransferTxData - data transmit transfer
++ Input: pHcInstance - device object
++ pReq - transfer request
++ Output:
++ Return:
++ Notes: writes request data
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdTransferTxData(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++
++ dataCopy = min(pReq->DataRemaining, (UINT)pReq->BlockLen);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* set the block data */
++ while(dataCopy) {
++ UINT32 outData = 0;
++ UINT count = 0;
++ if (dataCopy > 4) {
++ outData = ((UINT32)(*(pBuf+0))) |
++ (((UINT32)(*(pBuf+1))) << 8) |
++ (((UINT32)(*(pBuf+2))) << 16) |
++ (((UINT32)(*(pBuf+3))) << 24);
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_BUFFER_DATA_PORT, outData);
++ dataCopy -= 4;
++ pBuf += 4;
++ } else {
++ for(count = 0; (dataCopy > 0) && (count < 4); count++) {
++ outData |= (*pBuf) << (count*8);
++ pBuf++;
++ dataCopy--;
++ }
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_BUFFER_DATA_PORT, outData);
++ }
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++ if (pReq->DataRemaining) {
++ return FALSE;
++ }
++ return TRUE;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdTransferRxData - data receive transfer
++ Input: pHcInstance - device object
++ pReq - transfer request
++ Output:
++ Return:
++ Notes: reads request data
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdTransferRxData(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq)
++{
++ INT dataCopy;
++ PUINT8 pBuf;
++
++ dataCopy = min(pReq->DataRemaining, (UINT)pReq->BlockLen);
++ pBuf = (PUINT8)pReq->pHcdContext;
++
++ /* update remaining count */
++ pReq->DataRemaining -= dataCopy;
++ /* set the block data */
++ while(dataCopy) {
++ UINT32 inData;
++ UINT count = 0;
++ inData = READ_HOST_REG32(pHcInstance, HOST_REG_BUFFER_DATA_PORT);
++ for(count = 0; (dataCopy > 0) && (count < 4); count++) {
++ *pBuf = (inData >> (count*8)) & 0xFF;
++ dataCopy--;
++ pBuf++;
++ }
++ }
++
++ /* update pointer position */
++ pReq->pHcdContext = (PVOID)pBuf;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdRequest - SD request handler
++ Input: pHcd - HCD object
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdRequest(PSDHCD pHcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_INSTANCE pHcInstance = (PSDHCD_INSTANCE)pHcd->pContext;
++ UINT16 temp;
++ PSDREQUEST pReq;
++
++ pReq = GET_CURRENT_REQUEST(pHcd);
++ DBG_ASSERT(pReq != NULL);
++
++ /* make sure clock is off */
++ ClockStartStop(pHcInstance, CLOCK_OFF);
++
++ /* make sure error ints are disabled */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE,0);
++
++ /* mask the remove while we are spinning on the CMD ready bits */
++ MaskIrq(pHcInstance, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY,FALSE);
++
++ do {
++
++ if (pHcInstance->ShuttingDown) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdRequest returning canceled\n"));
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ switch (GET_SDREQ_RESP_TYPE(pReq->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ temp = 0x00;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ temp = 0x01 |
++ HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE;
++ break;
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ temp = 0x02;
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ temp = 0x02 | HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE
++ | HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE;
++ break;
++ case SDREQ_FLAGS_RESP_R1B:
++ temp = 0x03 | HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE
++ | HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE;
++ break;
++ default:
++ temp = 0x00;
++ DBG_ASSERT(FALSE);
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ break;
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ /* check and see if the card is still there... on some
++ * host controller implementations card removal seems to prevent the
++ * controller from actually starting the request */
++ WAIT_REGISTER32_CHANGE(pHcInstance,
++ &status,
++ HOST_REG_PRESENT_STATE,
++ HOST_REG_PRESENT_STATE_CARD_STATE_STABLE,
++ HOST_REG_PRESENT_STATE_CARD_STATE_STABLE,
++ pHcInstance->PresentStateWaitLimit);
++
++ if (!SDIO_SUCCESS(status)) {
++ /* card detect could not stabilize, card might be ejecting */
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ if (!(READ_HOST_REG32(pHcInstance, HOST_REG_PRESENT_STATE) &
++ HOST_REG_PRESENT_STATE_CARD_INSERTED)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST Card Removed! \n"));
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ /* start the clock */
++ ClockStartStop(pHcInstance, CLOCK_ON);
++ WAIT_FOR_DAT_CMD_DAT_READY(pHcInstance, &status);
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetCmdDatLine(pHcInstance);
++ break;
++ }
++
++ /* clear any error statuses */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_NORMAL_INT_STATUS, HOST_REG_NORMAL_INT_STATUS_CLEAR_ALL);
++
++ /* set the argument register */
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_ARGUMENT, pReq->Argument);
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST HcdRequest %s Data Transfer, Blocks:%d, BlockLen:%d \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->BlockCount, pReq->BlockLen));
++ /* set the block size register */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_BLOCK_SIZE, pReq->BlockLen);
++ /* set block count register */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_BLOCK_COUNT, pReq->BlockCount);
++ /* set flag in command register */
++ temp |= HOST_REG_COMMAND_REGISTER_DATA_PRESENT;
++
++ pReq->DataRemaining = pReq->BlockLen * pReq->BlockCount;
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ /* setup DMA , note, for SDMA, this routine could modify HOST_REG_BLOCK_SIZE*/
++ status = SetUpHCDDMA(pHcInstance, pReq);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ } else {
++ /* use the context to hold where we are in the buffer */
++ pReq->pHcdContext = pReq->pDataBuffer;
++ }
++ }
++
++#if 1
++ {
++ UINT32 test;
++
++ test = READ_HOST_REG32(pHcInstance, HOST_REG_ARGUMENT);
++ if (test != pReq->Argument) {
++ DBG_ASSERT(FALSE);
++ DBG_PRINT(SDDBG_ERROR, ("*********Argument:0x%X, Shouldbe:0x%X \n",
++ test,pReq->Argument));
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_ARGUMENT, pReq->Argument);
++ }
++
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS){
++ test = READ_HOST_REG16(pHcInstance, HOST_REG_BLOCK_SIZE) & HOST_REG_BLOCK_SIZE_LEN_MASK;
++ if (test != pReq->BlockLen) {
++ DBG_PRINT(SDDBG_ERROR, ("******BlockLength!!!! :0x%X, Should be:0x%X \n",
++ test,pReq->BlockLen));
++ if ( IS_HCD_SDMA(pHcInstance)) {
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_BLOCK_SIZE,
++ pReq->BlockLen | (UINT16)HOST_REG_BLOCK_SIZE_DMA_512K_BOUNDARY);
++ }
++ }
++ test = READ_HOST_REG16(pHcInstance, HOST_REG_BLOCK_COUNT);
++ if (test != pReq->BlockCount) {
++ DBG_PRINT(SDDBG_ERROR, ("******BlockCount!!!! :0x%X, Should be:0x%X \n",
++ test,pReq->BlockCount));
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_BLOCK_COUNT, pReq->BlockCount);
++ }
++ }
++ }
++#endif
++
++ /* set transfer mode register */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_TRANSFER_MODE,
++ ((pReq->BlockCount > 1) ? HOST_REG_TRANSFER_MODE_MULTI_BLOCK:0) |
++ ((pReq->BlockCount > 1) ? HOST_REG_TRANSFER_MODE_BLOCKCOUNT_ENABLE:0) |
++ ((pReq->Flags & SDREQ_FLAGS_AUTO_CMD12) ? HOST_REG_TRANSFER_MODE_AUTOCMD12 : 0) |
++ ((IS_SDREQ_WRITE_DATA(pReq->Flags))? 0 : HOST_REG_TRANSFER_MODE_READ) |
++ ((pReq->Flags & SDREQ_FLAGS_DATA_DMA)? HOST_REG_TRANSFER_MODE_DMA_ENABLE : 0));
++
++ /* set command register, make sure it is clear to write */
++ temp |= (pReq->Command << HOST_REG_COMMAND_REGISTER_CMD_SHIFT);
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST HcdRequest - CMDDAT:0x%X (RespType:%d, Command:0x%X , Arg:0x%X) \n",
++ temp, GET_SDREQ_RESP_TYPE(pReq->Flags), pReq->Command, pReq->Argument));
++
++ /* enable error status */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERR_STATUS_ENABLE, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ if (SDHCD_GET_OPER_CLOCK(pHcd) < pHcInstance->ClockSpinLimit) {
++ /* clock rate is very low, need to use interrupts here */
++
++ /* enable error interrupts */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ /* enable command complete IRQ */
++ UnmaskIrq(pHcInstance, HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE,FALSE);
++
++ /* enable error signal - hit it again */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ /* enable error status - hit it again */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_ERR_STATUS_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST HcdRequest using interrupt for command done (%s). (clock:%d, ref:%d)\n",
++ (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) ? "command only" : "with data",
++ SDHCD_GET_OPER_CLOCK(pHcd),
++ pHcInstance->ClockSpinLimit));
++
++ /* start the command */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_COMMAND_REGISTER, temp);
++ status = SDIO_STATUS_PENDING;
++ break;
++ }
++
++ /* if we get here we are doing this inline using polling */
++
++ /* write command */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_COMMAND_REGISTER, temp);
++
++ /* wait for command to finish */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_TRANS) {
++ WAIT_REGISTER32_CHANGE(pHcInstance,
++ &status,
++ HOST_REG_PRESENT_STATE,
++ HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD,
++ 0, pHcInstance->PresentStateWaitLimit);
++ } else {
++ WAIT_FOR_DAT_CMD_DAT_READY(pHcInstance, &status);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetCmdDatLine(pHcInstance);
++ break;
++ }
++
++ /* get errors */
++ temp = READ_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS);
++
++ if (temp != 0) {
++ status = TranslateSDError(pHcInstance, temp);
++ /* clear any existing errors - non-synchronized clear */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* reset command dat , just in case */
++ ResetCmdDatLine(pHcInstance);
++ break;
++ }
++
++ /* process the command */
++ status = ProcessCommandDone(pHcInstance, pReq, FALSE);
++
++ } while (FALSE);
++
++ if (status != SDIO_STATUS_PENDING) {
++ if (!pHcInstance->KeepClockOn) {
++ ClockStartStop(pHcInstance, CLOCK_OFF);
++ }
++ pReq->Status = status;
++ /* cleanup DMA */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ /* cleanup DMA if it was setup */
++ HcdTransferDataDMAEnd(pHcInstance,pReq);
++ }
++ if (IS_SDREQ_FORCE_DEFERRED_COMPLETE(pReq->Flags)) {
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST deferring completion to work item \n"));
++ /* the HCD must do the indication in a separate context and return status pending */
++ QueueEventResponse(pHcInstance, WORK_ITEM_IO_COMPLETE);
++ /* return pending */
++ status = SDIO_STATUS_PENDING;
++ } else {
++ /* complete the request */
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST Command Done, status:%d \n", status));
++ }
++ pHcInstance->Cancel = FALSE;
++ } else {
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST Bus Request Pending.... \n"));
++ }
++
++ /* now allow removal again */
++ UnmaskIrq(pHcInstance, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY,FALSE);
++ return status;
++}
++
++
++SDIO_STATUS ProcessCommandDone(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq, BOOL FromIsr)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ BOOL shortTransfer = FALSE;
++ UINT16 errors = 0;
++
++ do {
++
++ if (pHcInstance->Cancel) {
++ status = SDIO_STATUS_CANCELED;
++ break;
++ }
++
++ /* get the response data for the command */
++ GetResponseData(pHcInstance, pReq);
++
++ /* check for data */
++ if (!(pReq->Flags & SDREQ_FLAGS_DATA_TRANS)) {
++ /* no data phase, we're done */
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++ /* check with the bus driver if it is okay to continue with data */
++ status = SDIO_CheckResponse(&pHcInstance->Hcd, pReq, SDHCD_CHECK_DATA_TRANS_OK);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST : Response for Data transfer error :%d n",status));
++ break;
++ }
++
++ /* check for short transfer */
++ if ((pReq->Flags & SDREQ_FLAGS_DATA_SHORT_TRANSFER) &&
++ (pReq->DataRemaining <= STD_HOST_SHORT_TRANSFER_THRESHOLD) &&
++ (SDHCD_GET_OPER_CLOCK(&pHcInstance->Hcd) >= pHcInstance->ClockSpinLimit)) {
++ /* we will do a short transfer */
++ shortTransfer = TRUE;
++ break;
++ }
++
++ /* normal data transfers involve interrupts */
++ status = SDIO_STATUS_PENDING;
++ /* re-enable all errors for data transfers */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE,
++ HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ /* handle DMA case */
++ /* expecting interrupt */
++ UnmaskIrq(pHcInstance, HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE,FromIsr);
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST Pending DMA %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++ break;
++ }
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ UINT16 ints;
++ /* write data, see if the buffer is ready, it should be */
++ ints = READ_HOST_REG16(pHcInstance, HOST_REG_NORMAL_INT_STATUS);
++ if (ints & HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY) {
++ /* acknowledge it */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY);
++ /* send the initial buffer */
++ /* transfer data */
++ if (HcdTransferTxData(pHcInstance, pReq)) {
++ /* data fits in buffer */
++ /* wait for transfer complete */
++ UnmaskIrqFromIsr(pHcInstance,
++ HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE);
++ break;
++ }
++
++ /* fall through and enable write buffer interrupts */
++ }
++
++ /* expecting write buffer ready interrupt */
++ UnmaskIrq(pHcInstance,
++ HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE,
++ FromIsr);
++
++ } else {
++ /* expecting read buffer ready data */
++ UnmaskIrq(pHcInstance,
++ HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE,
++ FromIsr);
++ }
++
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST Pending %s transfer \n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++
++ } while (FALSE);
++
++ /* check short transfer */
++ while (shortTransfer) {
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD Using Short Transfer (%d bytes) %s \n",
++ pReq->DataRemaining, IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX"));
++
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ /* wait for buffer ready */
++ WAIT_REGISTER32_CHANGE(pHcInstance,
++ &status,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY,
++ pHcInstance->BufferReadyWaitLimit);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ /* acknowledge it */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY);
++
++ /* transfer data */
++ HcdTransferTxData(pHcInstance, pReq);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++
++ /* fall through for completion */
++ } else {
++
++ /* wait for read buffer ready */
++ WAIT_REGISTER32_CHANGE_OR(pHcInstance,
++ &status,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY |
++ HOST_REG_NORMAL_INT_STATUS_ERROR,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY |
++ HOST_REG_NORMAL_INT_STATUS_ERROR,
++ pHcInstance->BufferReadyWaitLimit);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ errors = READ_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS);
++
++ if (errors != 0) {
++ break;
++ }
++ /* acknowledge it */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY);
++
++ /* unload buffer */
++ HcdTransferRxData(pHcInstance, pReq);
++ DBG_ASSERT(pReq->DataRemaining == 0);
++
++ /* fall through for completion */
++ }
++
++ /* wait for transfer complete */
++ WAIT_REGISTER32_CHANGE_OR(pHcInstance,
++ &status,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE |
++ HOST_REG_NORMAL_INT_STATUS_ERROR,
++ HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE |
++ HOST_REG_NORMAL_INT_STATUS_ERROR,
++ pHcInstance->TransferCompleteWaitLimit);
++
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++
++ /* get final error status */
++ errors = READ_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS);
++
++ break;
++ }
++
++ if (errors != 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Using Short Transfer Errors! :0x%X \n",errors));
++ status = TranslateSDError(pHcInstance, errors);
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ }
++
++ if (!SDIO_SUCCESS(status)) {
++ ResetCmdDatLine(pHcInstance);
++ }
++
++ return status;
++}
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdConfig - HCD configuration handler
++ Input: pHcd - HCD object
++ pConfig - configuration setting
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pConfig)
++{
++ PSDHCD_INSTANCE pHcInstance = (PSDHCD_INSTANCE)pHcd->pContext;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT16 command;
++ UINT32 temp;
++
++ if(pHcInstance->ShuttingDown) {
++ DBG_PRINT(STD_HOST_TRACE_REQUESTS, ("SDIO STD HOST HcdConfig returning canceled\n"));
++ return SDIO_STATUS_CANCELED;
++ }
++
++ command = GET_SDCONFIG_CMD(pConfig);
++
++ switch (command){
++ case SDCONFIG_GET_WP:
++ /* get write protect */
++ temp = READ_HOST_REG32(pHcInstance, HOST_REG_PRESENT_STATE);
++ /* if write enabled, set WP value to zero */
++ *((SDCONFIG_WP_VALUE *)pConfig->pData) =
++ (temp & HOST_REG_PRESENT_STATE_WRITE_ENABLED )? 0 : 1;
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ ClockStartStop(pHcInstance,CLOCK_ON);
++ /* should be at least 80 clocks at our lowest clock setting */
++ status = OSSleep(100);
++ ClockStartStop(pHcInstance,CLOCK_OFF);
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ if (GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->SlotIRQEnable) {
++ {
++ SDIO_IRQ_MODE_FLAGS irqModeFlags;
++ UINT8 blockGapControl;
++
++ irqModeFlags = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA,pConfig)->IRQDetectMode;
++ if (irqModeFlags & IRQ_DETECT_4_BIT) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST: 4 Bit IRQ mode \r\n"));
++ /* in 4 bit mode, the clock needs to be left on */
++ pHcInstance->KeepClockOn = TRUE;
++ blockGapControl = READ_HOST_REG8(pHcInstance,HOST_REG_BLOCK_GAP);
++ if (irqModeFlags & IRQ_DETECT_MULTI_BLK) {
++ blockGapControl |= HOST_REG_INT_DETECT_AT_BLOCK_GAP;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST: 4 Bit Multi-block IRQ detection enabled \r\n"));
++ } else {
++ // no interrupts between blocks
++ blockGapControl &= ~HOST_REG_INT_DETECT_AT_BLOCK_GAP;
++ }
++ WRITE_HOST_REG8(pHcInstance,HOST_REG_BLOCK_GAP,blockGapControl);
++ } else {
++ /* in 1 bit mode, the clock can be left off */
++ pHcInstance->KeepClockOn = FALSE;
++ }
++ }
++ /* enable detection */
++ EnableDisableSDIOIRQ(pHcInstance,TRUE,FALSE);
++ } else {
++ pHcInstance->KeepClockOn = FALSE;
++ EnableDisableSDIOIRQ(pHcInstance,FALSE,FALSE);
++ }
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ /* re-enable IRQ detection */
++ EnableDisableSDIOIRQ(pHcInstance,TRUE,FALSE);
++ break;
++ case SDCONFIG_BUS_MODE_CTRL:
++ SetBusMode(pHcInstance, (PSDCONFIG_BUS_MODE_DATA)(pConfig->pData));
++ break;
++ case SDCONFIG_POWER_CTRL:
++ DBG_PRINT(STD_HOST_TRACE_CONFIG, ("SDIO STD HOST PwrControl: En:%d, VCC:0x%X \n",
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask));
++ status = SetPowerLevel(pHcInstance,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerEnable,
++ GET_SDCONFIG_CMD_DATA(PSDCONFIG_POWER_CTRL_DATA,pConfig)->SlotPowerVoltageMask);
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ *((CT_DEBUG_LEVEL *)pConfig->pData) = DBG_GET_DEBUG_LEVEL();
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_SET_DEBUG_LEVEL(*((CT_DEBUG_LEVEL *)pConfig->pData));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST Local HCD: HcdConfig - bad command: 0x%X\n",
++ command));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return status;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetPowerLevel - Set power level of board
++ Input: pHcInstance - device context
++ On - if true turns power on, else off
++ Level - SLOT_VOLTAGE_MASK level
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS SetPowerLevel(PSDHCD_INSTANCE pHcInstance, BOOL On, SLOT_VOLTAGE_MASK Level)
++{
++ UINT8 out;
++ UINT32 capCurrent;
++
++ capCurrent = READ_HOST_REG32(pHcInstance, HOST_REG_MAX_CURRENT_CAPABILITIES);
++
++ switch (Level) {
++ case SLOT_POWER_3_3V:
++ out = HOST_REG_POWER_CONTROL_VOLT_3_3;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_SHIFT;
++ break;
++ case SLOT_POWER_3_0V:
++ out = HOST_REG_POWER_CONTROL_VOLT_3_0;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_SHIFT;
++ break;
++ case SLOT_POWER_1_8V:
++ out = HOST_REG_POWER_CONTROL_VOLT_1_8;
++ /* extract */
++ capCurrent = (capCurrent & HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_MASK) >>
++ HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_SHIFT;
++ break;
++ default:
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST SetPowerLevel - illegal power level %d\n",
++ (UINT)Level));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ if (capCurrent != 0) {
++ /* convert to mA and set max current */
++ pHcInstance->Hcd.MaxSlotCurrent = capCurrent * HOST_REG_MAX_CURRENT_CAPABILITIES_SCALER;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO STD HOST No Current Caps value for VMask:0x%X, using 200mA \n",
++ Level));
++ /* set a value */
++ pHcInstance->Hcd.MaxSlotCurrent = 200;
++ }
++
++ if (On) {
++ out |= HOST_REG_POWER_CONTROL_ON;
++ }
++
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_POWER_CONTROL, out);
++ return SDIO_STATUS_SUCCESS;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ SetPowerOn - Set power on or off for card
++ Input: pHcInstance - device context
++ On - if true turns power on, else off
++ Output:
++ Return:
++ Notes: leavse the level alone
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void SetPowerOn(PSDHCD_INSTANCE pHcInstance, BOOL On)
++{
++ /* non-synchronized read modify write */
++ UINT8 out = READ_HOST_REG8(pHcInstance, HOST_REG_POWER_CONTROL);
++ if (On) {
++ out |= HOST_REG_POWER_CONTROL_ON;
++ } else {
++ out &= ~HOST_REG_POWER_CONTROL_ON;
++ }
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_POWER_CONTROL, out);
++ return;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdInitialize - Initialize MMC controller
++ Input: pHcInstance - device context
++ Output:
++ Return:
++ Notes: I/O resources must be mapped before calling this function
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++SDIO_STATUS HcdInitialize(PSDHCD_INSTANCE pHcInstance)
++{
++ UINT32 caps;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ UINT32 clockValue;
++ PTEXT pSpecVer;
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO STD HOST HcdInitialize\n"));
++
++ if (0 == pHcInstance->BufferReadyWaitLimit) {
++ /* initialize all these to defaults */
++ pHcInstance->BufferReadyWaitLimit = 50000;
++ pHcInstance->TransferCompleteWaitLimit = 100000;
++ pHcInstance->PresentStateWaitLimit = 30000;
++ pHcInstance->ResetWaitLimit = 30000;
++ }
++
++ /* reset the device */
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize, resetting\n"));
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_SW_RESET, HOST_REG_SW_RESET_ALL);
++ /* wait for done */
++ while(READ_HOST_REG8(pHcInstance, HOST_REG_SW_RESET) & HOST_REG_SW_RESET_ALL)
++ ;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize, reset\n"));
++
++ /* turn off clock */
++ ClockStartStop(pHcInstance, CLOCK_OFF);
++ /* display version info */
++ switch(((READ_HOST_REG16(pHcInstance, HOST_REG_VERSION) >> HOST_REG_VERSION_VENDOR_VERSION_SHIFT) &
++ (UINT16)HOST_REG_VERSION_VENDOR_VERSION_MASK)) {
++ case 0:
++ pSpecVer = "SD Host Spec. 1.0";
++ break;
++ case 1:
++ pSpecVer = "SD Host Spec. 2.0";
++ break;
++ default:
++ pSpecVer = "SD Host Spec. **UNKNOWN**";
++ }
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize: Spec version: %s, Vendor version: %d\n",
++ pSpecVer,
++ (READ_HOST_REG16(pHcInstance, HOST_REG_VERSION) >> HOST_REG_VERSION_VENDOR_VERSION_SHIFT) &
++ HOST_REG_VERSION_VENDOR_VERSION_MASK));
++
++ /* get capabilities */
++ caps = READ_HOST_REG32(pHcInstance, HOST_REG_CAPABILITIES);
++ /* save these */
++ pHcInstance->Caps = caps;
++
++ switch((caps & HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_MASK) >> HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_SHIFT) {
++ case 0x00:
++ pHcInstance->Hcd.MaxBytesPerBlock = 512;
++ break;
++ case 0x01:
++ pHcInstance->Hcd.MaxBytesPerBlock = 1024;
++ break;
++ case 0x02:
++ pHcInstance->Hcd.MaxBytesPerBlock = 2048;
++ break;
++ case 0x03:
++ pHcInstance->Hcd.MaxBytesPerBlock = 512;
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST invalid buffer length\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ break;
++ }
++
++ clockValue = (caps & HOST_REG_CAPABILITIES_CLOCK_MASK) >> HOST_REG_CAPABILITIES_CLOCK_SHIFT;
++ if (clockValue != 0) {
++ /* convert to Hz */
++ pHcInstance->BaseClock = clockValue*1000*1000;
++ } else {
++ DBG_PRINT(SDDBG_WARN, ("SDIO STD HOST base clock is zero! (caps:0x%X) \n",caps));
++ /* fall through and see if a default was setup */
++ }
++ if (pHcInstance->BaseClock == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST invalid base clock setting\n"));
++ status = SDIO_STATUS_DEVICE_ERROR;
++ return status;
++ }
++
++ pHcInstance->Hcd.MaxClockRate = pHcInstance->BaseClock;
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST Using clock %dHz, max. block %d, high speed %s, %s, %s, %s\n",
++ pHcInstance->BaseClock, pHcInstance->Hcd.MaxBytesPerBlock,
++ (caps & HOST_REG_CAPABILITIES_HIGH_SPEED)? "supported" : "not supported",
++ (caps & HOST_REG_CAPABILITIES_DMA)? "Std. DMA" : "",
++ (caps & HOST_REG_CAPABILITIES_ADMA)? "Adv. DMA" : "",
++ (caps & HOST_REG_CAPABILITIES_MMC8)? "MMC8bit" : ""));
++
++ /* setup the supported voltages and max current */
++ pHcInstance->Hcd.SlotVoltageCaps = 0;
++ /* max current is dynamically set based on the desired voltage, see SetPowerLevel() */
++ pHcInstance->Hcd.MaxSlotCurrent = 0;
++
++ if (caps & HOST_REG_CAPABILITIES_VOLT_1_8) {
++ pHcInstance->Hcd.SlotVoltageCaps |= SLOT_POWER_1_8V;
++ pHcInstance->Hcd.SlotVoltagePreferred = SLOT_POWER_1_8V;
++ }
++ if(caps & HOST_REG_CAPABILITIES_VOLT_3_0) {
++ pHcInstance->Hcd.SlotVoltageCaps |= SLOT_POWER_3_0V;
++ pHcInstance->Hcd.SlotVoltagePreferred = SLOT_POWER_3_0V;
++ }
++ if(caps & HOST_REG_CAPABILITIES_VOLT_3_3) {
++ pHcInstance->Hcd.SlotVoltageCaps |= SLOT_POWER_3_3V;
++ pHcInstance->Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V;
++ }
++
++ /* check host capabilities and back off some features */
++ if (!(caps & HOST_REG_CAPABILITIES_HIGH_SPEED)) {
++ pHcInstance->Hcd.Attributes &= ~SDHCD_ATTRIB_SD_HIGH_SPEED;
++ }
++
++ if (!(caps & HOST_REG_CAPABILITIES_MMC8)) {
++ pHcInstance->Hcd.Attributes &= ~SDHCD_ATTRIB_BUS_MMC8BIT;
++ pHcInstance->Hcd.Attributes &= ~SDHCD_ATTRIB_MMC_HIGH_SPEED;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize: caps: 0x%X, SlotVoltageCaps: 0x%X\n",
++ (UINT)caps, (UINT)pHcInstance->Hcd.SlotVoltageCaps));
++
++ /* set the default timeout */
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_TIMEOUT_CONTROL, pHcInstance->TimeOut);
++
++ /* clear any existing errors and status */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_NORMAL_INT_STATUS, HOST_REG_NORMAL_INT_STATUS_CLEAR_ALL);
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* enable error interrupts */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERR_STATUS_ENABLE, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize - error enable 16bit: 0x%X\n", READ_HOST_REG16(pHcInstance, HOST_REG_ERR_STATUS_ENABLE)));
++
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_ERR_STATUS_ENABLE, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST HcdInitialize - error enable 32 bit: 0x%X\n", READ_HOST_REG32(pHcInstance, HOST_REG_ERR_STATUS_ENABLE)));
++
++ /* leave disabled for now */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE, (UINT16)0);
++
++ /* enable statuses */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_STATUS_ENABLE, HOST_REG_INT_STATUS_ALL);
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STD HOST HcdInitialize\n"));
++ return status;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdDeinitialize - deactivate controller
++ Input: pHcInstance - context
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void HcdDeinitialize(PSDHCD_INSTANCE pHcInstance)
++{
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO STD HOST HcdDeinitialize\n"));
++ pHcInstance->KeepClockOn = FALSE;
++ MaskIrq(pHcInstance, HOST_REG_INT_STATUS_ALL,FALSE);
++ pHcInstance->ShuttingDown = TRUE;
++ /* disable error interrupts */
++ /* clear any existing errors */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, HOST_REG_ERROR_INT_STATUS_ALL_ERR);
++ /* disable error interrupts */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE, 0);
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERR_STATUS_ENABLE, 0);
++ ClockStartStop(pHcInstance, CLOCK_OFF);
++ SetPowerOn(pHcInstance, FALSE);
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STD HOST HcdDeinitialize\n"));
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ HcdSDInterrupt - process controller interrupt
++ Input: pHcInstance - context
++ Output:
++ Return: TRUE if interrupt was handled
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++BOOL HcdSDInterrupt(PSDHCD_INSTANCE pHcInstance)
++{
++ UINT16 ints;
++ UINT16 errors;
++ UINT16 enables;
++ UINT16 statenables;
++ UINT16 errorenables;
++ PSDREQUEST pReq;
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++
++ DBG_PRINT(STD_HOST_TRACE_INT, ("+SDIO STD HOST HcdSDInterrupt Int handler \n"));
++
++ pReq = GET_CURRENT_REQUEST(&pHcInstance->Hcd);
++
++ while (1) {
++
++ ints = READ_HOST_REG16(pHcInstance, HOST_REG_NORMAL_INT_STATUS);
++ errors = READ_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS);
++
++ enables = READ_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE);
++ statenables = READ_HOST_REG16(pHcInstance, HOST_REG_INT_STATUS_ENABLE);
++ errorenables = READ_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE);
++ DBG_PRINT(STD_HOST_TRACE_INT,
++ ("SDIO STD HOST HcdSDInterrupt, ints: 0x%X errors: 0x%x, sigenables: 0x%X, statenable: 0x%X errorenables:0x%X\n",
++ (UINT)ints, (UINT)errors, (UINT)enables, (UINT)statenables, (UINT)errorenables));
++
++ /* only look at ints and error ints that are enabled */
++ ints &= enables;
++ errors &= errorenables;
++
++ if ((ints == 0) && (errors == 0)) {
++ break;
++ }
++ /* clear any error statuses */
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS, errors);
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE) {
++ DBG_PRINT(STD_HOST_TRACE_INT, ("SDIO STD HOST HcdSDInterrupt clearing possible data timeout errors: 0x%X \n",
++ errors));
++ errors &= ~HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR;
++ }
++
++ if (errors != 0) {
++ status = TranslateSDError(pHcInstance, errors);
++ break;
++ }
++
++ /* handle insert/removal */
++ if (ints &
++ (HOST_REG_INT_STATUS_CARD_INSERT_ENABLE | HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE)){
++ /* card was inserted or removed, clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_INT_STATUS_CARD_INSERT_ENABLE |
++ HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE);
++ /* mask card insert */
++ MaskIrqFromIsr(pHcInstance, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY);
++ QueueEventResponse(pHcInstance, WORK_ITEM_CARD_DETECT);
++ /* we don't need to cancel any requests, every SD transaction is protected
++ by a timeout, we just let the timeout occur */
++ /* continue and process interrupts */
++ }
++
++ /* deal with card interrupts */
++ if ((pHcInstance->CardInserted) &&
++ (ints & HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE)) {
++ DBG_PRINT(STD_HOST_TRACE_SDIO_INT, ("SDIO STD HOST: SDIO Card Interrupt Detected \n"));
++ /* SD card interrupt*/
++ /* disable the interrupt, the user must clear the interrupt */
++ EnableDisableSDIOIRQ(pHcInstance,FALSE,TRUE);
++ QueueEventResponse(pHcInstance, WORK_ITEM_SDIO_IRQ);
++ /* continue looking for other interrupt causes */
++ } else if (ints & HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE) {
++ /* disable bogus interrupt */
++ EnableDisableSDIOIRQ(pHcInstance,FALSE,TRUE);
++ }
++
++ if (NULL == pReq) {
++ break;
++ }
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE) {
++ /* clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE);
++ /* disable this interrupt */
++ MaskIrqFromIsr(pHcInstance, HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE);
++ status = ProcessCommandDone(pHcInstance,pReq,TRUE);
++ if (status != SDIO_STATUS_PENDING) {
++ break;
++ }
++ continue;
++ }
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_DMA_INT) {
++ /* we should NOT get these, the descriptors should not have the INTERRUPT bit set */
++ DBG_ASSERT(FALSE);
++ break;
++ }
++
++ /* check TX buffer ready */
++ if (ints & HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY) {
++ DBG_ASSERT(IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY);
++ if (pReq->DataRemaining > 0) {
++ /* transfer data */
++ if (!HcdTransferTxData(pHcInstance, pReq)) {
++ /* still more data to go... we'll get more write RDY interrupts */
++ continue;
++ }
++
++ /* fall through if this is the last block */
++ }
++ /* transfer is done */
++ /* disable write rdy */
++ MaskIrqFromIsr(pHcInstance,
++ HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE);
++ /* all data transfered, wait for transfer complete */
++ UnmaskIrqFromIsr(pHcInstance,
++ HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE);
++ continue;
++ }
++
++ /* check RX buffer ready */
++ if (ints & (HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY)) {
++ DBG_ASSERT(!IS_SDREQ_WRITE_DATA(pReq->Flags));
++ /* clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY );
++ /* unload fifo */
++ HcdTransferRxData(pHcInstance, pReq);
++ if (pReq->DataRemaining > 0) {
++ /* more to do.. */
++ } else {
++ /* turn off read ready interrupts */
++ MaskIrqFromIsr(pHcInstance,
++ HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE);
++ /* all data transfered, wait for transfer complete */
++ UnmaskIrqFromIsr(pHcInstance,
++ HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE);
++ }
++ continue;
++ }
++
++ if (ints & HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE) {
++ DBG_ASSERT(IS_SDREQ_DATA_TRANS(pReq->Flags));
++ DBG_PRINT(STD_HOST_TRACE_INT, ("SDIO STD HOST HcdSDInterrupt Transfer done \n"));
++
++ /* clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE);
++ /* if we get here without an error, we are done with the data
++ * data operation */
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ }
++
++ }
++
++ if (status != SDIO_STATUS_PENDING) {
++ /* turn off interrupts and clock */
++ MaskIrqFromIsr(pHcInstance,
++ ~(HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY |
++ HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE) );
++
++ if (errors) {
++ /* reset statemachine */
++ ResetCmdDatLine(pHcInstance);
++ }
++
++ if (!pHcInstance->KeepClockOn) {
++ ClockStartStop(pHcInstance, CLOCK_OFF);
++ }
++
++ if (pReq != NULL) {
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ TRACE_SIGNAL_DATA_WRITE(pHcInstance, FALSE);
++ } else {
++ TRACE_SIGNAL_DATA_READ(pHcInstance, FALSE);
++ }
++ }
++ /* set the status */
++ pReq->Status = status;
++
++ /* cleanup DMA if used */
++ if (pReq->Flags & SDREQ_FLAGS_DATA_DMA) {
++ HcdTransferDataDMAEnd(pHcInstance,pReq);
++ }
++
++ if (IS_SDREQ_DATA_TRANS(pReq->Flags)) {
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST - %s Data Transfer Complete with status:%d\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX":"RX",
++ pReq->Status));
++ }
++
++ if ((DBG_GET_DEBUG_LEVEL() >= STD_HOST_TRACE_DATA_DUMP) && SDIO_SUCCESS(status) &&
++ IS_SDREQ_DATA_TRANS(pReq->Flags) && !IS_SDREQ_WRITE_DATA(pReq->Flags) &&
++ !(pReq->Flags & SDREQ_FLAGS_DATA_DMA)) {
++ SDLIB_PrintBuffer(pReq->pDataBuffer,(pReq->BlockLen*pReq->BlockCount),"SDIO STD HOST - RX DataDump");
++ }
++ /* queue work item to notify bus driver of I/O completion */
++ QueueEventResponse(pHcInstance, WORK_ITEM_IO_COMPLETE);
++ }
++ }
++
++ DBG_PRINT(STD_HOST_TRACE_INT, ("-SDIO STD HOST HcdSDInterrupt Int handler \n"));
++ return TRUE;
++}
++
++
++/* card detect callback from a deferred (non-ISR) context */
++void ProcessDeferredCardDetect(PSDHCD_INSTANCE pHcInstance)
++{
++
++ HCD_EVENT event;
++ volatile UINT32 temp;
++
++ event = EVENT_HCD_NOP;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO STD HOST Card Detect Processing \n"));
++ if (pHcInstance->ShuttingDown) {
++ return;
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD Host Card Detect Delaying to debounce card... \n"));
++
++ OSSleep(SD_SLOT_DEBOUNCE_MS);
++
++ /* wait for stable */
++ while(!(temp = READ_HOST_REG32(pHcInstance, HOST_REG_PRESENT_STATE))&
++ HOST_REG_PRESENT_STATE_CARD_STATE_STABLE) {
++ ;
++ }
++
++ /* look for removal */
++ if (!(temp & HOST_REG_PRESENT_STATE_CARD_INSERTED)) {
++ pHcInstance->CardInserted = FALSE;
++ pHcInstance->KeepClockOn = FALSE;
++ /* turn the power off */
++ SetPowerOn(pHcInstance, FALSE);
++ if (pHcInstance->StartUpCardCheckDone) {
++ DBG_PRINT(STD_HOST_TRACE_CARD_INSERT, ("SDIO STD HOST Card Detect REMOVE\n"));
++ /* card not present */
++ event = EVENT_HCD_DETACH;
++ }
++ } else {
++ /* card present */
++ event = EVENT_HCD_ATTACH;
++ pHcInstance->CardInserted = TRUE;
++ DBG_PRINT(STD_HOST_TRACE_CARD_INSERT, ("SDIO STD HOST Card Detect INSERT\n"));
++ }
++
++ if (!pHcInstance->StartUpCardCheckDone) {
++ /* startup check is now done */
++ pHcInstance->StartUpCardCheckDone = TRUE;
++ }
++ /* clear interrupt */
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_NORMAL_INT_STATUS,
++ HOST_REG_INT_STATUS_CARD_INSERT_ENABLE |
++ HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE);
++ /* re-enable insertion/removal */
++ UnmaskIrq(pHcInstance, HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY,FALSE);
++
++ if (event != EVENT_HCD_NOP) {
++ SDIO_HandleHcdEvent(&pHcInstance->Hcd, event);
++ }
++
++ if (!pHcInstance->CardInserted && !pHcInstance->RequestCompleteQueued) {
++ /* check for a stuck request */
++ PSDREQUEST pReq = GET_CURRENT_REQUEST(&pHcInstance->Hcd);
++ if (pReq != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST , Stuck Request! 0x%X\n",(UINT)pReq));
++ DumpStdHcdRegisters(pHcInstance);
++ DumpCurrentRequestInfo(pHcInstance);
++ }
++ }
++
++ DBG_PRINT(STD_HOST_TRACE_CARD_INSERT, ("- SDIO STD HOST Card Detect Processing \n"));
++}
++
++
++void DumpStdHcdRegisters(PSDHCD_INSTANCE pHcInstance)
++{
++ DBG_PRINT(SDDBG_TRACE, ("---------------- SDIO STD HOST, Register Dump ----------------- \n"));
++
++ DBG_PRINT(SDDBG_TRACE,(" NORMAL INT STATUS : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_NORMAL_INT_STATUS)));
++ DBG_PRINT(SDDBG_TRACE,(" ERROR INT STATUS : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_ERROR_INT_STATUS)));
++ DBG_PRINT(SDDBG_TRACE,(" INT SIGNAL ENABLE : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE)));
++ DBG_PRINT(SDDBG_TRACE,(" ERROR SIGNAL ENABLES : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_INT_ERR_SIGNAL_ENABLE)));
++ DBG_PRINT(SDDBG_TRACE,(" STATUS ENABLES : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_INT_STATUS_ENABLE)));
++ DBG_PRINT(SDDBG_TRACE,(" ERROR STATUS ENABLES : 0x%X \n",
++ READ_HOST_REG16(pHcInstance, HOST_REG_ERR_STATUS_ENABLE)));
++
++ DBG_PRINT(SDDBG_TRACE,(" HOST PRESENT_STATE : 0x%X \n",
++ READ_HOST_REG32(pHcInstance, HOST_REG_PRESENT_STATE)));
++
++
++ DBG_PRINT(SDDBG_TRACE, ("------------------------------------------------------------------"));
++}
++
++
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd.h 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,330 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_std_hcd.h
++
++ at abstract: OS Independent standard host header file
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_STD_HCD_H___
++#define __SDIO_STD_HCD_H___
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++#include "sdio_std_hcd_linux.h"
++
++enum STD_HOST_TRACE_ENUM {
++ STD_HOST_TRACE_CARD_INSERT = (SDDBG_TRACE + 1),
++ STD_HOST_TRACE_DATA = (SDDBG_TRACE + 2),
++ STD_HOST_TRACE_REQUESTS,
++ STD_HOST_TRACE_DATA_DUMP,
++ STD_HOST_TRACE_CONFIG,
++ STD_HOST_TRACE_INT,
++ STD_HOST_TRACE_CLOCK,
++ STD_HOST_TRACE_SDIO_INT,
++ STD_HOST_TRACE_LAST
++};
++
++ /* Host Controller register definitions */
++#define HOST_REG_SYSTEM_ADDRESS 0x00
++
++#define HOST_REG_BLOCK_SIZE 0x04
++#define HOST_REG_BLOCK_SIZE_LEN_MASK 0x0FFF
++#define HOST_REG_BLOCK_SIZE_DMA_MASK 0x7000
++#define HOST_REG_BLOCK_SIZE_DMA_SHIFT 12
++#define HOST_REG_BLOCK_SIZE_DMA_512K_BOUNDARY (7 << HOST_REG_BLOCK_SIZE_DMA_SHIFT)
++
++#define HOST_REG_BLOCK_COUNT 0x06
++
++#define HOST_REG_ARGUMENT 0x08
++
++#define HOST_REG_TRANSFER_MODE 0x0C
++#define HOST_REG_TRANSFER_MODE_MULTI_BLOCK (1 << 5)
++#define HOST_REG_TRANSFER_MODE_READ (1 << 4)
++#define HOST_REG_TRANSFER_MODE_AUTOCMD12 (1 << 2)
++#define HOST_REG_TRANSFER_MODE_BLOCKCOUNT_ENABLE (1 << 1)
++#define HOST_REG_TRANSFER_MODE_DMA_ENABLE (1 << 0)
++
++#define HOST_REG_COMMAND_REGISTER 0x0E
++#define HOST_REG_COMMAND_REGISTER_CMD_SHIFT 8
++#define HOST_REG_COMMAND_REGISTER_DATA_PRESENT (1 << 5)
++#define HOST_REG_COMMAND_REGISTER_CMD_INDEX_CHECK_ENABLE (1 << 4)
++#define HOST_REG_COMMAND_REGISTER_CRC_CHECK_ENABLE (1 << 3)
++
++
++#define HOST_REG_RESPONSE 0x10 /* 32-bit reguisters 0x10 through 0x1C */
++
++#define HOST_REG_BUFFER_DATA_PORT 0x20
++
++#define HOST_REG_PRESENT_STATE 0x24
++#define HOST_REG_PRESENT_STATE_WRITE_ENABLED (1 << 19)
++#define HOST_REG_PRESENT_STATE_CARD_DETECT (1 << 18)
++#define HOST_REG_PRESENT_STATE_CARD_STATE_STABLE (1 << 17)
++#define HOST_REG_PRESENT_STATE_CARD_INSERTED (1 << 16)
++#define HOST_REG_PRESENT_STATE_BUFFER_READ_ENABLE (1 << 11)
++#define HOST_REG_PRESENT_STATE_BUFFER_WRITE_ENABLE (1 << 10)
++#define HOST_REG_PRESENT_STATE_BUFFER_READ_TRANSFER_ACTIVE (1 << 9)
++#define HOST_REG_PRESENT_STATE_BUFFER_WRITE_TRANSFER_ACTIVE (1 << 8)
++#define HOST_REG_PRESENT_STATE_BUFFER_DAT_LINE_ACTIVE (1 << 2)
++#define HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_DAT (1 << 1)
++#define HOST_REG_PRESENT_STATE_BUFFER_COMMAND_INHIBIT_CMD (1 << 0)
++
++
++#define HOST_REG_CONTROL 0x28
++#define HOST_REG_CONTROL_LED_ON (1 << 0)
++#define HOST_REG_CONTROL_1BIT_WIDTH 0x00
++#define HOST_REG_CONTROL_4BIT_WIDTH (1 << 1)
++#define HOST_REG_CONTROL_HI_SPEED (1 << 2)
++#define HOST_REG_CONTROL_DMA_NONE (0 << 3)
++#define HOST_REG_CONTROL_DMA_32BIT (1 << 3)
++#define HOST_REG_CONTROL_DMA_64BIT (2 << 3)
++#define HOST_REG_CONTROL_DMA_MASK (3 << 3)
++#define HOST_REG_CONTROL_EXTENDED_DATA (1 << 5)
++#define HOST_REG_CONTROL_CARD_DETECT_TEST (1 << 6)
++#define HOST_REG_CONTROL_CARD_DETECT_SELECT (1 << 7)
++#define HOST_REG_CONTROL_BUSWIDTH_BITS \
++ (HOST_REG_CONTROL_1BIT_WIDTH | HOST_REG_CONTROL_4BIT_WIDTH | HOST_REG_CONTROL_EXTENDED_DATA)
++
++
++#define HOST_REG_POWER_CONTROL 0x29
++#define HOST_REG_POWER_CONTROL_ON (1 << 0)
++#define HOST_REG_POWER_CONTROL_VOLT_3_3 (7 << 1)
++#define HOST_REG_POWER_CONTROL_VOLT_3_0 (6 << 1)
++#define HOST_REG_POWER_CONTROL_VOLT_1_8 (5 << 1)
++
++#define HOST_REG_BLOCK_GAP 0x2A
++#define HOST_REG_INT_DETECT_AT_BLOCK_GAP (1 << 3)
++
++#define HOST_REG_CLOCK_CONTROL 0x2C
++#define HOST_REG_CLOCK_CONTROL_CLOCK_ENABLE (1 << 0)
++#define HOST_REG_CLOCK_CONTROL_CLOCK_STABLE (1 << 1)
++#define HOST_REG_CLOCK_CONTROL_SD_ENABLE (1 << 2)
++
++#define HOST_REG_TIMEOUT_CONTROL 0x2E
++#define HOST_REG_TIMEOUT_CONTROL_DEFAULT 0x0C
++
++#define HOST_REG_SW_RESET 0x2F
++#define HOST_REG_SW_RESET_ALL (1 << 0)
++#define HOST_REG_SW_RST_CMD_LINE (1 << 1)
++#define HOST_REG_SW_RST_DAT_LINE (1 << 2)
++
++#define HOST_REG_NORMAL_INT_STATUS 0x30
++#define HOST_REG_NORMAL_INT_STATUS_ERROR (1 << 15)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_INTERRUPT (1 << 8)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_REMOVAL (1 << 7)
++#define HOST_REG_NORMAL_INT_STATUS_CARD_INSERT (1 << 6)
++#define HOST_REG_NORMAL_INT_STATUS_BUFFER_READ_RDY (1 << 5)
++#define HOST_REG_NORMAL_INT_STATUS_BUFFER_WRITE_RDY (1 << 4)
++#define HOST_REG_NORMAL_INT_STATUS_DMA_INT (1 << 3)
++#define HOST_REG_NORMAL_INT_STATUS_BLOCK_GAP (1 << 2)
++#define HOST_REG_NORMAL_INT_STATUS_TRANSFER_COMPLETE (1 << 1)
++#define HOST_REG_NORMAL_INT_STATUS_CMD_COMPLETE (1 << 0)
++#define HOST_REG_NORMAL_INT_STATUS_CLEAR_ALL 0xFFFF
++
++#define HOST_REG_ERROR_INT_STATUS 0x32
++#define HOST_REG_ERROR_INT_STATUS_VENDOR_MASK 0xE000
++#define HOST_REG_ERROR_INT_STATUS_VENDOR_SHIFT 13
++#define HOST_REG_ERROR_INT_STATUS_SDMAERR (1 << 12)
++#define HOST_REG_ERROR_INT_STATUS_ADMAERR (1 << 9)
++#define HOST_REG_ERROR_INT_STATUS_AUTOCMD12ERR (1 << 8)
++#define HOST_REG_ERROR_INT_STATUS_CURRENTLIMITERR (1 << 7)
++#define HOST_REG_ERROR_INT_STATUS_DATAENDBITERR (1 << 6)
++#define HOST_REG_ERROR_INT_STATUS_DATACRCERR (1 << 5)
++#define HOST_REG_ERROR_INT_STATUS_DATATIMEOUTERR (1 << 4)
++#define HOST_REG_ERROR_INT_STATUS_CMDINDEXERR (1 << 3)
++#define HOST_REG_ERROR_INT_STATUS_CMDENDBITERR (1 << 2)
++#define HOST_REG_ERROR_INT_STATUS_CRCERR (1 << 1)
++#define HOST_REG_ERROR_INT_STATUS_CMDTIMEOUTERR (1 << 0)
++#define HOST_REG_ERROR_INT_STATUS_ALL_ERR 0x7FF
++
++#define HOST_REG_INT_STATUS_ENABLE 0x34
++#define HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE (1 << 8)
++#define HOST_REG_INT_STATUS_CARD_REMOVAL_ENABLE (1 << 7)
++#define HOST_REG_INT_STATUS_CARD_INSERT_ENABLE (1 << 6)
++#define HOST_REG_INT_STATUS_BUFFER_READ_RDY_ENABLE (1 << 5)
++#define HOST_REG_INT_STATUS_BUFFER_WRITE_RDY_ENABLE (1 << 4)
++#define HOST_REG_INT_STATUS_DMA_ENABLE (1 << 3)
++#define HOST_REG_INT_STATUS_BLOCK_GAP_ENABLE (1 << 2)
++#define HOST_REG_INT_STATUS_TRANSFER_COMPLETE_ENABLE (1 << 1)
++#define HOST_REG_INT_STATUS_CMD_COMPLETE_ENABLE (1 << 0)
++#define HOST_REG_INT_STATUS_ALL 0x00FB
++#define HOST_REG_INT_STATUS_ALLOW_INSERT_REMOVE_ONLY 0x00C0
++
++#define HOST_REG_ERR_STATUS_ENABLE 0x36
++/* same bits as HOST_REG_ERROR_INT_STATUS */
++
++#define HOST_REG_INT_SIGNAL_ENABLE 0x38
++/* same bits as HOST_REG_INT_STATUS_ENABLE */
++
++#define HOST_REG_INT_ERR_SIGNAL_ENABLE 0x3A
++/* same bits as HOST_REG_ERR_STATUS_ENABLE */
++
++#define HOST_REG_CAPABILITIES 0x40
++#define HOST_REG_CAPABILITIES_VOLT_1_8 (1 << 26)
++#define HOST_REG_CAPABILITIES_VOLT_3_0 (1 << 25)
++#define HOST_REG_CAPABILITIES_VOLT_3_3 (1 << 24)
++#define HOST_REG_CAPABILITIES_SUSPEND_RESUME (1 << 23)
++#define HOST_REG_CAPABILITIES_DMA (1 << 22)
++#define HOST_REG_CAPABILITIES_HIGH_SPEED (1 << 21)
++#define HOST_REG_CAPABILITIES_ADMA (1 << 20)
++#define HOST_REG_CAPABILITIES_64 (1 << 19)
++#define HOST_REG_CAPABILITIES_MMC8 (1 << 18)
++
++#define HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_MASK 0x30000
++#define HOST_REG_CAPABILITIES_MAX_BLOCK_LEN_SHIFT 16
++#define HOST_REG_CAPABILITIES_CLOCK_MASK 0x3F00
++#define HOST_REG_CAPABILITIES_CLOCK_SHIFT 8
++#define HOST_REG_CAPABILITIES_TIMEOUT_CLOCK_UNITS (1 << 7)
++#define HOST_REG_CAPABILITIES_TIMEOUT_FREQ_MASK 0x3F
++#define HOST_REG_CAPABILITIES_TIMEOUT_FREQ_SHIFT 0
++
++#define HOST_REG_MAX_CURRENT_CAPABILITIES 0x48
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_MASK 0xFF0000
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_1_8_SHIFT 16
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_MASK 0x00FF00
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_0_SHIFT 8
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_MASK 0x0000FF
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_3_3_SHIFT 0
++#define HOST_REG_MAX_CURRENT_CAPABILITIES_SCALER 4
++
++#define HOST_REG_ADMA_ERR_STATUS 0x54
++#define HOST_REG_ADMA_ERR_LEN_MISMATCH (1 << 2)
++#define HOST_REG_ADMA_STATE_MASK 0x03
++#define HOST_REG_ADMA_STATE_SHIFT 0
++#define HOST_REG_ADMA_STATE_STOP 0x0
++#define HOST_REG_ADMA_STATE_FDS 0x1
++#define HOST_REG_ADMA_STATE_CADR 0x2
++#define HOST_REG_ADMA_STATE_TFR 0x3
++
++#define HOST_REG_ADMA_ADDRESS 0x58
++
++#define HOST_REG_SLOT_INT_STATUS 0xFC
++#define HOST_REG_SLOT_INT_MASK 0xFF
++#define HOST_REG_MAX_INT_SLOTS 8
++
++#define HOST_REG_VERSION 0xFE
++#define HOST_REG_VERSION_SPEC_VERSION_MASK 0xFF
++#define HOST_REG_VERSION_VENDOR_VERSION_MASK 0xFF00
++#define HOST_REG_VERSION_VENDOR_VERSION_SHIFT 8
++
++#define SDIO_BD_MAX_SLOTS 24
++#define SDIO_SD_MAX_BLOCKS ((UINT)0xFFFF)
++
++#define SD_DEFAULT_RESPONSE_BYTES 6
++#define SD_R2_RESPONSE_BYTES 16
++#define STD_HOST_SHORT_TRANSFER_THRESHOLD 32
++#define SD_CLOCK_MAX_ENTRIES 9
++
++typedef struct _SD_CLOCK_TBL_ENTRY {
++ INT ClockRateDivisor; /* divisor */
++ UINT16 RegisterValue; /* register value for clock divisor */
++}SD_CLOCK_TBL_ENTRY;
++
++ /* standard host controller instance */
++typedef struct _SDHCD_INSTANCE {
++ SDLIST List; /* list */
++ SDHCD Hcd; /* HCD structure for registration */
++ SDDMA_DESCRIPTION DmaDescription; /* dma description for this HCD if used*/
++ UINT32 Caps; /* host controller capabilities */
++#define SDHC_HW_INIT 0x01
++#define SDHC_REGISTERED 0x02
++ UINT8 InitStateMask; /* init state for hardware independent layer */
++ BOOL CardInserted; /* card inserted flag */
++ BOOL Cancel; /* cancel flag */
++ BOOL ShuttingDown; /* indicates shut down of HCD */
++ BOOL StartUpCardCheckDone;
++ UINT32 BaseClock; /* base clock in hz */
++ UINT32 TimeOut; /* timeout setting */
++ UINT32 ClockSpinLimit; /* clock limit for command spin loops */
++ BOOL KeepClockOn;
++ UINT32 BufferReadyWaitLimit;
++ UINT32 TransferCompleteWaitLimit;
++ UINT32 PresentStateWaitLimit;
++ UINT32 ResetWaitLimit;
++ BOOL RequestCompleteQueued;
++ PVOID pRegs; /* a more direct pointer to the registers */
++ SDHCD_OS_SPECIFIC OsSpecific;
++}SDHCD_INSTANCE, *PSDHCD_INSTANCE;
++
++
++/* scatter-gather tables, as we use it in 32-bit mode */
++struct _SDHCD_SGDMA_DESCRIPTOR {
++ UINT32 Length;
++ UINT32 Address;
++}CT_PACK_STRUCT;
++
++
++typedef struct _SDHCD_SGDMA_DESCRIPTOR SDHCD_SGDMA_DESCRIPTOR;
++typedef struct _SDHCD_SGDMA_DESCRIPTOR *PSDHCD_SGDMA_DESCRIPTOR;
++
++#define SDDMA_VALID 0x1
++#define SDDMA_END 0x2
++#define SDDMA_INT 0x4
++#define SDDMA_LENGTH 0x10
++#define SDDMA_TRANSFER 0x20
++#define SDDMA_DESCRIP_LINK 0x30
++
++#define SET_DMA_LENGTH(d, l)\
++ ((d)->Length = ((l) << 12) | SDDMA_LENGTH | SDDMA_VALID)
++#define SET_DMA_ADDRESS(d, l)\
++ ((d)->Address = ((l) & 0xFFFFF000) | SDDMA_TRANSFER | SDDMA_VALID)
++#define SET_DMA_END_OF_TRANSFER(d)\
++ ((d)->Address |= SDDMA_END);
++
++/* prototypes */
++SDIO_STATUS HcdRequest(PSDHCD pHcd);
++SDIO_STATUS HcdConfig(PSDHCD pHcd, PSDCONFIG pReq);
++SDIO_STATUS HcdInitialize(PSDHCD_INSTANCE pHcInstance);
++void HcdDeinitialize(PSDHCD_INSTANCE pHcInstance);
++BOOL HcdSDInterrupt(PSDHCD_INSTANCE pHcInstance);
++void ProcessDeferredCardDetect(PSDHCD_INSTANCE pHcInstance);
++SDIO_STATUS QueueEventResponse(PSDHCD_INSTANCE pHcInstance, INT WorkItemID);
++BOOL HcdTransferTxData(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq);
++void HcdTransferRxData(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq);
++void SetPowerOn(PSDHCD_INSTANCE pHcInstance, BOOL On);
++UINT16 MaskIrq(PSDHCD_INSTANCE pHcInstance, UINT32 Mask, BOOL FromIsr);
++UINT16 UnmaskIrq(PSDHCD_INSTANCE pHcInstance, UINT32 Mask, BOOL FromIsr);
++#define MaskIrqFromIsr(p,m) MaskIrq((p),(m),TRUE)
++#define UnmaskIrqFromIsr(p,m) UnmaskIrq((p),(m),TRUE)
++
++void EnableDisableSDIOIRQ(PSDHCD_INSTANCE pHcInstance, BOOL Enable, BOOL FromIsr);
++SDIO_STATUS SetUpHCDDMA(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq);
++void HcdTransferDataDMAEnd(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq);
++void DumpStdHcdRegisters(PSDHCD_INSTANCE pHcInstance);
++void DumpDMADescriptorsInfo(PSDHCD_INSTANCE pHcInstance);
++void DumpCurrentRequestInfo(PSDHCD_INSTANCE pHcInstance);
++
++#endif
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_linux.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_linux.h 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,132 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_std_hcd_linux.h
++
++ at abstract: include file for linux dependent code
++
++ at notice: Copyright (c), 2005 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef __SDIO_STD_HCD_LINUX_H___
++#define __SDIO_STD_HCD_LINUX_H___
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <asm/irq.h>
++
++#define SDHCD_MAX_DEVICE_NAME 64
++
++/* Advance DMA parameters */
++#define SDHCD_MAX_ADMA_DESCRIPTOR 32
++#define SDHCD_ADMA_DESCRIPTOR_SIZE (SDHCD_MAX_ADMA_DESCRIPTOR * sizeof(SDHCD_SGDMA_DESCRIPTOR))
++#define SDHCD_MAX_ADMA_LENGTH 0x8000 /* up to 32KB per descriptor */
++#define SDHCD_ADMA_ADDRESS_MASK 0xFFFFE000 /* 4KB boundaries */
++#define SDHCD_ADMA_ALIGNMENT 0xFFF /* illegal alignment bits*/
++#define SDHCD_ADMA_LENGTH_ALIGNMENT 0x0 /* any length up to the max */
++
++/* simple DMA */
++#define SDHCD_MAX_SDMA_DESCRIPTOR 1
++#define SDHCD_MAX_SDMA_LENGTH 0x80000 /* up to 512KB for a single descriptor*/
++#define SDHCD_SDMA_ADDRESS_MASK 0xFFFFFFFF /* any 32 bit address */
++#define SDHCD_SDMA_ALIGNMENT 0x0 /* any 32 bit address */
++#define SDHCD_SDMA_LENGTH_ALIGNMENT 0x0 /* any length up to the max */
++
++#define HCD_COMMAND_MIN_POLLING_CLOCK 5000000
++
++/* debounce delay for slot */
++#define SD_SLOT_DEBOUNCE_MS 1000
++
++/* mapped memory address */
++typedef struct _SDHCD_MEMORY {
++ ULONG Raw; /* start of address range */
++ ULONG Length; /* length of range */
++ PVOID pMapped; /* the mapped address */
++}SDHCD_MEMORY, *PSDHCD_MEMORY;
++
++typedef struct _SDHCD_OS_SPECIFIC {
++ SDHCD_MEMORY Address; /* memory address of this device */
++ spinlock_t RegAccessLock; /* use to protect registers when needed */
++ struct work_struct iocomplete_work; /* work item definitions */
++ struct work_struct carddetect_work; /* work item definintions */
++ struct work_struct sdioirq_work; /* work item definintions */
++ spinlock_t Lock; /* general purpose lock against the ISR */
++ DMA_ADDRESS hDmaBuffer; /* handle for data buffer */
++ PUINT8 pDmaBuffer; /* virtual address of DMA command buffer */
++ PSDDMA_DESCRIPTOR pDmaList; /* in use scatter-gather list */
++ UINT SGcount; /* count of in-use scatter gather list */
++ UINT SlotNumber; /* the STD-host defined slot number assigned to this instance */
++/* everything below this line is used by the implementation that uses this STD core */
++ UINT16 InitMask; /* implementation specific portion init mask */
++ UINT32 ImpSpecific0; /* implementation specific storage */
++ UINT32 ImpSpecific1; /* implementation specific storage */
++} SDHCD_OS_SPECIFIC, *PSDHCD_OS_SPECIFIC;
++
++
++#define WORK_ITEM_IO_COMPLETE 0
++#define WORK_ITEM_CARD_DETECT 1
++#define WORK_ITEM_SDIO_IRQ 2
++
++#define READ_HOST_REG32(pHcInstance, OFFSET) \
++ _READ_DWORD_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET))
++#define WRITE_HOST_REG32(pHcInstance, OFFSET, VALUE) \
++ _WRITE_DWORD_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET),(VALUE))
++#define READ_HOST_REG16(pHcInstance, OFFSET) \
++ _READ_WORD_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET))
++#define WRITE_HOST_REG16(pHcInstance, OFFSET, VALUE) \
++ _WRITE_WORD_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET),(VALUE))
++#define READ_HOST_REG8(pHcInstance, OFFSET) \
++ _READ_BYTE_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET))
++#define WRITE_HOST_REG8(pHcInstance, OFFSET, VALUE) \
++ _WRITE_BYTE_REG((((UINT32)((pHcInstance)->pRegs))) + (OFFSET),(VALUE))
++
++#define TRACE_SIGNAL_DATA_WRITE(pHcInstance, on)
++#define TRACE_SIGNAL_DATA_READ(pHcInstance, on)
++#define TRACE_SIGNAL_DATA_ISR(pHcInstance, on)
++#define TRACE_SIGNAL_DATA_IOCOMP(pHcInstance, on)
++#define TRACE_SIGNAL_DATA_TIMEOUT(pHcInstance, on)
++
++
++
++#define IS_HCD_ADMA(pHc) ((pHc)->Hcd.pDmaDescription != NULL) && \
++ ((pHc)->Hcd.pDmaDescription->Flags & SDDMA_DESCRIPTION_FLAG_SGDMA)
++
++#define IS_HCD_SDMA(pHc) (((pHc)->Hcd.pDmaDescription != NULL) && \
++ (((pHc)->Hcd.pDmaDescription->Flags & \
++ (SDDMA_DESCRIPTION_FLAG_SGDMA | SDDMA_DESCRIPTION_FLAG_DMA)) == \
++ SDDMA_DESCRIPTION_FLAG_DMA))
++
++#endif
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_linux_lib.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_linux_lib.h 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,79 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_std_hcd_linux_lib.h
++
++ at abstract: include file for linux std host core APIs
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++#ifndef SDIO_STD_HCD_LINUX_LIB_H_
++#define SDIO_STD_HCD_LINUX_LIB_H_
++
++typedef struct _SDHCD_CORE_CONTEXT {
++ SDLIST List;
++ PVOID pBusContext; /* bus context this one belongs to */
++ SDLIST SlotList; /* the list of current slots handled by this driver */
++ spinlock_t SlotListLock; /* protection for the slot List */
++ UINT SlotCount; /* number of slots currently installed */
++ /* everything below this line is reserved for the user of this library */
++ UINT32 CoreReserved1;
++ UINT32 CoreReserved2;
++}SDHCD_CORE_CONTEXT, *PSDHCD_CORE_CONTEXT;
++
++void InitStdHostLib(void);
++void DeinitStdHostLib(void);
++PSDHCD_CORE_CONTEXT CreateStdHostCore(PVOID pBusContext);
++void DeleteStdHostCore(PSDHCD_CORE_CONTEXT pStdCore);
++PSDHCD_CORE_CONTEXT GetStdHostCore(PVOID pBusContext);
++
++INT GetCurrentHcdInstanceCount(PSDHCD_CORE_CONTEXT pStdCore);
++PSDHCD_INSTANCE CreateStdHcdInstance(POS_DEVICE pOSDevice,
++ UINT SlotNumber,
++ PTEXT pName);
++void DeleteStdHcdInstance(PSDHCD_INSTANCE pHcInstance);
++#define START_HCD_FLAGS_FORCE_NO_DMA 0x01 /* don't use DMA even though capabilities indicate it can */
++#define START_HCD_FLAGS_FORCE_SDMA 0x02 /* force SDMA even though the capabilities show advance DMA support */
++
++typedef SDIO_STATUS (*PPLAT_OVERRIDE_CALLBACK)(PSDHCD_INSTANCE);
++SDIO_STATUS AddStdHcdInstance(PSDHCD_CORE_CONTEXT pStdCore,
++ PSDHCD_INSTANCE pHcInstance,
++ UINT Flags,
++ PPLAT_OVERRIDE_CALLBACK pCallBack,
++ SDDMA_DESCRIPTION *pSDMADescrip,
++ SDDMA_DESCRIPTION *pADMADescrip);
++SDIO_STATUS StartStdHostCore(PSDHCD_CORE_CONTEXT pStdCore);
++PSDHCD_INSTANCE RemoveStdHcdInstance(PSDHCD_CORE_CONTEXT pStdCore);
++BOOL HandleSharedStdHostInterrupt(PSDHCD_CORE_CONTEXT pStdCore);
++#endif /*SDIO_STD_HCD_LINUX_LIB_H_*/
+Index: linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_os.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22.5/drivers/sdio/hcd/stdhost/sdio_std_hcd_os.c 2007-11-06 19:38:13.000000000 +0100
+@@ -0,0 +1,826 @@
++/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ at file: sdio_std_hcd_os.c
++
++ at abstract: Generic Linux implementation for the Standard SDIO Host Controller Driver
++
++#notes:
++
++ at notice: Copyright (c), 2006 Atheros Communications, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation;
++ *
++ * Software distributed under the License is distributed on an "AS
++ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
++ * implied. See the License for the specific language governing
++ * rights and limitations under the License.
++ *
++ * Portions o this code were developed with information supplied from the
++ * SD Card Association Simplified Specifications. The following conditions and disclaimers may apply:
++ *
++ * The following conditions apply to the release of the SD simplified specification (“Simplified
++ * Specification”) by the SD Card Association. The Simplified Specification is a subset of the complete
++ * SD Specification which is owned by the SD Card Association. This Simplified Specification is provided
++ * on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified
++ * Specification may require a license from the SD Card Association or other third parties.
++ * Disclaimers:
++ * The information contained in the Simplified Specification is presented only as a standard
++ * specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any
++ * representations or warranties of any kind. No responsibility is assumed by the SD Card Association for
++ * any damages, any infringements of patents or other right of the SD Card Association or any third
++ * parties, which may result from its use. No license is granted by implication, estoppel or otherwise
++ * under any patent or other rights of the SD Card Association or any third party. Nothing herein shall
++ * be construed as an obligation by the SD Card Association to disclose or distribute any technical
++ * information, know-how or other confidential information to any third party.
++ *
++ *
++ * The initial developers of the original code are Seung Yi and Paul Lever
++ *
++ * sdio at atheros.com
++ *
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++
++/* debug level for this module*/
++#define DBG_DECLARE 4;
++#include <linux/sdio/ctsystem.h>
++#include "sdio_std_hcd.h"
++#include "sdio_std_hcd_linux_lib.h"
++#include <linux/dma-mapping.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++static void hcd_iocomplete_wqueue_handler(void *context);
++static void hcd_carddetect_wqueue_handler(void *context);
++static void hcd_sdioirq_wqueue_handler(void *context);
++static SDIO_STATUS SetupDmaBuffers(PSDHCD_INSTANCE pHcInstance);
++static void DeinitializeStdHcdInstance(PSDHCD_INSTANCE pHcInstance);
++
++/* debug print parameter */
++module_param(debuglevel, int, 0644);
++MODULE_PARM_DESC(debuglevel, "debuglevel 0-7, controls debug prints");
++
++ /* defaults for all std hosts, various attributes will be cleared based
++ * on values from the capabilities register */
++#define DEFAULT_ATTRIBUTES (SDHCD_ATTRIB_BUS_1BIT | \
++ SDHCD_ATTRIB_BUS_4BIT | \
++ SDHCD_ATTRIB_MULTI_BLK_IRQ | \
++ SDHCD_ATTRIB_AUTO_CMD12 | \
++ SDHCD_ATTRIB_POWER_SWITCH | \
++ SDHCD_ATTRIB_BUS_MMC8BIT | \
++ SDHCD_ATTRIB_SD_HIGH_SPEED | \
++ SDHCD_ATTRIB_MMC_HIGH_SPEED)
++
++static UINT32 hcdattributes = DEFAULT_ATTRIBUTES;
++module_param(hcdattributes, int, 0644);
++MODULE_PARM_DESC(hcdattributes, "STD Host Attributes");
++static INT BaseClock = 0;
++module_param(BaseClock, int, 0444);
++MODULE_PARM_DESC(BaseClock, "BaseClock Hz when not present in configuration");
++static UINT32 timeout = HOST_REG_TIMEOUT_CONTROL_DEFAULT;
++module_param(timeout, int, 0644);
++MODULE_PARM_DESC(timeout, "STD Host data timeout control");
++static UINT32 ClockSpinLimit = HCD_COMMAND_MIN_POLLING_CLOCK;
++module_param(ClockSpinLimit, int, 0644);
++MODULE_PARM_DESC(ClockSpinLimit, "STD Host command clock spin time");
++
++typedef struct _STDHCD_DEV {
++ SDLIST CoreList; /* the list of core contexts */
++ spinlock_t CoreListLock; /* protection for the list */
++}STDHCD_DEV, *PSTDHCD_DEV;
++
++STDHCD_DEV StdDevices;
++
++void InitStdHostLib()
++{
++ ZERO_POBJECT(&StdDevices);
++ SDLIST_INIT(&StdDevices.CoreList);
++ spin_lock_init(&StdDevices.CoreListLock);
++}
++
++void DeinitStdHostLib()
++{
++
++
++}
++
++PSDHCD_CORE_CONTEXT CreateStdHostCore(PVOID pBusContext)
++{
++ PSDHCD_CORE_CONTEXT pStdCore = NULL;
++
++ do {
++ pStdCore = KernelAlloc(sizeof(SDHCD_CORE_CONTEXT));
++ if (NULL == pStdCore) {
++ break;
++ }
++ ZERO_POBJECT(pStdCore);
++ SDLIST_INIT(&pStdCore->SlotList);
++ spin_lock_init(&pStdCore->SlotListLock);
++ pStdCore->pBusContext = pBusContext;
++
++ /* add it */
++ spin_lock_irq(&StdDevices.CoreListLock);
++ SDListInsertHead(&StdDevices.CoreList, &pStdCore->List);
++ spin_unlock_irq(&StdDevices.CoreListLock);
++ } while (FALSE);
++
++ return pStdCore;
++}
++
++void DeleteStdHostCore(PSDHCD_CORE_CONTEXT pStdCore)
++{
++ spin_lock_irq(&StdDevices.CoreListLock);
++ /* remove */
++ SDListRemove(&pStdCore->List);
++ spin_unlock_irq(&StdDevices.CoreListLock);
++
++ KernelFree(pStdCore);
++}
++
++/* find the std core associated with this bus context */
++PSDHCD_CORE_CONTEXT GetStdHostCore(PVOID pBusContext)
++{
++ PSDLIST pListItem;
++ PSDHCD_CORE_CONTEXT pStdCore = NULL;
++
++ spin_lock_irq(&StdDevices.CoreListLock);
++
++ do {
++ if (SDLIST_IS_EMPTY(&StdDevices.CoreList)) {
++ break;
++ }
++
++ SDITERATE_OVER_LIST(&StdDevices.CoreList, pListItem) {
++ pStdCore = CONTAINING_STRUCT(pListItem, SDHCD_CORE_CONTEXT, List);
++ if (pStdCore->pBusContext == pBusContext) {
++ /* found it */
++ break;
++ }
++ pStdCore = NULL;
++ }
++
++ } while (FALSE);
++
++ spin_unlock_irq(&StdDevices.CoreListLock);
++ return pStdCore;
++}
++
++/* create a standard host memory instance */
++PSDHCD_INSTANCE CreateStdHcdInstance(POS_DEVICE pOSDevice,
++ UINT SlotNumber,
++ PTEXT pName)
++{
++ PSDHCD_INSTANCE pHcInstance = NULL;
++ BOOL success = FALSE;
++
++ do {
++ /* allocate an instance for this new device */
++ pHcInstance = (PSDHCD_INSTANCE)KernelAlloc(sizeof(SDHCD_INSTANCE));
++
++ if (pHcInstance == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Host: CreateStdHcdInstance - no memory for instance\n"));
++ break;
++ }
++
++ ZERO_POBJECT(pHcInstance);
++ SET_SDIO_STACK_VERSION(&pHcInstance->Hcd);
++
++ pHcInstance->OsSpecific.SlotNumber = SlotNumber;
++ spin_lock_init(&pHcInstance->OsSpecific.Lock);
++ spin_lock_init(&pHcInstance->OsSpecific.RegAccessLock);
++ /* initialize work items */
++ INIT_WORK(&(pHcInstance->OsSpecific.iocomplete_work), hcd_iocomplete_wqueue_handler, pHcInstance);
++ INIT_WORK(&(pHcInstance->OsSpecific.carddetect_work), hcd_carddetect_wqueue_handler, pHcInstance);
++ INIT_WORK(&(pHcInstance->OsSpecific.sdioirq_work), hcd_sdioirq_wqueue_handler, pHcInstance);
++ /* allocate space for the name */
++ pHcInstance->Hcd.pName = (PTEXT)KernelAlloc(strlen(pName)+1);
++ if (NULL == pHcInstance->Hcd.pName) {
++ break;
++ }
++ strcpy(pHcInstance->Hcd.pName,pName);
++ /* set OS device for DMA allocations and mapping */
++ pHcInstance->Hcd.pDevice = pOSDevice;
++ pHcInstance->Hcd.Attributes = hcdattributes;
++ pHcInstance->Hcd.MaxBlocksPerTrans = SDIO_SD_MAX_BLOCKS;
++ pHcInstance->Hcd.pContext = pHcInstance;
++ pHcInstance->Hcd.pRequest = HcdRequest;
++ pHcInstance->Hcd.pConfigure = HcdConfig;
++ pHcInstance->Hcd.pModule = THIS_MODULE;
++ pHcInstance->BaseClock = BaseClock;
++ pHcInstance->TimeOut = timeout;
++ pHcInstance->ClockSpinLimit = ClockSpinLimit;
++
++ success = TRUE;
++ } while (FALSE);
++
++ if (!success && (pHcInstance != NULL)) {
++ DeleteStdHcdInstance(pHcInstance);
++ }
++
++ return pHcInstance;
++}
++
++/*
++ * AddStdHcdInstance - add the std host controller instance
++*/
++SDIO_STATUS AddStdHcdInstance(PSDHCD_CORE_CONTEXT pStdCore,
++ PSDHCD_INSTANCE pHcInstance,
++ UINT Flags,
++ PPLAT_OVERRIDE_CALLBACK pCallBack,
++ SDDMA_DESCRIPTION *pSDMADescrip,
++ SDDMA_DESCRIPTION *pADMADescrip)
++{
++
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ do {
++
++ if (!SDIO_SUCCESS((status = HcdInitialize(pHcInstance)))) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST: StartStdHcdInstance - failed to init HW, status =%d\n",status));
++ break;
++ }
++ /* mark that the hardware was initialized */
++ pHcInstance->InitStateMask |= SDHC_HW_INIT;
++
++ pHcInstance->Hcd.pDmaDescription = NULL;
++
++ if (!(Flags & START_HCD_FLAGS_FORCE_NO_DMA)) {
++ /* check DMA parameters discovered by HcdInitialize */
++ if (!(Flags & START_HCD_FLAGS_FORCE_SDMA) &&
++ (pHcInstance->Caps & HOST_REG_CAPABILITIES_ADMA) &&
++ (pADMADescrip != NULL)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST: StartStdHcdInstance - using Advanced DMA\n"));
++ /* copy the DMA description for advanced DMA */
++ memcpy(&pHcInstance->DmaDescription, pADMADescrip, sizeof(SDDMA_DESCRIPTION));
++ /* set DMA description */
++ pHcInstance->Hcd.pDmaDescription = &pHcInstance->DmaDescription;
++ } else if ((pHcInstance->Caps & HOST_REG_CAPABILITIES_DMA) &&
++ (pSDMADescrip != NULL)) {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD HOST: StartStdHcdInstance - using Simple DMA\n"));
++ /* copy the DMA description for advanced DMA */
++ memcpy(&pHcInstance->DmaDescription, pSDMADescrip, sizeof(SDDMA_DESCRIPTION));
++ /* set DMA description */
++ pHcInstance->Hcd.pDmaDescription = &pHcInstance->DmaDescription;
++ }
++ }
++
++ if (IS_HCD_ADMA(pHcInstance)) {
++ /* setup DMA buffers for scatter-gather descriptor tables used in advanced DMA */
++ status = SetupDmaBuffers(pHcInstance);
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Host : StartStdHcdInstance - failed to setup DMA buffer\n"));
++ break;
++ }
++ }
++
++ if (pCallBack != NULL) {
++ /* allow the platform to override any settings */
++ status = pCallBack(pHcInstance);
++ if (!SDIO_SUCCESS(status)) {
++ break;
++ }
++ }
++ /* add this instance to our list, we will start the HCDs later */
++ /* protect the devicelist */
++ spin_lock_irq(&pStdCore->SlotListLock);
++ SDListInsertHead(&pStdCore->SlotList, &pHcInstance->List);
++ pStdCore->SlotCount++;
++ spin_unlock_irq(&pStdCore->SlotListLock);
++
++ } while (FALSE);
++
++
++ if (SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Host - ready! \n"));
++ } else {
++ /* undo everything */
++ DeinitializeStdHcdInstance(pHcInstance);
++ }
++
++ return status;
++}
++
++INT GetCurrentHcdInstanceCount(PSDHCD_CORE_CONTEXT pStdCore)
++{
++ return pStdCore->SlotCount;
++}
++
++static void DeinitializeStdHcdInstance(PSDHCD_INSTANCE pHcInstance)
++{
++ /* wait for any of our work items to run */
++ flush_scheduled_work();
++
++ if (pHcInstance->InitStateMask & SDHC_REGISTERED) {
++ SDIO_UnregisterHostController(&pHcInstance->Hcd);
++ pHcInstance->InitStateMask &= ~SDHC_REGISTERED;
++ }
++
++ if (pHcInstance->InitStateMask & SDHC_HW_INIT) {
++ HcdDeinitialize(pHcInstance);
++ pHcInstance->InitStateMask &= ~SDHC_HW_INIT;
++ }
++ /* free any DMA resources */
++ if (pHcInstance->OsSpecific.hDmaBuffer != (DMA_ADDRESS)NULL) {
++ dma_free_coherent(pHcInstance->Hcd.pDevice,
++ SDHCD_ADMA_DESCRIPTOR_SIZE,
++ pHcInstance->OsSpecific.pDmaBuffer,
++ pHcInstance->OsSpecific.hDmaBuffer);
++ pHcInstance->OsSpecific.hDmaBuffer = (DMA_ADDRESS)NULL;
++ pHcInstance->OsSpecific.pDmaBuffer = NULL;
++ }
++
++}
++void DeleteStdHcdInstance(PSDHCD_INSTANCE pHcInstance)
++{
++ if (pHcInstance->Hcd.pName != NULL) {
++ KernelFree(pHcInstance->Hcd.pName);
++ pHcInstance->Hcd.pName = NULL;
++ }
++
++ KernelFree(pHcInstance);
++}
++
++
++/*
++ * RemoveStdHcdInstance - remove the hcd instance
++*/
++PSDHCD_INSTANCE RemoveStdHcdInstance(PSDHCD_CORE_CONTEXT pStdCore)
++{
++ PSDHCD_INSTANCE pHcInstanceToRemove = NULL;
++ PSDLIST pListItem;
++
++ DBG_PRINT(SDDBG_TRACE, ("+SDIO STD HCD: RemoveStdHcdInstance\n"));
++
++ /* protect the devicelist */
++ spin_lock_irq(&pStdCore->SlotListLock);
++
++ do {
++ pListItem = SDListRemoveItemFromHead(&pStdCore->SlotList);
++
++ if (NULL == pListItem) {
++ break;
++ }
++
++ pHcInstanceToRemove = CONTAINING_STRUCT(pListItem,SDHCD_INSTANCE,List);
++
++ pStdCore->SlotCount--;
++
++ } while (FALSE);
++
++ spin_unlock_irq(&pStdCore->SlotListLock);
++
++ if (pHcInstanceToRemove != NULL) {
++ DBG_PRINT(SDDBG_TRACE, (" SDIO STD HCD: Deinitializing 0x%X \n",(UINT)pHcInstanceToRemove));
++ DeinitializeStdHcdInstance(pHcInstanceToRemove);
++ }
++
++ DBG_PRINT(SDDBG_TRACE, ("-SDIO STD HCD: RemoveStdHcdInstance\n"));
++
++ /* return the instance we found */
++ return pHcInstanceToRemove;
++}
++
++/*
++ * SetupDmaBuffers - allocate required DMA buffers
++ *
++*/
++static SDIO_STATUS SetupDmaBuffers(PSDHCD_INSTANCE pHcInstance)
++{
++ if (pHcInstance->Hcd.pDmaDescription == NULL) {
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ if (pHcInstance->Hcd.pDmaDescription->Flags & SDDMA_DESCRIPTION_FLAG_SGDMA) {
++ /* we are only supporting scatter-gather DMA in this driver */
++ /* allocate a DMA buffer large enough for the command buffers and the data buffers */
++ pHcInstance->OsSpecific.pDmaBuffer = dma_alloc_coherent(pHcInstance->Hcd.pDevice,
++ SDHCD_ADMA_DESCRIPTOR_SIZE,
++ &pHcInstance->OsSpecific.hDmaBuffer,
++ GFP_DMA);
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD Host : SetupDmaBuffers - pDmaBuffer: 0x%X, hDmaBuffer: 0x%X\n",
++ (UINT)pHcInstance->OsSpecific.pDmaBuffer , (UINT)pHcInstance->OsSpecific.hDmaBuffer ));
++ if (pHcInstance->OsSpecific.pDmaBuffer == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Host : SetupDmaBuffers - unable to get DMA buffer\n"));
++ return SDIO_STATUS_NO_RESOURCES;
++ }
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ DBG_PRINT(SDDBG_TRACE, ("SDIO STD Host : SetupDmaBuffers - invalid DMA type\n"));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++}
++
++/*
++ * QueueEventResponse - queues an event in a process context back to the bus driver
++ *
++*/
++SDIO_STATUS QueueEventResponse(PSDHCD_INSTANCE pHcInstance, INT WorkItemID)
++{
++ struct work_struct *work;
++
++ if (pHcInstance->ShuttingDown) {
++ return SDIO_STATUS_CANCELED;
++ }
++
++ switch (WorkItemID) {
++ case WORK_ITEM_IO_COMPLETE:
++ work = &pHcInstance->OsSpecific.iocomplete_work;
++ break;
++ case WORK_ITEM_CARD_DETECT:
++ work = &pHcInstance->OsSpecific.carddetect_work;
++ break;
++ case WORK_ITEM_SDIO_IRQ:
++ work = &pHcInstance->OsSpecific.sdioirq_work;
++ break;
++ default:
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_ERROR;
++ break;
++ }
++
++ if (schedule_work(work) > 0) {
++ if (WORK_ITEM_IO_COMPLETE == WorkItemID) {
++ pHcInstance->RequestCompleteQueued = TRUE;
++ }
++ return SDIO_STATUS_SUCCESS;
++ } else {
++ return SDIO_STATUS_PENDING;
++ }
++}
++
++/*
++ * hcd_iocomplete_wqueue_handler - the work queue for io completion
++*/
++static void hcd_iocomplete_wqueue_handler(void *context)
++{
++ PSDHCD_INSTANCE pHcInstance = (PSDHCD_INSTANCE)context;
++
++ pHcInstance->RequestCompleteQueued = FALSE;
++
++ if (!pHcInstance->ShuttingDown) {
++ SDIO_HandleHcdEvent(&pHcInstance->Hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++}
++
++/*
++ * hcd_carddetect_handler - the work queue for card detect debouncing
++*/
++static void hcd_carddetect_wqueue_handler(void *context)
++{
++ ProcessDeferredCardDetect((PSDHCD_INSTANCE)context);
++}
++
++/*
++ * hcd_sdioirq_handler - the work queue for handling SDIO IRQ
++*/
++static void hcd_sdioirq_wqueue_handler(void *context)
++{
++ PSDHCD_INSTANCE pHcInstance = (PSDHCD_INSTANCE)context;
++ DBG_PRINT(STD_HOST_TRACE_SDIO_INT, ("SDIO STD HOST: hcd_sdioirq_wqueue_handler \n"));
++ if (!pHcInstance->ShuttingDown) {
++ SDIO_HandleHcdEvent(&pHcInstance->Hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++ }
++}
++
++
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ UnmaskIrq - Unmask SD interrupts
++ Input: pHcInstance - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 UnmaskIrq(PSDHCD_INSTANCE pHcInstance, UINT32 Mask, BOOL FromIsr)
++{
++ UINT16 ints;
++ if (FromIsr) {
++
++ } else {
++ /* protected read-modify-write */
++ spin_lock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++
++ ints = READ_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE);
++ ints |= Mask;
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE, ints);
++
++ if (FromIsr) {
++
++ } else {
++ spin_unlock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++ return ints;
++}
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ MaskIrq - Mask SD interrupts
++ Input: pHcInstance - host controller
++ Mask - mask value
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++UINT16 MaskIrq(PSDHCD_INSTANCE pHcInstance, UINT32 Mask, BOOL FromIsr)
++{
++ UINT16 ints;
++ /* protected read-modify-write */
++ if (FromIsr) {
++
++ } else {
++ spin_lock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++ ints = READ_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE);
++ ints &= ~Mask;
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_SIGNAL_ENABLE, ints);
++ if (FromIsr) {
++
++ } else {
++ spin_unlock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++ return ints;
++}
++
++
++/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ EnableDisableSDIOIRQ - enable SDIO interrupt detection
++ Input: pHcInstance - host controller
++ Enable - enable SDIO IRQ detection
++ FromIsr - called from ISR
++ Output:
++ Return:
++ Notes:
++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
++void EnableDisableSDIOIRQ(PSDHCD_INSTANCE pHcInstance, BOOL Enable, BOOL FromIsr)
++{
++ UINT16 intsEnables;
++
++ if (FromIsr) {
++ if (Enable) {
++ // isr should never re-enable
++ DBG_ASSERT(FALSE);
++ } else {
++ MaskIrq(pHcInstance, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE,TRUE);
++ }
++ } else {
++ if (Enable) {
++ UnmaskIrq(pHcInstance, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE, FALSE);
++ } else {
++ MaskIrq(pHcInstance, HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE, FALSE);
++ }
++ }
++
++ /* protected read-modify-write */
++ if (FromIsr) {
++ spin_lock(&pHcInstance->OsSpecific.RegAccessLock);
++ } else {
++ spin_lock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++
++ intsEnables = READ_HOST_REG16(pHcInstance, HOST_REG_INT_STATUS_ENABLE);
++ if (Enable) {
++ intsEnables |= HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE;
++ } else {
++ intsEnables &= ~HOST_REG_INT_STATUS_CARD_INT_STAT_ENABLE;
++ }
++
++ WRITE_HOST_REG16(pHcInstance, HOST_REG_INT_STATUS_ENABLE, intsEnables);
++
++ if (FromIsr) {
++ spin_unlock(&pHcInstance->OsSpecific.RegAccessLock);
++ } else {
++ spin_unlock_irq(&pHcInstance->OsSpecific.RegAccessLock);
++ }
++}
++
++
++SDIO_STATUS SetUpHCDDMA(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq)
++{
++
++ PSDDMA_DESCRIPTOR pReqDescriptor = (PSDDMA_DESCRIPTOR)pReq->pDataBuffer;
++ UINT32 totalLength = 0;
++
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST SetUpHCDDMA (%s) DescCount:%d Blocks:%d, BlockLen:%d\n",
++ IS_SDREQ_WRITE_DATA(pReq->Flags) ? "TX" : "RX",
++ pReq->DescriptorCount, pReq->BlockCount, pReq->BlockLen));
++
++ if (IS_HCD_ADMA(pHcInstance) && (pReq->DescriptorCount > SDHCD_MAX_ADMA_DESCRIPTOR)) {
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_INVALID_PARAMETER;
++ } else if (IS_HCD_SDMA(pHcInstance) && (pReq->DescriptorCount > SDHCD_MAX_SDMA_DESCRIPTOR)) {
++ DBG_ASSERT(FALSE);
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ /* map this scatter gather entries to address and save for unmap */
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ dma_map_sg(pHcInstance->Hcd.pDevice, pReqDescriptor, pReq->DescriptorCount, DMA_TO_DEVICE);
++ } else {
++ dma_map_sg(pHcInstance->Hcd.pDevice, pReqDescriptor, pReq->DescriptorCount, DMA_FROM_DEVICE);
++ }
++
++ pHcInstance->OsSpecific.pDmaList = pReqDescriptor;
++ pHcInstance->OsSpecific.SGcount = pReq->DescriptorCount;
++
++ if (IS_HCD_ADMA(pHcInstance)) {
++ int ii;
++ PSDHCD_SGDMA_DESCRIPTOR pDescriptor =
++ (PSDHCD_SGDMA_DESCRIPTOR)pHcInstance->OsSpecific.pDmaBuffer;
++
++ DBG_ASSERT(pDescriptor != NULL);
++ /* for ADMA build the in memory descriptor table */
++ memset(pDescriptor, 0, pReq->DescriptorCount*(sizeof(SDHCD_SGDMA_DESCRIPTOR)));
++
++ for (ii = 0; ii < pReq->DescriptorCount; ii++,pDescriptor++) {
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST SetUpHCDDMA ADMA Descrp: 0x%X, ReqDescrip: 0x%X, len: %d bytes, addr: 0x%X\n",
++ (UINT)pDescriptor, (UINT)&pReqDescriptor[ii], (UINT)sg_dma_len(&pReqDescriptor[ii]), (UINT)sg_dma_address(&pReqDescriptor[ii])));
++ SET_DMA_LENGTH(pDescriptor, sg_dma_len(&pReqDescriptor[ii]));
++ SET_DMA_ADDRESS(pDescriptor, sg_dma_address(&pReqDescriptor[ii]));
++ totalLength += sg_dma_len(&pReqDescriptor[ii]);
++ if (ii == (pReq->DescriptorCount-1)) {
++ /* last entry, set END,
++ ****note: we do NOT want an interrupt generated for this last descriptor,
++ the controller will generate interrupts indicating:
++ write CRC acknowledgement and program done -or-
++ read CRC okay */
++ SET_DMA_END_OF_TRANSFER(pDescriptor);
++ }
++ }
++ } else {
++ DBG_PRINT(STD_HOST_TRACE_DATA, ("SDIO STD HOST SetUpHCDDMA SDMA, ReqDescrip: 0x%X, len: %d bytes, addr: 0x%X\n",
++ (UINT)pReqDescriptor, (UINT)sg_dma_len(pReqDescriptor), (UINT)sg_dma_address(pReqDescriptor)));
++ /* for simple DMA, setup DMA address */
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_SYSTEM_ADDRESS, sg_dma_address(pReqDescriptor));
++ /* since we only support 1 descriptor of up to 512KB size, we set the boundary up to 512KB
++ to prevent the DMA from stopping early , we let block count and length stop the DMA*/
++ WRITE_HOST_REG16(pHcInstance,
++ HOST_REG_BLOCK_SIZE,
++ READ_HOST_REG16(pHcInstance,HOST_REG_BLOCK_SIZE) | HOST_REG_BLOCK_SIZE_DMA_512K_BOUNDARY);
++ totalLength = sg_dma_len(pReqDescriptor);
++ }
++
++ if (totalLength != (pReq->BlockCount * pReq->BlockLen)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST DMA Block Length and Count Mismatch SGList Reports:%d bytes, Bus request : Blocks:%d,Bytes Per Block:%d \n",
++ totalLength,pReq->BlockCount,pReq->BlockLen));
++ return SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ if (IS_HCD_ADMA(pHcInstance)) {
++ /* program the controller to execute the descriptor list */
++ WRITE_HOST_REG32(pHcInstance, HOST_REG_ADMA_ADDRESS, (UINT32)pHcInstance->OsSpecific.hDmaBuffer);
++ /* unprotect read-modify-write, set 32-bit DMA mode */
++ WRITE_HOST_REG8(pHcInstance, HOST_REG_CONTROL,
++ (READ_HOST_REG8(pHcInstance, HOST_REG_CONTROL) & ~HOST_REG_CONTROL_DMA_MASK) |
++ HOST_REG_CONTROL_DMA_32BIT);
++ }
++
++ return SDIO_STATUS_PENDING;
++}
++
++/*
++ * HcdTransferDataDMAEnd - cleanup bus master scatter-gather DMA read/write
++*/
++void HcdTransferDataDMAEnd(PSDHCD_INSTANCE pHcInstance, PSDREQUEST pReq)
++{
++ if (pHcInstance->OsSpecific.SGcount > 0) {
++ if (IS_SDREQ_WRITE_DATA(pReq->Flags)) {
++ dma_unmap_sg(pHcInstance->Hcd.pDevice,
++ pHcInstance->OsSpecific.pDmaList,
++ pHcInstance->OsSpecific.SGcount,
++ DMA_TO_DEVICE);
++ } else {
++ dma_unmap_sg(pHcInstance->Hcd.pDevice,
++ pHcInstance->OsSpecific.pDmaList,
++ pHcInstance->OsSpecific.SGcount,
++ DMA_FROM_DEVICE);
++ }
++ pHcInstance->OsSpecific.SGcount = 0;
++ }
++}
++
++void DumpDMADescriptorsInfo(PSDHCD_INSTANCE pHcInstance)
++{
++ if (IS_HCD_ADMA(pHcInstance)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD HOST, ADMA Descriptor Start (PHYS):0x%X \n",
++ (UINT32)pHcInstance->OsSpecific.hDmaBuffer));
++ SDLIB_PrintBuffer((PUCHAR)pHcInstance->OsSpecific.pDmaBuffer, SDHCD_ADMA_DESCRIPTOR_SIZE, "SDIO STD HOST: ALL DMA Descriptors");
++ }
++}
++
++/* handle an interrupting standard host
++ * this route checks the slot interrupting register and calls the interrupt routine
++ * of the interrupting slot, the caller must the std core structure containing a
++ * list of hcd instances. This function will use the first hcd instance to read the
++ * slot interrupting register.
++ * */
++BOOL HandleSharedStdHostInterrupt(PSDHCD_CORE_CONTEXT pStdCore)
++{
++ PSDLIST pListItem;
++ UINT16 interruptingSlots;
++ BOOL handled = FALSE;
++ UINT slotIndex;
++ PSDHCD_INSTANCE pHcInstance;
++
++
++ /* this is called at ISR priority, we do not need to protect the list */
++ if (SDLIST_IS_EMPTY(&pStdCore->SlotList)) {
++ return FALSE;
++ }
++ /* the first controller will do, the interrupt status register
++ * is mapped to each slot controller */
++ pListItem = SDLIST_GET_ITEM_AT_HEAD(&pStdCore->SlotList);
++
++ pHcInstance = CONTAINING_STRUCT(pListItem, SDHCD_INSTANCE, List);
++
++ interruptingSlots = READ_HOST_REG16(pHcInstance, HOST_REG_SLOT_INT_STATUS);
++ interruptingSlots &= HOST_REG_SLOT_INT_MASK;
++
++ if (0 == interruptingSlots) {
++ /* not our interrupt */
++ return FALSE;
++ }
++
++ DBG_PRINT(STD_HOST_TRACE_INT, ("SDIO STD HOST HandleSharedStdHostInterrupt : slot ints:0x%X \n",interruptingSlots));
++
++ slotIndex = 0;
++
++ SDITERATE_OVER_LIST(&pStdCore->SlotList, pListItem) {
++ pHcInstance = CONTAINING_STRUCT(pListItem, SDHCD_INSTANCE, List);
++ /* is it interrupting ? */
++ if ((1 << pHcInstance->OsSpecific.SlotNumber) & interruptingSlots) {
++ DBG_PRINT(STD_HOST_TRACE_INT, ("SDIO STD HOST HandleSharedStdHostInterrupt pHcInstance: 0x%X, slot:%d is interrupting \n",
++ (UINT)pHcInstance,pHcInstance->OsSpecific.SlotNumber));
++
++ /* this one is interrupting.. */
++ TRACE_SIGNAL_DATA_ISR(pHcInstance, TRUE);
++ if (HcdSDInterrupt(pHcInstance)) {
++ /* at least one handled it */
++ handled = TRUE;
++ }
++ TRACE_SIGNAL_DATA_ISR(pHcInstance, FALSE);
++ }
++ }
++
++ return handled;
++}
++
++/* start the standard host instances
++ * this function registers the standard host drivers and queues an event to check the slots */
++SDIO_STATUS StartStdHostCore(PSDHCD_CORE_CONTEXT pStdCore)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDHCD_INSTANCE pHcInstance;
++ PSDLIST pListItem;
++ INT coreStarts = 0;
++
++ spin_lock_irq(&pStdCore->SlotListLock);
++
++ do {
++
++ if (SDLIST_IS_EMPTY(&pStdCore->SlotList)) {
++ break;
++ }
++
++ SDITERATE_OVER_LIST(&pStdCore->SlotList, pListItem) {
++
++ pHcInstance = CONTAINING_STRUCT(pListItem, SDHCD_INSTANCE, List);
++
++ spin_unlock_irq(&pStdCore->SlotListLock);
++
++ /* register with the SDIO bus driver */
++ status = SDIO_RegisterHostController(&pHcInstance->Hcd);
++
++ spin_lock_irq(&pStdCore->SlotListLock);
++
++ if (!SDIO_SUCCESS(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("SDIO STD Host - failed to register with host, status =%d\n",status));
++ break;
++ }
++
++ coreStarts++;
++
++ /* mark that it has been registered */
++ pHcInstance->InitStateMask |= SDHC_REGISTERED;
++
++ /* queue a work item to check for a card present at start up
++ this call will unmask the insert/remove interrupts */
++ QueueEventResponse(pHcInstance, WORK_ITEM_CARD_DETECT);
++ }
++
++ } while (FALSE);
++
++ spin_unlock_irq(&pStdCore->SlotListLock);
++
++ if (0 == coreStarts) {
++ return SDIO_STATUS_ERROR;
++ }
++
++ return SDIO_STATUS_SUCCESS;
++
++}
Added: developers/sameo/patches/ar6k-atheros/pnp_fixes_2.6.22.5.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/pnp_fixes_2.6.22.5.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/pnp_fixes_2.6.22.5.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,24 @@
+---
+ drivers/pnp/resource.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+Index: linux-2.6.22.5/drivers/pnp/resource.c
+===================================================================
+--- linux-2.6.22.5.orig/drivers/pnp/resource.c 2007-11-07 12:51:17.000000000 +0100
++++ linux-2.6.22.5/drivers/pnp/resource.c 2007-11-07 12:51:26.000000000 +0100
+@@ -447,6 +447,7 @@
+ }
+ }
+
++#if 0
+ /* check if the resource is already in use, skip if the
+ * device is active because it itself may be in use */
+ if(!dev->active) {
+@@ -454,6 +455,7 @@
+ return 0;
+ free_dma(*dma);
+ }
++#endif
+
+ /* check for conflicts with other pnp devices */
+ pnp_for_each_dev(tdev) {
Added: developers/sameo/patches/ar6k-atheros/s3c2440_wlan_gpio_cfg.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/s3c2440_wlan_gpio_cfg.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/s3c2440_wlan_gpio_cfg.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,19 @@
+---
+ arch/arm/mach-s3c2440/mach-gta02.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+Index: linux-2.6.22/arch/arm/mach-s3c2440/mach-gta02.c
+===================================================================
+--- linux-2.6.22.orig/arch/arm/mach-s3c2440/mach-gta02.c 2007-11-09 15:11:09.000000000 +0100
++++ linux-2.6.22/arch/arm/mach-s3c2440/mach-gta02.c 2007-11-09 15:24:36.000000000 +0100
+@@ -651,7 +651,10 @@
+ set_s3c2410ts_info(>a02_ts_cfg);
+
+ /* FIXME: hardcoded WLAN module power-up */
++ s3c2410_gpio_cfgpin(GTA02_CHIP_PWD, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_setpin(GTA02_CHIP_PWD, 0);
++
++ s3c2410_gpio_cfgpin(GTA02_GPIO_nWLAN_RESET, S3C2410_GPIO_OUTPUT);
+ switch (system_rev) {
+ case GTA02v1_SYSTEM_REV:
+ break;
Added: developers/sameo/patches/ar6k-atheros/s3c24xx_hcd_atheros.patch
===================================================================
--- developers/sameo/patches/ar6k-atheros/s3c24xx_hcd_atheros.patch 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/s3c24xx_hcd_atheros.patch 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,1240 @@
+---
+ drivers/sdio/hcd/Kconfig | 8
+ drivers/sdio/hcd/Makefile | 1
+ drivers/sdio/hcd/s3c24xx/Makefile | 2
+ drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.c | 1137 +++++++++++++++++++++++++++++++++
+ drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.h | 50 +
+ 5 files changed, 1198 insertions(+)
+
+Index: linux-2.6.22/drivers/sdio/hcd/Kconfig
+===================================================================
+--- linux-2.6.22.orig/drivers/sdio/hcd/Kconfig 2007-11-12 13:47:26.000000000 +0100
++++ linux-2.6.22/drivers/sdio/hcd/Kconfig 2007-11-12 13:47:34.000000000 +0100
+@@ -46,6 +46,14 @@
+ help
+ good luck.
+
++config SDIO_S3C24XX
++ tristate "Samsung s3c24xx host controller"
++ depends on PLAT_S3C24XX
++ default m
++ help
++ good luck.
++
++
+ config SDIO_SPI
+ tristate "SPI host controller"
+ depends on SPI
+Index: linux-2.6.22/drivers/sdio/hcd/Makefile
+===================================================================
+--- linux-2.6.22.orig/drivers/sdio/hcd/Makefile 2007-11-12 13:47:26.000000000 +0100
++++ linux-2.6.22/drivers/sdio/hcd/Makefile 2007-11-12 13:47:34.000000000 +0100
+@@ -6,3 +6,4 @@
+ obj-$(CONFIG_ARCH_OMAP24XX) += omap_2420/
+ obj-$(CONFIG_PXA27x) += pxa270/
+ obj-$(CONFIG_PXA255) += pxa255/
++obj-$(CONFIG_PLAT_S3C24XX) += s3c24xx/
+Index: linux-2.6.22/drivers/sdio/hcd/s3c24xx/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/s3c24xx/Makefile 2007-11-12 13:47:34.000000000 +0100
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_PLAT_S3C24XX) += sdio_s3c24xx_hcd.o
++sdio_s3c24xx_hcd-objs := s3c24xx_hcd.o
+Index: linux-2.6.22/drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.c 2007-11-23 18:25:27.000000000 +0100
+@@ -0,0 +1,1137 @@
++/*
++ * s3c24xx_hcd.c - Samsung S3C MCI driver
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/clk.h>
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++
++#include <linux/sdio/ctsystem.h>
++#include <linux/sdio/sdio_busdriver.h>
++#include <linux/sdio/sdio_lib.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++
++#include <asm/arch/regs-sdi.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/mci.h>
++#include <asm/arch/gta02.h>
++
++#include "s3c24xx_hcd.h"
++
++#define DESCRIPTION "S3c24xx SDIO host controller"
++#define AUTHOR "Samuel Ortiz <sameo at openedhand.com>"
++
++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
++
++static struct resource s3c24xx_hcd_mem = {
++ .start = S3C2410_PA_SDI,
++ .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static void s3c24xx_dump_regs(struct s3c24xx_hcd_context * context)
++{
++ u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
++ u32 datcon, datcnt, datsta, fsta, imask;
++
++ con = readl(context->base + S3C2410_SDICON);
++ pre = readl(context->base + S3C2410_SDIPRE);
++ cmdarg = readl(context->base + S3C2410_SDICMDARG);
++ cmdcon = readl(context->base + S3C2410_SDICMDCON);
++ cmdsta = readl(context->base + S3C2410_SDICMDSTAT);
++ r0 = readl(context->base + S3C2410_SDIRSP0);
++ r1 = readl(context->base + S3C2410_SDIRSP1);
++ r2 = readl(context->base + S3C2410_SDIRSP2);
++ r3 = readl(context->base + S3C2410_SDIRSP3);
++ timer = readl(context->base + S3C2410_SDITIMER);
++ bsize = readl(context->base + S3C2410_SDIBSIZE);
++ datcon = readl(context->base + S3C2410_SDIDCON);
++ datcnt = readl(context->base + S3C2410_SDIDCNT);
++ datsta = readl(context->base + S3C2410_SDIDSTA);
++ fsta = readl(context->base + S3C2410_SDIFSTA);
++ imask = readl(context->base + S3C2440_SDIIMSK);
++
++ printk("SDICON: 0x%08x\n", con);
++ printk("SDIPRE: 0x%08x\n", pre);
++ printk("SDICmdArg: 0x%08x\n", cmdarg);
++ printk("SDICmdCon: 0x%08x\n", cmdcon);
++ printk("SDICmdSta: 0x%08x\n", cmdsta);
++ printk("SDIRSP0: 0x%08x\n", r0);
++ printk("SDIRSP1: 0x%08x\n", r1);
++ printk("SDIRSP2: 0x%08x\n", r2);
++ printk("SDIRSP3: 0x%08x\n", r3);
++ printk("SDIDTimer: 0x%08x\n", timer);
++ printk("SDIBSize: 0x%08x\n", bsize);
++ printk("SDIDatCon: 0x%08x\n", datcon);
++ printk("SDIDatCnt: 0x%08x\n", datcnt);
++ printk("SDIDatSta: 0x%08x\n", datsta);
++ printk("SDIFSta: 0x%08x\n", fsta);
++ printk("SDIIntMsk: 0x%08x\n", imask);
++}
++
++static void s3c24xx_dump_fifo(struct s3c24xx_hcd_context * context, int iter)
++{
++ int i;
++
++ printk("Data FIFO dumping: \n");
++ for (i = 0; i < iter; i++) {
++ printk("\t[0]: 0x%08x", readl(context->base + S3C2440_SDIDATA));
++ printk(" [1]: 0x%08x ", readl(context->base + S3C2440_SDIDATA + 4));
++ printk(" [2]: 0x%08x ", readl(context->base + S3C2440_SDIDATA + 8));
++ printk(" [3]: 0x%08x ", readl(context->base + S3C2440_SDIDATA + 0xc));
++ }
++ printk("\n");
++
++}
++
++static inline void s3c24xx_hcd_clear_imask(struct s3c24xx_hcd_context * context)
++{
++ if (context->int_sdio)
++ writel(S3C2410_SDIIMSK_SDIOIRQ | S3C2410_SDIIMSK_READWAIT,
++ context->base + S3C2440_SDIIMSK);
++ else
++ writel(0, context->base + S3C2440_SDIIMSK);
++}
++
++static inline void s3c24xx_hcd_set_imask(struct s3c24xx_hcd_context * context)
++{
++ writel(context->int_mask, context->base + S3C2440_SDIIMSK);
++}
++
++
++static inline void s3c24xx_hcd_clear_dsta(struct s3c24xx_hcd_context * context)
++{
++ u32 dsta;
++
++ dsta = readl(context->base + S3C2410_SDIDSTA);
++ writel(dsta, context->base + S3C2410_SDIDSTA);
++}
++
++static inline void s3c24xx_hcd_clear_csta(struct s3c24xx_hcd_context * context)
++{
++ u32 csta, csta_clear = 0;
++
++ csta = readl(context->base + S3C2410_SDICMDSTAT);
++
++ if (csta & S3C2410_SDICMDSTAT_CRCFAIL)
++ csta_clear |= S3C2410_SDICMDSTAT_CRCFAIL;
++ if (csta & S3C2410_SDICMDSTAT_CMDSENT)
++ csta_clear |= S3C2410_SDICMDSTAT_CMDSENT;
++ if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
++ csta_clear |= S3C2410_SDICMDSTAT_CMDTIMEOUT;
++ if (csta & S3C2410_SDICMDSTAT_RSPFIN)
++ csta_clear |= S3C2410_SDICMDSTAT_RSPFIN;
++
++ writel(csta_clear, context->base + S3C2410_SDICMDSTAT);
++}
++
++static inline void s3c24xx_hcd_clear_sta(struct s3c24xx_hcd_context * context)
++{
++ u32 csta, dsta, csta_clear = 0, dsta_clear = 0;
++
++ csta = readl(context->base + S3C2410_SDICMDSTAT);
++ dsta = readl(context->base + S3C2410_SDIDSTA);
++
++ if (csta & S3C2410_SDICMDSTAT_CRCFAIL)
++ csta_clear |= S3C2410_SDICMDSTAT_CRCFAIL;
++ if (csta & S3C2410_SDICMDSTAT_CMDSENT)
++ csta_clear |= S3C2410_SDICMDSTAT_CMDSENT;
++ if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
++ csta_clear |= S3C2410_SDICMDSTAT_CMDTIMEOUT;
++ if (csta & S3C2410_SDICMDSTAT_RSPFIN)
++ csta_clear |= S3C2410_SDICMDSTAT_RSPFIN;
++
++
++ if (dsta & S3C2410_SDIDSTA_RDYWAITREQ)
++ dsta_clear |= S3C2410_SDIDSTA_RDYWAITREQ;
++ if (dsta & S3C2410_SDIDSTA_SDIOIRQDETECT)
++ dsta_clear |= S3C2410_SDIDSTA_SDIOIRQDETECT;
++ if (dsta & S3C2410_SDIDSTA_FIFOFAIL)
++ dsta_clear |= S3C2410_SDIDSTA_FIFOFAIL;
++ if (dsta & S3C2410_SDIDSTA_CRCFAIL)
++ dsta_clear |= S3C2410_SDIDSTA_CRCFAIL;
++ if (dsta & S3C2410_SDIDSTA_RXCRCFAIL)
++ dsta_clear |= S3C2410_SDIDSTA_RXCRCFAIL;
++ if (dsta & S3C2410_SDIDSTA_DATATIMEOUT)
++ dsta_clear |= S3C2410_SDIDSTA_DATATIMEOUT;
++ if (dsta & S3C2410_SDIDSTA_XFERFINISH)
++ dsta_clear |= S3C2410_SDIDSTA_XFERFINISH;
++ if (dsta & S3C2410_SDIDSTA_BUSYFINISH)
++ dsta_clear |= S3C2410_SDIDSTA_BUSYFINISH;
++ if (dsta & S3C2410_SDIDSTA_SBITERR)
++ dsta_clear |= S3C2410_SDIDSTA_SBITERR;
++
++ writel(csta_clear, context->base + S3C2410_SDICMDSTAT);
++ writel(dsta_clear, context->base + S3C2410_SDIDSTA);
++}
++
++static inline void s3c24xx_hcd_fifo_reset(struct s3c24xx_hcd_context * context)
++{
++ u32 fsta;
++
++ fsta = readl(context->base + S3C2410_SDIFSTA);
++ fsta |= S3C2440_SDIFSTA_FIFORESET;
++ writel(fsta, context->base + S3C2410_SDIFSTA);
++}
++
++
++static void s3c24xx_hcd_reset(struct s3c24xx_hcd_context * context)
++{
++ u32 con, counter;
++ unsigned long flags;
++
++ spin_lock_irqsave(&context->lock, flags);
++
++ con = readl(context->base + S3C2410_SDICON);
++
++ con |= S3C2440_SDICON_SDRESET;
++
++ writel(con, context->base + S3C2410_SDICON);
++
++ counter = 1000;
++ while(counter) {
++ con = readl(context->base + S3C2410_SDICON);
++ if (!(con & S3C2440_SDICON_SDRESET))
++ break;
++ counter--;
++ mdelay(1);
++ }
++
++ spin_unlock_irqrestore(&context->lock, flags);
++}
++
++static SDIO_STATUS s3c24xx_hcd_clock_enable(struct s3c24xx_hcd_context * context,
++ unsigned int clock_rate,
++ unsigned char enable)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ unsigned long flags;
++ u32 con;
++
++ spin_lock_irqsave(&context->lock, flags);
++
++ con = readl(context->base + S3C2410_SDICON);
++
++ if (enable && clock_rate) {
++ con |= S3C2410_SDICON_CLOCKTYPE;
++ } else {
++ con &= ~S3C2410_SDICON_CLOCKTYPE;
++ }
++
++ if (clock_rate) {
++ int prescaler;
++
++ for (prescaler = 0; prescaler < 0xff; prescaler++) {
++ context->device.actual_clock_rate =
++ context->device.max_clock_rate / (prescaler + 1);
++
++ if (context->device.actual_clock_rate <= clock_rate &&
++ context->device.actual_clock_rate <= context->hcd.MaxClockRate)
++ break;
++ }
++
++ if (prescaler == 0xff)
++ DBG_PRINT(SDDBG_ERROR , ("Using lowest clock rate\n"));
++
++ writel(prescaler, context->base + S3C2410_SDIPRE);
++ }
++
++ writel(con, context->base + S3C2410_SDICON);
++
++ spin_unlock_irqrestore(&context->lock, flags);
++
++ return SDIOErrorToOSError(status);
++}
++
++static void s3c24xx_hcd_set_bus_mode(struct s3c24xx_hcd_context *context,
++ PSDCONFIG_BUS_MODE_DATA pMode)
++{
++ u32 datacon;
++ unsigned long flags;
++
++ DBG_PRINT(SDDBG_TRACE , ("SetBusMode\n"));
++
++ spin_lock_irqsave(&context->lock, flags);
++ datacon = readl(context->base + S3C2410_SDIDCON);
++
++ switch (SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)) {
++ case SDCONFIG_BUS_WIDTH_1_BIT:
++ context->bus_width = 1;
++ datacon &= S3C2410_SDIDCON_WIDEBUS;
++ break;
++ case SDCONFIG_BUS_WIDTH_4_BIT:
++ context->bus_width = 4;
++ datacon |= S3C2410_SDIDCON_WIDEBUS;
++ break;
++ default:
++ DBG_PRINT(SDDBG_TRACE , ("Unknown bus width: %d\n", SDCONFIG_GET_BUSWIDTH(pMode->BusModeFlags)));
++ break;
++ }
++
++ writel(datacon, context->base + S3C2410_SDIDCON);
++ spin_unlock_irqrestore(&context->lock, flags);
++
++ /* Set clock rate and enable clock */
++ s3c24xx_hcd_clock_enable(context, pMode->ClockRate, 1);
++ pMode->ActualClockRate = context->device.actual_clock_rate;
++
++ printk("BUS mode: %d bits wide, actual clock rate: %d kHz (requested %d kHz)\n",
++ context->bus_width, pMode->ActualClockRate / 1000, pMode->ClockRate / 1000);
++ DBG_PRINT(SDDBG_TRACE , ("BUS mode: %d bits wide, actual clock rate: %d kHz (requested %d kHz)\n",
++ context->bus_width, pMode->ActualClockRate / 1000, pMode->ClockRate / 1000));
++}
++
++
++static void s3c24xx_hcd_pio_complete(struct s3c24xx_hcd_context * context)
++{
++ u32 fsta, counter;
++ u8 *ptr;
++ int fifo_count;
++ PSDREQUEST req;
++ SDIO_STATUS status;
++
++ req = GET_CURRENT_REQUEST(&context->hcd);
++ if (req == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("%s(): No current request\n", __FUNCTION__));
++ return;
++ }
++
++ ptr = req->pDataBuffer;
++
++ if (context->complete == S3C24XX_HCD_DATA_READ) {
++ counter = 0;
++ printk("Data read...");
++ do {
++ counter++;
++ fsta = readl(context->base + S3C2410_SDIFSTA);
++ mdelay(1);
++ if (counter > 1000) {
++ DBG_PRINT(SDDBG_ERROR, ("DATA read timeout\n"));
++ status = SDIO_STATUS_BUS_READ_TIMEOUT;
++ s3c24xx_dump_regs(context);
++ goto out;
++ break;
++ }
++ } while(!(fsta & S3C2410_SDIFSTA_RFDET));
++ printk("RX detected\n");
++
++ while ((fifo_count = (readl(context->base + S3C2410_SDIFSTA) & S3C2410_SDIFSTA_COUNTMASK))) {
++ if (fifo_count > req->DataRemaining) {
++ DBG_PRINT(SDDBG_ERROR, ("DATA read, fifo_count %d > expected %d\n", fifo_count, req->DataRemaining));
++ fifo_count = req->DataRemaining;
++ }
++
++// printk("%s(): Reading %d bytes, data size: %d\n", __FUNCTION__, fifo_count, context->data_size);
++
++ req->DataRemaining -= fifo_count;
++ while (fifo_count > 0) {
++ if (context->data_size == 4)
++ *(ptr) = readl(context->base + S3C2440_SDIDATA);
++ else if (context->data_size == 2)
++ *(ptr) = readw(context->base + S3C2440_SDIDATA);
++ else
++ *(ptr) = readb(context->base + S3C2440_SDIDATA);
++
++ ptr += context->data_size;
++ fifo_count -= context->data_size;
++ }
++
++ if (!req->DataRemaining) {
++ /* We poll for xfer finish */
++ counter = 0;
++ while (!(readl(context->base + S3C2410_SDIDSTA)
++ & S3C2410_SDIDSTA_XFERFINISH)) {
++ counter++;
++ mdelay(1);
++ if (counter > 500) {
++ printk("RX XFERFINISH missing\n");
++ //s3c24xx_dump_regs(context);
++ break;
++ }
++ }
++
++ status = SDIO_STATUS_SUCCESS;
++ goto out;
++ }
++ }
++
++ } else if (context->complete == S3C24XX_HCD_DATA_WRITE) {
++ counter = 0;
++ printk("Data write...");
++ do {
++ counter++;
++ fsta = readl(context->base + S3C2410_SDIFSTA);
++ mdelay(1);
++ if (counter > 1000) {
++ DBG_PRINT(SDDBG_ERROR, ("DATA write timeout\n"));
++ status = SDIO_STATUS_BUS_WRITE_ERROR;
++ goto out;
++ break;
++ }
++
++ } while(!(fsta & S3C2410_SDIFSTA_TFDET));
++ printk("TX detected\n");
++
++
++ if (req->BlockLen == 52) {
++ int i;
++
++ printk("Block size is 52\n");
++ for (i = 0; i < 52; i++)
++ printk("0x%x ", ptr[i]);
++ printk("\n");
++ }
++
++ while ((fifo_count = (63 -
++ (readl(context->base + S3C2410_SDIFSTA) & S3C2410_SDIFSTA_COUNTMASK)))) {
++// printk("%s(): We can write %d bytes\n", __FUNCTION__, fifo_count);
++
++ if (fifo_count > req->DataRemaining)
++ fifo_count = req->DataRemaining;
++
++ req->DataRemaining -= fifo_count;
++
++ while (fifo_count > 0) {
++ if (context->data_size == 4)
++ writel(*(ptr), context->base + S3C2440_SDIDATA);
++ else if (context->data_size == 2)
++ writew(*(ptr), context->base + S3C2440_SDIDATA);
++ else
++ writeb(*(ptr), context->base + S3C2440_SDIDATA);
++
++ ptr += context->data_size;
++ fifo_count -= context->data_size;
++ }
++
++ if (!req->DataRemaining) {
++ /* We poll for xfer finish */
++ counter = 0;
++ while (!(readl(context->base + S3C2410_SDIDSTA)
++ & S3C2410_SDIDSTA_XFERFINISH)) {
++ counter++;
++ mdelay(1);
++ if (counter > 500) {
++ printk("RX XFERFINISH missing\n");
++ //s3c24xx_dump_regs(context);
++ break;
++ }
++ }
++
++ status = SDIO_STATUS_SUCCESS;
++ goto out;
++ }
++ }
++
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("Wrong context: %d\n", context->complete));
++ }
++
++ out:
++ req->Status = status;
++}
++
++static void s3c24xx_hcd_pio_work(struct work_struct *work)
++{
++ PSDREQUEST req;
++ struct s3c24xx_hcd_context * context =
++ container_of(work, struct s3c24xx_hcd_context, pio_work);
++
++// printk("######## %s() ############\n", __FUNCTION__);
++
++ req = GET_CURRENT_REQUEST(&context->hcd);
++ if (req == NULL) {
++ if (context->int_sdio_pending) {
++ printk("SDIO IRQ processed\n");
++ SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++ context->int_sdio_pending = 0;
++ } else {
++ DBG_PRINT(SDDBG_ERROR, ("%s(): No current request\n", __FUNCTION__));
++ }
++ return;
++ }
++
++ if (req->Status == SDIO_STATUS_BUS_RESP_TIMEOUT) {
++ printk("### TIMEOUT ###\n");
++ s3c24xx_dump_regs(context);
++ SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_TRANSFER_DONE);
++ goto out;
++ }
++
++ if (context->int_sdio_pending) {
++ printk("SDIO IRQ processed\n");
++ SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_SDIO_IRQ_PENDING);
++ context->int_sdio_pending = 0;
++ }
++
++ spin_lock(&context->lock);
++
++ if (context->complete == S3C24XX_HCD_NO_RESPONSE &&
++ req->Status == SDIO_STATUS_SUCCESS) {
++ DBG_PRINT(SDDBG_TRACE, ("CMD done, Status: %d\n", req->Status));
++ SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++
++ if ((context->complete == S3C24XX_HCD_RESPONSE_SHORT ||
++ context->complete == S3C24XX_HCD_RESPONSE_LONG ||
++ context->complete == S3C24XX_HCD_DATA_READ ||
++ context->complete == S3C24XX_HCD_DATA_WRITE) &&
++ req->Status == SDIO_STATUS_SUCCESS) {
++ u32 resp[4];
++
++ /* We need to copy the response data and send it over */
++ resp[0] = readl(context->base + S3C2410_SDIRSP0);
++ resp[1] = readl(context->base + S3C2410_SDIRSP1);
++ resp[2] = readl(context->base + S3C2410_SDIRSP2);
++ resp[3] = readl(context->base + S3C2410_SDIRSP3);
++
++ if (GET_SDREQ_RESP_TYPE(req->Flags) != SDREQ_FLAGS_RESP_R2) {
++ //printk("SHORT response: 0x%08x\n", resp[0]);
++ DBG_PRINT(SDDBG_TRACE, ("SHORT response: 0x%08x\n", resp[0]));
++ memcpy(&req->Response[1], (u8*)resp, 4);
++ req->Response[5] = (readl(context->base + S3C2410_SDICMDSTAT) & 0xff);
++ } else {
++ printk("LONG response: 0x%08x\n", resp[0]);
++ DBG_PRINT(SDDBG_TRACE, ("LONG response: 0x%08x\n", resp[0]));
++ memcpy(&req->Response[1], (u8*)resp, 16);
++ //req->Response[17] = (readl(context->base + S3C2410_SDICMDSTAT) & 0xff);
++ }
++
++ if (context->complete == S3C24XX_HCD_RESPONSE_SHORT ||
++ context->complete == S3C24XX_HCD_RESPONSE_LONG) {
++ //SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_TRANSFER_DONE);
++ } else {
++ /* There is a data stage */
++ s3c24xx_hcd_pio_complete(context);
++ //SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_TRANSFER_DONE);
++ }
++ }
++
++
++ out:
++ s3c24xx_hcd_clear_sta(context);
++ s3c24xx_hcd_clear_imask(context);
++
++ writel(0, context->base + S3C2410_SDICMDARG);
++ writel(0, context->base + S3C2410_SDICMDCON);
++
++#if 0
++ if ((req->Argument == 0x941FF804) ||
++ (req->Argument == 0x1008A001)) {
++ s3c24xx_dump_regs(context);
++ printk("INT SDIO: %d\n", context->int_sdio);
++ }
++#endif
++ spin_unlock(&context->lock);
++
++ SDIO_HandleHcdEvent(&context->hcd, EVENT_HCD_TRANSFER_DONE);
++}
++
++
++static irqreturn_t s3c24xx_hcd_cd_irq(int irq, void *dev_id)
++{
++ printk("######## %s() ############\n", __FUNCTION__);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t s3c24xx_hcd_irq(int irq, void *dev_id)
++{
++ u32 cmdsta, dsta;
++ unsigned long flags;
++ PSDREQUEST req;
++ struct s3c24xx_hcd_context * context =
++ (struct s3c24xx_hcd_context *)dev_id;
++
++ spin_lock_irqsave(&context->lock, flags);
++
++ s3c24xx_hcd_clear_imask(context);
++
++ cmdsta = readl(context->base + S3C2410_SDICMDSTAT);
++ dsta = readl(context->base + S3C2410_SDIDSTA);
++ s3c24xx_hcd_clear_csta(context);
++
++// printk("######## IRQ cmsta: 0x%08x dsta: 0x%08x ############\n", cmdsta, dsta);
++
++ if (dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
++// printk("Got SDIO IRQ\n");
++ writel(S3C2410_SDIDSTA_SDIOIRQDETECT, context->base + S3C2410_SDIDSTA);
++
++ if (context->int_sdio &&
++ !context->int_sdio_reported &&
++ !context->int_sdio_pending) {
++ u32 imask;
++
++ printk("Got SDIO IRQ\n");
++ context->int_sdio = 0;
++ context->int_sdio_reported = 1;
++ context->int_sdio_pending = 1;
++
++ imask = readl(context->base + S3C2440_SDIIMSK);
++ imask &= ~S3C2410_SDIIMSK_SDIOIRQ;
++ writel(imask, context->base + S3C2440_SDIIMSK);
++ schedule_work(&context->pio_work);
++ }
++ }
++
++ req = GET_CURRENT_REQUEST(&context->hcd);
++ if (req == NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("%s(): No current request\n", __FUNCTION__));
++ goto out;
++ }
++
++ if (cmdsta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
++ DBG_PRINT(SDDBG_ERROR, ("TIMEOUT\n"));
++ req->Status = SDIO_STATUS_BUS_RESP_TIMEOUT;
++ schedule_work(&context->pio_work);
++ }
++
++ if (cmdsta & S3C2410_SDICMDSTAT_CMDSENT) {
++ if (context->complete == S3C24XX_HCD_NO_RESPONSE) {
++ req->Status = SDIO_STATUS_SUCCESS;
++ schedule_work(&context->pio_work);
++ }
++ }
++
++ if (cmdsta & S3C2410_SDICMDSTAT_RSPFIN) {
++ if (context->complete == S3C24XX_HCD_RESPONSE_SHORT ||
++ context->complete == S3C24XX_HCD_RESPONSE_LONG ||
++ context->complete == S3C24XX_HCD_DATA_READ ||
++ context->complete == S3C24XX_HCD_DATA_WRITE) {
++ req->Status = SDIO_STATUS_SUCCESS;
++ schedule_work(&context->pio_work);
++ }
++ }
++
++ out:
++ spin_unlock_irqrestore(&context->lock, flags);
++ return IRQ_HANDLED;
++}
++
++
++SDIO_STATUS s3c24xx_hcd_config(PSDHCD hcd, PSDCONFIG config)
++{
++ u32 con, imsk, dsta;
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ PSDCONFIG_SDIO_INT_CTRL_DATA int_data;
++ struct s3c24xx_hcd_context * context = (struct s3c24xx_hcd_context *)hcd->pContext;
++
++// printk("######## %s() ############\n", __FUNCTION__);
++
++ switch (GET_SDCONFIG_CMD(config)){
++ case SDCONFIG_GET_WP:
++ DBG_PRINT(SDDBG_TRACE, ("config GET_WP\n"));
++ *((SDCONFIG_WP_VALUE *)config->pData) = 0;
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ case SDCONFIG_SEND_INIT_CLOCKS:
++ DBG_PRINT(SDDBG_TRACE, ("config SEND_INIT_CLOCKS\n"));
++
++ /* We stop/start the clock */
++ con = readl(context->base + S3C2410_SDICON);
++
++ con &= ~S3C2410_SDICON_CLOCKTYPE;
++ writel(con, context->base + S3C2410_SDICON);
++
++ mdelay(100);
++
++ con |= S3C2410_SDICON_CLOCKTYPE;
++ writel(con, context->base + S3C2410_SDICON);
++
++ mdelay(100);
++
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ case SDCONFIG_SDIO_INT_CTRL:
++ printk("config SDIO_INT_CTRL\n");
++ DBG_PRINT(SDDBG_TRACE, ("config SDIO_INT_CTRL\n"));
++ int_data = GET_SDCONFIG_CMD_DATA(PSDCONFIG_SDIO_INT_CTRL_DATA, config);
++
++ if (int_data->SlotIRQEnable &
++ (IRQ_DETECT_1_BIT | IRQ_DETECT_4_BIT | IRQ_DETECT_MULTI_BLK) ) {
++ imsk = readl(context->base + S3C2440_SDIIMSK);
++
++ if (int_data->SlotIRQEnable) {
++ printk("SDIO_INT_CTRL enable IRQ\n");
++ DBG_PRINT(SDDBG_TRACE, ("SDIO_INT_CTRL enable IRQ\n"));
++ context->int_sdio = 1;
++ context->int_sdio_reported = 0;
++ imsk |= S3C2410_SDIIMSK_SDIOIRQ;
++ writel(imsk, context->base + S3C2440_SDIIMSK);
++ } else {
++ printk("SDIO_INT_CTRL disable IRQ\n");
++ DBG_PRINT(SDDBG_TRACE, ("SDIO_INT_CTRL disable IRQ\n"));
++ context->int_sdio = 0;
++ context->int_sdio_reported = 0;
++ imsk &= ~S3C2410_SDIIMSK_SDIOIRQ;
++ writel(imsk, context->base + S3C2440_SDIIMSK);
++ }
++ }
++
++ break;
++ case SDCONFIG_SDIO_REARM_INT:
++ printk("config SDIO_REARM_INT\n");
++ DBG_PRINT(SDDBG_TRACE, ("config SDIO_REARM_INT\n"));
++ context->int_sdio = 1;
++ context->int_sdio_reported = 0;
++ imsk = readl(context->base + S3C2440_SDIIMSK);
++ imsk |= S3C2410_SDIIMSK_SDIOIRQ;
++ writel(imsk, context->base + S3C2440_SDIIMSK);
++ dsta = readl(context->base + S3C2410_SDIDSTA);
++ if (dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
++ context->int_sdio_pending = 1;
++ }
++ break;
++ case SDCONFIG_FUNC_CHANGE_BUS_MODE:
++ case SDCONFIG_BUS_MODE_CTRL:
++ s3c24xx_hcd_set_bus_mode(context, (PSDCONFIG_BUS_MODE_DATA)(config->pData));
++ DBG_PRINT(SDDBG_TRACE, ("config BUS_MODE_CTRL\n"));
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ case SDCONFIG_POWER_CTRL:
++ DBG_PRINT(SDDBG_TRACE, ("config POWER_CTRL\n"));
++ status = SDIO_STATUS_SUCCESS;
++ break;
++ case SDCONFIG_GET_HCD_DEBUG:
++ DBG_PRINT(SDDBG_TRACE, ("config GET_HCD_DEBUG\n"));
++ break;
++ case SDCONFIG_SET_HCD_DEBUG:
++ DBG_PRINT(SDDBG_TRACE, ("config SET_HCD_DEBUG\n"));
++ break;
++ default:
++ /* invalid request */
++ DBG_PRINT(SDDBG_ERROR, ("%s() - unsupported command: 0x%X\n",
++ __FUNCTION__, GET_SDCONFIG_CMD(config)));
++ status = SDIO_STATUS_INVALID_PARAMETER;
++ }
++
++ return SDIOErrorToOSError(status);
++}
++
++static void dump_request(struct s3c24xx_hcd_context * context)
++{
++ if (context->hcd.pCurrentRequest != NULL) {
++ DBG_PRINT(SDDBG_ERROR, ("Current Request Command:%d, ARG:0x%8.8X flags: 0x%04x\n",
++ context->hcd.pCurrentRequest->Command, context->hcd.pCurrentRequest->Argument,
++ GET_SDREQ_RESP_TYPE(context->hcd.pCurrentRequest->Flags)));
++ if (IS_SDREQ_DATA_TRANS(context->hcd.pCurrentRequest->Flags)) {
++ DBG_PRINT(SDDBG_ERROR, ("Data %s, Blocks: %d, BlockLen:%d Remaining: %d \n",
++ IS_SDREQ_WRITE_DATA(context->hcd.pCurrentRequest->Flags) ? "WRITE":"READ",
++ context->hcd.pCurrentRequest->BlockCount,
++ context->hcd.pCurrentRequest->BlockLen,
++ context->hcd.pCurrentRequest->DataRemaining));
++ }
++ }
++}
++
++
++SDIO_STATUS s3c24xx_hcd_request(PSDHCD hcd)
++{
++ SDIO_STATUS status = SDIO_STATUS_PENDING;
++ PSDREQUEST req;
++ u32 cmdcon, imask;
++ unsigned long flags;
++ struct s3c24xx_hcd_context * context =
++ (struct s3c24xx_hcd_context *)hcd->pContext;
++
++// printk("######## %s() ############\n", __FUNCTION__);
++// dump_request(context);
++
++ req = GET_CURRENT_REQUEST(hcd);
++ DBG_ASSERT(req != NULL);
++
++ spin_lock_irqsave(&context->lock, flags);
++
++ /* Clear command, data and fifo status registers */
++ writel(0xFFFFFFFF, context->base + S3C2410_SDICMDSTAT);
++ writel(0xFFFFFFFF, context->base + S3C2410_SDIDSTA);
++ writel(0xFFFFFFFF, context->base + S3C2410_SDIFSTA);
++
++ /* Enabling irqs */
++ imask = S3C2410_SDIIMSK_READWAIT | S3C2410_SDIIMSK_SDIOIRQ;
++
++ cmdcon = readl(context->base + S3C2410_SDICMDCON);
++
++ switch (GET_SDREQ_RESP_TYPE(req->Flags)) {
++ case SDREQ_FLAGS_NO_RESP:
++ cmdcon &= ~S3C2410_SDICMDCON_WAITRSP;
++ context->complete = S3C24XX_HCD_NO_RESPONSE;
++ imask |= S3C2410_SDIIMSK_CMDSENT;
++ break;
++ case SDREQ_FLAGS_RESP_R1:
++ case SDREQ_FLAGS_RESP_R1B:
++ case SDREQ_FLAGS_RESP_R3:
++ case SDREQ_FLAGS_RESP_SDIO_R4:
++ case SDREQ_FLAGS_RESP_SDIO_R5:
++ case SDREQ_FLAGS_RESP_R6:
++ cmdcon &= ~S3C2410_SDICMDCON_LONGRSP;
++ cmdcon |= S3C2410_SDICMDCON_WAITRSP;
++ context->complete = S3C24XX_HCD_RESPONSE_SHORT;
++ imask |= S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_RESPONSEND
++ | S3C2410_SDIIMSK_CMDTIMEOUT | S3C2410_SDIIMSK_RESPONSECRC;
++ break;
++ case SDREQ_FLAGS_RESP_R2:
++ cmdcon |= S3C2410_SDICMDCON_LONGRSP;
++ cmdcon |= S3C2410_SDICMDCON_WAITRSP;
++ context->complete = S3C24XX_HCD_RESPONSE_LONG;
++ imask |= S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_RESPONSEND
++ | S3C2410_SDIIMSK_CMDTIMEOUT | S3C2410_SDIIMSK_RESPONSECRC;
++ break;
++
++ }
++
++ /* Check if there is a data part */
++ if (IS_SDREQ_DATA_TRANS(req->Flags) &&
++ !IS_SDREQ_WRITE_DATA(req->Flags)) {
++ /* Data read */
++ u32 dcon;
++
++ DBG_PRINT(SDDBG_DEBUG, ("Start data read, block count=%d, block size=%d\n",
++ req->BlockCount, req->BlockLen));
++
++ /* Setting timer */
++ writel(0x7fffff, context->base + S3C2410_SDITIMER);
++
++ /* Block size */
++ writel(req->BlockLen, context->base + S3C2410_SDIBSIZE);
++
++ /* Data configuration: receive after cmd, block mode*/
++ dcon = S3C2410_SDIDCON_RXAFTERCMD | S3C2410_SDIDCON_BLOCKMODE;
++ if (context->bus_width == 4)
++ dcon |= S3C2410_SDIDCON_WIDEBUS;
++
++ /* Number of blocks */
++ dcon |= (0xfff & req->BlockCount);
++
++ req->DataRemaining = req->BlockCount * req->BlockLen;
++
++ /* This is a read */
++ dcon |= S3C2410_SDIDCON_XFER_RXSTART;
++
++ /* Set data size, and start the transfer */
++ if (!(req->DataRemaining % 4)) {
++ context->data_size = 4;
++ dcon |= S3C2440_SDIDCON_DS_WORD;
++ } else if (!(req->DataRemaining % 2)) {
++ context->data_size = 2;
++ dcon |= S3C2440_SDIDCON_DS_HALFWORD;
++ } else {
++ context->data_size = 1;
++ dcon |= S3C2440_SDIDCON_DS_BYTE;
++ }
++ context->data_size = 1;
++ dcon |= S3C2440_SDIDCON_DS_BYTE;
++
++ dcon |= S3C2440_SDIDCON_DATSTART;
++
++ writel(dcon, context->base + S3C2410_SDIDCON);
++
++ imask |= S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST |
++ S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
++ S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
++
++ cmdcon |= S3C2410_SDICMDCON_WITHDATA;
++
++ context->complete = S3C24XX_HCD_DATA_READ;
++ } else if (IS_SDREQ_DATA_TRANS(req->Flags) &&
++ IS_SDREQ_WRITE_DATA(req->Flags)) {
++ /* Data write */
++ u32 dcon;
++
++ DBG_PRINT(SDDBG_DEBUG, ("Start data write, block count=%d, block size=%d\n",
++ req->BlockCount, req->BlockLen));
++
++ /* Setting timer */
++ writel(0x7fffff, context->base + S3C2410_SDITIMER);
++
++ /* Block size */
++ writel(req->BlockLen, context->base + S3C2410_SDIBSIZE);
++
++ /* Data configuration: receive after cmd, block mode*/
++ dcon = S3C2410_SDIDCON_TXAFTERRESP | S3C2410_SDIDCON_BLOCKMODE;
++ if (context->bus_width == 4)
++ dcon |= S3C2410_SDIDCON_WIDEBUS;
++
++ /* Number of blocks */
++ dcon |= (0xfff & req->BlockCount);
++
++ /* This is a write */
++ dcon |= S3C2410_SDIDCON_XFER_TXSTART;
++
++ req->DataRemaining = req->BlockCount * req->BlockLen;
++
++ /* Start data size, and start the transfer */
++ if (!(req->DataRemaining % 4)) {
++ context->data_size = 4;
++ dcon |= S3C2440_SDIDCON_DS_WORD;
++ } else if (!(req->DataRemaining % 2)) {
++ context->data_size = 2;
++ dcon |= S3C2440_SDIDCON_DS_HALFWORD;
++ } else {
++ context->data_size = 1;
++ dcon |= S3C2440_SDIDCON_DS_BYTE;
++ }
++ context->data_size = 1;
++ dcon |= S3C2440_SDIDCON_DS_BYTE;
++
++ dcon |= S3C2440_SDIDCON_DATSTART;
++
++ writel(dcon, context->base + S3C2410_SDIDCON);
++
++ imask |= S3C2410_SDIIMSK_TXFIFOHALF | S3C2410_SDIIMSK_TXFIFOEMPTY |
++ S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
++ S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
++
++ cmdcon |= S3C2410_SDICMDCON_WITHDATA;
++ context->complete = S3C24XX_HCD_DATA_WRITE;
++ } else {
++ cmdcon &= ~S3C2410_SDICMDCON_WITHDATA;
++ }
++
++ cmdcon |= req->Command & S3C2410_SDICMDCON_INDEX;
++ cmdcon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
++
++ req->Status = SDIO_STATUS_PENDING;
++
++ if (context->int_sdio)
++ imask |= S3C2410_SDIIMSK_SDIOIRQ;
++ context->int_mask = imask;
++ writel(imask, context->base + S3C2440_SDIIMSK);
++ writel(req->Argument, context->base + S3C2410_SDICMDARG);
++ writel(cmdcon, context->base + S3C2410_SDICMDCON);
++
++ spin_unlock_irqrestore(&context->lock, flags);
++
++ return status;
++}
++
++static int s3c24xx_hcd_initialize(struct s3c24xx_hcd_context * context)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++ u32 con, datacon;
++
++ /* Set multiplexing */
++ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
++ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
++ s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
++ s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
++
++ /* Reset the controller */
++// s3c24xx_hcd_reset(context);
++
++ con = readl(context->base + S3C2410_SDICON);
++ con |= S3C2410_SDICON_RWAITEN | S3C2410_SDICON_SDIOIRQ;
++ writel(con, context->base + S3C2410_SDICON);
++
++ datacon = readl(context->base + S3C2410_SDIDCON);
++ datacon |= S3C2410_SDIDCON_WIDEBUS;
++ writel(datacon, context->base + S3C2410_SDIDCON);
++
++ return SDIOErrorToOSError(status);
++}
++
++static int s3c24xx_hcd_hw_init(struct s3c24xx_hcd_context * context)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ printk("######## %s() ############\n", __FUNCTION__);
++
++ /* Clock */
++ context->device.clock = clk_get(NULL, "sdi");
++ if (IS_ERR(context->device.clock)) {
++ DBG_PRINT(SDDBG_ERROR, ("Couldn't get clock\n"));
++ status = PTR_ERR(context->device.clock);
++ context->device.clock = NULL;
++ return status;
++ }
++
++ status = clk_enable(context->device.clock);
++ if (SDIO_IS_ERROR(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("Couldn't get clock\n"));
++ return SDIOErrorToOSError(status);
++ }
++
++ context->device.max_clock_rate = clk_get_rate(context->device.clock);
++ context->device.actual_clock_rate = context->device.max_clock_rate;
++
++ /* I/O */
++ context->mem = request_mem_region(context->mem->start,
++ RESSIZE(context->mem), context->description);
++
++ if (!context->mem) {
++ DBG_PRINT(SDDBG_ERROR, ("Failed to request io memory region\n"));
++ status = -ENOENT;
++ goto out_disable_clock;
++ }
++
++ context->base = ioremap(context->mem->start, RESSIZE(context->mem));
++ if (context->base == 0) {
++ DBG_PRINT(SDDBG_ERROR, ("failed to ioremap() io memory region.\n"));
++ status = -EINVAL;
++ goto out_free_mem_region;
++ }
++
++ /* IRQ */
++#if 0
++ context->cd_irq = s3c2410_gpio_getirq(GTA02v1_GPIO_nSD_DETECT);
++ s3c2410_gpio_cfgpin(GTA02v1_GPIO_nSD_DETECT, S3C2410_GPIO_IRQ);
++
++ if (request_irq(context->cd_irq, s3c24xx_hcd_cd_irq, 0, context->description, context)) {
++ DBG_PRINT(SDDBG_ERROR, ("failed to request card detect interrupt.\n"));
++ status = -ENOENT;
++ goto out_unmap_mem_region;
++ }
++#endif
++
++ if (request_irq(context->io_irq, s3c24xx_hcd_irq, 0, context->description, context)) {
++ DBG_PRINT(SDDBG_ERROR, ("failed to request mci interrupt.\n"));
++ status = -ENOENT;
++ goto out_free_irq;
++ }
++
++
++ printk("S3c24xx SDIO: IRQ:%d Detect IRQ: %d base at 0x%p PCLK@%ld kHz\n",
++ context->io_irq, context->cd_irq, context->base, context->device.max_clock_rate/1000);
++
++ return SDIOErrorToOSError(status);
++
++ out_free_irq:
++// free_irq(context->cd_irq, context);
++// out_unmap_mem_region:
++ iounmap(context->base);
++
++ out_free_mem_region:
++ release_mem_region(context->mem->start, RESSIZE(context->mem));
++
++ out_disable_clock:
++ clk_disable(context->device.clock);
++
++ return SDIOErrorToOSError(status);
++}
++
++static void s3c24xx_hcd_hw_cleanup(struct s3c24xx_hcd_context * context)
++{
++ clk_disable(context->device.clock);
++ free_irq(context->io_irq, context);
++ iounmap(context->base);
++ release_mem_region(context->mem->start, RESSIZE(context->mem));
++}
++
++static int s3c24xx_hcd_probe(struct pnp_dev *pBusDevice, const struct pnp_device_id *pId)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ printk("######## %s() ############\n", __FUNCTION__);
++
++ hcd_context.io_irq = IRQ_SDI;
++ hcd_context.mem = &s3c24xx_hcd_mem;
++
++ spin_lock_init(&hcd_context.lock);
++
++ INIT_WORK (&hcd_context.pio_work, s3c24xx_hcd_pio_work);
++
++ hcd_context.int_sdio = 0;
++ hcd_context.int_sdio_reported = 0;
++ hcd_context.int_sdio_pending = 0;
++
++ status = s3c24xx_hcd_hw_init(&hcd_context);
++ if (SDIO_IS_ERROR(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("HW Init failed\n"));
++ return SDIOErrorToOSError(status);
++ }
++
++ status = s3c24xx_hcd_initialize(&hcd_context);
++ if (SDIO_IS_ERROR(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("HCD Initialisation failed\n"));
++ s3c24xx_hcd_hw_cleanup(&hcd_context);
++ return SDIOErrorToOSError(status);
++ }
++
++ status = SDIO_RegisterHostController(&hcd_context.hcd);
++ if (SDIO_IS_ERROR(status)) {
++ DBG_PRINT(SDDBG_ERROR, ("Host registration failed\n"));
++ s3c24xx_hcd_hw_cleanup(&hcd_context);
++ return SDIOErrorToOSError(status);
++ }
++
++ /* Our card is built-in, we force the attachement event */
++ SDIO_HandleHcdEvent(&hcd_context.hcd, EVENT_HCD_ATTACH);
++
++ return 0;
++}
++
++static void s3c24xx_hcd_remove(struct pnp_dev *pBusDevice)
++{
++}
++
++/* the driver context data */
++struct s3c24xx_hcd_context hcd_context = {
++ .description = DESCRIPTION,
++ .hcd.pName = "sdio_s3c24xx",
++ .hcd.Version = CT_SDIO_STACK_VERSION_CODE,
++ .hcd.pModule = THIS_MODULE,
++ /* builtin card, 4 bits bus */
++ .hcd.Attributes = SDHCD_ATTRIB_BUS_4BIT | SDHCD_ATTRIB_BUS_1BIT | SDHCD_ATTRIB_MULTI_BLK_IRQ,
++ .hcd.SlotNumber = 0,
++ .hcd.MaxSlotCurrent = 500, /* 1/2 amp */
++ .hcd.SlotVoltageCaps = SLOT_POWER_3_3V, /* 3.3V */
++ .hcd.SlotVoltagePreferred = SLOT_POWER_3_3V, /* 3.3V */
++ .hcd.MaxClockRate = 25000000,
++ .hcd.MaxBytesPerBlock = 0xfff, /* 0 - 4095 */
++ .hcd.MaxBlocksPerTrans = 0xfff, /* 0 - 4095 */
++ .hcd.pContext = &hcd_context,
++ .hcd.pRequest = s3c24xx_hcd_request,
++ .hcd.pConfigure = s3c24xx_hcd_config,
++ .device.pnp_device.name = "sdio_s3c24xx_hcd",
++ .device.pnp_driver.name = "sdio_s3c24xx_hcd",
++ .device.pnp_driver.probe = s3c24xx_hcd_probe,
++ .device.pnp_driver.remove = s3c24xx_hcd_remove,
++};
++
++
++static int __init s3c24xx_hcd_init(void)
++{
++ SDIO_STATUS status = SDIO_STATUS_SUCCESS;
++
++ printk("######## %s() ############\n", __FUNCTION__);
++
++ REL_PRINT(SDDBG_TRACE, ("SDIO S3C24xx started\n"));
++
++ status = SDIO_BusAddOSDevice(&hcd_context.device.dma,
++ &hcd_context.device.pnp_driver,
++ &hcd_context.device.pnp_device);
++
++ return SDIOErrorToOSError(status);
++}
++
++/*
++ * module cleanup
++*/
++static void __exit s3c24xx_hcd_cleanup(void) {
++ REL_PRINT(SDDBG_TRACE, ("+SDIO S3C24xx unloaded\n"));
++ SDIO_BusRemoveOSDevice(&hcd_context.device.pnp_driver, &hcd_context.device.pnp_device);
++}
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++module_init(s3c24xx_hcd_init);
++module_exit(s3c24xx_hcd_cleanup);
+Index: linux-2.6.22/drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.22/drivers/sdio/hcd/s3c24xx/s3c24xx_hcd.h 2007-11-22 22:01:57.000000000 +0100
+@@ -0,0 +1,50 @@
++#ifndef __SDIO_S3C24XX_HCD_H___
++#define __SDIO_S3C24XX_HCD_H___
++
++#define S3C24XX_HCD_NO_RESPONSE 1
++#define S3C24XX_HCD_RESPONSE_SHORT 2
++#define S3C24XX_HCD_RESPONSE_LONG 3
++#define S3C24XX_HCD_DATA_READ 4
++#define S3C24XX_HCD_DATA_WRITE 5
++
++struct s3c24xx_hcd_device {
++ OS_PNPDEVICE pnp_device; /* the OS device for this HCD */
++ OS_PNPDRIVER pnp_driver; /* the OS driver for this HCD */
++ SDDMA_DESCRIPTION dma;
++ struct clk * clock;
++ unsigned long max_clock_rate;
++ unsigned long actual_clock_rate;
++};
++
++
++/* driver wide data, this driver only supports one device,
++ * so we include the per device data here also */
++struct s3c24xx_hcd_context {
++ PTEXT description; /* human readable device decsription */
++ SDHCD hcd; /* HCD description for bus driver */
++ struct s3c24xx_hcd_device device; /* the single device's info */
++ struct resource *mem;
++ void __iomem *base;
++ UINT32 io_irq;
++ UINT32 cd_irq;
++ BOOL card_inserted; /* card inserted flag */
++ BOOL cmd_processed; /* command phase was processed */
++ UINT32 fifo_depth; /* FIFO depth for the bus mode */
++ BOOL irq_masked;
++ UINT32 bus_width;
++ UINT32 data_size; /* Word, half word, or byte */
++ UINT32 int_mask;
++ UINT32 int_sdio; /* Do we have SDIO interrupt on ? */
++ UINT32 int_sdio_reported;
++ UINT32 int_sdio_pending;
++ UINT32 complete;
++ spinlock_t lock;
++ struct work_struct pio_work;
++};
++
++SDIO_STATUS s3c24xx_hcd_config(PSDHCD hcd, PSDCONFIG config);
++SDIO_STATUS s3c24xx_hcd_request(PSDHCD hcd);
++
++struct s3c24xx_hcd_context hcd_context;
++
++#endif
Added: developers/sameo/patches/ar6k-atheros/series
===================================================================
--- developers/sameo/patches/ar6k-atheros/series 2007-11-26 09:11:57 UTC (rev 3510)
+++ developers/sameo/patches/ar6k-atheros/series 2007-11-26 14:17:02 UTC (rev 3511)
@@ -0,0 +1,7 @@
+common_atheros_sdiostack.patch
+common_atheros_sdiostack_functions.patch
+common_atheros_sdiostack_shcd.patch
+common_atheros_sdiostack_ar6000_wlan.patch
+pnp_fixes_2.6.22.5.patch
+s3c2440_wlan_gpio_cfg.patch
+s3c24xx_hcd_atheros.patch
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