Unable to set 32 bit software breakpoint

[Shakthi Kannan]

Hi,

I have done 'reset halt' and 'arm7_9 sw_bkpts enable' from openocd for
debug board v3 and FR. I have flashed the built u-boot to NAND.
Proceeding to use gdb:

/usr/local/openmoko/arm/bin/arm-angstrom-linux-gnueabi-gdb
(gdb) file /path/to/u-boot

  Reading symbols from /path/to/u-boot...done.

(gdb) target remote localhost:3333

  Remote debugging using localhost:3333
  0x00000000 in ?? ()

(gdb) load

  Loading section .text, size 0x2658c lma 0x33f80000
  Loading section .rodata, size 0xf60 lma 0x33fa658c
  Loading section .rodata.str1.4, size 0x9240 lma 0x33fa74ec
  Loading section .data, size 0x4070 lma 0x33fb072c
  Loading section .u_boot_cmd, size 0x6d8 lma 0x33fb479c
  Start address 0x33f80000, load size 216692
  Transfer rate: 217099 bits/sec, 12746 bytes/write.

At this point, I am able to set breakpoints:

(gdb) b cpu_init

  Breakpoint 1 at 0x33f81fa4: file cpu.c, line 99.

Doing 'info registers' shows pc at 0x33f80000:

(gdb) info registers
  ...
  pc             0x33f80000	0x33f80000 <_start>
  fps            0x0	0
  cpsr           0x200000d3	536871123

But, when I do "stepi", I get:

  Unable to set 32 bit software breakpoint at address 33f80000
  Unable to set 32 bit software breakpoint at address 33f810c4
  Unable to set 32 bit software breakpoint at address 33a3abb0
  target state: halted
  target halted in ARM state due to breakpoint, current mode: Supervisor
  cpsr: 0x200000d3 pc: 0x00000000
  MMU: disabled, D-Cache: disabled, I-Cache: disabled

The u-boot offset address that is built starts from 0x33f80000, which
is in nCS6 - RAM. How can I debug the u-boot on the NAND?

My libftdi1 is 0.13-2 on Debian. Appreciate any inputs,

Thanks!

SK

-- 
Shakthi Kannan
http://www.shakthimaan.com