WLAN from SDIO to SPI: battle plan

[dennis.yxun]

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HI Werner:
  I've been interested in your hardware SPI (with DMA enable).
  Conclude from your previous discussion, it's the Hardware
issue (signal integrity?).
  I write a very simple test code in u-boot. My first step is
trying to make SPI controller working, so i choose POLL mode.
Problem, I encounter here is that SPSTA0 transfer ready bit always 0(
not ready). One thing i have to mention, there is no slave SPI
device, and i thought it should be ok just to test the S3C2442 SPI
controller.

   If you are kind to spend a few minutes to review my code,
and give me some suggestions. will be great.

   here is few steps i made in my code.
   1. enbale SPI clock
   2. set SPI pin to function mode.(CLK, MISO, MOSI, CS(GPF3),
      should set nSS0 to function mode?
   3. config SPI controller, baudrate, SPCON0,


Werner Almesberger wrote:
> I wrote:
>> To be continued ...
> 
> After getting nowhere with trying to talk to the prototype board, and
> seeing no end of those short pulses on MISO (*), I decided that my
> suspicion that poor signal integrity was to blame even at this
> moderate clock speed was probably more than a convenient excuse.
> 
> (*) Here's a beautiful one. D5 is the clock, D2 is MISO:
>     http://people.openmoko.org/werner/wlan-spi/3.png
> 
> Then it occurred to me that I could just as well use the WLAN module
> that's already in the device: after turning off the SDIO driver,
> switching to mmc_spi over s3c24xx_spi_gpio, and adapting all the GPIO
> definitions, the mainline SDIO stack happily welcomed the new member
> with SDIO_ID=0271:010A :-)
> 
> I'll just go ahead with s3c24xx_spi_gpio for now, then rework and
> switch to s3c24xx_spi when the Atheros stack talks to the module as
> well.
> 
> I'll give "pure" SPI (G_SPI) a try when the EVB arrives.
> 
> To be continued ...
> 
> - Werner
> 
> 

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