WLAN from SDIO to SPI: battle plan

[dennis.yxun]

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HI Werner:
  Thank you for your reply, really appreciate!

  I find why i can't make SPI run successfully but can't explain myself,
seems it's the GCC compiler's problem.


  I've tried your code. It can run successfully.
So.. I go back to my code, as you mentioned the TAGD bit
("Tx Auto garbage") and also see you mask off SPI interrupt.
So I try to do the same, but unfortunately it still stalled at
transfer data step.wait for "REDY bit == 1".
  It puzzled me.. So I use the jtag to peep into it. Quite odd,
i find if using my previous patch, after running s3c24xx_spi_init
function, i will fail at initialize SPCON, SPPRE, SPPIN register,
 values are all 0.
  I try to disassemble the code, find the second "strb" instruction
should be blame to. see line 0x33f82b24 change 0x5900000c to 0x00.


33f82b14:   e59d2004    ldr r2, [sp, #4]                // r2 = 0x59000000
33f82b18:   e3a01000    mov r1, #0  ; 0x0               // r0 = 0
33f82b1c:   e3a0304f    mov r3, #79 ; 0x4f              // r3 = 0x4f
33f82b20:   e5c2300c    strb    r3, [r2, #12]    // 0x5900000c = 0x4f
33f82b24:   e5c2100f    strb    r1, [r2, #15]    //0x5900000c= 0x00!,god
33f82b28:   e5c2100d    strb    r1, [r2, #13]
33f82b2c:   e5c2100e    strb    r1, [r2, #14]
33f82b30:   e59d3004    ldr r3, [sp, #4]                // r3 = 0x59000000
33f82b34:   e3a02001    mov r2, #1  ; 0x1               // r2 = 0x1
33f82b38:   e5c32008    strb    r2, [r3, #8]      // 0x59000008 = 0x01
33f82b3c:   e5c3100b    strb    r1, [r3, #11]     // 0x59000008 = 0x00 !
33f82b40:   e5c31009    strb    r1, [r3, #9]
33f82b44:   e5c3100a    strb    r1, [r3, #10]
33f82b48:   e59d3004    ldr r3, [sp, #4]
33f82b4c:   e282201e    add r2, r2, #30 ; 0x1e
33f82b50:   e5c32000    strb    r2, [r3]


    but if i use code like this ( *(unsigned int *) 0x59000000 = 0x1f;)
then will be no problem.
    I've try to disassemble the code. and it use "str" instruction.

33f82b04:   e5823040    str r3, [r2, #64]
33f82b08:   e5923054    ldr r3, [r2, #84]
33f82b0c:   e3833008    orr r3, r3, #8  ; 0x8
33f82b10:   e5823054    str r3, [r2, #84]	
33f82b14:   e3a0304f    mov r3, #79 ; 0x4f
33f82b18:   e584300c    str r3, [r4, #12]       // here
33f82b1c:   e3a0301f    mov r3, #31 ; 0x1f
33f82b20:   e5843000    str r3, [r4]		// here
33f82b24:   e3a03001    mov r3, #1  ; 0x1
33f82b28:   e5843008    str r3, [r4, #8]	// here
33f82b2c:   e3a00000    mov r0, #0  ; 0x0
33f82b30:   e59d1004    ldr r1, [sp, #4]

   And i find it's nothing to do with "TAGD" bit or SPI interrupt mask bit.
   Next i will try to test SPI DMA.

Werner Almesberger wrote:
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