[PATCH] fix-lis302dl-isr-lock.patch

[joerg]

Am Mo  31. März 2008 schrieb Andy Green:
> (they share an SPI bus tho :-O ).
they do?

> 
> I suspect we have some other problem where edges can get missed by the
> CPU 

So why don't we use level here? 
I think edge is useful just for things like realtime clock / vsync etc (simply 
spoken periodic signals), where there just isn't any latch to be reset and we 
want to avoid level triggers out of sync of clock time frame when enabling 
CPU (level)interrupt while on IRQ-line the square wave of clock incidentally 
is at active level (God, sorry for this sentence).

In short: use edge if ISR must occur only on a certain point in time (i.e 
edge) and must not at all be processed later than triggering edge - 
the "better miss than delay" situation.
Use level, when ISR may start delayed, but *must* reset IRQ latch eventually.
A latch simply implies level mode. That's what it's in for.

jOERG