[PATCH 1/8] qi-add-missed-files-for-scm.patch

Andy Green andy at openmoko.com
Tue Oct 21 12:42:05 CEST 2008


Moved several files and they didn't get added to git

Signed-off-by: Andy Green <andy at openmoko.com>
---

 include/neo_tla01.h         |   28 +
 include/s3c6410.h           | 1430 +++++++++++++++++++++++++++++++++++++++++++
 src/cpu/s3c2442/gta02.c     |  428 +++++++++++++
 src/cpu/s3c2442/gta03.c     |  289 +++++++++
 src/cpu/s3c2442/nand_read.c |  153 +++++
 src/cpu/s3c2442/nand_read.h |   22 +
 src/cpu/s3c2442/qi.lds      |   60 ++
 src/cpu/s3c2442/start.S     |  311 +++++++++
 src/cpu/s3c2442/start_qi.c  |  106 +++
 src/cpu/s3c6410/qi.lds      |   57 ++
 src/cpu/s3c6410/start.S     |  548 ++++++++++++++++
 src/cpu/s3c6410/start_qi.c  |  105 +++
 src/cpu/s3c6410/tla01.c     |  246 +++++++
 13 files changed, 3783 insertions(+), 0 deletions(-)
 create mode 100644 include/neo_tla01.h
 create mode 100644 include/s3c6410.h
 create mode 100644 src/cpu/s3c2442/gta02.c
 create mode 100644 src/cpu/s3c2442/gta03.c
 create mode 100644 src/cpu/s3c2442/nand_read.c
 create mode 100644 src/cpu/s3c2442/nand_read.h
 create mode 100644 src/cpu/s3c2442/qi.lds
 create mode 100644 src/cpu/s3c2442/start.S
 create mode 100644 src/cpu/s3c2442/start_qi.c
 create mode 100644 src/cpu/s3c6410/qi.lds
 create mode 100644 src/cpu/s3c6410/start.S
 create mode 100644 src/cpu/s3c6410/start_qi.c
 create mode 100644 src/cpu/s3c6410/tla01.c

diff --git a/include/neo_tla01.h b/include/neo_tla01.h
new file mode 100644
index 0000000..6d9ca72
--- /dev/null
+++ b/include/neo_tla01.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: xiangfu liu <xiangfu at openmoko.org>
+ *
+ * Configuation settings for the FIC Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_MODE__
+#include <qi.h>
+extern const struct board_api board_api_tla01;
+#endif
+
+#define TEXT_BASE_TLA01 0x53000000
diff --git a/include/s3c6410.h b/include/s3c6410.h
new file mode 100644
index 0000000..d0b9dd6
--- /dev/null
+++ b/include/s3c6410.h
@@ -0,0 +1,1430 @@
+/*
+ * (C) Copyright 2007
+ * Byungjae Lee, Samsung Erectronics, bjlee at samsung.com.
+ *      - only support for S3C6400
+ *  $Id: s3c6410.h,v 1.6 2008/07/02 11:01:48 jsgood Exp $
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c6400.h
+ *
+ * Based on S3C6400 User's manual Rev 0.0
+ ************************************************/
+
+#ifndef __S3C6410_H__
+#define __S3C6410_H__
+
+#ifndef CONFIG_S3C6410
+#define CONFIG_S3C6410		1
+#endif
+
+#define S3C64XX_UART_CHANNELS	3
+#define S3C64XX_SPI_CHANNELS	2
+
+//#include <asm/hardware.h>
+
+#ifndef __ASSEMBLY__
+typedef enum {
+	S3C64XX_UART0,
+	S3C64XX_UART1,
+	S3C64XX_UART2,
+} S3C64XX_UARTS_NR;
+
+//#include <s3c64x0.h>
+#endif
+
+#define BIT0 			0x00000001
+#define BIT1 			0x00000002
+#define BIT2 			0x00000004
+#define BIT3 			0x00000008
+#define BIT4 			0x00000010
+#define BIT5 			0x00000020
+#define BIT6			0x00000040
+#define BIT7			0x00000080
+#define BIT8			0x00000100
+#define BIT9			0x00000200
+#define BIT10			0x00000400
+#define BIT11			0x00000800
+#define BIT12			0x00001000
+#define BIT13			0x00002000
+#define BIT14			0x00004000
+#define BIT15			0x00008000
+#define BIT16			0x00010000
+#define BIT17			0x00020000
+#define BIT18			0x00040000
+#define BIT19			0x00080000
+#define BIT20			0x00100000
+#define BIT21			0x00200000
+#define BIT22			0x00400000
+#define BIT23			0x00800000
+#define BIT24			0x01000000
+#define BIT25			0x02000000
+#define BIT26			0x04000000
+#define BIT27			0x08000000
+#define BIT28			0x10000000
+#define BIT29			0x20000000
+#define BIT30			0x40000000
+#define BIT31			0x80000000
+
+#define ROM_BASE0		0x00000000      /* base address of rom bank 0 */
+#define ROM_BASE1		0x04000000      /* base address of rom bank 1 */
+#define DRAM_BASE0		0x40000000      /* base address of dram bank 0 */
+#define DRAM_BASE1		0x50000000      /* base address of dram bank 1 */
+
+
+/* S3C6400 device base addresses */
+#define ELFIN_DMA_BASE		0x75000000
+#define ELFIN_LCD_BASE		0x77100000
+#define ELFIN_USB_HOST_BASE	0x74300000
+#define ELFIN_I2C_BASE		0x7f004000
+#define ELFIN_I2S_BASE		0x7f002000
+#define ELFIN_ADC_BASE		0x7e00b000
+#define ELFIN_SPI_BASE		0x7f00b000
+#define ELFIN_HSMMC_0_BASE	0x7c200000
+#define ELFIN_HSMMC_1_BASE	0x7c300000
+#define ELFIN_HSMMC_2_BASE	0x7c400000
+
+#define ELFIN_CLOCK_POWER_BASE	0x7e00f000
+
+/* Clock & Power Controller for mDirac3*/
+#define APLL_LOCK_OFFSET	0x00
+#define MPLL_LOCK_OFFSET	0x04
+#define EPLL_LOCK_OFFSET	0x08
+#define APLL_CON_OFFSET		0x0C
+#define MPLL_CON_OFFSET		0x10
+#define EPLL_CON0_OFFSET	0x14
+#define EPLL_CON1_OFFSET	0x18
+#define CLK_SRC_OFFSET		0x1C
+#define CLK_DIV0_OFFSET		0x20
+#define CLK_DIV1_OFFSET		0x24
+#define CLK_DIV2_OFFSET		0x28
+#define CLK_OUT_OFFSET		0x2C
+#define HCLK_GATE_OFFSET	0x30
+#define PCLK_GATE_OFFSET	0x34
+#define SCLK_GATE_OFFSET	0x38
+#define AHB_CON0_OFFSET		0x100
+#define AHB_CON1_OFFSET		0x104
+#define AHB_CON2_OFFSET		0x108
+#define SELECT_DMA_OFFSET	0x110
+#define SW_RST_OFFSET		0x114
+#define SYS_ID_OFFSET		0x118
+#define MEM_SYS_CFG_OFFSET	0x120
+#define QOS_OVERRIDE0_OFFSET	0x124
+#define QOS_OVERRIDE1_OFFSET	0x128
+#define MEM_CFG_STAT_OFFSET	0x12C
+#define PWR_CFG_OFFSET		0x804
+#define EINT_MASK_OFFSET	0x808
+#define NOR_CFG_OFFSET		0x810
+#define STOP_CFG_OFFSET		0x814
+#define SLEEP_CFG_OFFSET	0x818
+#define OSC_FREQ_OFFSET		0x820
+#define OSC_STABLE_OFFSET	0x824
+#define PWR_STABLE_OFFSET	0x828
+#define FPC_STABLE_OFFSET	0x82C
+#define MTC_STABLE_OFFSET	0x830
+#define OTHERS_OFFSET		0x900
+#define RST_STAT_OFFSET		0x904
+#define WAKEUP_STAT_OFFSET	0x908
+#define BLK_PWR_STAT_OFFSET	0x90C
+#define INF_REG0_OFFSET		0xA00
+#define INF_REG1_OFFSET		0xA04
+#define INF_REG2_OFFSET		0xA08
+#define INF_REG3_OFFSET		0xA0C
+#define INF_REG4_OFFSET		0xA10
+#define INF_REG5_OFFSET		0xA14
+#define INF_REG6_OFFSET		0xA18
+#define INF_REG7_OFFSET		0xA1C
+
+#define OSC_CNT_VAL_OFFSET	0x824
+#define PWR_CNT_VAL_OFFSET	0x828
+#define FPC_CNT_VAL_OFFSET	0x82C
+#define MTC_CNT_VAL_OFFSET	0x830
+
+
+#define APLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET)
+#define MPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET)
+#define EPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET)
+#define APLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET)
+#define MPLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET)
+#define EPLL_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET)
+#define EPLL_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET)
+#define CLK_SRC_REG		__REG(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET)
+#define CLK_DIV0_REG		__REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET)
+#define CLK_DIV1_REG		__REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET)
+#define CLK_DIV2_REG		__REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET)
+#define CLK_OUT_REG		__REG(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET)
+#define HCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET)
+#define PCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET)
+#define SCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET)
+#define AHB_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET)
+#define AHB_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET)
+#define AHB_CON2_REG		__REG(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET)
+#define SELECT_DMA_REG		__REG(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET)
+#define SW_RST_REG		__REG(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET)
+#define SYS_ID_REG		__REG(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET)
+#define MEM_SYS_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0_REG	__REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1_REG	__REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET)
+#define PWR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
+#define EINT_MASK_REG		__REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET)
+#define NOR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
+#define STOP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
+#define SLEEP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
+#define OSC_FREQ_REG		__REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET)
+#define OTHERS_REG		__REG(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET)
+#define RST_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
+#define WAKEUP_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET)
+#define INF_REG0_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
+#define INF_REG1_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET)
+#define INF_REG2_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET)
+#define INF_REG3_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET)
+#define INF_REG4_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET)
+#define INF_REG5_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET)
+#define INF_REG6_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET)
+#define INF_REG7_REG		__REG(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET)
+
+#define APLL_LOCK	(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET)
+#define MPLL_LOCK	(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET)
+#define EPLL_LOCK	(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET)
+#define APLL_CON	(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET)
+#define MPLL_CON	(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET)
+#define EPLL_CON0	(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET)
+#define EPLL_CON1	(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET)
+#define CLK_SRC		(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET)
+#define CLK_DIV0	(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET)
+#define CLK_DIV1	(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET)
+#define CLK_DIV2	(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET)
+#define CLK_OUT		(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET)
+#define HCLK_GATE	(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET)
+#define PCLK_GATE	(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET)
+#define SCLK_GATE	(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET)
+#define AHB_CON0	(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET)
+#define AHB_CON1	(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET)
+#define AHB_CON2	(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET)
+#define SELECT_DMA	(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET)
+#define SW_RST		(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET)
+#define SYS_ID		(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET)
+#define MEM_SYS_CFG	(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET)
+#define QOS_OVERRIDE0	(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET)
+#define QOS_OVERRIDE1	(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET)
+#define MEM_CFG_STAT	(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET)
+#define PWR_CFG		(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
+#define EINT_MASK	(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET)
+#define NOR_CFG		(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
+#define STOP_CFG	(ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
+#define SLEEP_CFG	(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
+#define OSC_FREQ	(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
+#define OSC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
+#define PWR_CNT_VAL	(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET)
+#define FPC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET)
+#define MTC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET)
+#define OTHERS		(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET)
+#define RST_STAT	(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
+#define WAKEUP_STAT	(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
+#define BLK_PWR_STAT	(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET)
+#define INF_REG0	(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
+#define INF_REG1	(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET)
+#define INF_REG2	(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET)
+#define INF_REG3	(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET)
+#define INF_REG4	(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET)
+#define INF_REG5	(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET)
+#define INF_REG6	(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET)
+#define INF_REG7	(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET)
+
+
+/*
+ * GPIO
+ */
+#define ELFIN_GPIO_BASE		0x7f008000
+
+#define GPACON_OFFSET		0x00
+#define GPADAT_OFFSET		0x04
+#define GPAPUD_OFFSET		0x08
+#define GPACONSLP_OFFSET	0x0C
+#define GPAPUDSLP_OFFSET	0x10
+#define GPBCON_OFFSET		0x20
+#define GPBDAT_OFFSET		0x04
+#define GPBPUD_OFFSET		0x08
+#define GPBCONSLP_OFFSET	0x0C
+#define GPBPUDSLP_OFFSET	0x30
+#define GPCCON_OFFSET		0x40
+#define GPCDAT_OFFSET		0x44
+#define GPCPUD_OFFSET		0x48
+#define GPCCONSLP_OFFSET	0x4C
+#define GPCPUDSLP_OFFSET	0x50
+#define GPDCON_OFFSET		0x60
+#define GPDDAT_OFFSET		0x64
+#define GPDPUD_OFFSET		0x68
+#define GPDCONSLP_OFFSET	0x6C
+#define GPDPUDSLP_OFFSET	0x70
+#define GPECON_OFFSET		0x80
+#define GPEDAT_OFFSET		0x84
+#define GPEPUD_OFFSET		0x88
+#define GPECONSLP_OFFSET	0x8C
+#define GPEPUDSLP_OFFSET	0x90
+#define GPFCON_OFFSET		0xA0
+#define GPFDAT_OFFSET		0xA4
+#define GPFPUD_OFFSET		0xA8
+#define GPFCONSLP_OFFSET	0xAC
+#define GPFPUDSLP_OFFSET	0xB0
+#define GPGCON_OFFSET		0xC0
+#define GPGDAT_OFFSET		0xC4
+#define GPGPUD_OFFSET		0xC8
+#define GPGCONSLP_OFFSET	0xCC
+#define GPGPUDSLP_OFFSET	0xD0
+#define GPHCON0_OFFSET		0xE0
+#define GPHCON1_OFFSET		0xE4
+#define GPHDAT_OFFSET		0xE8
+#define GPHPUD_OFFSET		0xEC
+#define GPHCONSLP_OFFSET	0xF0
+#define GPHPUDSLP_OFFSET	0xF4
+#define GPICON_OFFSET		0x100
+#define GPIDAT_OFFSET		0x104
+#define GPIPUD_OFFSET		0x108
+#define GPICONSLP_OFFSET	0x10C
+#define GPIPUDSLP_OFFSET	0x110
+#define GPJCON_OFFSET		0x120
+#define GPJDAT_OFFSET		0x124
+#define GPJPUD_OFFSET		0x128
+#define GPJCONSLP_OFFSET	0x12C
+#define GPJPUDSLP_OFFSET	0x130
+#define SPCON_OFFSET		0x1A0
+#define MEM0DRVCON_OFFSET	0x1D0
+#define MEM1DRVCON_OFFSET	0x1D4
+#define GPKCON0_OFFSET		0x800
+#define GPKCON1_OFFSET		0x804
+#define GPKDAT_OFFSET		0x808
+#define GPKPUD_OFFSET		0x80C
+#define GPLCON0_OFFSET		0x810
+#define GPLCON1_OFFSET		0x814
+#define GPLDAT_OFFSET		0x818
+#define GPLPUD_OFFSET		0x81C
+#define GPMCON_OFFSET		0x820
+#define GPMDAT_OFFSET		0x824
+#define GPMPUD_OFFSET		0x828
+#define GPNCON_OFFSET		0x830
+#define GPNDAT_OFFSET		0x834
+#define GPNPUD_OFFSET		0x838
+#define GPOCON_OFFSET		0x140
+#define GPODAT_OFFSET		0x144
+#define GPOPUD_OFFSET		0x148
+#define GPOCONSLP_OFFSET	0x14C
+#define GPOPUDSLP_OFFSET	0x150
+#define GPPCON_OFFSET		0x160
+#define GPPDAT_OFFSET		0x164
+#define GPPPUD_OFFSET		0x168
+#define GPPCONSLP_OFFSET	0x16C
+#define GPPPUDSLP_OFFSET	0x170
+#define GPQCON_OFFSET		0x180
+#define GPQDAT_OFFSET		0x184
+#define GPQPUD_OFFSET		0x188
+#define GPQCONSLP_OFFSET	0x18C
+#define GPQPUDSLP_OFFSET	0x190
+
+#define EINTPEND_OFFSET		0x924
+
+#define GPACON_REG		__REG(ELFIN_GPIO_BASE+GPACON_OFFSET)
+#define GPADAT_REG		__REG(ELFIN_GPIO_BASE+GPADAT_OFFSET)
+#define GPAPUD_REG		__REG(ELFIN_GPIO_BASE+GPAPUD_OFFSET)
+#define GPACONSLP_REG		__REG(ELFIN_GPIO_BASE+GPACONSLP_OFFSET)
+#define GPAPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET)
+#define GPBCON_REG		__REG(ELFIN_GPIO_BASE+GPBCON_OFFSET)
+#define GPBDAT_REG		__REG(ELFIN_GPIO_BASE+GPBDAT_OFFSET)
+#define GPBPUD_REG		__REG(ELFIN_GPIO_BASE+GPBPUD_OFFSET)
+#define GPBCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPBCONSLP_OFFSET)
+#define GPBPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET)
+#define GPCCON_REG		__REG(ELFIN_GPIO_BASE+GPCCON_OFFSET)
+#define GPCDAT_REG		__REG(ELFIN_GPIO_BASE+GPCDAT_OFFSET)
+#define GPCPUD_REG		__REG(ELFIN_GPIO_BASE+GPCPUD_OFFSET)
+#define GPCCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPCCONSLP_OFFSET)
+#define GPCPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET)
+#define GPDCON_REG		__REG(ELFIN_GPIO_BASE+GPDCON_OFFSET)
+#define GPDDAT_REG		__REG(ELFIN_GPIO_BASE+GPDDAT_OFFSET)
+#define GPDPUD_REG		__REG(ELFIN_GPIO_BASE+GPDPUD_OFFSET)
+#define GPDCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPDCONSLP_OFFSET)
+#define GPDPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET)
+#define GPECON_REG		__REG(ELFIN_GPIO_BASE+GPECON_OFFSET)
+#define GPEDAT_REG		__REG(ELFIN_GPIO_BASE+GPEDAT_OFFSET)
+#define GPEPUD_REG		__REG(ELFIN_GPIO_BASE+GPEPUD_OFFSET)
+#define GPECONSLP_REG		__REG(ELFIN_GPIO_BASE+GPECONSLP_OFFSET)
+#define GPEPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET)
+#define GPFCON_REG		__REG(ELFIN_GPIO_BASE+GPFCON_OFFSET)
+#define GPFDAT_REG		__REG(ELFIN_GPIO_BASE+GPFDAT_OFFSET)
+#define GPFPUD_REG		__REG(ELFIN_GPIO_BASE+GPFPUD_OFFSET)
+#define GPFCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPFCONSLP_OFFSET)
+#define GPFPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET)
+#define GPGCON_REG		__REG(ELFIN_GPIO_BASE+GPGCON_OFFSET)
+#define GPGDAT_REG		__REG(ELFIN_GPIO_BASE+GPGDAT_OFFSET)
+#define GPGPUD_REG		__REG(ELFIN_GPIO_BASE+GPGPUD_OFFSET)
+#define GPGCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPGCONSLP_OFFSET)
+#define GPGPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET)
+#define GPHCON0_REG		__REG(ELFIN_GPIO_BASE+GPHCON0_OFFSET)
+#define GPHCON1_REG		__REG(ELFIN_GPIO_BASE+GPHCON1_OFFSET)
+#define GPHDAT_REG		__REG(ELFIN_GPIO_BASE+GPHDAT_OFFSET)
+#define GPHPUD_REG		__REG(ELFIN_GPIO_BASE+GPHPUD_OFFSET)
+#define GPHCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPHCONSLP_OFFSET)
+#define GPHPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET)
+#define GPICON_REG		__REG(ELFIN_GPIO_BASE+GPICON_OFFSET)
+#define GPIDAT_REG		__REG(ELFIN_GPIO_BASE+GPIDAT_OFFSET)
+#define GPIPUD_REG		__REG(ELFIN_GPIO_BASE+GPIPUD_OFFSET)
+#define GPICONSLP_REG		__REG(ELFIN_GPIO_BASE+GPICONSLP_OFFSET)
+#define GPIPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET)
+#define GPJCON_REG		__REG(ELFIN_GPIO_BASE+GPJCON_OFFSET)
+#define GPJDAT_REG		__REG(ELFIN_GPIO_BASE+GPJDAT_OFFSET)
+#define GPJPUD_REG		__REG(ELFIN_GPIO_BASE+GPJPUD_OFFSET)
+#define GPJCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPJCONSLP_OFFSET)
+#define GPJPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET)
+#define GPKCON0_REG		__REG(ELFIN_GPIO_BASE+GPKCON0_OFFSET)
+#define GPKCON1_REG		__REG(ELFIN_GPIO_BASE+GPKCON1_OFFSET)
+#define GPKDAT_REG		__REG(ELFIN_GPIO_BASE+GPKDAT_OFFSET)
+#define GPKPUD_REG		__REG(ELFIN_GPIO_BASE+GPKPUD_OFFSET)
+#define GPLCON0_REG		__REG(ELFIN_GPIO_BASE+GPLCON0_OFFSET)
+#define GPLCON1_REG		__REG(ELFIN_GPIO_BASE+GPLCON1_OFFSET)
+#define GPLDAT_REG		__REG(ELFIN_GPIO_BASE+GPLDAT_OFFSET)
+#define GPLPUD_REG		__REG(ELFIN_GPIO_BASE+GPLPUD_OFFSET)
+#define GPMCON_REG		__REG(ELFIN_GPIO_BASE+GPMCON_OFFSET)
+#define GPMDAT_REG		__REG(ELFIN_GPIO_BASE+GPMDAT_OFFSET)
+#define GPMPUD_REG		__REG(ELFIN_GPIO_BASE+GPMPUD_OFFSET)
+#define GPNCON_REG		__REG(ELFIN_GPIO_BASE+GPNCON_OFFSET)
+#define GPNDAT_REG		__REG(ELFIN_GPIO_BASE+GPNDAT_OFFSET)
+#define GPNPUD_REG		__REG(ELFIN_GPIO_BASE+GPNPUD_OFFSET)
+#define GPOCON_REG		__REG(ELFIN_GPIO_BASE+GPOCON_OFFSET)
+#define GPODAT_REG		__REG(ELFIN_GPIO_BASE+GPODAT_OFFSET)
+#define GPOPUD_REG		__REG(ELFIN_GPIO_BASE+GPOPUD_OFFSET)
+#define GPOCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPOCONSLP_OFFSET)
+#define GPOPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET)
+#define GPPCON_REG		__REG(ELFIN_GPIO_BASE+GPPCON_OFFSET)
+#define GPPDAT_REG		__REG(ELFIN_GPIO_BASE+GPPDAT_OFFSET)
+#define GPPPUD_REG		__REG(ELFIN_GPIO_BASE+GPPPUD_OFFSET)
+#define GPPCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPPCONSLP_OFFSET)
+#define GPPPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET)
+#define GPQCON_REG		__REG(ELFIN_GPIO_BASE+GPQCON_OFFSET)
+#define GPQDAT_REG		__REG(ELFIN_GPIO_BASE+GPQDAT_OFFSET)
+#define GPQPUD_REG		__REG(ELFIN_GPIO_BASE+GPQPUD_OFFSET)
+#define GPQCONSLP_REG		__REG(ELFIN_GPIO_BASE+GPQCONSLP_OFFSET)
+#define GPQPUDSLP_REG		__REG(ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET)
+
+#define GPACON		(ELFIN_GPIO_BASE+GPACON_OFFSET)
+#define GPADAT		(ELFIN_GPIO_BASE+GPADAT_OFFSET)
+#define GPAPUD		(ELFIN_GPIO_BASE+GPAPUD_OFFSET)
+#define GPACONSLP	(ELFIN_GPIO_BASE+GPACONSLP_OFFSET)
+#define GPAPUDSLP	(ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET)
+#define GPBCON		(ELFIN_GPIO_BASE+GPBCON_OFFSET)
+#define GPBDAT		(ELFIN_GPIO_BASE+GPBDAT_OFFSET)
+#define GPBPUD		(ELFIN_GPIO_BASE+GPBPUD_OFFSET)
+#define GPBCONSLP	(ELFIN_GPIO_BASE+GPBCONSLP_OFFSET)
+#define GPBPUDSLP	(ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET)
+#define GPCCON		(ELFIN_GPIO_BASE+GPCCON_OFFSET)
+#define GPCDAT		(ELFIN_GPIO_BASE+GPCDAT_OFFSET)
+#define GPCPUD		(ELFIN_GPIO_BASE+GPCPUD_OFFSET)
+#define GPCCONSLP	(ELFIN_GPIO_BASE+GPCCONSLP_OFFSET)
+#define GPCPUDSLP	(ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET)
+#define GPDCON		(ELFIN_GPIO_BASE+GPDCON_OFFSET)
+#define GPDDAT		(ELFIN_GPIO_BASE+GPDDAT_OFFSET)
+#define GPDPUD		(ELFIN_GPIO_BASE+GPDPUD_OFFSET)
+#define GPDCONSLP	(ELFIN_GPIO_BASE+GPDCONSLP_OFFSET)
+#define GPDPUDSLP	(ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET)
+#define GPECON		(ELFIN_GPIO_BASE+GPECON_OFFSET)
+#define GPEDAT		(ELFIN_GPIO_BASE+GPEDAT_OFFSET)
+#define GPEPUD		(ELFIN_GPIO_BASE+GPEPUD_OFFSET)
+#define GPECONSLP	(ELFIN_GPIO_BASE+GPECONSLP_OFFSET)
+#define GPEPUDSLP	(ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET)
+#define GPFCON		(ELFIN_GPIO_BASE+GPFCON_OFFSET)
+#define GPFDAT		(ELFIN_GPIO_BASE+GPFDAT_OFFSET)
+#define GPFPUD		(ELFIN_GPIO_BASE+GPFPUD_OFFSET)
+#define GPFCONSLP	(ELFIN_GPIO_BASE+GPFCONSLP_OFFSET)
+#define GPFPUDSLP	(ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET)
+#define GPGCON		(ELFIN_GPIO_BASE+GPGCON_OFFSET)
+#define GPGDAT		(ELFIN_GPIO_BASE+GPGDAT_OFFSET)
+#define GPGPUD		(ELFIN_GPIO_BASE+GPGPUD_OFFSET)
+#define GPGCONSLP	(ELFIN_GPIO_BASE+GPGCONSLP_OFFSET)
+#define GPGPUDSLP	(ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET)
+#define GPHCON0		(ELFIN_GPIO_BASE+GPHCON0_OFFSET)
+#define GPHCON1		(ELFIN_GPIO_BASE+GPHCON1_OFFSET)
+#define GPHDAT		(ELFIN_GPIO_BASE+GPHDAT_OFFSET)
+#define GPHPUD		(ELFIN_GPIO_BASE+GPHPUD_OFFSET)
+#define GPHCONSLP	(ELFIN_GPIO_BASE+GPHCONSLP_OFFSET)
+#define GPHPUDSLP	(ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET)
+#define GPICON		(ELFIN_GPIO_BASE+GPICON_OFFSET)
+#define GPIDAT		(ELFIN_GPIO_BASE+GPIDAT_OFFSET)
+#define GPIPUD		(ELFIN_GPIO_BASE+GPIPUD_OFFSET)
+#define GPICONSLP	(ELFIN_GPIO_BASE+GPICONSLP_OFFSET)
+#define GPIPUDSLP	(ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET)
+#define GPJCON		(ELFIN_GPIO_BASE+GPJCON_OFFSET)
+#define GPJDAT		(ELFIN_GPIO_BASE+GPJDAT_OFFSET)
+#define GPJPUD		(ELFIN_GPIO_BASE+GPJPUD_OFFSET)
+#define GPJCONSLP	(ELFIN_GPIO_BASE+GPJCONSLP_OFFSET)
+#define GPJPUDSLP	(ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET)
+#define GPKCON0		(ELFIN_GPIO_BASE+GPKCON0_OFFSET)
+#define GPKCON1		(ELFIN_GPIO_BASE+GPKCON1_OFFSET)
+#define GPKDAT		(ELFIN_GPIO_BASE+GPKDAT_OFFSET)
+#define GPKPUD		(ELFIN_GPIO_BASE+GPKPUD_OFFSET)
+#define GPLCON0		(ELFIN_GPIO_BASE+GPLCON0_OFFSET)
+#define GPLCON1		(ELFIN_GPIO_BASE+GPLCON1_OFFSET)
+#define GPLDAT		(ELFIN_GPIO_BASE+GPLDAT_OFFSET)
+#define GPLPUD		(ELFIN_GPIO_BASE+GPLPUD_OFFSET)
+#define GPMCON		(ELFIN_GPIO_BASE+GPMCON_OFFSET)
+#define GPMDAT		(ELFIN_GPIO_BASE+GPMDAT_OFFSET)
+#define GPMPUD		(ELFIN_GPIO_BASE+GPMPUD_OFFSET)
+#define GPNCON		(ELFIN_GPIO_BASE+GPNCON_OFFSET)
+#define GPNDAT		(ELFIN_GPIO_BASE+GPNDAT_OFFSET)
+#define GPNPUD		(ELFIN_GPIO_BASE+GPNPUD_OFFSET)
+#define GPOCON		(ELFIN_GPIO_BASE+GPOCON_OFFSET)
+#define GPODAT		(ELFIN_GPIO_BASE+GPODAT_OFFSET)
+#define GPOPUD		(ELFIN_GPIO_BASE+GPOPUD_OFFSET)
+#define GPOCONSLP	(ELFIN_GPIO_BASE+GPOCONSLP_OFFSET)
+#define GPOPUDSLP	(ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET)
+#define GPPCON		(ELFIN_GPIO_BASE+GPPCON_OFFSET)
+#define GPPDAT		(ELFIN_GPIO_BASE+GPPDAT_OFFSET)
+#define GPPPUD		(ELFIN_GPIO_BASE+GPPPUD_OFFSET)
+#define GPPCONSLP	(ELFIN_GPIO_BASE+GPPCONSLP_OFFSET)
+#define GPPPUDSLP	(ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET)
+#define GPQCON		(ELFIN_GPIO_BASE+GPQCON_OFFSET)
+#define GPQDAT		(ELFIN_GPIO_BASE+GPQDAT_OFFSET)
+#define GPQPUD		(ELFIN_GPIO_BASE+GPQPUD_OFFSET)
+#define GPQCONSLP	(ELFIN_GPIO_BASE+GPQCONSLP_OFFSET)
+#define GPQPUDSLP	(ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET)
+
+/*
+ * Bus Matrix
+ */
+#define ELFIN_MEM_SYS_CFG	0x7e00f120
+
+
+
+/*
+ * Memory controller
+ */
+#define ELFIN_SROM_BASE		0x70000000
+
+#define SROM_BW_REG		__REG(ELFIN_SROM_BASE+0x0)
+#define SROM_BC0_REG		__REG(ELFIN_SROM_BASE+0x4)
+#define SROM_BC1_REG		__REG(ELFIN_SROM_BASE+0x8)
+#define SROM_BC2_REG		__REG(ELFIN_SROM_BASE+0xC)
+#define SROM_BC3_REG		__REG(ELFIN_SROM_BASE+0x10)
+#define SROM_BC4_REG		__REG(ELFIN_SROM_BASE+0x14)
+#define SROM_BC5_REG		__REG(ELFIN_SROM_BASE+0x18)
+
+
+
+/*
+ * SDRAM Controller
+ */
+#define ELFIN_DMC0_BASE		0x7e000000
+#define ELFIN_DMC1_BASE		0x7e001000
+
+#define INDEX_DMC_MEMC_STATUS   (0x00)
+#define INDEX_DMC_MEMC_CMD      (0x04)
+#define INDEX_DMC_DIRECT_CMD    (0x08)
+#define INDEX_DMC_MEMORY_CFG    (0x0C)
+#define INDEX_DMC_REFRESH_PRD   (0x10)
+#define INDEX_DMC_CAS_LATENCY   (0x14)
+#define INDEX_DMC_T_DQSS        (0x18)
+#define INDEX_DMC_T_MRD         (0x1C)
+#define INDEX_DMC_T_RAS         (0x20)
+#define INDEX_DMC_T_RC          (0x24)
+#define INDEX_DMC_T_RCD         (0x28)
+#define INDEX_DMC_T_RFC         (0x2C)
+#define INDEX_DMC_T_RP          (0x30)
+#define INDEX_DMC_T_RRD         (0x34)
+#define INDEX_DMC_T_WR          (0x38)
+#define INDEX_DMC_T_WTR         (0x3C)
+#define INDEX_DMC_T_XP          (0x40)
+#define INDEX_DMC_T_XSR         (0x44)
+#define INDEX_DMC_T_ESR         (0x48)
+#define INDEX_DMC_MEMORY_CFG2	(0x4C)
+#define INDEX_DMC_CHIP_0_CFG    (0x200)
+#define INDEX_DMC_CHIP_1_CFG    (0x204)
+#define INDEX_DMC_CHIP_2_CFG    (0x208)
+#define INDEX_DMC_CHIP_3_CFG    (0x20C)
+#define INDEX_DMC_USER_STATUS	(0x300)
+#define INDEX_DMC_USER_CONFIG	(0x304)
+
+/*
+* Memory Chip direct command
+*/
+#define DMC_NOP0 			0x0c0000
+#define DMC_NOP1			0x1c0000
+#define DMC_PA0 			0x000000	//Precharge all
+#define DMC_PA1 			0x100000
+#define DMC_AR0 			0x040000	//Autorefresh
+#define DMC_AR1 			0x140000
+#define DMC_SDR_MR0			0x080032	//MRS, CAS 3,  Burst Length 4
+#define DMC_SDR_MR1			0x180032
+#define DMC_DDR_MR0			0x080162
+#define DMC_DDR_MR1			0x180162
+#define DMC_mDDR_MR0			0x080032	//CAS 3, Burst Length 4
+#define DMC_mDDR_MR1			0x180032
+#define DMC_mSDR_EMR0			0x0a0000	//EMRS, DS:Full, PASR:Full Array
+#define DMC_mSDR_EMR1			0x1a0000
+#define DMC_DDR_EMR0			0x090000
+#define DMC_DDR_EMR1			0x190000
+#define DMC_mDDR_EMR0			0x0a0000	// DS:Full, PASR:Full Array
+#define DMC_mDDR_EMR1			0x1a0000
+
+
+/****************************************************************
+ Definitions for memory configuration
+ Set memory configuration
+	active_chips	 = 1'b0 (1 chip)
+	qos_master_chip  = 3'b000(ARID[3:0])
+	memory burst	 = 3'b010(burst 4)
+	stop_mem_clock	 = 1'b0(disable dynamical stop)
+	auto_power_down  = 1'b0(disable auto power-down mode)
+	power_down_prd	 = 6'b00_0000(0 cycle for auto power-down)
+	ap_bit		 = 1'b0 (bit position of auto-precharge is 10)
+	row_bits	 = 3'b010(# row address 13)
+	column_bits	 = 3'b010(# column address 10 )
+
+ Set user configuration
+	2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
+
+ Set chip select for chip [n]
+	 row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
+	 CHIP_[n]_CFG=0x30F8,  30: ADDR[31:24], F8: Mask[31:24]
+******************************************************************/
+
+/*
+ * HS MMC Interface
+ */
+#define ELFIN_HSMMC_BASE	0x7C200000
+
+#define HM_SYSAD		(0x00)
+#define HM_BLKSIZE		(0x04)
+#define HM_BLKCNT		(0x06)
+#define HM_ARGUMENT		(0x08)
+#define HM_TRNMOD		(0x0c)
+#define HM_CMDREG		(0x0e)
+#define HM_RSPREG0		(0x10)
+#define HM_RSPREG1		(0x14)
+#define HM_RSPREG2		(0x18)
+#define HM_RSPREG3		(0x1c)
+#define HM_BDATA		(0x20)
+#define HM_PRNSTS		(0x24)
+#define HM_HOSTCTL		(0x28)
+#define HM_PWRCON		(0x29)
+#define HM_BLKGAP		(0x2a)
+#define HM_WAKCON		(0x2b)
+#define HM_CLKCON		(0x2c)
+#define HM_TIMEOUTCON		(0x2e)
+#define HM_SWRST		(0x2f)
+#define HM_NORINTSTS		(0x30)
+#define HM_ERRINTSTS		(0x32)
+#define HM_NORINTSTSEN		(0x34)
+#define HM_ERRINTSTSEN		(0x36)
+#define HM_NORINTSIGEN		(0x38)
+#define HM_ERRINTSIGEN		(0x3a)
+#define HM_ACMD12ERRSTS		(0x3c)
+#define HM_CAPAREG		(0x40)
+#define HM_MAXCURR		(0x48)
+#define HM_CONTROL2		(0x80)
+#define HM_CONTROL3		(0x84)
+#define HM_CONTROL4		(0x8c)
+#define HM_HCVER		(0xfe)
+
+/*
+ * Nand flash controller
+ */
+#define ELFIN_NAND_BASE		0x70200000
+
+#define NFCONF_OFFSET           0x00
+#define NFCONT_OFFSET           0x04
+#define NFCMMD_OFFSET           0x08
+#define NFADDR_OFFSET           0x0c
+#define NFDATA_OFFSET		0x10
+#define NFMECCDATA0_OFFSET      0x14
+#define NFMECCDATA1_OFFSET      0x18
+#define NFSECCDATA0_OFFSET      0x1c
+#define NFSBLK_OFFSET           0x20
+#define NFEBLK_OFFSET           0x24
+#define NFSTAT_OFFSET           0x28
+#define NFESTAT0_OFFSET         0x2c
+#define NFESTAT1_OFFSET         0x30
+#define NFMECC0_OFFSET          0x34
+#define NFMECC1_OFFSET          0x38
+#define NFSECC_OFFSET           0x3c
+#define NFMLCBITPT_OFFSET       0x40
+#define NF8ECCERR0_OFFSET	0x44
+#define NF8ECCERR1_OFFSET	0x48
+#define NF8ECCERR2_OFFSET	0x4c
+#define NFM8ECC0_OFFSET		0x50
+#define NFM8ECC1_OFFSET		0x54
+#define NFM8ECC2_OFFSET		0x58
+#define NFM8ECC3_OFFSET		0x5c
+#define NFMLC8BITPT0_OFFSET	0x60
+#define NFMLC8BITPT1_OFFSET	0x64
+
+#define NFCONF			(ELFIN_NAND_BASE+NFCONF_OFFSET)
+#define NFCONT			(ELFIN_NAND_BASE+NFCONT_OFFSET)
+#define NFCMMD			(ELFIN_NAND_BASE+NFCMMD_OFFSET)
+#define NFADDR           	(ELFIN_NAND_BASE+NFADDR_OFFSET)
+#define NFDATA          	(ELFIN_NAND_BASE+NFDATA_OFFSET)
+#define NFMECCDATA0     	(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
+#define NFMECCDATA1     	(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
+#define NFSECCDATA0      	(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
+#define NFSBLK          	(ELFIN_NAND_BASE+NFSBLK_OFFSET)
+#define NFEBLK           	(ELFIN_NAND_BASE+NFEBLK_OFFSET)
+#define NFSTAT           	(ELFIN_NAND_BASE+NFSTAT_OFFSET)
+#define NFESTAT0         	(ELFIN_NAND_BASE+NFESTAT0_OFFSET)
+#define NFESTAT1         	(ELFIN_NAND_BASE+NFESTAT1_OFFSET)
+#define NFMECC0          	(ELFIN_NAND_BASE+NFMECC0_OFFSET)
+#define NFMECC1          	(ELFIN_NAND_BASE+NFMECC1_OFFSET)
+#define NFSECC           	(ELFIN_NAND_BASE+NFSECC_OFFSET)
+#define NFMLCBITPT           	(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
+#define NF8ECCERR0		(ELFIN_NAND_BASE+NF8ECCERR0_OFFSET)
+#define NF8ECCERR1		(ELFIN_NAND_BASE+NF8ECCERR1_OFFSET)
+#define NF8ECCERR2		(ELFIN_NAND_BASE+NF8ECCERR2_OFFSET)
+#define NFM8ECC0		(ELFIN_NAND_BASE+NFM8ECC0_OFFSET)
+#define NFM8ECC1		(ELFIN_NAND_BASE+NFM8ECC1_OFFSET)
+#define NFM8ECC2		(ELFIN_NAND_BASE+NFM8ECC2_OFFSET)
+#define NFM8ECC3		(ELFIN_NAND_BASE+NFM8ECC3_OFFSET)
+#define NFMLC8BITPT0		(ELFIN_NAND_BASE+NFMLC8BITPT0_OFFSET)
+#define NFMLC8BITPT1		(ELFIN_NAND_BASE+NFMLC8BITPT1_OFFSET)
+
+#define NFCONF_REG		__REG(ELFIN_NAND_BASE+NFCONF_OFFSET)
+#define NFCONT_REG		__REG(ELFIN_NAND_BASE+NFCONT_OFFSET)
+#define NFCMD_REG		__REG(ELFIN_NAND_BASE+NFCMMD_OFFSET)
+#define NFADDR_REG           	__REG(ELFIN_NAND_BASE+NFADDR_OFFSET)
+#define NFDATA_REG          	__REG(ELFIN_NAND_BASE+NFDATA_OFFSET)
+#define NFDATA8_REG          	__REGb(ELFIN_NAND_BASE+NFDATA_OFFSET)
+#define NFMECCDATA0_REG     	__REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
+#define NFMECCDATA1_REG     	__REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
+#define NFSECCDATA0_REG      	__REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
+#define NFSBLK_REG          	__REG(ELFIN_NAND_BASE+NFSBLK_OFFSET)
+#define NFEBLK_REG           	__REG(ELFIN_NAND_BASE+NFEBLK_OFFSET)
+#define NFSTAT_REG           	__REG(ELFIN_NAND_BASE+NFSTAT_OFFSET)
+#define NFESTAT0_REG         	__REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET)
+#define NFESTAT1_REG         	__REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET)
+#define NFMECC0_REG          	__REG(ELFIN_NAND_BASE+NFMECC0_OFFSET)
+#define NFMECC1_REG          	__REG(ELFIN_NAND_BASE+NFMECC1_OFFSET)
+#define NFSECC_REG           	__REG(ELFIN_NAND_BASE+NFSECC_OFFSET)
+#define NFMLCBITPT_REG         	__REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
+
+#define NFCONF_ECC_MLC		(1<<24)
+#define NFCONT_ECC_ENC		(1<<18)
+#define NFCONT_WP		(1<<16)
+#define NFCONT_MECCLOCK		(1<<7)
+#define NFCONT_SECCLOCK		(1<<6)
+#define NFCONT_INITMECC		(1<<5)
+#define NFCONT_INITSECC		(1<<4)
+#define NFCONT_INITECC		(NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT		(1<<1)
+#define NFCONT_CS		(1<<1)
+#define NFSTAT_ECCENCDONE	(1<<7)
+#define NFSTAT_ECCDECDONE	(1<<6)
+#define NFSTAT_RnB		(1<<0)
+#define NFESTAT0_ECCBUSY	(1<<31)
+
+
+
+/*************************************************************
+ * OneNAND Controller
+ *************************************************************/
+
+/*
+ * S3C6400 SFRs
+ */
+#define ONENAND_REG_MEM_CFG		(0x000)
+#define ONENAND_REG_BURST_LEN		(0x010)
+#define ONENAND_REG_MEM_RESET		(0x020)
+#define ONENAND_REG_INT_ERR_STAT	(0x030)
+#define ONENAND_REG_INT_ERR_MASK	(0x040)
+#define ONENAND_REG_INT_ERR_ACK		(0x050)
+#define ONENAND_REG_ECC_ERR_STAT	(0x060)
+#define ONENAND_REG_MANUFACT_ID		(0x070)
+#define ONENAND_REG_DEVICE_ID		(0x080)
+#define ONENAND_REG_DATA_BUF_SIZE	(0x090)
+#define ONENAND_REG_BOOT_BUF_SIZE	(0x0A0)
+#define ONENAND_REG_BUF_AMOUNT		(0x0B0)
+#define ONENAND_REG_TECH		(0x0C0)
+#define ONENAND_REG_FBA_WIDTH		(0x0D0)
+#define ONENAND_REG_FPA_WIDTH		(0x0E0)
+#define ONENAND_REG_FSA_WIDTH		(0x0F0)
+#define ONENAND_REG_REVISION		(0x100)
+#define ONENAND_REG_DATARAM0		(0x110)
+#define ONENAND_REG_DATARAM1		(0x120)
+#define ONENAND_REG_SYNC_MODE		(0x130)
+#define ONENAND_REG_TRANS_SPARE		(0x140)
+#define ONENAND_REG_LOCK_BIT		(0x150)
+#define ONENAND_REG_DBS_DFS_WIDTH	(0x160)
+#define ONENAND_REG_PAGE_CNT		(0x170)
+#define ONENAND_REG_ERR_PAGE_ADDR	(0x180)
+#define ONENAND_REG_BURST_RD_LAT	(0x190)
+#define ONENAND_REG_INT_PIN_ENABLE	(0x1A0)
+#define ONENAND_REG_INT_MON_CYC		(0x1B0)
+#define ONENAND_REG_ACC_CLOCK		(0x1C0)
+#define ONENAND_REG_SLOW_RD_PATH	(0x1D0)
+#define ONENAND_REG_ERR_BLK_ADDR	(0x1E0)
+#define ONENAND_REG_FLASH_VER_ID	(0x1F0)
+#define ONENAND_REG_FLASH_AUX_CNTRL	(0x300)
+
+/*
+ * S3C6400 SFR values
+ */
+#define ONENAND_MEM_CFG_SYNC_READ	(1 << 15)
+#define ONENAND_MEM_CFG_BRL_7		(7 << 12)
+#define ONENAND_MEM_CFG_BRL_6		(6 << 12)
+#define ONENAND_MEM_CFG_BRL_5		(5 << 12)
+#define ONENAND_MEM_CFG_BRL_4		(4 << 12)
+#define ONENAND_MEM_CFG_BRL_3		(3 << 12)
+#define ONENAND_MEM_CFG_BRL_10		(2 << 12)
+#define ONENAND_MEM_CFG_BRL_9		(1 << 12)
+#define ONENAND_MEM_CFG_BRL_8		(0 << 12)
+#define ONENAND_MEM_CFG_BRL_SHIFT	(12)
+#define ONENAND_MEM_CFG_BL_1K		(5 << 9)
+#define ONENAND_MEM_CFG_BL_32		(4 << 9)
+#define ONENAND_MEM_CFG_BL_16		(3 << 9)
+#define ONENAND_MEM_CFG_BL_8		(2 << 9)
+#define ONENAND_MEM_CFG_BL_4		(1 << 9)
+#define ONENAND_MEM_CFG_BL_CONT		(0 << 9)
+#define ONENAND_MEM_CFG_BL_SHIFT	(9)
+#define ONENAND_MEM_CFG_NO_ECC		(1 << 8)
+#define ONENAND_MEM_CFG_RDY_HIGH	(1 << 7)
+#define ONENAND_MEM_CFG_INT_HIGH	(1 << 6)
+#define ONENAND_MEM_CFG_IOBE		(1 << 5)
+#define ONENAND_MEM_CFG_RDY_CONF	(1 << 4)
+#define ONENAND_MEM_CFG_HF		(1 << 2)
+#define ONENAND_MEM_CFG_WM_SYNC		(1 << 1)
+#define ONENAND_MEM_CFG_BWPS_UNLOCK	(1 << 0)
+
+#define ONENAND_BURST_LEN_CONT		(0)
+#define ONENAND_BURST_LEN_4		(4)
+#define ONENAND_BURST_LEN_8		(8)
+#define ONENAND_BURST_LEN_16		(16)
+
+#define ONENAND_MEM_RESET_WARM		(0x1)
+#define ONENAND_MEM_RESET_COLD		(0x2)
+#define ONENAND_MEM_RESET_HOT		(0x3)
+
+#define ONENAND_INT_ERR_CACHE_OP_ERR	(1 << 13)
+#define ONENAND_INT_ERR_RST_CMP		(1 << 12)
+#define ONENAND_INT_ERR_RDY_ACT		(1 << 11)
+#define ONENAND_INT_ERR_INT_ACT		(1 << 10)
+#define ONENAND_INT_ERR_UNSUP_CMD	(1 << 9)
+#define ONENAND_INT_ERR_LOCKED_BLK	(1 << 8)
+#define ONENAND_INT_ERR_BLK_RW_CMP	(1 << 7)
+#define ONENAND_INT_ERR_ERS_CMP		(1 << 6)
+#define ONENAND_INT_ERR_PGM_CMP		(1 << 5)
+#define ONENAND_INT_ERR_LOAD_CMP	(1 << 4)
+#define ONENAND_INT_ERR_ERS_FAIL	(1 << 3)
+#define ONENAND_INT_ERR_PGM_FAIL	(1 << 2)
+#define ONENAND_INT_ERR_INT_TO		(1 << 1)
+#define ONENAND_INT_ERR_LD_FAIL_ECC_ERR	(1 << 0)
+
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+#define ONENAND_DEVICE_DENSITY_128Mb	(0x000)
+#define ONENAND_DEVICE_DENSITY_256Mb	(0x001)
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
+#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
+#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)
+
+#define ONENAND_SYNC_MODE_RM_SYNC	(1 << 1)
+#define ONENAND_SYNC_MODE_WM_SYNC	(1 << 0)
+
+#define ONENAND_TRANS_SPARE_TSRF_INC	(1 << 0)
+
+#define ONENAND_INT_PIN_ENABLE		(1 << 0)
+
+#define ONENAND_ACC_CLOCK_266_133	(0x5)
+#define ONENAND_ACC_CLOCK_166_83	(0x3)
+#define ONENAND_ACC_CLOCK_134_67	(0x3)
+#define ONENAND_ACC_CLOCK_100_50	(0x2)
+#define ONENAND_ACC_CLOCK_60_30		(0x2)
+
+#define ONENAND_FLASH_AUX_WD_DISABLE	(1 << 0)
+
+/*
+ * Datain values for mapped commands
+ */
+#define ONENAND_DATAIN_ERASE_STATUS	(0x00)
+#define ONENAND_DATAIN_ERASE_MULTI	(0x01)
+#define ONENAND_DATAIN_ERASE_SINGLE	(0x03)
+#define ONENAND_DATAIN_ERASE_VERIFY	(0x15)
+#define ONENAND_DATAIN_UNLOCK_START	(0x08)
+#define ONENAND_DATAIN_UNLOCK_END	(0x09)
+#define ONENAND_DATAIN_LOCK_START	(0x0A)
+#define ONENAND_DATAIN_LOCK_END		(0x0B)
+#define ONENAND_DATAIN_LOCKTIGHT_START	(0x0C)
+#define ONENAND_DATAIN_LOCKTIGHT_END	(0x0D)
+#define ONENAND_DATAIN_UNLOCK_ALL	(0x0E)
+#define ONENAND_DATAIN_COPYBACK_SRC	(0x1000)
+#define ONENAND_DATAIN_COPYBACK_DST	(0x2000)
+#define ONENAND_DATAIN_ACCESS_OTP	(0x12)
+#define ONENAND_DATAIN_ACCESS_MAIN	(0x14)
+#define ONENAND_DATAIN_PIPELINE_READ	(0x4000)
+#define ONENAND_DATAIN_PIPELINE_WRITE	(0x4100)
+#define ONENAND_DATAIN_RMW_LOAD		(0x10)
+#define ONENAND_DATAIN_RMW_MODIFY	(0x11)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+#define ONENAND_DDP_CHIP0		(0)
+#define ONENAND_DDP_CHIP1		(1 << ONENAND_DDP_SHIFT)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_UNLOCK_ALL		(0x27)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_OTP_ACCESS		(0x65)
+#define ONENAND_CMD_READID		(0x90)
+#define ONENAND_CMD_STARTADDR1		(0xE0)
+#define ONENAND_CMD_WP_STATUS		(0xE1)
+#define ONENAND_CMD_PIPELINE_READ	(0x01)
+#define ONENAND_CMD_PIPELINE_WRITE	(0x81)
+
+/*
+ * Command Mapping for S3C6400 OneNAND Controller
+ */
+#define ONENAND_AHB_ADDR		(0x20000000)
+#define ONENAND_DUMMY_ADDR		(0x20400000)
+#define ONENAND_CMD_SHIFT		(24)
+#define ONENAND_CMD_MAP_00		(0x0)
+#define ONENAND_CMD_MAP_01		(0x1)
+#define ONENAND_CMD_MAP_10		(0x2)
+#define ONENAND_CMD_MAP_11		(0x3)
+#define ONENAND_CMD_MAP_FF		(0xF)
+
+/*
+ * Mask for Mapping table
+ */
+#define ONENAND_MEM_ADDR_MASK		(0xffffff)
+#define ONENAND_DDP_SHIFT_1Gb		(21)
+#define ONENAND_DDP_SHIFT_2Gb		(22)
+#define ONENAND_DDP_SHIFT_4Gb		(23)
+#define ONENAND_FBA_SHIFT		(12)
+#define ONENAND_FPA_SHIFT		(6)
+#define ONENAND_FSA_SHIFT		(4)
+#define ONENAND_FBA_MASK_128Mb		(0xff)
+#define ONENAND_FBA_MASK_256Mb		(0x1ff)
+#define ONENAND_FBA_MASK_512Mb		(0x1ff)
+#define ONENAND_FBA_MASK_1Gb_DDP	(0x1ff)
+#define ONENAND_FBA_MASK_1Gb		(0x3ff)
+#define ONENAND_FBA_MASK_2Gb_DDP	(0x3ff)
+#define ONENAND_FBA_MASK_2Gb		(0x7ff)
+#define ONENAND_FBA_MASK_4Gb_DDP	(0x7ff)
+#define ONENAND_FBA_MASK_4Gb		(0xfff)
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FSA_MASK		(0x3)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
+#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
+#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
+#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
+#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+#define ONENAND_CTRL_OTP_L		(1 << 6)
+#define ONENAND_CTRL_OTP_BL		(1 << 5)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Register FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_1BIT_ALL		(0x5555)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+/*
+ * One-Time Programmable (OTP)
+ */
+#define ONENAND_OTP_LOCK_OFFSET		(14)
+
+/*************************************************************
+ * End of OneNAND Controller
+ *************************************************************/
+
+
+/*
+ * Interrupt
+ */
+#define ELFIN_VIC0_BASE_ADDR		(0x71200000)
+#define ELFIN_VIC1_BASE_ADDR		(0x71300000)
+#define oINTMOD				(0x0C)		// VIC INT SELECT (IRQ or FIQ)
+#define oINTUNMSK			(0x10)		// VIC INT EN (Unmask by writing 1)
+#define oINTMSK				(0x14)		// VIC INT EN CLEAR (Mask by writing 1)
+#define oINTSUBMSK			(0x1C)		// VIC SOFT INT CLEAR
+#define oVECTADDR			(0xF00)		// VIC ADDRESS
+
+
+
+/*
+ * Watchdog timer
+ */
+#define ELFIN_WATCHDOG_BASE		0x7E004000
+
+#define WTCON_REG			__REG(0x7E004004)
+#define WTDAT_REG			__REG(0x7E004008)
+#define WTCNT_REG			__REG(0x7E00400C)
+
+
+
+/*
+ * UART
+ */
+#define ELFIN_UART_BASE		0x7F005000
+
+#define ELFIN_UART0_OFFSET	0x0000
+#define ELFIN_UART1_OFFSET	0x0400
+#define ELFIN_UART2_OFFSET	0x0800
+
+#ifdef CONFIG_SERIAL1
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
+#elif defined(CONFIG_SERIAL2)
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
+#else
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
+#endif
+
+#define ULCON_OFFSET		0x00
+#define UCON_OFFSET		0x04
+#define UFCON_OFFSET		0x08
+#define UMCON_OFFSET		0x0C
+#define UTRSTAT_OFFSET		0x10
+#define UERSTAT_OFFSET		0x14
+#define UFSTAT_OFFSET		0x18
+#define UMSTAT_OFFSET		0x1C
+#define UTXH_OFFSET		0x20
+#define URXH_OFFSET		0x24
+#define UBRDIV_OFFSET		0x28
+#define UDIVSLOT_OFFSET		0x2C
+#define UINTP_OFFSET		0x30
+#define UINTSP_OFFSET		0x34
+#define UINTM_OFFSET		0x38
+
+#define ULCON0_REG		__REG(0x7F005000)
+#define UCON0_REG		__REG(0x7F005004)
+#define UFCON0_REG		__REG(0x7F005008)
+#define UMCON0_REG		__REG(0x7F00500C)
+#define UTRSTAT0_REG		__REG(0x7F005010)
+#define UERSTAT0_REG		__REG(0x7F005014)
+#define UFSTAT0_REG		__REG(0x7F005018)
+#define UMSTAT0_REG		__REG(0x7F00501c)
+#define UTXH0_REG		__REG(0x7F005020)
+#define URXH0_REG		__REG(0x7F005024)
+#define UBRDIV0_REG		__REG(0x7F005028)
+#define UDIVSLOT0_REG		__REG(0x7F00502c)
+#define UINTP0_REG		__REG(0x7F005030)
+#define UINTSP0_REG		__REG(0x7F005034)
+#define UINTM0_REG		__REG(0x7F005038)
+
+#define ULCON1_REG		__REG(0x7F005400)
+#define UCON1_REG		__REG(0x7F005404)
+#define UFCON1_REG		__REG(0x7F005408)
+#define UMCON1_REG		__REG(0x7F00540C)
+#define UTRSTAT1_REG		__REG(0x7F005410)
+#define UERSTAT1_REG		__REG(0x7F005414)
+#define UFSTAT1_REG		__REG(0x7F005418)
+#define UMSTAT1_REG		__REG(0x7F00541c)
+#define UTXH1_REG		__REG(0x7F005420)
+#define URXH1_REG		__REG(0x7F005424)
+#define UBRDIV1_REG		__REG(0x7F005428)
+#define UDIVSLOT1_REG		__REG(0x7F00542c)
+#define UINTP1_REG		__REG(0x7F005430)
+#define UINTSP1_REG		__REG(0x7F005434)
+#define UINTM1_REG		__REG(0x7F005438)
+
+#define UTRSTAT_TX_EMPTY	BIT2
+#define UTRSTAT_RX_READY	BIT0
+#define UART_ERR_MASK		0xF
+
+
+/*
+ * PWM timer
+ */
+#define ELFIN_TIMER_BASE	0x7F006000
+
+#define TCFG0_REG		__REG(0x7F006000)
+#define TCFG1_REG		__REG(0x7F006004)
+#define TCON_REG		__REG(0x7F006008)
+#define TCNTB0_REG		__REG(0x7F00600c)
+#define TCMPB0_REG		__REG(0x7F006010)
+#define TCNTO0_REG		__REG(0x7F006014)
+#define TCNTB1_REG		__REG(0x7F006018)
+#define TCMPB1_REG		__REG(0x7F00601c)
+#define TCNTO1_REG		__REG(0x7F006020)
+#define TCNTB2_REG		__REG(0x7F006024)
+#define TCMPB2_REG		__REG(0x7F006028)
+#define TCNTO2_REG		__REG(0x7F00602c)
+#define TCNTB3_REG		__REG(0x7F006030)
+#define TCMPB3_REG		__REG(0x7F006034)
+#define TCNTO3_REG		__REG(0x7F006038)
+#define TCNTB4_REG		__REG(0x7F00603c)
+#define TCNTO4_REG		__REG(0x7F006040)
+
+/* Fields */
+#define fTCFG0_DZONE		Fld(8,16)       /* the dead zone length (= timer 0) */
+#define fTCFG0_PRE1		Fld(8,8)        /* prescaler value for time 2,3,4 */
+#define fTCFG0_PRE0		Fld(8,0)        /* prescaler value for time 0,1 */
+#define fTCFG1_MUX4		Fld(4,16)
+/* bits */
+#define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
+#define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
+#define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)
+#define TCON_4_AUTO		(1 << 22)       /* auto reload on/off for Timer 4 */
+#define TCON_4_UPDATE		(1 << 21)       /* manual Update TCNTB4 */
+#define TCON_4_ONOFF		(1 << 20)       /* 0: Stop, 1: start Timer 4 */
+#define COUNT_4_ON		(TCON_4_ONOFF*1)
+#define COUNT_4_OFF		(TCON_4_ONOFF*0)
+#define TCON_3_AUTO		(1 << 19)       /* auto reload on/off for Timer 3 */
+#define TIMER3_ATLOAD_ON	(TCON_3_AUTO*1)
+#define TIMER3_ATLAOD_OFF	FClrBit(TCON, TCON_3_AUTO)
+#define TCON_3_INVERT		(1 << 18)       /* 1: Inverter on for TOUT3 */
+#define TIMER3_IVT_ON		(TCON_3_INVERT*1)
+#define TIMER3_IVT_OFF		(FClrBit(TCON, TCON_3_INVERT))
+#define TCON_3_MAN		(1 << 17)       /* manual Update TCNTB3,TCMPB3 */
+#define TIMER3_MANUP		(TCON_3_MAN*1)
+#define TIMER3_NOP		(FClrBit(TCON, TCON_3_MAN))
+#define TCON_3_ONOFF		(1 << 16)       /* 0: Stop, 1: start Timer 3 */
+#define TIMER3_ON		(TCON_3_ONOFF*1)
+#define TIMER3_OFF		(FClrBit(TCON, TCON_3_ONOFF))
+/* macros */
+#define GET_PRESCALE_TIMER4(x)	FExtr((x), fTCFG0_PRE1)
+#define GET_DIVIDER_TIMER4(x)	FExtr((x), fTCFG1_MUX4)
+
+/*
+ * RTC Controller
+ */
+#define ELFIN_RTC_BASE		0x7e005000
+
+#define RTCCON_REG		__REG(0x7e005040)
+#define TICNT_REG		__REG(0x7e005044)
+#define RTCALM_REG		__REG(0x7e005050)
+#define ALMSEC_REG		__REG(0x7e005054)
+#define ALMMIN_REG		__REG(0x7e005058)
+#define ALMHOUR_REG		__REG(0x7e00505c)
+#define ALMDATE_REG		__REG(0x7e005060)
+#define ALMMON_REG		__REG(0x7e005064)
+#define ALMYEAR_REG		__REG(0x7e005068)
+#define BCDSEC_REG		__REG(0x7e005070)
+#define BCDMIN_REG		__REG(0x7e005074)
+#define BCDHOUR_REG		__REG(0x7e005078)
+#define BCDDATE_REG		__REG(0x7e00507c)
+#define BCDDAY_REG		__REG(0x7e005080)
+#define BCDMON_REG		__REG(0x7e005084)
+#define BCDYEAR_REG		__REG(0x7e005088)
+
+/*
+ * USB2.0 HS OTG (Chapter 26)
+ */
+#define USBOTG_LINK_BASE	(0x7C000000)
+#define USBOTG_PHY_BASE		(0x7C100000)
+
+/* Core Global Registers */
+#define S3C_OTG_GOTGCTL		(USBOTG_LINK_BASE + 0x000)	/* OTG Control & Status */
+#define S3C_OTG_GOTGINT		(USBOTG_LINK_BASE + 0x004)	/* OTG Interrupt */
+#define S3C_OTG_GAHBCFG		(USBOTG_LINK_BASE + 0x008)	/* Core AHB Configuration */
+#define S3C_OTG_GUSBCFG		(USBOTG_LINK_BASE + 0x00C)	/* Core USB Configuration */
+#define S3C_OTG_GRSTCTL		(USBOTG_LINK_BASE + 0x010)	/* Core Reset */
+#define S3C_OTG_GINTSTS		(USBOTG_LINK_BASE + 0x014)	/* Core Interrupt */
+#define S3C_OTG_GINTMSK		(USBOTG_LINK_BASE + 0x018)	/* Core Interrupt Mask */
+#define S3C_OTG_GRXSTSR		(USBOTG_LINK_BASE + 0x01C)	/* Receive Status Debug Read/Status Read */
+#define S3C_OTG_GRXSTSP		(USBOTG_LINK_BASE + 0x020)	/* Receive Status Debug Pop/Status Pop */
+#define S3C_OTG_GRXFSIZ		(USBOTG_LINK_BASE + 0x024)	/* Receive FIFO Size */
+#define S3C_OTG_GNPTXFSIZ	(USBOTG_LINK_BASE + 0x028)	/* Non-Periodic Transmit FIFO Size */
+#define S3C_OTG_GNPTXSTS	(USBOTG_LINK_BASE + 0x02C)	/* Non-Periodic Transmit FIFO/Queue Status */
+
+#define S3C_OTG_HPTXFSIZ	(USBOTG_LINK_BASE + 0x100)	/* Host Periodic Transmit FIFO Size */
+#define S3C_OTG_DPTXFSIZ1	(USBOTG_LINK_BASE + 0x104)	/* Device Periodic Transmit FIFO-1 Size */
+#define S3C_OTG_DPTXFSIZ2	(USBOTG_LINK_BASE + 0x108)	/* Device Periodic Transmit FIFO-2 Size */
+#define S3C_OTG_DPTXFSIZ3	(USBOTG_LINK_BASE + 0x10C)	/* Device Periodic Transmit FIFO-3 Size */
+#define S3C_OTG_DPTXFSIZ4	(USBOTG_LINK_BASE + 0x110)	/* Device Periodic Transmit FIFO-4 Size */
+#define S3C_OTG_DPTXFSIZ5	(USBOTG_LINK_BASE + 0x114)	/* Device Periodic Transmit FIFO-5 Size */
+#define S3C_OTG_DPTXFSIZ6	(USBOTG_LINK_BASE + 0x118)	/* Device Periodic Transmit FIFO-6 Size */
+#define S3C_OTG_DPTXFSIZ7	(USBOTG_LINK_BASE + 0x11C)	/* Device Periodic Transmit FIFO-7 Size */
+#define S3C_OTG_DPTXFSIZ8	(USBOTG_LINK_BASE + 0x120)	/* Device Periodic Transmit FIFO-8 Size */
+#define S3C_OTG_DPTXFSIZ9	(USBOTG_LINK_BASE + 0x124)	/* Device Periodic Transmit FIFO-9 Size */
+#define S3C_OTG_DPTXFSIZ10	(USBOTG_LINK_BASE + 0x128)	/* Device Periodic Transmit FIFO-10 Size */
+#define S3C_OTG_DPTXFSIZ11	(USBOTG_LINK_BASE + 0x12C)	/* Device Periodic Transmit FIFO-11 Size */
+#define S3C_OTG_DPTXFSIZ12	(USBOTG_LINK_BASE + 0x130)	/* Device Periodic Transmit FIFO-12 Size */
+#define S3C_OTG_DPTXFSIZ13	(USBOTG_LINK_BASE + 0x134)	/* Device Periodic Transmit FIFO-13 Size */
+#define S3C_OTG_DPTXFSIZ14	(USBOTG_LINK_BASE + 0x138)	/* Device Periodic Transmit FIFO-14 Size */
+#define S3C_OTG_DPTXFSIZ15	(USBOTG_LINK_BASE + 0x13C)	/* Device Periodic Transmit FIFO-15 Size */
+
+/* Host Global Registers */
+#define S3C_OTG_HCFG		(USBOTG_LINK_BASE + 0x400)	/* Host Configuration */
+#define S3C_OTG_HFIR		(USBOTG_LINK_BASE + 0x404)	/* Host Frame Interval */
+#define S3C_OTG_HFNUM		(USBOTG_LINK_BASE + 0x408)	/* Host Frame Number/Frame Time Remaining */
+#define S3C_OTG_HPTXSTS		(USBOTG_LINK_BASE + 0x410)	/* Host Periodic Transmit FIFO/Queue Status */
+#define S3C_OTG_HAINT		(USBOTG_LINK_BASE + 0x414)	/* Host All Channels Interrupt */
+#define S3C_OTG_HAINTMSK	(USBOTG_LINK_BASE + 0x418)	/* Host All Channels Interrupt Mask */
+
+/* Host Port Control & Status Registers */
+#define S3C_OTG_HPRT		(USBOTG_LINK_BASE + 0x440)	/* Host Port Control & Status */
+
+/* Host Channel-Specific Registers */
+#define S3C_OTG_HCCHAR0		(USBOTG_LINK_BASE + 0x500)	/* Host Channel-0 Characteristics */
+#define S3C_OTG_HCSPLT0		(USBOTG_LINK_BASE + 0x504)	/* Host Channel-0 Split Control */
+#define S3C_OTG_HCINT0		(USBOTG_LINK_BASE + 0x508)	/* Host Channel-0 Interrupt */
+#define S3C_OTG_HCINTMSK0	(USBOTG_LINK_BASE + 0x50C)	/* Host Channel-0 Interrupt Mask */
+#define S3C_OTG_HCTSIZ0		(USBOTG_LINK_BASE + 0x510)	/* Host Channel-0 Transfer Size */
+#define S3C_OTG_HCDMA0		(USBOTG_LINK_BASE + 0x514)	/* Host Channel-0 DMA Address */
+
+
+/* Device Global Registers */
+#define S3C_OTG_DCFG		(USBOTG_LINK_BASE + 0x800)	/* Device Configuration */
+#define S3C_OTG_DCTL		(USBOTG_LINK_BASE + 0x804)	/* Device Control */
+#define S3C_OTG_DSTS		(USBOTG_LINK_BASE + 0x808)	/* Device Status */
+#define S3C_OTG_DIEPMSK 	(USBOTG_LINK_BASE + 0x810)	/* Device IN Endpoint Common Interrupt Mask */
+#define S3C_OTG_DOEPMSK 	(USBOTG_LINK_BASE + 0x814)	/* Device OUT Endpoint Common Interrupt Mask */
+#define S3C_OTG_DAINT		(USBOTG_LINK_BASE + 0x818)	/* Device All Endpoints Interrupt */
+#define S3C_OTG_DAINTMSK	(USBOTG_LINK_BASE + 0x81C)	/* Device All Endpoints Interrupt Mask */
+#define S3C_OTG_DTKNQR1 	(USBOTG_LINK_BASE + 0x820)	/* Device IN Token Sequence Learning Queue Read 1 */
+#define S3C_OTG_DTKNQR2 	(USBOTG_LINK_BASE + 0x824)	/* Device IN Token Sequence Learning Queue Read 2 */
+#define S3C_OTG_DVBUSDIS	(USBOTG_LINK_BASE + 0x828)	/* Device VBUS Discharge Time */
+#define S3C_OTG_DVBUSPULSE	(USBOTG_LINK_BASE + 0x82C)	/* Device VBUS Pulsing Time */
+#define S3C_OTG_DTKNQR3 	(USBOTG_LINK_BASE + 0x830)	/* Device IN Token Sequence Learning Queue Read 3 */
+#define S3C_OTG_DTKNQR4 	(USBOTG_LINK_BASE + 0x834)	/* Device IN Token Sequence Learning Queue Read 4 */
+
+/* Device Logical IN Endpoint-Specific Registers */
+#define S3C_OTG_DIEPCTL0	(USBOTG_LINK_BASE + 0x900)	/* Device IN Endpoint 0 Control */
+#define S3C_OTG_DIEPINT0	(USBOTG_LINK_BASE + 0x908)	/* Device IN Endpoint 0 Interrupt */
+#define S3C_OTG_DIEPTSIZ0	(USBOTG_LINK_BASE + 0x910)	/* Device IN Endpoint 0 Transfer Size */
+#define S3C_OTG_DIEPDMA0	(USBOTG_LINK_BASE + 0x914)	/* Device IN Endpoint 0 DMA Address */
+
+/* Device Logical OUT Endpoint-Specific Registers */
+#define S3C_OTG_DOEPCTL0	(USBOTG_LINK_BASE + 0xB00)	/* Device OUT Endpoint 0 Control */
+#define S3C_OTG_DOEPINT0	(USBOTG_LINK_BASE + 0xB08)	/* Device OUT Endpoint 0 Interrupt */
+#define S3C_OTG_DOEPTSIZ0	(USBOTG_LINK_BASE + 0xB10)	/* Device OUT Endpoint 0 Transfer Size */
+#define S3C_OTG_DOEPDMA0	(USBOTG_LINK_BASE + 0xB14)	/* Device OUT Endpoint 0 DMA Address */
+
+/* Power & clock gating registers */
+#define S3C_OTG_PCGCCTRL	(USBOTG_LINK_BASE + 0xE00)
+
+/* Endpoint FIFO address */
+#define S3C_OTG_EP0_FIFO	(USBOTG_LINK_BASE + 0x1000)
+
+
+
+/* OTG PHY CORE REGISTERS */
+#define S3C_OTG_PHYPWR		(USBOTG_PHY_BASE+0x00)
+#define S3C_OTG_PHYCTRL		(USBOTG_PHY_BASE+0x04)
+#define S3C_OTG_RSTCON		(USBOTG_PHY_BASE+0x08)
+
+/* include common stuff */
+#ifndef __ASSEMBLY__
+static inline S3C64XX_MEMCTL * S3C64XX_GetBase_MEMCTL(void)
+{
+	return (S3C64XX_MEMCTL *)(ELFIN_DMC0_BASE);
+}
+static inline S3C64XX_USB_HOST * S3C64XX_GetBase_USB_HOST(void)
+{
+	return (S3C64XX_USB_HOST *)ELFIN_USB_HOST_BASE;
+}
+static inline S3C64XX_INTERRUPT * S3C64XX_GetBase_INTERRUPT(void)
+{
+	return (S3C64XX_INTERRUPT *)ELFIN_VIC0_BASE_ADDR;
+}
+static inline S3C64XX_DMAS * S3C64XX_GetBase_DMAS(void)
+{
+	return (S3C64XX_DMAS *)ELFIN_DMA_BASE;
+}
+static inline S3C64XX_CLOCK_POWER * S3C64XX_GetBase_CLOCK_POWER(void)
+{
+	return (S3C64XX_CLOCK_POWER *)ELFIN_CLOCK_POWER_BASE;
+}
+static inline S3C64XX_LCD * S3C64XX_GetBase_LCD(void)
+{
+	return (S3C64XX_LCD *)ELFIN_LCD_BASE;
+}
+/*
+static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
+{
+	return (S3C2410_NAND *)ELFIN_NAND_BASE;
+}
+*/
+static inline S3C64XX_UART * S3C64XX_GetBase_UART(S3C64XX_UARTS_NR nr)
+{
+//	return (S3C64XX_UART *)(ELFIN_UART_BASE + (nr * 0x4000));
+	return (S3C64XX_UART *)(ELFIN_UART_BASE + (nr*0x400));
+}
+static inline S3C64XX_TIMERS * S3C64XX_GetBase_TIMERS(void)
+{
+	return (S3C64XX_TIMERS *)ELFIN_TIMER_BASE;
+}
+/*
+static inline S3C64XX_USB_DEVICE * S3C64XX_GetBase_USB_DEVICE(void)
+{
+	return (S3C64XX_USB_DEVICE *)ELFIN_USB_DEVICE_BASE;
+}
+*/
+static inline S3C64XX_WATCHDOG * S3C64XX_GetBase_WATCHDOG(void)
+{
+	return (S3C64XX_WATCHDOG *)ELFIN_WATCHDOG_BASE;
+}
+static inline S3C64XX_I2C * S3C64XX_GetBase_I2C(void)
+{
+	return (S3C64XX_I2C *)ELFIN_I2C_BASE;
+}
+static inline S3C64XX_I2S * S3C64XX_GetBase_I2S(void)
+{
+	return (S3C64XX_I2S *)ELFIN_I2S_BASE;
+}
+static inline S3C64XX_GPIO * S3C64XX_GetBase_GPIO(void)
+{
+	return (S3C64XX_GPIO *)ELFIN_GPIO_BASE;
+}
+static inline S3C64XX_RTC * S3C64XX_GetBase_RTC(void)
+{
+	return (S3C64XX_RTC *)ELFIN_RTC_BASE;
+}
+static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
+{
+	return (S3C2410_ADC *)ELFIN_ADC_BASE;
+}
+static inline S3C64XX_SPI * S3C64XX_GetBase_SPI(void)
+{
+	return (S3C64XX_SPI *)ELFIN_SPI_BASE;
+}
+#if 0
+static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
+{
+	return (S3C2410_SDI *)ELFIN_SDI_BASE;
+}
+#endif
+#else /* #ifndef __ASSEMBLY__ */
+
+/* watchdog */
+#define WTCON_OFFSET		0x00
+
+/* LCD controller */
+#define LCDBGCON_OFFSET		0x5c
+
+#endif /* #ifndef __ASSEMBLY__ */
+
+/* PENDING BIT */
+#define BIT_EINT0		(0x1)
+#define BIT_EINT1		(0x1<<1)
+#define BIT_EINT2		(0x1<<2)
+#define BIT_EINT3		(0x1<<3)
+#define BIT_EINT4_7		(0x1<<4)
+#define BIT_EINT8_23		(0x1<<5)
+#define BIT_BAT_FLT		(0x1<<7)
+#define BIT_TICK		(0x1<<8)
+#define BIT_WDT			(0x1<<9)
+#define BIT_TIMER0		(0x1<<10)
+#define BIT_TIMER1		(0x1<<11)
+#define BIT_TIMER2		(0x1<<12)
+#define BIT_TIMER3		(0x1<<13)
+#define BIT_TIMER4		(0x1<<14)
+#define BIT_UART2		(0x1<<15)
+#define BIT_LCD			(0x1<<16)
+#define BIT_DMA0		(0x1<<17)
+#define BIT_DMA1		(0x1<<18)
+#define BIT_DMA2		(0x1<<19)
+#define BIT_DMA3		(0x1<<20)
+#define BIT_SDI			(0x1<<21)
+#define BIT_SPI0		(0x1<<22)
+#define BIT_UART1		(0x1<<23)
+#define BIT_USBH		(0x1<<26)
+#define BIT_IIC			(0x1<<27)
+#define BIT_UART0		(0x1<<28)
+#define BIT_SPI1		(0x1<<29)
+#define BIT_RTC			(0x1<<30)
+#define BIT_ADC			(0x1<<31)
+#define BIT_ALLMSK		(0xFFFFFFFF)
+
+#endif /*__S3C6410_H__*/
diff --git a/src/cpu/s3c2442/gta02.c b/src/cpu/s3c2442/gta02.c
new file mode 100644
index 0000000..1bda6bf
--- /dev/null
+++ b/src/cpu/s3c2442/gta02.c
@@ -0,0 +1,428 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: Andy Green <andy at openmoko.com>
+ *
+ * (port_init_gta02 came out of Openmoko U-Boot)
+ *
+ * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <qi.h>
+#include <neo_gta02.h>
+#include <serial-s3c24xx.h>
+#include <ports-s3c24xx.h>
+#include <i2c-bitbang-s3c24xx.h>
+#include <pcf50633.h>
+#include <glamo-init.h>
+
+#define GTA02_DEBUG_UART 2
+
+#define PCF50633_I2C_ADS 0x73
+
+struct pcf50633_init {
+	u8 index;
+	u8 value;
+};
+
+const struct pcf50633_init pcf50633_init[] = {
+
+	{ PCF50633_REG_OOCWAKE,		0xd3 }, /* wake from ONKEY,EXTON!,RTC,USB,ADP */
+	{ PCF50633_REG_OOCTIM1,		0xaa },	/* debounce 14ms everything */
+	{ PCF50633_REG_OOCTIM2,		0x4a },
+	{ PCF50633_REG_OOCMODE,		0x55 },
+	{ PCF50633_REG_OOCCTL,		0x47 },
+
+	{ PCF50633_REG_SVMCTL,		0x08 },	/* 3.10V SYS voltage thresh. */
+	{ PCF50633_REG_BVMCTL,		0x02 },	/* 2.80V BAT voltage thresh. */
+
+	{ PCF50633_REG_AUTOENA,		0x01 },	/* always on */
+
+	{ PCF50633_REG_DOWN1OUT,	0x1b }, /* 1.3V (0x1b * .025V + 0.625V) */
+	{ PCF50633_REG_DOWN1ENA,	0x02 }, /* enabled if GPIO1 = HIGH */
+	{ PCF50633_REG_HCLDOOUT,	21 },	/* 3.0V (21 * 0.1V + 0.9V) */
+	{ PCF50633_REG_HCLDOENA,	0x01 }, /* ON by default*/
+
+	{ PCF50633_REG_INT1M,		0x00 },
+	{ PCF50633_REG_INT2M,		0x00 },
+	{ PCF50633_REG_INT3M,		0x00 },
+	{ PCF50633_REG_INT4M,		0x00 },
+	{ PCF50633_REG_INT5M,		0x00 },
+
+	{ PCF50633_REG_MBCC2,		0x28 },	/* Vbatconid=2.7V, Vmax=4.20V */
+	{ PCF50633_REG_MBCC3,		0x19 },	/* 25/255 == 98mA pre-charge */
+	{ PCF50633_REG_MBCC4,		0xff }, /* 255/255 == 1A adapter fast */
+	{ PCF50633_REG_MBCC5,		0x19 },	/* 25/255 == 98mA soft-start usb fast */
+	{ PCF50633_REG_MBCC6,		0x00 }, /* cutoff current 1/32 * Ichg */
+	{ PCF50633_REG_MBCC7,		0x00 },	/* 1.6A max bat curr, USB 100mA */
+	{ PCF50633_REG_MBCC8,		0x00 },
+	{ PCF50633_REG_MBCC1,		0xff }, /* chgena */
+
+	{ PCF50633_REG_BBCCTL,		0x19 },	/* 3V, 200uA, on */
+	{ PCF50633_REG_OOCSHDWN,	0x04 },  /* defeat 8s death from lowsys on A5 */
+
+};
+
+static const struct board_variant board_variants[] = {
+	[0] = {
+		.name = "A5 PCB",
+		.machine_revision = 0x350,
+	},
+	[1] = {
+		.name = "A6 PCB",
+		.machine_revision = 0x360,
+	}
+};
+
+
+void port_init_gta02(void)
+{
+#if 0
+	unsigned int * MPLLCON = (unsigned int *)0x4c000004;
+	unsigned int * UPLLCON = (unsigned int *)0x4c000008;
+	unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
+#endif
+	int n;
+
+	//CAUTION:Follow the configuration order for setting the ports.
+	// 1) setting value(GPnDAT)
+	// 2) setting control register  (GPnCON)
+	// 3) configure pull-up resistor(GPnUP)
+
+	/* 32bit data bus configuration   */
+	/*
+	 * === PORT A GROUP
+	 *     Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
+	 *     Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
+	 *     Binary :  1     1      1  , 1   1   1    1   ,  1     1     1     1
+	 *     Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0
+	 *     Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
+	 *     Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      1
+	 */
+	rGPACON = 0x007E5FFF;
+	rGPADAT = 0x00000000;
+	/*
+	 * ===* PORT B GROUP
+	 *      Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0
+	 *      Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
+	 *      Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT
+	 *      Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01
+	 */
+	rGPBCON = 0x00155555;
+	rGPBUP = 0x000007FF;
+	rGPBDAT = 0x00000000;
+	/*
+	 * === PORT C GROUP
+	 *     Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0
+	 *     Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
+	 *     Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10
+	 */
+	rGPCCON = 0x55555155;
+	rGPCUP = 0x0000FFFF & ~(1 << 5);
+	rGPCDAT = (1 << 13) | (1 << 15); /* index detect -> hi */
+	/*
+	 * === PORT D GROUP
+	 *     Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
+	 *     Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8
+	 *     Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10
+	 */
+	rGPDCON = 0x55555555;
+	rGPDUP = 0x0000FFFF;
+	rGPDDAT = (1 << 0) | (1 << 3) | (1 << 4); /* index detect -> hi */
+	/*
+	 * === PORT E GROUP
+	 *     Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4
+	 *     Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
+	 *     Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,
+	 *     -------------------------------------------------------------------------------------------------------
+	 *     Ports  :  GPE3   GPE2  GPE1    GPE0
+	 *     Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
+	 *     Binary :  10     10  ,  10      10
+	 */
+	rGPECON = 0xAAAAAAAA;
+	rGPEUP = 0x0000FFFF & ~(1 << 11);
+	rGPEDAT = 0x00000000;
+	/*
+	 * === PORT F GROUP
+	 *     Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
+	 *     Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
+	 *     Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0
+	 *     Binary :  01      01 ,  01     01  ,     10       10  , 10     10
+	 */
+	/* pulldown on GPF03: TP-4705+debug - debug conn will float */
+	rGPFCON = 0x0000AAAA;
+	rGPFUP = 0x000000FF & ~(1 << 3);
+	rGPFDAT = 0x00000000;
+
+
+	/*
+	 * === PORT G GROUP
+	 *     Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6
+	 *     Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
+	 *     Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
+	 *     Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11
+	 *     -----------------------------------------------------------------------------------------
+	 *     Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0
+	 *     Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
+	 *     Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
+	 *     Binary :     11         11   ,  10      11  ,  10        10
+	 */
+	rGPGCON = 0x01AAFE79;
+	rGPGUP = 0x0000FFFF;
+	rGPGDAT = 0x00000000;
+
+	/*
+	 * === PORT H GROUP
+	 *     Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0
+	 *     Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
+	 *     Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10
+	 */
+	/* pulldown on GPH08: UEXTCLK, just floats!
+	 * pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
+	 * pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
+	 */
+	rGPHCON = 0x001AAAAA;
+	rGPHUP = 0x000007FF & ~(1 << 8) & ~(1 << 0) & ~(1 << 3);
+	rGPHDAT = 0x00000000;
+
+	/* pulldown on GPJ00: input, just floats! */
+	/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
+	rGPJCON = 0x1551544;
+	rGPJUP = 0x1ffff & ~(1 << 0) & ~(1 << 7);
+	rGPJDAT = 0x00000100;
+
+	rGPJDAT |= (1 << 4) | (1 << 6);
+					/* Set GPJ4 to high (nGSM_EN) */
+					/* Set GPJ6 to high (nDL_GSM) */
+	rGPJDAT &= ~(1 << 5);	/* Set GPJ5 to low 3D RST */
+
+	/* leaving Glamo forced to Reset# active here killed
+	 * U-Boot when you touched the memory region
+	 */
+
+	rGPJDAT |= (1 << 5);	/* Set GPJ5 to high 3D RST */
+
+
+	/*
+	 * We have to talk to the PMU a little bit
+	 */
+
+	for (n = 0; n < ARRAY_SIZE(pcf50633_init); n++)
+		i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS,
+			       pcf50633_init[n].index, pcf50633_init[n].value);
+
+#if 0
+	/* change CPU clocking to 400MHz 1:4:8 */
+
+	/* clock divide 1:4:8 - do it first */
+	*CLKDIVN = 5;
+	/* configure UPLL */
+	*UPLLCON = ((88 << 12) + (4 << 4) + 2);
+	/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
+	asm __volatile__ (
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+	);
+	/* configure MPLL */
+	*MPLLCON = ((42 << 12) + (1 << 4) + 0);
+
+	/* get debug UART working at 115kbps */
+	serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 50 /* 50MHz PCLK */);
+#else
+	serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 33 /* 33MHz PCLK */);
+#endif
+
+	/* we're going to use Glamo for SD Card access, so we need to init the
+	 * evil beast
+	 */
+	glamo_core_init();
+}
+
+/**
+ * returns PCB revision information in b9,b8 and b2,b1,b0
+ * Pre-GTA02 A6 returns 0x000
+ *     GTA02 A6 returns 0x001
+ */
+
+int gta02_get_pcb_revision(void)
+{
+	int n;
+	u32 u;
+
+	/* make C13 and C15 pulled-down inputs */
+	rGPCCON &= ~0xcc000000;
+	rGPCUP  &= ~((1 << 13) | (1 << 15));
+	/* D0, D3 and D4 pulled-down inputs */
+	rGPDCON &= ~0x000003c3;
+	rGPDUP  &= ~((1 << 0) | (1 << 3) | (1 << 4));
+
+	/* delay after changing pulldowns */
+	u = rGPCDAT;
+	u = rGPDDAT;
+
+	/* read the version info */
+	u = rGPCDAT;
+	n =  (u >> (13 - 0)) & 0x001;
+	n |= (u >> (15 - 1)) & 0x002;
+	u = rGPDDAT;
+	n |= (u << (0 + 2))  & 0x004;
+
+	n |= (u << (8 - 3))  & 0x100;
+	n |= (u << (9 - 4))  & 0x200;
+
+	/*
+	 * when not being interrogated, all of the revision GPIO
+	 * are set to output HIGH without pulldown so no current flows
+	 * if they are NC or pulled up.
+	 */
+	/* make C13 and C15 high ouputs with no pulldowns */
+	rGPCCON |= 0x44000000;
+	rGPCUP  |= (1 << 13) | (1 << 15);
+	rGPCDAT |= (1 << 13) | (1 << 15);
+	/* D0, D3 and D4 high ouputs with no pulldowns */
+	rGPDCON |= 0x00000141;
+	rGPDUP  |= (1 << 0) | (1 << 3) | (1 << 4);
+	rGPDDAT |= (1 << 0) | (1 << 3) | (1 << 4);
+
+	n &= 1;
+
+	return n;
+}
+
+int sd_card_init_gta02(void)
+{
+	extern int mmc_init(int verbose);
+
+	return mmc_init(1);
+}
+
+int sd_card_block_read_gta02(unsigned char * buf, unsigned long start512,
+							       int blocks512)
+{
+unsigned long mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt,
+								     void *dst);
+
+	return mmc_bread(0, start512, blocks512, buf);
+}
+
+/* return nonzero if we believe we run on GTA02 */
+
+int is_this_board_gta02(void)
+{
+	/* look for GTA02 NOR */
+
+	*(volatile unsigned short *)(0x18000000) = 0x98;
+
+	return !!(*(volatile unsigned short *)(0x18000000) == 0x0020);
+}
+
+const struct board_variant const * get_board_variant_gta02(void)
+{
+	return &board_variants[gta02_get_pcb_revision() & 1];
+}
+
+static void putc_gta02(char c)
+{
+	serial_putc_s3c24xx(GTA02_DEBUG_UART, c);
+}
+
+static void close_gta02(void)
+{
+	/* explicitly clear any pending 8s timeout */
+
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_OOCSHDWN, 0x04);
+
+	/* clear any pending timeouts by reading interrupts */
+
+	i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT1);
+	i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT2);
+	i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT3);
+	i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT4);
+	i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT5);
+
+	/* set I2C GPIO back to peripheral unit */
+
+	(bb_s3c24xx.close)();
+}
+
+/*
+ * our API for bootloader on this machine
+ */
+
+const struct board_api board_api_gta02 = {
+	.name = "Freerunner / GTA02",
+	.linux_machine_id = 1304,
+	.linux_mem_start = 0x30000000,
+	.linux_mem_size = (128 * 1024 * 1024),
+	.linux_tag_placement = 0x30000000 + 0x100,
+	.get_board_variant = get_board_variant_gta02,
+	.is_this_board = is_this_board_gta02,
+	.port_init = port_init_gta02,
+	.putc = putc_gta02,
+	.close = close_gta02,
+	/* these are the ways we could boot GTA02 in order to try */
+	.kernel_source = {
+		[0] = {
+			.name = "SD Card EXT2 Kernel",
+			.block_init = sd_card_init_gta02,
+			.block_read = sd_card_block_read_gta02,
+			.partition_index = 1,
+			.filesystem = FS_EXT2,
+			.filepath = "boot/uImage.bin",
+			.commandline = "mtdparts=physmap-flash:-(nor);" \
+					"neo1973-nand:" \
+					 "0x00040000(qi)," \
+					 "0x00040000(cmdline)," \
+					 "0x00800000(backupkernel)," \
+					 "0x000a0000(extra)," \
+					 "0x00040000(identity)," \
+					 "0x0f6a0000(backuprootfs) " \
+				       "rootfstype=ext3 " \
+				       "root=/dev/mmcblk0p1 " \
+				       "console=ttySAC2,115200 " \
+				       "loglevel=8 " \
+				       "init=/sbin/init "\
+				       "ro"
+		},
+		[1] = {
+			.name = "NAND Kernel",
+			.block_read = nand_read_ll,
+			.offset_blocks512_if_no_partition = 0x80000 / 512,
+			.filesystem = FS_RAW,
+			.commandline = "mtdparts=physmap-flash:-(nor);" \
+					"neo1973-nand:" \
+					 "0x00040000(qi)," \
+					 "0x00040000(cmdline)," \
+					 "0x00800000(backupkernel)," \
+					 "0x000a0000(extra)," \
+					 "0x00040000(identity)," \
+					 "0x0f6a0000(backuprootfs) " \
+				       "rootfstype=jffs2 " \
+				       "root=/dev/mtdblock6 " \
+				       "console=ttySAC2,115200 " \
+				       "loglevel=3 " \
+				       "init=/sbin/init "\
+				       "ro"
+		},
+	},
+};
diff --git a/src/cpu/s3c2442/gta03.c b/src/cpu/s3c2442/gta03.c
new file mode 100644
index 0000000..73fa268
--- /dev/null
+++ b/src/cpu/s3c2442/gta03.c
@@ -0,0 +1,289 @@
+#include <qi.h>
+#include <neo_gta03.h>
+#include <serial-s3c24xx.h>
+#include <ports-s3c24xx.h>
+#include <i2c-bitbang-s3c24xx.h>
+#include <pcf50633.h>
+#include <s3c24xx-mci.h>
+
+#define GTA03_DEBUG_UART 2
+
+#define PCF50633_I2C_ADS 0x73
+
+
+static const struct board_variant board_variants[] = {
+	[0] = {
+		.name = "EVB PCB",
+		.machine_revision = 0x010,
+	},
+};
+
+void port_init_gta03(void)
+{
+	unsigned int * MPLLCON = (unsigned int *)0x4c000004;
+	unsigned int * UPLLCON = (unsigned int *)0x4c000008;
+	unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
+
+	//CAUTION:Follow the configuration order for setting the ports.
+	// 1) setting value(GPnDAT)
+	// 2) setting control register  (GPnCON)
+	// 3) configure pull-up resistor(GPnUP)
+
+	/* 32bit data bus configuration   */
+	/*
+	 * === PORT A GROUP
+	 *     Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
+	 *     Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
+	 *     Binary :  1     1      1  , 1   1   1    1   ,  1     1     1     1
+	 *     Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0
+	 *     Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
+	 *     Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      1
+	 */
+	rGPACON = 0x007F8FFF;
+	/*
+	 * ===* PORT B GROUP
+	 *      Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0
+	 *      Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
+	 *      Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT
+	 *      Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01
+	 */
+	rGPBCON = 0x00145554;
+	rGPBDAT |= (1 <<9 );	/* USB_PULLUP */
+	rGPBUP = 0x000007FF;
+	/*
+	 * === PORT C GROUP
+	 *     Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0
+	 *     Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
+	 *     Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10
+	 */
+	rGPCCON = 0xAAA776E9;
+	rGPCUP = 0x0000FFFF;
+	rGPCDAT |= (1 << 9); /* WLAN_nRESET pull high */
+	/*
+	 * === PORT D GROUP
+	 *     Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
+	 *     Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8
+	 *     Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10
+	 */
+	rGPDCON = 0xAAA0AAA5;
+	rGPDUP = 0x0000FFFF;
+	/*
+	 * === PORT E GROUP
+	 *     Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4
+	 *     Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
+	 *     Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,
+	 *     -------------------------------------------------------------------------------------------------------
+	 *     Ports  :  GPE3   GPE2  GPE1    GPE0
+	 *     Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
+	 *     Binary :  10     10  ,  10      10
+	 */
+	rGPECON = 0xAAAAAAAA;
+	rGPEUP = 0x0000FFFF;
+	/*
+	 * === PORT F GROUP
+	 *     Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
+	 *     Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
+	 *     Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0
+	 *     Binary :  01      01 ,  01     01  ,     10       10  , 10     10
+	 */
+	rGPFCON = 0x0000AAAA;
+	rGPFUP = 0x000000FF;
+
+	/*
+	 * === PORT G GROUP
+	 *     Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6
+	 *     Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
+	 *     Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
+	 *     Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11
+	 *     -----------------------------------------------------------------------------------------
+	 *     Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0
+	 *     Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
+	 *     Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
+	 *     Binary :     11         11   ,  10      11  ,  10        10
+	 */
+	rGPGCON = 0x02A9FE5A;
+	rGPGUP = 0x0000FFFF;
+
+	/*
+	 * === PORT H GROUP
+	 *     Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0
+	 *     Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
+	 *     Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10
+	 */
+	/* pulldown on GPH08: UEXTCLK, just floats!
+	 * pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
+	 * pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
+	 */
+	rGPHCON = 0x0019A0AA;
+	rGPHUP = 0x000007FF;
+
+	/* pulldown on GPJ00: input, just floats! */
+	/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
+	rGPJCON = 0x02AAAAAA;
+	rGPJUP = 0x1FFFF;
+
+	/*
+	 * We have to talk to the PMU a little bit
+	 */
+
+	/* We need SD Card rail (HCLDO) at 3.0V */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOOUT,
+									    21);
+
+	/* switch HCLDO on */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOENA, 1);
+
+	/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
+									  0x2b);
+
+	/* change CPU clocking to 533MHz 1:4:8 */
+
+	/* clock divide 1:4:8 - do it first */
+	*CLKDIVN = 5;
+	/* configure UPLL */
+	*UPLLCON = ((88 << 12) + (4 << 4) + 2);
+	/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
+	asm __volatile__ (
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+	);
+	/* configure MPLL */
+	*MPLLCON = ((169 << 12) + (2 << 4) + 1);
+
+
+	serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
+}
+
+/**
+ * returns PCB revision information in b0, d8, d9
+ * GTA03 EVB returns 0x000
+ * GTA03 returns 0x001
+ */
+
+int gta03_get_pcb_revision(void)
+{
+	int n;
+	u32 u;
+
+	/* make B0 inputs */
+	rGPBCON &= ~0x00000003;
+	/* D8 and D9 inputs */
+	rGPDCON &= ~0x000f0000;
+
+	/* delay after changing pulldowns */
+	u = rGPBDAT;
+	u = rGPDDAT;
+
+	/* read the version info */
+	u = rGPBDAT;
+	n = (u >> (0 - 0))& 0x001;
+	u = rGPDDAT;
+	n |= (u >> (8 -1))  & 0x002;
+	n |= (u >> (9 - 2))  & 0x004;
+
+	/*
+	 * when not being interrogated, all of the revision GPIO
+	 * are set to output
+	 */
+	/* make B0 high ouput */
+	rGPBCON |= 0x00000001;
+	/* D8 and D9 high ouputs */
+	rGPDCON |= 0x00050000;
+
+	return n;
+
+}
+
+const struct board_variant const * get_board_variant_gta03(void)
+{
+	return &board_variants[gta03_get_pcb_revision()];
+}
+
+int is_this_board_gta03(void)
+{
+	/* FIXME: find something gta03 specific */
+	return 1;
+}
+
+static void putc_gta03(char c)
+{
+	serial_putc_s3c24xx(GTA03_DEBUG_UART, c);
+}
+
+int sd_card_init_gta03(void)
+{
+	return s3c24xx_mmc_init(1);
+}
+
+int sd_card_block_read_gta03(unsigned char * buf, unsigned long start512,
+							       int blocks512)
+{
+	return s3c24xx_mmc_bread(0, start512, blocks512, buf);
+}
+
+
+
+/*
+ * our API for bootloader on this machine
+ */
+const struct board_api board_api_gta03 = {
+	.name = "GTA03-2442",
+	.linux_machine_id = 1866,
+	.linux_mem_start = 0x30000000,
+	.linux_mem_size = (128 * 1024 * 1024),
+	.linux_tag_placement = 0x30000000 + 0x100,
+	.get_board_variant = get_board_variant_gta03,
+	.is_this_board = is_this_board_gta03,
+	.port_init = port_init_gta03,
+	.putc = putc_gta03,
+	/* these are the ways we could boot GTA03 in order to try */
+	.kernel_source = {
+		[0] = {
+			.name = "SD Card EXT2 Kernel",
+			.block_init = sd_card_init_gta03,
+			.block_read = sd_card_block_read_gta03,
+			.partition_index = 1,
+			.filesystem = FS_EXT2,
+			.filepath = "boot/uImage.bin",
+			.commandline = "mtdparts=physmap-flash:-(nor);" \
+					"neo1973-nand:" \
+					 "0x00040000(qi)," \
+					 "0x00040000(cmdline)," \
+					 "0x00800000(backupkernel)," \
+					 "0x000a0000(extra)," \
+					 "0x00040000(identity)," \
+					 "0x0f6a0000(backuprootfs) " \
+				       "rootfstype=ext2 " \
+				       "root=/dev/mmcblk0p1 " \
+				       "console=ttySAC2,115200 " \
+				       "loglevel=4 " \
+				       "init=/sbin/init "\
+				       "ro"
+		},
+		[1] = {
+			.name = "NAND Kernel",
+			.block_read = nand_read_ll,
+			.offset_blocks512_if_no_partition = 0x80000 / 512,
+			.filesystem = FS_RAW,
+			.commandline = 	"mtdparts=neo1973-nand:" \
+					 "0x00040000(qi)," \
+					 "0x00040000(cmdline)," \
+					 "0x00800000(backupkernel)," \
+					 "0x000a0000(extra)," \
+					 "0x00040000(identity)," \
+					 "0x0f6a0000(backuprootfs) " \
+				       "rootfstype=jffs2 " \
+				       "root=/dev/mtdblock6 " \
+				       "console=ttySAC2,115200 " \
+				       "loglevel=4 " \
+				       "init=/sbin/init "\
+				       "ro"
+		},
+	},
+};
diff --git a/src/cpu/s3c2442/nand_read.c b/src/cpu/s3c2442/nand_read.c
new file mode 100644
index 0000000..cb2a2de
--- /dev/null
+++ b/src/cpu/s3c2442/nand_read.c
@@ -0,0 +1,153 @@
+/*
+ * nand_read.c: Simple NAND read functions for booting from NAND
+ *
+ * This is used by cpu/arm920/start.S assembler code,
+ * and the board-specific linker script must make sure this
+ * file is linked within the first 4kB of NAND flash.
+ *
+ * Taken from GPLv2 licensed vivi bootloader,
+ * Copyright (C) 2002 MIZI Research, Inc.
+ *
+ * Author: Hwang, Chideok <hwang at mizi.com>
+ * Date  : $Date: 2004/02/04 10:37:37 $
+ *
+ * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge at openmoko.org>
+ */
+
+/* NOTE this stuff runs in steppingstone context! */
+
+/* the API refers to 512-byte blocks */
+
+#include <qi.h>
+#include "nand_read.h"
+
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READSTART 0x30
+
+#define __REGb(x)	(*(volatile unsigned char *)(x))
+#define __REGw(x)	(*(volatile unsigned short *)(x))
+#define __REGi(x)	(*(volatile unsigned int *)(x))
+#define NF_BASE		0x4e000000
+#define NFCONF		__REGi(NF_BASE + 0x0)
+#define NFCONT		__REGi(NF_BASE + 0x4)
+#define NFCMD		__REGb(NF_BASE + 0x8)
+#define NFADDR		__REGb(NF_BASE + 0xc)
+#define NFDATA		__REGb(NF_BASE + 0x10)
+#define NFDATA16	__REGw(NF_BASE + 0x10)
+#define NFSTAT		__REGb(NF_BASE + 0x20)
+#define NFSTAT_BUSY	1
+#define nand_select()	(NFCONT &= ~(1 << 1))
+#define nand_deselect()	(NFCONT |= (1 << 1))
+#define nand_clear_RnB()	(NFSTAT |= (1 << 2))
+
+static inline void nand_wait(void)
+{
+	int i;
+
+	while (!(NFSTAT & NFSTAT_BUSY))
+		for (i=0; i<10; i++);
+}
+
+/* configuration for 2440 with 2048byte sized flash */
+#define NAND_5_ADDR_CYCLE
+#define NAND_PAGE_SIZE		2048
+#define BAD_BLOCK_OFFSET	NAND_PAGE_SIZE
+#define	NAND_BLOCK_MASK		(NAND_PAGE_SIZE - 1)
+#define NAND_BLOCK_SIZE		(NAND_PAGE_SIZE * 64)
+
+static int is_bad_block(unsigned long block_index)
+{
+	unsigned char data;
+	unsigned long page_num;
+
+	nand_clear_RnB();
+	page_num = block_index >> 2; /* addr / 2048 */
+	NFCMD = NAND_CMD_READ0;
+	NFADDR = BAD_BLOCK_OFFSET & 0xff;
+	NFADDR = (BAD_BLOCK_OFFSET >> 8) & 0xff;
+	NFADDR = page_num & 0xff;
+	NFADDR = (page_num >> 8) & 0xff;
+	NFADDR = (page_num >> 16) & 0xff;
+	NFCMD = NAND_CMD_READSTART;
+	nand_wait();
+	data = (NFDATA & 0xff);
+
+	if (data != 0xff)
+		return 1;
+
+	return 0;
+}
+
+static int nand_read_page_ll(unsigned char *buf, unsigned long block512)
+{
+	unsigned short *ptr16 = (unsigned short *)buf;
+	unsigned int i, page_num;
+#if 0
+	unsigned char ecc[64];
+	unsigned short *p16 = (unsigned short *)ecc;
+#endif
+
+	nand_clear_RnB();
+
+	NFCMD = NAND_CMD_READ0;
+
+	page_num = block512 >> 2; /* 512 block -> 2048 block */
+	/* Write Address */
+	NFADDR = 0;
+	NFADDR = 0;
+	NFADDR = page_num & 0xff;
+	NFADDR = (page_num >> 8) & 0xff;
+	NFADDR = (page_num >> 16) & 0xff;
+	NFCMD = NAND_CMD_READSTART;
+	nand_wait();
+
+	for (i = 0; i < NAND_PAGE_SIZE/2; i++)
+		*ptr16++ = NFDATA16;
+#if 0
+	for (i = 0; i < 64 / 2; i++) {
+		*p16++ = NFDATA16;
+	}
+#endif
+	return 4;
+}
+
+/* low level nand read function */
+int nand_read_ll(unsigned char *buf, unsigned long start_block512,
+								  int blocks512)
+{
+	int i, j;
+	int bad_count = 0;
+
+	if (start_block512 & 3) /* inside 2048-byte block */
+		return -1;
+
+	/* chip Enable */
+	nand_select();
+	nand_clear_RnB();
+
+	for (i = 0; i < 10; i++)
+		;
+
+	while (blocks512 > 0) {
+		if (is_bad_block(start_block512) ||
+				is_bad_block(start_block512 + 4)) {
+			start_block512 += 4;
+			blocks512 += 4;
+			if (bad_count++ == 4)
+				return -1;
+			continue;
+		}
+
+		j = nand_read_page_ll(buf, start_block512);
+		start_block512 += j;
+		buf += j << 9;
+		blocks512 -= j;
+	}
+
+	/* chip Disable */
+	nand_deselect();
+
+	return 0;
+}
+
diff --git a/src/cpu/s3c2442/nand_read.h b/src/cpu/s3c2442/nand_read.h
new file mode 100644
index 0000000..71aeda5
--- /dev/null
+++ b/src/cpu/s3c2442/nand_read.h
@@ -0,0 +1,22 @@
+/*
+ * nand_read.c: Simple NAND read functions for booting from NAND
+ *
+ * This is used by cpu/arm920/start.S assembler code,
+ * and the board-specific linker script must make sure this
+ * file is linked within the first 4kB of NAND flash.
+ *
+ * Taken from GPLv2 licensed vivi bootloader,
+ * Copyright (C) 2002 MIZI Research, Inc.
+ *
+ * Author: Hwang, Chideok <hwang at mizi.com>
+ * Date  : $Date: 2004/02/04 10:37:37 $
+ *
+ * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge at openmoko.org>
+ */
+#ifndef __NAND_READ_H
+#define __NAND_READ_H
+
+int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size);
+
+#endif /* __NAND_READ_H */
diff --git a/src/cpu/s3c2442/qi.lds b/src/cpu/s3c2442/qi.lds
new file mode 100644
index 0000000..504b130
--- /dev/null
+++ b/src/cpu/s3c2442/qi.lds
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	/* this is intended to take the first 4KBytes of stuff initially.
+	 * We have to make sure we have .rodata* in there for everything
+	 * because we do not compile PIC.
+	 */
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  src/cpu/s3c2442/start.o	(.text .rodata* .data)
+	  src/lowlevel_init.o		(.text .rodata* .data)
+	  src/cpu/s3c2442/start_qi.o	(.text .rodata* .data)
+	  src/blink_led.o		(.text .rodata* .data)
+	  src/cpu/s3c2442/nand_read.o	(.text .rodata* .data)
+	  src/drivers/serial-s3c24xx.o	(.text .rodata* .data)
+	}
+
+	. = ALIGN(4);
+	.everything_else  ADDR (.text) + SIZEOF (.text) + 0x33000000 :
+		AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) }
+
+	. = 0x33800000 ;
+	__bss_start = .;
+	.bss (NOLOAD) : 
+    { 
+        *(.bss) 
+    }
+
+	_end = .;
+}
diff --git a/src/cpu/s3c2442/start.S b/src/cpu/s3c2442/start.S
new file mode 100644
index 0000000..9961d8f
--- /dev/null
+++ b/src/cpu/s3c2442/start.S
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * 
+ * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define __ASM_MODE__
+#define __ASSEMBLY__
+
+#include <neo_gta02.h>
+
+#define S3C2410_MISCCR_nEN_SCLK0    (1 << 17)
+#define S3C2410_MISCCR_nEN_SCLK1    (1 << 18)
+#define S3C2410_MISCCR_nEN_SCLKE    (1 << 19)
+
+
+.globl _start, processor_id, is_jtag
+
+_start:	b       start_code
+/* if we are injected by JTAG, the script sets _istag content to nonzero */
+is_jtag:
+	.word	0
+
+/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
+ * we need to go through this hassle because before this moment, SDRAM is not
+ * working so we can't prep it from JTAG
+ */
+
+_steppingstone_done:
+	ldr	pc, _start_armboot
+
+_start_armboot:
+	.word 	start_qi
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+processor_id:
+	.word	0
+	.word	0x41129200 /* s3c2442 ID */
+	.word	0x410fb760 /* s3c6410 ID */
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+start_code:	
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+# define pWTCON		0x53000000
+
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+# define INTSUBMSK	0x4A00001C
+# define INTSUBMSK_val 	0x0000ffff
+
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+
+	ldr	r1, =INTSUBMSK_val
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+
+
+	/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
+# define CAMDIVN     	0x4C000018
+
+	ldr	r0, =CAMDIVN
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* Clock asynchronous mode */
+	mrc	p15, 0, r1, c1, c0, 0
+	orr	r1, r1, #0xc0000000
+	mcr	p15, 0, r1, c1, c0, 0
+
+#define LOCKTIME	0x4c000000
+
+	ldr	r0, =LOCKTIME
+	mov	r1, #0xffffff
+	str	r1, [r0]
+	
+# define UPLLCON	0x4c000008
+# define MPLLCON_val 	((142 << 12) + (7 << 4) + 1)
+# define UPLLCON_val   	(( 88 << 12) + (8 << 4) + 2)
+	
+	ldr	r0, =UPLLCON
+	ldr	r1, =UPLLCON_val
+	str	r1, [r0]
+
+	/* Page 7-19, seven nops between UPLL and MPLL */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	ldr	r1, =MPLLCON_val
+	str	r1, [r0, #-4]		/* MPLLCON */
+
+# define CLKDIVN	0x4C000014	/* clock divisor register */
+# define CLKDIVN_val  	7 /* FCLK:HCLK:PCLK = 1:3:6 */
+
+	/* FCLK:HCLK:PCLK = 1:3:6 */
+	ldr	r0, =CLKDIVN
+	mov	r1, #CLKDIVN_val
+	str	r1, [r0]
+
+	/* enable only CPU peripheral block clocks we actually use */
+	ldr	r0, =0x4c00000c		/* clkcon */
+	ldr	r1, =0x3f10	/* uart, pwm, gpio, nand, sdi clocks on */
+	str	r1, [r0]
+
+	/* gpio UART2 init, H port */
+	ldr	r0, =0x56000070
+	ldr	r1, =0x001AAAAA
+	str	r1, [r0]
+
+	/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
+	ldr	r0, =0x56000000	/* GPJ base */
+	ldr	r1, [r0, #0xd0]	/* GPJCON */
+	orr	r1, r1, #(1 << 16)
+	str	r1, [r0, #0xd0]
+
+	ldr	r1, [r0, #0xd4]	/* GPJDAT */
+	orr	r1, r1, #(1 << 8)
+	str	r1, [r0, #0xd4]
+
+
+	/* init uart2 */
+	ldr	r0, =0x50008000
+	mov	r1, #0x03
+	str	r1, [r0]
+	ldr	r1, =0x245
+	str	r1, [r0, #0x04]
+	mov	r1, #0x00
+	str	r1, [r0, #0x08]
+	mov	r1, #0x00
+	str	r1, [r0, #0x0c] 
+	mov	r1, #0x11
+	str	r1, [r0, #0x28]
+
+	ldr	r0, =0x50008000
+	ldr	r1, =0x54
+	str	r1, [r0, #0x20]
+
+/* reset nand controller, or it is dead to us */
+
+        mov     r1, #0x4E000000
+        ldr     r2, =0xfff0             @ initial value tacls=3,rph0=7,rph1=7
+        ldr     r3, [r1, #0]
+        orr     r3, r3, r2
+        str     r3, [r1, #0]
+
+        ldr     r3, [r1, #4]
+        orr     r3, r3, #1              @ enable nand controller
+        str     r3, [r1, #4]
+
+
+	/* take sdram out of power down */
+	ldr	r0, =0x56000080		/* misccr */
+	ldr	r1, [ r0 ]
+	bic	r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
+	str	r1, [ r0 ]
+
+	/* ensure signals stabalise */
+	mov	r1, #128
+1:	subs	r1, r1, #1
+	bpl	1b
+
+	bl	cpu_init_crit
+
+	/* ensure some refresh has happened */
+	ldr	r1, =0xfffff
+1:	subs	r1, r1, #1
+	bpl	1b
+
+	/* capture full EINT situation into gstatus 4 */
+
+	ldr	r0, =0x4A000000 /* SRCPND */
+	ldr	r1, [ r0 ]
+	and	r1, r1, #0xf
+
+	ldr	r0, =0x560000BC /* gstatus4 */
+	str	r1, [ r0 ]
+
+	ldr	r0, =0x560000A8 /* EINTPEND */
+	ldr	r1, [ r0 ]
+	ldr	r0, =0xfff0
+	and	r1, r1, r0
+	ldr	r0, =0x560000BC /* gstatus4 */
+	ldr     r0, [ r0 ]
+	orr	r1, r1, r0
+	ldr	r0, =0x560000BC /* gstatus4 */
+	str	r1, [ r0 ]
+
+	/* test for resume */
+
+	ldr	r1, =0x560000B4		/* gstatus2 */
+	ldr	r0, [ r1 ]
+	tst	r0, #0x02		/* is this resume from power down */
+					/* well, if it was, we are going to jump to
+					 * whatever address we stashed in gstatus3,
+					 * and gstatus4 will hold the wake interrupt
+					 * source for the OS to look at
+					 */
+	ldrne	pc, [r1, #4]
+
+
+								/* >> CFG_VIDEO_LOGO_MAX_SIZE */
+#define CFG_GBL_DATA_SIZE		128			/* size in bytes reserved for initial data */
+
+stack_setup:
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_GBL_DATA_SIZE 	/* bdinfo                        */
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000	/* clear                            */
+
+clbss_l:
+	str	r2, [r0]			/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	ble	clbss_l
+
+/* we are going to jump into the C part of the init now */
+spin:
+	b	_steppingstone_done
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+cpu_init_crit:
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependend, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	mov	ip, lr
+ 
+	bl	lowlevel_init
+
+	mov	lr, ip
+	mov	pc, lr
+
diff --git a/src/cpu/s3c2442/start_qi.c b/src/cpu/s3c2442/start_qi.c
new file mode 100644
index 0000000..ff479b6
--- /dev/null
+++ b/src/cpu/s3c2442/start_qi.c
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: xiangfu liu <xiangfu at openmoko.org>
+ *         Andy Green <andy at openmoko.com>
+ *
+ * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* NOTE this stuff runs in steppingstone context! */
+
+
+#include <qi.h>
+#include "nand_read.h"
+#include <neo_gta02.h>
+#include <neo_gta03.h>
+
+extern void bootloader_second_phase(void);
+
+const struct board_api *boards[] = {
+			&board_api_gta02,
+			&board_api_gta03,
+			NULL /* always last */
+};
+
+
+struct board_api const * this_board;
+extern int is_jtag;
+
+void start_qi(void)
+{
+	int flag = 0;
+	int board = 0;
+
+	/*
+	 * well, we can be running on this CPU two different ways.
+	 *
+	 * 1) We were copied into steppingstone and TEXT_BASE already
+	 *    by JTAG.  We don't have to do anything else.  JTAG script
+	 *    then sets data at address 0x4 to 0xffffffff as a signal we
+	 *    are running by JTAG.
+	 *
+	 * 2) We only got our first 4K into steppingstone, we need to copy
+	 *    the rest of ourselves into TEXT_BASE.
+	 *
+	 * So we do the copy out of NAND only if we see we did not come up
+	 * under control of JTAG.
+	 */
+
+	if (!is_jtag)
+		/*
+		* We got the first 4KBytes of the bootloader pulled into the
+		* steppingstone SRAM for free.  Now we pull the whole bootloader
+		* image into SDRAM.
+		*
+		* This code and the .S files are arranged by the linker script
+		* to expect to run from 0x0.  But the linker script has told
+		* everything else to expect to run from 0x33000000+.  That's
+		* why we are going to be able to copy this code and not have it
+		* crash when we run it from there.
+		*/
+
+		/* We randomly pull 32KBytes of bootloader */
+		if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0)
+			goto unhappy;
+
+	/* ask all the boards we support in turn if they recognize this
+	 * hardware we are running on, accept the first positive answer
+	 */
+
+	this_board = boards[board];
+	while (!flag && this_board) {
+
+		/* check if it is the right board... */
+		if (this_board->is_this_board()) {
+			flag = 1;
+			continue;
+		}
+
+		this_board = boards[board++];
+	}
+
+	/*
+	 * jump to bootloader_second_phase() running from DRAM copy
+	 */
+	bootloader_second_phase();
+
+unhappy:
+	while(1)
+		;
+
+}
diff --git a/src/cpu/s3c6410/qi.lds b/src/cpu/s3c6410/qi.lds
new file mode 100644
index 0000000..14051a4
--- /dev/null
+++ b/src/cpu/s3c6410/qi.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	/* this is intended to take the first 4KBytes of stuff initially.
+	 * We have to make sure we have .rodata* in there for everything
+	 * because we do not compile PIC.
+	 */
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  src/cpu/s3c6410/start.o	(.text .rodata* .data)
+	  src/lowlevel_init.o		(.text .rodata* .data)
+	  src/cpu/s3c6410/start_qi.o	(.text .rodata* .data)
+	  src/blink_led.o		(.text .rodata* .data)
+	}
+
+	. = ALIGN(4);
+	.everything_else  ADDR (.text) + SIZEOF (.text) + 0x53000000 :
+		AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) }
+
+	. = 0x53800000 ;
+	__bss_start = .;
+	.bss_6410 (NOLOAD) :
+    {
+        * (.bss)
+    }
+	_end = .;
+}
diff --git a/src/cpu/s3c6410/start.S b/src/cpu/s3c6410/start.S
new file mode 100644
index 0000000..7cb429e
--- /dev/null
+++ b/src/cpu/s3c6410/start.S
@@ -0,0 +1,548 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * 
+ * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define __ASM_MODE__
+#define __ASSEMBLY__
+
+#include <s3c6410.h>
+
+#define TEXT_BASE 0x53000000
+
+
+#define S3C6410_POP_A 0
+
+#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* fixed MPLL 533MHz */
+#define MPLL_MDIV	266
+#define MPLL_PDIV	3
+#define MPLL_SDIV	1
+
+#define Startup_APLLdiv		0
+#define APLL_MDIV	266
+#define APLL_PDIV	3
+#define APLL_SDIV	1
+#define	Startup_PCLKdiv		3
+#define Startup_HCLKdiv		1
+#define Startup_MPLLdiv		1
+#define Startup_HCLKx2div	1
+#define Startup_APLL	(12000000/(APLL_PDIV<<APLL_SDIV)*APLL_MDIV)
+#define Startup_HCLK	(Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
+
+#define CLK_DIV_VAL	((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
+#define APLL_VAL	set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+#define MPLL_VAL	set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+#if S3C6410_POP_A
+
+#define DMC1_MEM_CFG		0x00210011	/* Supports one CKE control, Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2		0xB41
+#define DMC1_CHIP0_CFG		0x150FC
+#define DMC1_CHIP1_CFG		0x154FC
+#define DMC_DDR_32_CFG		0x0		/* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH		5865		/* ns */
+#define DDR_tRAS		50		/* ns (min: 45ns)*/
+#define DDR_tRC 		68		/* ns (min: 67.5ns)*/
+#define DDR_tRCD		23		/* ns (min: 22.5ns)*/
+#define DDR_tRFC		133		/* ns (min: 80ns)*/
+#define DDR_tRP 		23		/* ns (min: 22.5ns)*/
+#define DDR_tRRD		20		/* ns (min: 15ns)*/
+#define DDR_tWR 		20		/* ns (min: 15ns)*/
+#define DDR_tXSR		125		/* ns (min: 120ns)*/
+#define DDR_CASL		3		/* CAS Latency 3 */
+
+#else
+
+#define DMC1_MEM_CFG		0x00010012	/* Supports one CKE control, Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2		0xB45
+#define DMC1_CHIP0_CFG		0x150F8
+#define DMC_DDR_32_CFG		0x0 		/* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH		7800		/* ns */
+#define DDR_tRAS		45		/* ns (min: 45ns)*/
+#define DDR_tRC 		68		/* ns (min: 67.5ns)*/
+#define DDR_tRCD		23		/* ns (min: 22.5ns)*/
+#define DDR_tRFC		80		/* ns (min: 80ns)*/
+#define DDR_tRP 		23		/* ns (min: 22.5ns)*/
+#define DDR_tRRD		15		/* ns (min: 15ns)*/
+#define DDR_tWR 		15		/* ns (min: 15ns)*/
+#define DDR_tXSR		120		/* ns (min: 120ns)*/
+#define DDR_CASL		3		/* CAS Latency 3 */
+
+#endif
+
+
+/*
+ * mDDR memory configuration
+ */
+#define DMC_DDR_BA_EMRS 	2
+#define DMC_DDR_MEM_CASLAT	3
+#define DMC_DDR_CAS_LATENCY	(DDR_CASL<<1)						//6   Set Cas Latency to 3
+#define DMC_DDR_t_DQSS		1							// Min 0.75 ~ 1.25
+#define DMC_DDR_t_MRD		2							//Min 2 tck
+#define DMC_DDR_t_RAS		(((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1)	//7, Min 45ns
+#define DMC_DDR_t_RC		(((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1) 	//10, Min 67.5ns
+#define DMC_DDR_t_RCD		(((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1) 	//4,5(TRM), Min 22.5ns
+#define DMC_DDR_schedule_RCD	((DMC_DDR_t_RCD - 3) << 3)
+#define DMC_DDR_t_RFC		(((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1) 	//11,18(TRM) Min 80ns
+#define DMC_DDR_schedule_RFC	((DMC_DDR_t_RFC - 3) << 5)
+#define DMC_DDR_t_RP		(((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1) 	//4, 5(TRM) Min 22.5ns
+#define DMC_DDR_schedule_RP	((DMC_DDR_t_RP - 3) << 3)
+#define DMC_DDR_t_RRD		(((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1)	//3, Min 15ns
+#define DMC_DDR_t_WR		(((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1)	//Min 15ns
+#define DMC_DDR_t_WTR		2
+#define DMC_DDR_t_XP		2							//1tck + tIS(1.5ns)
+#define DMC_DDR_t_XSR		(((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1)	//17, Min 120ns
+#define DMC_DDR_t_ESR		DMC_DDR_t_XSR
+#define DMC_DDR_REFRESH_PRD	(((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000) 	// TRM 2656
+#define DMC_DDR_USER_CONFIG	1							// 2b01 : mDDR
+
+
+.globl _start, processor_id, is_jtag
+
+_start:	b       start_code
+/* if we are injected by JTAG, the script sets _istag content to nonzero */
+is_jtag:
+	.word	0
+
+/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
+ * we need to go through this hassle because before this moment, SDRAM is not
+ * working so we can't prep it from JTAG
+ */
+
+_steppingstone_done:
+	ldr	pc, _start_armboot
+
+_start_armboot:
+	.word 	start_qi
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+processor_id:
+	.word	0
+	.word	0x41129200 /* s3c2442 ID */
+	.word	0x410fb760 /* s3c6410 ID */
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+start_code:	
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* Peri port setup */
+	ldr	r0, =0x70000000
+	orr	r0, r0, #0x13
+    	mcr	p15,0,r0,c15,c2,4       @ 256M(0x70000000-0x7fffffff)
+
+	ldr	r0, =ELFIN_MEM_SYS_CFG			@Memory sussystem address 0x7e00f120
+	mov	r1, #0xd				@ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1
+	str	r1, [r0]
+
+	ldr	r0, =ELFIN_DMC1_BASE			@DMC1 base address 0x7e001000
+
+	ldr	r1, =0x04
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+	ldr	r1, =DMC_DDR_REFRESH_PRD
+	str	r1, [r0, #INDEX_DMC_REFRESH_PRD]
+
+	ldr	r1, =DMC_DDR_CAS_LATENCY
+	str	r1, [r0, #INDEX_DMC_CAS_LATENCY]
+
+	ldr	r1, =DMC_DDR_t_DQSS
+	str	r1, [r0, #INDEX_DMC_T_DQSS]
+
+	ldr	r1, =DMC_DDR_t_MRD
+	str	r1, [r0, #INDEX_DMC_T_MRD]
+
+	ldr	r1, =DMC_DDR_t_RAS
+	str	r1, [r0, #INDEX_DMC_T_RAS]
+
+	ldr	r1, =DMC_DDR_t_RC
+	str	r1, [r0, #INDEX_DMC_T_RC]
+
+	ldr	r1, =DMC_DDR_t_RCD
+	ldr	r2, =DMC_DDR_schedule_RCD
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RCD]
+
+	ldr	r1, =DMC_DDR_t_RFC
+	ldr	r2, =DMC_DDR_schedule_RFC
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RFC]
+
+	ldr	r1, =DMC_DDR_t_RP
+	ldr	r2, =DMC_DDR_schedule_RP
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RP]
+
+	ldr	r1, =DMC_DDR_t_RRD
+	str	r1, [r0, #INDEX_DMC_T_RRD]
+
+	ldr	r1, =DMC_DDR_t_WR
+	str	r1, [r0, #INDEX_DMC_T_WR]
+
+	ldr	r1, =DMC_DDR_t_WTR
+	str	r1, [r0, #INDEX_DMC_T_WTR]
+
+	ldr	r1, =DMC_DDR_t_XP
+	str	r1, [r0, #INDEX_DMC_T_XP]
+
+	ldr	r1, =DMC_DDR_t_XSR
+	str	r1, [r0, #INDEX_DMC_T_XSR]
+
+	ldr	r1, =DMC_DDR_t_ESR
+	str	r1, [r0, #INDEX_DMC_T_ESR]
+
+	ldr	r1, =DMC1_MEM_CFG
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG]
+
+	ldr	r1, =DMC1_MEM_CFG2
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+
+	ldr	r1, =DMC1_CHIP0_CFG
+	str	r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+
+	ldr	r1, =DMC_DDR_32_CFG
+	str	r1, [r0, #INDEX_DMC_USER_CONFIG]
+
+	@DMC0 DDR Chip 0 configuration direct command reg
+	ldr	r1, =DMC_NOP0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Precharge All
+	ldr	r1, =DMC_PA0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Auto Refresh	2 time
+	ldr	r1, =DMC_AR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@MRS
+	ldr	r1, =DMC_mDDR_EMR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Mode Reg
+	ldr	r1, =DMC_mDDR_MR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+#if S3C6410_POP_A
+	ldr	r1, =DMC1_CHIP1_CFG
+	str	r1, [r0, #INDEX_DMC_CHIP_1_CFG]
+
+	@DMC0 DDR Chip 0 configuration direct command reg
+	ldr	r1, =DMC_NOP1
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Precharge All
+	ldr	r1, =DMC_PA1
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Auto Refresh	2 time
+	ldr	r1, =DMC_AR1
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@MRS
+	ldr	r1, =DMC_mDDR_EMR1
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	@Mode Reg
+	ldr	r1, =DMC_mDDR_MR1
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+#endif
+
+	@Enable DMC1
+	mov	r1, #0x0
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+check_dmc1_ready:
+	ldr	r1, [r0, #INDEX_DMC_MEMC_STATUS]
+	mov	r2, #0x3
+	and	r1, r1, r2
+	cmp	r1, #0x1
+	bne	check_dmc1_ready
+	nop
+
+	ldr	r0, =ELFIN_CLOCK_POWER_BASE	@0x7e00f000
+
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	mov	r2, #0x40
+	orr	r1, r1, r2
+	str	r1, [r0, #OTHERS_OFFSET]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	ldr	r2, =0x80
+	orr	r1, r1, r2
+	str	r1, [r0, #OTHERS_OFFSET]
+
+check_syncack:
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r2, =0xf00
+	and	r1, r1, r2
+	cmp	r1, #0xf00
+	bne	check_syncack
+
+	mov	r1, #0xff00
+	orr	r1, r1, #0xff
+	str	r1, [r0, #APLL_LOCK_OFFSET]
+	str	r1, [r0, #MPLL_LOCK_OFFSET]
+	str	r1, [r0, #EPLL_LOCK_OFFSET]
+/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
+/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */
+/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
+
+	ldr   	r1, [r0, #CLK_DIV2_OFFSET]
+	bic	r1, r1, #0x70000
+	orr	r1, r1, #0x30000
+	str	r1, [r0, #CLK_DIV2_OFFSET]
+
+
+	ldr   	r1, [r0, #CLK_DIV0_OFFSET]	/*Set Clock Divider*/
+	bic	r1, r1, #0x30000
+	bic	r1, r1, #0xff00
+	bic	r1, r1, #0xff
+	ldr	r2, =CLK_DIV_VAL
+	orr	r1, r1, r2
+	str	r1, [r0, #CLK_DIV0_OFFSET]
+
+	ldr	r1, =APLL_VAL
+	str	r1, [r0, #APLL_CON_OFFSET]
+	ldr	r1, =MPLL_VAL
+	str	r1, [r0, #MPLL_CON_OFFSET]
+
+	ldr	r1, =0x80200203			/* FOUT of EPLL is 96MHz */
+	str	r1, [r0, #EPLL_CON0_OFFSET]
+	ldr	r1, =0x0
+	str	r1, [r0, #EPLL_CON1_OFFSET]
+
+	ldr	r1, [r0, #CLK_SRC_OFFSET]	/* APLL, MPLL, EPLL select to Fout */
+
+	ldr	r2, =0x2007
+	orr	r1, r1, r2
+
+	str	r1, [r0, #CLK_SRC_OFFSET]
+
+	/* wait at least 200us to stablize all clock */
+	mov	r1, #0x10000
+1:	subs	r1, r1, #1
+	bne	1b
+
+	ldr	r1, [r0, #OTHERS_OFFSET]
+	orr	r1, r1, #0x20
+	str	r1, [r0, #OTHERS_OFFSET]
+
+
+	/* set GPIO to enable UART */
+	@ GPIO setting for UART
+	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r1, =0x220022
+	str   	r1, [r0, #GPACON_OFFSET]
+
+	ldr	r0, =ELFIN_UART_CONSOLE_BASE		@0x7F005000
+	mov	r1, #0x0
+	str	r1, [r0, #UFCON_OFFSET]
+	str	r1, [r0, #UMCON_OFFSET]
+
+	mov	r1, #0x3                	@was 0.
+	str	r1, [r0, #ULCON_OFFSET]
+
+	ldr	r1, =0xe45			/* UARTCLK SRC = 11 => EXT_UCLK1*/
+
+	str	r1, [r0, #UCON_OFFSET]
+
+	ldr	r1, =0x22
+	str	r1, [r0, #UBRDIV_OFFSET]
+
+	ldr	r1, =0x1FFF
+	str	r1, [r0, #UDIVSLOT_OFFSET]
+
+	ldr	r1, =0x4f4f4f4f
+	str	r1, [r0, #UTXH_OFFSET]		@'O'
+
+	/* send out a char to say hello */
+	ldr	r1, =0x55
+	str	r1, [r0, #UTXH_OFFSET]
+
+
+#if 0
+/* Below code is for ARM926EJS and ARM1026EJS */
+	.globl cleanDCache
+cleanDCache:
+	mrc	p15, 0, pc, c7, c10, 3	/* test/clean D-Cache */
+	bne	cleanDCache
+	mov	pc, lr
+
+	.globl cleanFlushDCache
+cleanFlushDCache:
+	mrc	p15, 0, pc, c7, c14, 3	/* test/cleanflush D-Cache */
+	bne	cleanFlushDCache
+	mov	pc, lr
+
+	.globl cleanFlushCache
+cleanFlushCache:
+	mrc	p15, 0, pc, c7, c14, 3	/* test/cleanflush D-Cache */
+	bne	cleanFlushCache
+	mcr	p15, 0, r0, c7, c5, 0	/* flush I-Cache */
+	mov	pc, lr
+
+	.ltorg
+#endif
+
+#if 0
+
+	/* enable only CPU peripheral block clocks we actually use */
+	ldr	r0, =0x4c00000c		/* clkcon */
+	ldr	r1, =0x3f10	/* uart, pwm, gpio, nand, sdi clocks on */
+	str	r1, [r0]
+
+	/* gpio UART2 init, H port */
+	ldr	r0, =0x56000070
+	ldr	r1, =0x001AAAAA
+	str	r1, [r0]
+
+	/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
+	ldr	r0, =0x56000000	/* GPJ base */
+	ldr	r1, [r0, #0xd0]	/* GPJCON */
+	orr	r1, r1, #(1 << 16)
+	str	r1, [r0, #0xd0]
+
+	ldr	r1, [r0, #0xd4]	/* GPJDAT */
+	orr	r1, r1, #(1 << 8)
+	str	r1, [r0, #0xd4]
+
+
+
+	/* take sdram out of power down */
+	ldr	r0, =0x56000080		/* misccr */
+	ldr	r1, [ r0 ]
+	bic	r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
+	str	r1, [ r0 ]
+
+	/* ensure signals stabalise */
+	mov	r1, #128
+1:	subs	r1, r1, #1
+	bpl	1b
+
+	bl	cpu_init_crit
+
+	/* ensure some refresh has happened */
+	ldr	r1, =0xfffff
+1:	subs	r1, r1, #1
+	bpl	1b
+
+	/* capture full EINT situation into gstatus 4 */
+
+	ldr	r0, =0x4A000000 /* SRCPND */
+	ldr	r1, [ r0 ]
+	and	r1, r1, #0xf
+
+	ldr	r0, =0x560000BC /* gstatus4 */
+	str	r1, [ r0 ]
+
+	ldr	r0, =0x560000A8 /* EINTPEND */
+	ldr	r1, [ r0 ]
+	ldr	r0, =0xfff0
+	and	r1, r1, r0
+	ldr	r0, =0x560000BC /* gstatus4 */
+	ldr     r0, [ r0 ]
+	orr	r1, r1, r0
+	ldr	r0, =0x560000BC /* gstatus4 */
+	str	r1, [ r0 ]
+
+	/* test for resume */
+
+	ldr	r1, =0x560000B4		/* gstatus2 */
+	ldr	r0, [ r1 ]
+	tst	r0, #0x02		/* is this resume from power down */
+					/* well, if it was, we are going to jump to
+					 * whatever address we stashed in gstatus3,
+					 * and gstatus4 will hold the wake interrupt
+					 * source for the OS to look at
+					 */
+	ldrne	pc, [r1, #4]
+
+#endif
+
+								/* >> CFG_VIDEO_LOGO_MAX_SIZE */
+#define CFG_GBL_DATA_SIZE		128			/* size in bytes reserved for initial data */
+
+stack_setup:
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_GBL_DATA_SIZE 	/* bdinfo                        */
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000	/* clear                            */
+
+clbss_l:
+	str	r2, [r0]			/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	ble	clbss_l
+
+/* we are going to jump into the C part of the init now */
+spin:
+	b	_steppingstone_done
diff --git a/src/cpu/s3c6410/start_qi.c b/src/cpu/s3c6410/start_qi.c
new file mode 100644
index 0000000..ca419ee
--- /dev/null
+++ b/src/cpu/s3c6410/start_qi.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: xiangfu liu <xiangfu at openmoko.org>
+ *         Andy Green <andy at openmoko.com>
+ *
+ * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* NOTE this stuff runs in steppingstone context! */
+
+
+#include <qi.h>
+#include <neo_tla01.h>
+
+extern void bootloader_second_phase(void);
+
+const struct board_api *boards[] = {
+			&board_api_tla01,
+			NULL /* always last */
+};
+
+struct board_api const * this_board;
+extern int is_jtag;
+
+void start_qi(void)
+{
+	int flag = 0;
+	int board = 0;
+
+	/*
+	 * well, we can be running on this CPU two different ways.
+	 *
+	 * 1) We were copied into steppingstone and TEXT_BASE already
+	 *    by JTAG.  We don't have to do anything else.  JTAG script
+	 *    then sets data at address 0x4 to 0xffffffff as a signal we
+	 *    are running by JTAG.
+	 *
+	 * 2) We only got our first 4K into steppingstone, we need to copy
+	 *    the rest of ourselves into TEXT_BASE.
+	 *
+	 * So we do the copy out of NAND only if we see we did not come up
+	 * under control of JTAG.
+	 */
+
+	if (!is_jtag)
+		/*
+		* We got the first 4KBytes of the bootloader pulled into the
+		* steppingstone SRAM for free.  Now we pull the whole bootloader
+		* image into SDRAM.
+		*
+		* This code and the .S files are arranged by the linker script
+		* to expect to run from 0x0.  But the linker script has told
+		* everything else to expect to run from 0x33000000+.  That's
+		* why we are going to be able to copy this code and not have it
+		* crash when we run it from there.
+		*/
+
+		/* We randomly pull 32KBytes of bootloader */
+		/* FIXME  this ain't right for s3c6410 */
+#if 0
+		if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0)
+			goto unhappy;
+#endif
+
+	/* ask all the boards we support in turn if they recognize this
+	 * hardware we are running on, accept the first positive answer
+	 */
+
+	this_board = boards[board];
+	while (!flag && this_board) {
+
+		/* check if it is the right board... */
+		if (this_board->is_this_board()) {
+			flag = 1;
+			continue;
+		}
+
+		this_board = boards[board++];
+	}
+
+	/*
+	 * jump to bootloader_second_phase() running from DRAM copy
+	 */
+	bootloader_second_phase();
+#if 0
+unhappy:
+	while(1)
+		;
+#endif
+}
diff --git a/src/cpu/s3c6410/tla01.c b/src/cpu/s3c6410/tla01.c
new file mode 100644
index 0000000..2269d09
--- /dev/null
+++ b/src/cpu/s3c6410/tla01.c
@@ -0,0 +1,246 @@
+#include <qi.h>
+#include <neo_tla01.h>
+#include <serial-s3c24xx.h>
+#include <ports-s3c24xx.h>
+#include <i2c-bitbang-s3c24xx.h>
+#include <pcf50633.h>
+
+#define GTA03_DEBUG_UART 2
+
+#define PCF50633_I2C_ADS 0x73
+
+
+static const struct board_variant board_variants[] = {
+	[0] = {
+		.name = "TLA01",
+		.machine_revision = 0x010,
+	},
+};
+
+void port_init_tla01(void)
+{
+	unsigned int * MPLLCON = (unsigned int *)0x4c000004;
+	unsigned int * UPLLCON = (unsigned int *)0x4c000008;
+	unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
+
+	//CAUTION:Follow the configuration order for setting the ports.
+	// 1) setting value(GPnDAT)
+	// 2) setting control register  (GPnCON)
+	// 3) configure pull-up resistor(GPnUP)
+
+	/* 32bit data bus configuration   */
+	/*
+	 * === PORT A GROUP
+	 *     Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
+	 *     Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
+	 *     Binary :  1     1      1  , 1   1   1    1   ,  1     1     1     1
+	 *     Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0
+	 *     Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
+	 *     Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      1
+	 */
+	rGPACON = 0x007F8FFF;
+	/*
+	 * ===* PORT B GROUP
+	 *      Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0
+	 *      Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
+	 *      Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT
+	 *      Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01
+	 */
+	rGPBCON = 0x00145554;
+	rGPBDAT |= (1 <<9 );	/* USB_PULLUP */
+	rGPBUP = 0x000007FF;
+	/*
+	 * === PORT C GROUP
+	 *     Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0
+	 *     Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
+	 *     Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10
+	 */
+	rGPCCON = 0xAAA776E9;
+	rGPCUP = 0x0000FFFF;
+	rGPCDAT |= (1 << 9); /* WLAN_nRESET pull high */
+	/*
+	 * === PORT D GROUP
+	 *     Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
+	 *     Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8
+	 *     Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10
+	 */
+	rGPDCON = 0xAAA0AAA5;
+	rGPDUP = 0x0000FFFF;
+	/*
+	 * === PORT E GROUP
+	 *     Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4
+	 *     Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
+	 *     Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,
+	 *     -------------------------------------------------------------------------------------------------------
+	 *     Ports  :  GPE3   GPE2  GPE1    GPE0
+	 *     Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
+	 *     Binary :  10     10  ,  10      10
+	 */
+	rGPECON = 0xAAAAAAAA;
+	rGPEUP = 0x0000FFFF;
+	/*
+	 * === PORT F GROUP
+	 *     Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
+	 *     Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
+	 *     Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0
+	 *     Binary :  01      01 ,  01     01  ,     10       10  , 10     10
+	 */
+	rGPFCON = 0x0000AAAA;
+	rGPFUP = 0x000000FF;
+
+	/*
+	 * === PORT G GROUP
+	 *     Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6
+	 *     Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
+	 *     Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
+	 *     Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11
+	 *     -----------------------------------------------------------------------------------------
+	 *     Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0
+	 *     Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
+	 *     Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
+	 *     Binary :     11         11   ,  10      11  ,  10        10
+	 */
+	rGPGCON = 0x02A9FE5A;
+	rGPGUP = 0x0000FFFF;
+
+	/*
+	 * === PORT H GROUP
+	 *     Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0
+	 *     Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
+	 *     Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10
+	 */
+	/* pulldown on GPH08: UEXTCLK, just floats!
+	 * pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
+	 * pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
+	 */
+	rGPHCON = 0x0019A0AA;
+	rGPHUP = 0x000007FF;
+
+	/* pulldown on GPJ00: input, just floats! */
+	/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
+	rGPJCON = 0x02AAAAAA;
+	rGPJUP = 0x1FFFF;
+
+	/*
+	 * We have to talk to the PMU a little bit
+	 */
+
+	/* We need SD Card rail (HCLDO) at 3.0V */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOOUT,
+									    21);
+
+	/* switch HCLDO on */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOENA, 1);
+
+	/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
+	i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
+									  0x2b);
+
+	/* change CPU clocking to 533MHz 1:4:8 */
+
+	/* clock divide 1:4:8 - do it first */
+	*CLKDIVN = 5;
+	/* configure UPLL */
+	*UPLLCON = ((88 << 12) + (4 << 4) + 2);
+	/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
+	asm __volatile__ (
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+		"nop\n"\
+	);
+	/* configure MPLL */
+	*MPLLCON = ((169 << 12) + (2 << 4) + 1);
+
+
+	serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
+}
+
+/**
+ * returns PCB revision information in b0, d8, d9
+ * GTA03 EVB returns 0x000
+ * GTA03 returns 0x001
+ */
+
+int tla01_get_pcb_revision(void)
+{
+	int n;
+	u32 u;
+
+	/* make B0 inputs */
+	rGPBCON &= ~0x00000003;
+	/* D8 and D9 inputs */
+	rGPDCON &= ~0x000f0000;
+
+	/* delay after changing pulldowns */
+	u = rGPBDAT;
+	u = rGPDDAT;
+
+	/* read the version info */
+	u = rGPBDAT;
+	n = (u >> (0 - 0))& 0x001;
+	u = rGPDDAT;
+	n |= (u >> (8 -1))  & 0x002;
+	n |= (u >> (9 - 2))  & 0x004;
+
+	/*
+	 * when not being interrogated, all of the revision GPIO
+	 * are set to output
+	 */
+	/* make B0 high ouput */
+	rGPBCON |= 0x00000001;
+	/* D8 and D9 high ouputs */
+	rGPDCON |= 0x00050000;
+
+	return n;
+
+}
+
+const struct board_variant const * get_board_variant_tla01(void)
+{
+	return &board_variants[tla01_get_pcb_revision()];
+}
+
+int is_this_board_tla01(void)
+{
+	/* FIXME: find something tla01 specific */
+	return 1;
+}
+
+static void putc_tla01(char c)
+{
+	serial_putc_s3c24xx(GTA03_DEBUG_UART, c);
+}
+
+
+/*
+ * our API for bootloader on this machine
+ */
+const struct board_api board_api_tla01 = {
+	.name = "TLA01",
+	.linux_machine_id = 1866,
+	.linux_mem_start = 0x30000000,
+	.linux_mem_size = (128 * 1024 * 1024),
+	.linux_tag_placement = 0x30000000 + 0x100,
+	.get_board_variant = get_board_variant_tla01,
+	.is_this_board = is_this_board_tla01,
+	.port_init = port_init_tla01,
+	.putc = putc_tla01,
+	.kernel_source = {
+		[0] = {
+			.name = "SD Card",
+			.block_read = NULL, /* FIXME It's s3c6400 sd card*/
+			.offset_blocks512_if_no_partition = 0x80000 / 512,
+			.filesystem = FS_RAW,
+			.commandline = "rootfstype=ext3 " \
+				       "root=/dev/mmcblk0p1 " \
+				       "console=ttySAC2,115200 " \
+				       "loglevel=4 " \
+				       "init=/sbin/init "\
+				       "ro"
+		},
+	},
+};




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