Variable Clock Frequency and Power Saving

[Jonas Bonn]

Hello All!

I put together a cpuidle driver for the S3C2410 and added the
NO_HZ/clockevents work from Andresz to my build.  What follows is a
list of time spent in idle (that's S3C2410 mode IDLE) for my GTA01.
Some of the long idle times are really impressive (almost 0.5
seconds).

All times are microseconds (uS):

479
 1104
 1169
 1534
 1638
 2559
 2893
 3000
 3020
 3147
 3214
 3217
 3217
 3219
 3220
 3221
 3223
 3224
 3230
 3230
 3250
 3271
 4056
 4434
 4441
 4934
 4935
 4935
 4935
 4935
 4935
 4935
 4935
 4936
 4937
 4937
 4939
 4939
 4940
 4941
 4942
 4942
 4962
 4973
 4975
 4984
 4986
 4991
 4991
 4994
 4995
 4996
 4997
 4997
 4997
 4997
 4997
 4997
 4998
 4998
 4998
 5000
 5001
 9848
 19929
 19937
 20260
 29927
 31474
 31859
 31875
 31983
 32383
 33366
 34864
 34920
 34949
 44286
 44297
 44920
 54916
 54921
 54922
 54944
 59956
 63551
 72726
 79855
 84923
 114109
 114382
 119435
 119681
 119910
 124680
 124683
 124709
 124709
 124709
 124927
 152550
 154337
 154665
 159424
 159875
 159932
 234936
 244924
 264931
 279266
 294928
 301520
 324950
 324952
 324952
 474928

Anyway, the point of this post is to see what is happening in
powersaving work.  I had a look at adding an idle-mode that switches
to SLOW mode; this might be feasible, but as so many drivers need to
adjust to the change of clock rate, the time to enter and leave this
idle mode becomes significant (although, for 0.5 seconds, it should be
no problem).

That said, there is no support for clock rate adjustment at all right
now.  Is somebody working on this or does this already work in
somebody's tree somewhere?

I think we need to adjust the 'clk' infrastructure so that:
i)  Children are notified when parent clock rate changes
ii)  Clocks can be reparented (for example, for SLOW mode we switch
from MPLL to XTAL).
iii)  Clocks get a list of callbacks to invoke when their rate changes
so that drivers can make the necessary adjustments.  (e.g. framebuffer
driver needs to know when hclk changes in order to adjust its vclk
divider)

Looking forward to feedback.
/Jonas