serial rxerr

[Andy Green]

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Somebody in the thread at some point said:

|> speed 9600 baud; rows 24; columns 80;

| Ok, this is one problem. The other one is the interrupt latency. The
| threshold is set on 8 chars
| so you have ~800us to get chars from the buffer and it is quite a lot.

What are we talking about there because it's unclear.

At 9600bps each 10-bit character is about 1ms in transit.

The threshold for the FIFO at 8 means that normally, the UART does not
make an RX interrupt to the CPU until it has 8 characters.  In the case
where <8 characters come, it waits for a timeout and then makes the
interrupt anyway.

There are still 56 slots left in the FIFO at that point, so even without
the hardware RTS action, we get ~56ms to service it.

It means we can be blocked for <56ms and we still don't lose any
received characters.

But with hardware RTS control, we should never lose characters at the RX
UART even if we have 1s latency.  As soon as the FIFO fills up, the
hardware tells the GSM chip "no more right now please" no matter what
the CPU is doing.

- -Andy
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