UCLK

[Cesar Eduardo Barros]

Joerg Reisenweber escreveu:
> Am Do  28. August 2008 schrieb Werner Almesberger:
>> Joerg Reisenweber wrote:
>>> Ah, and btw: does anybody have a decent set of bookmarks/pointers/quotes 
> to 
>>> S3C2442 datasheet sections needed to facilitate my duty to validate this 
> ECN? 
>> I think we need a more specific question :-)
>>
>> I.e., it's a connection between pads that are currently unconnected,
>> they both can be disabled if it turns our they cannot be used, and
>> the only thing between them is another pad that is usually disabled,
>> So what additional validation do you need ?
>>
>> If sending UCLK to from CLKOUT1 to UEXTCLK should end up exciting
>> CLKOUT0 and causing some obscure interference, we probably won't
>> find out in any theoretical study anyway.
> 
> I thought about much more basic things like "check if it's the right pin 
> name", "check if logic levels, fan in and fan out match", "check if the whole 
> idea is actually feasible" etc.
> For this I have to scrutinize the corresponding sections in CPU datasheet, so 
> I understand what I'm asking for and what it should work like, instead of 
> just forwarding a "bake recipe" from ML. So some pointer would be welcome ;-)
> Not eager to search the whole manual for "UEXTCLK"

I just replied in another email before seeing this one, but knowing what 
you want I can make a better reply (for the GTA02, the file I have is 
um_s3c2442b_rev12.pdf from the Samsung website):

- Chapter 1 (overview), the big pinout diagram (1-6), both tables 
following it (1-15 has the three pins in question at the bottom, at N22, 
AA13, AE14), the legend for the table (1-21, 1-22), the following table 
doesn't say much but has the signals again (on the UART and clock sections).
- Chapter 7 (clock & power), the diagram (7-3), the PPL values table 
(7-23) which is where 48MHz comes from (note that 96MHz is also an 
option, but I think the USB block needs 48MHz; we should check the 
kernel and u-boot source to see which mode they are using).
- Chapter 9 (I/O ports) has the GPH control registers (9-20) which is 
where the default state for the pins come from, and MISCCR (9-25) which 
choses which clock will be output.
- Chapter 11 (UART) has right on the introduction a mention of UEXTCLK 
(11-1), the baud rate generator description (11-7), and the UBRDIV 
divider registers (11-21).
- Chapter 25 (electrical data) should also say something about the pins 
electrical and timing characteristics, but I couldn't find anything more 
relevant than the generic voltage and current limits.

Note also that in some places it calls it UCLK instead of UEXTCLK (in 
particular in some tables at chapter 1).

-- 
Cesar Eduardo Barros
cesarb at cesarb.net
cesar.barros at gmail.com